opcodes/m32r-opc.h

   1 /* Instruction description for m32r.
   2
   3 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   4
   5 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20
  21 */
  22
  23 #ifndef m32r_OPC_H
  24 #define m32r_OPC_H
  25
  26 #define CGEN_ARCH m32r
  27
  28 /* Given symbol S, return m32r_cgen_<s>.  */
  29 #define CGEN_SYM(s) CGEN_CAT3 (m32r,_cgen_,s)
  30
  31 /* Selected cpu families.  */
  32 #define HAVE_CPU_M32R
  33
  34 #define CGEN_WORD_BITSIZE 32
  35 #define CGEN_DEFAULT_INSN_BITSIZE 32
  36 #define CGEN_BASE_INSN_BITSIZE 32
  37 #define CGEN_MAX_INSN_BITSIZE 32
  38 #define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8)
  39 #define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8)
  40 #define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8)
  41 #define CGEN_INT_INSN
  42
  43 /* +1 because the first entry is reserved (null) */
  44 #define CGEN_NUM_INSNS (127 + 1)
  45 #define CGEN_NUM_OPERANDS (21)
  46
  47 /* Number of non-boolean attributes. */
  48 #define CGEN_MAX_INSN_ATTRS 0
  49 #define CGEN_MAX_OPERAND_ATTRS 0
  50
  51 /* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES.  */
  52
  53 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
  54    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
  55    we can't hash on everything up to the space.  */
  56 #define CGEN_MNEMONIC_OPERANDS
  57
  58 /* Number of architecture variants.  */
  59 #define MAX_MACHS 1
  60
  61 /* Enums.  */
  62
  63 /* Enum declaration for insn format enums.  */
  64 typedef enum insn_op1 {
  65   OP1_0 = 0, OP1_1 = 1, OP1_2 = 2, OP1_3 = 3,
  66   OP1_4 = 4, OP1_5 = 5, OP1_6 = 6, OP1_7 = 7,
  67   OP1_8 = 8, OP1_9 = 9, OP1_10 = 10, OP1_11 = 11,
  68   OP1_12 = 12, OP1_13 = 13, OP1_14 = 14, OP1_15 = 15
  69 } INSN_OP1;
  70
  71 /* Enum declaration for op2 enums.  */
  72 typedef enum insn_op2 {
  73   OP2_0 = 0, OP2_1 = 1, OP2_2 = 2, OP2_3 = 3,
  74   OP2_4 = 4, OP2_5 = 5, OP2_6 = 6, OP2_7 = 7,
  75   OP2_8 = 8, OP2_9 = 9, OP2_10 = 10, OP2_11 = 11,
  76   OP2_12 = 12, OP2_13 = 13, OP2_14 = 14, OP2_15 = 15
  77 } INSN_OP2;
  78
  79 /* Enum declaration for m32r operand types.  */
  80 typedef enum cgen_operand_type {
  81   M32R_OPERAND_PC = 0, M32R_OPERAND_SR = 1, M32R_OPERAND_DR = 2, M32R_OPERAND_SRC1 = 3,
  82   M32R_OPERAND_SRC2 = 4, M32R_OPERAND_SCR = 5, M32R_OPERAND_DCR = 6, M32R_OPERAND_SIMM8 = 7,
  83   M32R_OPERAND_SIMM16 = 8, M32R_OPERAND_UIMM4 = 9, M32R_OPERAND_UIMM5 = 10, M32R_OPERAND_UIMM16 = 11,
  84   M32R_OPERAND_HI16 = 12, M32R_OPERAND_SLO16 = 13, M32R_OPERAND_ULO16 = 14, M32R_OPERAND_UIMM24 = 15,
  85   M32R_OPERAND_DISP8 = 16, M32R_OPERAND_DISP16 = 17, M32R_OPERAND_DISP24 = 18, M32R_OPERAND_CONDBIT = 19,
  86   M32R_OPERAND_ACCUM = 20
  87 } CGEN_OPERAND_TYPE;
  88
  89 /* Non-boolean attributes.  */
  90
  91 /* Enum declaration for machine type selection.  */
  92 typedef enum mach_attr {
  93   MACH_M32R = 0
  94 } MACH_ATTR;
  95
  96 /* Operand and instruction attribute indices.  */
  97
  98 /* Enum declaration for cgen_operand attrs.  */
  99 typedef enum cgen_operand_attr {
 100   CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_FAKE, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_PC,
 101   CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_RELAX, CGEN_OPERAND_RELOC, CGEN_OPERAND_SIGN_OPT,
 102   CGEN_OPERAND_UNSIGNED
 103 } CGEN_OPERAND_ATTR;
 104
 105 /* Enum declaration for cgen_insn attrs.  */
 106 typedef enum cgen_insn_attr {
 107   CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_FILL_SLOT, CGEN_INSN_RELAX,
 108   CGEN_INSN_RELAX_BC, CGEN_INSN_RELAX_BL, CGEN_INSN_RELAX_BNC, CGEN_INSN_RELAX_BRA,
 109   CGEN_INSN_RELAXABLE, CGEN_INSN_UNCOND_CTI
 110 } CGEN_INSN_ATTR;
 111
 112 /* Insn types are used by the simulator.  */
 113 /* Enum declaration for m32r instruction types.  */
 114 typedef enum cgen_insn_type {
 115   M32R_INSN_ILLEGAL, M32R_INSN_ADD, M32R_INSN_ADD3, M32R_INSN_AND,
 116   M32R_INSN_AND3, M32R_INSN_OR, M32R_INSN_OR3, M32R_INSN_XOR,
 117   M32R_INSN_XOR3, M32R_INSN_ADDI, M32R_INSN_ADDV, M32R_INSN_ADDV3,
 118   M32R_INSN_ADDX, M32R_INSN_BC8, M32R_INSN_BC8_S, M32R_INSN_BC24,
 119   M32R_INSN_BC24_L, M32R_INSN_BEQ, M32R_INSN_BEQZ, M32R_INSN_BGEZ,
 120   M32R_INSN_BGTZ, M32R_INSN_BLEZ, M32R_INSN_BLTZ, M32R_INSN_BNEZ,
 121   M32R_INSN_BL8, M32R_INSN_BL8_S, M32R_INSN_BL24, M32R_INSN_BL24_L,
 122   M32R_INSN_BNC8, M32R_INSN_BNC8_S, M32R_INSN_BNC24, M32R_INSN_BNC24_L,
 123   M32R_INSN_BNE, M32R_INSN_BRA8, M32R_INSN_BRA8_S, M32R_INSN_BRA24,
 124   M32R_INSN_BRA24_L, M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPU,
 125   M32R_INSN_CMPUI, M32R_INSN_DIV, M32R_INSN_DIVU, M32R_INSN_REM,
 126   M32R_INSN_REMU, M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD,
 127   M32R_INSN_LD_2, M32R_INSN_LD_D, M32R_INSN_LD_D2, M32R_INSN_LDB,
 128   M32R_INSN_LDB_2, M32R_INSN_LDB_D, M32R_INSN_LDB_D2, M32R_INSN_LDH,
 129   M32R_INSN_LDH_2, M32R_INSN_LDH_D, M32R_INSN_LDH_D2, M32R_INSN_LDUB,
 130   M32R_INSN_LDUB_2, M32R_INSN_LDUB_D, M32R_INSN_LDUB_D2, M32R_INSN_LDUH,
 131   M32R_INSN_LDUH_2, M32R_INSN_LDUH_D, M32R_INSN_LDUH_D2, M32R_INSN_LD_PLUS,
 132   M32R_INSN_LD24, M32R_INSN_LDI8, M32R_INSN_LDI8A, M32R_INSN_LDI16,
 133   M32R_INSN_LDI16A, M32R_INSN_LOCK, M32R_INSN_MACHI, M32R_INSN_MACLO,
 134   M32R_INSN_MACWHI, M32R_INSN_MACWLO, M32R_INSN_MUL, M32R_INSN_MULHI,
 135   M32R_INSN_MULLO, M32R_INSN_MULWHI, M32R_INSN_MULWLO, M32R_INSN_MV,
 136   M32R_INSN_MVFACHI, M32R_INSN_MVFACLO, M32R_INSN_MVFACMI, M32R_INSN_MVFC,
 137   M32R_INSN_MVTACHI, M32R_INSN_MVTACLO, M32R_INSN_MVTC, M32R_INSN_NEG,
 138   M32R_INSN_NOP, M32R_INSN_NOT, M32R_INSN_RAC, M32R_INSN_RACH,
 139   M32R_INSN_RTE, M32R_INSN_SETH, M32R_INSN_SLL, M32R_INSN_SLL3,
 140   M32R_INSN_SLLI, M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRAI,
 141   M32R_INSN_SRL, M32R_INSN_SRL3, M32R_INSN_SRLI, M32R_INSN_ST,
 142   M32R_INSN_ST_2, M32R_INSN_ST_D, M32R_INSN_ST_D2, M32R_INSN_STB,
 143   M32R_INSN_STB_2, M32R_INSN_STB_D, M32R_INSN_STB_D2, M32R_INSN_STH,
 144   M32R_INSN_STH_2, M32R_INSN_STH_D, M32R_INSN_STH_D2, M32R_INSN_ST_PLUS,
 145   M32R_INSN_ST_MINUS, M32R_INSN_SUB, M32R_INSN_SUBV, M32R_INSN_SUBX,
 146   M32R_INSN_TRAP, M32R_INSN_UNLOCK, M32R_INSN_PUSH, M32R_INSN_POP,
 147   M32R_INSN_MAX
 148 } CGEN_INSN_TYPE;
 149
 150 /* Index of `illegal' insn place holder.  */
 151 #define CGEN_INSN_ILLEGAL M32R_INSN_ILLEGAL
 152 /* Total number of insns in table.  */
 153 #define CGEN_MAX_INSNS ((int) M32R_INSN_MAX)
 154
 155 /* cgen.h uses things we just defined.  */
 156 #include "opcode/cgen.h"
 157
 158 /* This struct records data prior to insertion or after extraction.  */
 159 typedef struct cgen_fields
 160 {
 161   long f_nil;
 162   long f_op1;
 163   long f_op2;
 164   long f_cond;
 165   long f_r1;
 166   long f_r2;
 167   long f_simm8;
 168   long f_simm16;
 169   long f_shift_op2;
 170   long f_uimm4;
 171   long f_uimm5;
 172   long f_uimm16;
 173   long f_uimm24;
 174   long f_hi16;
 175   long f_disp8;
 176   long f_disp16;
 177   long f_disp24;
 178   int length;
 179 } CGEN_FIELDS;
 180
 181 /* Attributes.  */
 182 extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[];
 183 extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[];
 184
 185 extern CGEN_KEYWORD m32r_cgen_opval_mach;
 186 extern CGEN_KEYWORD m32r_cgen_opval_h_gr;
 187 extern CGEN_KEYWORD m32r_cgen_opval_h_cr;
 188
 189 #define CGEN_INIT_PARSE() \
 190 {\
 191 }
 192 #define CGEN_INIT_INSERT() \
 193 {\
 194 }
 195 #define CGEN_INIT_EXTRACT() \
 196 {\
 197 }
 198 #define CGEN_INIT_PRINT() \
 199 {\
 200 }
 201
 202 /* -- opc.h */
 203
 204 #undef CGEN_DIS_HASH_SIZE
 205 #define CGEN_DIS_HASH_SIZE 256
 206 #undef CGEN_DIS_HASH
 207 #define X(b) (((unsigned char *) (b))[0] & 0xf0)
 208 #define CGEN_DIS_HASH(buffer, insn) \
 209 (X (buffer) | \
 210  (X (buffer) == 0x40 || X (buffer) == 0xe0 || X (buffer) == 0x60 || X (buffer) == 0x50 ? 0 \
 211   : X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \
 212   : ((((unsigned char *) (buffer))[1] & 0xf0) >> 4)))
 213
 214 /* -- */
 215
 216
 217 #endif /* m32r_OPC_H */