opcodes/m32r-opc.h

   1 /* Instruction opcode header for m32r.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996-2014 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9    This file is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    It is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License along
  20    with this program; if not, write to the Free Software Foundation, Inc.,
  21    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #ifndef M32R_OPC_H
  26 #define M32R_OPC_H
  27
  28 /* -- opc.h */
  29
  30 #undef  CGEN_DIS_HASH_SIZE
  31 #define CGEN_DIS_HASH_SIZE 256
  32 #undef  CGEN_DIS_HASH
  33 #if 0
  34 #define X(b) (((unsigned char *) (b))[0] & 0xf0)
  35 #define CGEN_DIS_HASH(buffer, value) \
  36 (X (buffer) | \
  37  (X (buffer) == 0x40 || X (buffer) == 0xe0 || X (buffer) == 0x60 || X (buffer) == 0x50 ? 0 \
  38   : X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \
  39   : X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \
  40   : ((((unsigned char *) (buffer))[1] & 0xf0) >> 4)))
  41 #else
  42 #define CGEN_DIS_HASH(buffer, value) m32r_cgen_dis_hash (buffer, value)
  43 extern unsigned int m32r_cgen_dis_hash (const char *, CGEN_INSN_INT);
  44 #endif
  45
  46 /* -- */
  47 /* Enum declaration for m32r instruction types.  */
  48 typedef enum cgen_insn_type {
  49   M32R_INSN_INVALID, M32R_INSN_ADD, M32R_INSN_ADD3, M32R_INSN_AND
  50  , M32R_INSN_AND3, M32R_INSN_OR, M32R_INSN_OR3, M32R_INSN_XOR
  51  , M32R_INSN_XOR3, M32R_INSN_ADDI, M32R_INSN_ADDV, M32R_INSN_ADDV3
  52  , M32R_INSN_ADDX, M32R_INSN_BC8, M32R_INSN_BC24, M32R_INSN_BEQ
  53  , M32R_INSN_BEQZ, M32R_INSN_BGEZ, M32R_INSN_BGTZ, M32R_INSN_BLEZ
  54  , M32R_INSN_BLTZ, M32R_INSN_BNEZ, M32R_INSN_BL8, M32R_INSN_BL24
  55  , M32R_INSN_BCL8, M32R_INSN_BCL24, M32R_INSN_BNC8, M32R_INSN_BNC24
  56  , M32R_INSN_BNE, M32R_INSN_BRA8, M32R_INSN_BRA24, M32R_INSN_BNCL8
  57  , M32R_INSN_BNCL24, M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPU
  58  , M32R_INSN_CMPUI, M32R_INSN_CMPEQ, M32R_INSN_CMPZ, M32R_INSN_DIV
  59  , M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU, M32R_INSN_REMH
  60  , M32R_INSN_REMUH, M32R_INSN_REMB, M32R_INSN_REMUB, M32R_INSN_DIVUH
  61  , M32R_INSN_DIVB, M32R_INSN_DIVUB, M32R_INSN_DIVH, M32R_INSN_JC
  62  , M32R_INSN_JNC, M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD
  63  , M32R_INSN_LD_D, M32R_INSN_LDB, M32R_INSN_LDB_D, M32R_INSN_LDH
  64  , M32R_INSN_LDH_D, M32R_INSN_LDUB, M32R_INSN_LDUB_D, M32R_INSN_LDUH
  65  , M32R_INSN_LDUH_D, M32R_INSN_LD_PLUS, M32R_INSN_LD24, M32R_INSN_LDI8
  66  , M32R_INSN_LDI16, M32R_INSN_LOCK, M32R_INSN_MACHI, M32R_INSN_MACHI_A
  67  , M32R_INSN_MACLO, M32R_INSN_MACLO_A, M32R_INSN_MACWHI, M32R_INSN_MACWHI_A
  68  , M32R_INSN_MACWLO, M32R_INSN_MACWLO_A, M32R_INSN_MUL, M32R_INSN_MULHI
  69  , M32R_INSN_MULHI_A, M32R_INSN_MULLO, M32R_INSN_MULLO_A, M32R_INSN_MULWHI
  70  , M32R_INSN_MULWHI_A, M32R_INSN_MULWLO, M32R_INSN_MULWLO_A, M32R_INSN_MV
  71  , M32R_INSN_MVFACHI, M32R_INSN_MVFACHI_A, M32R_INSN_MVFACLO, M32R_INSN_MVFACLO_A
  72  , M32R_INSN_MVFACMI, M32R_INSN_MVFACMI_A, M32R_INSN_MVFC, M32R_INSN_MVTACHI
  73  , M32R_INSN_MVTACHI_A, M32R_INSN_MVTACLO, M32R_INSN_MVTACLO_A, M32R_INSN_MVTC
  74  , M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT, M32R_INSN_RAC
  75  , M32R_INSN_RAC_DSI, M32R_INSN_RACH, M32R_INSN_RACH_DSI, M32R_INSN_RTE
  76  , M32R_INSN_SETH, M32R_INSN_SLL, M32R_INSN_SLL3, M32R_INSN_SLLI
  77  , M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRAI, M32R_INSN_SRL
  78  , M32R_INSN_SRL3, M32R_INSN_SRLI, M32R_INSN_ST, M32R_INSN_ST_D
  79  , M32R_INSN_STB, M32R_INSN_STB_D, M32R_INSN_STH, M32R_INSN_STH_D
  80  , M32R_INSN_ST_PLUS, M32R_INSN_STH_PLUS, M32R_INSN_STB_PLUS, M32R_INSN_ST_MINUS
  81  , M32R_INSN_SUB, M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP
  82  , M32R_INSN_UNLOCK, M32R_INSN_SATB, M32R_INSN_SATH, M32R_INSN_SAT
  83  , M32R_INSN_PCMPBZ, M32R_INSN_SADD, M32R_INSN_MACWU1, M32R_INSN_MSBLO
  84  , M32R_INSN_MULWU1, M32R_INSN_MACLH1, M32R_INSN_SC, M32R_INSN_SNC
  85  , M32R_INSN_CLRPSW, M32R_INSN_SETPSW, M32R_INSN_BSET, M32R_INSN_BCLR
  86  , M32R_INSN_BTST
  87 } CGEN_INSN_TYPE;
  88
  89 /* Index of `invalid' insn place holder.  */
  90 #define CGEN_INSN_INVALID M32R_INSN_INVALID
  91
  92 /* Total number of insns in table.  */
  93 #define MAX_INSNS ((int) M32R_INSN_BTST + 1)
  94
  95 /* This struct records data prior to insertion or after extraction.  */
  96 struct cgen_fields
  97 {
  98   int length;
  99   long f_nil;
 100   long f_anyof;
 101   long f_op1;
 102   long f_op2;
 103   long f_cond;
 104   long f_r1;
 105   long f_r2;
 106   long f_simm8;
 107   long f_simm16;
 108   long f_shift_op2;
 109   long f_uimm3;
 110   long f_uimm4;
 111   long f_uimm5;
 112   long f_uimm8;
 113   long f_uimm16;
 114   long f_uimm24;
 115   long f_hi16;
 116   long f_disp8;
 117   long f_disp16;
 118   long f_disp24;
 119   long f_op23;
 120   long f_op3;
 121   long f_acc;
 122   long f_accs;
 123   long f_accd;
 124   long f_bits67;
 125   long f_bit4;
 126   long f_bit14;
 127   long f_imm1;
 128 };
 129
 130 #define CGEN_INIT_PARSE(od) \
 131 {\
 132 }
 133 #define CGEN_INIT_INSERT(od) \
 134 {\
 135 }
 136 #define CGEN_INIT_EXTRACT(od) \
 137 {\
 138 }
 139 #define CGEN_INIT_PRINT(od) \
 140 {\
 141 }
 142
 143
 144 #endif /* M32R_OPC_H */