opcodes/m32r-opc.h

   1 /* Instruction description for m32r.
   2
   3 This file is machine generated with CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef m32r_OPC_H
  26 #define m32r_OPC_H
  27
  28 #define CGEN_ARCH m32r
  29
  30 /* Given symbol S, return m32r_cgen_<s>.  */
  31 #define CGEN_SYM(s) CGEN_CAT3 (m32r,_cgen_,s)
  32
  33 /* Selected cpu families.  */
  34 #define HAVE_CPU_M32R
  35 /* start-sanitize-m32rx */
  36 #define HAVE_CPU_M32RX
  37 /* end-sanitize-m32rx */
  38
  39 #define CGEN_WORD_BITSIZE 32
  40 #define CGEN_DEFAULT_INSN_BITSIZE 32
  41 #define CGEN_BASE_INSN_BITSIZE 32
  42 #define CGEN_MAX_INSN_BITSIZE 32
  43 #define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8)
  44 #define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8)
  45 #define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8)
  46 #define CGEN_INT_INSN
  47
  48 /* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES.  */
  49
  50 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
  51    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
  52    we can't hash on everything up to the space.  */
  53 #define CGEN_MNEMONIC_OPERANDS
  54
  55 /* Enums.  */
  56
  57 /* Enum declaration for insn format enums.  */
  58 typedef enum insn_op1 {
  59   OP1_0, OP1_1, OP1_2, OP1_3
  60  , OP1_4, OP1_5, OP1_6, OP1_7
  61  , OP1_8, OP1_9, OP1_10, OP1_11
  62  , OP1_12, OP1_13, OP1_14, OP1_15
  63 } INSN_OP1;
  64
  65 /* Enum declaration for op2 enums.  */
  66 typedef enum insn_op2 {
  67   OP2_0, OP2_1, OP2_2, OP2_3
  68  , OP2_4, OP2_5, OP2_6, OP2_7
  69  , OP2_8, OP2_9, OP2_10, OP2_11
  70  , OP2_12, OP2_13, OP2_14, OP2_15
  71 } INSN_OP2;
  72
  73 /* Enum declaration for m32r operand types.  */
  74 typedef enum cgen_operand_type {
  75   M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1
  76  , M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8
  77  , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5, M32R_OPERAND_UIMM16
  78 /* start-sanitize-m32rx */
  79  , M32R_OPERAND_IMM1
  80 /* end-sanitize-m32rx */
  81 /* start-sanitize-m32rx */
  82  , M32R_OPERAND_ACCD
  83 /* end-sanitize-m32rx */
  84 /* start-sanitize-m32rx */
  85  , M32R_OPERAND_ACCS
  86 /* end-sanitize-m32rx */
  87 /* start-sanitize-m32rx */
  88  , M32R_OPERAND_ACC
  89 /* end-sanitize-m32rx */
  90  , M32R_OPERAND_HI16, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16, M32R_OPERAND_UIMM24
  91  , M32R_OPERAND_DISP8, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24, M32R_OPERAND_CONDBIT
  92  , M32R_OPERAND_ACCUM
  93 /* start-sanitize-m32rx */
  94  , M32R_OPERAND_ABORT_PARALLEL_EXECUTION
  95 /* end-sanitize-m32rx */
  96  , M32R_OPERAND_MAX
  97 } CGEN_OPERAND_TYPE;
  98
  99 /* Non-boolean attributes.  */
 100
 101 /* Enum declaration for machine type selection.  */
 102 typedef enum mach_attr {
 103   MACH_M32R
 104 /* start-sanitize-m32rx */
 105  , MACH_M32RX
 106 /* end-sanitize-m32rx */
 107  , MACH_MAX
 108 } MACH_ATTR;
 109
 110 /* Enum declaration for instructions which modify the link register as a side effect.  */
 111 typedef enum write_lr_attr {
 112   WRITE_LR_NO, WRITE_LR_YES
 113 } WRITE_LR_ATTR;
 114
 115 /* Enum declaration for instructions which modify their source register as a side effect.  */
 116 typedef enum write_src_attr {
 117   WRITE_SRC_NO, WRITE_SRC_YES
 118 } WRITE_SRC_ATTR;
 119
 120 /* start-sanitize-m32rx */
 121 /* Enum declaration for parallel execution pipeline selection.  */
 122 typedef enum pipe_attr {
 123   PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS
 124 } PIPE_ATTR;
 125
 126 /* end-sanitize-m32rx */
 127 /* Number of architecture variants.  */
 128 #define MAX_MACHS ((int) MACH_MAX)
 129
 130 /* Number of operands types.  */
 131 #define MAX_OPERANDS ((int) M32R_OPERAND_MAX)
 132
 133 /* Maximum number of operands referenced by any insn.  */
 134 #define MAX_OPERAND_INSTANCES 8
 135
 136 /* Operand and instruction attribute indices.  */
 137
 138 /* Enum declaration for cgen_operand attrs.  */
 139 typedef enum cgen_operand_attr {
 140   CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_FAKE, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_PC
 141  , CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_RELAX, CGEN_OPERAND_RELOC, CGEN_OPERAND_SIGN_OPT
 142  , CGEN_OPERAND_UNSIGNED
 143 } CGEN_OPERAND_ATTR;
 144
 145 /* Number of non-boolean elements in cgen_operand.  */
 146 #define CGEN_OPERAND_MAX_ATTRS ((int) CGEN_OPERAND_ABS_ADDR)
 147
 148 /* Enum declaration for cgen_insn attrs.  */
 149 typedef enum cgen_insn_attr {
 150   CGEN_INSN_MACH
 151 /* start-sanitize-m32rx */
 152  , CGEN_INSN_PIPE
 153 /* end-sanitize-m32rx */
 154  , CGEN_INSN_WRITE_LR, CGEN_INSN_WRITE_SRC, CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI
 155  , CGEN_INSN_FILL_SLOT, CGEN_INSN_PARALLEL, CGEN_INSN_RELAX, CGEN_INSN_RELAXABLE
 156  , CGEN_INSN_UNCOND_CTI
 157 } CGEN_INSN_ATTR;
 158
 159 /* Number of non-boolean elements in cgen_insn.  */
 160 #define CGEN_INSN_MAX_ATTRS ((int) CGEN_INSN_ALIAS)
 161
 162 /* Insn types are used by the simulator.  */
 163 /* Enum declaration for m32r instruction types.  */
 164 typedef enum cgen_insn_type {
 165   M32R_INSN_ILLEGAL, M32R_INSN_ADD, M32R_INSN_ADD3, M32R_INSN_ADD3_A
 166  , M32R_INSN_AND, M32R_INSN_AND3, M32R_INSN_AND3_A, M32R_INSN_OR
 167  , M32R_INSN_OR3, M32R_INSN_OR3_A, M32R_INSN_XOR, M32R_INSN_XOR3
 168  , M32R_INSN_XOR3_A, M32R_INSN_ADDI, M32R_INSN_ADDI_A, M32R_INSN_ADDV
 169  , M32R_INSN_ADDV3, M32R_INSN_ADDV3_A, M32R_INSN_ADDX, M32R_INSN_BC8
 170  , M32R_INSN_BC8_S, M32R_INSN_BC24, M32R_INSN_BC24_L, M32R_INSN_BEQ
 171  , M32R_INSN_BEQZ, M32R_INSN_BGEZ, M32R_INSN_BGTZ, M32R_INSN_BLEZ
 172  , M32R_INSN_BLTZ, M32R_INSN_BNEZ, M32R_INSN_BL8, M32R_INSN_BL8_S
 173  , M32R_INSN_BL24, M32R_INSN_BL24_L
 174 /* start-sanitize-m32rx */
 175  , M32R_INSN_BCL8
 176 /* end-sanitize-m32rx */
 177 /* start-sanitize-m32rx */
 178  , M32R_INSN_BCL8_S
 179 /* end-sanitize-m32rx */
 180 /* start-sanitize-m32rx */
 181  , M32R_INSN_BCL24
 182 /* end-sanitize-m32rx */
 183 /* start-sanitize-m32rx */
 184  , M32R_INSN_BCL24_L
 185 /* end-sanitize-m32rx */
 186  , M32R_INSN_BNC8, M32R_INSN_BNC8_S, M32R_INSN_BNC24, M32R_INSN_BNC24_L
 187  , M32R_INSN_BNE, M32R_INSN_BRA8, M32R_INSN_BRA8_S, M32R_INSN_BRA24
 188  , M32R_INSN_BRA24_L
 189 /* start-sanitize-m32rx */
 190  , M32R_INSN_BNCL8
 191 /* end-sanitize-m32rx */
 192 /* start-sanitize-m32rx */
 193  , M32R_INSN_BNCL8_S
 194 /* end-sanitize-m32rx */
 195 /* start-sanitize-m32rx */
 196  , M32R_INSN_BNCL24
 197 /* end-sanitize-m32rx */
 198 /* start-sanitize-m32rx */
 199  , M32R_INSN_BNCL24_L
 200 /* end-sanitize-m32rx */
 201  , M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPI_A, M32R_INSN_CMPU
 202  , M32R_INSN_CMPUI, M32R_INSN_CMPUI_A
 203 /* start-sanitize-m32rx */
 204  , M32R_INSN_CMPEQ
 205 /* end-sanitize-m32rx */
 206 /* start-sanitize-m32rx */
 207  , M32R_INSN_CMPZ
 208 /* end-sanitize-m32rx */
 209  , M32R_INSN_DIV, M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU
 210 /* start-sanitize-m32rx */
 211  , M32R_INSN_DIVH
 212 /* end-sanitize-m32rx */
 213 /* start-sanitize-m32rx */
 214  , M32R_INSN_JC
 215 /* end-sanitize-m32rx */
 216 /* start-sanitize-m32rx */
 217  , M32R_INSN_JNC
 218 /* end-sanitize-m32rx */
 219  , M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD, M32R_INSN_LD_2
 220  , M32R_INSN_LD_D, M32R_INSN_LD_D2, M32R_INSN_LDB, M32R_INSN_LDB_2
 221  , M32R_INSN_LDB_D, M32R_INSN_LDB_D2, M32R_INSN_LDH, M32R_INSN_LDH_2
 222  , M32R_INSN_LDH_D, M32R_INSN_LDH_D2, M32R_INSN_LDUB, M32R_INSN_LDUB_2
 223  , M32R_INSN_LDUB_D, M32R_INSN_LDUB_D2, M32R_INSN_LDUH, M32R_INSN_LDUH_2
 224  , M32R_INSN_LDUH_D, M32R_INSN_LDUH_D2, M32R_INSN_LD_PLUS, M32R_INSN_LD24
 225  , M32R_INSN_LD24_A, M32R_INSN_LDI8, M32R_INSN_LDI8_A, M32R_INSN_LDI8A
 226  , M32R_INSN_LDI8A_A, M32R_INSN_LDI16, M32R_INSN_LDI16A, M32R_INSN_LOCK
 227  , M32R_INSN_MACHI
 228 /* start-sanitize-m32rx */
 229  , M32R_INSN_MACHI_A
 230 /* end-sanitize-m32rx */
 231  , M32R_INSN_MACLO
 232 /* start-sanitize-m32rx */
 233  , M32R_INSN_MACLO_A
 234 /* end-sanitize-m32rx */
 235  , M32R_INSN_MACWHI, M32R_INSN_MACWLO, M32R_INSN_MUL, M32R_INSN_MULHI
 236 /* start-sanitize-m32rx */
 237  , M32R_INSN_MULHI_A
 238 /* end-sanitize-m32rx */
 239  , M32R_INSN_MULLO
 240 /* start-sanitize-m32rx */
 241  , M32R_INSN_MULLO_A
 242 /* end-sanitize-m32rx */
 243  , M32R_INSN_MULWHI, M32R_INSN_MULWLO, M32R_INSN_MV, M32R_INSN_MVFACHI
 244 /* start-sanitize-m32rx */
 245  , M32R_INSN_MVFACHI_A
 246 /* end-sanitize-m32rx */
 247  , M32R_INSN_MVFACLO
 248 /* start-sanitize-m32rx */
 249  , M32R_INSN_MVFACLO_A
 250 /* end-sanitize-m32rx */
 251  , M32R_INSN_MVFACMI
 252 /* start-sanitize-m32rx */
 253  , M32R_INSN_MVFACMI_A
 254 /* end-sanitize-m32rx */
 255  , M32R_INSN_MVFC, M32R_INSN_MVTACHI
 256 /* start-sanitize-m32rx */
 257  , M32R_INSN_MVTACHI_A
 258 /* end-sanitize-m32rx */
 259  , M32R_INSN_MVTACLO
 260 /* start-sanitize-m32rx */
 261  , M32R_INSN_MVTACLO_A
 262 /* end-sanitize-m32rx */
 263  , M32R_INSN_MVTC, M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT
 264  , M32R_INSN_RAC
 265 /* start-sanitize-m32rx */
 266  , M32R_INSN_RAC_D
 267 /* end-sanitize-m32rx */
 268 /* start-sanitize-m32rx */
 269  , M32R_INSN_RAC_DS
 270 /* end-sanitize-m32rx */
 271 /* start-sanitize-m32rx */
 272  , M32R_INSN_RAC_DSI
 273 /* end-sanitize-m32rx */
 274  , M32R_INSN_RACH
 275 /* start-sanitize-m32rx */
 276  , M32R_INSN_RACH_D
 277 /* end-sanitize-m32rx */
 278 /* start-sanitize-m32rx */
 279  , M32R_INSN_RACH_DS
 280 /* end-sanitize-m32rx */
 281 /* start-sanitize-m32rx */
 282  , M32R_INSN_RACH_DSI
 283 /* end-sanitize-m32rx */
 284  , M32R_INSN_RTE, M32R_INSN_SETH, M32R_INSN_SETH_A, M32R_INSN_SLL
 285  , M32R_INSN_SLL3, M32R_INSN_SLL3_A, M32R_INSN_SLLI, M32R_INSN_SLLI_A
 286  , M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRA3_A, M32R_INSN_SRAI
 287  , M32R_INSN_SRAI_A, M32R_INSN_SRL, M32R_INSN_SRL3, M32R_INSN_SRL3_A
 288  , M32R_INSN_SRLI, M32R_INSN_SRLI_A, M32R_INSN_ST, M32R_INSN_ST_2
 289  , M32R_INSN_ST_D, M32R_INSN_ST_D2, M32R_INSN_STB, M32R_INSN_STB_2
 290  , M32R_INSN_STB_D, M32R_INSN_STB_D2, M32R_INSN_STH, M32R_INSN_STH_2
 291  , M32R_INSN_STH_D, M32R_INSN_STH_D2, M32R_INSN_ST_PLUS, M32R_INSN_ST_MINUS
 292  , M32R_INSN_SUB, M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP
 293  , M32R_INSN_TRAP_A, M32R_INSN_UNLOCK, M32R_INSN_PUSH, M32R_INSN_POP
 294 /* start-sanitize-m32rx */
 295  , M32R_INSN_SATB
 296 /* end-sanitize-m32rx */
 297 /* start-sanitize-m32rx */
 298  , M32R_INSN_SATH
 299 /* end-sanitize-m32rx */
 300 /* start-sanitize-m32rx */
 301  , M32R_INSN_SAT
 302 /* end-sanitize-m32rx */
 303 /* start-sanitize-m32rx */
 304  , M32R_INSN_PCMPBZ
 305 /* end-sanitize-m32rx */
 306 /* start-sanitize-m32rx */
 307  , M32R_INSN_SADD
 308 /* end-sanitize-m32rx */
 309 /* start-sanitize-m32rx */
 310  , M32R_INSN_MACWU1
 311 /* end-sanitize-m32rx */
 312 /* start-sanitize-m32rx */
 313  , M32R_INSN_MSBLO
 314 /* end-sanitize-m32rx */
 315 /* start-sanitize-m32rx */
 316  , M32R_INSN_MULWU1
 317 /* end-sanitize-m32rx */
 318 /* start-sanitize-m32rx */
 319  , M32R_INSN_MACLH1
 320 /* end-sanitize-m32rx */
 321 /* start-sanitize-m32rx */
 322  , M32R_INSN_SC
 323 /* end-sanitize-m32rx */
 324 /* start-sanitize-m32rx */
 325  , M32R_INSN_SNC
 326 /* end-sanitize-m32rx */
 327  , M32R_INSN_MAX
 328 } CGEN_INSN_TYPE;
 329
 330 /* Index of `illegal' insn place holder.  */
 331 #define CGEN_INSN_ILLEGAL M32R_INSN_ILLEGAL
 332 /* Total number of insns in table.  */
 333 #define MAX_INSNS ((int) M32R_INSN_MAX)
 334
 335 /* cgen.h uses things we just defined.  */
 336 #include "opcode/cgen.h"
 337
 338 /* This struct records data prior to insertion or after extraction.  */
 339 struct cgen_fields
 340 {
 341   long f_nil;
 342   long f_op1;
 343   long f_op2;
 344   long f_cond;
 345   long f_r1;
 346   long f_r2;
 347   long f_simm8;
 348   long f_simm16;
 349   long f_shift_op2;
 350   long f_uimm4;
 351   long f_uimm5;
 352   long f_uimm16;
 353   long f_uimm24;
 354   long f_hi16;
 355   long f_disp8;
 356   long f_disp16;
 357   long f_disp24;
 358 /* start-sanitize-m32rx */
 359   long f_op23;
 360 /* end-sanitize-m32rx */
 361 /* start-sanitize-m32rx */
 362   long f_op3;
 363 /* end-sanitize-m32rx */
 364 /* start-sanitize-m32rx */
 365   long f_acc;
 366 /* end-sanitize-m32rx */
 367 /* start-sanitize-m32rx */
 368   long f_accs;
 369 /* end-sanitize-m32rx */
 370 /* start-sanitize-m32rx */
 371   long f_accd;
 372 /* end-sanitize-m32rx */
 373 /* start-sanitize-m32rx */
 374   long f_bits67;
 375 /* end-sanitize-m32rx */
 376 /* start-sanitize-m32rx */
 377   long f_bit14;
 378 /* end-sanitize-m32rx */
 379 /* start-sanitize-m32rx */
 380   long f_imm1;
 381 /* end-sanitize-m32rx */
 382   int length;
 383 };
 384
 385 /* Attributes.  */
 386 extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[];
 387 extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[];
 388
 389 /* Enum declaration for m32r hardware types.  */
 390 typedef enum hw_type {
 391   HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT
 392  , HW_H_ADDR, HW_H_IADDR, HW_H_HI16, HW_H_SLO16
 393  , HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM
 394 /* start-sanitize-m32rx */
 395  , HW_H_ACCUMS
 396 /* end-sanitize-m32rx */
 397 /* start-sanitize-m32rx */
 398  , HW_H_ABORT
 399 /* end-sanitize-m32rx */
 400  , HW_H_COND, HW_H_SM, HW_H_BSM, HW_H_IE
 401  , HW_H_BIE, HW_H_BCOND, HW_H_BPC, HW_MAX
 402 } HW_TYPE;
 403
 404 #define MAX_HW ((int) HW_MAX)
 405
 406 /* Hardware decls.  */
 407
 408 extern CGEN_KEYWORD m32r_cgen_opval_h_gr;
 409 extern CGEN_KEYWORD m32r_cgen_opval_h_cr;
 410 /* start-sanitize-m32rx */
 411 extern CGEN_KEYWORD m32r_cgen_opval_h_accums;
 412 /* end-sanitize-m32rx */
 413
 414 #define CGEN_INIT_PARSE() \
 415 {\
 416 }
 417 #define CGEN_INIT_INSERT() \
 418 {\
 419 }
 420 #define CGEN_INIT_EXTRACT() \
 421 {\
 422 }
 423 #define CGEN_INIT_PRINT() \
 424 {\
 425 }
 426
 427 /* -- opc.h */
 428
 429 #undef CGEN_DIS_HASH_SIZE
 430 #define CGEN_DIS_HASH_SIZE 256
 431 #undef CGEN_DIS_HASH
 432 #define X(b) (((unsigned char *) (b))[0] & 0xf0)
 433 #define CGEN_DIS_HASH(buffer, insn) \
 434 (X (buffer) | \
 435  (X (buffer) == 0x40 || X (buffer) == 0xe0 || X (buffer) == 0x60 || X (buffer) == 0x50 ? 0 \
 436   : X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \
 437   : X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \
 438   : ((((unsigned char *) (buffer))[1] & 0xf0) >> 4)))
 439
 440 /* -- */
 441
 442
 443 #endif /* m32r_OPC_H */