opcodes/mep-desc.c

   1 /* CPU data for mep.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996-2007 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9    This file is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    It is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License along
  20    with this program; if not, write to the Free Software Foundation, Inc.,
  21    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include "sysdep.h"
  26 #include <stdio.h>
  27 #include <stdarg.h>
  28 #include "ansidecl.h"
  29 #include "bfd.h"
  30 #include "symcat.h"
  31 #include "mep-desc.h"
  32 #include "mep-opc.h"
  33 #include "opintl.h"
  34 #include "libiberty.h"
  35 #include "xregex.h"
  36
  37 /* Attributes.  */
  38
  39 static const CGEN_ATTR_ENTRY bool_attr[] =
  40 {
  41   { "#f", 0 },
  42   { "#t", 1 },
  43   { 0, 0 }
  44 };
  45
  46 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
  47 {
  48   { "base", MACH_BASE },
  49   { "mep", MACH_MEP },
  50   { "h1", MACH_H1 },
  51   { "c5", MACH_C5 },
  52   { "max", MACH_MAX },
  53   { 0, 0 }
  54 };
  55
  56 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
  57 {
  58   { "mep", ISA_MEP },
  59   { "ext_core1", ISA_EXT_CORE1 },
  60   { "max", ISA_MAX },
  61   { 0, 0 }
  62 };
  63
  64 static const CGEN_ATTR_ENTRY CDATA_attr[] ATTRIBUTE_UNUSED =
  65 {
  66   { "LABEL", CDATA_LABEL },
  67   { "REGNUM", CDATA_REGNUM },
  68   { "FMAX_FLOAT", CDATA_FMAX_FLOAT },
  69   { "FMAX_INT", CDATA_FMAX_INT },
  70   { "POINTER", CDATA_POINTER },
  71   { "LONG", CDATA_LONG },
  72   { "ULONG", CDATA_ULONG },
  73   { "SHORT", CDATA_SHORT },
  74   { "USHORT", CDATA_USHORT },
  75   { "CHAR", CDATA_CHAR },
  76   { "UCHAR", CDATA_UCHAR },
  77   { "CP_DATA_BUS_INT", CDATA_CP_DATA_BUS_INT },
  78   { 0, 0 }
  79 };
  80
  81 static const CGEN_ATTR_ENTRY ALIGN_attr [] ATTRIBUTE_UNUSED =
  82 {
  83   {"integer", 1},
  84   { 0, 0 }
  85 };
  86
  87 static const CGEN_ATTR_ENTRY LATENCY_attr [] ATTRIBUTE_UNUSED =
  88 {
  89   {"integer", 0},
  90   { 0, 0 }
  91 };
  92
  93 static const CGEN_ATTR_ENTRY CONFIG_attr[] ATTRIBUTE_UNUSED =
  94 {
  95   { "NONE", CONFIG_NONE },
  96   { "default", CONFIG_DEFAULT },
  97   { 0, 0 }
  98 };
  99
 100 const CGEN_ATTR_TABLE mep_cgen_ifield_attr_table[] =
 101 {
 102   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 103   { "ISA", & ISA_attr[0], & ISA_attr[0] },
 104   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 105   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
 106   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
 107   { "RESERVED", &bool_attr[0], &bool_attr[0] },
 108   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
 109   { "SIGNED", &bool_attr[0], &bool_attr[0] },
 110   { 0, 0, 0 }
 111 };
 112
 113 const CGEN_ATTR_TABLE mep_cgen_hardware_attr_table[] =
 114 {
 115   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 116   { "ISA", & ISA_attr[0], & ISA_attr[0] },
 117   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 118   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
 119   { "PC", &bool_attr[0], &bool_attr[0] },
 120   { "PROFILE", &bool_attr[0], &bool_attr[0] },
 121   { "IS_FLOAT", &bool_attr[0], &bool_attr[0] },
 122   { 0, 0, 0 }
 123 };
 124
 125 const CGEN_ATTR_TABLE mep_cgen_operand_attr_table[] =
 126 {
 127   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 128   { "ISA", & ISA_attr[0], & ISA_attr[0] },
 129   { "CDATA", & CDATA_attr[0], & CDATA_attr[0] },
 130   { "ALIGN", & ALIGN_attr[0], & ALIGN_attr[0] },
 131   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 132   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
 133   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
 134   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
 135   { "SIGNED", &bool_attr[0], &bool_attr[0] },
 136   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
 137   { "RELAX", &bool_attr[0], &bool_attr[0] },
 138   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
 139   { "RELOC_IMPLIES_OVERFLOW", &bool_attr[0], &bool_attr[0] },
 140   { 0, 0, 0 }
 141 };
 142
 143 const CGEN_ATTR_TABLE mep_cgen_insn_attr_table[] =
 144 {
 145   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 146   { "ISA", & ISA_attr[0], & ISA_attr[0] },
 147   { "LATENCY", & LATENCY_attr[0], & LATENCY_attr[0] },
 148   { "CONFIG", & CONFIG_attr[0], & CONFIG_attr[0] },
 149   { "ALIAS", &bool_attr[0], &bool_attr[0] },
 150   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 151   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
 152   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
 153   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
 154   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
 155   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
 156   { "RELAXED", &bool_attr[0], &bool_attr[0] },
 157   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
 158   { "PBB", &bool_attr[0], &bool_attr[0] },
 159   { "OPTIONAL_BIT_INSN", &bool_attr[0], &bool_attr[0] },
 160   { "OPTIONAL_MUL_INSN", &bool_attr[0], &bool_attr[0] },
 161   { "OPTIONAL_DIV_INSN", &bool_attr[0], &bool_attr[0] },
 162   { "OPTIONAL_DEBUG_INSN", &bool_attr[0], &bool_attr[0] },
 163   { "OPTIONAL_LDZ_INSN", &bool_attr[0], &bool_attr[0] },
 164   { "OPTIONAL_ABS_INSN", &bool_attr[0], &bool_attr[0] },
 165   { "OPTIONAL_AVE_INSN", &bool_attr[0], &bool_attr[0] },
 166   { "OPTIONAL_MINMAX_INSN", &bool_attr[0], &bool_attr[0] },
 167   { "OPTIONAL_CLIP_INSN", &bool_attr[0], &bool_attr[0] },
 168   { "OPTIONAL_SAT_INSN", &bool_attr[0], &bool_attr[0] },
 169   { "OPTIONAL_UCI_INSN", &bool_attr[0], &bool_attr[0] },
 170   { "OPTIONAL_DSP_INSN", &bool_attr[0], &bool_attr[0] },
 171   { "OPTIONAL_CP_INSN", &bool_attr[0], &bool_attr[0] },
 172   { "OPTIONAL_CP64_INSN", &bool_attr[0], &bool_attr[0] },
 173   { "OPTIONAL_VLIW64", &bool_attr[0], &bool_attr[0] },
 174   { "MAY_TRAP", &bool_attr[0], &bool_attr[0] },
 175   { "VLIW_ALONE", &bool_attr[0], &bool_attr[0] },
 176   { "VLIW_NO_CORE_NOP", &bool_attr[0], &bool_attr[0] },
 177   { "VLIW_NO_COP_NOP", &bool_attr[0], &bool_attr[0] },
 178   { "VLIW64_NO_MATCHING_NOP", &bool_attr[0], &bool_attr[0] },
 179   { "VLIW32_NO_MATCHING_NOP", &bool_attr[0], &bool_attr[0] },
 180   { "VOLATILE", &bool_attr[0], &bool_attr[0] },
 181   { 0, 0, 0 }
 182 };
 183
 184 /* Instruction set variants.  */
 185
 186 static const CGEN_ISA mep_cgen_isa_table[] = {
 187   { "mep", 32, 32, 16, 32 },
 188   { "ext_core1", 32, 32, 16, 32 },
 189   { 0, 0, 0, 0, 0 }
 190 };
 191
 192 /* Machine variants.  */
 193
 194 static const CGEN_MACH mep_cgen_mach_table[] = {
 195   { "mep", "mep", MACH_MEP, 16 },
 196   { "h1", "h1", MACH_H1, 16 },
 197   { "c5", "c5", MACH_C5, 16 },
 198   { 0, 0, 0, 0 }
 199 };
 200
 201 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_gpr_entries[] =
 202 {
 203   { "$0", 0, {0, {{{0, 0}}}}, 0, 0 },
 204   { "$1", 1, {0, {{{0, 0}}}}, 0, 0 },
 205   { "$2", 2, {0, {{{0, 0}}}}, 0, 0 },
 206   { "$3", 3, {0, {{{0, 0}}}}, 0, 0 },
 207   { "$4", 4, {0, {{{0, 0}}}}, 0, 0 },
 208   { "$5", 5, {0, {{{0, 0}}}}, 0, 0 },
 209   { "$6", 6, {0, {{{0, 0}}}}, 0, 0 },
 210   { "$7", 7, {0, {{{0, 0}}}}, 0, 0 },
 211   { "$8", 8, {0, {{{0, 0}}}}, 0, 0 },
 212   { "$9", 9, {0, {{{0, 0}}}}, 0, 0 },
 213   { "$10", 10, {0, {{{0, 0}}}}, 0, 0 },
 214   { "$11", 11, {0, {{{0, 0}}}}, 0, 0 },
 215   { "$fp", 8, {0, {{{0, 0}}}}, 0, 0 },
 216   { "$tp", 13, {0, {{{0, 0}}}}, 0, 0 },
 217   { "$gp", 14, {0, {{{0, 0}}}}, 0, 0 },
 218   { "$sp", 15, {0, {{{0, 0}}}}, 0, 0 },
 219   { "$12", 12, {0, {{{0, 0}}}}, 0, 0 },
 220   { "$13", 13, {0, {{{0, 0}}}}, 0, 0 },
 221   { "$14", 14, {0, {{{0, 0}}}}, 0, 0 },
 222   { "$15", 15, {0, {{{0, 0}}}}, 0, 0 }
 223 };
 224
 225 CGEN_KEYWORD mep_cgen_opval_h_gpr =
 226 {
 227   & mep_cgen_opval_h_gpr_entries[0],
 228   20,
 229   0, 0, 0, 0, ""
 230 };
 231
 232 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_csr_entries[] =
 233 {
 234   { "$pc", 0, {0, {{{0, 0}}}}, 0, 0 },
 235   { "$lp", 1, {0, {{{0, 0}}}}, 0, 0 },
 236   { "$sar", 2, {0, {{{0, 0}}}}, 0, 0 },
 237   { "$rpb", 4, {0, {{{0, 0}}}}, 0, 0 },
 238   { "$rpe", 5, {0, {{{0, 0}}}}, 0, 0 },
 239   { "$rpc", 6, {0, {{{0, 0}}}}, 0, 0 },
 240   { "$hi", 7, {0, {{{0, 0}}}}, 0, 0 },
 241   { "$lo", 8, {0, {{{0, 0}}}}, 0, 0 },
 242   { "$mb0", 12, {0, {{{0, 0}}}}, 0, 0 },
 243   { "$me0", 13, {0, {{{0, 0}}}}, 0, 0 },
 244   { "$mb1", 14, {0, {{{0, 0}}}}, 0, 0 },
 245   { "$me1", 15, {0, {{{0, 0}}}}, 0, 0 },
 246   { "$psw", 16, {0, {{{0, 0}}}}, 0, 0 },
 247   { "$id", 17, {0, {{{0, 0}}}}, 0, 0 },
 248   { "$tmp", 18, {0, {{{0, 0}}}}, 0, 0 },
 249   { "$epc", 19, {0, {{{0, 0}}}}, 0, 0 },
 250   { "$exc", 20, {0, {{{0, 0}}}}, 0, 0 },
 251   { "$cfg", 21, {0, {{{0, 0}}}}, 0, 0 },
 252   { "$npc", 23, {0, {{{0, 0}}}}, 0, 0 },
 253   { "$dbg", 24, {0, {{{0, 0}}}}, 0, 0 },
 254   { "$depc", 25, {0, {{{0, 0}}}}, 0, 0 },
 255   { "$opt", 26, {0, {{{0, 0}}}}, 0, 0 },
 256   { "$rcfg", 27, {0, {{{0, 0}}}}, 0, 0 },
 257   { "$ccfg", 28, {0, {{{0, 0}}}}, 0, 0 },
 258   { "$vid", 22, {0, {{{0, 0}}}}, 0, 0 }
 259 };
 260
 261 CGEN_KEYWORD mep_cgen_opval_h_csr =
 262 {
 263   & mep_cgen_opval_h_csr_entries[0],
 264   25,
 265   0, 0, 0, 0, ""
 266 };
 267
 268 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_cr64_entries[] =
 269 {
 270   { "$c0", 0, {0, {{{0, 0}}}}, 0, 0 },
 271   { "$c1", 1, {0, {{{0, 0}}}}, 0, 0 },
 272   { "$c2", 2, {0, {{{0, 0}}}}, 0, 0 },
 273   { "$c3", 3, {0, {{{0, 0}}}}, 0, 0 },
 274   { "$c4", 4, {0, {{{0, 0}}}}, 0, 0 },
 275   { "$c5", 5, {0, {{{0, 0}}}}, 0, 0 },
 276   { "$c6", 6, {0, {{{0, 0}}}}, 0, 0 },
 277   { "$c7", 7, {0, {{{0, 0}}}}, 0, 0 },
 278   { "$c8", 8, {0, {{{0, 0}}}}, 0, 0 },
 279   { "$c9", 9, {0, {{{0, 0}}}}, 0, 0 },
 280   { "$c10", 10, {0, {{{0, 0}}}}, 0, 0 },
 281   { "$c11", 11, {0, {{{0, 0}}}}, 0, 0 },
 282   { "$c12", 12, {0, {{{0, 0}}}}, 0, 0 },
 283   { "$c13", 13, {0, {{{0, 0}}}}, 0, 0 },
 284   { "$c14", 14, {0, {{{0, 0}}}}, 0, 0 },
 285   { "$c15", 15, {0, {{{0, 0}}}}, 0, 0 },
 286   { "$c16", 16, {0, {{{0, 0}}}}, 0, 0 },
 287   { "$c17", 17, {0, {{{0, 0}}}}, 0, 0 },
 288   { "$c18", 18, {0, {{{0, 0}}}}, 0, 0 },
 289   { "$c19", 19, {0, {{{0, 0}}}}, 0, 0 },
 290   { "$c20", 20, {0, {{{0, 0}}}}, 0, 0 },
 291   { "$c21", 21, {0, {{{0, 0}}}}, 0, 0 },
 292   { "$c22", 22, {0, {{{0, 0}}}}, 0, 0 },
 293   { "$c23", 23, {0, {{{0, 0}}}}, 0, 0 },
 294   { "$c24", 24, {0, {{{0, 0}}}}, 0, 0 },
 295   { "$c25", 25, {0, {{{0, 0}}}}, 0, 0 },
 296   { "$c26", 26, {0, {{{0, 0}}}}, 0, 0 },
 297   { "$c27", 27, {0, {{{0, 0}}}}, 0, 0 },
 298   { "$c28", 28, {0, {{{0, 0}}}}, 0, 0 },
 299   { "$c29", 29, {0, {{{0, 0}}}}, 0, 0 },
 300   { "$c30", 30, {0, {{{0, 0}}}}, 0, 0 },
 301   { "$c31", 31, {0, {{{0, 0}}}}, 0, 0 }
 302 };
 303
 304 CGEN_KEYWORD mep_cgen_opval_h_cr64 =
 305 {
 306   & mep_cgen_opval_h_cr64_entries[0],
 307   32,
 308   0, 0, 0, 0, ""
 309 };
 310
 311 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_cr_entries[] =
 312 {
 313   { "$c0", 0, {0, {{{0, 0}}}}, 0, 0 },
 314   { "$c1", 1, {0, {{{0, 0}}}}, 0, 0 },
 315   { "$c2", 2, {0, {{{0, 0}}}}, 0, 0 },
 316   { "$c3", 3, {0, {{{0, 0}}}}, 0, 0 },
 317   { "$c4", 4, {0, {{{0, 0}}}}, 0, 0 },
 318   { "$c5", 5, {0, {{{0, 0}}}}, 0, 0 },
 319   { "$c6", 6, {0, {{{0, 0}}}}, 0, 0 },
 320   { "$c7", 7, {0, {{{0, 0}}}}, 0, 0 },
 321   { "$c8", 8, {0, {{{0, 0}}}}, 0, 0 },
 322   { "$c9", 9, {0, {{{0, 0}}}}, 0, 0 },
 323   { "$c10", 10, {0, {{{0, 0}}}}, 0, 0 },
 324   { "$c11", 11, {0, {{{0, 0}}}}, 0, 0 },
 325   { "$c12", 12, {0, {{{0, 0}}}}, 0, 0 },
 326   { "$c13", 13, {0, {{{0, 0}}}}, 0, 0 },
 327   { "$c14", 14, {0, {{{0, 0}}}}, 0, 0 },
 328   { "$c15", 15, {0, {{{0, 0}}}}, 0, 0 },
 329   { "$c16", 16, {0, {{{0, 0}}}}, 0, 0 },
 330   { "$c17", 17, {0, {{{0, 0}}}}, 0, 0 },
 331   { "$c18", 18, {0, {{{0, 0}}}}, 0, 0 },
 332   { "$c19", 19, {0, {{{0, 0}}}}, 0, 0 },
 333   { "$c20", 20, {0, {{{0, 0}}}}, 0, 0 },
 334   { "$c21", 21, {0, {{{0, 0}}}}, 0, 0 },
 335   { "$c22", 22, {0, {{{0, 0}}}}, 0, 0 },
 336   { "$c23", 23, {0, {{{0, 0}}}}, 0, 0 },
 337   { "$c24", 24, {0, {{{0, 0}}}}, 0, 0 },
 338   { "$c25", 25, {0, {{{0, 0}}}}, 0, 0 },
 339   { "$c26", 26, {0, {{{0, 0}}}}, 0, 0 },
 340   { "$c27", 27, {0, {{{0, 0}}}}, 0, 0 },
 341   { "$c28", 28, {0, {{{0, 0}}}}, 0, 0 },
 342   { "$c29", 29, {0, {{{0, 0}}}}, 0, 0 },
 343   { "$c30", 30, {0, {{{0, 0}}}}, 0, 0 },
 344   { "$c31", 31, {0, {{{0, 0}}}}, 0, 0 }
 345 };
 346
 347 CGEN_KEYWORD mep_cgen_opval_h_cr =
 348 {
 349   & mep_cgen_opval_h_cr_entries[0],
 350   32,
 351   0, 0, 0, 0, ""
 352 };
 353
 354 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_ccr_entries[] =
 355 {
 356   { "$ccr0", 0, {0, {{{0, 0}}}}, 0, 0 },
 357   { "$ccr1", 1, {0, {{{0, 0}}}}, 0, 0 },
 358   { "$ccr2", 2, {0, {{{0, 0}}}}, 0, 0 },
 359   { "$ccr3", 3, {0, {{{0, 0}}}}, 0, 0 },
 360   { "$ccr4", 4, {0, {{{0, 0}}}}, 0, 0 },
 361   { "$ccr5", 5, {0, {{{0, 0}}}}, 0, 0 },
 362   { "$ccr6", 6, {0, {{{0, 0}}}}, 0, 0 },
 363   { "$ccr7", 7, {0, {{{0, 0}}}}, 0, 0 },
 364   { "$ccr8", 8, {0, {{{0, 0}}}}, 0, 0 },
 365   { "$ccr9", 9, {0, {{{0, 0}}}}, 0, 0 },
 366   { "$ccr10", 10, {0, {{{0, 0}}}}, 0, 0 },
 367   { "$ccr11", 11, {0, {{{0, 0}}}}, 0, 0 },
 368   { "$ccr12", 12, {0, {{{0, 0}}}}, 0, 0 },
 369   { "$ccr13", 13, {0, {{{0, 0}}}}, 0, 0 },
 370   { "$ccr14", 14, {0, {{{0, 0}}}}, 0, 0 },
 371   { "$ccr15", 15, {0, {{{0, 0}}}}, 0, 0 },
 372   { "$ccr16", 16, {0, {{{0, 0}}}}, 0, 0 },
 373   { "$ccr17", 17, {0, {{{0, 0}}}}, 0, 0 },
 374   { "$ccr18", 18, {0, {{{0, 0}}}}, 0, 0 },
 375   { "$ccr19", 19, {0, {{{0, 0}}}}, 0, 0 },
 376   { "$ccr20", 20, {0, {{{0, 0}}}}, 0, 0 },
 377   { "$ccr21", 21, {0, {{{0, 0}}}}, 0, 0 },
 378   { "$ccr22", 22, {0, {{{0, 0}}}}, 0, 0 },
 379   { "$ccr23", 23, {0, {{{0, 0}}}}, 0, 0 },
 380   { "$ccr24", 24, {0, {{{0, 0}}}}, 0, 0 },
 381   { "$ccr25", 25, {0, {{{0, 0}}}}, 0, 0 },
 382   { "$ccr26", 26, {0, {{{0, 0}}}}, 0, 0 },
 383   { "$ccr27", 27, {0, {{{0, 0}}}}, 0, 0 },
 384   { "$ccr28", 28, {0, {{{0, 0}}}}, 0, 0 },
 385   { "$ccr29", 29, {0, {{{0, 0}}}}, 0, 0 },
 386   { "$ccr30", 30, {0, {{{0, 0}}}}, 0, 0 },
 387   { "$ccr31", 31, {0, {{{0, 0}}}}, 0, 0 },
 388   { "$ccr32", 32, {0, {{{0, 0}}}}, 0, 0 },
 389   { "$ccr33", 33, {0, {{{0, 0}}}}, 0, 0 },
 390   { "$ccr34", 34, {0, {{{0, 0}}}}, 0, 0 },
 391   { "$ccr35", 35, {0, {{{0, 0}}}}, 0, 0 },
 392   { "$ccr36", 36, {0, {{{0, 0}}}}, 0, 0 },
 393   { "$ccr37", 37, {0, {{{0, 0}}}}, 0, 0 },
 394   { "$ccr38", 38, {0, {{{0, 0}}}}, 0, 0 },
 395   { "$ccr39", 39, {0, {{{0, 0}}}}, 0, 0 },
 396   { "$ccr40", 40, {0, {{{0, 0}}}}, 0, 0 },
 397   { "$ccr41", 41, {0, {{{0, 0}}}}, 0, 0 },
 398   { "$ccr42", 42, {0, {{{0, 0}}}}, 0, 0 },
 399   { "$ccr43", 43, {0, {{{0, 0}}}}, 0, 0 },
 400   { "$ccr44", 44, {0, {{{0, 0}}}}, 0, 0 },
 401   { "$ccr45", 45, {0, {{{0, 0}}}}, 0, 0 },
 402   { "$ccr46", 46, {0, {{{0, 0}}}}, 0, 0 },
 403   { "$ccr47", 47, {0, {{{0, 0}}}}, 0, 0 },
 404   { "$ccr48", 48, {0, {{{0, 0}}}}, 0, 0 },
 405   { "$ccr49", 49, {0, {{{0, 0}}}}, 0, 0 },
 406   { "$ccr50", 50, {0, {{{0, 0}}}}, 0, 0 },
 407   { "$ccr51", 51, {0, {{{0, 0}}}}, 0, 0 },
 408   { "$ccr52", 52, {0, {{{0, 0}}}}, 0, 0 },
 409   { "$ccr53", 53, {0, {{{0, 0}}}}, 0, 0 },
 410   { "$ccr54", 54, {0, {{{0, 0}}}}, 0, 0 },
 411   { "$ccr55", 55, {0, {{{0, 0}}}}, 0, 0 },
 412   { "$ccr56", 56, {0, {{{0, 0}}}}, 0, 0 },
 413   { "$ccr57", 57, {0, {{{0, 0}}}}, 0, 0 },
 414   { "$ccr58", 58, {0, {{{0, 0}}}}, 0, 0 },
 415   { "$ccr59", 59, {0, {{{0, 0}}}}, 0, 0 },
 416   { "$ccr60", 60, {0, {{{0, 0}}}}, 0, 0 },
 417   { "$ccr61", 61, {0, {{{0, 0}}}}, 0, 0 },
 418   { "$ccr62", 62, {0, {{{0, 0}}}}, 0, 0 },
 419   { "$ccr63", 63, {0, {{{0, 0}}}}, 0, 0 }
 420 };
 421
 422 CGEN_KEYWORD mep_cgen_opval_h_ccr =
 423 {
 424   & mep_cgen_opval_h_ccr_entries[0],
 425   64,
 426   0, 0, 0, 0, ""
 427 };
 428
 429
 430 /* The hardware table.  */
 431
 432 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 433 #define A(a) (1 << CGEN_HW_##a)
 434 #else
 435 #define A(a) (1 << CGEN_HW_/**/a)
 436 #endif
 437
 438 const CGEN_HW_ENTRY mep_cgen_hw_table[] =
 439 {
 440   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
 441   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
 442   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
 443   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
 444   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
 445   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
 446   { "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_gpr, { 0|A(PROFILE)|A(CACHE_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
 447   { "h-csr", HW_H_CSR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_csr, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
 448   { "h-cr64", HW_H_CR64, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr64, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
 449   { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
 450   { "h-ccr", HW_H_CCR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_ccr, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
 451   { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
 452 };
 453
 454 #undef A
 455
 456
 457 /* The instruction field table.  */
 458
 459 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 460 #define A(a) (1 << CGEN_IFLD_##a)
 461 #else
 462 #define A(a) (1 << CGEN_IFLD_/**/a)
 463 #endif
 464
 465 const CGEN_IFLD mep_cgen_ifld_table[] =
 466 {
 467   { MEP_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
 468   { MEP_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
 469   { MEP_F_MAJOR, "f-major", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 470   { MEP_F_RN, "f-rn", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 471   { MEP_F_RN3, "f-rn3", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 472   { MEP_F_RM, "f-rm", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 473   { MEP_F_RL, "f-rl", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 474   { MEP_F_SUB2, "f-sub2", 0, 32, 14, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 475   { MEP_F_SUB3, "f-sub3", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 476   { MEP_F_SUB4, "f-sub4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 477   { MEP_F_EXT, "f-ext", 0, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 478   { MEP_F_EXT4, "f-ext4", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 479   { MEP_F_EXT62, "f-ext62", 0, 32, 20, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 480   { MEP_F_CRN, "f-crn", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 481   { MEP_F_CSRN_HI, "f-csrn-hi", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 482   { MEP_F_CSRN_LO, "f-csrn-lo", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 483   { MEP_F_CSRN, "f-csrn", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 484   { MEP_F_CRNX_HI, "f-crnx-hi", 0, 32, 28, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 485   { MEP_F_CRNX_LO, "f-crnx-lo", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 486   { MEP_F_CRNX, "f-crnx", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 487   { MEP_F_0, "f-0", 0, 32, 0, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 488   { MEP_F_1, "f-1", 0, 32, 1, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 489   { MEP_F_2, "f-2", 0, 32, 2, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 490   { MEP_F_3, "f-3", 0, 32, 3, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 491   { MEP_F_4, "f-4", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 492   { MEP_F_5, "f-5", 0, 32, 5, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 493   { MEP_F_6, "f-6", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 494   { MEP_F_7, "f-7", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 495   { MEP_F_8, "f-8", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 496   { MEP_F_9, "f-9", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 497   { MEP_F_10, "f-10", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 498   { MEP_F_11, "f-11", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 499   { MEP_F_12, "f-12", 0, 32, 12, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 500   { MEP_F_13, "f-13", 0, 32, 13, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 501   { MEP_F_14, "f-14", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 502   { MEP_F_15, "f-15", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 503   { MEP_F_16, "f-16", 0, 32, 16, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 504   { MEP_F_17, "f-17", 0, 32, 17, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 505   { MEP_F_18, "f-18", 0, 32, 18, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 506   { MEP_F_19, "f-19", 0, 32, 19, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 507   { MEP_F_20, "f-20", 0, 32, 20, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 508   { MEP_F_21, "f-21", 0, 32, 21, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 509   { MEP_F_22, "f-22", 0, 32, 22, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 510   { MEP_F_23, "f-23", 0, 32, 23, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 511   { MEP_F_24, "f-24", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 512   { MEP_F_25, "f-25", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 513   { MEP_F_26, "f-26", 0, 32, 26, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 514   { MEP_F_27, "f-27", 0, 32, 27, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 515   { MEP_F_28, "f-28", 0, 32, 28, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 516   { MEP_F_29, "f-29", 0, 32, 29, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 517   { MEP_F_30, "f-30", 0, 32, 30, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 518   { MEP_F_31, "f-31", 0, 32, 31, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 519   { MEP_F_8S8A2, "f-8s8a2", 0, 32, 8, 7, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 520   { MEP_F_12S4A2, "f-12s4a2", 0, 32, 4, 11, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 521   { MEP_F_17S16A2, "f-17s16a2", 0, 32, 16, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 522   { MEP_F_24S5A2N_HI, "f-24s5a2n-hi", 0, 32, 16, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 523   { MEP_F_24S5A2N_LO, "f-24s5a2n-lo", 0, 32, 5, 7, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 524   { MEP_F_24S5A2N, "f-24s5a2n", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 525   { MEP_F_24U5A2N_HI, "f-24u5a2n-hi", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 526   { MEP_F_24U5A2N_LO, "f-24u5a2n-lo", 0, 32, 5, 7, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 527   { MEP_F_24U5A2N, "f-24u5a2n", 0, 0, 0, 0,{ 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 528   { MEP_F_2U6, "f-2u6", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 529   { MEP_F_7U9, "f-7u9", 0, 32, 9, 7, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 530   { MEP_F_7U9A2, "f-7u9a2", 0, 32, 9, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 531   { MEP_F_7U9A4, "f-7u9a4", 0, 32, 9, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 532   { MEP_F_16S16, "f-16s16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 533   { MEP_F_2U10, "f-2u10", 0, 32, 10, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 534   { MEP_F_3U5, "f-3u5", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 535   { MEP_F_4U8, "f-4u8", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 536   { MEP_F_5U8, "f-5u8", 0, 32, 8, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 537   { MEP_F_5U24, "f-5u24", 0, 32, 24, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 538   { MEP_F_6S8, "f-6s8", 0, 32, 8, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 539   { MEP_F_8S8, "f-8s8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 540   { MEP_F_16U16, "f-16u16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 541   { MEP_F_12U16, "f-12u16", 0, 32, 16, 12, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 542   { MEP_F_3U29, "f-3u29", 0, 32, 29, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 543   { MEP_F_CDISP10, "f-cdisp10", 0, 32, 22, 10, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 544   { MEP_F_24U8A4N_HI, "f-24u8a4n-hi", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 545   { MEP_F_24U8A4N_LO, "f-24u8a4n-lo", 0, 32, 8, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 546   { MEP_F_24U8A4N, "f-24u8a4n", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 547   { MEP_F_24U8N_HI, "f-24u8n-hi", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 548   { MEP_F_24U8N_LO, "f-24u8n-lo", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 549   { MEP_F_24U8N, "f-24u8n", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 550   { MEP_F_24U4N_HI, "f-24u4n-hi", 0, 32, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 551   { MEP_F_24U4N_LO, "f-24u4n-lo", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 552   { MEP_F_24U4N, "f-24u4n", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 553   { MEP_F_CALLNUM, "f-callnum", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 554   { MEP_F_CCRN_HI, "f-ccrn-hi", 0, 32, 28, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 555   { MEP_F_CCRN_LO, "f-ccrn-lo", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 556   { MEP_F_CCRN, "f-ccrn", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 557   { MEP_F_C5N4, "f-c5n4", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 558   { MEP_F_C5N5, "f-c5n5", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 559   { MEP_F_C5N6, "f-c5n6", 0, 32, 24, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 560   { MEP_F_C5N7, "f-c5n7", 0, 32, 28, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 561   { MEP_F_RL5, "f-rl5", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 562   { MEP_F_12S20, "f-12s20", 0, 32, 20, 12, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 563   { MEP_F_C5_RNM, "f-c5-rnm", 0, 32, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 564   { MEP_F_C5_RM, "f-c5-rm", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 565   { MEP_F_C5_16U16, "f-c5-16u16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 566   { MEP_F_C5_RMUIMM20, "f-c5-rmuimm20", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 567   { MEP_F_C5_RNMUIMM24, "f-c5-rnmuimm24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 568   { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
 569 };
 570
 571 #undef A
 572
 573
 574
 575 /* multi ifield declarations */
 576
 577 const CGEN_MAYBE_MULTI_IFLD MEP_F_CSRN_MULTI_IFIELD [];
 578 const CGEN_MAYBE_MULTI_IFLD MEP_F_CRNX_MULTI_IFIELD [];
 579 const CGEN_MAYBE_MULTI_IFLD MEP_F_24S5A2N_MULTI_IFIELD [];
 580 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U5A2N_MULTI_IFIELD [];
 581 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8A4N_MULTI_IFIELD [];
 582 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8N_MULTI_IFIELD [];
 583 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U4N_MULTI_IFIELD [];
 584 const CGEN_MAYBE_MULTI_IFLD MEP_F_CALLNUM_MULTI_IFIELD [];
 585 const CGEN_MAYBE_MULTI_IFLD MEP_F_CCRN_MULTI_IFIELD [];
 586 const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RMUIMM20_MULTI_IFIELD [];
 587 const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RNMUIMM24_MULTI_IFIELD [];
 588
 589
 590 /* multi ifield definitions */
 591
 592 const CGEN_MAYBE_MULTI_IFLD MEP_F_CSRN_MULTI_IFIELD [] =
 593 {
 594     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CSRN_HI] } },
 595     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CSRN_LO] } },
 596     { 0, { (const PTR) 0 } }
 597 };
 598 const CGEN_MAYBE_MULTI_IFLD MEP_F_CRNX_MULTI_IFIELD [] =
 599 {
 600     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRNX_HI] } },
 601     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRNX_LO] } },
 602     { 0, { (const PTR) 0 } }
 603 };
 604 const CGEN_MAYBE_MULTI_IFLD MEP_F_24S5A2N_MULTI_IFIELD [] =
 605 {
 606     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24S5A2N_HI] } },
 607     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24S5A2N_LO] } },
 608     { 0, { (const PTR) 0 } }
 609 };
 610 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U5A2N_MULTI_IFIELD [] =
 611 {
 612     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U5A2N_HI] } },
 613     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U5A2N_LO] } },
 614     { 0, { (const PTR) 0 } }
 615 };
 616 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8A4N_MULTI_IFIELD [] =
 617 {
 618     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8A4N_HI] } },
 619     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8A4N_LO] } },
 620     { 0, { (const PTR) 0 } }
 621 };
 622 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8N_MULTI_IFIELD [] =
 623 {
 624     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8N_HI] } },
 625     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8N_LO] } },
 626     { 0, { (const PTR) 0 } }
 627 };
 628 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U4N_MULTI_IFIELD [] =
 629 {
 630     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U4N_HI] } },
 631     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U4N_LO] } },
 632     { 0, { (const PTR) 0 } }
 633 };
 634 const CGEN_MAYBE_MULTI_IFLD MEP_F_CALLNUM_MULTI_IFIELD [] =
 635 {
 636     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5] } },
 637     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_6] } },
 638     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7] } },
 639     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_11] } },
 640     { 0, { (const PTR) 0 } }
 641 };
 642 const CGEN_MAYBE_MULTI_IFLD MEP_F_CCRN_MULTI_IFIELD [] =
 643 {
 644     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CCRN_HI] } },
 645     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CCRN_LO] } },
 646     { 0, { (const PTR) 0 } }
 647 };
 648 const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RMUIMM20_MULTI_IFIELD [] =
 649 {
 650     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_RM] } },
 651     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_16U16] } },
 652     { 0, { (const PTR) 0 } }
 653 };
 654 const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RNMUIMM24_MULTI_IFIELD [] =
 655 {
 656     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_RNM] } },
 657     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_16U16] } },
 658     { 0, { (const PTR) 0 } }
 659 };
 660
 661 /* The operand table.  */
 662
 663 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 664 #define A(a) (1 << CGEN_OPERAND_##a)
 665 #else
 666 #define A(a) (1 << CGEN_OPERAND_/**/a)
 667 #endif
 668 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 669 #define OPERAND(op) MEP_OPERAND_##op
 670 #else
 671 #define OPERAND(op) MEP_OPERAND_/**/op
 672 #endif
 673
 674 const CGEN_OPERAND mep_cgen_operand_table[] =
 675 {
 676 /* pc: program counter */
 677   { "pc", MEP_OPERAND_PC, HW_H_PC, 0, 0,
 678     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_NIL] } },
 679     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 680 /* r0: register 0 */
 681   { "r0", MEP_OPERAND_R0, HW_H_GPR, 0, 0,
 682     { 0, { (const PTR) 0 } },
 683     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 684 /* rn: register Rn */
 685   { "rn", MEP_OPERAND_RN, HW_H_GPR, 4, 4,
 686     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
 687     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 688 /* rm: register Rm */
 689   { "rm", MEP_OPERAND_RM, HW_H_GPR, 8, 4,
 690     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
 691     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 692 /* rl: register Rl */
 693   { "rl", MEP_OPERAND_RL, HW_H_GPR, 12, 4,
 694     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RL] } },
 695     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 696 /* rn3: register 0-7 */
 697   { "rn3", MEP_OPERAND_RN3, HW_H_GPR, 5, 3,
 698     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
 699     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 700 /* rma: register Rm holding pointer */
 701   { "rma", MEP_OPERAND_RMA, HW_H_GPR, 8, 4,
 702     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
 703     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_POINTER, 0 } }, { { 1, 0 } } } }  },
 704 /* rnc: register Rn holding char */
 705   { "rnc", MEP_OPERAND_RNC, HW_H_GPR, 4, 4,
 706     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
 707     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 708 /* rnuc: register Rn holding unsigned char */
 709   { "rnuc", MEP_OPERAND_RNUC, HW_H_GPR, 4, 4,
 710     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
 711     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 712 /* rns: register Rn holding short */
 713   { "rns", MEP_OPERAND_RNS, HW_H_GPR, 4, 4,
 714     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
 715     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 716 /* rnus: register Rn holding unsigned short */
 717   { "rnus", MEP_OPERAND_RNUS, HW_H_GPR, 4, 4,
 718     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
 719     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 720 /* rnl: register Rn holding long */
 721   { "rnl", MEP_OPERAND_RNL, HW_H_GPR, 4, 4,
 722     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
 723     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 724 /* rnul: register Rn holding unsigned  long */
 725   { "rnul", MEP_OPERAND_RNUL, HW_H_GPR, 4, 4,
 726     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
 727     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_ULONG, 0 } }, { { 1, 0 } } } }  },
 728 /* rn3c: register 0-7 holding unsigned char */
 729   { "rn3c", MEP_OPERAND_RN3C, HW_H_GPR, 5, 3,
 730     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
 731     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 732 /* rn3uc: register 0-7 holding byte */
 733   { "rn3uc", MEP_OPERAND_RN3UC, HW_H_GPR, 5, 3,
 734     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
 735     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 736 /* rn3s: register 0-7 holding unsigned short */
 737   { "rn3s", MEP_OPERAND_RN3S, HW_H_GPR, 5, 3,
 738     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
 739     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 740 /* rn3us: register 0-7 holding short */
 741   { "rn3us", MEP_OPERAND_RN3US, HW_H_GPR, 5, 3,
 742     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
 743     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 744 /* rn3l: register 0-7 holding unsigned long */
 745   { "rn3l", MEP_OPERAND_RN3L, HW_H_GPR, 5, 3,
 746     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
 747     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 748 /* rn3ul: register 0-7 holding long */
 749   { "rn3ul", MEP_OPERAND_RN3UL, HW_H_GPR, 5, 3,
 750     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
 751     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_ULONG, 0 } }, { { 1, 0 } } } }  },
 752 /* lp: link pointer */
 753   { "lp", MEP_OPERAND_LP, HW_H_CSR, 0, 0,
 754     { 0, { (const PTR) 0 } },
 755     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 756 /* sar: shift amount register */
 757   { "sar", MEP_OPERAND_SAR, HW_H_CSR, 0, 0,
 758     { 0, { (const PTR) 0 } },
 759     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 760 /* hi: high result */
 761   { "hi", MEP_OPERAND_HI, HW_H_CSR, 0, 0,
 762     { 0, { (const PTR) 0 } },
 763     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 764 /* lo: low result */
 765   { "lo", MEP_OPERAND_LO, HW_H_CSR, 0, 0,
 766     { 0, { (const PTR) 0 } },
 767     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 768 /* mb0: modulo begin register 0 */
 769   { "mb0", MEP_OPERAND_MB0, HW_H_CSR, 0, 0,
 770     { 0, { (const PTR) 0 } },
 771     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 772 /* me0: modulo end register 0 */
 773   { "me0", MEP_OPERAND_ME0, HW_H_CSR, 0, 0,
 774     { 0, { (const PTR) 0 } },
 775     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 776 /* mb1: modulo begin register 1 */
 777   { "mb1", MEP_OPERAND_MB1, HW_H_CSR, 0, 0,
 778     { 0, { (const PTR) 0 } },
 779     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 780 /* me1: modulo end register 1 */
 781   { "me1", MEP_OPERAND_ME1, HW_H_CSR, 0, 0,
 782     { 0, { (const PTR) 0 } },
 783     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 784 /* psw: program status word */
 785   { "psw", MEP_OPERAND_PSW, HW_H_CSR, 0, 0,
 786     { 0, { (const PTR) 0 } },
 787     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 788 /* epc: exception prog counter */
 789   { "epc", MEP_OPERAND_EPC, HW_H_CSR, 0, 0,
 790     { 0, { (const PTR) 0 } },
 791     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 792 /* exc: exception cause */
 793   { "exc", MEP_OPERAND_EXC, HW_H_CSR, 0, 0,
 794     { 0, { (const PTR) 0 } },
 795     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 796 /* npc: nmi program counter */
 797   { "npc", MEP_OPERAND_NPC, HW_H_CSR, 0, 0,
 798     { 0, { (const PTR) 0 } },
 799     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 800 /* dbg: debug register */
 801   { "dbg", MEP_OPERAND_DBG, HW_H_CSR, 0, 0,
 802     { 0, { (const PTR) 0 } },
 803     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 804 /* depc: debug exception pc */
 805   { "depc", MEP_OPERAND_DEPC, HW_H_CSR, 0, 0,
 806     { 0, { (const PTR) 0 } },
 807     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 808 /* opt: option register */
 809   { "opt", MEP_OPERAND_OPT, HW_H_CSR, 0, 0,
 810     { 0, { (const PTR) 0 } },
 811     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 812 /* r1: register 1 */
 813   { "r1", MEP_OPERAND_R1, HW_H_GPR, 0, 0,
 814     { 0, { (const PTR) 0 } },
 815     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 816 /* tp: tiny data area pointer */
 817   { "tp", MEP_OPERAND_TP, HW_H_GPR, 0, 0,
 818     { 0, { (const PTR) 0 } },
 819     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 820 /* sp: stack pointer */
 821   { "sp", MEP_OPERAND_SP, HW_H_GPR, 0, 0,
 822     { 0, { (const PTR) 0 } },
 823     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 824 /* tpr: comment */
 825   { "tpr", MEP_OPERAND_TPR, HW_H_GPR, 0, 0,
 826     { 0, { (const PTR) 0 } },
 827     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 828 /* spr: comment */
 829   { "spr", MEP_OPERAND_SPR, HW_H_GPR, 0, 0,
 830     { 0, { (const PTR) 0 } },
 831     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 832 /* csrn: control/special register */
 833   { "csrn", MEP_OPERAND_CSRN, HW_H_CSR, 8, 5,
 834     { 2, { (const PTR) &MEP_F_CSRN_MULTI_IFIELD[0] } },
 835     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } }  },
 836 /* csrn-idx: control/special reg idx */
 837   { "csrn-idx", MEP_OPERAND_CSRN_IDX, HW_H_UINT, 8, 5,
 838     { 2, { (const PTR) &MEP_F_CSRN_MULTI_IFIELD[0] } },
 839     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 840 /* crn64: copro Rn (64-bit) */
 841   { "crn64", MEP_OPERAND_CRN64, HW_H_CR64, 4, 4,
 842     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRN] } },
 843     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
 844 /* crn: copro Rn (32-bit) */
 845   { "crn", MEP_OPERAND_CRN, HW_H_CR, 4, 4,
 846     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRN] } },
 847     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
 848 /* crnx64: copro Rn (0-31, 64-bit) */
 849   { "crnx64", MEP_OPERAND_CRNX64, HW_H_CR64, 4, 5,
 850     { 2, { (const PTR) &MEP_F_CRNX_MULTI_IFIELD[0] } },
 851     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
 852 /* crnx: copro Rn (0-31, 32-bit) */
 853   { "crnx", MEP_OPERAND_CRNX, HW_H_CR, 4, 5,
 854     { 2, { (const PTR) &MEP_F_CRNX_MULTI_IFIELD[0] } },
 855     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
 856 /* ccrn: copro control reg CCRn */
 857   { "ccrn", MEP_OPERAND_CCRN, HW_H_CCR, 4, 6,
 858     { 2, { (const PTR) &MEP_F_CCRN_MULTI_IFIELD[0] } },
 859     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } }  },
 860 /* cccc: copro flags */
 861   { "cccc", MEP_OPERAND_CCCC, HW_H_UINT, 8, 4,
 862     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
 863     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 864 /* pcrel8a2: comment */
 865   { "pcrel8a2", MEP_OPERAND_PCREL8A2, HW_H_SINT, 8, 7,
 866     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S8A2] } },
 867     { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } }  },
 868 /* pcrel12a2: comment */
 869   { "pcrel12a2", MEP_OPERAND_PCREL12A2, HW_H_SINT, 4, 11,
 870     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_12S4A2] } },
 871     { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } }  },
 872 /* pcrel17a2: comment */
 873   { "pcrel17a2", MEP_OPERAND_PCREL17A2, HW_H_SINT, 16, 16,
 874     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_17S16A2] } },
 875     { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } }  },
 876 /* pcrel24a2: comment */
 877   { "pcrel24a2", MEP_OPERAND_PCREL24A2, HW_H_SINT, 5, 23,
 878     { 2, { (const PTR) &MEP_F_24S5A2N_MULTI_IFIELD[0] } },
 879     { 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } }  },
 880 /* pcabs24a2: comment */
 881   { "pcabs24a2", MEP_OPERAND_PCABS24A2, HW_H_UINT, 5, 23,
 882     { 2, { (const PTR) &MEP_F_24U5A2N_MULTI_IFIELD[0] } },
 883     { 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } }  },
 884 /* sdisp16: comment */
 885   { "sdisp16", MEP_OPERAND_SDISP16, HW_H_SINT, 16, 16,
 886     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16S16] } },
 887     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 888 /* simm16: comment */
 889   { "simm16", MEP_OPERAND_SIMM16, HW_H_SINT, 16, 16,
 890     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16S16] } },
 891     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 892 /* uimm16: comment */
 893   { "uimm16", MEP_OPERAND_UIMM16, HW_H_UINT, 16, 16,
 894     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16U16] } },
 895     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 896 /* code16: uci/dsp code (16 bits) */
 897   { "code16", MEP_OPERAND_CODE16, HW_H_UINT, 16, 16,
 898     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16U16] } },
 899     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 900 /* udisp2: SSARB addend (2 bits) */
 901   { "udisp2", MEP_OPERAND_UDISP2, HW_H_SINT, 6, 2,
 902     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_2U6] } },
 903     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 904 /* uimm2: interrupt (2 bits) */
 905   { "uimm2", MEP_OPERAND_UIMM2, HW_H_UINT, 10, 2,
 906     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_2U10] } },
 907     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 908 /* simm6: add const (6 bits) */
 909   { "simm6", MEP_OPERAND_SIMM6, HW_H_SINT, 8, 6,
 910     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_6S8] } },
 911     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 912 /* simm8: mov const (8 bits) */
 913   { "simm8", MEP_OPERAND_SIMM8, HW_H_SINT, 8, 8,
 914     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S8] } },
 915     { 0|A(RELOC_IMPLIES_OVERFLOW), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 916 /* addr24a4: comment */
 917   { "addr24a4", MEP_OPERAND_ADDR24A4, HW_H_UINT, 8, 22,
 918     { 2, { (const PTR) &MEP_F_24U8A4N_MULTI_IFIELD[0] } },
 919     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } }  },
 920 /* code24: coprocessor code */
 921   { "code24", MEP_OPERAND_CODE24, HW_H_UINT, 4, 24,
 922     { 2, { (const PTR) &MEP_F_24U4N_MULTI_IFIELD[0] } },
 923     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 924 /* callnum: system call number */
 925   { "callnum", MEP_OPERAND_CALLNUM, HW_H_UINT, 5, 4,
 926     { 4, { (const PTR) &MEP_F_CALLNUM_MULTI_IFIELD[0] } },
 927     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 928 /* uimm3: bit immediate (3 bits) */
 929   { "uimm3", MEP_OPERAND_UIMM3, HW_H_UINT, 5, 3,
 930     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_3U5] } },
 931     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 932 /* uimm4: bCC const (4 bits) */
 933   { "uimm4", MEP_OPERAND_UIMM4, HW_H_UINT, 8, 4,
 934     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_4U8] } },
 935     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 936 /* uimm5: bit/shift val (5 bits) */
 937   { "uimm5", MEP_OPERAND_UIMM5, HW_H_UINT, 8, 5,
 938     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5U8] } },
 939     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 940 /* udisp7: comment */
 941   { "udisp7", MEP_OPERAND_UDISP7, HW_H_UINT, 9, 7,
 942     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9] } },
 943     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 944 /* udisp7a2: comment */
 945   { "udisp7a2", MEP_OPERAND_UDISP7A2, HW_H_UINT, 9, 6,
 946     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A2] } },
 947     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 2, 0 } } } }  },
 948 /* udisp7a4: comment */
 949   { "udisp7a4", MEP_OPERAND_UDISP7A4, HW_H_UINT, 9, 5,
 950     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A4] } },
 951     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } }  },
 952 /* uimm7a4: comment */
 953   { "uimm7a4", MEP_OPERAND_UIMM7A4, HW_H_UINT, 9, 5,
 954     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A4] } },
 955     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } }  },
 956 /* uimm24: immediate (24 bits) */
 957   { "uimm24", MEP_OPERAND_UIMM24, HW_H_UINT, 8, 24,
 958     { 2, { (const PTR) &MEP_F_24U8N_MULTI_IFIELD[0] } },
 959     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 960 /* cimm4: cache immed'te (4 bits) */
 961   { "cimm4", MEP_OPERAND_CIMM4, HW_H_UINT, 4, 4,
 962     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
 963     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 964 /* cimm5: clip immediate (5 bits) */
 965   { "cimm5", MEP_OPERAND_CIMM5, HW_H_UINT, 24, 5,
 966     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5U24] } },
 967     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 968 /* cdisp10: comment */
 969   { "cdisp10", MEP_OPERAND_CDISP10, HW_H_SINT, 22, 10,
 970     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
 971     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 972 /* cdisp10a2: comment */
 973   { "cdisp10a2", MEP_OPERAND_CDISP10A2, HW_H_SINT, 22, 10,
 974     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
 975     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 976 /* cdisp10a4: comment */
 977   { "cdisp10a4", MEP_OPERAND_CDISP10A4, HW_H_SINT, 22, 10,
 978     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
 979     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 980 /* cdisp10a8: comment */
 981   { "cdisp10a8", MEP_OPERAND_CDISP10A8, HW_H_SINT, 22, 10,
 982     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
 983     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 984 /* zero: Zero operand */
 985   { "zero", MEP_OPERAND_ZERO, HW_H_SINT, 0, 0,
 986     { 0, { (const PTR) 0 } },
 987     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 988 /* rl5: register Rl c5 */
 989   { "rl5", MEP_OPERAND_RL5, HW_H_GPR, 20, 4,
 990     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RL5] } },
 991     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 992 /* cdisp12: copro addend (12 bits) */
 993   { "cdisp12", MEP_OPERAND_CDISP12, HW_H_SINT, 20, 12,
 994     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_12S20] } },
 995     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 996 /* c5rmuimm20: 20-bit immediate in rm and imm16 */
 997   { "c5rmuimm20", MEP_OPERAND_C5RMUIMM20, HW_H_UINT, 8, 20,
 998     { 2, { (const PTR) &MEP_F_C5_RMUIMM20_MULTI_IFIELD[0] } },
 999     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1000 /* c5rnmuimm24: 24-bit immediate in rn, rm, and imm16 */
1001   { "c5rnmuimm24", MEP_OPERAND_C5RNMUIMM24, HW_H_UINT, 4, 24,
1002     { 2, { (const PTR) &MEP_F_C5_RNMUIMM24_MULTI_IFIELD[0] } },
1003     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1004 /* cp_flag: branch condition register */
1005   { "cp_flag", MEP_OPERAND_CP_FLAG, HW_H_CCR, 0, 0,
1006     { 0, { (const PTR) 0 } },
1007     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1008 /* sentinel */
1009   { 0, 0, 0, 0, 0,
1010     { 0, { (const PTR) 0 } },
1011     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }
1012 };
1013
1014 #undef A
1015
1016
1017 /* The instruction table.  */
1018
1019 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1020 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1021 #define A(a) (1 << CGEN_INSN_##a)
1022 #else
1023 #define A(a) (1 << CGEN_INSN_/**/a)
1024 #endif
1025
1026 static const CGEN_IBASE mep_cgen_insn_table[MAX_INSNS] =
1027 {
1028   /* Special null first entry.
1029      A `num' value of zero is thus invalid.
1030      Also, the special `invalid' insn resides here.  */
1031   { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } },
1032 /* stcb $rn,($rma) */
1033   {
1034     MEP_INSN_STCB_R, "stcb_r", "stcb", 16,
1035     { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1036   },
1037 /* ldcb $rn,($rma) */
1038   {
1039     MEP_INSN_LDCB_R, "ldcb_r", "ldcb", 16,
1040     { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } } } }
1041   },
1042 /* pref $cimm4,($rma) */
1043   {
1044     MEP_INSN_PREF, "pref", "pref", 16,
1045     { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1046   },
1047 /* pref $cimm4,$sdisp16($rma) */
1048   {
1049     MEP_INSN_PREFD, "prefd", "pref", 32,
1050     { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1051   },
1052 /* casb3 $rl5,$rn,($rm) */
1053   {
1054     MEP_INSN_CASB3, "casb3", "casb3", 32,
1055     { 0|A(OPTIONAL_BIT_INSN)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1056   },
1057 /* cash3 $rl5,$rn,($rm) */
1058   {
1059     MEP_INSN_CASH3, "cash3", "cash3", 32,
1060     { 0|A(OPTIONAL_BIT_INSN)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1061   },
1062 /* casw3 $rl5,$rn,($rm) */
1063   {
1064     MEP_INSN_CASW3, "casw3", "casw3", 32,
1065     { 0|A(OPTIONAL_BIT_INSN)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1066   },
1067 /* sbcp $crn,$cdisp12($rma) */
1068   {
1069     MEP_INSN_SBCP, "sbcp", "sbcp", 32,
1070     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1071   },
1072 /* lbcp $crn,$cdisp12($rma) */
1073   {
1074     MEP_INSN_LBCP, "lbcp", "lbcp", 32,
1075     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1076   },
1077 /* lbucp $crn,$cdisp12($rma) */
1078   {
1079     MEP_INSN_LBUCP, "lbucp", "lbucp", 32,
1080     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1081   },
1082 /* shcp $crn,$cdisp12($rma) */
1083   {
1084     MEP_INSN_SHCP, "shcp", "shcp", 32,
1085     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1086   },
1087 /* lhcp $crn,$cdisp12($rma) */
1088   {
1089     MEP_INSN_LHCP, "lhcp", "lhcp", 32,
1090     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1091   },
1092 /* lhucp $crn,$cdisp12($rma) */
1093   {
1094     MEP_INSN_LHUCP, "lhucp", "lhucp", 32,
1095     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1096   },
1097 /* lbucpa $crn,($rma+),$cdisp10 */
1098   {
1099     MEP_INSN_LBUCPA, "lbucpa", "lbucpa", 32,
1100     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1101   },
1102 /* lhucpa $crn,($rma+),$cdisp10a2 */
1103   {
1104     MEP_INSN_LHUCPA, "lhucpa", "lhucpa", 32,
1105     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1106   },
1107 /* lbucpm0 $crn,($rma+),$cdisp10 */
1108   {
1109     MEP_INSN_LBUCPM0, "lbucpm0", "lbucpm0", 32,
1110     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1111   },
1112 /* lhucpm0 $crn,($rma+),$cdisp10a2 */
1113   {
1114     MEP_INSN_LHUCPM0, "lhucpm0", "lhucpm0", 32,
1115     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1116   },
1117 /* lbucpm1 $crn,($rma+),$cdisp10 */
1118   {
1119     MEP_INSN_LBUCPM1, "lbucpm1", "lbucpm1", 32,
1120     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1121   },
1122 /* lhucpm1 $crn,($rma+),$cdisp10a2 */
1123   {
1124     MEP_INSN_LHUCPM1, "lhucpm1", "lhucpm1", 32,
1125     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1126   },
1127 /* uci $rn,$rm,$uimm16 */
1128   {
1129     MEP_INSN_UCI, "uci", "uci", 32,
1130     { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1131   },
1132 /* dsp $rn,$rm,$uimm16 */
1133   {
1134     MEP_INSN_DSP, "dsp", "dsp", 32,
1135     { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1136   },
1137 /* sb $rnc,($rma) */
1138   {
1139     MEP_INSN_SB, "sb", "sb", 16,
1140     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1141   },
1142 /* sh $rns,($rma) */
1143   {
1144     MEP_INSN_SH, "sh", "sh", 16,
1145     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1146   },
1147 /* sw $rnl,($rma) */
1148   {
1149     MEP_INSN_SW, "sw", "sw", 16,
1150     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1151   },
1152 /* lb $rnc,($rma) */
1153   {
1154     MEP_INSN_LB, "lb", "lb", 16,
1155     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1156   },
1157 /* lh $rns,($rma) */
1158   {
1159     MEP_INSN_LH, "lh", "lh", 16,
1160     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1161   },
1162 /* lw $rnl,($rma) */
1163   {
1164     MEP_INSN_LW, "lw", "lw", 16,
1165     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1166   },
1167 /* lbu $rnuc,($rma) */
1168   {
1169     MEP_INSN_LBU, "lbu", "lbu", 16,
1170     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1171   },
1172 /* lhu $rnus,($rma) */
1173   {
1174     MEP_INSN_LHU, "lhu", "lhu", 16,
1175     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1176   },
1177 /* sw $rnl,$udisp7a4($spr) */
1178   {
1179     MEP_INSN_SW_SP, "sw-sp", "sw", 16,
1180     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1181   },
1182 /* lw $rnl,$udisp7a4($spr) */
1183   {
1184     MEP_INSN_LW_SP, "lw-sp", "lw", 16,
1185     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1186   },
1187 /* sb $rn3c,$udisp7($tpr) */
1188   {
1189     MEP_INSN_SB_TP, "sb-tp", "sb", 16,
1190     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1191   },
1192 /* sh $rn3s,$udisp7a2($tpr) */
1193   {
1194     MEP_INSN_SH_TP, "sh-tp", "sh", 16,
1195     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1196   },
1197 /* sw $rn3l,$udisp7a4($tpr) */
1198   {
1199     MEP_INSN_SW_TP, "sw-tp", "sw", 16,
1200     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1201   },
1202 /* lb $rn3c,$udisp7($tpr) */
1203   {
1204     MEP_INSN_LB_TP, "lb-tp", "lb", 16,
1205     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1206   },
1207 /* lh $rn3s,$udisp7a2($tpr) */
1208   {
1209     MEP_INSN_LH_TP, "lh-tp", "lh", 16,
1210     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1211   },
1212 /* lw $rn3l,$udisp7a4($tpr) */
1213   {
1214     MEP_INSN_LW_TP, "lw-tp", "lw", 16,
1215     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1216   },
1217 /* lbu $rn3uc,$udisp7($tpr) */
1218   {
1219     MEP_INSN_LBU_TP, "lbu-tp", "lbu", 16,
1220     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1221   },
1222 /* lhu $rn3us,$udisp7a2($tpr) */
1223   {
1224     MEP_INSN_LHU_TP, "lhu-tp", "lhu", 16,
1225     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1226   },
1227 /* sb $rnc,$sdisp16($rma) */
1228   {
1229     MEP_INSN_SB16, "sb16", "sb", 32,
1230     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1231   },
1232 /* sh $rns,$sdisp16($rma) */
1233   {
1234     MEP_INSN_SH16, "sh16", "sh", 32,
1235     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1236   },
1237 /* sw $rnl,$sdisp16($rma) */
1238   {
1239     MEP_INSN_SW16, "sw16", "sw", 32,
1240     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1241   },
1242 /* lb $rnc,$sdisp16($rma) */
1243   {
1244     MEP_INSN_LB16, "lb16", "lb", 32,
1245     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1246   },
1247 /* lh $rns,$sdisp16($rma) */
1248   {
1249     MEP_INSN_LH16, "lh16", "lh", 32,
1250     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1251   },
1252 /* lw $rnl,$sdisp16($rma) */
1253   {
1254     MEP_INSN_LW16, "lw16", "lw", 32,
1255     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1256   },
1257 /* lbu $rnuc,$sdisp16($rma) */
1258   {
1259     MEP_INSN_LBU16, "lbu16", "lbu", 32,
1260     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1261   },
1262 /* lhu $rnus,$sdisp16($rma) */
1263   {
1264     MEP_INSN_LHU16, "lhu16", "lhu", 32,
1265     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1266   },
1267 /* sw $rnl,($addr24a4) */
1268   {
1269     MEP_INSN_SW24, "sw24", "sw", 32,
1270     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1271   },
1272 /* lw $rnl,($addr24a4) */
1273   {
1274     MEP_INSN_LW24, "lw24", "lw", 32,
1275     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1276   },
1277 /* extb $rn */
1278   {
1279     MEP_INSN_EXTB, "extb", "extb", 16,
1280     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1281   },
1282 /* exth $rn */
1283   {
1284     MEP_INSN_EXTH, "exth", "exth", 16,
1285     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1286   },
1287 /* extub $rn */
1288   {
1289     MEP_INSN_EXTUB, "extub", "extub", 16,
1290     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1291   },
1292 /* extuh $rn */
1293   {
1294     MEP_INSN_EXTUH, "extuh", "extuh", 16,
1295     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1296   },
1297 /* ssarb $udisp2($rm) */
1298   {
1299     MEP_INSN_SSARB, "ssarb", "ssarb", 16,
1300     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1301   },
1302 /* mov $rn,$rm */
1303   {
1304     MEP_INSN_MOV, "mov", "mov", 16,
1305     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1306   },
1307 /* mov $rn,$simm8 */
1308   {
1309     MEP_INSN_MOVI8, "movi8", "mov", 16,
1310     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1311   },
1312 /* mov $rn,$simm16 */
1313   {
1314     MEP_INSN_MOVI16, "movi16", "mov", 32,
1315     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1316   },
1317 /* movu $rn3,$uimm24 */
1318   {
1319     MEP_INSN_MOVU24, "movu24", "movu", 32,
1320     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1321   },
1322 /* movu $rn,$uimm16 */
1323   {
1324     MEP_INSN_MOVU16, "movu16", "movu", 32,
1325     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1326   },
1327 /* movh $rn,$uimm16 */
1328   {
1329     MEP_INSN_MOVH, "movh", "movh", 32,
1330     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1331   },
1332 /* add3 $rl,$rn,$rm */
1333   {
1334     MEP_INSN_ADD3, "add3", "add3", 16,
1335     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1336   },
1337 /* add $rn,$simm6 */
1338   {
1339     MEP_INSN_ADD, "add", "add", 16,
1340     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1341   },
1342 /* add3 $rn,$spr,$uimm7a4 */
1343   {
1344     MEP_INSN_ADD3I, "add3i", "add3", 16,
1345     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1346   },
1347 /* advck3 \$0,$rn,$rm */
1348   {
1349     MEP_INSN_ADVCK3, "advck3", "advck3", 16,
1350     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1351   },
1352 /* sub $rn,$rm */
1353   {
1354     MEP_INSN_SUB, "sub", "sub", 16,
1355     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1356   },
1357 /* sbvck3 \$0,$rn,$rm */
1358   {
1359     MEP_INSN_SBVCK3, "sbvck3", "sbvck3", 16,
1360     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1361   },
1362 /* neg $rn,$rm */
1363   {
1364     MEP_INSN_NEG, "neg", "neg", 16,
1365     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1366   },
1367 /* slt3 \$0,$rn,$rm */
1368   {
1369     MEP_INSN_SLT3, "slt3", "slt3", 16,
1370     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1371   },
1372 /* sltu3 \$0,$rn,$rm */
1373   {
1374     MEP_INSN_SLTU3, "sltu3", "sltu3", 16,
1375     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1376   },
1377 /* slt3 \$0,$rn,$uimm5 */
1378   {
1379     MEP_INSN_SLT3I, "slt3i", "slt3", 16,
1380     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1381   },
1382 /* sltu3 \$0,$rn,$uimm5 */
1383   {
1384     MEP_INSN_SLTU3I, "sltu3i", "sltu3", 16,
1385     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1386   },
1387 /* sl1ad3 \$0,$rn,$rm */
1388   {
1389     MEP_INSN_SL1AD3, "sl1ad3", "sl1ad3", 16,
1390     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1391   },
1392 /* sl2ad3 \$0,$rn,$rm */
1393   {
1394     MEP_INSN_SL2AD3, "sl2ad3", "sl2ad3", 16,
1395     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1396   },
1397 /* add3 $rn,$rm,$simm16 */
1398   {
1399     MEP_INSN_ADD3X, "add3x", "add3", 32,
1400     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1401   },
1402 /* slt3 $rn,$rm,$simm16 */
1403   {
1404     MEP_INSN_SLT3X, "slt3x", "slt3", 32,
1405     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1406   },
1407 /* sltu3 $rn,$rm,$uimm16 */
1408   {
1409     MEP_INSN_SLTU3X, "sltu3x", "sltu3", 32,
1410     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1411   },
1412 /* or $rn,$rm */
1413   {
1414     MEP_INSN_OR, "or", "or", 16,
1415     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1416   },
1417 /* and $rn,$rm */
1418   {
1419     MEP_INSN_AND, "and", "and", 16,
1420     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1421   },
1422 /* xor $rn,$rm */
1423   {
1424     MEP_INSN_XOR, "xor", "xor", 16,
1425     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1426   },
1427 /* nor $rn,$rm */
1428   {
1429     MEP_INSN_NOR, "nor", "nor", 16,
1430     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1431   },
1432 /* or3 $rn,$rm,$uimm16 */
1433   {
1434     MEP_INSN_OR3, "or3", "or3", 32,
1435     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1436   },
1437 /* and3 $rn,$rm,$uimm16 */
1438   {
1439     MEP_INSN_AND3, "and3", "and3", 32,
1440     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1441   },
1442 /* xor3 $rn,$rm,$uimm16 */
1443   {
1444     MEP_INSN_XOR3, "xor3", "xor3", 32,
1445     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1446   },
1447 /* sra $rn,$rm */
1448   {
1449     MEP_INSN_SRA, "sra", "sra", 16,
1450     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1451   },
1452 /* srl $rn,$rm */
1453   {
1454     MEP_INSN_SRL, "srl", "srl", 16,
1455     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1456   },
1457 /* sll $rn,$rm */
1458   {
1459     MEP_INSN_SLL, "sll", "sll", 16,
1460     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1461   },
1462 /* sra $rn,$uimm5 */
1463   {
1464     MEP_INSN_SRAI, "srai", "sra", 16,
1465     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1466   },
1467 /* srl $rn,$uimm5 */
1468   {
1469     MEP_INSN_SRLI, "srli", "srl", 16,
1470     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1471   },
1472 /* sll $rn,$uimm5 */
1473   {
1474     MEP_INSN_SLLI, "slli", "sll", 16,
1475     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1476   },
1477 /* sll3 \$0,$rn,$uimm5 */
1478   {
1479     MEP_INSN_SLL3, "sll3", "sll3", 16,
1480     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1481   },
1482 /* fsft $rn,$rm */
1483   {
1484     MEP_INSN_FSFT, "fsft", "fsft", 16,
1485     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1486   },
1487 /* bra $pcrel12a2 */
1488   {
1489     MEP_INSN_BRA, "bra", "bra", 16,
1490     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1491   },
1492 /* beqz $rn,$pcrel8a2 */
1493   {
1494     MEP_INSN_BEQZ, "beqz", "beqz", 16,
1495     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1496   },
1497 /* bnez $rn,$pcrel8a2 */
1498   {
1499     MEP_INSN_BNEZ, "bnez", "bnez", 16,
1500     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1501   },
1502 /* beqi $rn,$uimm4,$pcrel17a2 */
1503   {
1504     MEP_INSN_BEQI, "beqi", "beqi", 32,
1505     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1506   },
1507 /* bnei $rn,$uimm4,$pcrel17a2 */
1508   {
1509     MEP_INSN_BNEI, "bnei", "bnei", 32,
1510     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1511   },
1512 /* blti $rn,$uimm4,$pcrel17a2 */
1513   {
1514     MEP_INSN_BLTI, "blti", "blti", 32,
1515     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1516   },
1517 /* bgei $rn,$uimm4,$pcrel17a2 */
1518   {
1519     MEP_INSN_BGEI, "bgei", "bgei", 32,
1520     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1521   },
1522 /* beq $rn,$rm,$pcrel17a2 */
1523   {
1524     MEP_INSN_BEQ, "beq", "beq", 32,
1525     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1526   },
1527 /* bne $rn,$rm,$pcrel17a2 */
1528   {
1529     MEP_INSN_BNE, "bne", "bne", 32,
1530     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1531   },
1532 /* bsr $pcrel12a2 */
1533   {
1534     MEP_INSN_BSR12, "bsr12", "bsr", 16,
1535     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1536   },
1537 /* bsr $pcrel24a2 */
1538   {
1539     MEP_INSN_BSR24, "bsr24", "bsr", 32,
1540     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1541   },
1542 /* jmp $rm */
1543   {
1544     MEP_INSN_JMP, "jmp", "jmp", 16,
1545     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1546   },
1547 /* jmp $pcabs24a2 */
1548   {
1549     MEP_INSN_JMP24, "jmp24", "jmp", 32,
1550     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1551   },
1552 /* jsr $rm */
1553   {
1554     MEP_INSN_JSR, "jsr", "jsr", 16,
1555     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1556   },
1557 /* ret */
1558   {
1559     MEP_INSN_RET, "ret", "ret", 16,
1560     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1561   },
1562 /* repeat $rn,$pcrel17a2 */
1563   {
1564     MEP_INSN_REPEAT, "repeat", "repeat", 32,
1565     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1566   },
1567 /* erepeat $pcrel17a2 */
1568   {
1569     MEP_INSN_EREPEAT, "erepeat", "erepeat", 32,
1570     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1571   },
1572 /* stc $rn,\$lp */
1573   {
1574     MEP_INSN_STC_LP, "stc_lp", "stc", 16,
1575     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1576   },
1577 /* stc $rn,\$hi */
1578   {
1579     MEP_INSN_STC_HI, "stc_hi", "stc", 16,
1580     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1581   },
1582 /* stc $rn,\$lo */
1583   {
1584     MEP_INSN_STC_LO, "stc_lo", "stc", 16,
1585     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1586   },
1587 /* stc $rn,$csrn */
1588   {
1589     MEP_INSN_STC, "stc", "stc", 16,
1590     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1591   },
1592 /* ldc $rn,\$lp */
1593   {
1594     MEP_INSN_LDC_LP, "ldc_lp", "ldc", 16,
1595     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1596   },
1597 /* ldc $rn,\$hi */
1598   {
1599     MEP_INSN_LDC_HI, "ldc_hi", "ldc", 16,
1600     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1601   },
1602 /* ldc $rn,\$lo */
1603   {
1604     MEP_INSN_LDC_LO, "ldc_lo", "ldc", 16,
1605     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1606   },
1607 /* ldc $rn,$csrn */
1608   {
1609     MEP_INSN_LDC, "ldc", "ldc", 16,
1610     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1611   },
1612 /* di */
1613   {
1614     MEP_INSN_DI, "di", "di", 16,
1615     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1616   },
1617 /* ei */
1618   {
1619     MEP_INSN_EI, "ei", "ei", 16,
1620     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1621   },
1622 /* reti */
1623   {
1624     MEP_INSN_RETI, "reti", "reti", 16,
1625     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1626   },
1627 /* halt */
1628   {
1629     MEP_INSN_HALT, "halt", "halt", 16,
1630     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1631   },
1632 /* sleep */
1633   {
1634     MEP_INSN_SLEEP, "sleep", "sleep", 16,
1635     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1636   },
1637 /* swi $uimm2 */
1638   {
1639     MEP_INSN_SWI, "swi", "swi", 16,
1640     { 0|A(VOLATILE)|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1641   },
1642 /* break */
1643   {
1644     MEP_INSN_BREAK, "break", "break", 16,
1645     { 0|A(VOLATILE)|A(MAY_TRAP)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1646   },
1647 /* syncm */
1648   {
1649     MEP_INSN_SYNCM, "syncm", "syncm", 16,
1650     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1651   },
1652 /* stcb $rn,$uimm16 */
1653   {
1654     MEP_INSN_STCB, "stcb", "stcb", 32,
1655     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1656   },
1657 /* ldcb $rn,$uimm16 */
1658   {
1659     MEP_INSN_LDCB, "ldcb", "ldcb", 32,
1660     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } } } }
1661   },
1662 /* bsetm ($rma),$uimm3 */
1663   {
1664     MEP_INSN_BSETM, "bsetm", "bsetm", 16,
1665     { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1666   },
1667 /* bclrm ($rma),$uimm3 */
1668   {
1669     MEP_INSN_BCLRM, "bclrm", "bclrm", 16,
1670     { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1671   },
1672 /* bnotm ($rma),$uimm3 */
1673   {
1674     MEP_INSN_BNOTM, "bnotm", "bnotm", 16,
1675     { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1676   },
1677 /* btstm \$0,($rma),$uimm3 */
1678   {
1679     MEP_INSN_BTSTM, "btstm", "btstm", 16,
1680     { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1681   },
1682 /* tas $rn,($rma) */
1683   {
1684     MEP_INSN_TAS, "tas", "tas", 16,
1685     { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1686   },
1687 /* cache $cimm4,($rma) */
1688   {
1689     MEP_INSN_CACHE, "cache", "cache", 16,
1690     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1691   },
1692 /* mul $rn,$rm */
1693   {
1694     MEP_INSN_MUL, "mul", "mul", 16,
1695     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1696   },
1697 /* mulu $rn,$rm */
1698   {
1699     MEP_INSN_MULU, "mulu", "mulu", 16,
1700     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1701   },
1702 /* mulr $rn,$rm */
1703   {
1704     MEP_INSN_MULR, "mulr", "mulr", 16,
1705     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } } } }
1706   },
1707 /* mulru $rn,$rm */
1708   {
1709     MEP_INSN_MULRU, "mulru", "mulru", 16,
1710     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } } } }
1711   },
1712 /* madd $rn,$rm */
1713   {
1714     MEP_INSN_MADD, "madd", "madd", 32,
1715     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1716   },
1717 /* maddu $rn,$rm */
1718   {
1719     MEP_INSN_MADDU, "maddu", "maddu", 32,
1720     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1721   },
1722 /* maddr $rn,$rm */
1723   {
1724     MEP_INSN_MADDR, "maddr", "maddr", 32,
1725     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } } } }
1726   },
1727 /* maddru $rn,$rm */
1728   {
1729     MEP_INSN_MADDRU, "maddru", "maddru", 32,
1730     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } } } }
1731   },
1732 /* div $rn,$rm */
1733   {
1734     MEP_INSN_DIV, "div", "div", 16,
1735     { 0|A(MAY_TRAP)|A(OPTIONAL_DIV_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 34, 0 } }, { { CONFIG_NONE, 0 } } } }
1736   },
1737 /* divu $rn,$rm */
1738   {
1739     MEP_INSN_DIVU, "divu", "divu", 16,
1740     { 0|A(MAY_TRAP)|A(OPTIONAL_DIV_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 34, 0 } }, { { CONFIG_NONE, 0 } } } }
1741   },
1742 /* dret */
1743   {
1744     MEP_INSN_DRET, "dret", "dret", 16,
1745     { 0|A(OPTIONAL_DEBUG_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1746   },
1747 /* dbreak */
1748   {
1749     MEP_INSN_DBREAK, "dbreak", "dbreak", 16,
1750     { 0|A(VOLATILE)|A(MAY_TRAP)|A(OPTIONAL_DEBUG_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1751   },
1752 /* ldz $rn,$rm */
1753   {
1754     MEP_INSN_LDZ, "ldz", "ldz", 32,
1755     { 0|A(OPTIONAL_LDZ_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1756   },
1757 /* abs $rn,$rm */
1758   {
1759     MEP_INSN_ABS, "abs", "abs", 32,
1760     { 0|A(OPTIONAL_ABS_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1761   },
1762 /* ave $rn,$rm */
1763   {
1764     MEP_INSN_AVE, "ave", "ave", 32,
1765     { 0|A(OPTIONAL_AVE_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1766   },
1767 /* min $rn,$rm */
1768   {
1769     MEP_INSN_MIN, "min", "min", 32,
1770     { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1771   },
1772 /* max $rn,$rm */
1773   {
1774     MEP_INSN_MAX, "max", "max", 32,
1775     { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1776   },
1777 /* minu $rn,$rm */
1778   {
1779     MEP_INSN_MINU, "minu", "minu", 32,
1780     { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1781   },
1782 /* maxu $rn,$rm */
1783   {
1784     MEP_INSN_MAXU, "maxu", "maxu", 32,
1785     { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1786   },
1787 /* clip $rn,$cimm5 */
1788   {
1789     MEP_INSN_CLIP, "clip", "clip", 32,
1790     { 0|A(OPTIONAL_CLIP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1791   },
1792 /* clipu $rn,$cimm5 */
1793   {
1794     MEP_INSN_CLIPU, "clipu", "clipu", 32,
1795     { 0|A(OPTIONAL_CLIP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1796   },
1797 /* sadd $rn,$rm */
1798   {
1799     MEP_INSN_SADD, "sadd", "sadd", 32,
1800     { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1801   },
1802 /* ssub $rn,$rm */
1803   {
1804     MEP_INSN_SSUB, "ssub", "ssub", 32,
1805     { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1806   },
1807 /* saddu $rn,$rm */
1808   {
1809     MEP_INSN_SADDU, "saddu", "saddu", 32,
1810     { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1811   },
1812 /* ssubu $rn,$rm */
1813   {
1814     MEP_INSN_SSUBU, "ssubu", "ssubu", 32,
1815     { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1816   },
1817 /* swcp $crn,($rma) */
1818   {
1819     MEP_INSN_SWCP, "swcp", "swcp", 16,
1820     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1821   },
1822 /* lwcp $crn,($rma) */
1823   {
1824     MEP_INSN_LWCP, "lwcp", "lwcp", 16,
1825     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1826   },
1827 /* smcp $crn64,($rma) */
1828   {
1829     MEP_INSN_SMCP, "smcp", "smcp", 16,
1830     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1831   },
1832 /* lmcp $crn64,($rma) */
1833   {
1834     MEP_INSN_LMCP, "lmcp", "lmcp", 16,
1835     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1836   },
1837 /* swcpi $crn,($rma+) */
1838   {
1839     MEP_INSN_SWCPI, "swcpi", "swcpi", 16,
1840     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1841   },
1842 /* lwcpi $crn,($rma+) */
1843   {
1844     MEP_INSN_LWCPI, "lwcpi", "lwcpi", 16,
1845     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1846   },
1847 /* smcpi $crn64,($rma+) */
1848   {
1849     MEP_INSN_SMCPI, "smcpi", "smcpi", 16,
1850     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1851   },
1852 /* lmcpi $crn64,($rma+) */
1853   {
1854     MEP_INSN_LMCPI, "lmcpi", "lmcpi", 16,
1855     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1856   },
1857 /* swcp $crn,$sdisp16($rma) */
1858   {
1859     MEP_INSN_SWCP16, "swcp16", "swcp", 32,
1860     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1861   },
1862 /* lwcp $crn,$sdisp16($rma) */
1863   {
1864     MEP_INSN_LWCP16, "lwcp16", "lwcp", 32,
1865     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1866   },
1867 /* smcp $crn64,$sdisp16($rma) */
1868   {
1869     MEP_INSN_SMCP16, "smcp16", "smcp", 32,
1870     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1871   },
1872 /* lmcp $crn64,$sdisp16($rma) */
1873   {
1874     MEP_INSN_LMCP16, "lmcp16", "lmcp", 32,
1875     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1876   },
1877 /* sbcpa $crn,($rma+),$cdisp10 */
1878   {
1879     MEP_INSN_SBCPA, "sbcpa", "sbcpa", 32,
1880     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1881   },
1882 /* lbcpa $crn,($rma+),$cdisp10 */
1883   {
1884     MEP_INSN_LBCPA, "lbcpa", "lbcpa", 32,
1885     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1886   },
1887 /* shcpa $crn,($rma+),$cdisp10a2 */
1888   {
1889     MEP_INSN_SHCPA, "shcpa", "shcpa", 32,
1890     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1891   },
1892 /* lhcpa $crn,($rma+),$cdisp10a2 */
1893   {
1894     MEP_INSN_LHCPA, "lhcpa", "lhcpa", 32,
1895     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1896   },
1897 /* swcpa $crn,($rma+),$cdisp10a4 */
1898   {
1899     MEP_INSN_SWCPA, "swcpa", "swcpa", 32,
1900     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1901   },
1902 /* lwcpa $crn,($rma+),$cdisp10a4 */
1903   {
1904     MEP_INSN_LWCPA, "lwcpa", "lwcpa", 32,
1905     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1906   },
1907 /* smcpa $crn64,($rma+),$cdisp10a8 */
1908   {
1909     MEP_INSN_SMCPA, "smcpa", "smcpa", 32,
1910     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1911   },
1912 /* lmcpa $crn64,($rma+),$cdisp10a8 */
1913   {
1914     MEP_INSN_LMCPA, "lmcpa", "lmcpa", 32,
1915     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1916   },
1917 /* sbcpm0 $crn,($rma+),$cdisp10 */
1918   {
1919     MEP_INSN_SBCPM0, "sbcpm0", "sbcpm0", 32,
1920     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1921   },
1922 /* lbcpm0 $crn,($rma+),$cdisp10 */
1923   {
1924     MEP_INSN_LBCPM0, "lbcpm0", "lbcpm0", 32,
1925     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1926   },
1927 /* shcpm0 $crn,($rma+),$cdisp10a2 */
1928   {
1929     MEP_INSN_SHCPM0, "shcpm0", "shcpm0", 32,
1930     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1931   },
1932 /* lhcpm0 $crn,($rma+),$cdisp10a2 */
1933   {
1934     MEP_INSN_LHCPM0, "lhcpm0", "lhcpm0", 32,
1935     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1936   },
1937 /* swcpm0 $crn,($rma+),$cdisp10a4 */
1938   {
1939     MEP_INSN_SWCPM0, "swcpm0", "swcpm0", 32,
1940     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1941   },
1942 /* lwcpm0 $crn,($rma+),$cdisp10a4 */
1943   {
1944     MEP_INSN_LWCPM0, "lwcpm0", "lwcpm0", 32,
1945     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1946   },
1947 /* smcpm0 $crn64,($rma+),$cdisp10a8 */
1948   {
1949     MEP_INSN_SMCPM0, "smcpm0", "smcpm0", 32,
1950     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1951   },
1952 /* lmcpm0 $crn64,($rma+),$cdisp10a8 */
1953   {
1954     MEP_INSN_LMCPM0, "lmcpm0", "lmcpm0", 32,
1955     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1956   },
1957 /* sbcpm1 $crn,($rma+),$cdisp10 */
1958   {
1959     MEP_INSN_SBCPM1, "sbcpm1", "sbcpm1", 32,
1960     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1961   },
1962 /* lbcpm1 $crn,($rma+),$cdisp10 */
1963   {
1964     MEP_INSN_LBCPM1, "lbcpm1", "lbcpm1", 32,
1965     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1966   },
1967 /* shcpm1 $crn,($rma+),$cdisp10a2 */
1968   {
1969     MEP_INSN_SHCPM1, "shcpm1", "shcpm1", 32,
1970     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1971   },
1972 /* lhcpm1 $crn,($rma+),$cdisp10a2 */
1973   {
1974     MEP_INSN_LHCPM1, "lhcpm1", "lhcpm1", 32,
1975     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1976   },
1977 /* swcpm1 $crn,($rma+),$cdisp10a4 */
1978   {
1979     MEP_INSN_SWCPM1, "swcpm1", "swcpm1", 32,
1980     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1981   },
1982 /* lwcpm1 $crn,($rma+),$cdisp10a4 */
1983   {
1984     MEP_INSN_LWCPM1, "lwcpm1", "lwcpm1", 32,
1985     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1986   },
1987 /* smcpm1 $crn64,($rma+),$cdisp10a8 */
1988   {
1989     MEP_INSN_SMCPM1, "smcpm1", "smcpm1", 32,
1990     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1991   },
1992 /* lmcpm1 $crn64,($rma+),$cdisp10a8 */
1993   {
1994     MEP_INSN_LMCPM1, "lmcpm1", "lmcpm1", 32,
1995     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1996   },
1997 /* bcpeq $cccc,$pcrel17a2 */
1998   {
1999     MEP_INSN_BCPEQ, "bcpeq", "bcpeq", 32,
2000     { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2001   },
2002 /* bcpne $cccc,$pcrel17a2 */
2003   {
2004     MEP_INSN_BCPNE, "bcpne", "bcpne", 32,
2005     { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2006   },
2007 /* bcpat $cccc,$pcrel17a2 */
2008   {
2009     MEP_INSN_BCPAT, "bcpat", "bcpat", 32,
2010     { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2011   },
2012 /* bcpaf $cccc,$pcrel17a2 */
2013   {
2014     MEP_INSN_BCPAF, "bcpaf", "bcpaf", 32,
2015     { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2016   },
2017 /* synccp */
2018   {
2019     MEP_INSN_SYNCCP, "synccp", "synccp", 16,
2020     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2021   },
2022 /* jsrv $rm */
2023   {
2024     MEP_INSN_JSRV, "jsrv", "jsrv", 16,
2025     { 0|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2026   },
2027 /* bsrv $pcrel24a2 */
2028   {
2029     MEP_INSN_BSRV, "bsrv", "bsrv", 32,
2030     { 0|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2031   },
2032 /* --unused-- */
2033   {
2034     MEP_INSN_SIM_SYSCALL, "sim-syscall", "--unused--", 16,
2035     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2036   },
2037 /* --reserved-- */
2038   {
2039     MEP_INSN_RI_0, "ri-0", "--reserved--", 16,
2040     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2041   },
2042 /* --reserved-- */
2043   {
2044     MEP_INSN_RI_1, "ri-1", "--reserved--", 16,
2045     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2046   },
2047 /* --reserved-- */
2048   {
2049     MEP_INSN_RI_2, "ri-2", "--reserved--", 16,
2050     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2051   },
2052 /* --reserved-- */
2053   {
2054     MEP_INSN_RI_3, "ri-3", "--reserved--", 16,
2055     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2056   },
2057 /* --reserved-- */
2058   {
2059     MEP_INSN_RI_4, "ri-4", "--reserved--", 16,
2060     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2061   },
2062 /* --reserved-- */
2063   {
2064     MEP_INSN_RI_5, "ri-5", "--reserved--", 16,
2065     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2066   },
2067 /* --reserved-- */
2068   {
2069     MEP_INSN_RI_6, "ri-6", "--reserved--", 16,
2070     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2071   },
2072 /* --reserved-- */
2073   {
2074     MEP_INSN_RI_7, "ri-7", "--reserved--", 16,
2075     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2076   },
2077 /* --reserved-- */
2078   {
2079     MEP_INSN_RI_8, "ri-8", "--reserved--", 16,
2080     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2081   },
2082 /* --reserved-- */
2083   {
2084     MEP_INSN_RI_9, "ri-9", "--reserved--", 16,
2085     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2086   },
2087 /* --reserved-- */
2088   {
2089     MEP_INSN_RI_10, "ri-10", "--reserved--", 16,
2090     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2091   },
2092 /* --reserved-- */
2093   {
2094     MEP_INSN_RI_11, "ri-11", "--reserved--", 16,
2095     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2096   },
2097 /* --reserved-- */
2098   {
2099     MEP_INSN_RI_12, "ri-12", "--reserved--", 16,
2100     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2101   },
2102 /* --reserved-- */
2103   {
2104     MEP_INSN_RI_13, "ri-13", "--reserved--", 16,
2105     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2106   },
2107 /* --reserved-- */
2108   {
2109     MEP_INSN_RI_14, "ri-14", "--reserved--", 16,
2110     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2111   },
2112 /* --reserved-- */
2113   {
2114     MEP_INSN_RI_15, "ri-15", "--reserved--", 16,
2115     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2116   },
2117 /* --reserved-- */
2118   {
2119     MEP_INSN_RI_17, "ri-17", "--reserved--", 16,
2120     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2121   },
2122 /* --reserved-- */
2123   {
2124     MEP_INSN_RI_20, "ri-20", "--reserved--", 16,
2125     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2126   },
2127 /* --reserved-- */
2128   {
2129     MEP_INSN_RI_21, "ri-21", "--reserved--", 16,
2130     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2131   },
2132 /* --reserved-- */
2133   {
2134     MEP_INSN_RI_22, "ri-22", "--reserved--", 16,
2135     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2136   },
2137 /* --reserved-- */
2138   {
2139     MEP_INSN_RI_23, "ri-23", "--reserved--", 16,
2140     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2141   },
2142 /* --reserved-- */
2143   {
2144     MEP_INSN_RI_26, "ri-26", "--reserved--", 16,
2145     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2146   },
2147 };
2148
2149 #undef OP
2150 #undef A
2151
2152 /* Initialize anything needed to be done once, before any cpu_open call.  */
2153
2154 static void
2155 init_tables (void)
2156 {
2157 }
2158
2159 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
2160 static void build_hw_table      (CGEN_CPU_TABLE *);
2161 static void build_ifield_table  (CGEN_CPU_TABLE *);
2162 static void build_operand_table (CGEN_CPU_TABLE *);
2163 static void build_insn_table    (CGEN_CPU_TABLE *);
2164 static void mep_cgen_rebuild_tables (CGEN_CPU_TABLE *);
2165
2166 /* Subroutine of mep_cgen_cpu_open to look up a mach via its bfd name.  */
2167
2168 static const CGEN_MACH *
2169 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
2170 {
2171   while (table->name)
2172     {
2173       if (strcmp (name, table->bfd_name) == 0)
2174         return table;
2175       ++table;
2176     }
2177   abort ();
2178 }
2179
2180 /* Subroutine of mep_cgen_cpu_open to build the hardware table.  */
2181
2182 static void
2183 build_hw_table (CGEN_CPU_TABLE *cd)
2184 {
2185   int i;
2186   int machs = cd->machs;
2187   const CGEN_HW_ENTRY *init = & mep_cgen_hw_table[0];
2188   /* MAX_HW is only an upper bound on the number of selected entries.
2189      However each entry is indexed by it's enum so there can be holes in
2190      the table.  */
2191   const CGEN_HW_ENTRY **selected =
2192     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
2193
2194   cd->hw_table.init_entries = init;
2195   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
2196   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
2197   /* ??? For now we just use machs to determine which ones we want.  */
2198   for (i = 0; init[i].name != NULL; ++i)
2199     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
2200         & machs)
2201       selected[init[i].type] = &init[i];
2202   cd->hw_table.entries = selected;
2203   cd->hw_table.num_entries = MAX_HW;
2204 }
2205
2206 /* Subroutine of mep_cgen_cpu_open to build the hardware table.  */
2207
2208 static void
2209 build_ifield_table (CGEN_CPU_TABLE *cd)
2210 {
2211   cd->ifld_table = & mep_cgen_ifld_table[0];
2212 }
2213
2214 /* Subroutine of mep_cgen_cpu_open to build the hardware table.  */
2215
2216 static void
2217 build_operand_table (CGEN_CPU_TABLE *cd)
2218 {
2219   int i;
2220   int machs = cd->machs;
2221   const CGEN_OPERAND *init = & mep_cgen_operand_table[0];
2222   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
2223      However each entry is indexed by it's enum so there can be holes in
2224      the table.  */
2225   const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
2226
2227   cd->operand_table.init_entries = init;
2228   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
2229   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
2230   /* ??? For now we just use mach to determine which ones we want.  */
2231   for (i = 0; init[i].name != NULL; ++i)
2232     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
2233         & machs)
2234       selected[init[i].type] = &init[i];
2235   cd->operand_table.entries = selected;
2236   cd->operand_table.num_entries = MAX_OPERANDS;
2237 }
2238
2239 /* Subroutine of mep_cgen_cpu_open to build the hardware table.
2240    ??? This could leave out insns not supported by the specified mach/isa,
2241    but that would cause errors like "foo only supported by bar" to become
2242    "unknown insn", so for now we include all insns and require the app to
2243    do the checking later.
2244    ??? On the other hand, parsing of such insns may require their hardware or
2245    operand elements to be in the table [which they mightn't be].  */
2246
2247 static void
2248 build_insn_table (CGEN_CPU_TABLE *cd)
2249 {
2250   int i;
2251   const CGEN_IBASE *ib = & mep_cgen_insn_table[0];
2252   CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
2253
2254   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
2255   for (i = 0; i < MAX_INSNS; ++i)
2256     insns[i].base = &ib[i];
2257   cd->insn_table.init_entries = insns;
2258   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
2259   cd->insn_table.num_init_entries = MAX_INSNS;
2260 }
2261
2262 /* Subroutine of mep_cgen_cpu_open to rebuild the tables.  */
2263
2264 static void
2265 mep_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
2266 {
2267   int i;
2268   CGEN_BITSET *isas = cd->isas;
2269   unsigned int machs = cd->machs;
2270
2271   cd->int_insn_p = CGEN_INT_INSN_P;
2272
2273   /* Data derived from the isa spec.  */
2274 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
2275   cd->default_insn_bitsize = UNSET;
2276   cd->base_insn_bitsize = UNSET;
2277   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
2278   cd->max_insn_bitsize = 0;
2279   for (i = 0; i < MAX_ISAS; ++i)
2280     if (cgen_bitset_contains (isas, i))
2281       {
2282         const CGEN_ISA *isa = & mep_cgen_isa_table[i];
2283
2284         /* Default insn sizes of all selected isas must be
2285            equal or we set the result to 0, meaning "unknown".  */
2286         if (cd->default_insn_bitsize == UNSET)
2287           cd->default_insn_bitsize = isa->default_insn_bitsize;
2288         else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
2289           ; /* This is ok.  */
2290         else
2291           cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
2292
2293         /* Base insn sizes of all selected isas must be equal
2294            or we set the result to 0, meaning "unknown".  */
2295         if (cd->base_insn_bitsize == UNSET)
2296           cd->base_insn_bitsize = isa->base_insn_bitsize;
2297         else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
2298           ; /* This is ok.  */
2299         else
2300           cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
2301
2302         /* Set min,max insn sizes.  */
2303         if (isa->min_insn_bitsize < cd->min_insn_bitsize)
2304           cd->min_insn_bitsize = isa->min_insn_bitsize;
2305         if (isa->max_insn_bitsize > cd->max_insn_bitsize)
2306           cd->max_insn_bitsize = isa->max_insn_bitsize;
2307       }
2308
2309   /* Data derived from the mach spec.  */
2310   for (i = 0; i < MAX_MACHS; ++i)
2311     if (((1 << i) & machs) != 0)
2312       {
2313         const CGEN_MACH *mach = & mep_cgen_mach_table[i];
2314
2315         if (mach->insn_chunk_bitsize != 0)
2316         {
2317           if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
2318             {
2319               fprintf (stderr, "mep_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
2320                        cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
2321               abort ();
2322             }
2323
2324           cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
2325         }
2326       }
2327
2328   /* Determine which hw elements are used by MACH.  */
2329   build_hw_table (cd);
2330
2331   /* Build the ifield table.  */
2332   build_ifield_table (cd);
2333
2334   /* Determine which operands are used by MACH/ISA.  */
2335   build_operand_table (cd);
2336
2337   /* Build the instruction table.  */
2338   build_insn_table (cd);
2339 }
2340
2341 /* Initialize a cpu table and return a descriptor.
2342    It's much like opening a file, and must be the first function called.
2343    The arguments are a set of (type/value) pairs, terminated with
2344    CGEN_CPU_OPEN_END.
2345
2346    Currently supported values:
2347    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
2348    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
2349    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
2350    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
2351    CGEN_CPU_OPEN_END:     terminates arguments
2352
2353    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
2354    precluded.
2355
2356    ??? We only support ISO C stdargs here, not K&R.
2357    Laziness, plus experiment to see if anything requires K&R - eventually
2358    K&R will no longer be supported - e.g. GDB is currently trying this.  */
2359
2360 CGEN_CPU_DESC
2361 mep_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
2362 {
2363   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
2364   static int init_p;
2365   CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
2366   unsigned int machs = 0; /* 0 = "unspecified" */
2367   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
2368   va_list ap;
2369
2370   if (! init_p)
2371     {
2372       init_tables ();
2373       init_p = 1;
2374     }
2375
2376   memset (cd, 0, sizeof (*cd));
2377
2378   va_start (ap, arg_type);
2379   while (arg_type != CGEN_CPU_OPEN_END)
2380     {
2381       switch (arg_type)
2382         {
2383         case CGEN_CPU_OPEN_ISAS :
2384           isas = va_arg (ap, CGEN_BITSET *);
2385           break;
2386         case CGEN_CPU_OPEN_MACHS :
2387           machs = va_arg (ap, unsigned int);
2388           break;
2389         case CGEN_CPU_OPEN_BFDMACH :
2390           {
2391             const char *name = va_arg (ap, const char *);
2392             const CGEN_MACH *mach =
2393               lookup_mach_via_bfd_name (mep_cgen_mach_table, name);
2394
2395             machs |= 1 << mach->num;
2396             break;
2397           }
2398         case CGEN_CPU_OPEN_ENDIAN :
2399           endian = va_arg (ap, enum cgen_endian);
2400           break;
2401         default :
2402           fprintf (stderr, "mep_cgen_cpu_open: unsupported argument `%d'\n",
2403                    arg_type);
2404           abort (); /* ??? return NULL? */
2405         }
2406       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
2407     }
2408   va_end (ap);
2409
2410   /* Mach unspecified means "all".  */
2411   if (machs == 0)
2412     machs = (1 << MAX_MACHS) - 1;
2413   /* Base mach is always selected.  */
2414   machs |= 1;
2415   if (endian == CGEN_ENDIAN_UNKNOWN)
2416     {
2417       /* ??? If target has only one, could have a default.  */
2418       fprintf (stderr, "mep_cgen_cpu_open: no endianness specified\n");
2419       abort ();
2420     }
2421
2422   cd->isas = cgen_bitset_copy (isas);
2423   cd->machs = machs;
2424   cd->endian = endian;
2425   /* FIXME: for the sparc case we can determine insn-endianness statically.
2426      The worry here is where both data and insn endian can be independently
2427      chosen, in which case this function will need another argument.
2428      Actually, will want to allow for more arguments in the future anyway.  */
2429   cd->insn_endian = endian;
2430
2431   /* Table (re)builder.  */
2432   cd->rebuild_tables = mep_cgen_rebuild_tables;
2433   mep_cgen_rebuild_tables (cd);
2434
2435   /* Default to not allowing signed overflow.  */
2436   cd->signed_overflow_ok_p = 0;
2437
2438   return (CGEN_CPU_DESC) cd;
2439 }
2440
2441 /* Cover fn to mep_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
2442    MACH_NAME is the bfd name of the mach.  */
2443
2444 CGEN_CPU_DESC
2445 mep_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
2446 {
2447   return mep_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
2448                                CGEN_CPU_OPEN_ENDIAN, endian,
2449                                CGEN_CPU_OPEN_END);
2450 }
2451
2452 /* Close a cpu table.
2453    ??? This can live in a machine independent file, but there's currently
2454    no place to put this file (there's no libcgen).  libopcodes is the wrong
2455    place as some simulator ports use this but they don't use libopcodes.  */
2456
2457 void
2458 mep_cgen_cpu_close (CGEN_CPU_DESC cd)
2459 {
2460   unsigned int i;
2461   const CGEN_INSN *insns;
2462
2463   if (cd->macro_insn_table.init_entries)
2464     {
2465       insns = cd->macro_insn_table.init_entries;
2466       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
2467         if (CGEN_INSN_RX ((insns)))
2468           regfree (CGEN_INSN_RX (insns));
2469     }
2470
2471   if (cd->insn_table.init_entries)
2472     {
2473       insns = cd->insn_table.init_entries;
2474       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
2475         if (CGEN_INSN_RX (insns))
2476           regfree (CGEN_INSN_RX (insns));
2477     }
2478
2479   if (cd->macro_insn_table.init_entries)
2480     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
2481
2482   if (cd->insn_table.init_entries)
2483     free ((CGEN_INSN *) cd->insn_table.init_entries);
2484
2485   if (cd->hw_table.entries)
2486     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
2487
2488   if (cd->operand_table.entries)
2489     free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
2490
2491   free (cd);
2492 }
2493