1 /* micromips-opc.c. microMIPS opcode table.
2 Copyright 2008, 2012 Free Software Foundation, Inc.
3 Contributed by Chao-ying Fu, MIPS Technologies, Inc.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
23 #include "opcode/mips.h"
24 #include "mips-formats.h"
26 static unsigned char reg_0_map
[] = { 0 };
27 static unsigned char reg_28_map
[] = { 28 };
28 static unsigned char reg_29_map
[] = { 29 };
29 static unsigned char reg_31_map
[] = { 31 };
30 static unsigned char reg_m16_map
[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
31 static unsigned char reg_mn_map
[] = { 0, 17, 2, 3, 16, 18, 19, 20 };
32 static unsigned char reg_q_map
[] = { 0, 17, 2, 3, 4, 5, 6, 7 };
34 static unsigned char reg_h_map1
[] = { 5, 5, 6, 4, 4, 4, 4, 4 };
35 static unsigned char reg_h_map2
[] = { 6, 7, 7, 21, 22, 5, 6, 7 };
37 static int int_b_map
[] = {
38 1, 4, 8, 12, 16, 20, 24, -1
40 static int int_c_map
[] = {
41 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
44 /* Return the mips_operand structure for the operand at the beginning of P. */
46 const struct mips_operand
*
47 decode_micromips_operand (const char *p
)
54 case 'a': MAPPED_REG (0, 0, GP
, reg_28_map
);
55 case 'b': MAPPED_REG (3, 23, GP
, reg_m16_map
);
56 case 'c': MAPPED_REG (3, 4, GP
, reg_m16_map
);
57 case 'd': MAPPED_REG (3, 7, GP
, reg_m16_map
);
58 case 'e': MAPPED_REG (3, 1, GP
, reg_m16_map
);
59 case 'f': MAPPED_REG (3, 3, GP
, reg_m16_map
);
60 case 'g': MAPPED_REG (3, 0, GP
, reg_m16_map
);
61 case 'h': REG_PAIR (3, 7, GP
, reg_h_map
);
62 case 'j': REG (5, 0, GP
);
63 case 'l': MAPPED_REG (3, 4, GP
, reg_m16_map
);
64 case 'm': MAPPED_REG (3, 1, GP
, reg_mn_map
);
65 case 'n': MAPPED_REG (3, 4, GP
, reg_mn_map
);
66 case 'p': REG (5, 5, GP
);
67 case 'q': MAPPED_REG (3, 7, GP
, reg_q_map
);
68 case 'r': SPECIAL (0, 0, PC
);
69 case 's': MAPPED_REG (0, 0, GP
, reg_29_map
);
70 case 't': SPECIAL (0, 0, REPEAT_PREV_REG
);
71 case 'x': SPECIAL (0, 0, REPEAT_DEST_REG
);
72 case 'y': MAPPED_REG (0, 0, GP
, reg_31_map
);
73 case 'z': MAPPED_REG (0, 0, GP
, reg_0_map
);
75 case 'A': INT_ADJ (7, 0, 63, 2, FALSE
); /* (-64 .. 63) << 2 */
76 case 'B': MAPPED_INT (3, 1, int_b_map
, FALSE
);
77 case 'C': MAPPED_INT (4, 0, int_c_map
, TRUE
);
78 case 'D': BRANCH (10, 0, 1);
79 case 'E': BRANCH (7, 0, 1);
80 case 'F': HINT (4, 0);
81 case 'G': INT_ADJ (4, 0, 14, 0, FALSE
); /* (-1 .. 14) */
82 case 'H': INT_ADJ (4, 0, 15, 1, FALSE
); /* (0 .. 15) << 1 */
83 case 'I': INT_ADJ (7, 0, 126, 0, FALSE
); /* (-1 .. 126) */
84 case 'J': INT_ADJ (4, 0, 15, 2, FALSE
); /* (0 .. 15) << 2 */
85 case 'L': INT_ADJ (4, 0, 15, 0, FALSE
); /* (0 .. 15) */
86 case 'M': INT_ADJ (3, 1, 8, 0, FALSE
); /* (1 .. 8) */
87 case 'N': SPECIAL (2, 4, LWM_SWM_LIST
);
88 case 'O': HINT (4, 0);
89 case 'P': INT_ADJ (5, 0, 31, 2, FALSE
); /* (0 .. 31) << 2 */
90 case 'Q': INT_ADJ (23, 0, 4194303, 2, FALSE
);
91 /* (-4194304 .. 4194303) */
92 case 'U': INT_ADJ (5, 0, 31, 2, FALSE
); /* (0 .. 31) << 2 */
93 case 'W': INT_ADJ (6, 1, 63, 2, FALSE
); /* (0 .. 63) << 2 */
94 case 'X': SINT (4, 1);
95 case 'Y': SPECIAL (9, 1, ADDIUSP_INT
);
96 case 'Z': UINT (0, 0); /* 0 only */
103 case 'A': BIT (5, 6, 0); /* (0 .. 31) */
104 case 'B': MSB (5, 11, 1, TRUE
, 32); /* (1 .. 32), 32-bit op */
105 case 'C': MSB (5, 11, 1, FALSE
, 32); /* (1 .. 32), 32-bit op */
106 case 'E': BIT (5, 6, 32); /* (32 .. 63) */
107 case 'F': MSB (5, 11, 33, TRUE
, 64); /* (33 .. 64), 64-bit op */
108 case 'G': MSB (5, 11, 33, FALSE
, 64); /* (33 .. 64), 64-bit op */
109 case 'H': MSB (5, 11, 1, FALSE
, 64); /* (1 .. 32), 64-bit op */
111 case 'i': JALX (26, 0, 2);
112 case 'j': SINT (9, 0);
116 case '.': SINT (10, 6);
117 case '<': BIT (5, 11, 0); /* (0 .. 31) */
118 case '>': BIT (5, 11, 32); /* (32 .. 63) */
119 case '\\': BIT (3, 21, 0); /* (0 .. 7) */
120 case '|': HINT (4, 12);
121 case '~': SINT (12, 0);
122 case '@': SINT (10, 16);
123 case '^': HINT (5, 11);
125 case '0': SINT (6, 16);
126 case '1': HINT (5, 16);
127 case '2': HINT (2, 14);
128 case '3': HINT (3, 13);
129 case '4': HINT (4, 12);
130 case '5': HINT (8, 13);
131 case '6': HINT (5, 16);
132 case '7': REG (2, 14, ACC
);
133 case '8': HINT (6, 14);
135 case 'B': HINT (10, 16);
136 case 'C': HINT (23, 3);
137 case 'D': REG (5, 11, FP
);
138 case 'E': REG (5, 21, COPRO
);
139 case 'G': REG (5, 16, COPRO
);
140 case 'K': REG (5, 16, HW
);
141 case 'H': UINT (3, 11);
142 case 'M': REG (3, 13, CCC
);
143 case 'N': REG (3, 18, CCC
);
144 case 'R': REG (5, 6, FP
);
145 case 'S': REG (5, 16, FP
);
146 case 'T': REG (5, 21, FP
);
147 case 'V': REG (5, 16, FP
);
149 case 'a': JUMP (26, 0, 1);
150 case 'b': REG (5, 16, GP
);
151 case 'c': HINT (10, 16);
152 case 'd': REG (5, 11, GP
);
153 case 'h': HINT (5, 11);
154 case 'i': HINT (16, 0);
155 case 'j': SINT (16, 0);
156 case 'k': HINT (5, 21);
157 case 'n': SPECIAL (5, 21, LWM_SWM_LIST
);
158 case 'o': SINT (16, 0);
159 case 'p': BRANCH (16, 0, 1);
160 case 'q': HINT (10, 6);
161 case 'r': REG (5, 16, GP
);
162 case 's': REG (5, 16, GP
);
163 case 't': REG (5, 21, GP
);
164 case 'u': HINT (16, 0);
165 case 'v': REG (5, 16, GP
);
166 case 'w': REG (5, 21, GP
);
167 case 'y': REG (5, 6, GP
);
168 case 'z': MAPPED_REG (0, 0, GP
, reg_0_map
);
173 #define UBD INSN_UNCOND_BRANCH_DELAY
174 #define CBD INSN_COND_BRANCH_DELAY
175 #define NODS INSN_NO_DELAY_SLOT
176 #define TRAP INSN_NO_DELAY_SLOT
177 #define SM INSN_STORE_MEMORY
178 #define BD16 INSN2_BRANCH_DELAY_16BIT /* Used in pinfo2. */
179 #define BD32 INSN2_BRANCH_DELAY_32BIT /* Used in pinfo2. */
181 /* For 16-bit/32-bit microMIPS instructions. They are used in pinfo2. */
182 #define UBR INSN2_UNCOND_BRANCH
183 #define CBR INSN2_COND_BRANCH
184 #define WR_mb INSN2_WRITE_GPR_MB
185 #define RD_mc INSN2_READ_GPR_MC
186 #define RD_md INSN2_MOD_GPR_MD
187 #define WR_md INSN2_MOD_GPR_MD
188 #define RD_me INSN2_READ_GPR_ME
189 #define RD_mf INSN2_MOD_GPR_MF
190 #define WR_mf INSN2_MOD_GPR_MF
191 #define RD_mg INSN2_READ_GPR_MG
192 #define WR_mh INSN2_WRITE_GPR_MH
193 #define RD_mj INSN2_READ_GPR_MJ
194 #define WR_mj INSN2_WRITE_GPR_MJ
195 #define RD_ml RD_mc /* Reuse, since the bit position is the same. */
196 #define RD_mmn INSN2_READ_GPR_MMN
197 #define RD_mp INSN2_READ_GPR_MP
198 #define WR_mp INSN2_WRITE_GPR_MP
199 #define RD_mq INSN2_READ_GPR_MQ
200 #define RD_sp INSN2_MOD_SP
201 #define WR_sp INSN2_MOD_SP
202 #define RD_31 INSN2_READ_GPR_31
203 #define RD_gp INSN2_READ_GP
204 #define RD_pc INSN2_READ_PC
206 /* For 32-bit microMIPS instructions. */
207 #define WR_s INSN_WRITE_GPR_S
208 #define WR_d INSN_WRITE_GPR_D
209 #define WR_t INSN_WRITE_GPR_T
210 #define WR_31 INSN_WRITE_GPR_31
211 #define WR_D INSN_WRITE_FPR_D
212 #define WR_T INSN_WRITE_FPR_T
213 #define WR_S INSN_WRITE_FPR_S
214 #define WR_CC INSN_WRITE_COND_CODE
216 #define RD_s INSN_READ_GPR_S
217 #define RD_b INSN_READ_GPR_S
218 #define RD_t INSN_READ_GPR_T
219 #define RD_T INSN_READ_FPR_T
220 #define RD_S INSN_READ_FPR_S
221 #define RD_R INSN_READ_FPR_R
222 #define RD_D INSN2_READ_FPR_D /* Used in pinfo2. */
223 #define RD_CC INSN_READ_COND_CODE
224 #define RD_C0 INSN_COP
225 #define RD_C1 INSN_COP
226 #define RD_C2 INSN_COP
227 #define WR_C0 INSN_COP
228 #define WR_C1 INSN_COP
229 #define WR_C2 INSN_COP
232 #define WR_HI INSN_WRITE_HI
233 #define RD_HI INSN_READ_HI
235 #define WR_LO INSN_WRITE_LO
236 #define RD_LO INSN_READ_LO
238 #define WR_HILO WR_HI|WR_LO
239 #define RD_HILO RD_HI|RD_LO
240 #define MOD_HILO WR_HILO|RD_HILO
242 /* Reuse INSN_ISA1 for 32-bit microMIPS ISA. All instructions in I1
243 are accepted as 32-bit microMIPS ISA.
244 Reuse INSN_ISA3 for 64-bit microMIPS ISA. All instructions in I3
245 are accepted as 64-bit microMIPS ISA. */
249 /* MIPS DSP ASE support. */
250 #define WR_a WR_HILO /* Write DSP accumulators (reuse WR_HILO). */
251 #define RD_a RD_HILO /* Read DSP accumulators (reuse RD_HILO). */
252 #define MOD_a WR_a|RD_a
253 #define DSP_VOLA INSN_NO_DELAY_SLOT
255 #define D33 ASE_DSPR2
257 /* MIPS MCU (MicroController) ASE support. */
260 /* MIPS Enhanced VA Scheme. */
263 /* TLB invalidate instruction support. */
264 #define TLBINV ASE_EVA
266 /* MIPS Virtualization ASE. */
267 #define IVIRT ASE_VIRT
268 #define IVIRT64 ASE_VIRT64
270 const struct mips_opcode micromips_opcodes
[] =
272 /* These instructions appear first so that the disassembler will find
273 them first. The assemblers uses a hash table based on the
274 instruction name anyhow. */
275 /* name, args, match, mask, pinfo, pinfo2, membership, [ase], [exclusions] */
276 {"pref", "k,~(b)", 0x60002000, 0xfc00f000, RD_b
, 0, I1
},
277 {"pref", "k,A(b)", 0, (int) M_PREF_AB
, INSN_MACRO
, 0, I1
},
278 {"prefx", "h,t(b)", 0x540001a0, 0xfc0007ff, RD_b
|RD_t
|FP_S
, 0, I1
},
279 {"nop", "", 0x0c00, 0xffff, 0, INSN2_ALIAS
, I1
},
280 {"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS
, I1
}, /* sll */
281 {"ssnop", "", 0x00000800, 0xffffffff, 0, INSN2_ALIAS
, I1
}, /* sll */
282 {"ehb", "", 0x00001800, 0xffffffff, 0, INSN2_ALIAS
, I1
}, /* sll */
283 {"pause", "", 0x00002800, 0xffffffff, 0, INSN2_ALIAS
, I1
}, /* sll */
284 {"li", "md,mI", 0xec00, 0xfc00, 0, WR_md
, I1
},
285 {"li", "t,j", 0x30000000, 0xfc1f0000, WR_t
, INSN2_ALIAS
, I1
}, /* addiu */
286 {"li", "t,i", 0x50000000, 0xfc1f0000, WR_t
, INSN2_ALIAS
, I1
}, /* ori */
288 /* Disabled until we can handle 48-bit opcodes. */
289 {"li", "s,I", 0x7c0000010000, 0xfc00001f0000, WR_t
, 0, I3
}, /* li48 */
291 {"li", "t,I", 0, (int) M_LI
, INSN_MACRO
, 0, I1
},
292 {"move", "d,s", 0, (int) M_MOVE
, INSN_MACRO
, 0, I1
},
293 {"move", "mp,mj", 0x0c00, 0xfc00, 0, WR_mp
|RD_mj
, I1
},
294 {"move", "d,s", 0x58000150, 0xffe007ff, WR_d
|RD_s
, INSN2_ALIAS
, I3
}, /* daddu */
295 {"move", "d,s", 0x00000150, 0xffe007ff, WR_d
|RD_s
, INSN2_ALIAS
, I1
}, /* addu */
296 {"move", "d,s", 0x00000290, 0xffe007ff, WR_d
|RD_s
, INSN2_ALIAS
, I1
}, /* or */
297 {"b", "mD", 0xcc00, 0xfc00, UBD
, 0, I1
},
298 {"b", "p", 0x94000000, 0xffff0000, UBD
, INSN2_ALIAS
, I1
}, /* beq 0, 0 */
299 {"b", "p", 0x40400000, 0xffff0000, UBD
, INSN2_ALIAS
, I1
}, /* bgez 0 */
300 {"bal", "p", 0x40600000, 0xffff0000, UBD
|WR_31
, INSN2_ALIAS
|BD32
, I1
}, /* bgezal 0 */
301 {"bals", "p", 0x42600000, 0xffff0000, UBD
|WR_31
, INSN2_ALIAS
|BD16
, I1
}, /* bgezals 0 */
302 {"bc", "p", 0x40e00000, 0xffff0000, NODS
, INSN2_ALIAS
|UBR
, I1
}, /* beqzc 0 */
304 {"abs", "d,v", 0, (int) M_ABS
, INSN_MACRO
, 0, I1
},
305 {"abs.d", "T,V", 0x5400237b, 0xfc00ffff, WR_T
|RD_S
|FP_D
, 0, I1
},
306 {"abs.s", "T,V", 0x5400037b, 0xfc00ffff, WR_T
|RD_S
|FP_S
, 0, I1
},
307 {"abs.ps", "T,V", 0x5400437b, 0xfc00ffff, WR_T
|RD_S
|FP_D
, 0, I1
},
308 {"aclr", "\\,~(b)", 0x2000b000, 0xff00f000, SM
|RD_b
|NODS
, 0, 0, MC
},
309 {"aclr", "\\,A(b)", 0, (int) M_ACLR_AB
, INSN_MACRO
, 0, 0, MC
},
310 {"add", "d,v,t", 0x00000110, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, I1
},
311 {"add", "t,r,I", 0, (int) M_ADD_I
, INSN_MACRO
, 0, I1
},
312 {"add.d", "D,V,T", 0x54000130, 0xfc0007ff, WR_D
|RD_S
|RD_T
|FP_D
, 0, I1
},
313 {"add.s", "D,V,T", 0x54000030, 0xfc0007ff, WR_D
|RD_S
|RD_T
|FP_S
, 0, I1
},
314 {"add.ps", "D,V,T", 0x54000230, 0xfc0007ff, WR_D
|RD_S
|RD_T
|FP_D
, 0, I1
},
315 {"addi", "t,r,j", 0x10000000, 0xfc000000, WR_t
|RD_s
, 0, I1
},
316 {"addiu", "mp,mj,mZ", 0x0c00, 0xfc00, 0, WR_mp
|RD_mj
, I1
}, /* move */
317 {"addiu", "md,ms,mW", 0x6c01, 0xfc01, 0, WR_md
|RD_sp
, I1
}, /* addiur1sp */
318 {"addiu", "md,mc,mB", 0x6c00, 0xfc01, 0, WR_md
|RD_mc
, I1
}, /* addiur2 */
319 {"addiu", "ms,mt,mY", 0x4c01, 0xfc01, 0, WR_sp
|RD_sp
, I1
}, /* addiusp */
320 {"addiu", "mp,mt,mX", 0x4c00, 0xfc01, 0, WR_mp
|RD_mp
, I1
}, /* addius5 */
321 {"addiu", "mb,mr,mQ", 0x78000000, 0xfc000000, 0, WR_mb
|RD_pc
, I1
}, /* addiupc */
322 {"addiu", "t,r,j", 0x30000000, 0xfc000000, WR_t
|RD_s
, 0, I1
},
323 {"addiupc", "mb,mQ", 0x78000000, 0xfc000000, 0, WR_mb
|RD_pc
, I1
},
324 {"addiur1sp", "md,mW", 0x6c01, 0xfc01, 0, WR_md
|RD_sp
, I1
},
325 {"addiur2", "md,mc,mB", 0x6c00, 0xfc01, 0, WR_md
|RD_mc
, I1
},
326 {"addiusp", "mY", 0x4c01, 0xfc01, 0, WR_sp
|RD_sp
, I1
},
327 {"addius5", "mp,mX", 0x4c00, 0xfc01, 0, WR_mp
|RD_mp
, I1
},
328 {"addu", "mp,mj,mz", 0x0c00, 0xfc00, 0, WR_mp
|RD_mj
, I1
}, /* move */
329 {"addu", "mp,mz,mj", 0x0c00, 0xfc00, 0, WR_mp
|RD_mj
, I1
}, /* move */
330 {"addu", "md,me,ml", 0x0400, 0xfc01, 0, WR_md
|RD_me
|RD_ml
, I1
},
331 {"addu", "d,v,t", 0x00000150, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, I1
},
332 {"addu", "t,r,I", 0, (int) M_ADDU_I
, INSN_MACRO
, 0, I1
},
333 /* We have no flag to mark the read from "y", so we use NODS to disable
334 delay slot scheduling of ALNV.PS altogether. */
335 {"alnv.ps", "D,V,T,y", 0x54000019, 0xfc00003f, NODS
|WR_D
|RD_S
|RD_T
|FP_D
, 0, I1
},
336 {"and", "mf,mt,mg", 0x4480, 0xffc0, 0, WR_mf
|RD_mf
|RD_mg
, I1
},
337 {"and", "mf,mg,mx", 0x4480, 0xffc0, 0, WR_mf
|RD_mf
|RD_mg
, I1
},
338 {"and", "d,v,t", 0x00000250, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, I1
},
339 {"and", "t,r,I", 0, (int) M_AND_I
, INSN_MACRO
, 0, I1
},
340 {"andi", "md,mc,mC", 0x2c00, 0xfc00, 0, WR_md
|RD_mc
, I1
},
341 {"andi", "t,r,i", 0xd0000000, 0xfc000000, WR_t
|RD_s
, 0, I1
},
342 {"aset", "\\,~(b)", 0x20003000, 0xff00f000, SM
|RD_b
|NODS
, 0, 0, MC
},
343 {"aset", "\\,A(b)", 0, (int) M_ASET_AB
, INSN_MACRO
, 0, 0, MC
},
344 /* b is at the top of the table. */
345 /* bal is at the top of the table. */
346 {"bc1f", "p", 0x43800000, 0xffff0000, CBD
|RD_CC
|FP_S
, 0, I1
},
347 {"bc1f", "N,p", 0x43800000, 0xffe30000, CBD
|RD_CC
|FP_S
, 0, I1
},
348 {"bc1fl", "p", 0, (int) M_BC1FL
, INSN_MACRO
, INSN2_M_FP_S
, I1
},
349 {"bc1fl", "N,p", 0, (int) M_BC1FL
, INSN_MACRO
, INSN2_M_FP_S
, I1
},
350 {"bc2f", "p", 0x42800000, 0xffff0000, CBD
|RD_CC
, 0, I1
},
351 {"bc2f", "N,p", 0x42800000, 0xffe30000, CBD
|RD_CC
, 0, I1
},
352 {"bc2fl", "p", 0, (int) M_BC2FL
, INSN_MACRO
, 0, I1
},
353 {"bc2fl", "N,p", 0, (int) M_BC2FL
, INSN_MACRO
, 0, I1
},
354 {"bc1t", "p", 0x43a00000, 0xffff0000, CBD
|RD_CC
|FP_S
, 0, I1
},
355 {"bc1t", "N,p", 0x43a00000, 0xffe30000, CBD
|RD_CC
|FP_S
, 0, I1
},
356 {"bc1tl", "p", 0, (int) M_BC1TL
, INSN_MACRO
, INSN2_M_FP_S
, I1
},
357 {"bc1tl", "N,p", 0, (int) M_BC1TL
, INSN_MACRO
, INSN2_M_FP_S
, I1
},
358 {"bc2t", "p", 0x42a00000, 0xffff0000, CBD
|RD_CC
, 0, I1
},
359 {"bc2t", "N,p", 0x42a00000, 0xffe30000, CBD
|RD_CC
, 0, I1
},
360 {"bc2tl", "p", 0, (int) M_BC2TL
, INSN_MACRO
, 0, I1
},
361 {"bc2tl", "N,p", 0, (int) M_BC2TL
, INSN_MACRO
, 0, I1
},
362 {"beqz", "md,mE", 0x8c00, 0xfc00, CBD
, RD_md
, I1
},
363 {"beqz", "s,p", 0x94000000, 0xffe00000, CBD
|RD_s
, 0, I1
},
364 {"beqzc", "s,p", 0x40e00000, 0xffe00000, NODS
|RD_s
, CBR
, I1
},
365 {"beqzl", "s,p", 0, (int) M_BEQL
, INSN_MACRO
, 0, I1
},
366 {"beq", "md,mz,mE", 0x8c00, 0xfc00, CBD
, RD_md
, I1
}, /* beqz */
367 {"beq", "mz,md,mE", 0x8c00, 0xfc00, CBD
, RD_md
, I1
}, /* beqz */
368 {"beq", "s,t,p", 0x94000000, 0xfc000000, CBD
|RD_s
|RD_t
, 0, I1
},
369 {"beq", "s,I,p", 0, (int) M_BEQ_I
, INSN_MACRO
, 0, I1
},
370 {"beql", "s,t,p", 0, (int) M_BEQL
, INSN_MACRO
, 0, I1
},
371 {"beql", "s,I,p", 0, (int) M_BEQL_I
, INSN_MACRO
, 0, I1
},
372 {"bge", "s,t,p", 0, (int) M_BGE
, INSN_MACRO
, 0, I1
},
373 {"bge", "s,I,p", 0, (int) M_BGE_I
, INSN_MACRO
, 0, I1
},
374 {"bgel", "s,t,p", 0, (int) M_BGEL
, INSN_MACRO
, 0, I1
},
375 {"bgel", "s,I,p", 0, (int) M_BGEL_I
, INSN_MACRO
, 0, I1
},
376 {"bgeu", "s,t,p", 0, (int) M_BGEU
, INSN_MACRO
, 0, I1
},
377 {"bgeu", "s,I,p", 0, (int) M_BGEU_I
, INSN_MACRO
, 0, I1
},
378 {"bgeul", "s,t,p", 0, (int) M_BGEUL
, INSN_MACRO
, 0, I1
},
379 {"bgeul", "s,I,p", 0, (int) M_BGEUL_I
, INSN_MACRO
, 0, I1
},
380 {"bgez", "s,p", 0x40400000, 0xffe00000, CBD
|RD_s
, 0, I1
},
381 {"bgezl", "s,p", 0, (int) M_BGEZL
, INSN_MACRO
, 0, I1
},
382 {"bgezal", "s,p", 0x40600000, 0xffe00000, CBD
|RD_s
|WR_31
, BD32
, I1
},
383 {"bgezals", "s,p", 0x42600000, 0xffe00000, CBD
|RD_s
|WR_31
, BD16
, I1
},
384 {"bgezall", "s,p", 0, (int) M_BGEZALL
, INSN_MACRO
, 0, I1
},
385 {"bgt", "s,t,p", 0, (int) M_BGT
, INSN_MACRO
, 0, I1
},
386 {"bgt", "s,I,p", 0, (int) M_BGT_I
, INSN_MACRO
, 0, I1
},
387 {"bgtl", "s,t,p", 0, (int) M_BGTL
, INSN_MACRO
, 0, I1
},
388 {"bgtl", "s,I,p", 0, (int) M_BGTL_I
, INSN_MACRO
, 0, I1
},
389 {"bgtu", "s,t,p", 0, (int) M_BGTU
, INSN_MACRO
, 0, I1
},
390 {"bgtu", "s,I,p", 0, (int) M_BGTU_I
, INSN_MACRO
, 0, I1
},
391 {"bgtul", "s,t,p", 0, (int) M_BGTUL
, INSN_MACRO
, 0, I1
},
392 {"bgtul", "s,I,p", 0, (int) M_BGTUL_I
, INSN_MACRO
, 0, I1
},
393 {"bgtz", "s,p", 0x40c00000, 0xffe00000, CBD
|RD_s
, 0, I1
},
394 {"bgtzl", "s,p", 0, (int) M_BGTZL
, INSN_MACRO
, 0, I1
},
395 {"ble", "s,t,p", 0, (int) M_BLE
, INSN_MACRO
, 0, I1
},
396 {"ble", "s,I,p", 0, (int) M_BLE_I
, INSN_MACRO
, 0, I1
},
397 {"blel", "s,t,p", 0, (int) M_BLEL
, INSN_MACRO
, 0, I1
},
398 {"blel", "s,I,p", 0, (int) M_BLEL_I
, INSN_MACRO
, 0, I1
},
399 {"bleu", "s,t,p", 0, (int) M_BLEU
, INSN_MACRO
, 0, I1
},
400 {"bleu", "s,I,p", 0, (int) M_BLEU_I
, INSN_MACRO
, 0, I1
},
401 {"bleul", "s,t,p", 0, (int) M_BLEUL
, INSN_MACRO
, 0, I1
},
402 {"bleul", "s,I,p", 0, (int) M_BLEUL_I
, INSN_MACRO
, 0, I1
},
403 {"blez", "s,p", 0x40800000, 0xffe00000, CBD
|RD_s
, 0, I1
},
404 {"blezl", "s,p", 0, (int) M_BLEZL
, INSN_MACRO
, 0, I1
},
405 {"blt", "s,t,p", 0, (int) M_BLT
, INSN_MACRO
, 0, I1
},
406 {"blt", "s,I,p", 0, (int) M_BLT_I
, INSN_MACRO
, 0, I1
},
407 {"bltl", "s,t,p", 0, (int) M_BLTL
, INSN_MACRO
, 0, I1
},
408 {"bltl", "s,I,p", 0, (int) M_BLTL_I
, INSN_MACRO
, 0, I1
},
409 {"bltu", "s,t,p", 0, (int) M_BLTU
, INSN_MACRO
, 0, I1
},
410 {"bltu", "s,I,p", 0, (int) M_BLTU_I
, INSN_MACRO
, 0, I1
},
411 {"bltul", "s,t,p", 0, (int) M_BLTUL
, INSN_MACRO
, 0, I1
},
412 {"bltul", "s,I,p", 0, (int) M_BLTUL_I
, INSN_MACRO
, 0, I1
},
413 {"bltz", "s,p", 0x40000000, 0xffe00000, CBD
|RD_s
, 0, I1
},
414 {"bltzl", "s,p", 0, (int) M_BLTZL
, INSN_MACRO
, 0, I1
},
415 {"bltzal", "s,p", 0x40200000, 0xffe00000, CBD
|RD_s
|WR_31
, BD32
, I1
},
416 {"bltzals", "s,p", 0x42200000, 0xffe00000, CBD
|RD_s
|WR_31
, BD16
, I1
},
417 {"bltzall", "s,p", 0, (int) M_BLTZALL
, INSN_MACRO
, 0, I1
},
418 {"bnez", "md,mE", 0xac00, 0xfc00, CBD
, RD_md
, I1
},
419 {"bnez", "s,p", 0xb4000000, 0xffe00000, CBD
|RD_s
, 0, I1
},
420 {"bnezc", "s,p", 0x40a00000, 0xffe00000, NODS
|RD_s
, CBR
, I1
},
421 {"bnezl", "s,p", 0, (int) M_BNEL
, INSN_MACRO
, 0, I1
},
422 {"bne", "md,mz,mE", 0xac00, 0xfc00, CBD
, RD_md
, I1
}, /* bnez */
423 {"bne", "mz,md,mE", 0xac00, 0xfc00, CBD
, RD_md
, I1
}, /* bnez */
424 {"bne", "s,t,p", 0xb4000000, 0xfc000000, CBD
|RD_s
|RD_t
, 0, I1
},
425 {"bne", "s,I,p", 0, (int) M_BNE_I
, INSN_MACRO
, 0, I1
},
426 {"bnel", "s,t,p", 0, (int) M_BNEL
, INSN_MACRO
, 0, I1
},
427 {"bnel", "s,I,p", 0, (int) M_BNEL_I
, INSN_MACRO
, 0, I1
},
428 {"break", "", 0x4680, 0xffff, TRAP
, 0, I1
},
429 {"break", "", 0x00000007, 0xffffffff, TRAP
, 0, I1
},
430 {"break", "mF", 0x4680, 0xfff0, TRAP
, 0, I1
},
431 {"break", "c", 0x00000007, 0xfc00ffff, TRAP
, 0, I1
},
432 {"break", "c,q", 0x00000007, 0xfc00003f, TRAP
, 0, I1
},
433 {"c.f.d", "S,T", 0x5400043c, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
434 {"c.f.d", "M,S,T", 0x5400043c, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
435 {"c.f.s", "S,T", 0x5400003c, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
436 {"c.f.s", "M,S,T", 0x5400003c, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
437 {"c.f.ps", "S,T", 0x5400083c, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
438 {"c.f.ps", "M,S,T", 0x5400083c, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
439 {"c.un.d", "S,T", 0x5400047c, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
440 {"c.un.d", "M,S,T", 0x5400047c, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
441 {"c.un.s", "S,T", 0x5400007c, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
442 {"c.un.s", "M,S,T", 0x5400007c, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
443 {"c.un.ps", "S,T", 0x5400087c, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
444 {"c.un.ps", "M,S,T", 0x5400087c, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
445 {"c.eq.d", "S,T", 0x540004bc, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
446 {"c.eq.d", "M,S,T", 0x540004bc, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
447 {"c.eq.s", "S,T", 0x540000bc, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
448 {"c.eq.s", "M,S,T", 0x540000bc, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
449 {"c.eq.ps", "S,T", 0x540008bc, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
450 {"c.eq.ps", "M,S,T", 0x540008bc, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
451 {"c.ueq.d", "S,T", 0x540004fc, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
452 {"c.ueq.d", "M,S,T", 0x540004fc, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
453 {"c.ueq.s", "S,T", 0x540000fc, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
454 {"c.ueq.s", "M,S,T", 0x540000fc, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
455 {"c.ueq.ps", "S,T", 0x540008fc, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
456 {"c.ueq.ps", "M,S,T", 0x540008fc, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
457 {"c.olt.d", "S,T", 0x5400053c, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
458 {"c.olt.d", "M,S,T", 0x5400053c, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
459 {"c.olt.s", "S,T", 0x5400013c, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
460 {"c.olt.s", "M,S,T", 0x5400013c, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
461 {"c.olt.ps", "S,T", 0x5400093c, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
462 {"c.olt.ps", "M,S,T", 0x5400093c, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
463 {"c.ult.d", "S,T", 0x5400057c, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
464 {"c.ult.d", "M,S,T", 0x5400057c, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
465 {"c.ult.s", "S,T", 0x5400017c, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
466 {"c.ult.s", "M,S,T", 0x5400017c, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
467 {"c.ult.ps", "S,T", 0x5400097c, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
468 {"c.ult.ps", "M,S,T", 0x5400097c, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
469 {"c.ole.d", "S,T", 0x540005bc, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
470 {"c.ole.d", "M,S,T", 0x540005bc, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
471 {"c.ole.s", "S,T", 0x540001bc, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
472 {"c.ole.s", "M,S,T", 0x540001bc, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
473 {"c.ole.ps", "S,T", 0x540009bc, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
474 {"c.ole.ps", "M,S,T", 0x540009bc, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
475 {"c.ule.d", "S,T", 0x540005fc, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
476 {"c.ule.d", "M,S,T", 0x540005fc, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
477 {"c.ule.s", "S,T", 0x540001fc, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
478 {"c.ule.s", "M,S,T", 0x540001fc, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
479 {"c.ule.ps", "S,T", 0x540009fc, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
480 {"c.ule.ps", "M,S,T", 0x540009fc, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
481 {"c.sf.d", "S,T", 0x5400063c, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
482 {"c.sf.d", "M,S,T", 0x5400063c, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
483 {"c.sf.s", "S,T", 0x5400023c, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
484 {"c.sf.s", "M,S,T", 0x5400023c, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
485 {"c.sf.ps", "S,T", 0x54000a3c, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
486 {"c.sf.ps", "M,S,T", 0x54000a3c, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
487 {"c.ngle.d", "S,T", 0x5400067c, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
488 {"c.ngle.d", "M,S,T", 0x5400067c, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
489 {"c.ngle.s", "S,T", 0x5400027c, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
490 {"c.ngle.s", "M,S,T", 0x5400027c, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
491 {"c.ngle.ps", "S,T", 0x54000a7c, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
492 {"c.ngle.ps", "M,S,T", 0x54000a7c, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
493 {"c.seq.d", "S,T", 0x540006bc, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
494 {"c.seq.d", "M,S,T", 0x540006bc, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
495 {"c.seq.s", "S,T", 0x540002bc, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
496 {"c.seq.s", "M,S,T", 0x540002bc, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
497 {"c.seq.ps", "S,T", 0x54000abc, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
498 {"c.seq.ps", "M,S,T", 0x54000abc, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
499 {"c.ngl.d", "S,T", 0x540006fc, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
500 {"c.ngl.d", "M,S,T", 0x540006fc, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
501 {"c.ngl.s", "S,T", 0x540002fc, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
502 {"c.ngl.s", "M,S,T", 0x540002fc, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
503 {"c.ngl.ps", "S,T", 0x54000afc, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
504 {"c.ngl.ps", "M,S,T", 0x54000afc, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
505 {"c.lt.d", "S,T", 0x5400073c, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
506 {"c.lt.d", "M,S,T", 0x5400073c, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
507 {"c.lt.s", "S,T", 0x5400033c, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
508 {"c.lt.s", "M,S,T", 0x5400033c, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
509 {"c.lt.ps", "S,T", 0x54000b3c, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
510 {"c.lt.ps", "M,S,T", 0x54000b3c, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
511 {"c.nge.d", "S,T", 0x5400077c, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
512 {"c.nge.d", "M,S,T", 0x5400077c, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
513 {"c.nge.s", "S,T", 0x5400037c, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
514 {"c.nge.s", "M,S,T", 0x5400037c, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
515 {"c.nge.ps", "S,T", 0x54000b7c, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
516 {"c.nge.ps", "M,S,T", 0x54000b7c, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
517 {"c.le.d", "S,T", 0x540007bc, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
518 {"c.le.d", "M,S,T", 0x540007bc, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
519 {"c.le.s", "S,T", 0x540003bc, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
520 {"c.le.s", "M,S,T", 0x540003bc, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
521 {"c.le.ps", "S,T", 0x54000bbc, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
522 {"c.le.ps", "M,S,T", 0x54000bbc, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
523 {"c.ngt.d", "S,T", 0x540007fc, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
524 {"c.ngt.d", "M,S,T", 0x540007fc, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
525 {"c.ngt.s", "S,T", 0x540003fc, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
526 {"c.ngt.s", "M,S,T", 0x540003fc, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_S
, 0, I1
},
527 {"c.ngt.ps", "S,T", 0x54000bfc, 0xfc00ffff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
528 {"c.ngt.ps", "M,S,T", 0x54000bfc, 0xfc001fff, RD_S
|RD_T
|WR_CC
|FP_D
, 0, I1
},
529 {"cache", "k,~(b)", 0x20006000, 0xfc00f000, RD_b
, 0, I1
},
530 {"cache", "k,A(b)", 0, (int) M_CACHE_AB
, INSN_MACRO
, 0, I1
},
531 {"ceil.l.d", "T,S", 0x5400533b, 0xfc00ffff, WR_T
|RD_S
|FP_D
, 0, I1
},
532 {"ceil.l.s", "T,S", 0x5400133b, 0xfc00ffff, WR_T
|RD_S
|FP_S
|FP_D
, 0, I1
},
533 {"ceil.w.d", "T,S", 0x54005b3b, 0xfc00ffff, WR_T
|RD_S
|FP_S
|FP_D
, 0, I1
},
534 {"ceil.w.s", "T,S", 0x54001b3b, 0xfc00ffff, WR_T
|RD_S
|FP_S
, 0, I1
},
535 {"cfc1", "t,G", 0x5400103b, 0xfc00ffff, WR_t
|RD_C1
|FP_S
, 0, I1
},
536 {"cfc1", "t,S", 0x5400103b, 0xfc00ffff, WR_t
|RD_C1
|FP_S
, 0, I1
},
537 {"cfc2", "t,G", 0x0000cd3c, 0xfc00ffff, WR_t
|RD_C2
, 0, I1
},
538 {"clo", "t,s", 0x00004b3c, 0xfc00ffff, WR_t
|RD_s
, 0, I1
},
539 {"clz", "t,s", 0x00005b3c, 0xfc00ffff, WR_t
|RD_s
, 0, I1
},
540 {"cop2", "C", 0x00000002, 0xfc000007, CP
, 0, I1
},
541 {"ctc1", "t,G", 0x5400183b, 0xfc00ffff, RD_t
|WR_CC
|FP_S
, 0, I1
},
542 {"ctc1", "t,S", 0x5400183b, 0xfc00ffff, RD_t
|WR_CC
|FP_S
, 0, I1
},
543 {"ctc2", "t,G", 0x0000dd3c, 0xfc00ffff, RD_t
|WR_C2
|WR_CC
, 0, I1
},
544 {"cvt.d.l", "T,S", 0x5400537b, 0xfc00ffff, WR_T
|RD_S
|FP_D
, 0, I1
},
545 {"cvt.d.s", "T,S", 0x5400137b, 0xfc00ffff, WR_T
|RD_S
|FP_S
|FP_D
, 0, I1
},
546 {"cvt.d.w", "T,S", 0x5400337b, 0xfc00ffff, WR_T
|RD_S
|FP_S
|FP_D
, 0, I1
},
547 {"cvt.l.d", "T,S", 0x5400413b, 0xfc00ffff, WR_T
|RD_S
|FP_D
, 0, I1
},
548 {"cvt.l.s", "T,S", 0x5400013b, 0xfc00ffff, WR_T
|RD_S
|FP_S
|FP_D
, 0, I1
},
549 {"cvt.s.l", "T,S", 0x54005b7b, 0xfc00ffff, WR_T
|RD_S
|FP_S
|FP_D
, 0, I1
},
550 {"cvt.s.d", "T,S", 0x54001b7b, 0xfc00ffff, WR_T
|RD_S
|FP_S
|FP_D
, 0, I1
},
551 {"cvt.s.w", "T,S", 0x54003b7b, 0xfc00ffff, WR_T
|RD_S
|FP_S
, 0, I1
},
552 {"cvt.s.pl", "T,S", 0x5400213b, 0xfc00ffff, WR_T
|RD_S
|FP_S
|FP_D
, 0, I1
},
553 {"cvt.s.pu", "T,S", 0x5400293b, 0xfc00ffff, WR_T
|RD_S
|FP_S
|FP_D
, 0, I1
},
554 {"cvt.w.d", "T,S", 0x5400493b, 0xfc00ffff, WR_T
|RD_S
|FP_S
|FP_D
, 0, I1
},
555 {"cvt.w.s", "T,S", 0x5400093b, 0xfc00ffff, WR_T
|RD_S
|FP_S
, 0, I1
},
556 {"cvt.ps.s", "D,V,T", 0x54000180, 0xfc0007ff, WR_D
|RD_S
|RD_T
|FP_S
|FP_D
, 0, I1
},
557 {"dabs", "d,v", 0, (int) M_DABS
, INSN_MACRO
, 0, I3
},
558 {"dadd", "d,v,t", 0x58000110, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, I3
},
559 {"dadd", "t,r,I", 0, (int) M_DADD_I
, INSN_MACRO
, 0, I3
},
560 {"daddi", "t,r,.", 0x5800001c, 0xfc00003f, WR_t
|RD_s
, 0, I3
},
561 {"daddi", "t,r,I", 0, (int) M_DADD_I
, INSN_MACRO
, 0, I3
},
562 {"daddiu", "t,r,j", 0x5c000000, 0xfc000000, WR_t
|RD_s
, 0, I3
},
563 {"daddu", "d,v,t", 0x58000150, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, I3
},
564 {"daddu", "t,r,I", 0, (int) M_DADDU_I
, INSN_MACRO
, 0, I3
},
565 {"dclo", "t,s", 0x58004b3c, 0xfc00ffff, WR_t
|RD_s
, 0, I3
},
566 {"dclz", "t,s", 0x58005b3c, 0xfc00ffff, WR_t
|RD_s
, 0, I3
},
567 {"deret", "", 0x0000e37c, 0xffffffff, NODS
, 0, I1
},
568 {"dext", "t,r,I,+I", 0, (int) M_DEXT
, INSN_MACRO
, 0, I3
},
569 {"dext", "t,r,+A,+C",0x5800002c, 0xfc00003f, WR_t
|RD_s
, 0, I3
},
570 {"dextm", "t,r,+A,+G",0x58000024, 0xfc00003f, WR_t
|RD_s
, 0, I3
},
571 {"dextu", "t,r,+E,+H",0x58000014, 0xfc00003f, WR_t
|RD_s
, 0, I3
},
572 /* For ddiv, see the comments about div. */
573 {"ddiv", "z,s,t", 0x5800ab3c, 0xfc00ffff, RD_s
|RD_t
|WR_HILO
, 0, I3
},
574 {"ddiv", "z,t", 0x5800ab3c, 0xfc1fffff, RD_s
|RD_t
|WR_HILO
, 0, I3
},
575 {"ddiv", "d,v,t", 0, (int) M_DDIV_3
, INSN_MACRO
, 0, I3
},
576 {"ddiv", "d,v,I", 0, (int) M_DDIV_3I
, INSN_MACRO
, 0, I3
},
577 /* For ddivu, see the comments about div. */
578 {"ddivu", "z,s,t", 0x5800bb3c, 0xfc00ffff, RD_s
|RD_t
|WR_HILO
, 0, I3
},
579 {"ddivu", "z,t", 0x5800bb3c, 0xfc1fffff, RD_s
|RD_t
|WR_HILO
, 0, I3
},
580 {"ddivu", "d,v,t", 0, (int) M_DDIVU_3
, INSN_MACRO
, 0, I3
},
581 {"ddivu", "d,v,I", 0, (int) M_DDIVU_3I
, INSN_MACRO
, 0, I3
},
582 {"di", "", 0x0000477c, 0xffffffff, WR_s
|RD_C0
, 0, I1
},
583 {"di", "s", 0x0000477c, 0xffe0ffff, WR_s
|RD_C0
, 0, I1
},
584 {"dins", "t,r,I,+I", 0, (int) M_DINS
, INSN_MACRO
, 0, I3
},
585 {"dins", "t,r,+A,+B",0x5800000c, 0xfc00003f, WR_t
|RD_s
, 0, I3
},
586 {"dinsm", "t,r,+A,+F",0x58000004, 0xfc00003f, WR_t
|RD_s
, 0, I3
},
587 {"dinsu", "t,r,+E,+F",0x58000034, 0xfc00003f, WR_t
|RD_s
, 0, I3
},
588 /* The MIPS assembler treats the div opcode with two operands as
589 though the first operand appeared twice (the first operand is both
590 a source and a destination). To get the div machine instruction,
591 you must use an explicit destination of $0. */
592 {"div", "z,s,t", 0x0000ab3c, 0xfc00ffff, RD_s
|RD_t
|WR_HILO
, 0, I1
},
593 {"div", "z,t", 0x0000ab3c, 0xfc1fffff, RD_s
|RD_t
|WR_HILO
, 0, I1
},
594 {"div", "d,v,t", 0, (int) M_DIV_3
, INSN_MACRO
, 0, I1
},
595 {"div", "d,v,I", 0, (int) M_DIV_3I
, INSN_MACRO
, 0, I1
},
596 {"div.d", "D,V,T", 0x540001f0, 0xfc0007ff, WR_D
|RD_S
|RD_T
|FP_D
, 0, I1
},
597 {"div.s", "D,V,T", 0x540000f0, 0xfc0007ff, WR_D
|RD_S
|RD_T
|FP_S
, 0, I1
},
598 /* For divu, see the comments about div. */
599 {"divu", "z,s,t", 0x0000bb3c, 0xfc00ffff, RD_s
|RD_t
|WR_HILO
, 0, I1
},
600 {"divu", "z,t", 0x0000bb3c, 0xfc1fffff, RD_s
|RD_t
|WR_HILO
, 0, I1
},
601 {"divu", "d,v,t", 0, (int) M_DIVU_3
, INSN_MACRO
, 0, I1
},
602 {"divu", "d,v,I", 0, (int) M_DIVU_3I
, INSN_MACRO
, 0, I1
},
603 {"dla", "t,A(b)", 0, (int) M_DLA_AB
, INSN_MACRO
, 0, I3
},
604 {"dlca", "t,A(b)", 0, (int) M_DLCA_AB
, INSN_MACRO
, 0, I3
},
605 {"dli", "t,j", 0x30000000, 0xfc1f0000, WR_t
, 0, I3
}, /* addiu */
606 {"dli", "t,i", 0x50000000, 0xfc1f0000, WR_t
, 0, I3
}, /* ori */
607 {"dli", "t,I", 0, (int) M_DLI
, INSN_MACRO
, 0, I3
},
608 {"dmfc0", "t,G", 0x580000fc, 0xfc00ffff, WR_t
|RD_C0
, 0, I3
},
609 {"dmfc0", "t,G,H", 0x580000fc, 0xfc00c7ff, WR_t
|RD_C0
, 0, I3
},
610 {"dmfgc0", "t,G", 0x580000e7, 0xfc00ffff, WR_t
|RD_C0
, 0, 0, IVIRT64
},
611 {"dmfgc0", "t,G,H", 0x580000e7, 0xfc00c7ff, WR_t
|RD_C0
, 0, 0, IVIRT64
},
612 {"dmtc0", "t,G", 0x580002fc, 0xfc00ffff, RD_t
|WR_C0
|WR_CC
, 0, I3
},
613 {"dmtc0", "t,G,H", 0x580002fc, 0xfc00c7ff, RD_t
|WR_C0
|WR_CC
, 0, I3
},
614 {"dmtgc0", "t,G", 0x580002e7, 0xfc00ffff, RD_t
|WR_C0
|WR_CC
, 0, 0, IVIRT64
},
615 {"dmtgc0", "t,G,H", 0x580002e7, 0xfc00c7ff, RD_t
|WR_C0
|WR_CC
, 0, 0, IVIRT64
},
616 {"dmfc1", "t,S", 0x5400243b, 0xfc00ffff, WR_t
|RD_S
|FP_S
, 0, I3
},
617 {"dmfc1", "t,G", 0x5400243b, 0xfc00ffff, WR_t
|RD_S
|FP_S
, 0, I3
},
618 {"dmtc1", "t,G", 0x54002c3b, 0xfc00ffff, RD_t
|WR_S
|FP_S
, 0, I3
},
619 {"dmtc1", "t,S", 0x54002c3b, 0xfc00ffff, RD_t
|WR_S
|FP_S
, 0, I3
},
620 {"dmfc2", "t,G", 0x00006d3c, 0xfc00ffff, WR_t
|RD_C2
, 0, I3
},
621 /*{"dmfc2", "t,G,H", 0x58000283, 0xfc001fff, WR_t|RD_C2, 0, I3 },*/
622 {"dmtc2", "t,G", 0x00007d3c, 0xfc00ffff, RD_t
|WR_C2
|WR_CC
, 0, I3
},
623 /*{"dmtc2", "t,G,H", 0x58000683, 0xfc001fff, RD_t|WR_C2|WR_CC, 0, I3 },*/
624 {"dmul", "d,v,t", 0, (int) M_DMUL
, INSN_MACRO
, 0, I3
},
625 {"dmul", "d,v,I", 0, (int) M_DMUL_I
, INSN_MACRO
, 0, I3
},
626 {"dmulo", "d,v,t", 0, (int) M_DMULO
, INSN_MACRO
, 0, I3
},
627 {"dmulo", "d,v,I", 0, (int) M_DMULO_I
, INSN_MACRO
, 0, I3
},
628 {"dmulou", "d,v,t", 0, (int) M_DMULOU
, INSN_MACRO
, 0, I3
},
629 {"dmulou", "d,v,I", 0, (int) M_DMULOU_I
, INSN_MACRO
, 0, I3
},
630 {"dmult", "s,t", 0x58008b3c, 0xfc00ffff, RD_s
|RD_t
|WR_HILO
, 0, I3
},
631 {"dmultu", "s,t", 0x58009b3c, 0xfc00ffff, RD_s
|RD_t
|WR_HILO
, 0, I3
},
632 {"dneg", "d,w", 0x58000190, 0xfc1f07ff, WR_d
|RD_t
, 0, I3
}, /* dsub 0 */
633 {"dnegu", "d,w", 0x580001d0, 0xfc1f07ff, WR_d
|RD_t
, 0, I3
}, /* dsubu 0 */
634 {"drem", "z,s,t", 0x5800ab3c, 0xfc00ffff, RD_s
|RD_t
|WR_HILO
, 0, I3
},
635 {"drem", "d,v,t", 0, (int) M_DREM_3
, INSN_MACRO
, 0, I3
},
636 {"drem", "d,v,I", 0, (int) M_DREM_3I
, INSN_MACRO
, 0, I3
},
637 {"dremu", "z,s,t", 0x5800bb3c, 0xfc00ffff, RD_s
|RD_t
|WR_HILO
, 0, I3
},
638 {"dremu", "d,v,t", 0, (int) M_DREMU_3
, INSN_MACRO
, 0, I3
},
639 {"dremu", "d,v,I", 0, (int) M_DREMU_3I
, INSN_MACRO
, 0, I3
},
640 {"drol", "d,v,t", 0, (int) M_DROL
, INSN_MACRO
, 0, I3
},
641 {"drol", "d,v,I", 0, (int) M_DROL_I
, INSN_MACRO
, 0, I3
},
642 {"dror", "d,v,t", 0, (int) M_DROR
, INSN_MACRO
, 0, I3
},
643 {"dror", "d,v,I", 0, (int) M_DROR_I
, INSN_MACRO
, 0, I3
},
644 {"dror", "t,r,<", 0x580000c0, 0xfc0007ff, WR_t
|RD_s
, 0, I3
},
645 {"drorv", "d,t,s", 0x580000d0, 0xfc0007ff, RD_t
|RD_s
|WR_d
, 0, I3
},
646 {"dror32", "t,r,<", 0x580000c8, 0xfc0007ff, WR_t
|RD_s
, 0, I3
},
647 {"drotl", "d,v,t", 0, (int) M_DROL
, INSN_MACRO
, 0, I3
},
648 {"drotl", "d,v,I", 0, (int) M_DROL_I
, INSN_MACRO
, 0, I3
},
649 {"drotr", "d,v,t", 0, (int) M_DROR
, INSN_MACRO
, 0, I3
},
650 {"drotr", "d,v,I", 0, (int) M_DROR_I
, INSN_MACRO
, 0, I3
},
651 {"drotrv", "d,t,s", 0x580000d0, 0xfc0007ff, RD_t
|RD_s
|WR_d
, 0, I3
},
652 {"drotr32", "t,r,<", 0x580000c8, 0xfc0007ff, WR_t
|RD_s
, 0, I3
},
653 {"dsbh", "t,r", 0x58007b3c, 0xfc00ffff, WR_t
|RD_s
, 0, I3
},
654 {"dshd", "t,r", 0x5800fb3c, 0xfc00ffff, WR_t
|RD_s
, 0, I3
},
655 {"dsllv", "d,t,s", 0x58000010, 0xfc0007ff, WR_d
|RD_t
|RD_s
, 0, I3
},
656 {"dsll32", "t,r,<", 0x58000008, 0xfc0007ff, WR_t
|RD_s
, 0, I3
},
657 {"dsll", "d,t,s", 0x58000010, 0xfc0007ff, WR_d
|RD_t
|RD_s
, 0, I3
}, /* dsllv */
658 {"dsll", "t,r,>", 0x58000008, 0xfc0007ff, WR_t
|RD_s
, 0, I3
}, /* dsll32 */
659 {"dsll", "t,r,<", 0x58000000, 0xfc0007ff, WR_t
|RD_s
, 0, I3
},
660 {"dsrav", "d,t,s", 0x58000090, 0xfc0007ff, WR_d
|RD_t
|RD_s
, 0, I3
},
661 {"dsra32", "t,r,<", 0x58000088, 0xfc0007ff, WR_t
|RD_s
, 0, I3
},
662 {"dsra", "d,t,s", 0x58000090, 0xfc0007ff, WR_d
|RD_t
|RD_s
, 0, I3
}, /* dsrav */
663 {"dsra", "t,r,>", 0x58000088, 0xfc0007ff, WR_t
|RD_s
, 0, I3
}, /* dsra32 */
664 {"dsra", "t,r,<", 0x58000080, 0xfc0007ff, WR_t
|RD_s
, 0, I3
},
665 {"dsrlv", "d,t,s", 0x58000050, 0xfc0007ff, WR_d
|RD_t
|RD_s
, 0, I3
},
666 {"dsrl32", "t,r,<", 0x58000048, 0xfc0007ff, WR_t
|RD_s
, 0, I3
},
667 {"dsrl", "d,t,s", 0x58000050, 0xfc0007ff, WR_d
|RD_t
|RD_s
, 0, I3
}, /* dsrlv */
668 {"dsrl", "t,r,>", 0x58000048, 0xfc0007ff, WR_t
|RD_s
, 0, I3
}, /* dsrl32 */
669 {"dsrl", "t,r,<", 0x58000040, 0xfc0007ff, WR_t
|RD_s
, 0, I3
},
670 {"dsub", "d,v,t", 0x58000190, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, I3
},
671 {"dsub", "d,v,I", 0, (int) M_DSUB_I
, INSN_MACRO
, 0, I3
},
672 {"dsubu", "d,v,t", 0x580001d0, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, I3
},
673 {"dsubu", "d,v,I", 0, (int) M_DSUBU_I
, INSN_MACRO
, 0, I3
},
674 {"ei", "", 0x0000577c, 0xffffffff, WR_s
|WR_C0
, 0, I1
},
675 {"ei", "s", 0x0000577c, 0xffe0ffff, WR_s
|WR_C0
, 0, I1
},
676 {"eret", "", 0x0000f37c, 0xffffffff, NODS
, 0, I1
},
677 {"ext", "t,r,+A,+C", 0x0000002c, 0xfc00003f, WR_t
|RD_s
, 0, I1
},
678 {"floor.l.d", "T,V", 0x5400433b, 0xfc00ffff, WR_T
|RD_S
|FP_D
, 0, I1
},
679 {"floor.l.s", "T,V", 0x5400033b, 0xfc00ffff, WR_T
|RD_S
|FP_S
|FP_D
, 0, I1
},
680 {"floor.w.d", "T,V", 0x54004b3b, 0xfc00ffff, WR_T
|RD_S
|FP_S
|FP_D
, 0, I1
},
681 {"floor.w.s", "T,V", 0x54000b3b, 0xfc00ffff, WR_T
|RD_S
|FP_S
, 0, I1
},
682 {"hypcall", "", 0x0000c37c, 0xffffffff, TRAP
, 0, 0, IVIRT
},
683 {"hypcall", "B", 0x0000c37c, 0xfc00ffff, TRAP
, 0, 0, IVIRT
},
684 {"ins", "t,r,+A,+B", 0x0000000c, 0xfc00003f, WR_t
|RD_s
, 0, I1
},
685 {"iret", "", 0x0000d37c, 0xffffffff, NODS
, 0, 0, MC
},
686 {"jr", "mj", 0x4580, 0xffe0, UBD
, RD_mj
, I1
},
687 {"jr", "s", 0x00000f3c, 0xffe0ffff, UBD
|RD_s
, BD32
, I1
}, /* jalr */
688 {"jrs", "s", 0x00004f3c, 0xffe0ffff, UBD
|RD_s
, BD16
, I1
}, /* jalrs */
689 {"jraddiusp", "mP", 0x4700, 0xffe0, NODS
, UBR
|RD_31
|WR_sp
|RD_sp
, I1
},
690 /* This macro is after the real instruction so that it only matches with
692 {"jraddiusp", "mP", 0, (int) M_JRADDIUSP
, INSN_MACRO
, 0, I1
},
693 {"jrc", "mj", 0x45a0, 0xffe0, NODS
, UBR
|RD_mj
, I1
},
694 /* This macro is after the real instruction so that it only matches with
696 {"jrc", "s", 0, (int) M_JRC
, INSN_MACRO
, 0, I1
},
697 {"jr.hb", "s", 0x00001f3c, 0xffe0ffff, UBD
|RD_s
, BD32
, I1
}, /* jalr.hb */
698 {"jrs.hb", "s", 0x00005f3c, 0xffe0ffff, UBD
|RD_s
, BD16
, I1
}, /* jalrs.hb */
699 {"j", "mj", 0x4580, 0xffe0, UBD
, RD_mj
, I1
}, /* jr */
700 {"j", "s", 0x00000f3c, 0xffe0ffff, UBD
|RD_s
, BD32
, I1
}, /* jr */
701 /* SVR4 PIC code requires special handling for j, so it must be a
703 {"j", "a", 0, (int) M_J_A
, INSN_MACRO
, 0, I1
},
704 /* This form of j is used by the disassembler and internally by the
705 assembler, but will never match user input (because the line above
706 will match first). */
707 {"j", "a", 0xd4000000, 0xfc000000, UBD
, 0, I1
},
708 {"jalr", "mj", 0x45c0, 0xffe0, UBD
|WR_31
, RD_mj
|BD32
, I1
},
709 {"jalr", "my,mj", 0x45c0, 0xffe0, UBD
|WR_31
, RD_mj
|BD32
, I1
},
710 {"jalr", "s", 0x03e00f3c, 0xffe0ffff, UBD
|RD_s
|WR_t
, BD32
, I1
},
711 {"jalr", "t,s", 0x00000f3c, 0xfc00ffff, UBD
|RD_s
|WR_t
, BD32
, I1
},
712 {"jalr.hb", "s", 0x03e01f3c, 0xffe0ffff, UBD
|RD_s
|WR_t
, BD32
, I1
},
713 {"jalr.hb", "t,s", 0x00001f3c, 0xfc00ffff, UBD
|RD_s
|WR_t
, BD32
, I1
},
714 {"jalrs", "mj", 0x45e0, 0xffe0, UBD
|WR_31
, RD_mj
|BD16
, I1
},
715 {"jalrs", "my,mj", 0x45e0, 0xffe0, UBD
|WR_31
, RD_mj
|BD16
, I1
},
716 {"jalrs", "s", 0x03e04f3c, 0xffe0ffff, UBD
|RD_s
|WR_t
, BD16
, I1
},
717 {"jalrs", "t,s", 0x00004f3c, 0xfc00ffff, UBD
|RD_s
|WR_t
, BD16
, I1
},
718 {"jalrs.hb", "s", 0x03e05f3c, 0xffe0ffff, UBD
|RD_s
|WR_t
, BD16
, I1
},
719 {"jalrs.hb", "t,s", 0x00005f3c, 0xfc00ffff, UBD
|RD_s
|WR_t
, BD16
, I1
},
720 /* SVR4 PIC code requires special handling for jal, so it must be a
722 {"jal", "d,s", 0, (int) M_JAL_2
, INSN_MACRO
, 0, I1
},
723 {"jal", "s", 0, (int) M_JAL_1
, INSN_MACRO
, 0, I1
},
724 {"jal", "a", 0, (int) M_JAL_A
, INSN_MACRO
, 0, I1
},
725 /* This form of jal is used by the disassembler and internally by the
726 assembler, but will never match user input (because the line above
727 will match first). */
728 {"jal", "a", 0xf4000000, 0xfc000000, UBD
|WR_31
, BD32
, I1
},
729 {"jals", "d,s", 0, (int) M_JALS_2
, INSN_MACRO
, 0, I1
},
730 {"jals", "s", 0, (int) M_JALS_1
, INSN_MACRO
, 0, I1
},
731 {"jals", "a", 0, (int) M_JALS_A
, INSN_MACRO
, 0, I1
},
732 {"jals", "a", 0x74000000, 0xfc000000, UBD
|WR_31
, BD16
, I1
},
733 {"jalx", "+i", 0xf0000000, 0xfc000000, UBD
|WR_31
, BD32
, I1
},
734 {"la", "t,A(b)", 0, (int) M_LA_AB
, INSN_MACRO
, 0, I1
},
735 {"lb", "t,o(b)", 0x1c000000, 0xfc000000, RD_b
|WR_t
, 0, I1
},
736 {"lb", "t,A(b)", 0, (int) M_LB_AB
, INSN_MACRO
, 0, I1
},
737 {"lbu", "md,mG(ml)", 0x0800, 0xfc00, 0, WR_md
|RD_ml
, I1
},
738 {"lbu", "t,o(b)", 0x14000000, 0xfc000000, RD_b
|WR_t
, 0, I1
},
739 {"lbu", "t,A(b)", 0, (int) M_LBU_AB
, INSN_MACRO
, 0, I1
},
740 {"lca", "t,A(b)", 0, (int) M_LCA_AB
, INSN_MACRO
, 0, I1
},
741 /* The macro has to be first to handle o32 correctly. */
742 {"ld", "t,A(b)", 0, (int) M_LD_AB
, INSN_MACRO
, 0, I1
},
743 {"ld", "t,o(b)", 0xdc000000, 0xfc000000, RD_b
|WR_t
, 0, I3
},
744 {"ldc1", "T,o(b)", 0xbc000000, 0xfc000000, RD_b
|WR_T
|FP_D
, 0, I1
},
745 {"ldc1", "E,o(b)", 0xbc000000, 0xfc000000, RD_b
|WR_T
|FP_D
, 0, I1
},
746 {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB
, INSN_MACRO
, INSN2_M_FP_D
, I1
},
747 {"ldc1", "E,A(b)", 0, (int) M_LDC1_AB
, INSN_MACRO
, INSN2_M_FP_D
, I1
},
748 {"ldc2", "E,~(b)", 0x20002000, 0xfc00f000, RD_b
|WR_CC
, 0, I1
},
749 {"ldc2", "E,A(b)", 0, (int) M_LDC2_AB
, INSN_MACRO
, 0, I1
},
750 {"l.d", "T,o(b)", 0xbc000000, 0xfc000000, RD_b
|WR_T
|FP_D
, 0, I1
}, /* ldc1 */
751 {"l.d", "T,A(b)", 0, (int) M_LDC1_AB
, INSN_MACRO
, INSN2_M_FP_D
, I1
},
752 {"ldl", "t,~(b)", 0x60004000, 0xfc00f000, WR_t
|RD_b
, 0, I3
},
753 {"ldl", "t,A(b)", 0, (int) M_LDL_AB
, INSN_MACRO
, 0, I3
},
754 {"ldm", "n,~(b)", 0x20007000, 0xfc00f000, RD_b
, 0, I3
},
755 {"ldm", "n,A(b)", 0, (int) M_LDM_AB
, INSN_MACRO
, 0, I3
},
756 {"ldp", "t,~(b)", 0x20004000, 0xfc00f000, RD_b
|WR_t
, 0, I3
},
757 {"ldp", "t,A(b)", 0, (int) M_LDP_AB
, INSN_MACRO
, 0, I3
},
758 {"ldr", "t,~(b)", 0x60005000, 0xfc00f000, WR_t
|RD_b
, 0, I3
},
759 {"ldr", "t,A(b)", 0, (int) M_LDR_AB
, INSN_MACRO
, 0, I3
},
760 {"ldxc1", "D,t(b)", 0x540000c8, 0xfc0007ff, WR_D
|RD_t
|RD_b
|FP_D
, 0, I1
},
761 {"lh", "t,o(b)", 0x3c000000, 0xfc000000, RD_b
|WR_t
, 0, I1
},
762 {"lh", "t,A(b)", 0, (int) M_LH_AB
, INSN_MACRO
, 0, I1
},
763 {"lhu", "md,mH(ml)", 0x2800, 0xfc00, 0, WR_md
|RD_ml
, I1
},
764 {"lhu", "t,o(b)", 0x34000000, 0xfc000000, RD_b
|WR_t
, 0, I1
},
765 {"lhu", "t,A(b)", 0, (int) M_LHU_AB
, INSN_MACRO
, 0, I1
},
766 /* li is at the start of the table. */
767 {"li.d", "t,F", 0, (int) M_LI_D
, INSN_MACRO
, INSN2_M_FP_D
, I1
},
768 {"li.d", "T,L", 0, (int) M_LI_DD
, INSN_MACRO
, INSN2_M_FP_D
, I1
},
769 {"li.s", "t,f", 0, (int) M_LI_S
, INSN_MACRO
, INSN2_M_FP_S
, I1
},
770 {"li.s", "T,l", 0, (int) M_LI_SS
, INSN_MACRO
, INSN2_M_FP_S
, I1
},
771 {"ll", "t,~(b)", 0x60003000, 0xfc00f000, RD_b
|WR_t
, 0, I1
},
772 {"ll", "t,A(b)", 0, (int) M_LL_AB
, INSN_MACRO
, 0, I1
},
773 {"lld", "t,~(b)", 0x60007000, 0xfc00f000, RD_b
|WR_t
, 0, I3
},
774 {"lld", "t,A(b)", 0, (int) M_LLD_AB
, INSN_MACRO
, 0, I3
},
775 {"lui", "s,u", 0x41a00000, 0xffe00000, WR_s
, 0, I1
},
776 {"luxc1", "D,t(b)", 0x54000148, 0xfc0007ff, WR_D
|RD_t
|RD_b
|FP_D
, 0, I1
},
777 {"lw", "md,mJ(ml)", 0x6800, 0xfc00, 0, WR_md
|RD_ml
, I1
},
778 {"lw", "mp,mU(ms)", 0x4800, 0xfc00, 0, WR_mp
|RD_sp
, I1
}, /* lwsp */
779 {"lw", "md,mA(ma)", 0x6400, 0xfc00, 0, WR_md
|RD_gp
, I1
}, /* lwgp */
780 {"lw", "t,o(b)", 0xfc000000, 0xfc000000, RD_b
|WR_t
, 0, I1
},
781 {"lw", "t,A(b)", 0, (int) M_LW_AB
, INSN_MACRO
, 0, I1
},
782 {"lwc1", "T,o(b)", 0x9c000000, 0xfc000000, RD_b
|WR_T
|FP_S
, 0, I1
},
783 {"lwc1", "E,o(b)", 0x9c000000, 0xfc000000, RD_b
|WR_T
|FP_S
, 0, I1
},
784 {"lwc1", "T,A(b)", 0, (int) M_LWC1_AB
, INSN_MACRO
, INSN2_M_FP_S
, I1
},
785 {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB
, INSN_MACRO
, INSN2_M_FP_S
, I1
},
786 {"lwc2", "E,~(b)", 0x20000000, 0xfc00f000, RD_b
|WR_CC
, 0, I1
},
787 {"lwc2", "E,A(b)", 0, (int) M_LWC2_AB
, INSN_MACRO
, 0, I1
},
788 {"l.s", "T,o(b)", 0x9c000000, 0xfc000000, RD_b
|WR_T
|FP_S
, 0, I1
}, /* lwc1 */
789 {"l.s", "T,A(b)", 0, (int) M_LWC1_AB
, INSN_MACRO
, INSN2_M_FP_S
, I1
},
790 {"lwl", "t,~(b)", 0x60000000, 0xfc00f000, RD_b
|WR_t
, 0, I1
},
791 {"lwl", "t,A(b)", 0, (int) M_LWL_AB
, INSN_MACRO
, 0, I1
},
792 {"lcache", "t,~(b)", 0x60000000, 0xfc00f000, RD_b
|WR_t
, 0, I1
}, /* same */
793 {"lcache", "t,A(b)", 0, (int) M_LWL_AB
, INSN_MACRO
, 0, I1
},
794 {"lwm", "mN,mJ(ms)", 0x4500, 0xffc0, NODS
, RD_sp
, I1
},
795 {"lwm", "n,~(b)", 0x20005000, 0xfc00f000, RD_b
|NODS
, 0, I1
},
796 {"lwm", "n,A(b)", 0, (int) M_LWM_AB
, INSN_MACRO
, 0, I1
},
797 {"lwp", "t,~(b)", 0x20001000, 0xfc00f000, RD_b
|WR_t
|NODS
, 0, I1
},
798 {"lwp", "t,A(b)", 0, (int) M_LWP_AB
, INSN_MACRO
, 0, I1
},
799 {"lwr", "t,~(b)", 0x60001000, 0xfc00f000, RD_b
|WR_t
, 0, I1
},
800 {"lwr", "t,A(b)", 0, (int) M_LWR_AB
, INSN_MACRO
, 0, I1
},
801 {"lwu", "t,~(b)", 0x6000e000, 0xfc00f000, RD_b
|WR_t
, 0, I3
},
802 {"lwu", "t,A(b)", 0, (int) M_LWU_AB
, INSN_MACRO
, 0, I3
},
803 {"lwxc1", "D,t(b)", 0x54000048, 0xfc0007ff, WR_D
|RD_t
|RD_b
|FP_S
, 0, I1
},
804 {"flush", "t,~(b)", 0x60001000, 0xfc00f000, RD_b
|WR_t
, 0, I1
}, /* same */
805 {"flush", "t,A(b)", 0, (int) M_LWR_AB
, INSN_MACRO
, 0, I1
},
806 {"lwxs", "d,t(b)", 0x00000118, 0xfc0007ff, RD_b
|RD_t
|WR_d
, 0, I1
},
807 {"madd", "s,t", 0x0000cb3c, 0xfc00ffff, RD_s
|RD_t
|MOD_HILO
, 0, I1
},
808 {"madd", "7,s,t", 0x00000abc, 0xfc003fff, MOD_a
|RD_s
|RD_t
, 0, 0, D32
},
809 {"madd.d", "D,R,S,T", 0x54000009, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_D
, 0, I1
},
810 {"madd.s", "D,R,S,T", 0x54000001, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_S
, 0, I1
},
811 {"madd.ps", "D,R,S,T", 0x54000011, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_D
, 0, I1
},
812 {"maddu", "s,t", 0x0000db3c, 0xfc00ffff, RD_s
|RD_t
|MOD_HILO
, 0, I1
},
813 {"maddu", "7,s,t", 0x00001abc, 0xfc003fff, MOD_a
|RD_s
|RD_t
, 0, 0, D32
},
814 {"mfc0", "t,G", 0x000000fc, 0xfc00ffff, WR_t
|RD_C0
, 0, I1
},
815 {"mfc0", "t,G,H", 0x000000fc, 0xfc00c7ff, WR_t
|RD_C0
, 0, I1
},
816 {"mfc1", "t,S", 0x5400203b, 0xfc00ffff, WR_t
|RD_S
|FP_S
, 0, I1
},
817 {"mfc1", "t,G", 0x5400203b, 0xfc00ffff, WR_t
|RD_S
|FP_S
, 0, I1
},
818 {"mfc2", "t,G", 0x00004d3c, 0xfc00ffff, WR_t
|RD_C2
, 0, I1
},
819 {"mfgc0", "t,G", 0x000004fc, 0xfc00ffff, WR_t
|RD_C0
, 0, 0, IVIRT
},
820 {"mfgc0", "t,G,H", 0x000004fc, 0xfc00c7ff, WR_t
|RD_C0
, 0, 0, IVIRT
},
821 {"mfhc1", "t,S", 0x5400303b, 0xfc00ffff, WR_t
|RD_S
|FP_D
, 0, I1
},
822 {"mfhc1", "t,G", 0x5400303b, 0xfc00ffff, WR_t
|RD_S
|FP_D
, 0, I1
},
823 {"mfhc2", "t,G", 0x00008d3c, 0xfc00ffff, WR_t
|RD_C2
, 0, I1
},
824 {"mfhi", "mj", 0x4600, 0xffe0, RD_HI
, WR_mj
, I1
},
825 {"mfhi", "s", 0x00000d7c, 0xffe0ffff, WR_s
|RD_HI
, 0, I1
},
826 {"mfhi", "s,7", 0x0000007c, 0xffe03fff, WR_s
|RD_HI
, 0, 0, D32
},
827 {"mflo", "mj", 0x4640, 0xffe0, RD_LO
, WR_mj
, I1
},
828 {"mflo", "s", 0x00001d7c, 0xffe0ffff, WR_s
|RD_LO
, 0, I1
},
829 {"mflo", "s,7", 0x0000107c, 0xffe03fff, WR_s
|RD_LO
, 0, 0, D32
},
830 {"mov.d", "T,S", 0x5400207b, 0xfc00ffff, WR_T
|RD_S
|FP_D
, 0, I1
},
831 {"mov.s", "T,S", 0x5400007b, 0xfc00ffff, WR_T
|RD_S
|FP_S
, 0, I1
},
832 {"mov.ps", "T,S", 0x5400407b, 0xfc00ffff, WR_T
|RD_S
|FP_D
, 0, I1
},
833 {"movep", "mh,mm,mn", 0x8400, 0xfc01, NODS
, WR_mh
|RD_mmn
, I1
},
834 /* This macro is after the real instruction so that it only matches with
836 {"movep", "mh,mm,mn", 0, (int) M_MOVEP
, INSN_MACRO
, 0, I1
},
837 {"movf", "t,s,M", 0x5400017b, 0xfc001fff, WR_t
|RD_s
|RD_CC
|FP_S
|FP_D
, 0, I1
},
838 {"movf.d", "T,S,M", 0x54000220, 0xfc001fff, WR_T
|RD_S
|RD_CC
|FP_D
, 0, I1
},
839 {"movf.s", "T,S,M", 0x54000020, 0xfc001fff, WR_T
|RD_S
|RD_CC
|FP_S
, 0, I1
},
840 {"movf.ps", "T,S,M", 0x54000420, 0xfc001fff, WR_T
|RD_S
|RD_CC
|FP_D
, 0, I1
},
841 {"movn", "d,v,t", 0x00000018, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, I1
},
842 {"movn.d", "D,S,t", 0x54000138, 0xfc0007ff, WR_D
|RD_S
|RD_t
|FP_D
, 0, I1
},
843 {"movn.s", "D,S,t", 0x54000038, 0xfc0007ff, WR_D
|RD_S
|RD_t
|FP_S
, 0, I1
},
844 {"movn.ps", "D,S,t", 0x54000238, 0xfc0007ff, WR_D
|RD_S
|RD_t
|FP_D
, 0, I1
},
845 {"movt", "t,s,M", 0x5400097b, 0xfc001fff, WR_t
|RD_s
|RD_CC
|FP_S
|FP_D
, 0, I1
},
846 {"movt.d", "T,S,M", 0x54000260, 0xfc001fff, WR_T
|RD_S
|RD_CC
|FP_D
, 0, I1
},
847 {"movt.s", "T,S,M", 0x54000060, 0xfc001fff, WR_T
|RD_S
|RD_CC
|FP_S
, 0, I1
},
848 {"movt.ps", "T,S,M", 0x54000460, 0xfc001fff, WR_T
|RD_S
|RD_CC
|FP_D
, 0, I1
},
849 {"movz", "d,v,t", 0x00000058, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, I1
},
850 {"movz.d", "D,S,t", 0x54000178, 0xfc0007ff, WR_D
|RD_S
|RD_t
|FP_D
, 0, I1
},
851 {"movz.s", "D,S,t", 0x54000078, 0xfc0007ff, WR_D
|RD_S
|RD_t
|FP_S
, 0, I1
},
852 {"movz.ps", "D,S,t", 0x54000278, 0xfc0007ff, WR_D
|RD_S
|RD_t
|FP_D
, 0, I1
},
853 {"msub", "s,t", 0x0000eb3c, 0xfc00ffff, RD_s
|RD_t
|MOD_HILO
, 0, I1
},
854 {"msub", "7,s,t", 0x00002abc, 0xfc003fff, MOD_a
|RD_s
|RD_t
, 0, 0, D32
},
855 {"msub.d", "D,R,S,T", 0x54000029, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_D
, 0, I1
},
856 {"msub.s", "D,R,S,T", 0x54000021, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_S
, 0, I1
},
857 {"msub.ps", "D,R,S,T", 0x54000031, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_D
, 0, I1
},
858 {"msubu", "s,t", 0x0000fb3c, 0xfc00ffff, RD_s
|RD_t
|MOD_HILO
, 0, I1
},
859 {"msubu", "7,s,t", 0x00003abc, 0xfc003fff, MOD_a
|RD_s
|RD_t
, 0, 0, D32
},
860 {"mtc0", "t,G", 0x000002fc, 0xfc00ffff, RD_t
|WR_C0
|WR_CC
, 0, I1
},
861 {"mtc0", "t,G,H", 0x000002fc, 0xfc00c7ff, RD_t
|WR_C0
|WR_CC
, 0, I1
},
862 {"mtc1", "t,S", 0x5400283b, 0xfc00ffff, RD_t
|WR_S
|FP_S
, 0, I1
},
863 {"mtc1", "t,G", 0x5400283b, 0xfc00ffff, RD_t
|WR_S
|FP_S
, 0, I1
},
864 {"mtc2", "t,G", 0x00005d3c, 0xfc00ffff, RD_t
|WR_C2
|WR_CC
, 0, I1
},
865 {"mtgc0", "t,G", 0x000006fc, 0xfc00ffff, RD_t
|WR_C0
|WR_CC
, 0, 0, IVIRT
},
866 {"mtgc0", "t,G,H", 0x000006fc, 0xfc00c7ff, RD_t
|WR_C0
|WR_CC
, 0, 0, IVIRT
},
867 {"mthc1", "t,S", 0x5400383b, 0xfc00ffff, RD_t
|WR_S
|FP_D
, 0, I1
},
868 {"mthc1", "t,G", 0x5400383b, 0xfc00ffff, RD_t
|WR_S
|FP_D
, 0, I1
},
869 {"mthc2", "t,G", 0x00009d3c, 0xfc00ffff, RD_t
|WR_C2
|WR_CC
, 0, I1
},
870 {"mthi", "s", 0x00002d7c, 0xffe0ffff, RD_s
|WR_HI
, 0, I1
},
871 {"mthi", "s,7", 0x0000207c, 0xffe03fff, RD_s
|WR_HI
, 0, 0, D32
},
872 {"mtlo", "s", 0x00003d7c, 0xffe0ffff, RD_s
|WR_LO
, 0, I1
},
873 {"mtlo", "s,7", 0x0000307c, 0xffe03fff, RD_s
|WR_LO
, 0, 0, D32
},
874 {"mul", "d,v,t", 0x00000210, 0xfc0007ff, WR_d
|RD_s
|RD_t
|WR_HILO
, 0, I1
},
875 {"mul", "d,v,I", 0, (int) M_MUL_I
, INSN_MACRO
, 0, I1
},
876 {"mul.d", "D,V,T", 0x540001b0, 0xfc0007ff, WR_D
|RD_S
|RD_T
|FP_D
, 0, I1
},
877 {"mul.s", "D,V,T", 0x540000b0, 0xfc0007ff, WR_D
|RD_S
|RD_T
|FP_S
, 0, I1
},
878 {"mul.ps", "D,V,T", 0x540002b0, 0xfc0007ff, WR_D
|RD_S
|RD_T
|FP_D
, 0, I1
},
879 {"mulo", "d,v,t", 0, (int) M_MULO
, INSN_MACRO
, 0, I1
},
880 {"mulo", "d,v,I", 0, (int) M_MULO_I
, INSN_MACRO
, 0, I1
},
881 {"mulou", "d,v,t", 0, (int) M_MULOU
, INSN_MACRO
, 0, I1
},
882 {"mulou", "d,v,I", 0, (int) M_MULOU_I
, INSN_MACRO
, 0, I1
},
883 {"mult", "s,t", 0x00008b3c, 0xfc00ffff, RD_s
|RD_t
|WR_HILO
, 0, I1
},
884 {"mult", "7,s,t", 0x00000cbc, 0xfc003fff, WR_a
|RD_s
|RD_t
, 0, 0, D32
},
885 {"multu", "s,t", 0x00009b3c, 0xfc00ffff, RD_s
|RD_t
|WR_HILO
, 0, I1
},
886 {"multu", "7,s,t", 0x00001cbc, 0xfc003fff, WR_a
|RD_s
|RD_t
, 0, 0, D32
},
887 {"neg", "d,w", 0x00000190, 0xfc1f07ff, WR_d
|RD_t
, 0, I1
}, /* sub 0 */
888 {"negu", "d,w", 0x000001d0, 0xfc1f07ff, WR_d
|RD_t
, 0, I1
}, /* subu 0 */
889 {"neg.d", "T,V", 0x54002b7b, 0xfc00ffff, WR_T
|RD_S
|FP_D
, 0, I1
},
890 {"neg.s", "T,V", 0x54000b7b, 0xfc00ffff, WR_T
|RD_S
|FP_S
, 0, I1
},
891 {"neg.ps", "T,V", 0x54004b7b, 0xfc00ffff, WR_T
|RD_S
|FP_D
, 0, I1
},
892 {"nmadd.d", "D,R,S,T", 0x5400000a, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_D
, 0, I1
},
893 {"nmadd.s", "D,R,S,T", 0x54000002, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_S
, 0, I1
},
894 {"nmadd.ps", "D,R,S,T", 0x54000012, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_D
, 0, I1
},
895 {"nmsub.d", "D,R,S,T", 0x5400002a, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_D
, 0, I1
},
896 {"nmsub.s", "D,R,S,T", 0x54000022, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_S
, 0, I1
},
897 {"nmsub.ps", "D,R,S,T", 0x54000032, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_D
, 0, I1
},
898 /* nop is at the start of the table. */
899 {"not", "mf,mg", 0x4400, 0xffc0, 0, WR_mf
|RD_mg
, I1
}, /* put not before nor */
900 {"not", "d,v", 0x000002d0, 0xffe007ff, WR_d
|RD_s
|RD_t
, 0, I1
}, /* nor d,s,0 */
901 {"nor", "mf,mz,mg", 0x4400, 0xffc0, 0, WR_mf
|RD_mg
, I1
}, /* not */
902 {"nor", "mf,mg,mz", 0x4400, 0xffc0, 0, WR_mf
|RD_mg
, I1
}, /* not */
903 {"nor", "d,v,t", 0x000002d0, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, I1
},
904 {"nor", "t,r,I", 0, (int) M_NOR_I
, INSN_MACRO
, 0, I1
},
905 {"or", "mp,mj,mz", 0x0c00, 0xfc00, 0, WR_mp
|RD_mj
, I1
}, /* move */
906 {"or", "mp,mz,mj", 0x0c00, 0xfc00, 0, WR_mp
|RD_mj
, I1
}, /* move */
907 {"or", "mf,mt,mg", 0x44c0, 0xffc0, 0, WR_mf
|RD_mf
|RD_mg
, I1
},
908 {"or", "mf,mg,mx", 0x44c0, 0xffc0, 0, WR_mf
|RD_mf
|RD_mg
, I1
},
909 {"or", "d,v,t", 0x00000290, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, I1
},
910 {"or", "t,r,I", 0, (int) M_OR_I
, INSN_MACRO
, 0, I1
},
911 {"ori", "mp,mj,mZ", 0x0c00, 0xfc00, 0, WR_mp
|RD_mj
, I1
}, /* move */
912 {"ori", "t,r,i", 0x50000000, 0xfc000000, WR_t
|RD_s
, 0, I1
},
913 {"pll.ps", "D,V,T", 0x54000080, 0xfc0007ff, WR_D
|RD_S
|RD_T
|FP_D
, 0, I1
},
914 {"plu.ps", "D,V,T", 0x540000c0, 0xfc0007ff, WR_D
|RD_S
|RD_T
|FP_D
, 0, I1
},
915 {"pul.ps", "D,V,T", 0x54000100, 0xfc0007ff, WR_D
|RD_S
|RD_T
|FP_D
, 0, I1
},
916 {"puu.ps", "D,V,T", 0x54000140, 0xfc0007ff, WR_D
|RD_S
|RD_T
|FP_D
, 0, I1
},
917 /* pref is at the start of the table. */
918 {"recip.d", "T,S", 0x5400523b, 0xfc00ffff, WR_T
|RD_S
|FP_D
, 0, I1
},
919 {"recip.s", "T,S", 0x5400123b, 0xfc00ffff, WR_T
|RD_S
|FP_S
, 0, I1
},
920 {"rem", "z,s,t", 0x0000ab3c, 0xfc00ffff, RD_s
|RD_t
|WR_HILO
, 0, I1
},
921 {"rem", "d,v,t", 0, (int) M_REM_3
, INSN_MACRO
, 0, I1
},
922 {"rem", "d,v,I", 0, (int) M_REM_3I
, INSN_MACRO
, 0, I1
},
923 {"remu", "z,s,t", 0x0000bb3c, 0xfc00ffff, RD_s
|RD_t
|WR_HILO
, 0, I1
},
924 {"remu", "d,v,t", 0, (int) M_REMU_3
, INSN_MACRO
, 0, I1
},
925 {"remu", "d,v,I", 0, (int) M_REMU_3I
, INSN_MACRO
, 0, I1
},
926 {"rdhwr", "t,K", 0x00006b3c, 0xfc00ffff, 0, WR_t
, I1
},
927 {"rdpgpr", "t,r", 0x0000e17c, 0xfc00ffff, WR_t
, 0, I1
},
928 {"rol", "d,v,t", 0, (int) M_ROL
, INSN_MACRO
, 0, I1
},
929 {"rol", "d,v,I", 0, (int) M_ROL_I
, INSN_MACRO
, 0, I1
},
930 {"ror", "d,v,t", 0, (int) M_ROR
, INSN_MACRO
, 0, I1
},
931 {"ror", "d,v,I", 0, (int) M_ROR_I
, INSN_MACRO
, 0, I1
},
932 {"ror", "t,r,<", 0x000000c0, 0xfc0007ff, WR_t
|RD_s
, 0, I1
},
933 {"rorv", "d,t,s", 0x000000d0, 0xfc0007ff, RD_t
|RD_s
|WR_d
, 0, I1
},
934 {"rotl", "d,v,t", 0, (int) M_ROL
, INSN_MACRO
, 0, I1
},
935 {"rotl", "d,v,I", 0, (int) M_ROL_I
, INSN_MACRO
, 0, I1
},
936 {"rotr", "d,v,t", 0, (int) M_ROR
, INSN_MACRO
, 0, I1
},
937 {"rotr", "t,r,<", 0x000000c0, 0xfc0007ff, WR_t
|RD_s
, 0, I1
},
938 {"rotrv", "d,t,s", 0x000000d0, 0xfc0007ff, RD_t
|RD_s
|WR_d
, 0, I1
},
939 {"round.l.d", "T,S", 0x5400733b, 0xfc00ffff, WR_T
|RD_S
|FP_D
, 0, I1
},
940 {"round.l.s", "T,S", 0x5400333b, 0xfc00ffff, WR_T
|RD_S
|FP_S
|FP_D
, 0, I1
},
941 {"round.w.d", "T,S", 0x54007b3b, 0xfc00ffff, WR_T
|RD_S
|FP_S
|FP_D
, 0, I1
},
942 {"round.w.s", "T,S", 0x54003b3b, 0xfc00ffff, WR_T
|RD_S
|FP_S
, 0, I1
},
943 {"rsqrt.d", "T,S", 0x5400423b, 0xfc00ffff, WR_T
|RD_S
|FP_D
, 0, I1
},
944 {"rsqrt.s", "T,S", 0x5400023b, 0xfc00ffff, WR_T
|RD_S
|FP_S
, 0, I1
},
945 {"sb", "mq,mL(ml)", 0x8800, 0xfc00, SM
, RD_mq
|RD_ml
, I1
},
946 {"sb", "t,o(b)", 0x18000000, 0xfc000000, SM
|RD_t
|RD_b
, 0, I1
},
947 {"sb", "t,A(b)", 0, (int) M_SB_AB
, INSN_MACRO
, 0, I1
},
948 {"sc", "t,~(b)", 0x6000b000, 0xfc00f000, SM
|RD_t
|WR_t
|RD_b
, 0, I1
},
949 {"sc", "t,A(b)", 0, (int) M_SC_AB
, INSN_MACRO
, 0, I1
},
950 {"scd", "t,~(b)", 0x6000f000, 0xfc00f000, SM
|RD_t
|WR_t
|RD_b
, 0, I3
},
951 {"scd", "t,A(b)", 0, (int) M_SCD_AB
, INSN_MACRO
, 0, I3
},
952 /* The macro has to be first to handle o32 correctly. */
953 {"sd", "t,A(b)", 0, (int) M_SD_AB
, INSN_MACRO
, 0, I1
},
954 {"sd", "t,o(b)", 0xd8000000, 0xfc000000, SM
|RD_t
|RD_b
, 0, I3
},
955 {"sdbbp", "", 0x46c0, 0xffff, TRAP
, 0, I1
},
956 {"sdbbp", "", 0x0000db7c, 0xffffffff, TRAP
, 0, I1
},
957 {"sdbbp", "mO", 0x46c0, 0xfff0, TRAP
, 0, I1
},
958 {"sdbbp", "B", 0x0000db7c, 0xfc00ffff, TRAP
, 0, I1
},
959 {"sdc1", "T,o(b)", 0xb8000000, 0xfc000000, SM
|RD_T
|RD_b
|FP_D
, 0, I1
},
960 {"sdc1", "E,o(b)", 0xb8000000, 0xfc000000, SM
|RD_T
|RD_b
|FP_D
, 0, I1
},
961 {"sdc1", "T,A(b)", 0, (int) M_SDC1_AB
, INSN_MACRO
, INSN2_M_FP_D
, I1
},
962 {"sdc1", "E,A(b)", 0, (int) M_SDC1_AB
, INSN_MACRO
, INSN2_M_FP_D
, I1
},
963 {"sdc2", "E,~(b)", 0x2000a000, 0xfc00f000, SM
|RD_C2
|RD_b
, 0, I1
},
964 {"sdc2", "E,A(b)", 0, (int) M_SDC2_AB
, INSN_MACRO
, 0, I1
},
965 {"s.d", "T,o(b)", 0xb8000000, 0xfc000000, SM
|RD_T
|RD_b
|FP_D
, 0, I1
}, /* sdc1 */
966 {"s.d", "T,A(b)", 0, (int) M_SDC1_AB
, INSN_MACRO
, INSN2_M_FP_D
, I1
},
967 {"sdl", "t,~(b)", 0x6000c000, 0xfc00f000, SM
|RD_t
|RD_b
, 0, I3
},
968 {"sdl", "t,A(b)", 0, (int) M_SDL_AB
, INSN_MACRO
, 0, I3
},
969 {"sdm", "n,~(b)", 0x2000f000, 0xfc00f000, SM
|RD_b
, 0, I3
},
970 {"sdm", "n,A(b)", 0, (int) M_SDM_AB
, INSN_MACRO
, 0, I3
},
971 {"sdp", "t,~(b)", 0x2000c000, 0xfc00f000, SM
|RD_t
|RD_b
, 0, I3
},
972 {"sdp", "t,A(b)", 0, (int) M_SDP_AB
, INSN_MACRO
, 0, I3
},
973 {"sdr", "t,~(b)", 0x6000d000, 0xfc00f000, SM
|RD_t
|RD_b
, 0, I3
},
974 {"sdr", "t,A(b)", 0, (int) M_SDR_AB
, INSN_MACRO
, 0, I3
},
975 {"sdxc1", "D,t(b)", 0x54000108, 0xfc0007ff, SM
|RD_t
|RD_b
|FP_D
, RD_D
, I1
},
976 {"seb", "t,r", 0x00002b3c, 0xfc00ffff, WR_t
|RD_s
, 0, I1
},
977 {"seh", "t,r", 0x00003b3c, 0xfc00ffff, WR_t
|RD_s
, 0, I1
},
978 {"seq", "d,v,t", 0, (int) M_SEQ
, INSN_MACRO
, 0, I1
},
979 {"seq", "d,v,I", 0, (int) M_SEQ_I
, INSN_MACRO
, 0, I1
},
980 {"sge", "d,v,t", 0, (int) M_SGE
, INSN_MACRO
, 0, I1
},
981 {"sge", "d,v,I", 0, (int) M_SGE_I
, INSN_MACRO
, 0, I1
},
982 {"sgeu", "d,v,t", 0, (int) M_SGEU
, INSN_MACRO
, 0, I1
},
983 {"sgeu", "d,v,I", 0, (int) M_SGEU_I
, INSN_MACRO
, 0, I1
},
984 {"sgt", "d,v,t", 0, (int) M_SGT
, INSN_MACRO
, 0, I1
},
985 {"sgt", "d,v,I", 0, (int) M_SGT_I
, INSN_MACRO
, 0, I1
},
986 {"sgtu", "d,v,t", 0, (int) M_SGTU
, INSN_MACRO
, 0, I1
},
987 {"sgtu", "d,v,I", 0, (int) M_SGTU_I
, INSN_MACRO
, 0, I1
},
988 {"sh", "mq,mH(ml)", 0xa800, 0xfc00, SM
, RD_mq
|RD_ml
, I1
},
989 {"sh", "t,o(b)", 0x38000000, 0xfc000000, SM
|RD_t
|RD_b
, 0, I1
},
990 {"sh", "t,A(b)", 0, (int) M_SH_AB
, INSN_MACRO
, 0, I1
},
991 {"sle", "d,v,t", 0, (int) M_SLE
, INSN_MACRO
, 0, I1
},
992 {"sle", "d,v,I", 0, (int) M_SLE_I
, INSN_MACRO
, 0, I1
},
993 {"sleu", "d,v,t", 0, (int) M_SLEU
, INSN_MACRO
, 0, I1
},
994 {"sleu", "d,v,I", 0, (int) M_SLEU_I
, INSN_MACRO
, 0, I1
},
995 {"sllv", "d,t,s", 0x00000010, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, I1
},
996 {"sll", "md,mc,mM", 0x2400, 0xfc01, 0, WR_md
|RD_mc
, I1
},
997 {"sll", "d,w,s", 0x00000010, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, I1
}, /* sllv */
998 {"sll", "t,r,<", 0x00000000, 0xfc0007ff, WR_t
|RD_s
, 0, I1
},
999 {"slt", "d,v,t", 0x00000350, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, I1
},
1000 {"slt", "d,v,I", 0, (int) M_SLT_I
, INSN_MACRO
, 0, I1
},
1001 {"slti", "t,r,j", 0x90000000, 0xfc000000, WR_t
|RD_s
, 0, I1
},
1002 {"sltiu", "t,r,j", 0xb0000000, 0xfc000000, WR_t
|RD_s
, 0, I1
},
1003 {"sltu", "d,v,t", 0x00000390, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, I1
},
1004 {"sltu", "d,v,I", 0, (int) M_SLTU_I
, INSN_MACRO
, 0, I1
},
1005 {"sne", "d,v,t", 0, (int) M_SNE
, INSN_MACRO
, 0, I1
},
1006 {"sne", "d,v,I", 0, (int) M_SNE_I
, INSN_MACRO
, 0, I1
},
1007 {"sqrt.d", "T,S", 0x54004a3b, 0xfc00ffff, WR_T
|RD_S
|FP_D
, 0, I1
},
1008 {"sqrt.s", "T,S", 0x54000a3b, 0xfc00ffff, WR_T
|RD_S
|FP_S
, 0, I1
},
1009 {"srav", "d,t,s", 0x00000090, 0xfc0007ff, WR_d
|RD_t
|RD_s
, 0, I1
},
1010 {"sra", "d,w,s", 0x00000090, 0xfc0007ff, WR_d
|RD_t
|RD_s
, 0, I1
}, /* srav */
1011 {"sra", "t,r,<", 0x00000080, 0xfc0007ff, WR_t
|RD_s
, 0, I1
},
1012 {"srlv", "d,t,s", 0x00000050, 0xfc0007ff, WR_d
|RD_t
|RD_s
, 0, I1
},
1013 {"srl", "md,mc,mM", 0x2401, 0xfc01, 0, WR_md
|RD_mc
, I1
},
1014 {"srl", "d,w,s", 0x00000050, 0xfc0007ff, WR_d
|RD_t
|RD_s
, 0, I1
}, /* srlv */
1015 {"srl", "t,r,<", 0x00000040, 0xfc0007ff, WR_t
|RD_s
, 0, I1
},
1016 /* ssnop is at the start of the table. */
1017 {"sub", "d,v,t", 0x00000190, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, I1
},
1018 {"sub", "d,v,I", 0, (int) M_SUB_I
, INSN_MACRO
, 0, I1
},
1019 {"sub.d", "D,V,T", 0x54000170, 0xfc0007ff, WR_D
|RD_S
|RD_T
|FP_D
, 0, I1
},
1020 {"sub.s", "D,V,T", 0x54000070, 0xfc0007ff, WR_D
|RD_S
|RD_T
|FP_S
, 0, I1
},
1021 {"sub.ps", "D,V,T", 0x54000270, 0xfc0007ff, WR_D
|RD_S
|RD_T
|FP_D
, 0, I1
},
1022 {"subu", "md,me,ml", 0x0401, 0xfc01, 0, WR_md
|RD_me
|RD_ml
, I1
},
1023 {"subu", "d,v,t", 0x000001d0, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, I1
},
1024 {"subu", "d,v,I", 0, (int) M_SUBU_I
, INSN_MACRO
, 0, I1
},
1025 {"suxc1", "D,t(b)", 0x54000188, 0xfc0007ff, SM
|RD_t
|RD_b
|FP_D
, RD_D
, I1
},
1026 {"sw", "mq,mJ(ml)", 0xe800, 0xfc00, SM
, RD_mq
|RD_ml
, I1
},
1027 {"sw", "mp,mU(ms)", 0xc800, 0xfc00, SM
, RD_mp
|RD_sp
, I1
}, /* swsp */
1028 {"sw", "t,o(b)", 0xf8000000, 0xfc000000, SM
|RD_t
|RD_b
, 0, I1
},
1029 {"sw", "t,A(b)", 0, (int) M_SW_AB
, INSN_MACRO
, 0, I1
},
1030 {"swc1", "T,o(b)", 0x98000000, 0xfc000000, SM
|RD_T
|RD_b
|FP_S
, 0, I1
},
1031 {"swc1", "E,o(b)", 0x98000000, 0xfc000000, SM
|RD_T
|RD_b
|FP_S
, 0, I1
},
1032 {"swc1", "T,A(b)", 0, (int) M_SWC1_AB
, INSN_MACRO
, INSN2_M_FP_S
, I1
},
1033 {"swc1", "E,A(b)", 0, (int) M_SWC1_AB
, INSN_MACRO
, INSN2_M_FP_S
, I1
},
1034 {"swc2", "E,~(b)", 0x20008000, 0xfc00f000, SM
|RD_C2
|RD_b
, 0, I1
},
1035 {"swc2", "E,A(b)", 0, (int) M_SWC2_AB
, INSN_MACRO
, 0, I1
},
1036 {"s.s", "T,o(b)", 0x98000000, 0xfc000000, SM
|RD_T
|RD_b
|FP_S
, 0, I1
}, /* swc1 */
1037 {"s.s", "T,A(b)", 0, (int) M_SWC1_AB
, INSN_MACRO
, INSN2_M_FP_S
, I1
},
1038 {"swl", "t,~(b)", 0x60008000, 0xfc00f000, SM
|RD_t
|RD_b
, 0, I1
},
1039 {"swl", "t,A(b)", 0, (int) M_SWL_AB
, INSN_MACRO
, 0, I1
},
1040 {"scache", "t,~(b)", 0x60008000, 0xfc00f000, SM
|RD_t
|RD_b
, 0, I1
}, /* same */
1041 {"scache", "t,A(b)", 0, (int) M_SWL_AB
, INSN_MACRO
, 0, I1
},
1042 {"swm", "mN,mJ(ms)", 0x4540, 0xffc0, NODS
, RD_sp
, I1
},
1043 {"swm", "n,~(b)", 0x2000d000, 0xfc00f000, SM
|RD_b
|NODS
, 0, I1
},
1044 {"swm", "n,A(b)", 0, (int) M_SWM_AB
, INSN_MACRO
, 0, I1
},
1045 {"swp", "t,~(b)", 0x20009000, 0xfc00f000, SM
|RD_t
|RD_b
|NODS
, 0, I1
},
1046 {"swp", "t,A(b)", 0, (int) M_SWP_AB
, INSN_MACRO
, 0, I1
},
1047 {"swr", "t,~(b)", 0x60009000, 0xfc00f000, SM
|RD_b
|RD_t
, 0, I1
},
1048 {"swr", "t,A(b)", 0, (int) M_SWR_AB
, INSN_MACRO
, 0, I1
},
1049 {"invalidate", "t,~(b)",0x60009000, 0xfc00f000, SM
|RD_b
|RD_t
, 0, I1
}, /* same */
1050 {"invalidate", "t,A(b)",0, (int) M_SWR_AB
, INSN_MACRO
, 0, I1
},
1051 {"swxc1", "D,t(b)", 0x54000088, 0xfc0007ff, SM
|RD_t
|RD_b
|FP_S
, RD_D
, I1
},
1052 {"sync_acquire", "", 0x00116b7c, 0xffffffff, NODS
, 0, I1
},
1053 {"sync_mb", "", 0x00106b7c, 0xffffffff, NODS
, 0, I1
},
1054 {"sync_release", "", 0x00126b7c, 0xffffffff, NODS
, 0, I1
},
1055 {"sync_rmb", "", 0x00136b7c, 0xffffffff, NODS
, 0, I1
},
1056 {"sync_wmb", "", 0x00046b7c, 0xffffffff, NODS
, 0, I1
},
1057 {"sync", "", 0x00006b7c, 0xffffffff, NODS
, 0, I1
},
1058 {"sync", "1", 0x00006b7c, 0xffe0ffff, NODS
, 0, I1
},
1059 {"synci", "o(b)", 0x42000000, 0xffe00000, SM
|RD_b
, 0, I1
},
1060 {"syscall", "", 0x00008b7c, 0xffffffff, TRAP
, 0, I1
},
1061 {"syscall", "B", 0x00008b7c, 0xfc00ffff, TRAP
, 0, I1
},
1062 {"teqi", "s,j", 0x41c00000, 0xffe00000, RD_s
|TRAP
, 0, I1
},
1063 {"teq", "s,t", 0x0000003c, 0xfc00ffff, RD_s
|RD_t
|TRAP
, 0, I1
},
1064 {"teq", "s,t,|", 0x0000003c, 0xfc000fff, RD_s
|RD_t
|TRAP
, 0, I1
},
1065 {"teq", "s,j", 0x41c00000, 0xffe00000, RD_s
|TRAP
, 0, I1
}, /* teqi */
1066 {"teq", "s,I", 0, (int) M_TEQ_I
, INSN_MACRO
, 0, I1
},
1067 {"tgei", "s,j", 0x41200000, 0xffe00000, RD_s
|TRAP
, 0, I1
},
1068 {"tge", "s,t", 0x0000023c, 0xfc00ffff, RD_s
|RD_t
|TRAP
, 0, I1
},
1069 {"tge", "s,t,|", 0x0000023c, 0xfc000fff, RD_s
|RD_t
|TRAP
, 0, I1
},
1070 {"tge", "s,j", 0x41200000, 0xffe00000, RD_s
|TRAP
, 0, I1
}, /* tgei */
1071 {"tge", "s,I", 0, (int) M_TGE_I
, INSN_MACRO
, 0, I1
},
1072 {"tgeiu", "s,j", 0x41600000, 0xffe00000, RD_s
|TRAP
, 0, I1
},
1073 {"tgeu", "s,t", 0x0000043c, 0xfc00ffff, RD_s
|RD_t
|TRAP
, 0, I1
},
1074 {"tgeu", "s,t,|", 0x0000043c, 0xfc000fff, RD_s
|RD_t
|TRAP
, 0, I1
},
1075 {"tgeu", "s,j", 0x41600000, 0xffe00000, RD_s
|TRAP
, 0, I1
}, /* tgeiu */
1076 {"tgeu", "s,I", 0, (int) M_TGEU_I
, INSN_MACRO
, 0, I1
},
1077 {"tlbinv", "", 0x0000437c, 0xffffffff, INSN_TLB
, 0, 0, TLBINV
},
1078 {"tlbinvf", "", 0x0000537c, 0xffffffff, INSN_TLB
, 0, 0, TLBINV
},
1079 {"tlbginv", "", 0x0000417c, 0xffffffff, INSN_TLB
, 0, 0, IVIRT
},
1080 {"tlbginvf","", 0x0000517c, 0xffffffff, INSN_TLB
, 0, 0, IVIRT
},
1081 {"tlbgp", "", 0x0000017c, 0xffffffff, INSN_TLB
, 0, 0, IVIRT
},
1082 {"tlbgr", "", 0x0000117c, 0xffffffff, INSN_TLB
, 0, 0, IVIRT
},
1083 {"tlbgwi", "", 0x0000217c, 0xffffffff, INSN_TLB
, 0, 0, IVIRT
},
1084 {"tlbgwr", "", 0x0000317c, 0xffffffff, INSN_TLB
, 0, 0, IVIRT
},
1085 {"tlbp", "", 0x0000037c, 0xffffffff, INSN_TLB
, 0, I1
},
1086 {"tlbr", "", 0x0000137c, 0xffffffff, INSN_TLB
, 0, I1
},
1087 {"tlbwi", "", 0x0000237c, 0xffffffff, INSN_TLB
, 0, I1
},
1088 {"tlbwr", "", 0x0000337c, 0xffffffff, INSN_TLB
, 0, I1
},
1089 {"tlti", "s,j", 0x41000000, 0xffe00000, RD_s
|TRAP
, 0, I1
},
1090 {"tlt", "s,t", 0x0000083c, 0xfc00ffff, RD_s
|RD_t
|TRAP
, 0, I1
},
1091 {"tlt", "s,t,|", 0x0000083c, 0xfc000fff, RD_s
|RD_t
|TRAP
, 0, I1
},
1092 {"tlt", "s,j", 0x41000000, 0xffe00000, RD_s
|TRAP
, 0, I1
}, /* tlti */
1093 {"tlt", "s,I", 0, (int) M_TLT_I
, INSN_MACRO
, 0, I1
},
1094 {"tltiu", "s,j", 0x41400000, 0xffe00000, RD_s
|TRAP
, 0, I1
},
1095 {"tltu", "s,t", 0x00000a3c, 0xfc00ffff, RD_s
|RD_t
|TRAP
, 0, I1
},
1096 {"tltu", "s,t,|", 0x00000a3c, 0xfc000fff, RD_s
|RD_t
|TRAP
, 0, I1
},
1097 {"tltu", "s,j", 0x41400000, 0xffe00000, RD_s
|TRAP
, 0, I1
}, /* tltiu */
1098 {"tltu", "s,I", 0, (int) M_TLTU_I
, INSN_MACRO
, 0, I1
},
1099 {"tnei", "s,j", 0x41800000, 0xffe00000, RD_s
|TRAP
, 0, I1
},
1100 {"tne", "s,t", 0x00000c3c, 0xfc00ffff, RD_s
|RD_t
|TRAP
, 0, I1
},
1101 {"tne", "s,t,|", 0x00000c3c, 0xfc000fff, RD_s
|RD_t
|TRAP
, 0, I1
},
1102 {"tne", "s,j", 0x41800000, 0xffe00000, RD_s
|TRAP
, 0, I1
}, /* tnei */
1103 {"tne", "s,I", 0, (int) M_TNE_I
, INSN_MACRO
, 0, I1
},
1104 {"trunc.l.d", "T,S", 0x5400633b, 0xfc00ffff, WR_T
|RD_S
|FP_D
, 0, I1
},
1105 {"trunc.l.s", "T,S", 0x5400233b, 0xfc00ffff, WR_T
|RD_S
|FP_S
|FP_D
, 0, I1
},
1106 {"trunc.w.d", "T,S", 0x54006b3b, 0xfc00ffff, WR_T
|RD_S
|FP_S
|FP_D
, 0, I1
},
1107 {"trunc.w.s", "T,S", 0x54002b3b, 0xfc00ffff, WR_T
|RD_S
|FP_S
, 0, I1
},
1108 {"uld", "t,A(b)", 0, (int) M_ULD_AB
, INSN_MACRO
, 0, I3
},
1109 {"ulh", "t,A(b)", 0, (int) M_ULH_AB
, INSN_MACRO
, 0, I1
},
1110 {"ulhu", "t,A(b)", 0, (int) M_ULHU_AB
, INSN_MACRO
, 0, I1
},
1111 {"ulw", "t,A(b)", 0, (int) M_ULW_AB
, INSN_MACRO
, 0, I1
},
1112 {"usd", "t,A(b)", 0, (int) M_USD_AB
, INSN_MACRO
, 0, I1
},
1113 {"ush", "t,A(b)", 0, (int) M_USH_AB
, INSN_MACRO
, 0, I1
},
1114 {"usw", "t,A(b)", 0, (int) M_USW_AB
, INSN_MACRO
, 0, I1
},
1115 {"wait", "", 0x0000937c, 0xffffffff, NODS
, 0, I1
},
1116 {"wait", "B", 0x0000937c, 0xfc00ffff, NODS
, 0, I1
},
1117 {"wrpgpr", "t,r", 0x0000f17c, 0xfc00ffff, RD_s
, 0, I1
},
1118 {"wsbh", "t,r", 0x00007b3c, 0xfc00ffff, WR_t
|RD_s
, 0, I1
},
1119 {"xor", "mf,mt,mg", 0x4440, 0xffc0, 0, WR_mf
|RD_mf
|RD_mg
, I1
},
1120 {"xor", "mf,mg,mx", 0x4440, 0xffc0, 0, WR_mf
|RD_mf
|RD_mg
, I1
},
1121 {"xor", "d,v,t", 0x00000310, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, I1
},
1122 {"xor", "t,r,I", 0, (int) M_XOR_I
, INSN_MACRO
, 0, I1
},
1123 {"xori", "t,r,i", 0x70000000, 0xfc000000, WR_t
|RD_s
, 0, I1
},
1124 /* microMIPS Enhanced VA Scheme */
1125 {"lbue", "t,+j(b)", 0x60006000, 0xfc00fe00, RD_b
|WR_t
, 0, 0, EVA
},
1126 {"lbue", "t,A(b)", 0, (int) M_LBUE_AB
, INSN_MACRO
, 0, 0, EVA
},
1127 {"lhue", "t,+j(b)", 0x60006200, 0xfc00fe00, RD_b
|WR_t
, 0, 0, EVA
},
1128 {"lhue", "t,A(b)", 0, (int) M_LHUE_AB
, INSN_MACRO
, 0, 0, EVA
},
1129 {"lbe", "t,+j(b)", 0x60006800, 0xfc00fe00, RD_b
|WR_t
, 0, 0, EVA
},
1130 {"lbe", "t,A(b)", 0, (int) M_LBE_AB
, INSN_MACRO
, 0, 0, EVA
},
1131 {"lhe", "t,+j(b)", 0x60006a00, 0xfc00fe00, RD_b
|WR_t
, 0, 0, EVA
},
1132 {"lhe", "t,A(b)", 0, (int) M_LHE_AB
, INSN_MACRO
, 0, 0, EVA
},
1133 {"lle", "t,+j(b)", 0x60006c00, 0xfc00fe00, RD_b
|WR_t
, 0, 0, EVA
},
1134 {"lle", "t,A(b)", 0, (int) M_LLE_AB
, INSN_MACRO
, 0, 0, EVA
},
1135 {"lwe", "t,+j(b)", 0x60006e00, 0xfc00fe00, RD_b
|WR_t
, 0, 0, EVA
},
1136 {"lwe", "t,A(b)", 0, (int) M_LWE_AB
, INSN_MACRO
, 0, 0, EVA
},
1137 {"lwle", "t,+j(b)", 0x60006400, 0xfc00fe00, RD_b
|WR_t
, 0, 0, EVA
},
1138 {"lwle", "t,A(b)", 0, (int) M_LWLE_AB
, INSN_MACRO
, 0, 0, EVA
},
1139 {"lwre", "t,+j(b)", 0x60006600, 0xfc00fe00, RD_b
|WR_t
, 0, 0, EVA
},
1140 {"lwre", "t,A(b)", 0, (int) M_LWRE_AB
, INSN_MACRO
, 0, 0, EVA
},
1141 {"sbe", "t,+j(b)", 0x6000a800, 0xfc00fe00, SM
|RD_b
|WR_t
, 0, 0, EVA
},
1142 {"sbe", "t,A(b)", 0, (int) M_SBE_AB
, INSN_MACRO
, 0, 0, EVA
},
1143 {"sce", "t,+j(b)", 0x6000ac00, 0xfc00fe00, SM
|RD_t
|WR_t
|RD_b
, 0, 0, EVA
},
1144 {"sce", "t,A(b)", 0, (int) M_SCE_AB
, INSN_MACRO
, 0, 0, EVA
},
1145 {"she", "t,+j(b)", 0x6000aa00, 0xfc00fe00, SM
|RD_b
|WR_t
, 0, 0, EVA
},
1146 {"she", "t,A(b)", 0, (int) M_SHE_AB
, INSN_MACRO
, 0, 0, EVA
},
1147 {"swe", "t,+j(b)", 0x6000ae00, 0xfc00fe00, SM
|RD_b
|WR_t
, 0, 0, EVA
},
1148 {"swe", "t,A(b)", 0, (int) M_SWE_AB
, INSN_MACRO
, 0, 0, EVA
},
1149 {"swle", "t,+j(b)", 0x6000a000, 0xfc00fe00, SM
|RD_b
|WR_t
, 0, 0, EVA
},
1150 {"swle", "t,A(b)", 0, (int) M_SWLE_AB
, INSN_MACRO
, 0, 0, EVA
},
1151 {"swre", "t,+j(b)", 0x6000a200, 0xfc00fe00, SM
|RD_b
|WR_t
, 0, 0, EVA
},
1152 {"swre", "t,A(b)", 0, (int) M_SWRE_AB
, INSN_MACRO
, 0, 0, EVA
},
1153 {"cachee", "k,+j(b)", 0x6000a600, 0xfc00fe00, RD_b
, 0, 0, EVA
},
1154 {"cachee", "k,A(b)", 0, (int) M_CACHEE_AB
,INSN_MACRO
, 0, 0, EVA
},
1155 {"prefe", "k,+j(b)", 0x6000a400, 0xfc00fe00, RD_b
, 0, 0, EVA
},
1156 {"prefe", "k,A(b)", 0, (int) M_PREFE_AB
, INSN_MACRO
, 0, 0, EVA
},
1158 {"absq_s.ph", "t,s", 0x0000113c, 0xfc00ffff, WR_t
|RD_s
, 0, 0, D32
},
1159 {"absq_s.w", "t,s", 0x0000213c, 0xfc00ffff, WR_t
|RD_s
, 0, 0, D32
},
1160 {"addq.ph", "d,s,t", 0x0000000d, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1161 {"addq_s.ph", "d,s,t", 0x0000040d, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1162 {"addq_s.w", "d,s,t", 0x00000305, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1163 {"addsc", "d,s,t", 0x00000385, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1164 {"addu.qb", "d,s,t", 0x000000cd, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1165 {"addu_s.qb", "d,s,t", 0x000004cd, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1166 {"addwc", "d,s,t", 0x000003c5, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1167 {"bitrev", "t,s", 0x0000313c, 0xfc00ffff, WR_t
|RD_s
, 0, 0, D32
},
1168 {"bposge32", "p", 0x43600000, 0xffff0000, CBD
, 0, 0, D32
},
1169 {"cmp.eq.ph", "s,t", 0x00000005, 0xfc00ffff, RD_s
|RD_t
, 0, 0, D32
},
1170 {"cmpgu.eq.qb", "d,s,t", 0x000000c5, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1171 {"cmp.le.ph", "s,t", 0x00000085, 0xfc00ffff, RD_s
|RD_t
, 0, 0, D32
},
1172 {"cmpgu.le.qb", "d,s,t", 0x00000145, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1173 {"cmp.lt.ph", "s,t", 0x00000045, 0xfc00ffff, RD_s
|RD_t
, 0, 0, D32
},
1174 {"cmpgu.lt.qb", "d,s,t", 0x00000105, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1175 {"cmpu.eq.qb", "s,t", 0x00000245, 0xfc00ffff, RD_s
|RD_t
, 0, 0, D32
},
1176 {"cmpu.le.qb", "s,t", 0x000002c5, 0xfc00ffff, RD_s
|RD_t
, 0, 0, D32
},
1177 {"cmpu.lt.qb", "s,t", 0x00000285, 0xfc00ffff, RD_s
|RD_t
, 0, 0, D32
},
1178 {"dpaq_sa.l.w", "7,s,t", 0x000012bc, 0xfc003fff, MOD_a
|RD_s
|RD_t
, 0, 0, D32
},
1179 {"dpaq_s.w.ph", "7,s,t", 0x000002bc, 0xfc003fff, MOD_a
|RD_s
|RD_t
, 0, 0, D32
},
1180 {"dpau.h.qbl", "7,s,t", 0x000020bc, 0xfc003fff, MOD_a
|RD_s
|RD_t
, 0, 0, D32
},
1181 {"dpau.h.qbr", "7,s,t", 0x000030bc, 0xfc003fff, MOD_a
|RD_s
|RD_t
, 0, 0, D32
},
1182 {"dpsq_sa.l.w", "7,s,t", 0x000016bc, 0xfc003fff, MOD_a
|RD_s
|RD_t
, 0, 0, D32
},
1183 {"dpsq_s.w.ph", "7,s,t", 0x000006bc, 0xfc003fff, MOD_a
|RD_s
|RD_t
, 0, 0, D32
},
1184 {"dpsu.h.qbl", "7,s,t", 0x000024bc, 0xfc003fff, MOD_a
|RD_s
|RD_t
, 0, 0, D32
},
1185 {"dpsu.h.qbr", "7,s,t", 0x000034bc, 0xfc003fff, MOD_a
|RD_s
|RD_t
, 0, 0, D32
},
1186 {"extpdp", "t,7,6", 0x0000367c, 0xfc003fff, WR_t
|RD_a
|DSP_VOLA
, 0, 0, D32
},
1187 {"extpdpv", "t,7,s", 0x000038bc, 0xfc003fff, WR_t
|RD_a
|RD_s
|DSP_VOLA
, 0, 0, D32
},
1188 {"extp", "t,7,6", 0x0000267c, 0xfc003fff, WR_t
|RD_a
, 0, 0, D32
},
1189 {"extpv", "t,7,s", 0x000028bc, 0xfc003fff, WR_t
|RD_a
|RD_s
, 0, 0, D32
},
1190 {"extr_rs.w", "t,7,6", 0x00002e7c, 0xfc003fff, WR_t
|RD_a
, 0, 0, D32
},
1191 {"extr_r.w", "t,7,6", 0x00001e7c, 0xfc003fff, WR_t
|RD_a
, 0, 0, D32
},
1192 {"extr_s.h", "t,7,6", 0x00003e7c, 0xfc003fff, WR_t
|RD_a
, 0, 0, D32
},
1193 {"extrv_rs.w", "t,7,s", 0x00002ebc, 0xfc003fff, WR_t
|RD_a
|RD_s
, 0, 0, D32
},
1194 {"extrv_r.w", "t,7,s", 0x00001ebc, 0xfc003fff, WR_t
|RD_a
|RD_s
, 0, 0, D32
},
1195 {"extrv_s.h", "t,7,s", 0x00003ebc, 0xfc003fff, WR_t
|RD_a
|RD_s
, 0, 0, D32
},
1196 {"extrv.w", "t,7,s", 0x00000ebc, 0xfc003fff, WR_t
|RD_a
|RD_s
, 0, 0, D32
},
1197 {"extr.w", "t,7,6", 0x00000e7c, 0xfc003fff, WR_t
|RD_a
, 0, 0, D32
},
1198 {"insv", "t,s", 0x0000413c, 0xfc00ffff, WR_t
|RD_s
, 0, 0, D32
},
1199 {"lbux", "d,t(b)", 0x00000225, 0xfc0007ff, WR_d
|RD_b
|RD_t
, 0, 0, D32
},
1200 {"lhx", "d,t(b)", 0x00000165, 0xfc0007ff, WR_d
|RD_b
|RD_t
, 0, 0, D32
},
1201 {"lwx", "d,t(b)", 0x000001a5, 0xfc0007ff, WR_d
|RD_b
|RD_t
, 0, 0, D32
},
1202 {"maq_sa.w.phl", "7,s,t", 0x00003a7c, 0xfc003fff, MOD_a
|RD_s
|RD_t
, 0, 0, D32
},
1203 {"maq_sa.w.phr", "7,s,t", 0x00002a7c, 0xfc003fff, MOD_a
|RD_s
|RD_t
, 0, 0, D32
},
1204 {"maq_s.w.phl", "7,s,t", 0x00001a7c, 0xfc003fff, MOD_a
|RD_s
|RD_t
, 0, 0, D32
},
1205 {"maq_s.w.phr", "7,s,t", 0x00000a7c, 0xfc003fff, MOD_a
|RD_s
|RD_t
, 0, 0, D32
},
1206 {"modsub", "d,s,t", 0x00000295, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1207 {"mthlip", "s,7", 0x0000027c, 0xffe03fff, RD_s
|MOD_a
|DSP_VOLA
, 0, 0, D32
},
1208 {"muleq_s.w.phl", "d,s,t", 0x00000025, 0xfc0007ff, WR_d
|RD_s
|RD_t
|WR_HILO
, 0, 0, D32
},
1209 {"muleq_s.w.phr", "d,s,t", 0x00000065, 0xfc0007ff, WR_d
|RD_s
|RD_t
|WR_HILO
, 0, 0, D32
},
1210 {"muleu_s.ph.qbl", "d,s,t", 0x00000095, 0xfc0007ff, WR_d
|RD_s
|RD_t
|WR_HILO
, 0, 0, D32
},
1211 {"muleu_s.ph.qbr", "d,s,t", 0x000000d5, 0xfc0007ff, WR_d
|RD_s
|RD_t
|WR_HILO
, 0, 0, D32
},
1212 {"mulq_rs.ph", "d,s,t", 0x00000115, 0xfc0007ff, WR_d
|RD_s
|RD_t
|WR_HILO
, 0, 0, D32
},
1213 {"mulsaq_s.w.ph", "7,s,t", 0x00003cbc, 0xfc003fff, MOD_a
|RD_s
|RD_t
, 0, 0, D32
},
1214 {"packrl.ph", "d,s,t", 0x000001ad, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1215 {"pick.ph", "d,s,t", 0x0000022d, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1216 {"pick.qb", "d,s,t", 0x000001ed, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1217 {"precequ.ph.qbla", "t,s", 0x0000733c, 0xfc00ffff, WR_t
|RD_s
, 0, 0, D32
},
1218 {"precequ.ph.qbl", "t,s", 0x0000713c, 0xfc00ffff, WR_t
|RD_s
, 0, 0, D32
},
1219 {"precequ.ph.qbra", "t,s", 0x0000933c, 0xfc00ffff, WR_t
|RD_s
, 0, 0, D32
},
1220 {"precequ.ph.qbr", "t,s", 0x0000913c, 0xfc00ffff, WR_t
|RD_s
, 0, 0, D32
},
1221 {"preceq.w.phl", "t,s", 0x0000513c, 0xfc00ffff, WR_t
|RD_s
, 0, 0, D32
},
1222 {"preceq.w.phr", "t,s", 0x0000613c, 0xfc00ffff, WR_t
|RD_s
, 0, 0, D32
},
1223 {"preceu.ph.qbla", "t,s", 0x0000b33c, 0xfc00ffff, WR_t
|RD_s
, 0, 0, D32
},
1224 {"preceu.ph.qbl", "t,s", 0x0000b13c, 0xfc00ffff, WR_t
|RD_s
, 0, 0, D32
},
1225 {"preceu.ph.qbra", "t,s",0x0000d33c, 0xfc00ffff, WR_t
|RD_s
, 0, 0, D32
},
1226 {"preceu.ph.qbr", "t,s", 0x0000d13c, 0xfc00ffff, WR_t
|RD_s
, 0, 0, D32
},
1227 {"precrq.ph.w", "d,s,t", 0x000000ed, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1228 {"precrq.qb.ph", "d,s,t", 0x000000ad, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1229 {"precrq_rs.ph.w", "d,s,t", 0x0000012d, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1230 {"precrqu_s.qb.ph", "d,s,t", 0x0000016d, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1231 {"raddu.w.qb", "t,s", 0x0000f13c, 0xfc00ffff, WR_t
|RD_s
, 0, 0, D32
},
1232 {"rddsp", "t", 0x000fc67c, 0xfc1fffff, WR_t
, 0, 0, D32
},
1233 {"rddsp", "t,8", 0x0000067c, 0xfc103fff, WR_t
, 0, 0, D32
},
1234 {"repl.ph", "d,@", 0x0000003d, 0xfc0007ff, WR_d
, 0, 0, D32
},
1235 {"repl.qb", "t,5", 0x000005fc, 0xfc001fff, WR_t
, 0, 0, D32
},
1236 {"replv.ph", "t,s", 0x0000033c, 0xfc00ffff, WR_t
|RD_s
, 0, 0, D32
},
1237 {"replv.qb", "t,s", 0x0000133c, 0xfc00ffff, WR_t
|RD_s
, 0, 0, D32
},
1238 {"shilo", "7,0", 0x0000001d, 0xffc03fff, MOD_a
, 0, 0, D32
},
1239 {"shilov", "7,s", 0x0000127c, 0xffe03fff, MOD_a
|RD_s
, 0, 0, D32
},
1240 {"shll.ph", "t,s,4", 0x000003b5, 0xfc000fff, WR_t
|RD_s
, 0, 0, D32
},
1241 {"shll.qb", "t,s,3", 0x0000087c, 0xfc001fff, WR_t
|RD_s
, 0, 0, D32
},
1242 {"shll_s.ph", "t,s,4", 0x00000bb5, 0xfc000fff, WR_t
|RD_s
, 0, 0, D32
},
1243 {"shll_s.w", "t,s,^", 0x000003f5, 0xfc0007ff, WR_t
|RD_s
, 0, 0, D32
},
1244 {"shllv.ph", "d,t,s", 0x0000038d, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1245 {"shllv.qb", "d,t,s", 0x00000395, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1246 {"shllv_s.ph", "d,t,s", 0x0000078d, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1247 {"shllv_s.w", "d,t,s", 0x000003d5, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1248 {"shra.ph", "t,s,4", 0x00000335, 0xfc000fff, WR_t
|RD_s
, 0, 0, D32
},
1249 {"shra_r.ph", "t,s,4", 0x00000735, 0xfc000fff, WR_t
|RD_s
, 0, 0, D32
},
1250 {"shra_r.w", "t,s,^", 0x000002f5, 0xfc0007ff, WR_t
|RD_s
, 0, 0, D32
},
1251 {"shrav.ph", "d,t,s", 0x0000018d, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1252 {"shrav_r.ph", "d,t,s", 0x0000058d, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1253 {"shrav_r.w", "d,t,s", 0x000002d5, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1254 {"shrl.qb", "t,s,3", 0x0000187c, 0xfc001fff, WR_t
|RD_s
, 0, 0, D32
},
1255 {"shrlv.qb", "d,t,s", 0x00000355, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1256 {"subq.ph", "d,s,t", 0x0000020d, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1257 {"subq_s.ph", "d,s,t", 0x0000060d, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1258 {"subq_s.w", "d,s,t", 0x00000345, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1259 {"subu.qb", "d,s,t", 0x000002cd, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1260 {"subu_s.qb", "d,s,t", 0x000006cd, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D32
},
1261 {"wrdsp", "t", 0x000fd67c, 0xfc1fffff, RD_t
|DSP_VOLA
, 0, 0, D32
},
1262 {"wrdsp", "t,8", 0x0000167c, 0xfc103fff, RD_t
|DSP_VOLA
, 0, 0, D32
},
1263 /* MIPS DSP ASE Rev2. */
1264 {"absq_s.qb", "t,s", 0x0000013c, 0xfc00ffff, WR_t
|RD_s
, 0, 0, D33
},
1265 {"addqh.ph", "d,s,t", 0x0000004d, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D33
},
1266 {"addqh_r.ph", "d,s,t", 0x0000044d, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D33
},
1267 {"addqh.w", "d,s,t", 0x0000008d, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D33
},
1268 {"addqh_r.w", "d,s,t", 0x0000048d, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D33
},
1269 {"addu.ph", "d,s,t", 0x0000010d, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D33
},
1270 {"addu_s.ph", "d,s,t", 0x0000050d, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D33
},
1271 {"adduh.qb", "d,s,t", 0x0000014d, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D33
},
1272 {"adduh_r.qb", "d,s,t", 0x0000054d, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D33
},
1273 {"append", "t,s,h", 0x00000215, 0xfc0007ff, WR_t
|RD_t
|RD_s
, 0, 0, D33
},
1274 {"balign", "t,s,I", 0, (int) M_BALIGN
, INSN_MACRO
, 0, 0, D33
},
1275 {"balign", "t,s,2", 0x000008bc, 0xfc003fff, WR_t
|RD_t
|RD_s
, 0, 0, D33
},
1276 {"cmpgdu.eq.qb", "d,s,t", 0x00000185, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D33
},
1277 {"cmpgdu.lt.qb", "d,s,t", 0x000001c5, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D33
},
1278 {"cmpgdu.le.qb", "d,s,t", 0x00000205, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D33
},
1279 {"dpa.w.ph", "7,s,t", 0x000000bc, 0xfc003fff, MOD_a
|RD_s
|RD_t
, 0, 0, D33
},
1280 {"dpaqx_s.w.ph", "7,s,t", 0x000022bc, 0xfc003fff, MOD_a
|RD_s
|RD_t
, 0, 0, D33
},
1281 {"dpaqx_sa.w.ph", "7,s,t", 0x000032bc, 0xfc003fff, MOD_a
|RD_s
|RD_t
, 0, 0, D33
},
1282 {"dpax.w.ph", "7,s,t", 0x000010bc, 0xfc003fff, MOD_a
|RD_s
|RD_t
, 0, 0, D33
},
1283 {"dps.w.ph", "7,s,t", 0x000004bc, 0xfc003fff, MOD_a
|RD_s
|RD_t
, 0, 0, D33
},
1284 {"dpsqx_s.w.ph", "7,s,t", 0x000026bc, 0xfc003fff, MOD_a
|RD_s
|RD_t
, 0, 0, D33
},
1285 {"dpsqx_sa.w.ph", "7,s,t", 0x000036bc, 0xfc003fff, MOD_a
|RD_s
|RD_t
, 0, 0, D33
},
1286 {"dpsx.w.ph", "7,s,t", 0x000014bc, 0xfc003fff, MOD_a
|RD_s
|RD_t
, 0, 0, D33
},
1287 {"mul.ph", "d,s,t", 0x0000002d, 0xfc0007ff, WR_d
|RD_s
|RD_t
|WR_HILO
, 0, 0, D33
},
1288 {"mul_s.ph", "d,s,t", 0x0000042d, 0xfc0007ff, WR_d
|RD_s
|RD_t
|WR_HILO
, 0, 0, D33
},
1289 {"mulq_rs.w", "d,s,t", 0x00000195, 0xfc0007ff, WR_d
|RD_s
|RD_t
|WR_HILO
, 0, 0, D33
},
1290 {"mulq_s.ph", "d,s,t", 0x00000155, 0xfc0007ff, WR_d
|RD_s
|RD_t
|WR_HILO
, 0, 0, D33
},
1291 {"mulq_s.w", "d,s,t", 0x000001d5, 0xfc0007ff, WR_d
|RD_s
|RD_t
|WR_HILO
, 0, 0, D33
},
1292 {"mulsa.w.ph", "7,s,t", 0x00002cbc, 0xfc003fff, MOD_a
|RD_s
|RD_t
, 0, 0, D33
},
1293 {"precr.qb.ph", "d,s,t", 0x0000006d, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D33
},
1294 {"precr_sra.ph.w", "t,s,h", 0x000003cd, 0xfc0007ff, WR_t
|RD_t
|RD_s
, 0, 0, D33
},
1295 {"precr_sra_r.ph.w", "t,s,h", 0x000007cd, 0xfc0007ff, WR_t
|RD_t
|RD_s
, 0, 0, D33
},
1296 {"prepend", "t,s,h", 0x00000255, 0xfc0007ff, WR_t
|RD_t
|RD_s
, 0, 0, D33
},
1297 {"shra.qb", "t,s,3", 0x000001fc, 0xfc001fff, WR_t
|RD_s
, 0, 0, D33
},
1298 {"shra_r.qb", "t,s,3", 0x000011fc, 0xfc001fff, WR_t
|RD_s
, 0, 0, D33
},
1299 {"shrav.qb", "d,t,s", 0x000001cd, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D33
},
1300 {"shrav_r.qb", "d,t,s", 0x000005cd, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D33
},
1301 {"shrl.ph", "t,s,4", 0x000003fc, 0xfc000fff, WR_t
|RD_s
, 0, 0, D33
},
1302 {"shrlv.ph", "d,t,s", 0x00000315, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D33
},
1303 {"subu.ph", "d,s,t", 0x0000030d, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D33
},
1304 {"subu_s.ph", "d,s,t", 0x0000070d, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D33
},
1305 {"subuh.qb", "d,s,t", 0x0000034d, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D33
},
1306 {"subuh_r.qb", "d,s,t", 0x0000074d, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D33
},
1307 {"subqh.ph", "d,s,t", 0x0000024d, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D33
},
1308 {"subqh_r.ph", "d,s,t", 0x0000064d, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D33
},
1309 {"subqh.w", "d,s,t", 0x0000028d, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D33
},
1310 {"subqh_r.w", "d,s,t", 0x0000068d, 0xfc0007ff, WR_d
|RD_s
|RD_t
, 0, 0, D33
},
1313 const int bfd_micromips_num_opcodes
=
1314 ((sizeof micromips_opcodes
) / (sizeof (micromips_opcodes
[0])));
projects / deliverable / binutils-gdb.git / blob