1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
7 This file is part of GDB, GAS, and the GNU binutils.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
25 #include "libiberty.h"
26 #include "opcode/mips.h"
29 /* FIXME: These are needed to figure out if the code is mips16 or
30 not. The low bit of the address is often a good indicator. No
31 symbol table is available when this code runs out in an embedded
32 system as when it is used for disassembler support in a monitor. */
34 #if !defined(EMBEDDED_ENV)
35 #define SYMTAB_AVAILABLE 1
40 /* Mips instructions are at maximum this many bytes long. */
43 static void set_default_mips_dis_options
44 PARAMS ((struct disassemble_info
*));
45 static void parse_mips_dis_option
46 PARAMS ((const char *, unsigned int));
47 static void parse_mips_dis_options
48 PARAMS ((const char *));
49 static int _print_insn_mips
50 PARAMS ((bfd_vma
, struct disassemble_info
*, enum bfd_endian
));
51 static int print_insn_mips
52 PARAMS ((bfd_vma
, unsigned long int, struct disassemble_info
*));
53 static void print_insn_arg
54 PARAMS ((const char *, unsigned long, bfd_vma
, struct disassemble_info
*));
55 static int print_insn_mips16
56 PARAMS ((bfd_vma
, struct disassemble_info
*));
58 PARAMS ((Elf_Internal_Ehdr
*));
59 static void print_mips16_insn_arg
60 PARAMS ((int, const struct mips_opcode
*, int, bfd_boolean
, int, bfd_vma
,
61 struct disassemble_info
*));
63 /* FIXME: These should be shared with gdb somehow. */
65 /* The mips16 register names. */
66 static const char * const mips16_reg_names
[] = {
67 "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3"
70 static const char * const mips_gpr_names_numeric
[32] = {
71 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
72 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
73 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
74 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
77 static const char * const mips_gpr_names_oldabi
[32] = {
78 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
79 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
80 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
81 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
84 static const char * const mips_gpr_names_newabi
[32] = {
85 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
86 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
87 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
88 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
91 static const char * const mips_fpr_names_numeric
[32] = {
92 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
93 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
94 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
95 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
98 static const char * const mips_fpr_names_32
[32] = {
99 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
100 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
101 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
102 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
105 static const char * const mips_fpr_names_n32
[32] = {
106 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
107 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
108 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
109 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
112 static const char * const mips_fpr_names_64
[32] = {
113 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
114 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
115 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
116 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
119 static const char * const mips_cp0_names_numeric
[32] = {
120 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
121 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
122 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
123 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
126 static const char * const mips_cp0_names_mips3264
[32] = {
127 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
128 "c0_context", "c0_pagemask", "c0_wired", "$7",
129 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
130 "c0_status", "c0_cause", "c0_epc", "c0_prid",
131 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
132 "c0_xcontext", "$21", "$22", "c0_debug",
133 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
134 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
137 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
138 static const char * const mips_cp0_names_sb1
[32] = {
139 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
140 "c0_context", "c0_pagemask", "c0_wired", "$7",
141 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
142 "c0_status", "c0_cause", "c0_epc", "c0_prid",
143 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
144 "c0_xcontext", "$21", "$22", "c0_debug",
145 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
146 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
149 struct mips_abi_choice
{
151 const char * const *gpr_names
;
152 const char * const *fpr_names
;
155 struct mips_abi_choice mips_abi_choices
[] = {
156 { "numeric", mips_gpr_names_numeric
, mips_fpr_names_numeric
},
157 { "32", mips_gpr_names_oldabi
, mips_fpr_names_32
},
158 { "n32", mips_gpr_names_newabi
, mips_fpr_names_n32
},
159 { "64", mips_gpr_names_newabi
, mips_fpr_names_64
},
162 struct mips_arch_choice
{
165 unsigned long bfd_mach
;
168 const char * const *cp0_names
;
171 struct mips_arch_choice mips_arch_choices
[] = {
172 { "numeric", 0, 0, 0, 0,
173 mips_cp0_names_numeric
},
174 { "r3000", 1, bfd_mach_mips3000
, CPU_R3000
, ISA_MIPS1
,
176 { "r3900", 1, bfd_mach_mips3900
, CPU_R3900
, ISA_MIPS1
,
178 { "r4000", 1, bfd_mach_mips4000
, CPU_R4000
, ISA_MIPS3
,
180 { "r4010", 1, bfd_mach_mips4010
, CPU_R4010
, ISA_MIPS2
,
182 { "vr4100", 1, bfd_mach_mips4100
, CPU_VR4100
, ISA_MIPS3
,
184 { "vr4111", 1, bfd_mach_mips4111
, CPU_R4111
, ISA_MIPS3
,
186 { "vr4120", 1, bfd_mach_mips4120
, CPU_VR4120
, ISA_MIPS3
,
188 { "r4300", 1, bfd_mach_mips4300
, CPU_R4300
, ISA_MIPS3
,
190 { "r4400", 1, bfd_mach_mips4400
, CPU_R4400
, ISA_MIPS3
,
192 { "r4600", 1, bfd_mach_mips4600
, CPU_R4600
, ISA_MIPS3
,
194 { "r4650", 1, bfd_mach_mips4650
, CPU_R4650
, ISA_MIPS3
,
196 { "r5000", 1, bfd_mach_mips5000
, CPU_R5000
, ISA_MIPS4
,
198 { "vr5400", 1, bfd_mach_mips5400
, CPU_VR5400
, ISA_MIPS4
,
200 { "vr5500", 1, bfd_mach_mips5500
, CPU_VR5500
, ISA_MIPS4
,
202 { "r6000", 1, bfd_mach_mips6000
, CPU_R6000
, ISA_MIPS2
,
204 { "r8000", 1, bfd_mach_mips8000
, CPU_R8000
, ISA_MIPS4
,
206 { "r10000", 1, bfd_mach_mips10000
, CPU_R10000
, ISA_MIPS4
,
208 { "r12000", 1, bfd_mach_mips12000
, CPU_R12000
, ISA_MIPS4
,
210 { "mips5", 1, bfd_mach_mips5
, CPU_MIPS5
, ISA_MIPS5
,
212 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
213 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
214 _MIPS32 Architecture For Programmers Volume I: Introduction to the
215 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
217 { "mips32", 1, bfd_mach_mipsisa32
, CPU_MIPS32
,
218 ISA_MIPS32
| INSN_MIPS16
,
219 mips_cp0_names_mips3264
},
220 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
221 { "mips64", 1, bfd_mach_mipsisa64
, CPU_MIPS64
,
222 ISA_MIPS64
| INSN_MIPS16
| INSN_MIPS3D
| INSN_MDMX
,
223 mips_cp0_names_mips3264
},
224 { "sb1", 1, bfd_mach_mips_sb1
, CPU_SB1
,
225 ISA_MIPS64
| INSN_MIPS3D
| INSN_SB1
,
226 mips_cp0_names_sb1
},
228 /* This entry, mips16, is here only for ISA/processor selection; do
229 not print its name. */
230 { "", 1, bfd_mach_mips16
, CPU_MIPS16
, ISA_MIPS3
| INSN_MIPS16
,
234 /* ISA and processor type to disassemble for, and register names to use.
235 set_default_mips_dis_options and parse_mips_dis_options fill in these
237 static int mips_processor
;
239 static const char * const *mips_gpr_names
;
240 static const char * const *mips_fpr_names
;
241 static const char * const *mips_cp0_names
;
243 static const struct mips_abi_choice
*choose_abi_by_name
244 PARAMS ((const char *, unsigned int));
245 static const struct mips_arch_choice
*choose_arch_by_name
246 PARAMS ((const char *, unsigned int));
247 static const struct mips_arch_choice
*choose_arch_by_number
248 PARAMS ((unsigned long));
250 static const struct mips_abi_choice
*
251 choose_abi_by_name (name
, namelen
)
253 unsigned int namelen
;
255 const struct mips_abi_choice
*c
;
258 for (i
= 0, c
= NULL
; i
< ARRAY_SIZE (mips_abi_choices
) && c
== NULL
; i
++)
260 if (strncmp (mips_abi_choices
[i
].name
, name
, namelen
) == 0
261 && strlen (mips_abi_choices
[i
].name
) == namelen
)
262 c
= &mips_abi_choices
[i
];
267 static const struct mips_arch_choice
*
268 choose_arch_by_name (name
, namelen
)
270 unsigned int namelen
;
272 const struct mips_arch_choice
*c
= NULL
;
275 for (i
= 0, c
= NULL
; i
< ARRAY_SIZE (mips_arch_choices
) && c
== NULL
; i
++)
277 if (strncmp (mips_arch_choices
[i
].name
, name
, namelen
) == 0
278 && strlen (mips_arch_choices
[i
].name
) == namelen
)
279 c
= &mips_arch_choices
[i
];
284 static const struct mips_arch_choice
*
285 choose_arch_by_number (mach
)
288 static unsigned long hint_bfd_mach
;
289 static const struct mips_arch_choice
*hint_arch_choice
;
290 const struct mips_arch_choice
*c
;
293 /* We optimize this because even if the user specifies no
294 flags, this will be done for every instruction! */
295 if (hint_bfd_mach
== mach
296 && hint_arch_choice
!= NULL
297 && hint_arch_choice
->bfd_mach
== hint_bfd_mach
)
298 return hint_arch_choice
;
300 for (i
= 0, c
= NULL
; i
< ARRAY_SIZE (mips_arch_choices
) && c
== NULL
; i
++)
302 if (mips_arch_choices
[i
].bfd_mach_valid
303 && mips_arch_choices
[i
].bfd_mach
== mach
)
305 c
= &mips_arch_choices
[i
];
306 hint_bfd_mach
= mach
;
307 hint_arch_choice
= c
;
314 set_default_mips_dis_options (info
)
315 struct disassemble_info
*info
;
317 const struct mips_arch_choice
*chosen_arch
;
319 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
320 and numeric FPR and CP0 register names. */
321 mips_isa
= ISA_MIPS3
;
322 mips_processor
= CPU_R3000
;
323 mips_gpr_names
= mips_gpr_names_oldabi
;
324 mips_fpr_names
= mips_fpr_names_numeric
;
325 mips_cp0_names
= mips_cp0_names_numeric
;
327 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
328 if (info
->flavour
== bfd_target_elf_flavour
&& info
->symbols
!= NULL
)
330 Elf_Internal_Ehdr
*header
;
332 header
= elf_elfheader (bfd_asymbol_bfd (*(info
->symbols
)));
333 if (is_newabi (header
))
334 mips_gpr_names
= mips_gpr_names_newabi
;
337 /* Set ISA, architecture, and cp0 register names as best we can. */
338 #if ! SYMTAB_AVAILABLE
339 /* This is running out on a target machine, not in a host tool.
340 FIXME: Where does mips_target_info come from? */
341 target_processor
= mips_target_info
.processor
;
342 mips_isa
= mips_target_info
.isa
;
344 chosen_arch
= choose_arch_by_number (info
->mach
);
345 if (chosen_arch
!= NULL
)
347 mips_processor
= chosen_arch
->processor
;
348 mips_isa
= chosen_arch
->isa
;
349 if (chosen_arch
->cp0_names
!= NULL
)
350 mips_cp0_names
= chosen_arch
->cp0_names
;
356 parse_mips_dis_option (option
, len
)
360 unsigned int i
, optionlen
, vallen
;
362 const struct mips_abi_choice
*chosen_abi
;
363 const struct mips_arch_choice
*chosen_arch
;
365 /* Look for the = that delimits the end of the option name. */
366 for (i
= 0; i
< len
; i
++)
368 if (option
[i
] == '=')
371 if (i
== 0) /* Invalid option: no name before '='. */
373 if (i
== len
) /* Invalid option: no '='. */
375 if (i
== (len
- 1)) /* Invalid option: no value after '='. */
379 val
= option
+ (optionlen
+ 1);
380 vallen
= len
- (optionlen
+ 1);
382 if (strncmp("gpr-names", option
, optionlen
) == 0
383 && strlen("gpr-names") == optionlen
)
385 chosen_abi
= choose_abi_by_name (val
, vallen
);
386 if (chosen_abi
!= NULL
&& chosen_abi
->gpr_names
!= NULL
)
387 mips_gpr_names
= chosen_abi
->gpr_names
;
391 if (strncmp("fpr-names", option
, optionlen
) == 0
392 && strlen("fpr-names") == optionlen
)
394 chosen_abi
= choose_abi_by_name (val
, vallen
);
395 if (chosen_abi
!= NULL
&& chosen_abi
->fpr_names
!= NULL
)
396 mips_fpr_names
= chosen_abi
->fpr_names
;
400 if (strncmp("cp0-names", option
, optionlen
) == 0
401 && strlen("cp0-names") == optionlen
)
403 chosen_arch
= choose_arch_by_name (val
, vallen
);
404 if (chosen_arch
!= NULL
&& chosen_arch
->cp0_names
!= NULL
)
405 mips_cp0_names
= chosen_arch
->cp0_names
;
409 if (strncmp("reg-names", option
, optionlen
) == 0
410 && strlen("reg-names") == optionlen
)
412 /* We check both ABI and ARCH here unconditionally, so
413 that "numeric" will do the desirable thing: select
414 numeric register names for all registers. Other than
415 that, a given name probably won't match both. */
416 chosen_abi
= choose_abi_by_name (val
, vallen
);
417 if (chosen_abi
!= NULL
)
419 if (chosen_abi
->gpr_names
!= NULL
)
420 mips_gpr_names
= chosen_abi
->gpr_names
;
421 if (chosen_abi
->fpr_names
!= NULL
)
422 mips_fpr_names
= chosen_abi
->fpr_names
;
424 chosen_arch
= choose_arch_by_name (val
, vallen
);
425 if (chosen_arch
!= NULL
)
427 if (chosen_arch
->cp0_names
!= NULL
)
428 mips_cp0_names
= chosen_arch
->cp0_names
;
433 /* Invalid option. */
437 parse_mips_dis_options (options
)
440 const char *option_end
;
445 while (*options
!= '\0')
447 /* Skip empty options. */
454 /* We know that *options is neither NUL or a comma. */
455 option_end
= options
+ 1;
456 while (*option_end
!= ',' && *option_end
!= '\0')
459 parse_mips_dis_option (options
, option_end
- options
);
461 /* Go on to the next one. If option_end points to a comma, it
462 will be skipped above. */
463 options
= option_end
;
468 /* Print insn arguments for 32/64-bit code. */
471 print_insn_arg (d
, l
, pc
, info
)
473 register unsigned long int l
;
475 struct disassemble_info
*info
;
486 (*info
->fprintf_func
) (info
->stream
, "%c", *d
);
493 (*info
->fprintf_func
) (info
->stream
, "%s",
494 mips_gpr_names
[(l
>> OP_SH_RS
) & OP_MASK_RS
]);
499 (*info
->fprintf_func
) (info
->stream
, "%s",
500 mips_gpr_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
505 (*info
->fprintf_func
) (info
->stream
, "0x%x",
506 (l
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
);
509 case 'j': /* Same as i, but sign-extended. */
511 delta
= (l
>> OP_SH_DELTA
) & OP_MASK_DELTA
;
514 (*info
->fprintf_func
) (info
->stream
, "%d",
519 (*info
->fprintf_func
) (info
->stream
, "0x%x",
520 (unsigned int) ((l
>> OP_SH_PREFX
)
525 (*info
->fprintf_func
) (info
->stream
, "0x%x",
526 (unsigned int) ((l
>> OP_SH_CACHE
)
531 info
->target
= (((pc
+ 4) & ~(bfd_vma
) 0x0fffffff)
532 | (((l
>> OP_SH_TARGET
) & OP_MASK_TARGET
) << 2));
533 (*info
->print_address_func
) (info
->target
, info
);
537 /* Sign extend the displacement. */
538 delta
= (l
>> OP_SH_DELTA
) & OP_MASK_DELTA
;
541 info
->target
= (delta
<< 2) + pc
+ INSNLEN
;
542 (*info
->print_address_func
) (info
->target
, info
);
546 (*info
->fprintf_func
) (info
->stream
, "%s",
547 mips_gpr_names
[(l
>> OP_SH_RD
) & OP_MASK_RD
]);
552 /* First check for both rd and rt being equal. */
553 unsigned int reg
= (l
>> OP_SH_RD
) & OP_MASK_RD
;
554 if (reg
== ((l
>> OP_SH_RT
) & OP_MASK_RT
))
555 (*info
->fprintf_func
) (info
->stream
, "%s",
556 mips_gpr_names
[reg
]);
559 /* If one is zero use the other. */
561 (*info
->fprintf_func
) (info
->stream
, "%s",
562 mips_gpr_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
563 else if (((l
>> OP_SH_RT
) & OP_MASK_RT
) == 0)
564 (*info
->fprintf_func
) (info
->stream
, "%s",
565 mips_gpr_names
[reg
]);
566 else /* Bogus, result depends on processor. */
567 (*info
->fprintf_func
) (info
->stream
, "%s or %s",
569 mips_gpr_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
575 (*info
->fprintf_func
) (info
->stream
, "%s", mips_gpr_names
[0]);
579 (*info
->fprintf_func
) (info
->stream
, "0x%x",
580 (l
>> OP_SH_SHAMT
) & OP_MASK_SHAMT
);
584 (*info
->fprintf_func
) (info
->stream
, "0x%x",
585 (l
>> OP_SH_CODE
) & OP_MASK_CODE
);
589 (*info
->fprintf_func
) (info
->stream
, "0x%x",
590 (l
>> OP_SH_CODE2
) & OP_MASK_CODE2
);
594 (*info
->fprintf_func
) (info
->stream
, "0x%x",
595 (l
>> OP_SH_COPZ
) & OP_MASK_COPZ
);
599 (*info
->fprintf_func
) (info
->stream
, "0x%x",
600 (l
>> OP_SH_CODE20
) & OP_MASK_CODE20
);
604 (*info
->fprintf_func
) (info
->stream
, "0x%x",
605 (l
>> OP_SH_CODE19
) & OP_MASK_CODE19
);
610 (*info
->fprintf_func
) (info
->stream
, "%s",
611 mips_fpr_names
[(l
>> OP_SH_FS
) & OP_MASK_FS
]);
616 (*info
->fprintf_func
) (info
->stream
, "%s",
617 mips_fpr_names
[(l
>> OP_SH_FT
) & OP_MASK_FT
]);
621 (*info
->fprintf_func
) (info
->stream
, "%s",
622 mips_fpr_names
[(l
>> OP_SH_FD
) & OP_MASK_FD
]);
626 (*info
->fprintf_func
) (info
->stream
, "%s",
627 mips_fpr_names
[(l
>> OP_SH_FR
) & OP_MASK_FR
]);
631 /* Coprocessor register for lwcN instructions, et al.
633 Note that there is no load/store cp0 instructions, and
634 that FPU (cp1) instructions disassemble this field using
635 'T' format. Therefore, until we gain understanding of
637 we can simply print the register numbers. */
638 (*info
->fprintf_func
) (info
->stream
, "$%d",
639 (l
>> OP_SH_RT
) & OP_MASK_RT
);
643 /* Coprocessor register for mtcN instructions, et al.
644 Note that FPU (cp1) instructions disassemble this field using
645 'S' format. Therefore, we only need to worry about cp0, cp2,
647 op
= (l
>> OP_SH_OP
) & OP_MASK_OP
;
648 if (op
== OP_OP_COP0
)
649 (*info
->fprintf_func
) (info
->stream
, "%s",
650 mips_cp0_names
[(l
>> OP_SH_RD
) & OP_MASK_RD
]);
652 (*info
->fprintf_func
) (info
->stream
, "$%d",
653 (l
>> OP_SH_RD
) & OP_MASK_RD
);
657 (*info
->fprintf_func
) (info
->stream
, "$fcc%d",
658 (l
>> OP_SH_BCC
) & OP_MASK_BCC
);
662 (*info
->fprintf_func
) (info
->stream
, "$fcc%d",
663 (l
>> OP_SH_CCC
) & OP_MASK_CCC
);
667 (*info
->fprintf_func
) (info
->stream
, "%d",
668 (l
>> OP_SH_PERFREG
) & OP_MASK_PERFREG
);
672 (*info
->fprintf_func
) (info
->stream
, "%d",
673 (l
>> OP_SH_VECBYTE
) & OP_MASK_VECBYTE
);
677 (*info
->fprintf_func
) (info
->stream
, "%d",
678 (l
>> OP_SH_VECALIGN
) & OP_MASK_VECALIGN
);
682 (*info
->fprintf_func
) (info
->stream
, "%d",
683 (l
>> OP_SH_SEL
) & OP_MASK_SEL
);
687 (*info
->fprintf_func
) (info
->stream
, "%d",
688 (l
>> OP_SH_ALN
) & OP_MASK_ALN
);
693 unsigned int vsel
= (l
>> OP_SH_VSEL
) & OP_MASK_VSEL
;
694 if ((vsel
& 0x10) == 0)
698 for (fmt
= 0; fmt
< 3; fmt
++, vsel
>>= 1)
701 (*info
->fprintf_func
) (info
->stream
, "$v%d[%d]",
702 (l
>> OP_SH_FT
) & OP_MASK_FT
,
705 else if ((vsel
& 0x08) == 0)
707 (*info
->fprintf_func
) (info
->stream
, "$v%d",
708 (l
>> OP_SH_FT
) & OP_MASK_FT
);
712 (*info
->fprintf_func
) (info
->stream
, "0x%x",
713 (l
>> OP_SH_FT
) & OP_MASK_FT
);
719 (*info
->fprintf_func
) (info
->stream
, "$v%d",
720 (l
>> OP_SH_FD
) & OP_MASK_FD
);
724 (*info
->fprintf_func
) (info
->stream
, "$v%d",
725 (l
>> OP_SH_FS
) & OP_MASK_FS
);
729 (*info
->fprintf_func
) (info
->stream
, "$v%d",
730 (l
>> OP_SH_FT
) & OP_MASK_FT
);
734 /* xgettext:c-format */
735 (*info
->fprintf_func
) (info
->stream
,
736 _("# internal error, undefined modifier(%c)"),
742 /* Check if the object uses NewABI conventions. */
746 Elf_Internal_Ehdr
*header
;
748 /* There are no old-style ABIs which use 64-bit ELF. */
749 if (header
->e_ident
[EI_CLASS
] == ELFCLASS64
)
752 /* If a 32-bit ELF file, n32 is a new-style ABI. */
753 if ((header
->e_flags
& EF_MIPS_ABI2
) != 0)
759 /* Print the mips instruction at address MEMADDR in debugged memory,
760 on using INFO. Returns length of the instruction, in bytes, which is
761 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
762 this is little-endian code. */
765 print_insn_mips (memaddr
, word
, info
)
767 unsigned long int word
;
768 struct disassemble_info
*info
;
770 register const struct mips_opcode
*op
;
771 static bfd_boolean init
= 0;
772 static const struct mips_opcode
*mips_hash
[OP_MASK_OP
+ 1];
774 /* Build a hash table to shorten the search time. */
779 for (i
= 0; i
<= OP_MASK_OP
; i
++)
781 for (op
= mips_opcodes
; op
< &mips_opcodes
[NUMOPCODES
]; op
++)
783 if (op
->pinfo
== INSN_MACRO
)
785 if (i
== ((op
->match
>> OP_SH_OP
) & OP_MASK_OP
))
796 info
->bytes_per_chunk
= INSNLEN
;
797 info
->display_endian
= info
->endian
;
798 info
->insn_info_valid
= 1;
799 info
->branch_delay_insns
= 0;
801 info
->insn_type
= dis_nonbranch
;
805 op
= mips_hash
[(word
>> OP_SH_OP
) & OP_MASK_OP
];
808 for (; op
< &mips_opcodes
[NUMOPCODES
]; op
++)
810 if (op
->pinfo
!= INSN_MACRO
&& (word
& op
->mask
) == op
->match
)
812 register const char *d
;
814 /* We always allow to disassemble the jalx instruction. */
815 if (! OPCODE_IS_MEMBER (op
, mips_isa
, mips_processor
)
816 && strcmp (op
->name
, "jalx"))
819 /* Figure out instruction type and branch delay information. */
820 if ((op
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
822 if ((info
->insn_type
& INSN_WRITE_GPR_31
) != 0)
823 info
->insn_type
= dis_jsr
;
825 info
->insn_type
= dis_branch
;
826 info
->branch_delay_insns
= 1;
828 else if ((op
->pinfo
& (INSN_COND_BRANCH_DELAY
829 | INSN_COND_BRANCH_LIKELY
)) != 0)
831 if ((info
->insn_type
& INSN_WRITE_GPR_31
) != 0)
832 info
->insn_type
= dis_condjsr
;
834 info
->insn_type
= dis_condbranch
;
835 info
->branch_delay_insns
= 1;
837 else if ((op
->pinfo
& (INSN_STORE_MEMORY
838 | INSN_LOAD_MEMORY_DELAY
)) != 0)
839 info
->insn_type
= dis_dref
;
841 (*info
->fprintf_func
) (info
->stream
, "%s", op
->name
);
844 if (d
!= NULL
&& *d
!= '\0')
846 (*info
->fprintf_func
) (info
->stream
, "\t");
847 for (; *d
!= '\0'; d
++)
848 print_insn_arg (d
, word
, memaddr
, info
);
856 /* Handle undefined instructions. */
857 info
->insn_type
= dis_noninsn
;
858 (*info
->fprintf_func
) (info
->stream
, "0x%x", word
);
862 /* In an environment where we do not know the symbol type of the
863 instruction we are forced to assume that the low order bit of the
864 instructions' address may mark it as a mips16 instruction. If we
865 are single stepping, or the pc is within the disassembled function,
866 this works. Otherwise, we need a clue. Sometimes. */
869 _print_insn_mips (memaddr
, info
, endianness
)
871 struct disassemble_info
*info
;
872 enum bfd_endian endianness
;
874 bfd_byte buffer
[INSNLEN
];
877 set_default_mips_dis_options (info
);
878 parse_mips_dis_options (info
->disassembler_options
);
881 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
882 /* Only a few tools will work this way. */
884 return print_insn_mips16 (memaddr
, info
);
888 if (info
->mach
== bfd_mach_mips16
889 || (info
->flavour
== bfd_target_elf_flavour
890 && info
->symbols
!= NULL
891 && ((*(elf_symbol_type
**) info
->symbols
)->internal_elf_sym
.st_other
893 return print_insn_mips16 (memaddr
, info
);
896 status
= (*info
->read_memory_func
) (memaddr
, buffer
, INSNLEN
, info
);
901 if (endianness
== BFD_ENDIAN_BIG
)
902 insn
= (unsigned long) bfd_getb32 (buffer
);
904 insn
= (unsigned long) bfd_getl32 (buffer
);
906 return print_insn_mips (memaddr
, insn
, info
);
910 (*info
->memory_error_func
) (status
, memaddr
, info
);
916 print_insn_big_mips (memaddr
, info
)
918 struct disassemble_info
*info
;
920 return _print_insn_mips (memaddr
, info
, BFD_ENDIAN_BIG
);
924 print_insn_little_mips (memaddr
, info
)
926 struct disassemble_info
*info
;
928 return _print_insn_mips (memaddr
, info
, BFD_ENDIAN_LITTLE
);
931 /* Disassemble mips16 instructions. */
934 print_insn_mips16 (memaddr
, info
)
936 struct disassemble_info
*info
;
942 bfd_boolean use_extend
;
944 const struct mips_opcode
*op
, *opend
;
946 info
->bytes_per_chunk
= 2;
947 info
->display_endian
= info
->endian
;
948 info
->insn_info_valid
= 1;
949 info
->branch_delay_insns
= 0;
951 info
->insn_type
= dis_nonbranch
;
955 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
958 (*info
->memory_error_func
) (status
, memaddr
, info
);
964 if (info
->endian
== BFD_ENDIAN_BIG
)
965 insn
= bfd_getb16 (buffer
);
967 insn
= bfd_getl16 (buffer
);
969 /* Handle the extend opcode specially. */
971 if ((insn
& 0xf800) == 0xf000)
974 extend
= insn
& 0x7ff;
978 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
981 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
982 (unsigned int) extend
);
983 (*info
->memory_error_func
) (status
, memaddr
, info
);
987 if (info
->endian
== BFD_ENDIAN_BIG
)
988 insn
= bfd_getb16 (buffer
);
990 insn
= bfd_getl16 (buffer
);
992 /* Check for an extend opcode followed by an extend opcode. */
993 if ((insn
& 0xf800) == 0xf000)
995 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
996 (unsigned int) extend
);
997 info
->insn_type
= dis_noninsn
;
1004 /* FIXME: Should probably use a hash table on the major opcode here. */
1006 opend
= mips16_opcodes
+ bfd_mips16_num_opcodes
;
1007 for (op
= mips16_opcodes
; op
< opend
; op
++)
1009 if (op
->pinfo
!= INSN_MACRO
&& (insn
& op
->mask
) == op
->match
)
1013 if (strchr (op
->args
, 'a') != NULL
)
1017 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
1018 (unsigned int) extend
);
1019 info
->insn_type
= dis_noninsn
;
1027 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2,
1032 if (info
->endian
== BFD_ENDIAN_BIG
)
1033 extend
= bfd_getb16 (buffer
);
1035 extend
= bfd_getl16 (buffer
);
1040 (*info
->fprintf_func
) (info
->stream
, "%s", op
->name
);
1041 if (op
->args
[0] != '\0')
1042 (*info
->fprintf_func
) (info
->stream
, "\t");
1044 for (s
= op
->args
; *s
!= '\0'; s
++)
1048 && (((insn
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
)
1049 == ((insn
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
)))
1051 /* Skip the register and the comma. */
1057 && (((insn
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
)
1058 == ((insn
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
)))
1060 /* Skip the register and the comma. */
1064 print_mips16_insn_arg (*s
, op
, insn
, use_extend
, extend
, memaddr
,
1068 if ((op
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1070 info
->branch_delay_insns
= 1;
1071 if (info
->insn_type
!= dis_jsr
)
1072 info
->insn_type
= dis_branch
;
1080 (*info
->fprintf_func
) (info
->stream
, "0x%x", extend
| 0xf000);
1081 (*info
->fprintf_func
) (info
->stream
, "0x%x", insn
);
1082 info
->insn_type
= dis_noninsn
;
1087 /* Disassemble an operand for a mips16 instruction. */
1090 print_mips16_insn_arg (type
, op
, l
, use_extend
, extend
, memaddr
, info
)
1092 const struct mips_opcode
*op
;
1094 bfd_boolean use_extend
;
1097 struct disassemble_info
*info
;
1104 (*info
->fprintf_func
) (info
->stream
, "%c", type
);
1109 (*info
->fprintf_func
) (info
->stream
, "%s",
1110 mips16_reg_names
[((l
>> MIPS16OP_SH_RY
)
1111 & MIPS16OP_MASK_RY
)]);
1116 (*info
->fprintf_func
) (info
->stream
, "%s",
1117 mips16_reg_names
[((l
>> MIPS16OP_SH_RX
)
1118 & MIPS16OP_MASK_RX
)]);
1122 (*info
->fprintf_func
) (info
->stream
, "%s",
1123 mips16_reg_names
[((l
>> MIPS16OP_SH_RZ
)
1124 & MIPS16OP_MASK_RZ
)]);
1128 (*info
->fprintf_func
) (info
->stream
, "%s",
1129 mips16_reg_names
[((l
>> MIPS16OP_SH_MOVE32Z
)
1130 & MIPS16OP_MASK_MOVE32Z
)]);
1134 (*info
->fprintf_func
) (info
->stream
, "%s", mips_gpr_names
[0]);
1138 (*info
->fprintf_func
) (info
->stream
, "%s", mips_gpr_names
[29]);
1142 (*info
->fprintf_func
) (info
->stream
, "$pc");
1146 (*info
->fprintf_func
) (info
->stream
, "%s", mips_gpr_names
[31]);
1150 (*info
->fprintf_func
) (info
->stream
, "%s",
1151 mips_gpr_names
[((l
>> MIPS16OP_SH_REGR32
)
1152 & MIPS16OP_MASK_REGR32
)]);
1156 (*info
->fprintf_func
) (info
->stream
, "%s",
1157 mips_gpr_names
[MIPS16OP_EXTRACT_REG32R (l
)]);
1183 int immed
, nbits
, shift
, signedp
, extbits
, pcrel
, extu
, branch
;
1195 immed
= (l
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
1201 immed
= (l
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
1207 immed
= (l
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
1213 immed
= (l
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
1219 immed
= (l
>> MIPS16OP_SH_IMM4
) & MIPS16OP_MASK_IMM4
;
1225 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
1226 info
->insn_type
= dis_dref
;
1227 info
->data_size
= 1;
1232 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
1233 info
->insn_type
= dis_dref
;
1234 info
->data_size
= 2;
1239 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
1240 if ((op
->pinfo
& MIPS16_INSN_READ_PC
) == 0
1241 && (op
->pinfo
& MIPS16_INSN_READ_SP
) == 0)
1243 info
->insn_type
= dis_dref
;
1244 info
->data_size
= 4;
1250 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
1251 info
->insn_type
= dis_dref
;
1252 info
->data_size
= 8;
1256 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
1261 immed
= (l
>> MIPS16OP_SH_IMM6
) & MIPS16OP_MASK_IMM6
;
1265 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
1270 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
1271 /* FIXME: This might be lw, or it might be addiu to $sp or
1272 $pc. We assume it's load. */
1273 info
->insn_type
= dis_dref
;
1274 info
->data_size
= 4;
1279 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
1280 info
->insn_type
= dis_dref
;
1281 info
->data_size
= 8;
1285 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
1290 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
1296 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
1301 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
1305 info
->insn_type
= dis_condbranch
;
1309 immed
= (l
>> MIPS16OP_SH_IMM11
) & MIPS16OP_MASK_IMM11
;
1313 info
->insn_type
= dis_branch
;
1318 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
1320 /* FIXME: This can be lw or la. We assume it is lw. */
1321 info
->insn_type
= dis_dref
;
1322 info
->data_size
= 4;
1327 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
1329 info
->insn_type
= dis_dref
;
1330 info
->data_size
= 8;
1335 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
1344 if (signedp
&& immed
>= (1 << (nbits
- 1)))
1345 immed
-= 1 << nbits
;
1347 if ((type
== '<' || type
== '>' || type
== '[' || type
== ']')
1354 immed
|= ((extend
& 0x1f) << 11) | (extend
& 0x7e0);
1355 else if (extbits
== 15)
1356 immed
|= ((extend
& 0xf) << 11) | (extend
& 0x7f0);
1358 immed
= ((extend
>> 6) & 0x1f) | (extend
& 0x20);
1359 immed
&= (1 << extbits
) - 1;
1360 if (! extu
&& immed
>= (1 << (extbits
- 1)))
1361 immed
-= 1 << extbits
;
1365 (*info
->fprintf_func
) (info
->stream
, "%d", immed
);
1373 baseaddr
= memaddr
+ 2;
1375 else if (use_extend
)
1376 baseaddr
= memaddr
- 2;
1384 /* If this instruction is in the delay slot of a jr
1385 instruction, the base address is the address of the
1386 jr instruction. If it is in the delay slot of jalr
1387 instruction, the base address is the address of the
1388 jalr instruction. This test is unreliable: we have
1389 no way of knowing whether the previous word is
1390 instruction or data. */
1391 status
= (*info
->read_memory_func
) (memaddr
- 4, buffer
, 2,
1394 && (((info
->endian
== BFD_ENDIAN_BIG
1395 ? bfd_getb16 (buffer
)
1396 : bfd_getl16 (buffer
))
1397 & 0xf800) == 0x1800))
1398 baseaddr
= memaddr
- 4;
1401 status
= (*info
->read_memory_func
) (memaddr
- 2, buffer
,
1404 && (((info
->endian
== BFD_ENDIAN_BIG
1405 ? bfd_getb16 (buffer
)
1406 : bfd_getl16 (buffer
))
1407 & 0xf81f) == 0xe800))
1408 baseaddr
= memaddr
- 2;
1411 info
->target
= (baseaddr
& ~((1 << shift
) - 1)) + immed
;
1412 (*info
->print_address_func
) (info
->target
, info
);
1420 l
= ((l
& 0x1f) << 23) | ((l
& 0x3e0) << 13) | (extend
<< 2);
1421 info
->target
= ((memaddr
+ 4) & ~(bfd_vma
) 0x0fffffff) | l
;
1422 (*info
->print_address_func
) (info
->target
, info
);
1423 info
->insn_type
= dis_jsr
;
1424 info
->branch_delay_insns
= 1;
1430 int need_comma
, amask
, smask
;
1434 l
= (l
>> MIPS16OP_SH_IMM6
) & MIPS16OP_MASK_IMM6
;
1436 amask
= (l
>> 3) & 7;
1438 if (amask
> 0 && amask
< 5)
1440 (*info
->fprintf_func
) (info
->stream
, "%s", mips_gpr_names
[4]);
1442 (*info
->fprintf_func
) (info
->stream
, "-%s",
1443 mips_gpr_names
[amask
+ 3]);
1447 smask
= (l
>> 1) & 3;
1450 (*info
->fprintf_func
) (info
->stream
, "%s??",
1451 need_comma
? "," : "");
1456 (*info
->fprintf_func
) (info
->stream
, "%s%s",
1457 need_comma
? "," : "",
1458 mips_gpr_names
[16]);
1460 (*info
->fprintf_func
) (info
->stream
, "-%s",
1461 mips_gpr_names
[smask
+ 15]);
1467 (*info
->fprintf_func
) (info
->stream
, "%s%s",
1468 need_comma
? "," : "",
1469 mips_gpr_names
[31]);
1473 if (amask
== 5 || amask
== 6)
1475 (*info
->fprintf_func
) (info
->stream
, "%s$f0",
1476 need_comma
? "," : "");
1478 (*info
->fprintf_func
) (info
->stream
, "-$f1");
1484 /* xgettext:c-format */
1485 (*info
->fprintf_func
)
1487 _("# internal disassembler error, unrecognised modifier (%c)"),
1494 print_mips_disassembler_options (stream
)
1499 fprintf (stream
, _("\n\
1500 The following MIPS specific disassembler options are supported for use\n\
1501 with the -M switch (multiple options should be separated by commas):\n"));
1503 fprintf (stream
, _("\n\
1504 gpr-names=ABI Print GPR names according to specified ABI.\n\
1505 Default: based on binary being disassembled.\n"));
1507 fprintf (stream
, _("\n\
1508 fpr-names=ABI Print FPR names according to specified ABI.\n\
1509 Default: numeric.\n"));
1511 fprintf (stream
, _("\n\
1512 cp0-names=ARCH Print CP0 register names according to\n\
1513 specified architecture.\n\
1514 Default: based on binary being disassembled.\n"));
1516 fprintf (stream
, _("\n\
1517 reg-names=ABI Print GPR and FPR names according to\n\
1518 specified ABI.\n"));
1520 fprintf (stream
, _("\n\
1521 reg-names=ARCH Print CP0 register names according to\n\
1522 specified architecture.\n"));
1524 fprintf (stream
, _("\n\
1525 For the options above, the following values are supported for \"ABI\":\n\
1527 for (i
= 0; mips_abi_choices
[i
].name
!= NULL
; i
++)
1528 fprintf (stream
, " %s", mips_abi_choices
[i
].name
);
1529 fprintf (stream
, _("\n"));
1531 fprintf (stream
, _("\n\
1532 For the options above, The following values are supported for \"ARCH\":\n\
1534 for (i
= 0; mips_arch_choices
[i
].name
!= NULL
; i
++)
1535 if (*mips_arch_choices
[i
].name
!= '\0')
1536 fprintf (stream
, " %s", mips_arch_choices
[i
].name
);
1537 fprintf (stream
, _("\n"));
1539 fprintf (stream
, _("\n"));