opcodes/mn10300-opc.c

   1 /* Assemble Matsushita MN10300 instructions.
   2    Copyright (C) 1996 Free Software Foundation, Inc.
   3
   4 This program is free software; you can redistribute it and/or modify
   5 it under the terms of the GNU General Public License as published by
   6 the Free Software Foundation; either version 2 of the License, or
   7 (at your option) any later version.
   8
   9 This program is distributed in the hope that it will be useful,
  10 but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 GNU General Public License for more details.
  13
  14 You should have received a copy of the GNU General Public License
  15 along with this program; if not, write to the Free Software
  16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  17
  18 #include "ansidecl.h"
  19 #include "opcode/mn10300.h"
  20
  21 \f
  22 const struct mn10300_operand mn10300_operands[] = {
  23 #define UNUSED  0
  24   {0, 0, 0},
  25
  26 /* dn register in the first register operand position.  */
  27 #define DN0      (UNUSED+1)
  28   {2, 0, MN10300_OPERAND_DREG},
  29
  30 /* dn register in the second register operand position.  */
  31 #define DN1      (DN0+1)
  32   {2, 2, MN10300_OPERAND_DREG},
  33
  34 /* dn register in the third register operand position.  */
  35 #define DN2      (DN1+1)
  36   {2, 4, MN10300_OPERAND_DREG},
  37
  38 /* dm register in the first register operand position.  */
  39 #define DM0      (DN2+1)
  40   {2, 0, MN10300_OPERAND_DREG},
  41
  42 /* dm register in the second register operand position.  */
  43 #define DM1      (DM0+1)
  44   {2, 2, MN10300_OPERAND_DREG},
  45
  46 /* dm register in the third register operand position.  */
  47 #define DM2      (DM1+1)
  48   {2, 4, MN10300_OPERAND_DREG},
  49
  50 /* an register in the first register operand position.  */
  51 #define AN0      (DM2+1)
  52   {2, 0, MN10300_OPERAND_AREG},
  53
  54 /* an register in the second register operand position.  */
  55 #define AN1      (AN0+1)
  56   {2, 2, MN10300_OPERAND_AREG},
  57
  58 /* an register in the third register operand position.  */
  59 #define AN2      (AN1+1)
  60   {2, 4, MN10300_OPERAND_AREG},
  61
  62 /* am register in the first register operand position.  */
  63 #define AM0      (AN2+1)
  64   {2, 0, MN10300_OPERAND_AREG},
  65
  66 /* am register in the second register operand position.  */
  67 #define AM1      (AM0+1)
  68   {2, 2, MN10300_OPERAND_AREG},
  69
  70 /* am register in the third register operand position.  */
  71 #define AM2      (AM1+1)
  72   {2, 4, MN10300_OPERAND_AREG},
  73
  74 /* 8 bit unsigned immediate which may promote to a 16bit
  75    unsigned immediate.  */
  76 #define IMM8    (AM2+1)
  77   {8, 0, MN10300_OPERAND_PROMOTE},
  78
  79 /* 16 bit unsigned immediate which may promote to a 32bit
  80    unsigned immediate.  */
  81 #define IMM16    (IMM8+1)
  82   {16, 0, MN10300_OPERAND_PROMOTE},
  83
  84 /* 16 bit pc-relative immediate which may promote to a 16bit
  85    pc-relative immediate.  */
  86 #define IMM16_PCREL    (IMM16+1)
  87   {16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_PCREL},
  88
  89 /* 16bit unsigned dispacement in a memory operation which
  90    may promote to a 32bit displacement.  */
  91 #define IMM16_MEM    (IMM16_PCREL+1)
  92   {16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
  93
  94 /* 32bit immediate, high 16 bits in the main instruction
  95    word, 16bits in the extension word.
  96
  97    The "bits" field indicates how many bits are in the
  98    main instruction word for MN10300_OPERAND_SPLIT!  */
  99 #define IMM32    (IMM16_MEM+1)
 100   {16, 0, MN10300_OPERAND_SPLIT},
 101
 102 /* 32bit pc-relative offset.  */
 103 #define IMM32_PCREL    (IMM32+1)
 104   {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
 105
 106 /* 32bit memory offset.  */
 107 #define IMM32_MEM    (IMM32_PCREL+1)
 108   {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
 109
 110 /* 32bit immediate, high 16 bits in the main instruction
 111    word, 16bits in the extension word, low 16bits are left
 112    shifted 8 places.
 113
 114    The "bits" field indicates how many bits are in the
 115    main instruction word for MN10300_OPERAND_SPLIT!  */
 116 #define IMM32_LOWSHIFT8    (IMM32_MEM+1)
 117   {16, 8, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
 118
 119 /* 32bit immediate, high 24 bits in the main instruction
 120    word, 8 in the extension word.
 121
 122    The "bits" field indicates how many bits are in the
 123    main instruction word for MN10300_OPERAND_SPLIT!  */
 124 #define IMM32_HIGH24    (IMM32_LOWSHIFT8+1)
 125   {24, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
 126
 127 /* 32bit immediate, high 24 bits in the main instruction
 128    word, 8 in the extension word, low 8 bits are left
 129    shifted 16 places.
 130
 131    The "bits" field indicates how many bits are in the
 132    main instruction word for MN10300_OPERAND_SPLIT!  */
 133 #define IMM32_HIGH24_LOWSHIFT16    (IMM32_HIGH24+1)
 134   {24, 16, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
 135
 136 /* Stack pointer.  */
 137 #define SP    (IMM32_HIGH24_LOWSHIFT16+1)
 138   {8, 0, MN10300_OPERAND_SP},
 139
 140 /* Processor status word.  */
 141 #define PSW    (SP+1)
 142   {0, 0, MN10300_OPERAND_PSW},
 143
 144 /* MDR register.  */
 145 #define MDR    (PSW+1)
 146   {0, 0, MN10300_OPERAND_MDR},
 147
 148 /* Index register.  */
 149 #define DI (MDR+1)
 150   {2, 2, MN10300_OPERAND_DREG},
 151
 152 /* 8 bit signed displacement, may promote to 16bit signed dispacement.  */
 153 #define SD8    (DI+1)
 154   {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
 155
 156 /* 16 bit signed displacement, may promote to 32bit dispacement.  */
 157 #define SD16    (SD8+1)
 158   {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
 159
 160 /* 8 bit signed displacement that can not promote.  */
 161 #define SD8N    (SD16+1)
 162   {8, 0, MN10300_OPERAND_SIGNED},
 163
 164 /* 8 bit pc-relative displacement.  */
 165 #define SD8N_PCREL    (SD8N+1)
 166   {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PCREL},
 167
 168 /* 8 bit signed displacement shifted left 8 bits in the instruction.  */
 169 #define SD8N_SHIFT8    (SD8N_PCREL+1)
 170   {8, 8, MN10300_OPERAND_SIGNED},
 171
 172 /* 8 bit signed immediate which may promote to 16bit signed immediate.  */
 173 #define SIMM8    (SD8N_SHIFT8+1)
 174   {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
 175
 176 /* 16 bit signed immediate which may promote to 32bit  immediate.  */
 177 #define SIMM16    (SIMM8+1)
 178   {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
 179
 180 /* Either an open paren or close paren.  */
 181 #define PAREN   (SIMM16+1)
 182   {0, 0, MN10300_OPERAND_PAREN},
 183
 184 /* dn register that appears in the first and second register positions.  */
 185 #define DN01     (PAREN+1)
 186   {2, 0, MN10300_OPERAND_DREG | MN10300_OPERAND_REPEATED},
 187
 188 /* an register that appears in the first and second register positions.  */
 189 #define AN01     (DN01+1)
 190   {2, 0, MN10300_OPERAND_AREG | MN10300_OPERAND_REPEATED},
 191
 192 /* 16bit pc-relative displacement which may promote to 32bit pc-relative
 193    displacement.  */
 194 #define D16_SHIFT (AN01+1)
 195   {16, 8, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_PCREL},
 196
 197 /* 8 bit immediate found in the extension word.  */
 198 #define IMM8E    (D16_SHIFT+1)
 199   {8, 0, MN10300_OPERAND_EXTENDED},
 200
 201 /* Register list found in the extension word shifted 8 bits left.  */
 202 #define REGSE_SHIFT8    (IMM8E+1)
 203   {8, 8, MN10300_OPERAND_EXTENDED | MN10300_OPERAND_REG_LIST},
 204
 205 /* Register list shifted 8 bits left.  */
 206 #define REGS_SHIFT8 (REGSE_SHIFT8 + 1)
 207   {8, 8, MN10300_OPERAND_REG_LIST},
 208
 209 /* Reigster list.  */
 210 #define REGS    (REGS_SHIFT8+1)
 211   {8, 0, MN10300_OPERAND_REG_LIST},
 212 } ;
 213
 214 #define MEM(ADDR) PAREN, ADDR, PAREN
 215 #define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
 216 \f
 217 /* The opcode table.
 218
 219    The format of the opcode table is:
 220
 221    NAME         OPCODE          MASK            { OPERANDS }
 222
 223    NAME is the name of the instruction.
 224    OPCODE is the instruction opcode.
 225    MASK is the opcode mask; this is used to tell the disassembler
 226      which bits in the actual opcode must match OPCODE.
 227    OPERANDS is the list of operands.
 228
 229    The disassembler reads the table in order and prints the first
 230    instruction which matches, so this table is sorted to put more
 231    specific instructions before more general instructions.  It is also
 232    sorted by major opcode.  */
 233
 234 const struct mn10300_opcode mn10300_opcodes[] = {
 235 { "mov",        0x8000,         0xf000,         FMT_S1, {SIMM8, DN01}},
 236 { "mov",        0x80,           0xf0,           FMT_S0, {DM1, DN0}},
 237 { "mov",        0xf1e0,         0xfff0,         FMT_D0, {DM1, AN0}},
 238 { "mov",        0xf1d0,         0xfff0,         FMT_D0, {AM1, DN0}},
 239 { "mov",        0x9000,         0xf000,         FMT_S1, {IMM8, AN01}},
 240 { "mov",        0x90,           0xf0,           FMT_S0, {AM1, AN0}},
 241 { "mov",        0x3c,           0xfc,           FMT_S0, {SP, AN0}},
 242 { "mov",        0xf2f0,         0xfff3,         FMT_D0, {AM1, SP}},
 243 { "mov",        0xf2e4,         0xfffc,         FMT_D0, {PSW, DN0}},
 244 { "mov",        0xf2f3,         0xfff3,         FMT_D0, {DM1, PSW}},
 245 { "mov",        0xf2e0,         0xfffc,         FMT_D0, {MDR, DN0}},
 246 { "mov",        0xf2f2,         0xfff3,         FMT_D0, {DM1, MDR}},
 247 { "mov",        0x70,           0xf0,           FMT_S0, {MEM(AM0), DN1}},
 248 { "mov",        0xf80000,       0xfff000,       FMT_D1, {MEM2(SD8, AM0), DN1}},
 249 { "mov",        0xfa000000,     0xfff00000,     FMT_D2, {MEM2(SD16, AM0), DN1}},
 250 { "mov",        0xfc000000,     0xfff00000,     FMT_D4, {MEM2(IMM32,AM0), DN1}},
 251 { "mov",        0x5800,         0xfc00,         FMT_S1, {MEM2(IMM8, SP), DN0}},
 252 { "mov",        0xfab40000,     0xfffc0000,     FMT_D2, {MEM2(IMM16, SP), DN0}},
 253 { "mov",        0xfcb40000,     0xfffc0000,     FMT_D4, {MEM2(IMM32, SP), DN0}},
 254 { "mov",        0xf300,         0xffc0,         FMT_D0, {MEM2(DI, AM0), DN2}},
 255 { "mov",        0x300000,       0xfc0000,       FMT_S2, {MEM(IMM16_MEM), DN0}},
 256 { "mov",        0xfca40000,     0xfffc0000,     FMT_D4, {MEM(IMM32_MEM), DN0}},
 257 { "mov",        0xf000,         0xfff0,         FMT_D0, {MEM(AM0), AN1}},
 258 { "mov",        0xf82000,       0xfff000,       FMT_D1, {MEM2(SD8,AM0), AN1}},
 259 { "mov",        0xfa200000,     0xfff00000,     FMT_D2, {MEM2(SD16, AM0), AN1}},
 260 { "mov",        0xfc200000,     0xfff00000,     FMT_D4, {MEM2(IMM32,AM0), AN1}},
 261 { "mov",        0x5c00,         0xfc00,         FMT_S1, {MEM2(IMM8, SP), AN0}},
 262 { "mov",        0xfab00000,     0xfffc0000,     FMT_D2, {MEM2(IMM16, SP), AN0}},
 263 { "mov",        0xfcb00000,     0xfffc0000,     FMT_D4, {MEM2(IMM32, SP), AN0}},
 264 { "mov",        0xf380,         0xffc0,         FMT_D0, {MEM2(DI, AM0), AN2}},
 265 { "mov",        0xfaa00000,     0xfffc0000,     FMT_D2, {MEM(IMM16_MEM), AN0}},
 266 { "mov",        0xfca00000,     0xfffc0000,     FMT_D4, {MEM(IMM32_MEM), AN0}},
 267 { "mov",        0xf8f000,       0xfffc00,       FMT_D1, {MEM2(SD8N, AM0), SP}},
 268 { "mov",        0x60,           0xf0,           FMT_S0, {DM1, MEM(AN0)}},
 269 { "mov",        0xf81000,       0xfff000,       FMT_D1, {DM1, MEM2(SD8, AN0)}},
 270 { "mov",        0xfa100000,     0xfff00000,     FMT_D2, {DM1, MEM2(SD16, AN0)}},
 271 { "mov",        0xfc100000,     0xfff00000,     FMT_D4, {DM1, MEM2(IMM32,AN0)}},
 272 { "mov",        0x4200,         0xf300,         FMT_S1, {DM1, MEM2(IMM8, SP)}},
 273 { "mov",        0xfa910000,     0xfff30000,     FMT_D2, {DM1, MEM2(IMM16, SP)}},
 274 { "mov",        0xfc910000,     0xfff30000,     FMT_D4, {DM1, MEM2(IMM32, SP)}},
 275 { "mov",        0xf340,         0xffc0,         FMT_D0, {DM2, MEM2(DI, AN0)}},
 276 { "mov",        0x010000,       0xf30000,       FMT_S2, {DM1, MEM(IMM16_MEM)}},
 277 { "mov",        0xfc810000,     0xfff30000,     FMT_D4, {DM1, MEM(IMM32_MEM)}},
 278 { "mov",        0xf010,         0xfff0,         FMT_D0, {AM1, MEM(AN0)}},
 279 { "mov",        0xf83000,       0xfff000,       FMT_D1, {AM1, MEM2(SD8, AN0)}},
 280 { "mov",        0xfa300000,     0xfff00000,     FMT_D2, {AM1, MEM2(SD16, AN0)}},
 281 { "mov",        0xfc300000,     0xfff00000,     FMT_D4, {AM1, MEM2(IMM32,AN0)}},
 282 { "mov",        0x4300,         0xf300,         FMT_S1, {AM1, MEM2(IMM8, SP)}},
 283 { "mov",        0xfa900000,     0xfff30000,     FMT_D2, {AM1, MEM2(IMM16, SP)}},
 284 { "mov",        0xfc900000,     0xfff30000,     FMT_D4, {AM1, MEM2(IMM32, SP)}},
 285 { "mov",        0xf3c0,         0xffc0,         FMT_D0, {AM2, MEM2(DI, AN0)}},
 286 { "mov",        0xfa800000,     0xfff30000,     FMT_D2, {AM1, MEM(IMM16_MEM)}},
 287 { "mov",        0xfc800000,     0xfff30000,     FMT_D4, {AM1, MEM(IMM32_MEM)}},
 288 { "mov",        0xf8f400,       0xfffc00,       FMT_D1, {SP, MEM2(SD8N, AN0)}},
 289 { "mov",        0x2c0000,       0xfc0000,       FMT_S2, {SIMM16, DN0}},
 290 { "mov",        0xfccc0000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},
 291 { "mov",        0x240000,       0xfc0000,       FMT_S2, {IMM16, AN0}},
 292 { "mov",        0xfcdc0000,     0xfffc0000,     FMT_D4, {IMM32, AN0}},
 293
 294 { "movbu",      0xf040,         0xfff0,         FMT_D0, {MEM(AM0), DN1}},
 295 { "movbu",      0xf84000,       0xfff000,       FMT_D1, {MEM2(SD8, AM0), DN1}},
 296 { "movbu",      0xfa400000,     0xfff00000,     FMT_D2, {MEM2(SD16, AM0), DN1}},
 297 { "movbu",      0xfc400000,     0xfff00000,     FMT_D4, {MEM2(IMM32,AM0), DN1}},
 298 { "movbu",      0xf8b800,       0xfffc00,       FMT_D1, {MEM2(IMM8, SP), DN0}},
 299 { "movbu",      0xfab80000,     0xfffc0000,     FMT_D2, {MEM2(IMM16, SP), DN0}},
 300 { "movbu",      0xfcb80000,     0xfffc0000,     FMT_D4, {MEM2(IMM32, SP), DN0}},
 301 { "movbu",      0xf400,         0xffc0,         FMT_D0, {MEM2(DI, AM0), DN2}},
 302 { "movbu",      0x340000,       0xfc0000,       FMT_S2, {MEM(IMM16_MEM), DN0}},
 303 { "movbu",      0xfca80000,     0xfffc0000,     FMT_D4, {MEM(IMM32_MEM), DN0}},
 304 { "movbu",      0xf050,         0xfff0,         FMT_D0, {DM1, MEM(AN0)}},
 305 { "movbu",      0xf85000,       0xfff000,       FMT_D1, {DM1, MEM2(SD8, AN0)}},
 306 { "movbu",      0xfa500000,     0xfff00000,     FMT_D2, {DM1, MEM2(SD16, AN0)}},
 307 { "movbu",      0xfc500000,     0xfff00000,     FMT_D4, {DM1, MEM2(IMM32,AN0)}},
 308 { "movbu",      0xf89200,       0xfff300,       FMT_D1, {DM1, MEM2(IMM8, SP)}},
 309 { "movbu",      0xfa920000,     0xfff30000,     FMT_D2, {DM1, MEM2(IMM16, SP)}},
 310 { "movbu",      0xfc920000,     0xfff30000,     FMT_D4, {DM1, MEM2(IMM32, SP)}},
 311 { "movbu",      0xf440,         0xffc0,         FMT_D0, {DM2, MEM2(DI, AN0)}},
 312 { "movbu",      0x020000,       0xf30000,       FMT_S2, {DM1, MEM(IMM16_MEM)}},
 313 { "movbu",      0xfc820000,     0xfff30000,     FMT_D4, {DM1, MEM(IMM32_MEM)}},
 314
 315 { "movhu",      0xf060,         0xfff0,         FMT_D0, {MEM(AM0), DN1}},
 316 { "movhu",      0xf86000,       0xfff000,       FMT_D1, {MEM2(SD8, AM0), DN1}},
 317 { "movhu",      0xfa600000,     0xfff00000,     FMT_D2, {MEM2(SD16, AM0), DN1}},
 318 { "movhu",      0xfc600000,     0xfff00000,     FMT_D4, {MEM2(IMM32,AM0), DN1}},
 319 { "movhu",      0xf8bc00,       0xfffc00,       FMT_D1, {MEM2(IMM8, SP), DN0}},
 320 { "movhu",      0xfabc0000,     0xfffc0000,     FMT_D2, {MEM2(IMM16, SP), DN0}},
 321 { "movhu",      0xfcbc0000,     0xfffc0000,     FMT_D4, {MEM2(IMM32, SP), DN0}},
 322 { "movhu",      0xf480,         0xffc0,         FMT_D0, {MEM2(DI, AM0), DN2}},
 323 { "movhu",      0x380000,       0xfc0000,       FMT_S2, {MEM(IMM16_MEM), DN0}},
 324 { "movhu",      0xfcac0000,     0xfffc0000,     FMT_D4, {MEM(IMM32_MEM), DN0}},
 325 { "movhu",      0xf070,         0xfff0,         FMT_D0, {DM1, MEM(AN0)}},
 326 { "movhu",      0xf87000,       0xfff000,       FMT_D1, {DM1, MEM2(SD8, AN0)}},
 327 { "movhu",      0xfa700000,     0xfff00000,     FMT_D2, {DM1, MEM2(SD16, AN0)}},
 328 { "movhu",      0xfc700000,     0xfff00000,     FMT_D4, {DM1, MEM2(IMM32,AN0)}},
 329 { "movhu",      0xf89300,       0xfff300,       FMT_D1, {DM1, MEM2(IMM8, SP)}},
 330 { "movhu",      0xfa930000,     0xfff30000,     FMT_D2, {DM1, MEM2(IMM16, SP)}},
 331 { "movhu",      0xfc930000,     0xfff30000,     FMT_D4, {DM1, MEM2(IMM32, SP)}},
 332 { "movhu",      0xf4c0,         0xffc0,         FMT_D0, {DM2, MEM2(DI, AN0)}},
 333 { "movhu",      0x030000,       0xf30000,       FMT_S2, {DM1, MEM(IMM16_MEM)}},
 334 { "movhu",      0xfc830000,     0xfff30000,     FMT_D4, {DM1, MEM(IMM32_MEM)}},
 335
 336 { "ext",        0xf2d0,         0xfffc,         FMT_D0, {DN0}},
 337 { "extb",       0x10,           0xfc,           FMT_S0, {DN0}},
 338 { "extbu",      0x14,           0xfc,           FMT_S0, {DN0}},
 339 { "exth",       0x18,           0xfc,           FMT_S0, {DN0}},
 340 { "exthu",      0x1c,           0xfc,           FMT_S0, {DN0}},
 341
 342 { "movm",       0xce00,         0xff00,         FMT_S1, {MEM(SP), REGS}},
 343 { "movm",       0xcf00,         0xff00,         FMT_S1, {REGS, MEM(SP)}},
 344
 345 { "clr",        0x00,           0xf3,           FMT_S0, {DN1}},
 346
 347 { "add",        0xe0,           0xf0,           FMT_S0, {DM1, DN0}},
 348 { "add",        0xf160,         0xfff0,         FMT_D0, {DM1, AN0}},
 349 { "add",        0xf150,         0xfff0,         FMT_D0, {AM1, DN0}},
 350 { "add",        0xf170,         0xfff0,         FMT_D0, {AM1, AN0}},
 351 { "add",        0x2800,         0xfc00,         FMT_S1, {SIMM8, DN0}},
 352 { "add",        0xfac00000,     0xfffc0000,     FMT_D2, {SIMM16, DN0}},
 353 { "add",        0xfcc00000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},
 354 { "add",        0x2000,         0xfc00,         FMT_S1, {SIMM8, AN0}},
 355 { "add",        0xfad00000,     0xfffc0000,     FMT_D2, {SIMM16, AN0}},
 356 { "add",        0xfcd00000,     0xfffc0000,     FMT_D4, {IMM32, AN0}},
 357 { "add",        0xf8fe00,       0xffff00,       FMT_D1, {SIMM8, SP}},
 358 { "add",        0xfafe0000,     0xffff0000,     FMT_D2, {SIMM16, SP}},
 359 { "add",        0xfcfe0000,     0xffff0000,     FMT_D4, {IMM32, SP}},
 360 { "addc",       0xf140,         0xfff0,         FMT_D0, {DM1, DN0}},
 361
 362 { "sub",        0xf100,         0xfff0,         FMT_D0, {DM1, DN0}},
 363 { "sub",        0xf120,         0xfff0,         FMT_D0, {DM1, AN0}},
 364 { "sub",        0xf110,         0xfff0,         FMT_D0, {AM1, DN0}},
 365 { "sub",        0xf130,         0xfff0,         FMT_D0, {AM1, AN0}},
 366 { "sub",        0xfcc40000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},
 367 { "sub",        0xfcd40000,     0xfffc0000,     FMT_D4, {IMM32, AN0}},
 368 { "subc",       0xf180,         0xfff0,         FMT_D0, {DM1, DN0}},
 369
 370 { "mul",        0xf240,         0xfff0,         FMT_D0, {DM1, DN0}},
 371 { "mulu",       0xf250,         0xfff0,         FMT_D0, {DM1, DN0}},
 372
 373 { "div",        0xf260,         0xfff0,         FMT_D0, {DM1, DN0}},
 374 { "divu",       0xf270,         0xfff0,         FMT_D0, {DM1, DN0}},
 375
 376 { "inc",        0x40,           0xf3,           FMT_S0, {DN1}},
 377 { "inc",        0x41,           0xf3,           FMT_S0, {AN1}},
 378 { "inc4",       0x50,           0xfc,           FMT_S0, {AN0}},
 379
 380 { "cmp",        0xa000,         0xf000,         FMT_S1, {SIMM8, DN01}},
 381 { "cmp",        0xa0,           0xf0,           FMT_S0, {DM1, DN0}},
 382 { "cmp",        0xf1a0,         0xfff0,         FMT_D0, {DM1, AN0}},
 383 { "cmp",        0xf190,         0xfff0,         FMT_D0, {AM1, DN0}},
 384 { "cmp",        0xb000,         0xf000,         FMT_S1, {IMM8, AN01}},
 385 { "cmp",        0xb0,           0xf0,           FMT_S0, {AM1, AN0}},
 386 { "cmp",        0xfac80000,     0xfffc0000,     FMT_D2, {SIMM16, DN0}},
 387 { "cmp",        0xfcc80000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},
 388 { "cmp",        0xfad80000,     0xfffc0000,     FMT_D2, {IMM16, AN0}},
 389 { "cmp",        0xfcd80000,     0xfffc0000,     FMT_D4, {IMM32, AN0}},
 390
 391 { "and",        0xf200,         0xfff0,         FMT_D0, {DM1, DN0}},
 392 { "and",        0xf8e000,       0xfffc00,       FMT_D1, {IMM8, DN0}},
 393 { "and",        0xfae00000,     0xfffc0000,     FMT_D2, {IMM16, DN0}},
 394 { "and",        0xfce00000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},
 395 { "and",        0xfafc0000,     0xffff0000,     FMT_D2, {IMM16, PSW}},
 396 { "or",         0xf210,         0xfff0,         FMT_D0, {DM1, DN0}},
 397 { "or",         0xf8e400,       0xfffc00,       FMT_D1, {IMM8, DN0}},
 398 { "or",         0xfae40000,     0xfffc0000,     FMT_D2, {IMM16, DN0}},
 399 { "or",         0xfce40000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},
 400 { "or",         0xfafd0000,     0xffff0000,     FMT_D2, {IMM16, PSW}},
 401 { "xor",        0xf220,         0xfff0,         FMT_D0, {DM1, DN0}},
 402 { "xor",        0xfae80000,     0xfffc0000,     FMT_D2, {IMM16, DN0}},
 403 { "xor",        0xfce80000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},
 404 { "not",        0xf230,         0xfffc,         FMT_D0, {DN0}},
 405
 406 { "btst",       0xf8ec00,       0xfffc00,       FMT_D1, {IMM8, DN0}},
 407 { "btst",       0xfaec0000,     0xfffc0000,     FMT_D2, {IMM16, DN0}},
 408 { "btst",       0xfcec0000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},
 409 { "btst",       0xfe020000,     0xffff0000,     FMT_D5, {IMM8E,
 410                                                          MEM(IMM32_LOWSHIFT8)}},
 411 { "btst",       0xfaf80000,     0xfffc0000,     FMT_D2,
 412                                         {IMM8, MEM2(SD8N_SHIFT8,AN0)}},
 413 { "bset",       0xf080,         0xfff0,         FMT_D0, {DM1, MEM(AN0)}},
 414 { "bset",       0xfe000000,     0xffff0000,     FMT_D5, {IMM8E,
 415                                                          MEM(IMM32_LOWSHIFT8)}},
 416 { "bset",       0xfaf00000,     0xfffc0000,     FMT_D2,
 417                                         {IMM8, MEM2(SD8N_SHIFT8,AN0)}},
 418 { "bclr",       0xf090,         0xfff0,         FMT_D0, {DM1, MEM(AN0)}},
 419 { "bclr",       0xfe010000,     0xffff0000,     FMT_D5, {IMM8E,
 420                                                          MEM(IMM32_LOWSHIFT8)}},
 421 { "bclr",       0xfaf40000,     0xfffc0000,     FMT_D2, {IMM8,
 422                                                 MEM2(SD8N_SHIFT8,AN0)}},
 423
 424 { "asr",        0xf2b0,         0xfff0,         FMT_D0, {DM1, DN0}},
 425 { "asr",        0xf8c800,       0xfffc00,       FMT_D1, {IMM8, DN0}},
 426 { "lsr",        0xf2a0,         0xfff0,         FMT_D0, {DM1, DN0}},
 427 { "lsr",        0xf8c400,       0xfffc00,       FMT_D1, {IMM8, DN0}},
 428 { "asl",        0xf290,         0xfff0,         FMT_D0, {DM1, DN0}},
 429 { "asl",        0xf8c000,       0xfffc00,       FMT_D1, {IMM8, DN0}},
 430 { "asl2",       0x54,           0xfc,           FMT_S0, {DN0}},
 431 { "ror",        0xf284,         0xfffc,         FMT_D0, {DN0}},
 432 { "rol",        0xf280,         0xfffc,         FMT_D0, {DN0}},
 433
 434 { "beq",        0xc800,         0xff00,         FMT_S1, {SD8N_PCREL}},
 435 { "bne",        0xc900,         0xff00,         FMT_S1, {SD8N_PCREL}},
 436 { "bgt",        0xc100,         0xff00,         FMT_S1, {SD8N_PCREL}},
 437 { "bge",        0xc200,         0xff00,         FMT_S1, {SD8N_PCREL}},
 438 { "ble",        0xc300,         0xff00,         FMT_S1, {SD8N_PCREL}},
 439 { "blt",        0xc000,         0xff00,         FMT_S1, {SD8N_PCREL}},
 440 { "bhi",        0xc500,         0xff00,         FMT_S1, {SD8N_PCREL}},
 441 { "bcc",        0xc600,         0xff00,         FMT_S1, {SD8N_PCREL}},
 442 { "bls",        0xc700,         0xff00,         FMT_S1, {SD8N_PCREL}},
 443 { "bcs",        0xc400,         0xff00,         FMT_S1, {SD8N_PCREL}},
 444 { "bvc",        0xf8e800,       0xffff00,       FMT_D1, {SD8N_PCREL}},
 445 { "bvs",        0xf8e900,       0xffff00,       FMT_D1, {SD8N_PCREL}},
 446 { "bnc",        0xf8ea00,       0xffff00,       FMT_D1, {SD8N_PCREL}},
 447 { "bns",        0xf8eb00,       0xffff00,       FMT_D1, {SD8N_PCREL}},
 448 { "bra",        0xca00,         0xff00,         FMT_S1, {SD8N_PCREL}},
 449
 450 { "leq",        0xd8,           0xff,           FMT_S0, {UNUSED}},
 451 { "lne",        0xd9,           0xff,           FMT_S0, {UNUSED}},
 452 { "lgt",        0xd1,           0xff,           FMT_S0, {UNUSED}},
 453 { "lge",        0xd2,           0xff,           FMT_S0, {UNUSED}},
 454 { "lle",        0xd3,           0xff,           FMT_S0, {UNUSED}},
 455 { "llt",        0xd0,           0xff,           FMT_S0, {UNUSED}},
 456 { "lhi",        0xd5,           0xff,           FMT_S0, {UNUSED}},
 457 { "lcc",        0xd6,           0xff,           FMT_S0, {UNUSED}},
 458 { "lls",        0xd7,           0xff,           FMT_S0, {UNUSED}},
 459 { "lcs",        0xd4,           0xff,           FMT_S0, {UNUSED}},
 460 { "lra",        0xda,           0xff,           FMT_S0, {UNUSED}},
 461 { "setlb",      0xdb,           0xff,           FMT_S0, {UNUSED}},
 462
 463 { "jmp",        0xf0f4,         0xfffc,         FMT_D0, {PAREN,AN0,PAREN}},
 464 { "jmp",        0xcc0000,       0xff0000,       FMT_S2, {IMM16_PCREL}},
 465 { "jmp",        0xdc000000,     0xff000000,     FMT_S4, {IMM32_HIGH24}},
 466 { "call",       0xcd000000,     0xff000000,     FMT_S4, {D16_SHIFT,REGS,IMM8E}},
 467 { "call",       0xdd000000,     0xff000000,     FMT_S6,
 468                                         {IMM32_HIGH24_LOWSHIFT16,REGSE_SHIFT8,IMM8E}},
 469 { "calls",      0xf0f0,         0xfffc,         FMT_D0, {PAREN,AN0,PAREN}},
 470 { "calls",      0xfaff0000,     0xffff0000,     FMT_D2, {IMM16_PCREL}},
 471 { "calls",      0xfcff0000,     0xffff0000,     FMT_D4, {IMM32_PCREL}},
 472
 473 { "ret",        0xdf0000,       0xff0000,       FMT_S2, {REGS_SHIFT8, IMM8}},
 474 { "retf",       0xde0000,       0xff0000,       FMT_S2, {REGS_SHIFT8, IMM8}},
 475 { "rets",       0xf0fc,         0xffff,         FMT_D0, {UNUSED}},
 476 { "rti",        0xf0fd,         0xffff,         FMT_D0, {UNUSED}},
 477 { "trap",       0xf0fe,         0xffff,         FMT_D0, {UNUSED}},
 478 { "rtm",        0xf0ff,         0xffff,         FMT_D0, {UNUSED}},
 479 { "nop",        0xcb,           0xff,           FMT_S0, {UNUSED}},
 480 /* { "udf", 0, 0, {0}},  */
 481
 482 { "putx",       0xf500,         0xfff0,         FMT_D0, {DN01}},
 483 { "getx",       0xf6f0,         0xfff0,         FMT_D0, {DN01}},
 484 { "mulq",       0xf600,         0xfff0,         FMT_D0, {DM1, DN0}},
 485 { "mulq",       0xf90000,       0xfffc00,       FMT_D1, {SIMM8, DN0}},
 486 { "mulq",       0xfb000000,     0xfffc0000,     FMT_D2, {SIMM16, DN0}},
 487 { "mulq",       0xfd000000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},
 488 { "mulqu",      0xf610,         0xfff0,         FMT_D0, {DM1, DN0}},
 489 { "mulqu",      0xf91400,       0xfffc00,       FMT_D1, {SIMM8, DN0}},
 490 { "mulqu",      0xfb140000,     0xfffc0000,     FMT_D2, {SIMM16, DN0}},
 491 { "mulqu",      0xfd140000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},
 492 { "sat16",      0xf640,         0xfff0,         FMT_D0, {DM1, DN0}},
 493 { "sat24",      0xf650,         0xfff0,         FMT_D0, {DM1, DN0}},
 494 { "bsch",       0xf670,         0xfff0,         FMT_D0, {DM1, DN0}},
 495
 496 /* Extension.  When talking to the simulator, gdb requires some instruction
 497    that will trigger a "breakpoint" (really just an instruction that isn't
 498    otherwise used by the tools.  This instruction must be the same size
 499    as the smallest instruction on the target machine.  In the case of the
 500    mn10x00 the "break" instruction must be one byte.  0xff is available on
 501    both mn10x00 architectures.  */
 502 { "break",      0xff,           0xff,           FMT_S0, {UNUSED}},
 503 { 0, 0, 0, 0, {0}},
 504
 505 } ;
 506
 507 const int mn10300_num_opcodes =
 508   sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]);
 509
 510 \f