opcodes/ppc-dis.c

   1 /* ppc-dis.c -- Disassemble PowerPC instructions
   2    Copyright (C) 1994-2016 Free Software Foundation, Inc.
   3    Written by Ian Lance Taylor, Cygnus Support
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING.  If not, write to the
  19    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  20    MA 02110-1301, USA.  */
  21
  22 #include "sysdep.h"
  23 #include <stdio.h>
  24 #include "dis-asm.h"
  25 #include "elf-bfd.h"
  26 #include "elf/ppc.h"
  27 #include "opintl.h"
  28 #include "opcode/ppc.h"
  29
  30 /* This file provides several disassembler functions, all of which use
  31    the disassembler interface defined in dis-asm.h.  Several functions
  32    are provided because this file handles disassembly for the PowerPC
  33    in both big and little endian mode and also for the POWER (RS/6000)
  34    chip.  */
  35 static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
  36                                ppc_cpu_t);
  37
  38 struct dis_private
  39 {
  40   /* Stash the result of parsing disassembler_options here.  */
  41   ppc_cpu_t dialect;
  42 } private;
  43
  44 #define POWERPC_DIALECT(INFO) \
  45   (((struct dis_private *) ((INFO)->private_data))->dialect)
  46
  47 struct ppc_mopt {
  48   const char *opt;
  49   ppc_cpu_t cpu;
  50   ppc_cpu_t sticky;
  51 };
  52
  53 struct ppc_mopt ppc_opts[] = {
  54   { "403",     (PPC_OPCODE_PPC | PPC_OPCODE_403),
  55     0 },
  56   { "405",     (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405),
  57     0 },
  58   { "440",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
  59                 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
  60     0 },
  61   { "464",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
  62                 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
  63     0 },
  64   { "476",     (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_440
  65                 | PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
  66     0 },
  67   { "601",     (PPC_OPCODE_PPC | PPC_OPCODE_601),
  68     0 },
  69   { "603",     (PPC_OPCODE_PPC),
  70     0 },
  71   { "604",     (PPC_OPCODE_PPC),
  72     0 },
  73   { "620",     (PPC_OPCODE_PPC | PPC_OPCODE_64),
  74     0 },
  75   { "7400",    (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
  76     0 },
  77   { "7410",    (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
  78     0 },
  79   { "7450",    (PPC_OPCODE_PPC | PPC_OPCODE_7450 | PPC_OPCODE_ALTIVEC),
  80     0 },
  81   { "7455",    (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
  82     0 },
  83   { "750cl",   (PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS)
  84     , 0 },
  85   { "821",     (PPC_OPCODE_PPC | PPC_OPCODE_860),
  86     0 },
  87   { "850",     (PPC_OPCODE_PPC | PPC_OPCODE_860),
  88     0 },
  89   { "860",     (PPC_OPCODE_PPC | PPC_OPCODE_860),
  90     0 },
  91   { "a2",      (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
  92                 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
  93                 | PPC_OPCODE_A2),
  94     0 },
  95   { "altivec", (PPC_OPCODE_PPC),
  96     PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 },
  97   { "any",     0,
  98     PPC_OPCODE_ANY },
  99   { "booke",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
 100     0 },
 101   { "booke32", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
 102     0 },
 103   { "cell",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 104                 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
 105     0 },
 106   { "com",     (PPC_OPCODE_COMMON),
 107     0 },
 108   { "e300",    (PPC_OPCODE_PPC | PPC_OPCODE_E300),
 109     0 },
 110   { "e500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
 111                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 112                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 113                 | PPC_OPCODE_E500),
 114     0 },
 115   { "e500mc",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 116                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 117                 | PPC_OPCODE_E500MC),
 118     0 },
 119   { "e500mc64",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 120                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 121                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
 122                 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 123     0 },
 124   { "e5500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 125                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 126                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 127                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 128                 | PPC_OPCODE_POWER7),
 129     0 },
 130   { "e6500",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 131                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 132                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
 133                 | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4
 134                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 135     0 },
 136   { "e500x2",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
 137                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 138                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 139                 | PPC_OPCODE_E500),
 140     0 },
 141   { "efs",     (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
 142     0 },
 143   { "power4",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
 144     0 },
 145   { "power5",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 146                 | PPC_OPCODE_POWER5),
 147     0 },
 148   { "power6",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 149                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
 150     0 },
 151   { "power7",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 152                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 153                 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 154     0 },
 155   { "power8",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 156                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 157                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM
 158                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX),
 159     0 },
 160   { "power9",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 161                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 162                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 163                 | PPC_OPCODE_HTM | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2
 164                 | PPC_OPCODE_VSX | PPC_OPCODE_VSX3 ),
 165     0 },
 166   { "ppc",     (PPC_OPCODE_PPC),
 167     0 },
 168   { "ppc32",   (PPC_OPCODE_PPC),
 169     0 },
 170   { "ppc64",   (PPC_OPCODE_PPC | PPC_OPCODE_64),
 171     0 },
 172   { "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE),
 173     0 },
 174   { "ppcps",   (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS),
 175     0 },
 176   { "pwr",     (PPC_OPCODE_POWER),
 177     0 },
 178   { "pwr2",    (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
 179     0 },
 180   { "pwr4",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
 181     0 },
 182   { "pwr5",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 183                 | PPC_OPCODE_POWER5),
 184     0 },
 185   { "pwr5x",   (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 186                 | PPC_OPCODE_POWER5),
 187     0 },
 188   { "pwr6",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 189                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
 190     0 },
 191   { "pwr7",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 192                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 193                 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 194     0 },
 195   { "pwr8",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 196                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 197                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM
 198                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX),
 199     0 },
 200   { "pwr9",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 201                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 202                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 203                 | PPC_OPCODE_HTM | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2
 204                 | PPC_OPCODE_VSX | PPC_OPCODE_VSX3 ),
 205     0 },
 206   { "pwrx",    (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
 207     0 },
 208   { "spe",     (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
 209     PPC_OPCODE_SPE },
 210   { "titan",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
 211                 | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
 212     0 },
 213   { "vle",     (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_VLE),
 214     PPC_OPCODE_VLE },
 215   { "vsx",     (PPC_OPCODE_PPC),
 216     PPC_OPCODE_VSX | PPC_OPCODE_VSX3 },
 217   { "htm",     (PPC_OPCODE_PPC),
 218     PPC_OPCODE_HTM },
 219 };
 220
 221 /* Switch between Booke and VLE dialects for interlinked dumps.  */
 222 static ppc_cpu_t
 223 get_powerpc_dialect (struct disassemble_info *info)
 224 {
 225   ppc_cpu_t dialect = 0;
 226
 227   dialect = POWERPC_DIALECT (info);
 228
 229   /* Disassemble according to the section headers flags for VLE-mode.  */
 230   if (dialect & PPC_OPCODE_VLE
 231       && info->section->owner != NULL
 232       && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
 233       && elf_object_id (info->section->owner) == PPC32_ELF_DATA
 234       && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
 235     return dialect;
 236   else
 237     return dialect & ~ PPC_OPCODE_VLE;
 238 }
 239
 240 /* Handle -m and -M options that set cpu type, and .machine arg.  */
 241
 242 ppc_cpu_t
 243 ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg)
 244 {
 245   unsigned int i;
 246
 247   for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
 248     if (strcmp (ppc_opts[i].opt, arg) == 0)
 249       {
 250         if (ppc_opts[i].sticky)
 251           {
 252             *sticky |= ppc_opts[i].sticky;
 253             if ((ppc_cpu & ~*sticky) != 0)
 254               break;
 255           }
 256         ppc_cpu = ppc_opts[i].cpu;
 257         break;
 258       }
 259   if (i >= sizeof (ppc_opts) / sizeof (ppc_opts[0]))
 260     return 0;
 261
 262   ppc_cpu |= *sticky;
 263   return ppc_cpu;
 264 }
 265
 266 /* Determine which set of machines to disassemble for.  */
 267
 268 static void
 269 powerpc_init_dialect (struct disassemble_info *info)
 270 {
 271   ppc_cpu_t dialect = 0;
 272   ppc_cpu_t sticky = 0;
 273   char *arg;
 274   struct dis_private *priv = calloc (sizeof (*priv), 1);
 275
 276   if (priv == NULL)
 277     priv = &private;
 278
 279   switch (info->mach)
 280     {
 281     case bfd_mach_ppc_403:
 282     case bfd_mach_ppc_403gc:
 283       dialect = ppc_parse_cpu (dialect, &sticky, "403");
 284       break;
 285     case bfd_mach_ppc_405:
 286       dialect = ppc_parse_cpu (dialect, &sticky, "405");
 287       break;
 288     case bfd_mach_ppc_601:
 289       dialect = ppc_parse_cpu (dialect, &sticky, "601");
 290       break;
 291     case bfd_mach_ppc_a35:
 292     case bfd_mach_ppc_rs64ii:
 293     case bfd_mach_ppc_rs64iii:
 294       dialect = ppc_parse_cpu (dialect, &sticky, "pwr2") | PPC_OPCODE_64;
 295       break;
 296     case bfd_mach_ppc_e500:
 297       dialect = ppc_parse_cpu (dialect, &sticky, "e500");
 298       break;
 299     case bfd_mach_ppc_e500mc:
 300       dialect = ppc_parse_cpu (dialect, &sticky, "e500mc");
 301       break;
 302     case bfd_mach_ppc_e500mc64:
 303       dialect = ppc_parse_cpu (dialect, &sticky, "e500mc64");
 304       break;
 305     case bfd_mach_ppc_e5500:
 306       dialect = ppc_parse_cpu (dialect, &sticky, "e5500");
 307       break;
 308     case bfd_mach_ppc_e6500:
 309       dialect = ppc_parse_cpu (dialect, &sticky, "e6500");
 310       break;
 311     case bfd_mach_ppc_titan:
 312       dialect = ppc_parse_cpu (dialect, &sticky, "titan");
 313       break;
 314     case bfd_mach_ppc_vle:
 315       dialect = ppc_parse_cpu (dialect, &sticky, "vle");
 316       break;
 317     default:
 318       dialect = ppc_parse_cpu (dialect, &sticky, "power9") | PPC_OPCODE_ANY;
 319     }
 320
 321   arg = info->disassembler_options;
 322   while (arg != NULL)
 323     {
 324       ppc_cpu_t new_cpu = 0;
 325       char *end = strchr (arg, ',');
 326
 327       if (end != NULL)
 328         *end = 0;
 329
 330       if ((new_cpu = ppc_parse_cpu (dialect, &sticky, arg)) != 0)
 331         dialect = new_cpu;
 332       else if (strcmp (arg, "32") == 0)
 333         dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
 334       else if (strcmp (arg, "64") == 0)
 335         dialect |= PPC_OPCODE_64;
 336       else
 337         fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), arg);
 338
 339       if (end != NULL)
 340         *end++ = ',';
 341       arg = end;
 342     }
 343
 344   info->private_data = priv;
 345   POWERPC_DIALECT(info) = dialect;
 346 }
 347
 348 #define PPC_OPCD_SEGS 64
 349 static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1];
 350 #define VLE_OPCD_SEGS 32
 351 static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1];
 352
 353 /* Calculate opcode table indices to speed up disassembly,
 354    and init dialect.  */
 355
 356 void
 357 disassemble_init_powerpc (struct disassemble_info *info)
 358 {
 359   int i;
 360   unsigned short last;
 361
 362   if (powerpc_opcd_indices[PPC_OPCD_SEGS] == 0)
 363     {
 364
 365       i = powerpc_num_opcodes;
 366       while (--i >= 0)
 367         {
 368           unsigned op = PPC_OP (powerpc_opcodes[i].opcode);
 369
 370           powerpc_opcd_indices[op] = i;
 371         }
 372
 373       last = powerpc_num_opcodes;
 374       for (i = PPC_OPCD_SEGS; i > 0; --i)
 375         {
 376           if (powerpc_opcd_indices[i] == 0)
 377             powerpc_opcd_indices[i] = last;
 378           last = powerpc_opcd_indices[i];
 379         }
 380
 381       i = vle_num_opcodes;
 382       while (--i >= 0)
 383         {
 384           unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask);
 385           unsigned seg = VLE_OP_TO_SEG (op);
 386
 387           vle_opcd_indices[seg] = i;
 388         }
 389
 390       last = vle_num_opcodes;
 391       for (i = VLE_OPCD_SEGS; i > 0; --i)
 392         {
 393           if (vle_opcd_indices[i] == 0)
 394             vle_opcd_indices[i] = last;
 395           last = vle_opcd_indices[i];
 396         }
 397     }
 398
 399   if (info->arch == bfd_arch_powerpc)
 400     powerpc_init_dialect (info);
 401 }
 402
 403 /* Print a big endian PowerPC instruction.  */
 404
 405 int
 406 print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
 407 {
 408   return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info));
 409 }
 410
 411 /* Print a little endian PowerPC instruction.  */
 412
 413 int
 414 print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
 415 {
 416   return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info));
 417 }
 418
 419 /* Print a POWER (RS/6000) instruction.  */
 420
 421 int
 422 print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
 423 {
 424   return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
 425 }
 426
 427 /* Extract the operand value from the PowerPC or POWER instruction.  */
 428
 429 static long
 430 operand_value_powerpc (const struct powerpc_operand *operand,
 431                        unsigned long insn, ppc_cpu_t dialect)
 432 {
 433   long value;
 434   int invalid;
 435   /* Extract the value from the instruction.  */
 436   if (operand->extract)
 437     value = (*operand->extract) (insn, dialect, &invalid);
 438   else
 439     {
 440       if (operand->shift >= 0)
 441         value = (insn >> operand->shift) & operand->bitm;
 442       else
 443         value = (insn << -operand->shift) & operand->bitm;
 444       if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
 445         {
 446           /* BITM is always some number of zeros followed by some
 447              number of ones, followed by some number of zeros.  */
 448           unsigned long top = operand->bitm;
 449           /* top & -top gives the rightmost 1 bit, so this
 450              fills in any trailing zeros.  */
 451           top |= (top & -top) - 1;
 452           top &= ~(top >> 1);
 453           value = (value ^ top) - top;
 454         }
 455     }
 456
 457   return value;
 458 }
 459
 460 /* Determine whether the optional operand(s) should be printed.  */
 461
 462 static int
 463 skip_optional_operands (const unsigned char *opindex,
 464                         unsigned long insn, ppc_cpu_t dialect)
 465 {
 466   const struct powerpc_operand *operand;
 467
 468   for (; *opindex != 0; opindex++)
 469     {
 470       operand = &powerpc_operands[*opindex];
 471       if ((operand->flags & PPC_OPERAND_NEXT) != 0
 472           || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
 473               && operand_value_powerpc (operand, insn, dialect) !=
 474                  ppc_optional_operand_value (operand)))
 475         return 0;
 476     }
 477
 478   return 1;
 479 }
 480
 481 /* Find a match for INSN in the opcode table, given machine DIALECT.
 482    A DIALECT of -1 is special, matching all machine opcode variations.  */
 483
 484 static const struct powerpc_opcode *
 485 lookup_powerpc (unsigned long insn, ppc_cpu_t dialect)
 486 {
 487   const struct powerpc_opcode *opcode;
 488   const struct powerpc_opcode *opcode_end;
 489   unsigned long op;
 490
 491   /* Get the major opcode of the instruction.  */
 492   op = PPC_OP (insn);
 493
 494   /* Find the first match in the opcode table for this major opcode.  */
 495   opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1];
 496   for (opcode = powerpc_opcodes + powerpc_opcd_indices[op];
 497        opcode < opcode_end;
 498        ++opcode)
 499     {
 500       const unsigned char *opindex;
 501       const struct powerpc_operand *operand;
 502       int invalid;
 503
 504       if ((insn & opcode->mask) != opcode->opcode
 505           || (dialect != (ppc_cpu_t) -1
 506               && ((opcode->flags & dialect) == 0
 507                   || (opcode->deprecated & dialect) != 0)))
 508         continue;
 509
 510       /* Check validity of operands.  */
 511       invalid = 0;
 512       for (opindex = opcode->operands; *opindex != 0; opindex++)
 513         {
 514           operand = powerpc_operands + *opindex;
 515           if (operand->extract)
 516             (*operand->extract) (insn, dialect, &invalid);
 517         }
 518       if (invalid)
 519         continue;
 520
 521       return opcode;
 522     }
 523
 524   return NULL;
 525 }
 526
 527 /* Find a match for INSN in the VLE opcode table.  */
 528
 529 static const struct powerpc_opcode *
 530 lookup_vle (unsigned long insn)
 531 {
 532   const struct powerpc_opcode *opcode;
 533   const struct powerpc_opcode *opcode_end;
 534   unsigned op, seg;
 535
 536   op = PPC_OP (insn);
 537   if (op >= 0x20 && op <= 0x37)
 538     {
 539       /* This insn has a 4-bit opcode.  */
 540       op &= 0x3c;
 541     }
 542   seg = VLE_OP_TO_SEG (op);
 543
 544   /* Find the first match in the opcode table for this major opcode.  */
 545   opcode_end = vle_opcodes + vle_opcd_indices[seg + 1];
 546   for (opcode = vle_opcodes + vle_opcd_indices[seg];
 547        opcode < opcode_end;
 548        ++opcode)
 549     {
 550       unsigned long table_opcd = opcode->opcode;
 551       unsigned long table_mask = opcode->mask;
 552       bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
 553       unsigned long insn2;
 554       const unsigned char *opindex;
 555       const struct powerpc_operand *operand;
 556       int invalid;
 557
 558       insn2 = insn;
 559       if (table_op_is_short)
 560         insn2 >>= 16;
 561       if ((insn2 & table_mask) != table_opcd)
 562         continue;
 563
 564       /* Check validity of operands.  */
 565       invalid = 0;
 566       for (opindex = opcode->operands; *opindex != 0; ++opindex)
 567         {
 568           operand = powerpc_operands + *opindex;
 569           if (operand->extract)
 570             (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
 571         }
 572       if (invalid)
 573         continue;
 574
 575       return opcode;
 576     }
 577
 578   return NULL;
 579 }
 580
 581 /* Print a PowerPC or POWER instruction.  */
 582
 583 static int
 584 print_insn_powerpc (bfd_vma memaddr,
 585                     struct disassemble_info *info,
 586                     int bigendian,
 587                     ppc_cpu_t dialect)
 588 {
 589   bfd_byte buffer[4];
 590   int status;
 591   unsigned long insn;
 592   const struct powerpc_opcode *opcode;
 593   bfd_boolean insn_is_short;
 594
 595   status = (*info->read_memory_func) (memaddr, buffer, 4, info);
 596   if (status != 0)
 597     {
 598       /* The final instruction may be a 2-byte VLE insn.  */
 599       if ((dialect & PPC_OPCODE_VLE) != 0)
 600         {
 601           /* Clear buffer so unused bytes will not have garbage in them.  */
 602           buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0;
 603           status = (*info->read_memory_func) (memaddr, buffer, 2, info);
 604           if (status != 0)
 605             {
 606               (*info->memory_error_func) (status, memaddr, info);
 607               return -1;
 608             }
 609         }
 610       else
 611         {
 612           (*info->memory_error_func) (status, memaddr, info);
 613           return -1;
 614         }
 615     }
 616
 617   if (bigendian)
 618     insn = bfd_getb32 (buffer);
 619   else
 620     insn = bfd_getl32 (buffer);
 621
 622   /* Get the major opcode of the insn.  */
 623   opcode = NULL;
 624   insn_is_short = FALSE;
 625   if ((dialect & PPC_OPCODE_VLE) != 0)
 626     {
 627       opcode = lookup_vle (insn);
 628       if (opcode != NULL)
 629         insn_is_short = PPC_OP_SE_VLE(opcode->mask);
 630     }
 631   if (opcode == NULL)
 632     opcode = lookup_powerpc (insn, dialect);
 633   if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
 634     opcode = lookup_powerpc (insn, (ppc_cpu_t) -1);
 635
 636   if (opcode != NULL)
 637     {
 638       const unsigned char *opindex;
 639       const struct powerpc_operand *operand;
 640       int need_comma;
 641       int need_paren;
 642       int skip_optional;
 643
 644       if (opcode->operands[0] != 0)
 645         (*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
 646       else
 647         (*info->fprintf_func) (info->stream, "%s", opcode->name);
 648
 649       if (insn_is_short)
 650         /* The operands will be fetched out of the 16-bit instruction.  */
 651         insn >>= 16;
 652
 653       /* Now extract and print the operands.  */
 654       need_comma = 0;
 655       need_paren = 0;
 656       skip_optional = -1;
 657       for (opindex = opcode->operands; *opindex != 0; opindex++)
 658         {
 659           long value;
 660
 661           operand = powerpc_operands + *opindex;
 662
 663           /* Operands that are marked FAKE are simply ignored.  We
 664              already made sure that the extract function considered
 665              the instruction to be valid.  */
 666           if ((operand->flags & PPC_OPERAND_FAKE) != 0)
 667             continue;
 668
 669           /* If all of the optional operands have the value zero,
 670              then don't print any of them.  */
 671           if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
 672             {
 673               if (skip_optional < 0)
 674                 skip_optional = skip_optional_operands (opindex, insn,
 675                                                         dialect);
 676               if (skip_optional)
 677                 continue;
 678             }
 679
 680           value = operand_value_powerpc (operand, insn, dialect);
 681
 682           if (need_comma)
 683             {
 684               (*info->fprintf_func) (info->stream, ",");
 685               need_comma = 0;
 686             }
 687
 688           /* Print the operand as directed by the flags.  */
 689           if ((operand->flags & PPC_OPERAND_GPR) != 0
 690               || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
 691             (*info->fprintf_func) (info->stream, "r%ld", value);
 692           else if ((operand->flags & PPC_OPERAND_FPR) != 0)
 693             (*info->fprintf_func) (info->stream, "f%ld", value);
 694           else if ((operand->flags & PPC_OPERAND_VR) != 0)
 695             (*info->fprintf_func) (info->stream, "v%ld", value);
 696           else if ((operand->flags & PPC_OPERAND_VSR) != 0)
 697             (*info->fprintf_func) (info->stream, "vs%ld", value);
 698           else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
 699             (*info->print_address_func) (memaddr + value, info);
 700           else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
 701             (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
 702           else if ((operand->flags & PPC_OPERAND_FSL) != 0)
 703             (*info->fprintf_func) (info->stream, "fsl%ld", value);
 704           else if ((operand->flags & PPC_OPERAND_FCR) != 0)
 705             (*info->fprintf_func) (info->stream, "fcr%ld", value);
 706           else if ((operand->flags & PPC_OPERAND_UDI) != 0)
 707             (*info->fprintf_func) (info->stream, "%ld", value);
 708           else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
 709                    && (((dialect & PPC_OPCODE_PPC) != 0)
 710                        || ((dialect & PPC_OPCODE_VLE) != 0)))
 711             (*info->fprintf_func) (info->stream, "cr%ld", value);
 712           else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
 713                    && (((dialect & PPC_OPCODE_PPC) != 0)
 714                        || ((dialect & PPC_OPCODE_VLE) != 0)))
 715             {
 716               static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
 717               int cr;
 718               int cc;
 719
 720               cr = value >> 2;
 721               if (cr != 0)
 722                 (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
 723               cc = value & 3;
 724               (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
 725             }
 726           else
 727             (*info->fprintf_func) (info->stream, "%d", (int) value);
 728
 729           if (need_paren)
 730             {
 731               (*info->fprintf_func) (info->stream, ")");
 732               need_paren = 0;
 733             }
 734
 735           if ((operand->flags & PPC_OPERAND_PARENS) == 0)
 736             need_comma = 1;
 737           else
 738             {
 739               (*info->fprintf_func) (info->stream, "(");
 740               need_paren = 1;
 741             }
 742         }
 743
 744       /* We have found and printed an instruction.
 745          If it was a short VLE instruction we have more to do.  */
 746       if (insn_is_short)
 747         {
 748           memaddr += 2;
 749           return 2;
 750         }
 751       else
 752         /* Otherwise, return.  */
 753         return 4;
 754     }
 755
 756   /* We could not find a match.  */
 757   (*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
 758
 759   return 4;
 760 }
 761
 762 void
 763 print_ppc_disassembler_options (FILE *stream)
 764 {
 765   unsigned int i, col;
 766
 767   fprintf (stream, _("\n\
 768 The following PPC specific disassembler options are supported for use with\n\
 769 the -M switch:\n"));
 770
 771   for (col = 0, i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
 772     {
 773       col += fprintf (stream, " %s,", ppc_opts[i].opt);
 774       if (col > 66)
 775         {
 776           fprintf (stream, "\n");
 777           col = 0;
 778         }
 779     }
 780   fprintf (stream, " 32, 64\n");
 781 }