opcodes/ppc-dis.c

   1 /* ppc-dis.c -- Disassemble PowerPC instructions
   2    Copyright (C) 1994-2018 Free Software Foundation, Inc.
   3    Written by Ian Lance Taylor, Cygnus Support
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING.  If not, write to the
  19    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  20    MA 02110-1301, USA.  */
  21
  22 #include "sysdep.h"
  23 #include <stdio.h>
  24 #include "disassemble.h"
  25 #include "elf-bfd.h"
  26 #include "elf/ppc.h"
  27 #include "opintl.h"
  28 #include "opcode/ppc.h"
  29 #include "libiberty.h"
  30
  31 /* This file provides several disassembler functions, all of which use
  32    the disassembler interface defined in dis-asm.h.  Several functions
  33    are provided because this file handles disassembly for the PowerPC
  34    in both big and little endian mode and also for the POWER (RS/6000)
  35    chip.  */
  36 static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
  37                                ppc_cpu_t);
  38
  39 struct dis_private
  40 {
  41   /* Stash the result of parsing disassembler_options here.  */
  42   ppc_cpu_t dialect;
  43 } private;
  44
  45 #define POWERPC_DIALECT(INFO) \
  46   (((struct dis_private *) ((INFO)->private_data))->dialect)
  47
  48 struct ppc_mopt {
  49   /* Option string, without -m or -M prefix.  */
  50   const char *opt;
  51   /* CPU option flags.  */
  52   ppc_cpu_t cpu;
  53   /* Flags that should stay on, even when combined with another cpu
  54      option.  This should only be used for generic options like
  55      "-many" or "-maltivec" where it is reasonable to add some
  56      capability to another cpu selection.  The added flags are sticky
  57      so that, for example, "-many -me500" and "-me500 -many" result in
  58      the same assembler or disassembler behaviour.  Do not use
  59      "sticky" for specific cpus, as this will prevent that cpu's flags
  60      from overriding the defaults set in powerpc_init_dialect or a
  61      prior -m option.  */
  62   ppc_cpu_t sticky;
  63 };
  64
  65 struct ppc_mopt ppc_opts[] = {
  66   { "403",     PPC_OPCODE_PPC | PPC_OPCODE_403,
  67     0 },
  68   { "405",     PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405,
  69     0 },
  70   { "440",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
  71                 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
  72     0 },
  73   { "464",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
  74                 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
  75     0 },
  76   { "476",     (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_476
  77                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
  78     0 },
  79   { "601",     PPC_OPCODE_PPC | PPC_OPCODE_601,
  80     0 },
  81   { "603",     PPC_OPCODE_PPC,
  82     0 },
  83   { "604",     PPC_OPCODE_PPC,
  84     0 },
  85   { "620",     PPC_OPCODE_PPC | PPC_OPCODE_64,
  86     0 },
  87   { "7400",    PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
  88     0 },
  89   { "7410",    PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
  90     0 },
  91   { "7450",    PPC_OPCODE_PPC | PPC_OPCODE_7450 | PPC_OPCODE_ALTIVEC,
  92     0 },
  93   { "7455",    PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
  94     0 },
  95   { "750cl",   PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
  96     , 0 },
  97   { "gekko",   PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
  98     , 0 },
  99   { "broadway", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
 100     , 0 },
 101   { "821",     PPC_OPCODE_PPC | PPC_OPCODE_860,
 102     0 },
 103   { "850",     PPC_OPCODE_PPC | PPC_OPCODE_860,
 104     0 },
 105   { "860",     PPC_OPCODE_PPC | PPC_OPCODE_860,
 106     0 },
 107   { "a2",      (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
 108                 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
 109                 | PPC_OPCODE_A2),
 110     0 },
 111   { "altivec", PPC_OPCODE_PPC,
 112     PPC_OPCODE_ALTIVEC },
 113   { "any",     PPC_OPCODE_PPC,
 114     PPC_OPCODE_ANY },
 115   { "booke",   PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
 116     0 },
 117   { "booke32", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
 118     0 },
 119   { "cell",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 120                 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
 121     0 },
 122   { "com",     PPC_OPCODE_COMMON,
 123     0 },
 124   { "e200z4",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
 125                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 126                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 127                 | PPC_OPCODE_E500 | PPC_OPCODE_VLE | PPC_OPCODE_E200Z4
 128                 | PPC_OPCODE_EFS2 | PPC_OPCODE_LSP),
 129     0 },
 130   { "e300",    PPC_OPCODE_PPC | PPC_OPCODE_E300,
 131     0 },
 132   { "e500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
 133                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 134                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 135                 | PPC_OPCODE_E500),
 136     0 },
 137   { "e500mc",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 138                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 139                 | PPC_OPCODE_E500MC),
 140     0 },
 141   { "e500mc64",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 142                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 143                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
 144                 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 145     0 },
 146   { "e5500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 147                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 148                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 149                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 150     0 },
 151   { "e6500",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 152                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 153                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
 154                 | PPC_OPCODE_E6500 | PPC_OPCODE_TMR | PPC_OPCODE_POWER4
 155                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 156     0 },
 157   { "e500x2",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
 158                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 159                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 160                 | PPC_OPCODE_E500),
 161     0 },
 162   { "efs",     PPC_OPCODE_PPC | PPC_OPCODE_EFS,
 163     0 },
 164   { "efs2",    PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2,
 165     0 },
 166   { "power4",  PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
 167     0 },
 168   { "power5",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 169                 | PPC_OPCODE_POWER5),
 170     0 },
 171   { "power6",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 172                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
 173     0 },
 174   { "power7",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 175                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 176                 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 177     0 },
 178   { "power8",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 179                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 180                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8
 181                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 182     0 },
 183   { "power9",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 184                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 185                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 186                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 187     0 },
 188   { "ppc",     PPC_OPCODE_PPC,
 189     0 },
 190   { "ppc32",   PPC_OPCODE_PPC,
 191     0 },
 192   { "32",      PPC_OPCODE_PPC,
 193     0 },
 194   { "ppc64",   PPC_OPCODE_PPC | PPC_OPCODE_64,
 195     0 },
 196   { "64",      PPC_OPCODE_PPC | PPC_OPCODE_64,
 197     0 },
 198   { "ppc64bridge", PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE,
 199     0 },
 200   { "ppcps",   PPC_OPCODE_PPC | PPC_OPCODE_PPCPS,
 201     0 },
 202   { "pwr",     PPC_OPCODE_POWER,
 203     0 },
 204   { "pwr2",    PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
 205     0 },
 206   { "pwr4",    PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
 207     0 },
 208   { "pwr5",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 209                 | PPC_OPCODE_POWER5),
 210     0 },
 211   { "pwr5x",   (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 212                 | PPC_OPCODE_POWER5),
 213     0 },
 214   { "pwr6",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 215                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
 216     0 },
 217   { "pwr7",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 218                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 219                 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 220     0 },
 221   { "pwr8",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 222                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 223                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8
 224                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 225     0 },
 226   { "pwr9",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 227                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 228                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 229                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 230     0 },
 231   { "pwrx",    PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
 232     0 },
 233   { "raw",     PPC_OPCODE_PPC,
 234     PPC_OPCODE_RAW },
 235   { "spe",     PPC_OPCODE_PPC | PPC_OPCODE_EFS,
 236     PPC_OPCODE_SPE },
 237   { "spe2",     PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE,
 238     PPC_OPCODE_SPE2 },
 239   { "titan",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
 240                 | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
 241     0 },
 242   { "vle",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
 243                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 244                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 245                 | PPC_OPCODE_LSP | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE2),
 246     PPC_OPCODE_VLE },
 247   { "vsx",     PPC_OPCODE_PPC,
 248     PPC_OPCODE_VSX },
 249 };
 250
 251 /* Switch between Booke and VLE dialects for interlinked dumps.  */
 252 static ppc_cpu_t
 253 get_powerpc_dialect (struct disassemble_info *info)
 254 {
 255   ppc_cpu_t dialect = 0;
 256
 257   dialect = POWERPC_DIALECT (info);
 258
 259   /* Disassemble according to the section headers flags for VLE-mode.  */
 260   if (dialect & PPC_OPCODE_VLE
 261       && info->section != NULL && info->section->owner != NULL
 262       && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
 263       && elf_object_id (info->section->owner) == PPC32_ELF_DATA
 264       && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
 265     return dialect;
 266   else
 267     return dialect & ~ PPC_OPCODE_VLE;
 268 }
 269
 270 /* Handle -m and -M options that set cpu type, and .machine arg.  */
 271
 272 ppc_cpu_t
 273 ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg)
 274 {
 275   unsigned int i;
 276
 277   for (i = 0; i < ARRAY_SIZE (ppc_opts); i++)
 278     if (disassembler_options_cmp (ppc_opts[i].opt, arg) == 0)
 279       {
 280         if (ppc_opts[i].sticky)
 281           {
 282             *sticky |= ppc_opts[i].sticky;
 283             if ((ppc_cpu & ~*sticky) != 0)
 284               break;
 285           }
 286         ppc_cpu = ppc_opts[i].cpu;
 287         break;
 288       }
 289   if (i >= ARRAY_SIZE (ppc_opts))
 290     return 0;
 291
 292   ppc_cpu |= *sticky;
 293   return ppc_cpu;
 294 }
 295
 296 /* Determine which set of machines to disassemble for.  */
 297
 298 static void
 299 powerpc_init_dialect (struct disassemble_info *info)
 300 {
 301   ppc_cpu_t dialect = 0;
 302   ppc_cpu_t sticky = 0;
 303   struct dis_private *priv = calloc (sizeof (*priv), 1);
 304
 305   if (priv == NULL)
 306     priv = &private;
 307
 308   switch (info->mach)
 309     {
 310     case bfd_mach_ppc_403:
 311     case bfd_mach_ppc_403gc:
 312       dialect = ppc_parse_cpu (dialect, &sticky, "403");
 313       break;
 314     case bfd_mach_ppc_405:
 315       dialect = ppc_parse_cpu (dialect, &sticky, "405");
 316       break;
 317     case bfd_mach_ppc_601:
 318       dialect = ppc_parse_cpu (dialect, &sticky, "601");
 319       break;
 320     case bfd_mach_ppc_750:
 321       dialect = ppc_parse_cpu (dialect, &sticky, "750cl");
 322       break;
 323     case bfd_mach_ppc_a35:
 324     case bfd_mach_ppc_rs64ii:
 325     case bfd_mach_ppc_rs64iii:
 326       dialect = ppc_parse_cpu (dialect, &sticky, "pwr2") | PPC_OPCODE_64;
 327       break;
 328     case bfd_mach_ppc_e500:
 329       dialect = ppc_parse_cpu (dialect, &sticky, "e500");
 330       break;
 331     case bfd_mach_ppc_e500mc:
 332       dialect = ppc_parse_cpu (dialect, &sticky, "e500mc");
 333       break;
 334     case bfd_mach_ppc_e500mc64:
 335       dialect = ppc_parse_cpu (dialect, &sticky, "e500mc64");
 336       break;
 337     case bfd_mach_ppc_e5500:
 338       dialect = ppc_parse_cpu (dialect, &sticky, "e5500");
 339       break;
 340     case bfd_mach_ppc_e6500:
 341       dialect = ppc_parse_cpu (dialect, &sticky, "e6500");
 342       break;
 343     case bfd_mach_ppc_titan:
 344       dialect = ppc_parse_cpu (dialect, &sticky, "titan");
 345       break;
 346     case bfd_mach_ppc_vle:
 347       dialect = ppc_parse_cpu (dialect, &sticky, "vle");
 348       break;
 349     default:
 350       if (info->arch == bfd_arch_powerpc)
 351         dialect = ppc_parse_cpu (dialect, &sticky, "power9") | PPC_OPCODE_ANY;
 352       else
 353         dialect = ppc_parse_cpu (dialect, &sticky, "pwr");
 354       break;
 355     }
 356
 357   const char *opt;
 358   FOR_EACH_DISASSEMBLER_OPTION (opt, info->disassembler_options)
 359     {
 360       ppc_cpu_t new_cpu = 0;
 361
 362       if (disassembler_options_cmp (opt, "32") == 0)
 363         dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
 364       else if (disassembler_options_cmp (opt, "64") == 0)
 365         dialect |= PPC_OPCODE_64;
 366       else if ((new_cpu = ppc_parse_cpu (dialect, &sticky, opt)) != 0)
 367         dialect = new_cpu;
 368       else
 369         /* xgettext: c-format */
 370         opcodes_error_handler (_("warning: ignoring unknown -M%s option"), opt);
 371     }
 372
 373   info->private_data = priv;
 374   POWERPC_DIALECT(info) = dialect;
 375 }
 376
 377 #define PPC_OPCD_SEGS (1 + PPC_OP (-1))
 378 static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS + 1];
 379 #define VLE_OPCD_SEGS (1 + VLE_OP_TO_SEG (VLE_OP (-1, 0xffff)))
 380 static unsigned short vle_opcd_indices[VLE_OPCD_SEGS + 1];
 381 #define SPE2_OPCD_SEGS (1 + SPE2_XOP_TO_SEG (SPE2_XOP (-1)))
 382 static unsigned short spe2_opcd_indices[SPE2_OPCD_SEGS + 1];
 383
 384 /* Calculate opcode table indices to speed up disassembly,
 385    and init dialect.  */
 386
 387 void
 388 disassemble_init_powerpc (struct disassemble_info *info)
 389 {
 390   if (powerpc_opcd_indices[PPC_OPCD_SEGS] == 0)
 391     {
 392       unsigned seg, idx, op;
 393
 394       /* PPC opcodes */
 395       for (seg = 0, idx = 0; seg <= PPC_OPCD_SEGS; seg++)
 396         {
 397           powerpc_opcd_indices[seg] = idx;
 398           for (; idx < powerpc_num_opcodes; idx++)
 399             if (seg < PPC_OP (powerpc_opcodes[idx].opcode))
 400               break;
 401         }
 402
 403       /* VLE opcodes */
 404       for (seg = 0, idx = 0; seg <= VLE_OPCD_SEGS; seg++)
 405         {
 406           vle_opcd_indices[seg] = idx;
 407           for (; idx < vle_num_opcodes; idx++)
 408             {
 409               op = VLE_OP (vle_opcodes[idx].opcode, vle_opcodes[idx].mask);
 410               if (seg < VLE_OP_TO_SEG (op))
 411                 break;
 412             }
 413         }
 414
 415       /* SPE2 opcodes */
 416       for (seg = 0, idx = 0; seg <= SPE2_OPCD_SEGS; seg++)
 417         {
 418           spe2_opcd_indices[seg] = idx;
 419           for (; idx < spe2_num_opcodes; idx++)
 420             {
 421               op = SPE2_XOP (spe2_opcodes[idx].opcode);
 422               if (seg < SPE2_XOP_TO_SEG (op))
 423                 break;
 424             }
 425         }
 426     }
 427
 428   powerpc_init_dialect (info);
 429 }
 430
 431 /* Print a big endian PowerPC instruction.  */
 432
 433 int
 434 print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
 435 {
 436   return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info));
 437 }
 438
 439 /* Print a little endian PowerPC instruction.  */
 440
 441 int
 442 print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
 443 {
 444   return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info));
 445 }
 446
 447 /* Extract the operand value from the PowerPC or POWER instruction.  */
 448
 449 static int64_t
 450 operand_value_powerpc (const struct powerpc_operand *operand,
 451                        uint64_t insn, ppc_cpu_t dialect)
 452 {
 453   int64_t value;
 454   int invalid;
 455   /* Extract the value from the instruction.  */
 456   if (operand->extract)
 457     value = (*operand->extract) (insn, dialect, &invalid);
 458   else
 459     {
 460       if (operand->shift >= 0)
 461         value = (insn >> operand->shift) & operand->bitm;
 462       else
 463         value = (insn << -operand->shift) & operand->bitm;
 464       if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
 465         {
 466           /* BITM is always some number of zeros followed by some
 467              number of ones, followed by some number of zeros.  */
 468           uint64_t top = operand->bitm;
 469           /* top & -top gives the rightmost 1 bit, so this
 470              fills in any trailing zeros.  */
 471           top |= (top & -top) - 1;
 472           top &= ~(top >> 1);
 473           value = (value ^ top) - top;
 474         }
 475     }
 476
 477   return value;
 478 }
 479
 480 /* Determine whether the optional operand(s) should be printed.  */
 481
 482 static int
 483 skip_optional_operands (const unsigned char *opindex,
 484                         uint64_t insn, ppc_cpu_t dialect)
 485 {
 486   const struct powerpc_operand *operand;
 487
 488   for (; *opindex != 0; opindex++)
 489     {
 490       operand = &powerpc_operands[*opindex];
 491       if ((operand->flags & PPC_OPERAND_NEXT) != 0
 492           || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
 493               && operand_value_powerpc (operand, insn, dialect) !=
 494                  ppc_optional_operand_value (operand)))
 495         return 0;
 496     }
 497
 498   return 1;
 499 }
 500
 501 /* Find a match for INSN in the opcode table, given machine DIALECT.  */
 502
 503 static const struct powerpc_opcode *
 504 lookup_powerpc (uint64_t insn, ppc_cpu_t dialect)
 505 {
 506   const struct powerpc_opcode *opcode, *opcode_end, *last;
 507   unsigned long op;
 508
 509   /* Get the major opcode of the instruction.  */
 510   op = PPC_OP (insn);
 511
 512   /* Find the first match in the opcode table for this major opcode.  */
 513   opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1];
 514   last = NULL;
 515   for (opcode = powerpc_opcodes + powerpc_opcd_indices[op];
 516        opcode < opcode_end;
 517        ++opcode)
 518     {
 519       const unsigned char *opindex;
 520       const struct powerpc_operand *operand;
 521       int invalid;
 522
 523       if ((insn & opcode->mask) != opcode->opcode
 524           || ((dialect & PPC_OPCODE_ANY) == 0
 525               && ((opcode->flags & dialect) == 0
 526                   || (opcode->deprecated & dialect) != 0)))
 527         continue;
 528
 529       /* Check validity of operands.  */
 530       invalid = 0;
 531       for (opindex = opcode->operands; *opindex != 0; opindex++)
 532         {
 533           operand = powerpc_operands + *opindex;
 534           if (operand->extract)
 535             (*operand->extract) (insn, dialect, &invalid);
 536         }
 537       if (invalid)
 538         continue;
 539
 540       if ((dialect & PPC_OPCODE_RAW) == 0)
 541         return opcode;
 542
 543       /* The raw machine insn is one that is not a specialization.  */
 544       if (last == NULL
 545           || (last->mask & ~opcode->mask) != 0)
 546         last = opcode;
 547     }
 548
 549   return last;
 550 }
 551
 552 /* Find a match for INSN in the VLE opcode table.  */
 553
 554 static const struct powerpc_opcode *
 555 lookup_vle (uint64_t insn)
 556 {
 557   const struct powerpc_opcode *opcode;
 558   const struct powerpc_opcode *opcode_end;
 559   unsigned op, seg;
 560
 561   op = PPC_OP (insn);
 562   if (op >= 0x20 && op <= 0x37)
 563     {
 564       /* This insn has a 4-bit opcode.  */
 565       op &= 0x3c;
 566     }
 567   seg = VLE_OP_TO_SEG (op);
 568
 569   /* Find the first match in the opcode table for this major opcode.  */
 570   opcode_end = vle_opcodes + vle_opcd_indices[seg + 1];
 571   for (opcode = vle_opcodes + vle_opcd_indices[seg];
 572        opcode < opcode_end;
 573        ++opcode)
 574     {
 575       uint64_t table_opcd = opcode->opcode;
 576       uint64_t table_mask = opcode->mask;
 577       bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
 578       uint64_t insn2;
 579       const unsigned char *opindex;
 580       const struct powerpc_operand *operand;
 581       int invalid;
 582
 583       insn2 = insn;
 584       if (table_op_is_short)
 585         insn2 >>= 16;
 586       if ((insn2 & table_mask) != table_opcd)
 587         continue;
 588
 589       /* Check validity of operands.  */
 590       invalid = 0;
 591       for (opindex = opcode->operands; *opindex != 0; ++opindex)
 592         {
 593           operand = powerpc_operands + *opindex;
 594           if (operand->extract)
 595             (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
 596         }
 597       if (invalid)
 598         continue;
 599
 600       return opcode;
 601     }
 602
 603   return NULL;
 604 }
 605
 606 /* Find a match for INSN in the SPE2 opcode table.  */
 607
 608 static const struct powerpc_opcode *
 609 lookup_spe2 (uint64_t insn)
 610 {
 611   const struct powerpc_opcode *opcode, *opcode_end;
 612   unsigned op, xop, seg;
 613
 614   op = PPC_OP (insn);
 615   if (op != 0x4)
 616     {
 617       /* This is not SPE2 insn.
 618        * All SPE2 instructions have OP=4 and differs by XOP  */
 619       return NULL;
 620     }
 621   xop = SPE2_XOP (insn);
 622   seg = SPE2_XOP_TO_SEG (xop);
 623
 624   /* Find the first match in the opcode table for this major opcode.  */
 625   opcode_end = spe2_opcodes + spe2_opcd_indices[seg + 1];
 626   for (opcode = spe2_opcodes + spe2_opcd_indices[seg];
 627        opcode < opcode_end;
 628        ++opcode)
 629     {
 630       uint64_t table_opcd = opcode->opcode;
 631       uint64_t table_mask = opcode->mask;
 632       uint64_t insn2;
 633       const unsigned char *opindex;
 634       const struct powerpc_operand *operand;
 635       int invalid;
 636
 637       insn2 = insn;
 638       if ((insn2 & table_mask) != table_opcd)
 639         continue;
 640
 641       /* Check validity of operands.  */
 642       invalid = 0;
 643       for (opindex = opcode->operands; *opindex != 0; ++opindex)
 644         {
 645           operand = powerpc_operands + *opindex;
 646           if (operand->extract)
 647             (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
 648         }
 649       if (invalid)
 650         continue;
 651
 652       return opcode;
 653     }
 654
 655   return NULL;
 656 }
 657
 658 /* Print a PowerPC or POWER instruction.  */
 659
 660 static int
 661 print_insn_powerpc (bfd_vma memaddr,
 662                     struct disassemble_info *info,
 663                     int bigendian,
 664                     ppc_cpu_t dialect)
 665 {
 666   bfd_byte buffer[4];
 667   int status;
 668   uint64_t insn;
 669   const struct powerpc_opcode *opcode;
 670   int insn_length = 4;  /* Assume we have a normal 4-byte instruction.  */
 671
 672   status = (*info->read_memory_func) (memaddr, buffer, 4, info);
 673
 674   /* The final instruction may be a 2-byte VLE insn.  */
 675   if (status != 0 && (dialect & PPC_OPCODE_VLE) != 0)
 676     {
 677       /* Clear buffer so unused bytes will not have garbage in them.  */
 678       buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0;
 679       status = (*info->read_memory_func) (memaddr, buffer, 2, info);
 680     }
 681
 682   if (status != 0)
 683     {
 684       (*info->memory_error_func) (status, memaddr, info);
 685       return -1;
 686     }
 687
 688   if (bigendian)
 689     insn = bfd_getb32 (buffer);
 690   else
 691     insn = bfd_getl32 (buffer);
 692
 693   /* Get the major opcode of the insn.  */
 694   opcode = NULL;
 695   if ((dialect & PPC_OPCODE_VLE) != 0)
 696     {
 697       opcode = lookup_vle (insn);
 698       if (opcode != NULL && PPC_OP_SE_VLE (opcode->mask))
 699         {
 700           /* The operands will be fetched out of the 16-bit instruction.  */
 701           insn >>= 16;
 702           insn_length = 2;
 703         }
 704     }
 705   if (opcode == NULL && (dialect & PPC_OPCODE_SPE2) != 0)
 706     opcode = lookup_spe2 (insn);
 707   if (opcode == NULL)
 708     opcode = lookup_powerpc (insn, dialect & ~PPC_OPCODE_ANY);
 709   if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
 710     opcode = lookup_powerpc (insn, dialect);
 711
 712   if (opcode != NULL)
 713     {
 714       const unsigned char *opindex;
 715       const struct powerpc_operand *operand;
 716       int need_comma;
 717       int need_paren;
 718       int skip_optional;
 719
 720       if (opcode->operands[0] != 0)
 721         (*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
 722       else
 723         (*info->fprintf_func) (info->stream, "%s", opcode->name);
 724
 725       /* Now extract and print the operands.  */
 726       need_comma = 0;
 727       need_paren = 0;
 728       skip_optional = -1;
 729       for (opindex = opcode->operands; *opindex != 0; opindex++)
 730         {
 731           int64_t value;
 732
 733           operand = powerpc_operands + *opindex;
 734
 735           /* If all of the optional operands have the value zero,
 736              then don't print any of them.  */
 737           if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
 738             {
 739               if (skip_optional < 0)
 740                 skip_optional = skip_optional_operands (opindex, insn,
 741                                                         dialect);
 742               if (skip_optional)
 743                 continue;
 744             }
 745
 746           value = operand_value_powerpc (operand, insn, dialect);
 747
 748           if (need_comma)
 749             {
 750               (*info->fprintf_func) (info->stream, ",");
 751               need_comma = 0;
 752             }
 753
 754           /* Print the operand as directed by the flags.  */
 755           if ((operand->flags & PPC_OPERAND_GPR) != 0
 756               || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
 757             (*info->fprintf_func) (info->stream, "r%" PPC_INT_FMT "d", value);
 758           else if ((operand->flags & PPC_OPERAND_FPR) != 0)
 759             (*info->fprintf_func) (info->stream, "f%" PPC_INT_FMT "d", value);
 760           else if ((operand->flags & PPC_OPERAND_VR) != 0)
 761             (*info->fprintf_func) (info->stream, "v%" PPC_INT_FMT "d", value);
 762           else if ((operand->flags & PPC_OPERAND_VSR) != 0)
 763             (*info->fprintf_func) (info->stream, "vs%" PPC_INT_FMT "d", value);
 764           else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
 765             (*info->print_address_func) (memaddr + value, info);
 766           else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
 767             (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
 768           else if ((operand->flags & PPC_OPERAND_FSL) != 0)
 769             (*info->fprintf_func) (info->stream, "fsl%" PPC_INT_FMT "d", value);
 770           else if ((operand->flags & PPC_OPERAND_FCR) != 0)
 771             (*info->fprintf_func) (info->stream, "fcr%" PPC_INT_FMT "d", value);
 772           else if ((operand->flags & PPC_OPERAND_UDI) != 0)
 773             (*info->fprintf_func) (info->stream, "%" PPC_INT_FMT "d", value);
 774           else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
 775                    && (((dialect & PPC_OPCODE_PPC) != 0)
 776                        || ((dialect & PPC_OPCODE_VLE) != 0)))
 777             (*info->fprintf_func) (info->stream, "cr%" PPC_INT_FMT "d", value);
 778           else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
 779                    && (((dialect & PPC_OPCODE_PPC) != 0)
 780                        || ((dialect & PPC_OPCODE_VLE) != 0)))
 781             {
 782               static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
 783               int cr;
 784               int cc;
 785
 786               cr = value >> 2;
 787               if (cr != 0)
 788                 (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
 789               cc = value & 3;
 790               (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
 791             }
 792           else
 793             (*info->fprintf_func) (info->stream, "%" PPC_INT_FMT "d", value);
 794
 795           if (need_paren)
 796             {
 797               (*info->fprintf_func) (info->stream, ")");
 798               need_paren = 0;
 799             }
 800
 801           if ((operand->flags & PPC_OPERAND_PARENS) == 0)
 802             need_comma = 1;
 803           else
 804             {
 805               (*info->fprintf_func) (info->stream, "(");
 806               need_paren = 1;
 807             }
 808         }
 809
 810       /* We have found and printed an instruction.  */
 811       return insn_length;
 812     }
 813
 814   /* We could not find a match.  */
 815   (*info->fprintf_func) (info->stream, ".long 0x%" PPC_INT_FMT "x", insn);
 816
 817   return 4;
 818 }
 819
 820 const disasm_options_and_args_t *
 821 disassembler_options_powerpc (void)
 822 {
 823   static disasm_options_and_args_t *opts_and_args;
 824
 825   if (opts_and_args == NULL)
 826     {
 827       size_t i, num_options = ARRAY_SIZE (ppc_opts);
 828       disasm_options_t *opts;
 829
 830       opts_and_args = XNEW (disasm_options_and_args_t);
 831       opts_and_args->args = NULL;
 832
 833       opts = &opts_and_args->options;
 834       opts->name = XNEWVEC (const char *, num_options + 1);
 835       opts->description = NULL;
 836       opts->arg = NULL;
 837       for (i = 0; i < num_options; i++)
 838         opts->name[i] = ppc_opts[i].opt;
 839       /* The array we return must be NULL terminated.  */
 840       opts->name[i] = NULL;
 841     }
 842
 843   return opts_and_args;
 844 }
 845
 846 void
 847 print_ppc_disassembler_options (FILE *stream)
 848 {
 849   unsigned int i, col;
 850
 851   fprintf (stream, _("\n\
 852 The following PPC specific disassembler options are supported for use with\n\
 853 the -M switch:\n"));
 854
 855   for (col = 0, i = 0; i < ARRAY_SIZE (ppc_opts); i++)
 856     {
 857       col += fprintf (stream, " %s,", ppc_opts[i].opt);
 858       if (col > 66)
 859         {
 860           fprintf (stream, "\n");
 861           col = 0;
 862         }
 863     }
 864   fprintf (stream, "\n");
 865 }