1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
3 2005, 2006, 2007 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
6 This file is part of GDB, GAS, and the GNU binutils.
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 2, or (at your option) any later version.
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
25 #include "opcode/ppc.h"
28 /* This file holds the PowerPC opcode table. The opcode table
29 includes almost all of the extended instruction mnemonics. This
30 permits the disassembler to use them, and simplifies the assembler
31 logic, at the cost of increasing the table size. The table is
32 strictly constant data, so the compiler should be able to put it in
35 This file also holds the operand table. All knowledge about
36 inserting operands into instructions and vice-versa is kept in this
39 /* Local insertion and extraction functions. */
41 static unsigned long insert_bat (unsigned long, long, int, const char **);
42 static long extract_bat (unsigned long, int, int *);
43 static unsigned long insert_bba (unsigned long, long, int, const char **);
44 static long extract_bba (unsigned long, int, int *);
45 static unsigned long insert_bd (unsigned long, long, int, const char **);
46 static long extract_bd (unsigned long, int, int *);
47 static unsigned long insert_bdm (unsigned long, long, int, const char **);
48 static long extract_bdm (unsigned long, int, int *);
49 static unsigned long insert_bdp (unsigned long, long, int, const char **);
50 static long extract_bdp (unsigned long, int, int *);
51 static unsigned long insert_bo (unsigned long, long, int, const char **);
52 static long extract_bo (unsigned long, int, int *);
53 static unsigned long insert_boe (unsigned long, long, int, const char **);
54 static long extract_boe (unsigned long, int, int *);
55 static unsigned long insert_dq (unsigned long, long, int, const char **);
56 static long extract_dq (unsigned long, int, int *);
57 static unsigned long insert_ds (unsigned long, long, int, const char **);
58 static long extract_ds (unsigned long, int, int *);
59 static unsigned long insert_de (unsigned long, long, int, const char **);
60 static long extract_de (unsigned long, int, int *);
61 static unsigned long insert_des (unsigned long, long, int, const char **);
62 static long extract_des (unsigned long, int, int *);
63 static unsigned long insert_fxm (unsigned long, long, int, const char **);
64 static long extract_fxm (unsigned long, int, int *);
65 static unsigned long insert_li (unsigned long, long, int, const char **);
66 static long extract_li (unsigned long, int, int *);
67 static unsigned long insert_mbe (unsigned long, long, int, const char **);
68 static long extract_mbe (unsigned long, int, int *);
69 static unsigned long insert_mb6 (unsigned long, long, int, const char **);
70 static long extract_mb6 (unsigned long, int, int *);
71 static unsigned long insert_nb (unsigned long, long, int, const char **);
72 static long extract_nb (unsigned long, int, int *);
73 static unsigned long insert_nsi (unsigned long, long, int, const char **);
74 static long extract_nsi (unsigned long, int, int *);
75 static unsigned long insert_ral (unsigned long, long, int, const char **);
76 static unsigned long insert_ram (unsigned long, long, int, const char **);
77 static unsigned long insert_raq (unsigned long, long, int, const char **);
78 static unsigned long insert_ras (unsigned long, long, int, const char **);
79 static unsigned long insert_rbs (unsigned long, long, int, const char **);
80 static long extract_rbs (unsigned long, int, int *);
81 static unsigned long insert_rsq (unsigned long, long, int, const char **);
82 static unsigned long insert_rtq (unsigned long, long, int, const char **);
83 static unsigned long insert_sh6 (unsigned long, long, int, const char **);
84 static long extract_sh6 (unsigned long, int, int *);
85 static unsigned long insert_spr (unsigned long, long, int, const char **);
86 static long extract_spr (unsigned long, int, int *);
87 static unsigned long insert_sprg (unsigned long, long, int, const char **);
88 static long extract_sprg (unsigned long, int, int *);
89 static unsigned long insert_tbr (unsigned long, long, int, const char **);
90 static long extract_tbr (unsigned long, int, int *);
91 static unsigned long insert_ev2 (unsigned long, long, int, const char **);
92 static long extract_ev2 (unsigned long, int, int *);
93 static unsigned long insert_ev4 (unsigned long, long, int, const char **);
94 static long extract_ev4 (unsigned long, int, int *);
95 static unsigned long insert_ev8 (unsigned long, long, int, const char **);
96 static long extract_ev8 (unsigned long, int, int *);
98 /* The operands table.
100 The fields are bits, shift, insert, extract, flags.
102 We used to put parens around the various additions, like the one
103 for BA just below. However, that caused trouble with feeble
104 compilers with a limit on depth of a parenthesized expression, like
105 (reportedly) the compiler in Microsoft Developer Studio 5. So we
106 omit the parens, since the macros are never used in a context where
107 the addition will be ambiguous. */
109 const struct powerpc_operand powerpc_operands
[] =
111 /* The zero index is used to indicate the end of the list of
114 { 0, 0, NULL
, NULL
, 0 },
116 /* The BA field in an XL form instruction. */
117 #define BA UNUSED + 1
118 #define BA_MASK (0x1f << 16)
119 { 5, 16, NULL
, NULL
, PPC_OPERAND_CR
},
121 /* The BA field in an XL form instruction when it must be the same
122 as the BT field in the same instruction. */
124 { 5, 16, insert_bat
, extract_bat
, PPC_OPERAND_FAKE
},
126 /* The BB field in an XL form instruction. */
128 #define BB_MASK (0x1f << 11)
129 { 5, 11, NULL
, NULL
, PPC_OPERAND_CR
},
131 /* The BB field in an XL form instruction when it must be the same
132 as the BA field in the same instruction. */
134 { 5, 11, insert_bba
, extract_bba
, PPC_OPERAND_FAKE
},
136 /* The BD field in a B form instruction. The lower two bits are
139 { 16, 0, insert_bd
, extract_bd
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
141 /* The BD field in a B form instruction when absolute addressing is
144 { 16, 0, insert_bd
, extract_bd
, PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
146 /* The BD field in a B form instruction when the - modifier is used.
147 This sets the y bit of the BO field appropriately. */
149 { 16, 0, insert_bdm
, extract_bdm
,
150 PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
152 /* The BD field in a B form instruction when the - modifier is used
153 and absolute address is used. */
155 { 16, 0, insert_bdm
, extract_bdm
,
156 PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
158 /* The BD field in a B form instruction when the + modifier is used.
159 This sets the y bit of the BO field appropriately. */
161 { 16, 0, insert_bdp
, extract_bdp
,
162 PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
164 /* The BD field in a B form instruction when the + modifier is used
165 and absolute addressing is used. */
167 { 16, 0, insert_bdp
, extract_bdp
,
168 PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
170 /* The BF field in an X or XL form instruction. */
172 { 3, 23, NULL
, NULL
, PPC_OPERAND_CR
},
174 /* An optional BF field. This is used for comparison instructions,
175 in which an omitted BF field is taken as zero. */
177 { 3, 23, NULL
, NULL
, PPC_OPERAND_CR
| PPC_OPERAND_OPTIONAL
},
179 /* The BFA field in an X or XL form instruction. */
181 { 3, 18, NULL
, NULL
, PPC_OPERAND_CR
},
183 /* The BI field in a B form or XL form instruction. */
185 #define BI_MASK (0x1f << 16)
186 { 5, 16, NULL
, NULL
, PPC_OPERAND_CR
},
188 /* The BO field in a B form instruction. Certain values are
191 #define BO_MASK (0x1f << 21)
192 { 5, 21, insert_bo
, extract_bo
, 0 },
194 /* The BO field in a B form instruction when the + or - modifier is
195 used. This is like the BO field, but it must be even. */
197 { 5, 21, insert_boe
, extract_boe
, 0 },
200 { 2, 11, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
202 /* The BT field in an X or XL form instruction. */
204 { 5, 21, NULL
, NULL
, PPC_OPERAND_CR
},
206 /* The condition register number portion of the BI field in a B form
207 or XL form instruction. This is used for the extended
208 conditional branch mnemonics, which set the lower two bits of the
209 BI field. This field is optional. */
211 { 3, 18, NULL
, NULL
, PPC_OPERAND_CR
| PPC_OPERAND_OPTIONAL
},
213 /* The CRB field in an X form instruction. */
215 { 5, 6, NULL
, NULL
, 0 },
217 /* The CRFD field in an X form instruction. */
219 { 3, 23, NULL
, NULL
, PPC_OPERAND_CR
},
221 /* The CRFS field in an X form instruction. */
222 #define CRFS CRFD + 1
223 { 3, 0, NULL
, NULL
, PPC_OPERAND_CR
},
225 /* The CT field in an X form instruction. */
227 { 5, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
229 /* The D field in a D form instruction. This is a displacement off
230 a register, and implies that the next operand is a register in
233 { 16, 0, NULL
, NULL
, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
235 /* The DE field in a DE form instruction. This is like D, but is 12
238 { 14, 0, insert_de
, extract_de
, PPC_OPERAND_PARENS
},
240 /* The DES field in a DES form instruction. This is like DS, but is 14
241 bits only (12 stored.) */
243 { 14, 0, insert_des
, extract_des
, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
245 /* The DQ field in a DQ form instruction. This is like D, but the
246 lower four bits are forced to zero. */
248 { 16, 0, insert_dq
, extract_dq
,
249 PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
| PPC_OPERAND_DQ
},
251 /* The DS field in a DS form instruction. This is like D, but the
252 lower two bits are forced to zero. */
254 { 16, 0, insert_ds
, extract_ds
,
255 PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
| PPC_OPERAND_DS
},
257 /* The E field in a wrteei instruction. */
259 { 1, 15, NULL
, NULL
, 0 },
261 /* The FL1 field in a POWER SC form instruction. */
263 { 4, 12, NULL
, NULL
, 0 },
265 /* The FL2 field in a POWER SC form instruction. */
267 { 3, 2, NULL
, NULL
, 0 },
269 /* The FLM field in an XFL form instruction. */
271 { 8, 17, NULL
, NULL
, 0 },
273 /* The FRA field in an X or A form instruction. */
275 #define FRA_MASK (0x1f << 16)
276 { 5, 16, NULL
, NULL
, PPC_OPERAND_FPR
},
278 /* The FRB field in an X or A form instruction. */
280 #define FRB_MASK (0x1f << 11)
281 { 5, 11, NULL
, NULL
, PPC_OPERAND_FPR
},
283 /* The FRC field in an A form instruction. */
285 #define FRC_MASK (0x1f << 6)
286 { 5, 6, NULL
, NULL
, PPC_OPERAND_FPR
},
288 /* The FRS field in an X form instruction or the FRT field in a D, X
289 or A form instruction. */
292 { 5, 21, NULL
, NULL
, PPC_OPERAND_FPR
},
294 /* The FXM field in an XFX instruction. */
296 #define FXM_MASK (0xff << 12)
297 { 8, 12, insert_fxm
, extract_fxm
, 0 },
299 /* Power4 version for mfcr. */
301 { 8, 12, insert_fxm
, extract_fxm
, PPC_OPERAND_OPTIONAL
},
303 /* The L field in a D or X form instruction. */
305 { 1, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
307 /* The LEV field in a POWER SVC form instruction. */
308 #define SVC_LEV L + 1
309 { 7, 5, NULL
, NULL
, 0 },
311 /* The LEV field in an SC form instruction. */
312 #define LEV SVC_LEV + 1
313 { 7, 5, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
315 /* The LI field in an I form instruction. The lower two bits are
318 { 26, 0, insert_li
, extract_li
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
320 /* The LI field in an I form instruction when used as an absolute
323 { 26, 0, insert_li
, extract_li
, PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
325 /* The LS field in an X (sync) form instruction. */
327 { 2, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
329 /* The MB field in an M form instruction. */
331 #define MB_MASK (0x1f << 6)
332 { 5, 6, NULL
, NULL
, 0 },
334 /* The ME field in an M form instruction. */
336 #define ME_MASK (0x1f << 1)
337 { 5, 1, NULL
, NULL
, 0 },
339 /* The MB and ME fields in an M form instruction expressed a single
340 operand which is a bitmask indicating which bits to select. This
341 is a two operand form using PPC_OPERAND_NEXT. See the
342 description in opcode/ppc.h for what this means. */
344 { 5, 6, NULL
, NULL
, PPC_OPERAND_OPTIONAL
| PPC_OPERAND_NEXT
},
345 { 32, 0, insert_mbe
, extract_mbe
, 0 },
347 /* The MB or ME field in an MD or MDS form instruction. The high
348 bit is wrapped to the low end. */
351 #define MB6_MASK (0x3f << 5)
352 { 6, 5, insert_mb6
, extract_mb6
, 0 },
354 /* The MO field in an mbar instruction. */
356 { 5, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
358 /* The NB field in an X form instruction. The value 32 is stored as
361 { 6, 11, insert_nb
, extract_nb
, 0 },
363 /* The NSI field in a D form instruction. This is the same as the
364 SI field, only negated. */
366 { 16, 0, insert_nsi
, extract_nsi
,
367 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
},
369 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
371 #define RA_MASK (0x1f << 16)
372 { 5, 16, NULL
, NULL
, PPC_OPERAND_GPR
},
374 /* As above, but 0 in the RA field means zero, not r0. */
376 { 5, 16, NULL
, NULL
, PPC_OPERAND_GPR_0
},
378 /* The RA field in the DQ form lq instruction, which has special
379 value restrictions. */
381 { 5, 16, insert_raq
, NULL
, PPC_OPERAND_GPR_0
},
383 /* The RA field in a D or X form instruction which is an updating
384 load, which means that the RA field may not be zero and may not
385 equal the RT field. */
387 { 5, 16, insert_ral
, NULL
, PPC_OPERAND_GPR_0
},
389 /* The RA field in an lmw instruction, which has special value
392 { 5, 16, insert_ram
, NULL
, PPC_OPERAND_GPR_0
},
394 /* The RA field in a D or X form instruction which is an updating
395 store or an updating floating point load, which means that the RA
396 field may not be zero. */
398 { 5, 16, insert_ras
, NULL
, PPC_OPERAND_GPR_0
},
400 /* The RA field of the tlbwe instruction, which is optional. */
401 #define RAOPT RAS + 1
402 { 5, 16, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
404 /* The RB field in an X, XO, M, or MDS form instruction. */
406 #define RB_MASK (0x1f << 11)
407 { 5, 11, NULL
, NULL
, PPC_OPERAND_GPR
},
409 /* The RB field in an X form instruction when it must be the same as
410 the RS field in the instruction. This is used for extended
411 mnemonics like mr. */
413 { 5, 1, insert_rbs
, extract_rbs
, PPC_OPERAND_FAKE
},
415 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
416 instruction or the RT field in a D, DS, X, XFX or XO form
420 #define RT_MASK (0x1f << 21)
421 { 5, 21, NULL
, NULL
, PPC_OPERAND_GPR
},
423 /* The RS field of the DS form stq instruction, which has special
424 value restrictions. */
426 { 5, 21, insert_rsq
, NULL
, PPC_OPERAND_GPR_0
},
428 /* The RT field of the DQ form lq instruction, which has special
429 value restrictions. */
431 { 5, 21, insert_rtq
, NULL
, PPC_OPERAND_GPR_0
},
433 /* The RS field of the tlbwe instruction, which is optional. */
436 { 5, 21, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
438 /* The SH field in an X or M form instruction. */
440 #define SH_MASK (0x1f << 11)
441 { 5, 11, NULL
, NULL
, 0 },
443 /* The SH field in an MD form instruction. This is split. */
445 #define SH6_MASK ((0x1f << 11) | (1 << 1))
446 { 6, 1, insert_sh6
, extract_sh6
, 0 },
448 /* The SH field of the tlbwe instruction, which is optional. */
450 { 5, 11,NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
452 /* The SI field in a D form instruction. */
454 { 16, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
},
456 /* The SI field in a D form instruction when we accept a wide range
457 of positive values. */
458 #define SISIGNOPT SI + 1
459 { 16, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
461 /* The SPR field in an XFX form instruction. This is flipped--the
462 lower 5 bits are stored in the upper 5 and vice- versa. */
463 #define SPR SISIGNOPT + 1
465 #define SPR_MASK (0x3ff << 11)
466 { 10, 11, insert_spr
, extract_spr
, 0 },
468 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
469 #define SPRBAT SPR + 1
470 #define SPRBAT_MASK (0x3 << 17)
471 { 2, 17, NULL
, NULL
, 0 },
473 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
474 #define SPRG SPRBAT + 1
475 { 5, 16, insert_sprg
, extract_sprg
, 0 },
477 /* The SR field in an X form instruction. */
479 { 4, 16, NULL
, NULL
, 0 },
481 /* The STRM field in an X AltiVec form instruction. */
483 #define STRM_MASK (0x3 << 21)
484 { 2, 21, NULL
, NULL
, 0 },
486 /* The SV field in a POWER SC form instruction. */
488 { 14, 2, NULL
, NULL
, 0 },
490 /* The TBR field in an XFX form instruction. This is like the SPR
491 field, but it is optional. */
493 { 10, 11, insert_tbr
, extract_tbr
, PPC_OPERAND_OPTIONAL
},
495 /* The TO field in a D or X form instruction. */
497 #define TO_MASK (0x1f << 21)
498 { 5, 21, NULL
, NULL
, 0 },
500 /* The U field in an X form instruction. */
502 { 4, 12, NULL
, NULL
, 0 },
504 /* The UI field in a D form instruction. */
506 { 16, 0, NULL
, NULL
, 0 },
508 /* The VA field in a VA, VX or VXR form instruction. */
510 #define VA_MASK (0x1f << 16)
511 { 5, 16, NULL
, NULL
, PPC_OPERAND_VR
},
513 /* The VB field in a VA, VX or VXR form instruction. */
515 #define VB_MASK (0x1f << 11)
516 { 5, 11, NULL
, NULL
, PPC_OPERAND_VR
},
518 /* The VC field in a VA form instruction. */
520 #define VC_MASK (0x1f << 6)
521 { 5, 6, NULL
, NULL
, PPC_OPERAND_VR
},
523 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
526 #define VD_MASK (0x1f << 21)
527 { 5, 21, NULL
, NULL
, PPC_OPERAND_VR
},
529 /* The SIMM field in a VX form instruction. */
531 { 5, 16, NULL
, NULL
, PPC_OPERAND_SIGNED
},
533 /* The UIMM field in a VX form instruction, and TE in Z form. */
534 #define UIMM SIMM + 1
536 { 5, 16, NULL
, NULL
, 0 },
538 /* The SHB field in a VA form instruction. */
540 { 4, 6, NULL
, NULL
, 0 },
542 /* The other UIMM field in a EVX form instruction. */
543 #define EVUIMM SHB + 1
544 { 5, 11, NULL
, NULL
, 0 },
546 /* The other UIMM field in a half word EVX form instruction. */
547 #define EVUIMM_2 EVUIMM + 1
548 { 32, 11, insert_ev2
, extract_ev2
, PPC_OPERAND_PARENS
},
550 /* The other UIMM field in a word EVX form instruction. */
551 #define EVUIMM_4 EVUIMM_2 + 1
552 { 32, 11, insert_ev4
, extract_ev4
, PPC_OPERAND_PARENS
},
554 /* The other UIMM field in a double EVX form instruction. */
555 #define EVUIMM_8 EVUIMM_4 + 1
556 { 32, 11, insert_ev8
, extract_ev8
, PPC_OPERAND_PARENS
},
559 #define WS EVUIMM_8 + 1
560 #define WS_MASK (0x7 << 11)
561 { 3, 11, NULL
, NULL
, 0 },
563 /* The L field in an mtmsrd or A form instruction. */
564 #define MTMSRD_L WS + 1
566 { 1, 16, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
569 { 2, 9, NULL
, NULL
, 0 },
572 { 1, 16, NULL
, NULL
, 0 },
575 { 2, 19, NULL
, NULL
, 0 },
578 { 1, 20, NULL
, NULL
, 0 },
580 /* SH field starting at bit position 16. */
582 /* The DCM and DGM fields in a Z form instruction. */
585 { 6, 10, NULL
, NULL
, 0 },
587 /* The L field in an X form with the RT field fixed instruction. */
588 #define XRT_L SH16 + 1
589 { 2, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
591 /* The EH field in larx instruction. */
593 { 1, 0, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
596 /* The functions used to insert and extract complicated operands. */
598 /* The BA field in an XL form instruction when it must be the same as
599 the BT field in the same instruction. This operand is marked FAKE.
600 The insertion function just copies the BT field into the BA field,
601 and the extraction function just checks that the fields are the
605 insert_bat (unsigned long insn
,
606 long value ATTRIBUTE_UNUSED
,
607 int dialect ATTRIBUTE_UNUSED
,
608 const char **errmsg ATTRIBUTE_UNUSED
)
610 return insn
| (((insn
>> 21) & 0x1f) << 16);
614 extract_bat (unsigned long insn
,
615 int dialect ATTRIBUTE_UNUSED
,
618 if (((insn
>> 21) & 0x1f) != ((insn
>> 16) & 0x1f))
623 /* The BB field in an XL form instruction when it must be the same as
624 the BA field in the same instruction. This operand is marked FAKE.
625 The insertion function just copies the BA field into the BB field,
626 and the extraction function just checks that the fields are the
630 insert_bba (unsigned long insn
,
631 long value ATTRIBUTE_UNUSED
,
632 int dialect ATTRIBUTE_UNUSED
,
633 const char **errmsg ATTRIBUTE_UNUSED
)
635 return insn
| (((insn
>> 16) & 0x1f) << 11);
639 extract_bba (unsigned long insn
,
640 int dialect ATTRIBUTE_UNUSED
,
643 if (((insn
>> 16) & 0x1f) != ((insn
>> 11) & 0x1f))
648 /* The BD field in a B form instruction. The lower two bits are
652 insert_bd (unsigned long insn
,
654 int dialect ATTRIBUTE_UNUSED
,
655 const char **errmsg ATTRIBUTE_UNUSED
)
657 return insn
| (value
& 0xfffc);
661 extract_bd (unsigned long insn
,
662 int dialect ATTRIBUTE_UNUSED
,
663 int *invalid ATTRIBUTE_UNUSED
)
665 return ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
668 /* The BD field in a B form instruction when the - modifier is used.
669 This modifier means that the branch is not expected to be taken.
670 For chips built to versions of the architecture prior to version 2
671 (ie. not Power4 compatible), we set the y bit of the BO field to 1
672 if the offset is negative. When extracting, we require that the y
673 bit be 1 and that the offset be positive, since if the y bit is 0
674 we just want to print the normal form of the instruction.
675 Power4 compatible targets use two bits, "a", and "t", instead of
676 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
677 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
678 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
679 for branch on CTR. We only handle the taken/not-taken hint here.
680 Note that we don't relax the conditions tested here when
681 disassembling with -Many because insns using extract_bdm and
682 extract_bdp always occur in pairs. One or the other will always
686 insert_bdm (unsigned long insn
,
689 const char **errmsg ATTRIBUTE_UNUSED
)
691 if ((dialect
& PPC_OPCODE_POWER4
) == 0)
693 if ((value
& 0x8000) != 0)
698 if ((insn
& (0x14 << 21)) == (0x04 << 21))
700 else if ((insn
& (0x14 << 21)) == (0x10 << 21))
703 return insn
| (value
& 0xfffc);
707 extract_bdm (unsigned long insn
,
711 if ((dialect
& PPC_OPCODE_POWER4
) == 0)
713 if (((insn
& (1 << 21)) == 0) != ((insn
& (1 << 15)) == 0))
718 if ((insn
& (0x17 << 21)) != (0x06 << 21)
719 && (insn
& (0x1d << 21)) != (0x18 << 21))
723 return ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
726 /* The BD field in a B form instruction when the + modifier is used.
727 This is like BDM, above, except that the branch is expected to be
731 insert_bdp (unsigned long insn
,
734 const char **errmsg ATTRIBUTE_UNUSED
)
736 if ((dialect
& PPC_OPCODE_POWER4
) == 0)
738 if ((value
& 0x8000) == 0)
743 if ((insn
& (0x14 << 21)) == (0x04 << 21))
745 else if ((insn
& (0x14 << 21)) == (0x10 << 21))
748 return insn
| (value
& 0xfffc);
752 extract_bdp (unsigned long insn
,
756 if ((dialect
& PPC_OPCODE_POWER4
) == 0)
758 if (((insn
& (1 << 21)) == 0) == ((insn
& (1 << 15)) == 0))
763 if ((insn
& (0x17 << 21)) != (0x07 << 21)
764 && (insn
& (0x1d << 21)) != (0x19 << 21))
768 return ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
771 /* Check for legal values of a BO field. */
774 valid_bo (long value
, int dialect
, int extract
)
776 if ((dialect
& PPC_OPCODE_POWER4
) == 0)
779 /* Certain encodings have bits that are required to be zero.
780 These are (z must be zero, y may be anything):
787 switch (value
& 0x14)
794 valid
= (value
& 0x2) == 0;
797 valid
= (value
& 0x8) == 0;
800 valid
= value
== 0x14;
803 /* When disassembling with -Many, accept power4 encodings too. */
805 || (dialect
& PPC_OPCODE_ANY
) == 0
810 /* Certain encodings have bits that are required to be zero.
811 These are (z must be zero, a & t may be anything):
822 if ((value
& 0x14) == 0)
823 return (value
& 0x1) == 0;
824 else if ((value
& 0x14) == 0x14)
825 return value
== 0x14;
830 /* The BO field in a B form instruction. Warn about attempts to set
831 the field to an illegal value. */
834 insert_bo (unsigned long insn
,
839 if (!valid_bo (value
, dialect
, 0))
840 *errmsg
= _("invalid conditional option");
841 return insn
| ((value
& 0x1f) << 21);
845 extract_bo (unsigned long insn
,
851 value
= (insn
>> 21) & 0x1f;
852 if (!valid_bo (value
, dialect
, 1))
857 /* The BO field in a B form instruction when the + or - modifier is
858 used. This is like the BO field, but it must be even. When
859 extracting it, we force it to be even. */
862 insert_boe (unsigned long insn
,
867 if (!valid_bo (value
, dialect
, 0))
868 *errmsg
= _("invalid conditional option");
869 else if ((value
& 1) != 0)
870 *errmsg
= _("attempt to set y bit when using + or - modifier");
872 return insn
| ((value
& 0x1f) << 21);
876 extract_boe (unsigned long insn
,
882 value
= (insn
>> 21) & 0x1f;
883 if (!valid_bo (value
, dialect
, 1))
888 /* The DQ field in a DQ form instruction. This is like D, but the
889 lower four bits are forced to zero. */
892 insert_dq (unsigned long insn
,
894 int dialect ATTRIBUTE_UNUSED
,
897 if ((value
& 0xf) != 0)
898 *errmsg
= _("offset not a multiple of 16");
899 return insn
| (value
& 0xfff0);
903 extract_dq (unsigned long insn
,
904 int dialect ATTRIBUTE_UNUSED
,
905 int *invalid ATTRIBUTE_UNUSED
)
907 return ((insn
& 0xfff0) ^ 0x8000) - 0x8000;
911 insert_ev2 (unsigned long insn
,
913 int dialect ATTRIBUTE_UNUSED
,
916 if ((value
& 1) != 0)
917 *errmsg
= _("offset not a multiple of 2");
918 if ((value
> 62) != 0)
919 *errmsg
= _("offset greater than 62");
920 return insn
| ((value
& 0x3e) << 10);
924 extract_ev2 (unsigned long insn
,
925 int dialect ATTRIBUTE_UNUSED
,
926 int *invalid ATTRIBUTE_UNUSED
)
928 return (insn
>> 10) & 0x3e;
932 insert_ev4 (unsigned long insn
,
934 int dialect ATTRIBUTE_UNUSED
,
937 if ((value
& 3) != 0)
938 *errmsg
= _("offset not a multiple of 4");
939 if ((value
> 124) != 0)
940 *errmsg
= _("offset greater than 124");
941 return insn
| ((value
& 0x7c) << 9);
945 extract_ev4 (unsigned long insn
,
946 int dialect ATTRIBUTE_UNUSED
,
947 int *invalid ATTRIBUTE_UNUSED
)
949 return (insn
>> 9) & 0x7c;
953 insert_ev8 (unsigned long insn
,
955 int dialect ATTRIBUTE_UNUSED
,
958 if ((value
& 7) != 0)
959 *errmsg
= _("offset not a multiple of 8");
960 if ((value
> 248) != 0)
961 *errmsg
= _("offset greater than 248");
962 return insn
| ((value
& 0xf8) << 8);
966 extract_ev8 (unsigned long insn
,
967 int dialect ATTRIBUTE_UNUSED
,
968 int *invalid ATTRIBUTE_UNUSED
)
970 return (insn
>> 8) & 0xf8;
973 /* The DS field in a DS form instruction. This is like D, but the
974 lower two bits are forced to zero. */
977 insert_ds (unsigned long insn
,
979 int dialect ATTRIBUTE_UNUSED
,
982 if ((value
& 3) != 0)
983 *errmsg
= _("offset not a multiple of 4");
984 return insn
| (value
& 0xfffc);
988 extract_ds (unsigned long insn
,
989 int dialect ATTRIBUTE_UNUSED
,
990 int *invalid ATTRIBUTE_UNUSED
)
992 return ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
995 /* The DE field in a DE form instruction. */
998 insert_de (unsigned long insn
,
1000 int dialect ATTRIBUTE_UNUSED
,
1001 const char **errmsg
)
1003 if (value
> 2047 || value
< -2048)
1004 *errmsg
= _("offset not between -2048 and 2047");
1005 return insn
| ((value
<< 4) & 0xfff0);
1009 extract_de (unsigned long insn
,
1010 int dialect ATTRIBUTE_UNUSED
,
1011 int *invalid ATTRIBUTE_UNUSED
)
1013 return (insn
& 0xfff0) >> 4;
1016 /* The DES field in a DES form instruction. */
1018 static unsigned long
1019 insert_des (unsigned long insn
,
1021 int dialect ATTRIBUTE_UNUSED
,
1022 const char **errmsg
)
1024 if (value
> 8191 || value
< -8192)
1025 *errmsg
= _("offset not between -8192 and 8191");
1026 else if ((value
& 3) != 0)
1027 *errmsg
= _("offset not a multiple of 4");
1028 return insn
| ((value
<< 2) & 0xfff0);
1032 extract_des (unsigned long insn
,
1033 int dialect ATTRIBUTE_UNUSED
,
1034 int *invalid ATTRIBUTE_UNUSED
)
1036 return (((insn
>> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
1039 /* FXM mask in mfcr and mtcrf instructions. */
1041 static unsigned long
1042 insert_fxm (unsigned long insn
,
1045 const char **errmsg
)
1047 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1048 one bit of the mask field is set. */
1049 if ((insn
& (1 << 20)) != 0)
1051 if (value
== 0 || (value
& -value
) != value
)
1053 *errmsg
= _("invalid mask field");
1058 /* If the optional field on mfcr is missing that means we want to use
1059 the old form of the instruction that moves the whole cr. In that
1060 case we'll have VALUE zero. There doesn't seem to be a way to
1061 distinguish this from the case where someone writes mfcr %r3,0. */
1062 else if (value
== 0)
1065 /* If only one bit of the FXM field is set, we can use the new form
1066 of the instruction, which is faster. Unlike the Power4 branch hint
1067 encoding, this is not backward compatible. Do not generate the
1068 new form unless -mpower4 has been given, or -many and the two
1069 operand form of mfcr was used. */
1070 else if ((value
& -value
) == value
1071 && ((dialect
& PPC_OPCODE_POWER4
) != 0
1072 || ((dialect
& PPC_OPCODE_ANY
) != 0
1073 && (insn
& (0x3ff << 1)) == 19 << 1)))
1076 /* Any other value on mfcr is an error. */
1077 else if ((insn
& (0x3ff << 1)) == 19 << 1)
1079 *errmsg
= _("ignoring invalid mfcr mask");
1083 return insn
| ((value
& 0xff) << 12);
1087 extract_fxm (unsigned long insn
,
1088 int dialect ATTRIBUTE_UNUSED
,
1091 long mask
= (insn
>> 12) & 0xff;
1093 /* Is this a Power4 insn? */
1094 if ((insn
& (1 << 20)) != 0)
1096 /* Exactly one bit of MASK should be set. */
1097 if (mask
== 0 || (mask
& -mask
) != mask
)
1101 /* Check that non-power4 form of mfcr has a zero MASK. */
1102 else if ((insn
& (0x3ff << 1)) == 19 << 1)
1111 /* The LI field in an I form instruction. The lower two bits are
1114 static unsigned long
1115 insert_li (unsigned long insn
,
1117 int dialect ATTRIBUTE_UNUSED
,
1118 const char **errmsg
)
1120 if ((value
& 3) != 0)
1121 *errmsg
= _("ignoring least significant bits in branch offset");
1122 return insn
| (value
& 0x3fffffc);
1126 extract_li (unsigned long insn
,
1127 int dialect ATTRIBUTE_UNUSED
,
1128 int *invalid ATTRIBUTE_UNUSED
)
1130 return ((insn
& 0x3fffffc) ^ 0x2000000) - 0x2000000;
1133 /* The MB and ME fields in an M form instruction expressed as a single
1134 operand which is itself a bitmask. The extraction function always
1135 marks it as invalid, since we never want to recognize an
1136 instruction which uses a field of this type. */
1138 static unsigned long
1139 insert_mbe (unsigned long insn
,
1141 int dialect ATTRIBUTE_UNUSED
,
1142 const char **errmsg
)
1144 unsigned long uval
, mask
;
1145 int mb
, me
, mx
, count
, last
;
1151 *errmsg
= _("illegal bitmask");
1157 if ((uval
& 1) != 0)
1163 /* mb: location of last 0->1 transition */
1164 /* me: location of last 1->0 transition */
1165 /* count: # transitions */
1167 for (mx
= 0, mask
= 1L << 31; mx
< 32; ++mx
, mask
>>= 1)
1169 if ((uval
& mask
) && !last
)
1175 else if (!(uval
& mask
) && last
)
1185 if (count
!= 2 && (count
!= 0 || ! last
))
1186 *errmsg
= _("illegal bitmask");
1188 return insn
| (mb
<< 6) | ((me
- 1) << 1);
1192 extract_mbe (unsigned long insn
,
1193 int dialect ATTRIBUTE_UNUSED
,
1202 mb
= (insn
>> 6) & 0x1f;
1203 me
= (insn
>> 1) & 0x1f;
1207 for (i
= mb
; i
<= me
; i
++)
1208 ret
|= 1L << (31 - i
);
1210 else if (mb
== me
+ 1)
1212 else /* (mb > me + 1) */
1215 for (i
= me
+ 1; i
< mb
; i
++)
1216 ret
&= ~(1L << (31 - i
));
1221 /* The MB or ME field in an MD or MDS form instruction. The high bit
1222 is wrapped to the low end. */
1224 static unsigned long
1225 insert_mb6 (unsigned long insn
,
1227 int dialect ATTRIBUTE_UNUSED
,
1228 const char **errmsg ATTRIBUTE_UNUSED
)
1230 return insn
| ((value
& 0x1f) << 6) | (value
& 0x20);
1234 extract_mb6 (unsigned long insn
,
1235 int dialect ATTRIBUTE_UNUSED
,
1236 int *invalid ATTRIBUTE_UNUSED
)
1238 return ((insn
>> 6) & 0x1f) | (insn
& 0x20);
1241 /* The NB field in an X form instruction. The value 32 is stored as
1244 static unsigned long
1245 insert_nb (unsigned long insn
,
1247 int dialect ATTRIBUTE_UNUSED
,
1248 const char **errmsg
)
1250 if (value
< 0 || value
> 32)
1251 *errmsg
= _("value out of range");
1254 return insn
| ((value
& 0x1f) << 11);
1258 extract_nb (unsigned long insn
,
1259 int dialect ATTRIBUTE_UNUSED
,
1260 int *invalid ATTRIBUTE_UNUSED
)
1264 ret
= (insn
>> 11) & 0x1f;
1270 /* The NSI field in a D form instruction. This is the same as the SI
1271 field, only negated. The extraction function always marks it as
1272 invalid, since we never want to recognize an instruction which uses
1273 a field of this type. */
1275 static unsigned long
1276 insert_nsi (unsigned long insn
,
1278 int dialect ATTRIBUTE_UNUSED
,
1279 const char **errmsg ATTRIBUTE_UNUSED
)
1281 return insn
| (-value
& 0xffff);
1285 extract_nsi (unsigned long insn
,
1286 int dialect ATTRIBUTE_UNUSED
,
1290 return -(((insn
& 0xffff) ^ 0x8000) - 0x8000);
1293 /* The RA field in a D or X form instruction which is an updating
1294 load, which means that the RA field may not be zero and may not
1295 equal the RT field. */
1297 static unsigned long
1298 insert_ral (unsigned long insn
,
1300 int dialect ATTRIBUTE_UNUSED
,
1301 const char **errmsg
)
1304 || (unsigned long) value
== ((insn
>> 21) & 0x1f))
1305 *errmsg
= "invalid register operand when updating";
1306 return insn
| ((value
& 0x1f) << 16);
1309 /* The RA field in an lmw instruction, which has special value
1312 static unsigned long
1313 insert_ram (unsigned long insn
,
1315 int dialect ATTRIBUTE_UNUSED
,
1316 const char **errmsg
)
1318 if ((unsigned long) value
>= ((insn
>> 21) & 0x1f))
1319 *errmsg
= _("index register in load range");
1320 return insn
| ((value
& 0x1f) << 16);
1323 /* The RA field in the DQ form lq instruction, which has special
1324 value restrictions. */
1326 static unsigned long
1327 insert_raq (unsigned long insn
,
1329 int dialect ATTRIBUTE_UNUSED
,
1330 const char **errmsg
)
1332 long rtvalue
= (insn
& RT_MASK
) >> 21;
1334 if (value
== rtvalue
)
1335 *errmsg
= _("source and target register operands must be different");
1336 return insn
| ((value
& 0x1f) << 16);
1339 /* The RA field in a D or X form instruction which is an updating
1340 store or an updating floating point load, which means that the RA
1341 field may not be zero. */
1343 static unsigned long
1344 insert_ras (unsigned long insn
,
1346 int dialect ATTRIBUTE_UNUSED
,
1347 const char **errmsg
)
1350 *errmsg
= _("invalid register operand when updating");
1351 return insn
| ((value
& 0x1f) << 16);
1354 /* The RB field in an X form instruction when it must be the same as
1355 the RS field in the instruction. This is used for extended
1356 mnemonics like mr. This operand is marked FAKE. The insertion
1357 function just copies the BT field into the BA field, and the
1358 extraction function just checks that the fields are the same. */
1360 static unsigned long
1361 insert_rbs (unsigned long insn
,
1362 long value ATTRIBUTE_UNUSED
,
1363 int dialect ATTRIBUTE_UNUSED
,
1364 const char **errmsg ATTRIBUTE_UNUSED
)
1366 return insn
| (((insn
>> 21) & 0x1f) << 11);
1370 extract_rbs (unsigned long insn
,
1371 int dialect ATTRIBUTE_UNUSED
,
1374 if (((insn
>> 21) & 0x1f) != ((insn
>> 11) & 0x1f))
1379 /* The RT field of the DQ form lq instruction, which has special
1380 value restrictions. */
1382 static unsigned long
1383 insert_rtq (unsigned long insn
,
1385 int dialect ATTRIBUTE_UNUSED
,
1386 const char **errmsg
)
1388 if ((value
& 1) != 0)
1389 *errmsg
= _("target register operand must be even");
1390 return insn
| ((value
& 0x1f) << 21);
1393 /* The RS field of the DS form stq instruction, which has special
1394 value restrictions. */
1396 static unsigned long
1397 insert_rsq (unsigned long insn
,
1398 long value ATTRIBUTE_UNUSED
,
1399 int dialect ATTRIBUTE_UNUSED
,
1400 const char **errmsg
)
1402 if ((value
& 1) != 0)
1403 *errmsg
= _("source register operand must be even");
1404 return insn
| ((value
& 0x1f) << 21);
1407 /* The SH field in an MD form instruction. This is split. */
1409 static unsigned long
1410 insert_sh6 (unsigned long insn
,
1412 int dialect ATTRIBUTE_UNUSED
,
1413 const char **errmsg ATTRIBUTE_UNUSED
)
1415 return insn
| ((value
& 0x1f) << 11) | ((value
& 0x20) >> 4);
1419 extract_sh6 (unsigned long insn
,
1420 int dialect ATTRIBUTE_UNUSED
,
1421 int *invalid ATTRIBUTE_UNUSED
)
1423 return ((insn
>> 11) & 0x1f) | ((insn
<< 4) & 0x20);
1426 /* The SPR field in an XFX form instruction. This is flipped--the
1427 lower 5 bits are stored in the upper 5 and vice- versa. */
1429 static unsigned long
1430 insert_spr (unsigned long insn
,
1432 int dialect ATTRIBUTE_UNUSED
,
1433 const char **errmsg ATTRIBUTE_UNUSED
)
1435 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
1439 extract_spr (unsigned long insn
,
1440 int dialect ATTRIBUTE_UNUSED
,
1441 int *invalid ATTRIBUTE_UNUSED
)
1443 return ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
1446 /* Some dialects have 8 SPRG registers instead of the standard 4. */
1448 static unsigned long
1449 insert_sprg (unsigned long insn
,
1452 const char **errmsg
)
1454 /* This check uses PPC_OPCODE_403 because PPC405 is later defined
1455 as a synonym. If ever a 405 specific dialect is added this
1456 check should use that instead. */
1459 && (dialect
& (PPC_OPCODE_BOOKE
| PPC_OPCODE_403
)) == 0))
1460 *errmsg
= _("invalid sprg number");
1462 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1463 user mode. Anything else must use spr 272..279. */
1464 if (value
<= 3 || (insn
& 0x100) != 0)
1467 return insn
| ((value
& 0x17) << 16);
1471 extract_sprg (unsigned long insn
,
1475 unsigned long val
= (insn
>> 16) & 0x1f;
1477 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1478 If not BOOKE or 405, then both use only 272..275. */
1480 || (val
< 0x10 && (insn
& 0x100) != 0)
1482 && (dialect
& (PPC_OPCODE_BOOKE
| PPC_OPCODE_403
)) == 0))
1487 /* The TBR field in an XFX instruction. This is just like SPR, but it
1488 is optional. When TBR is omitted, it must be inserted as 268 (the
1489 magic number of the TB register). These functions treat 0
1490 (indicating an omitted optional operand) as 268. This means that
1491 ``mftb 4,0'' is not handled correctly. This does not matter very
1492 much, since the architecture manual does not define mftb as
1493 accepting any values other than 268 or 269. */
1497 static unsigned long
1498 insert_tbr (unsigned long insn
,
1500 int dialect ATTRIBUTE_UNUSED
,
1501 const char **errmsg ATTRIBUTE_UNUSED
)
1505 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
1509 extract_tbr (unsigned long insn
,
1510 int dialect ATTRIBUTE_UNUSED
,
1511 int *invalid ATTRIBUTE_UNUSED
)
1515 ret
= ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
1521 /* Macros used to form opcodes. */
1523 /* The main opcode. */
1524 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1525 #define OP_MASK OP (0x3f)
1527 /* The main opcode combined with a trap code in the TO field of a D
1528 form instruction. Used for extended mnemonics for the trap
1530 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1531 #define OPTO_MASK (OP_MASK | TO_MASK)
1533 /* The main opcode combined with a comparison size bit in the L field
1534 of a D form or X form instruction. Used for extended mnemonics for
1535 the comparison instructions. */
1536 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1537 #define OPL_MASK OPL (0x3f,1)
1539 /* An A form instruction. */
1540 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1541 #define A_MASK A (0x3f, 0x1f, 1)
1543 /* An A_MASK with the FRB field fixed. */
1544 #define AFRB_MASK (A_MASK | FRB_MASK)
1546 /* An A_MASK with the FRC field fixed. */
1547 #define AFRC_MASK (A_MASK | FRC_MASK)
1549 /* An A_MASK with the FRA and FRC fields fixed. */
1550 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1552 /* An AFRAFRC_MASK, but with L bit clear. */
1553 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
1555 /* A B form instruction. */
1556 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1557 #define B_MASK B (0x3f, 1, 1)
1559 /* A B form instruction setting the BO field. */
1560 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1561 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1563 /* A BBO_MASK with the y bit of the BO field removed. This permits
1564 matching a conditional branch regardless of the setting of the y
1565 bit. Similarly for the 'at' bits used for power4 branch hints. */
1566 #define Y_MASK (((unsigned long) 1) << 21)
1567 #define AT1_MASK (((unsigned long) 3) << 21)
1568 #define AT2_MASK (((unsigned long) 9) << 21)
1569 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
1570 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1572 /* A B form instruction setting the BO field and the condition bits of
1574 #define BBOCB(op, bo, cb, aa, lk) \
1575 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1576 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1578 /* A BBOCB_MASK with the y bit of the BO field removed. */
1579 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1580 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1581 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1583 /* A BBOYCB_MASK in which the BI field is fixed. */
1584 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1585 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1587 /* An Context form instruction. */
1588 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
1589 #define CTX_MASK CTX(0x3f, 0x7)
1591 /* An User Context form instruction. */
1592 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1593 #define UCTX_MASK UCTX(0x3f, 0x1f)
1595 /* The main opcode mask with the RA field clear. */
1596 #define DRA_MASK (OP_MASK | RA_MASK)
1598 /* A DS form instruction. */
1599 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1600 #define DS_MASK DSO (0x3f, 3)
1602 /* A DE form instruction. */
1603 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1604 #define DE_MASK DEO (0x3e, 0xf)
1606 /* An EVSEL form instruction. */
1607 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1608 #define EVSEL_MASK EVSEL(0x3f, 0xff)
1610 /* An M form instruction. */
1611 #define M(op, rc) (OP (op) | ((rc) & 1))
1612 #define M_MASK M (0x3f, 1)
1614 /* An M form instruction with the ME field specified. */
1615 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1617 /* An M_MASK with the MB and ME fields fixed. */
1618 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1620 /* An M_MASK with the SH and ME fields fixed. */
1621 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1623 /* An MD form instruction. */
1624 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1625 #define MD_MASK MD (0x3f, 0x7, 1)
1627 /* An MD_MASK with the MB field fixed. */
1628 #define MDMB_MASK (MD_MASK | MB6_MASK)
1630 /* An MD_MASK with the SH field fixed. */
1631 #define MDSH_MASK (MD_MASK | SH6_MASK)
1633 /* An MDS form instruction. */
1634 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1635 #define MDS_MASK MDS (0x3f, 0xf, 1)
1637 /* An MDS_MASK with the MB field fixed. */
1638 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1640 /* An SC form instruction. */
1641 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1642 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1644 /* An VX form instruction. */
1645 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1647 /* The mask for an VX form instruction. */
1648 #define VX_MASK VX(0x3f, 0x7ff)
1650 /* An VA form instruction. */
1651 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1653 /* The mask for an VA form instruction. */
1654 #define VXA_MASK VXA(0x3f, 0x3f)
1656 /* An VXR form instruction. */
1657 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1659 /* The mask for a VXR form instruction. */
1660 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1662 /* An X form instruction. */
1663 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1665 /* A Z form instruction. */
1666 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1668 /* An X form instruction with the RC bit specified. */
1669 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1671 /* A Z form instruction with the RC bit specified. */
1672 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
1674 /* The mask for an X form instruction. */
1675 #define X_MASK XRC (0x3f, 0x3ff, 1)
1677 /* The mask for a Z form instruction. */
1678 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
1679 #define Z2_MASK ZRC (0x3f, 0xff, 1)
1681 /* An X_MASK with the RA field fixed. */
1682 #define XRA_MASK (X_MASK | RA_MASK)
1684 /* An X_MASK with the RB field fixed. */
1685 #define XRB_MASK (X_MASK | RB_MASK)
1687 /* An X_MASK with the RT field fixed. */
1688 #define XRT_MASK (X_MASK | RT_MASK)
1690 /* An XRT_MASK mask with the L bits clear. */
1691 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
1693 /* An X_MASK with the RA and RB fields fixed. */
1694 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1696 /* An XRARB_MASK, but with the L bit clear. */
1697 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1699 /* An X_MASK with the RT and RA fields fixed. */
1700 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1702 /* An XRTRA_MASK, but with L bit clear. */
1703 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1705 /* An X form instruction with the L bit specified. */
1706 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1708 /* The mask for an X form comparison instruction. */
1709 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1711 /* The mask for an X form comparison instruction with the L field
1713 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1715 /* An X form trap instruction with the TO field specified. */
1716 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1717 #define XTO_MASK (X_MASK | TO_MASK)
1719 /* An X form tlb instruction with the SH field specified. */
1720 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1721 #define XTLB_MASK (X_MASK | SH_MASK)
1723 /* An X form sync instruction. */
1724 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1726 /* An X form sync instruction with everything filled in except the LS field. */
1727 #define XSYNC_MASK (0xff9fffff)
1729 /* An X_MASK, but with the EH bit clear. */
1730 #define XEH_MASK (X_MASK & ~((unsigned long )1))
1732 /* An X form AltiVec dss instruction. */
1733 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1734 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1736 /* An XFL form instruction. */
1737 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1738 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1740 /* An X form isel instruction. */
1741 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1742 #define XISEL_MASK XISEL(0x3f, 0x1f)
1744 /* An XL form instruction with the LK field set to 0. */
1745 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1747 /* An XL form instruction which uses the LK field. */
1748 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1750 /* The mask for an XL form instruction. */
1751 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1753 /* An XL form instruction which explicitly sets the BO field. */
1754 #define XLO(op, bo, xop, lk) \
1755 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1756 #define XLO_MASK (XL_MASK | BO_MASK)
1758 /* An XL form instruction which explicitly sets the y bit of the BO
1760 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1761 #define XLYLK_MASK (XL_MASK | Y_MASK)
1763 /* An XL form instruction which sets the BO field and the condition
1764 bits of the BI field. */
1765 #define XLOCB(op, bo, cb, xop, lk) \
1766 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1767 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1769 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1770 #define XLBB_MASK (XL_MASK | BB_MASK)
1771 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1772 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1774 /* A mask for branch instructions using the BH field. */
1775 #define XLBH_MASK (XL_MASK | (0x1c << 11))
1777 /* An XL_MASK with the BO and BB fields fixed. */
1778 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1780 /* An XL_MASK with the BO, BI and BB fields fixed. */
1781 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1783 /* An XO form instruction. */
1784 #define XO(op, xop, oe, rc) \
1785 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1786 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1788 /* An XO_MASK with the RB field fixed. */
1789 #define XORB_MASK (XO_MASK | RB_MASK)
1791 /* An XS form instruction. */
1792 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1793 #define XS_MASK XS (0x3f, 0x1ff, 1)
1795 /* A mask for the FXM version of an XFX form instruction. */
1796 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
1798 /* An XFX form instruction with the FXM field filled in. */
1799 #define XFXM(op, xop, fxm, p4) \
1800 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1801 | ((unsigned long)(p4) << 20))
1803 /* An XFX form instruction with the SPR field filled in. */
1804 #define XSPR(op, xop, spr) \
1805 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1806 #define XSPR_MASK (X_MASK | SPR_MASK)
1808 /* An XFX form instruction with the SPR field filled in except for the
1810 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1812 /* An XFX form instruction with the SPR field filled in except for the
1814 #define XSPRG_MASK (XSPR_MASK & ~(0x17 << 16))
1816 /* An X form instruction with everything filled in except the E field. */
1817 #define XE_MASK (0xffff7fff)
1819 /* An X form user context instruction. */
1820 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1821 #define XUC_MASK XUC(0x3f, 0x1f)
1823 /* The BO encodings used in extended conditional branch mnemonics. */
1824 #define BODNZF (0x0)
1825 #define BODNZFP (0x1)
1827 #define BODZFP (0x3)
1828 #define BODNZT (0x8)
1829 #define BODNZTP (0x9)
1831 #define BODZTP (0xb)
1842 #define BODNZ (0x10)
1843 #define BODNZP (0x11)
1845 #define BODZP (0x13)
1846 #define BODNZM4 (0x18)
1847 #define BODNZP4 (0x19)
1848 #define BODZM4 (0x1a)
1849 #define BODZP4 (0x1b)
1853 /* The BI condition bit encodings used in extended conditional branch
1860 /* The TO encodings used in extended trap mnemonics. */
1877 /* Smaller names for the flags so each entry in the opcodes table will
1878 fit on a single line. */
1880 #define PPC PPC_OPCODE_PPC
1881 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1882 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1883 #define POWER4 PPC_OPCODE_POWER4
1884 #define POWER5 PPC_OPCODE_POWER5
1885 #define POWER6 PPC_OPCODE_POWER6
1886 #define CELL PPC_OPCODE_CELL
1887 #define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
1888 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
1889 #define PPC403 PPC_OPCODE_403
1890 #define PPC405 PPC403
1891 #define PPC440 PPC_OPCODE_440
1894 #define PPCVEC PPC_OPCODE_ALTIVEC
1895 #define POWER PPC_OPCODE_POWER
1896 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1897 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1898 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1899 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1900 #define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1901 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
1902 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1903 #define MFDEC1 PPC_OPCODE_POWER
1904 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1905 #define BOOKE PPC_OPCODE_BOOKE
1906 #define BOOKE64 PPC_OPCODE_BOOKE64
1907 #define CLASSIC PPC_OPCODE_CLASSIC
1908 #define PPCE300 PPC_OPCODE_E300
1909 #define PPCSPE PPC_OPCODE_SPE
1910 #define PPCISEL PPC_OPCODE_ISEL
1911 #define PPCEFS PPC_OPCODE_EFS
1912 #define PPCBRLK PPC_OPCODE_BRLOCK
1913 #define PPCPMR PPC_OPCODE_PMR
1914 #define PPCCHLK PPC_OPCODE_CACHELCK
1915 #define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1916 #define PPCRFMCI PPC_OPCODE_RFMCI
1918 /* The opcode table.
1920 The format of the opcode table is:
1922 NAME OPCODE MASK FLAGS { OPERANDS }
1924 NAME is the name of the instruction.
1925 OPCODE is the instruction opcode.
1926 MASK is the opcode mask; this is used to tell the disassembler
1927 which bits in the actual opcode must match OPCODE.
1928 FLAGS are flags indicated what processors support the instruction.
1929 OPERANDS is the list of operands.
1931 The disassembler reads the table in order and prints the first
1932 instruction which matches, so this table is sorted to put more
1933 specific instructions before more general instructions. It is also
1934 sorted by major opcode. */
1936 const struct powerpc_opcode powerpc_opcodes
[] = {
1937 { "attn", X(0,256), X_MASK
, POWER4
, { 0 } },
1938 { "tdlgti", OPTO(2,TOLGT
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1939 { "tdllti", OPTO(2,TOLLT
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1940 { "tdeqi", OPTO(2,TOEQ
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1941 { "tdlgei", OPTO(2,TOLGE
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1942 { "tdlnli", OPTO(2,TOLNL
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1943 { "tdllei", OPTO(2,TOLLE
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1944 { "tdlngi", OPTO(2,TOLNG
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1945 { "tdgti", OPTO(2,TOGT
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1946 { "tdgei", OPTO(2,TOGE
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1947 { "tdnli", OPTO(2,TONL
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1948 { "tdlti", OPTO(2,TOLT
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1949 { "tdlei", OPTO(2,TOLE
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1950 { "tdngi", OPTO(2,TONG
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1951 { "tdnei", OPTO(2,TONE
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1952 { "tdi", OP(2), OP_MASK
, PPC64
, { TO
, RA
, SI
} },
1954 { "twlgti", OPTO(3,TOLGT
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1955 { "tlgti", OPTO(3,TOLGT
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1956 { "twllti", OPTO(3,TOLLT
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1957 { "tllti", OPTO(3,TOLLT
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1958 { "tweqi", OPTO(3,TOEQ
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1959 { "teqi", OPTO(3,TOEQ
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1960 { "twlgei", OPTO(3,TOLGE
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1961 { "tlgei", OPTO(3,TOLGE
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1962 { "twlnli", OPTO(3,TOLNL
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1963 { "tlnli", OPTO(3,TOLNL
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1964 { "twllei", OPTO(3,TOLLE
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1965 { "tllei", OPTO(3,TOLLE
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1966 { "twlngi", OPTO(3,TOLNG
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1967 { "tlngi", OPTO(3,TOLNG
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1968 { "twgti", OPTO(3,TOGT
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1969 { "tgti", OPTO(3,TOGT
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1970 { "twgei", OPTO(3,TOGE
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1971 { "tgei", OPTO(3,TOGE
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1972 { "twnli", OPTO(3,TONL
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1973 { "tnli", OPTO(3,TONL
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1974 { "twlti", OPTO(3,TOLT
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1975 { "tlti", OPTO(3,TOLT
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1976 { "twlei", OPTO(3,TOLE
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1977 { "tlei", OPTO(3,TOLE
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1978 { "twngi", OPTO(3,TONG
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1979 { "tngi", OPTO(3,TONG
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1980 { "twnei", OPTO(3,TONE
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1981 { "tnei", OPTO(3,TONE
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1982 { "twi", OP(3), OP_MASK
, PPCCOM
, { TO
, RA
, SI
} },
1983 { "ti", OP(3), OP_MASK
, PWRCOM
, { TO
, RA
, SI
} },
1985 { "macchw", XO(4,172,0,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
1986 { "macchw.", XO(4,172,0,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
1987 { "macchwo", XO(4,172,1,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
1988 { "macchwo.", XO(4,172,1,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
1989 { "macchws", XO(4,236,0,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
1990 { "macchws.", XO(4,236,0,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
1991 { "macchwso", XO(4,236,1,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
1992 { "macchwso.", XO(4,236,1,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
1993 { "macchwsu", XO(4,204,0,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
1994 { "macchwsu.", XO(4,204,0,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
1995 { "macchwsuo", XO(4,204,1,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
1996 { "macchwsuo.", XO(4,204,1,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
1997 { "macchwu", XO(4,140,0,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
1998 { "macchwu.", XO(4,140,0,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
1999 { "macchwuo", XO(4,140,1,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2000 { "macchwuo.", XO(4,140,1,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2001 { "machhw", XO(4,44,0,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2002 { "machhw.", XO(4,44,0,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2003 { "machhwo", XO(4,44,1,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2004 { "machhwo.", XO(4,44,1,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2005 { "machhws", XO(4,108,0,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2006 { "machhws.", XO(4,108,0,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2007 { "machhwso", XO(4,108,1,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2008 { "machhwso.", XO(4,108,1,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2009 { "machhwsu", XO(4,76,0,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2010 { "machhwsu.", XO(4,76,0,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2011 { "machhwsuo", XO(4,76,1,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2012 { "machhwsuo.", XO(4,76,1,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2013 { "machhwu", XO(4,12,0,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2014 { "machhwu.", XO(4,12,0,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2015 { "machhwuo", XO(4,12,1,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2016 { "machhwuo.", XO(4,12,1,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2017 { "maclhw", XO(4,428,0,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2018 { "maclhw.", XO(4,428,0,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2019 { "maclhwo", XO(4,428,1,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2020 { "maclhwo.", XO(4,428,1,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2021 { "maclhws", XO(4,492,0,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2022 { "maclhws.", XO(4,492,0,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2023 { "maclhwso", XO(4,492,1,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2024 { "maclhwso.", XO(4,492,1,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2025 { "maclhwsu", XO(4,460,0,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2026 { "maclhwsu.", XO(4,460,0,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2027 { "maclhwsuo", XO(4,460,1,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2028 { "maclhwsuo.", XO(4,460,1,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2029 { "maclhwu", XO(4,396,0,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2030 { "maclhwu.", XO(4,396,0,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2031 { "maclhwuo", XO(4,396,1,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2032 { "maclhwuo.", XO(4,396,1,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2033 { "mulchw", XRC(4,168,0), X_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2034 { "mulchw.", XRC(4,168,1), X_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2035 { "mulchwu", XRC(4,136,0), X_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2036 { "mulchwu.", XRC(4,136,1), X_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2037 { "mulhhw", XRC(4,40,0), X_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2038 { "mulhhw.", XRC(4,40,1), X_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2039 { "mulhhwu", XRC(4,8,0), X_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2040 { "mulhhwu.", XRC(4,8,1), X_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2041 { "mullhw", XRC(4,424,0), X_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2042 { "mullhw.", XRC(4,424,1), X_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2043 { "mullhwu", XRC(4,392,0), X_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2044 { "mullhwu.", XRC(4,392,1), X_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2045 { "nmacchw", XO(4,174,0,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2046 { "nmacchw.", XO(4,174,0,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2047 { "nmacchwo", XO(4,174,1,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2048 { "nmacchwo.", XO(4,174,1,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2049 { "nmacchws", XO(4,238,0,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2050 { "nmacchws.", XO(4,238,0,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2051 { "nmacchwso", XO(4,238,1,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2052 { "nmacchwso.", XO(4,238,1,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2053 { "nmachhw", XO(4,46,0,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2054 { "nmachhw.", XO(4,46,0,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2055 { "nmachhwo", XO(4,46,1,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2056 { "nmachhwo.", XO(4,46,1,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2057 { "nmachhws", XO(4,110,0,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2058 { "nmachhws.", XO(4,110,0,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2059 { "nmachhwso", XO(4,110,1,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2060 { "nmachhwso.", XO(4,110,1,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2061 { "nmaclhw", XO(4,430,0,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2062 { "nmaclhw.", XO(4,430,0,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2063 { "nmaclhwo", XO(4,430,1,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2064 { "nmaclhwo.", XO(4,430,1,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2065 { "nmaclhws", XO(4,494,0,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2066 { "nmaclhws.", XO(4,494,0,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2067 { "nmaclhwso", XO(4,494,1,0), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2068 { "nmaclhwso.", XO(4,494,1,1), XO_MASK
, PPC405
|PPC440
, { RT
, RA
, RB
} },
2069 { "mfvscr", VX(4, 1540), VX_MASK
, PPCVEC
, { VD
} },
2070 { "mtvscr", VX(4, 1604), VX_MASK
, PPCVEC
, { VB
} },
2072 /* Double-precision opcodes. */
2073 /* Some of these conflict with AltiVec, so move them before, since
2074 PPCVEC includes the PPC_OPCODE_PPC set. */
2075 { "efscfd", VX(4, 719), VX_MASK
, PPCEFS
, { RS
, RB
} },
2076 { "efdabs", VX(4, 740), VX_MASK
, PPCEFS
, { RS
, RA
} },
2077 { "efdnabs", VX(4, 741), VX_MASK
, PPCEFS
, { RS
, RA
} },
2078 { "efdneg", VX(4, 742), VX_MASK
, PPCEFS
, { RS
, RA
} },
2079 { "efdadd", VX(4, 736), VX_MASK
, PPCEFS
, { RS
, RA
, RB
} },
2080 { "efdsub", VX(4, 737), VX_MASK
, PPCEFS
, { RS
, RA
, RB
} },
2081 { "efdmul", VX(4, 744), VX_MASK
, PPCEFS
, { RS
, RA
, RB
} },
2082 { "efddiv", VX(4, 745), VX_MASK
, PPCEFS
, { RS
, RA
, RB
} },
2083 { "efdcmpgt", VX(4, 748), VX_MASK
, PPCEFS
, { CRFD
, RA
, RB
} },
2084 { "efdcmplt", VX(4, 749), VX_MASK
, PPCEFS
, { CRFD
, RA
, RB
} },
2085 { "efdcmpeq", VX(4, 750), VX_MASK
, PPCEFS
, { CRFD
, RA
, RB
} },
2086 { "efdtstgt", VX(4, 764), VX_MASK
, PPCEFS
, { CRFD
, RA
, RB
} },
2087 { "efdtstlt", VX(4, 765), VX_MASK
, PPCEFS
, { CRFD
, RA
, RB
} },
2088 { "efdtsteq", VX(4, 766), VX_MASK
, PPCEFS
, { CRFD
, RA
, RB
} },
2089 { "efdcfsi", VX(4, 753), VX_MASK
, PPCEFS
, { RS
, RB
} },
2090 { "efdcfsid", VX(4, 739), VX_MASK
, PPCEFS
, { RS
, RB
} },
2091 { "efdcfui", VX(4, 752), VX_MASK
, PPCEFS
, { RS
, RB
} },
2092 { "efdcfuid", VX(4, 738), VX_MASK
, PPCEFS
, { RS
, RB
} },
2093 { "efdcfsf", VX(4, 755), VX_MASK
, PPCEFS
, { RS
, RB
} },
2094 { "efdcfuf", VX(4, 754), VX_MASK
, PPCEFS
, { RS
, RB
} },
2095 { "efdctsi", VX(4, 757), VX_MASK
, PPCEFS
, { RS
, RB
} },
2096 { "efdctsidz",VX(4, 747), VX_MASK
, PPCEFS
, { RS
, RB
} },
2097 { "efdctsiz", VX(4, 762), VX_MASK
, PPCEFS
, { RS
, RB
} },
2098 { "efdctui", VX(4, 756), VX_MASK
, PPCEFS
, { RS
, RB
} },
2099 { "efdctuidz",VX(4, 746), VX_MASK
, PPCEFS
, { RS
, RB
} },
2100 { "efdctuiz", VX(4, 760), VX_MASK
, PPCEFS
, { RS
, RB
} },
2101 { "efdctsf", VX(4, 759), VX_MASK
, PPCEFS
, { RS
, RB
} },
2102 { "efdctuf", VX(4, 758), VX_MASK
, PPCEFS
, { RS
, RB
} },
2103 { "efdcfs", VX(4, 751), VX_MASK
, PPCEFS
, { RS
, RB
} },
2104 /* End of double-precision opcodes. */
2106 { "vaddcuw", VX(4, 384), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2107 { "vaddfp", VX(4, 10), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2108 { "vaddsbs", VX(4, 768), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2109 { "vaddshs", VX(4, 832), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2110 { "vaddsws", VX(4, 896), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2111 { "vaddubm", VX(4, 0), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2112 { "vaddubs", VX(4, 512), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2113 { "vadduhm", VX(4, 64), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2114 { "vadduhs", VX(4, 576), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2115 { "vadduwm", VX(4, 128), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2116 { "vadduws", VX(4, 640), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2117 { "vand", VX(4, 1028), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2118 { "vandc", VX(4, 1092), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2119 { "vavgsb", VX(4, 1282), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2120 { "vavgsh", VX(4, 1346), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2121 { "vavgsw", VX(4, 1410), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2122 { "vavgub", VX(4, 1026), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2123 { "vavguh", VX(4, 1090), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2124 { "vavguw", VX(4, 1154), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2125 { "vcfsx", VX(4, 842), VX_MASK
, PPCVEC
, { VD
, VB
, UIMM
} },
2126 { "vcfux", VX(4, 778), VX_MASK
, PPCVEC
, { VD
, VB
, UIMM
} },
2127 { "vcmpbfp", VXR(4, 966, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2128 { "vcmpbfp.", VXR(4, 966, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2129 { "vcmpeqfp", VXR(4, 198, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2130 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2131 { "vcmpequb", VXR(4, 6, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2132 { "vcmpequb.", VXR(4, 6, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2133 { "vcmpequh", VXR(4, 70, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2134 { "vcmpequh.", VXR(4, 70, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2135 { "vcmpequw", VXR(4, 134, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2136 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2137 { "vcmpgefp", VXR(4, 454, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2138 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2139 { "vcmpgtfp", VXR(4, 710, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2140 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2141 { "vcmpgtsb", VXR(4, 774, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2142 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2143 { "vcmpgtsh", VXR(4, 838, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2144 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2145 { "vcmpgtsw", VXR(4, 902, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2146 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2147 { "vcmpgtub", VXR(4, 518, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2148 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2149 { "vcmpgtuh", VXR(4, 582, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2150 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2151 { "vcmpgtuw", VXR(4, 646, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2152 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2153 { "vctsxs", VX(4, 970), VX_MASK
, PPCVEC
, { VD
, VB
, UIMM
} },
2154 { "vctuxs", VX(4, 906), VX_MASK
, PPCVEC
, { VD
, VB
, UIMM
} },
2155 { "vexptefp", VX(4, 394), VX_MASK
, PPCVEC
, { VD
, VB
} },
2156 { "vlogefp", VX(4, 458), VX_MASK
, PPCVEC
, { VD
, VB
} },
2157 { "vmaddfp", VXA(4, 46), VXA_MASK
, PPCVEC
, { VD
, VA
, VC
, VB
} },
2158 { "vmaxfp", VX(4, 1034), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2159 { "vmaxsb", VX(4, 258), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2160 { "vmaxsh", VX(4, 322), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2161 { "vmaxsw", VX(4, 386), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2162 { "vmaxub", VX(4, 2), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2163 { "vmaxuh", VX(4, 66), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2164 { "vmaxuw", VX(4, 130), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2165 { "vmhaddshs", VXA(4, 32), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
2166 { "vmhraddshs", VXA(4, 33), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
2167 { "vminfp", VX(4, 1098), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2168 { "vminsb", VX(4, 770), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2169 { "vminsh", VX(4, 834), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2170 { "vminsw", VX(4, 898), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2171 { "vminub", VX(4, 514), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2172 { "vminuh", VX(4, 578), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2173 { "vminuw", VX(4, 642), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2174 { "vmladduhm", VXA(4, 34), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
2175 { "vmrghb", VX(4, 12), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2176 { "vmrghh", VX(4, 76), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2177 { "vmrghw", VX(4, 140), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2178 { "vmrglb", VX(4, 268), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2179 { "vmrglh", VX(4, 332), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2180 { "vmrglw", VX(4, 396), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2181 { "vmsummbm", VXA(4, 37), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
2182 { "vmsumshm", VXA(4, 40), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
2183 { "vmsumshs", VXA(4, 41), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
2184 { "vmsumubm", VXA(4, 36), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
2185 { "vmsumuhm", VXA(4, 38), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
2186 { "vmsumuhs", VXA(4, 39), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
2187 { "vmulesb", VX(4, 776), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2188 { "vmulesh", VX(4, 840), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2189 { "vmuleub", VX(4, 520), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2190 { "vmuleuh", VX(4, 584), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2191 { "vmulosb", VX(4, 264), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2192 { "vmulosh", VX(4, 328), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2193 { "vmuloub", VX(4, 8), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2194 { "vmulouh", VX(4, 72), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2195 { "vnmsubfp", VXA(4, 47), VXA_MASK
, PPCVEC
, { VD
, VA
, VC
, VB
} },
2196 { "vnor", VX(4, 1284), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2197 { "vor", VX(4, 1156), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2198 { "vperm", VXA(4, 43), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
2199 { "vpkpx", VX(4, 782), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2200 { "vpkshss", VX(4, 398), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2201 { "vpkshus", VX(4, 270), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2202 { "vpkswss", VX(4, 462), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2203 { "vpkswus", VX(4, 334), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2204 { "vpkuhum", VX(4, 14), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2205 { "vpkuhus", VX(4, 142), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2206 { "vpkuwum", VX(4, 78), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2207 { "vpkuwus", VX(4, 206), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2208 { "vrefp", VX(4, 266), VX_MASK
, PPCVEC
, { VD
, VB
} },
2209 { "vrfim", VX(4, 714), VX_MASK
, PPCVEC
, { VD
, VB
} },
2210 { "vrfin", VX(4, 522), VX_MASK
, PPCVEC
, { VD
, VB
} },
2211 { "vrfip", VX(4, 650), VX_MASK
, PPCVEC
, { VD
, VB
} },
2212 { "vrfiz", VX(4, 586), VX_MASK
, PPCVEC
, { VD
, VB
} },
2213 { "vrlb", VX(4, 4), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2214 { "vrlh", VX(4, 68), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2215 { "vrlw", VX(4, 132), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2216 { "vrsqrtefp", VX(4, 330), VX_MASK
, PPCVEC
, { VD
, VB
} },
2217 { "vsel", VXA(4, 42), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
2218 { "vsl", VX(4, 452), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2219 { "vslb", VX(4, 260), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2220 { "vsldoi", VXA(4, 44), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, SHB
} },
2221 { "vslh", VX(4, 324), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2222 { "vslo", VX(4, 1036), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2223 { "vslw", VX(4, 388), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2224 { "vspltb", VX(4, 524), VX_MASK
, PPCVEC
, { VD
, VB
, UIMM
} },
2225 { "vsplth", VX(4, 588), VX_MASK
, PPCVEC
, { VD
, VB
, UIMM
} },
2226 { "vspltisb", VX(4, 780), VX_MASK
, PPCVEC
, { VD
, SIMM
} },
2227 { "vspltish", VX(4, 844), VX_MASK
, PPCVEC
, { VD
, SIMM
} },
2228 { "vspltisw", VX(4, 908), VX_MASK
, PPCVEC
, { VD
, SIMM
} },
2229 { "vspltw", VX(4, 652), VX_MASK
, PPCVEC
, { VD
, VB
, UIMM
} },
2230 { "vsr", VX(4, 708), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2231 { "vsrab", VX(4, 772), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2232 { "vsrah", VX(4, 836), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2233 { "vsraw", VX(4, 900), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2234 { "vsrb", VX(4, 516), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2235 { "vsrh", VX(4, 580), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2236 { "vsro", VX(4, 1100), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2237 { "vsrw", VX(4, 644), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2238 { "vsubcuw", VX(4, 1408), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2239 { "vsubfp", VX(4, 74), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2240 { "vsubsbs", VX(4, 1792), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2241 { "vsubshs", VX(4, 1856), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2242 { "vsubsws", VX(4, 1920), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2243 { "vsububm", VX(4, 1024), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2244 { "vsububs", VX(4, 1536), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2245 { "vsubuhm", VX(4, 1088), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2246 { "vsubuhs", VX(4, 1600), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2247 { "vsubuwm", VX(4, 1152), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2248 { "vsubuws", VX(4, 1664), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2249 { "vsumsws", VX(4, 1928), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2250 { "vsum2sws", VX(4, 1672), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2251 { "vsum4sbs", VX(4, 1800), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2252 { "vsum4shs", VX(4, 1608), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2253 { "vsum4ubs", VX(4, 1544), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2254 { "vupkhpx", VX(4, 846), VX_MASK
, PPCVEC
, { VD
, VB
} },
2255 { "vupkhsb", VX(4, 526), VX_MASK
, PPCVEC
, { VD
, VB
} },
2256 { "vupkhsh", VX(4, 590), VX_MASK
, PPCVEC
, { VD
, VB
} },
2257 { "vupklpx", VX(4, 974), VX_MASK
, PPCVEC
, { VD
, VB
} },
2258 { "vupklsb", VX(4, 654), VX_MASK
, PPCVEC
, { VD
, VB
} },
2259 { "vupklsh", VX(4, 718), VX_MASK
, PPCVEC
, { VD
, VB
} },
2260 { "vxor", VX(4, 1220), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
2262 { "evaddw", VX(4, 512), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2263 { "evaddiw", VX(4, 514), VX_MASK
, PPCSPE
, { RS
, RB
, UIMM
} },
2264 { "evsubfw", VX(4, 516), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2265 { "evsubw", VX(4, 516), VX_MASK
, PPCSPE
, { RS
, RB
, RA
} },
2266 { "evsubifw", VX(4, 518), VX_MASK
, PPCSPE
, { RS
, UIMM
, RB
} },
2267 { "evsubiw", VX(4, 518), VX_MASK
, PPCSPE
, { RS
, RB
, UIMM
} },
2268 { "evabs", VX(4, 520), VX_MASK
, PPCSPE
, { RS
, RA
} },
2269 { "evneg", VX(4, 521), VX_MASK
, PPCSPE
, { RS
, RA
} },
2270 { "evextsb", VX(4, 522), VX_MASK
, PPCSPE
, { RS
, RA
} },
2271 { "evextsh", VX(4, 523), VX_MASK
, PPCSPE
, { RS
, RA
} },
2272 { "evrndw", VX(4, 524), VX_MASK
, PPCSPE
, { RS
, RA
} },
2273 { "evcntlzw", VX(4, 525), VX_MASK
, PPCSPE
, { RS
, RA
} },
2274 { "evcntlsw", VX(4, 526), VX_MASK
, PPCSPE
, { RS
, RA
} },
2276 { "brinc", VX(4, 527), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2278 { "evand", VX(4, 529), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2279 { "evandc", VX(4, 530), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2280 { "evmr", VX(4, 535), VX_MASK
, PPCSPE
, { RS
, RA
, BBA
} },
2281 { "evor", VX(4, 535), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2282 { "evorc", VX(4, 539), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2283 { "evxor", VX(4, 534), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2284 { "eveqv", VX(4, 537), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2285 { "evnand", VX(4, 542), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2286 { "evnot", VX(4, 536), VX_MASK
, PPCSPE
, { RS
, RA
, BBA
} },
2287 { "evnor", VX(4, 536), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2289 { "evrlw", VX(4, 552), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2290 { "evrlwi", VX(4, 554), VX_MASK
, PPCSPE
, { RS
, RA
, EVUIMM
} },
2291 { "evslw", VX(4, 548), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2292 { "evslwi", VX(4, 550), VX_MASK
, PPCSPE
, { RS
, RA
, EVUIMM
} },
2293 { "evsrws", VX(4, 545), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2294 { "evsrwu", VX(4, 544), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2295 { "evsrwis", VX(4, 547), VX_MASK
, PPCSPE
, { RS
, RA
, EVUIMM
} },
2296 { "evsrwiu", VX(4, 546), VX_MASK
, PPCSPE
, { RS
, RA
, EVUIMM
} },
2297 { "evsplati", VX(4, 553), VX_MASK
, PPCSPE
, { RS
, SIMM
} },
2298 { "evsplatfi", VX(4, 555), VX_MASK
, PPCSPE
, { RS
, SIMM
} },
2299 { "evmergehi", VX(4, 556), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2300 { "evmergelo", VX(4, 557), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2301 { "evmergehilo",VX(4,558), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2302 { "evmergelohi",VX(4,559), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2304 { "evcmpgts", VX(4, 561), VX_MASK
, PPCSPE
, { CRFD
, RA
, RB
} },
2305 { "evcmpgtu", VX(4, 560), VX_MASK
, PPCSPE
, { CRFD
, RA
, RB
} },
2306 { "evcmplts", VX(4, 563), VX_MASK
, PPCSPE
, { CRFD
, RA
, RB
} },
2307 { "evcmpltu", VX(4, 562), VX_MASK
, PPCSPE
, { CRFD
, RA
, RB
} },
2308 { "evcmpeq", VX(4, 564), VX_MASK
, PPCSPE
, { CRFD
, RA
, RB
} },
2309 { "evsel", EVSEL(4,79),EVSEL_MASK
, PPCSPE
, { RS
, RA
, RB
, CRFS
} },
2311 { "evldd", VX(4, 769), VX_MASK
, PPCSPE
, { RS
, EVUIMM_8
, RA
} },
2312 { "evlddx", VX(4, 768), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2313 { "evldw", VX(4, 771), VX_MASK
, PPCSPE
, { RS
, EVUIMM_8
, RA
} },
2314 { "evldwx", VX(4, 770), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2315 { "evldh", VX(4, 773), VX_MASK
, PPCSPE
, { RS
, EVUIMM_8
, RA
} },
2316 { "evldhx", VX(4, 772), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2317 { "evlwhe", VX(4, 785), VX_MASK
, PPCSPE
, { RS
, EVUIMM_4
, RA
} },
2318 { "evlwhex", VX(4, 784), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2319 { "evlwhou", VX(4, 789), VX_MASK
, PPCSPE
, { RS
, EVUIMM_4
, RA
} },
2320 { "evlwhoux", VX(4, 788), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2321 { "evlwhos", VX(4, 791), VX_MASK
, PPCSPE
, { RS
, EVUIMM_4
, RA
} },
2322 { "evlwhosx", VX(4, 790), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2323 { "evlwwsplat",VX(4, 793), VX_MASK
, PPCSPE
, { RS
, EVUIMM_4
, RA
} },
2324 { "evlwwsplatx",VX(4, 792), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2325 { "evlwhsplat",VX(4, 797), VX_MASK
, PPCSPE
, { RS
, EVUIMM_4
, RA
} },
2326 { "evlwhsplatx",VX(4, 796), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2327 { "evlhhesplat",VX(4, 777), VX_MASK
, PPCSPE
, { RS
, EVUIMM_2
, RA
} },
2328 { "evlhhesplatx",VX(4, 776), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2329 { "evlhhousplat",VX(4, 781), VX_MASK
, PPCSPE
, { RS
, EVUIMM_2
, RA
} },
2330 { "evlhhousplatx",VX(4, 780), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2331 { "evlhhossplat",VX(4, 783), VX_MASK
, PPCSPE
, { RS
, EVUIMM_2
, RA
} },
2332 { "evlhhossplatx",VX(4, 782), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2334 { "evstdd", VX(4, 801), VX_MASK
, PPCSPE
, { RS
, EVUIMM_8
, RA
} },
2335 { "evstddx", VX(4, 800), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2336 { "evstdw", VX(4, 803), VX_MASK
, PPCSPE
, { RS
, EVUIMM_8
, RA
} },
2337 { "evstdwx", VX(4, 802), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2338 { "evstdh", VX(4, 805), VX_MASK
, PPCSPE
, { RS
, EVUIMM_8
, RA
} },
2339 { "evstdhx", VX(4, 804), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2340 { "evstwwe", VX(4, 825), VX_MASK
, PPCSPE
, { RS
, EVUIMM_4
, RA
} },
2341 { "evstwwex", VX(4, 824), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2342 { "evstwwo", VX(4, 829), VX_MASK
, PPCSPE
, { RS
, EVUIMM_4
, RA
} },
2343 { "evstwwox", VX(4, 828), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2344 { "evstwhe", VX(4, 817), VX_MASK
, PPCSPE
, { RS
, EVUIMM_4
, RA
} },
2345 { "evstwhex", VX(4, 816), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2346 { "evstwho", VX(4, 821), VX_MASK
, PPCSPE
, { RS
, EVUIMM_4
, RA
} },
2347 { "evstwhox", VX(4, 820), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2349 { "evfsabs", VX(4, 644), VX_MASK
, PPCSPE
, { RS
, RA
} },
2350 { "evfsnabs", VX(4, 645), VX_MASK
, PPCSPE
, { RS
, RA
} },
2351 { "evfsneg", VX(4, 646), VX_MASK
, PPCSPE
, { RS
, RA
} },
2352 { "evfsadd", VX(4, 640), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2353 { "evfssub", VX(4, 641), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2354 { "evfsmul", VX(4, 648), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2355 { "evfsdiv", VX(4, 649), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2356 { "evfscmpgt", VX(4, 652), VX_MASK
, PPCSPE
, { CRFD
, RA
, RB
} },
2357 { "evfscmplt", VX(4, 653), VX_MASK
, PPCSPE
, { CRFD
, RA
, RB
} },
2358 { "evfscmpeq", VX(4, 654), VX_MASK
, PPCSPE
, { CRFD
, RA
, RB
} },
2359 { "evfststgt", VX(4, 668), VX_MASK
, PPCSPE
, { CRFD
, RA
, RB
} },
2360 { "evfststlt", VX(4, 669), VX_MASK
, PPCSPE
, { CRFD
, RA
, RB
} },
2361 { "evfststeq", VX(4, 670), VX_MASK
, PPCSPE
, { CRFD
, RA
, RB
} },
2362 { "evfscfui", VX(4, 656), VX_MASK
, PPCSPE
, { RS
, RB
} },
2363 { "evfsctuiz", VX(4, 664), VX_MASK
, PPCSPE
, { RS
, RB
} },
2364 { "evfscfsi", VX(4, 657), VX_MASK
, PPCSPE
, { RS
, RB
} },
2365 { "evfscfuf", VX(4, 658), VX_MASK
, PPCSPE
, { RS
, RB
} },
2366 { "evfscfsf", VX(4, 659), VX_MASK
, PPCSPE
, { RS
, RB
} },
2367 { "evfsctui", VX(4, 660), VX_MASK
, PPCSPE
, { RS
, RB
} },
2368 { "evfsctsi", VX(4, 661), VX_MASK
, PPCSPE
, { RS
, RB
} },
2369 { "evfsctsiz", VX(4, 666), VX_MASK
, PPCSPE
, { RS
, RB
} },
2370 { "evfsctuf", VX(4, 662), VX_MASK
, PPCSPE
, { RS
, RB
} },
2371 { "evfsctsf", VX(4, 663), VX_MASK
, PPCSPE
, { RS
, RB
} },
2373 { "efsabs", VX(4, 708), VX_MASK
, PPCEFS
, { RS
, RA
} },
2374 { "efsnabs", VX(4, 709), VX_MASK
, PPCEFS
, { RS
, RA
} },
2375 { "efsneg", VX(4, 710), VX_MASK
, PPCEFS
, { RS
, RA
} },
2376 { "efsadd", VX(4, 704), VX_MASK
, PPCEFS
, { RS
, RA
, RB
} },
2377 { "efssub", VX(4, 705), VX_MASK
, PPCEFS
, { RS
, RA
, RB
} },
2378 { "efsmul", VX(4, 712), VX_MASK
, PPCEFS
, { RS
, RA
, RB
} },
2379 { "efsdiv", VX(4, 713), VX_MASK
, PPCEFS
, { RS
, RA
, RB
} },
2380 { "efscmpgt", VX(4, 716), VX_MASK
, PPCEFS
, { CRFD
, RA
, RB
} },
2381 { "efscmplt", VX(4, 717), VX_MASK
, PPCEFS
, { CRFD
, RA
, RB
} },
2382 { "efscmpeq", VX(4, 718), VX_MASK
, PPCEFS
, { CRFD
, RA
, RB
} },
2383 { "efststgt", VX(4, 732), VX_MASK
, PPCEFS
, { CRFD
, RA
, RB
} },
2384 { "efststlt", VX(4, 733), VX_MASK
, PPCEFS
, { CRFD
, RA
, RB
} },
2385 { "efststeq", VX(4, 734), VX_MASK
, PPCEFS
, { CRFD
, RA
, RB
} },
2386 { "efscfui", VX(4, 720), VX_MASK
, PPCEFS
, { RS
, RB
} },
2387 { "efsctuiz", VX(4, 728), VX_MASK
, PPCEFS
, { RS
, RB
} },
2388 { "efscfsi", VX(4, 721), VX_MASK
, PPCEFS
, { RS
, RB
} },
2389 { "efscfuf", VX(4, 722), VX_MASK
, PPCEFS
, { RS
, RB
} },
2390 { "efscfsf", VX(4, 723), VX_MASK
, PPCEFS
, { RS
, RB
} },
2391 { "efsctui", VX(4, 724), VX_MASK
, PPCEFS
, { RS
, RB
} },
2392 { "efsctsi", VX(4, 725), VX_MASK
, PPCEFS
, { RS
, RB
} },
2393 { "efsctsiz", VX(4, 730), VX_MASK
, PPCEFS
, { RS
, RB
} },
2394 { "efsctuf", VX(4, 726), VX_MASK
, PPCEFS
, { RS
, RB
} },
2395 { "efsctsf", VX(4, 727), VX_MASK
, PPCEFS
, { RS
, RB
} },
2397 { "evmhossf", VX(4, 1031), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2398 { "evmhossfa", VX(4, 1063), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2399 { "evmhosmf", VX(4, 1039), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2400 { "evmhosmfa", VX(4, 1071), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2401 { "evmhosmi", VX(4, 1037), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2402 { "evmhosmia", VX(4, 1069), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2403 { "evmhoumi", VX(4, 1036), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2404 { "evmhoumia", VX(4, 1068), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2405 { "evmhessf", VX(4, 1027), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2406 { "evmhessfa", VX(4, 1059), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2407 { "evmhesmf", VX(4, 1035), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2408 { "evmhesmfa", VX(4, 1067), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2409 { "evmhesmi", VX(4, 1033), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2410 { "evmhesmia", VX(4, 1065), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2411 { "evmheumi", VX(4, 1032), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2412 { "evmheumia", VX(4, 1064), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2414 { "evmhossfaaw",VX(4, 1287), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2415 { "evmhossiaaw",VX(4, 1285), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2416 { "evmhosmfaaw",VX(4, 1295), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2417 { "evmhosmiaaw",VX(4, 1293), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2418 { "evmhousiaaw",VX(4, 1284), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2419 { "evmhoumiaaw",VX(4, 1292), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2420 { "evmhessfaaw",VX(4, 1283), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2421 { "evmhessiaaw",VX(4, 1281), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2422 { "evmhesmfaaw",VX(4, 1291), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2423 { "evmhesmiaaw",VX(4, 1289), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2424 { "evmheusiaaw",VX(4, 1280), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2425 { "evmheumiaaw",VX(4, 1288), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2427 { "evmhossfanw",VX(4, 1415), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2428 { "evmhossianw",VX(4, 1413), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2429 { "evmhosmfanw",VX(4, 1423), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2430 { "evmhosmianw",VX(4, 1421), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2431 { "evmhousianw",VX(4, 1412), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2432 { "evmhoumianw",VX(4, 1420), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2433 { "evmhessfanw",VX(4, 1411), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2434 { "evmhessianw",VX(4, 1409), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2435 { "evmhesmfanw",VX(4, 1419), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2436 { "evmhesmianw",VX(4, 1417), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2437 { "evmheusianw",VX(4, 1408), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2438 { "evmheumianw",VX(4, 1416), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2440 { "evmhogsmfaa",VX(4, 1327), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2441 { "evmhogsmiaa",VX(4, 1325), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2442 { "evmhogumiaa",VX(4, 1324), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2443 { "evmhegsmfaa",VX(4, 1323), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2444 { "evmhegsmiaa",VX(4, 1321), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2445 { "evmhegumiaa",VX(4, 1320), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2447 { "evmhogsmfan",VX(4, 1455), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2448 { "evmhogsmian",VX(4, 1453), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2449 { "evmhogumian",VX(4, 1452), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2450 { "evmhegsmfan",VX(4, 1451), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2451 { "evmhegsmian",VX(4, 1449), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2452 { "evmhegumian",VX(4, 1448), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2454 { "evmwhssf", VX(4, 1095), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2455 { "evmwhssfa", VX(4, 1127), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2456 { "evmwhsmf", VX(4, 1103), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2457 { "evmwhsmfa", VX(4, 1135), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2458 { "evmwhsmi", VX(4, 1101), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2459 { "evmwhsmia", VX(4, 1133), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2460 { "evmwhumi", VX(4, 1100), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2461 { "evmwhumia", VX(4, 1132), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2463 { "evmwlumi", VX(4, 1096), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2464 { "evmwlumia", VX(4, 1128), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2466 { "evmwlssiaaw",VX(4, 1345), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2467 { "evmwlsmiaaw",VX(4, 1353), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2468 { "evmwlusiaaw",VX(4, 1344), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2469 { "evmwlumiaaw",VX(4, 1352), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2471 { "evmwlssianw",VX(4, 1473), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2472 { "evmwlsmianw",VX(4, 1481), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2473 { "evmwlusianw",VX(4, 1472), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2474 { "evmwlumianw",VX(4, 1480), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2476 { "evmwssf", VX(4, 1107), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2477 { "evmwssfa", VX(4, 1139), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2478 { "evmwsmf", VX(4, 1115), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2479 { "evmwsmfa", VX(4, 1147), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2480 { "evmwsmi", VX(4, 1113), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2481 { "evmwsmia", VX(4, 1145), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2482 { "evmwumi", VX(4, 1112), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2483 { "evmwumia", VX(4, 1144), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2485 { "evmwssfaa", VX(4, 1363), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2486 { "evmwsmfaa", VX(4, 1371), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2487 { "evmwsmiaa", VX(4, 1369), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2488 { "evmwumiaa", VX(4, 1368), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2490 { "evmwssfan", VX(4, 1491), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2491 { "evmwsmfan", VX(4, 1499), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2492 { "evmwsmian", VX(4, 1497), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2493 { "evmwumian", VX(4, 1496), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2495 { "evaddssiaaw",VX(4, 1217), VX_MASK
, PPCSPE
, { RS
, RA
} },
2496 { "evaddsmiaaw",VX(4, 1225), VX_MASK
, PPCSPE
, { RS
, RA
} },
2497 { "evaddusiaaw",VX(4, 1216), VX_MASK
, PPCSPE
, { RS
, RA
} },
2498 { "evaddumiaaw",VX(4, 1224), VX_MASK
, PPCSPE
, { RS
, RA
} },
2500 { "evsubfssiaaw",VX(4, 1219), VX_MASK
, PPCSPE
, { RS
, RA
} },
2501 { "evsubfsmiaaw",VX(4, 1227), VX_MASK
, PPCSPE
, { RS
, RA
} },
2502 { "evsubfusiaaw",VX(4, 1218), VX_MASK
, PPCSPE
, { RS
, RA
} },
2503 { "evsubfumiaaw",VX(4, 1226), VX_MASK
, PPCSPE
, { RS
, RA
} },
2505 { "evmra", VX(4, 1220), VX_MASK
, PPCSPE
, { RS
, RA
} },
2507 { "evdivws", VX(4, 1222), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2508 { "evdivwu", VX(4, 1223), VX_MASK
, PPCSPE
, { RS
, RA
, RB
} },
2510 { "mulli", OP(7), OP_MASK
, PPCCOM
, { RT
, RA
, SI
} },
2511 { "muli", OP(7), OP_MASK
, PWRCOM
, { RT
, RA
, SI
} },
2513 { "subfic", OP(8), OP_MASK
, PPCCOM
, { RT
, RA
, SI
} },
2514 { "sfi", OP(8), OP_MASK
, PWRCOM
, { RT
, RA
, SI
} },
2516 { "dozi", OP(9), OP_MASK
, M601
, { RT
, RA
, SI
} },
2518 { "bce", B(9,0,0), B_MASK
, BOOKE64
, { BO
, BI
, BD
} },
2519 { "bcel", B(9,0,1), B_MASK
, BOOKE64
, { BO
, BI
, BD
} },
2520 { "bcea", B(9,1,0), B_MASK
, BOOKE64
, { BO
, BI
, BDA
} },
2521 { "bcela", B(9,1,1), B_MASK
, BOOKE64
, { BO
, BI
, BDA
} },
2523 { "cmplwi", OPL(10,0), OPL_MASK
, PPCCOM
, { OBF
, RA
, UI
} },
2524 { "cmpldi", OPL(10,1), OPL_MASK
, PPC64
, { OBF
, RA
, UI
} },
2525 { "cmpli", OP(10), OP_MASK
, PPC
, { BF
, L
, RA
, UI
} },
2526 { "cmpli", OP(10), OP_MASK
, PWRCOM
, { BF
, RA
, UI
} },
2528 { "cmpwi", OPL(11,0), OPL_MASK
, PPCCOM
, { OBF
, RA
, SI
} },
2529 { "cmpdi", OPL(11,1), OPL_MASK
, PPC64
, { OBF
, RA
, SI
} },
2530 { "cmpi", OP(11), OP_MASK
, PPC
, { BF
, L
, RA
, SI
} },
2531 { "cmpi", OP(11), OP_MASK
, PWRCOM
, { BF
, RA
, SI
} },
2533 { "addic", OP(12), OP_MASK
, PPCCOM
, { RT
, RA
, SI
} },
2534 { "ai", OP(12), OP_MASK
, PWRCOM
, { RT
, RA
, SI
} },
2535 { "subic", OP(12), OP_MASK
, PPCCOM
, { RT
, RA
, NSI
} },
2537 { "addic.", OP(13), OP_MASK
, PPCCOM
, { RT
, RA
, SI
} },
2538 { "ai.", OP(13), OP_MASK
, PWRCOM
, { RT
, RA
, SI
} },
2539 { "subic.", OP(13), OP_MASK
, PPCCOM
, { RT
, RA
, NSI
} },
2541 { "li", OP(14), DRA_MASK
, PPCCOM
, { RT
, SI
} },
2542 { "lil", OP(14), DRA_MASK
, PWRCOM
, { RT
, SI
} },
2543 { "addi", OP(14), OP_MASK
, PPCCOM
, { RT
, RA0
, SI
} },
2544 { "cal", OP(14), OP_MASK
, PWRCOM
, { RT
, D
, RA0
} },
2545 { "subi", OP(14), OP_MASK
, PPCCOM
, { RT
, RA0
, NSI
} },
2546 { "la", OP(14), OP_MASK
, PPCCOM
, { RT
, D
, RA0
} },
2548 { "lis", OP(15), DRA_MASK
, PPCCOM
, { RT
, SISIGNOPT
} },
2549 { "liu", OP(15), DRA_MASK
, PWRCOM
, { RT
, SISIGNOPT
} },
2550 { "addis", OP(15), OP_MASK
, PPCCOM
, { RT
,RA0
,SISIGNOPT
} },
2551 { "cau", OP(15), OP_MASK
, PWRCOM
, { RT
,RA0
,SISIGNOPT
} },
2552 { "subis", OP(15), OP_MASK
, PPCCOM
, { RT
, RA0
, NSI
} },
2554 { "bdnz-", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, { BDM
} },
2555 { "bdnz+", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, { BDP
} },
2556 { "bdnz", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, { BD
} },
2557 { "bdn", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PWRCOM
, { BD
} },
2558 { "bdnzl-", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, { BDM
} },
2559 { "bdnzl+", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, { BDP
} },
2560 { "bdnzl", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, { BD
} },
2561 { "bdnl", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PWRCOM
, { BD
} },
2562 { "bdnza-", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, { BDMA
} },
2563 { "bdnza+", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, { BDPA
} },
2564 { "bdnza", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, { BDA
} },
2565 { "bdna", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PWRCOM
, { BDA
} },
2566 { "bdnzla-", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, { BDMA
} },
2567 { "bdnzla+", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, { BDPA
} },
2568 { "bdnzla", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, { BDA
} },
2569 { "bdnla", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PWRCOM
, { BDA
} },
2570 { "bdz-", BBO(16,BODZ
,0,0), BBOATBI_MASK
, PPCCOM
, { BDM
} },
2571 { "bdz+", BBO(16,BODZ
,0,0), BBOATBI_MASK
, PPCCOM
, { BDP
} },
2572 { "bdz", BBO(16,BODZ
,0,0), BBOATBI_MASK
, COM
, { BD
} },
2573 { "bdzl-", BBO(16,BODZ
,0,1), BBOATBI_MASK
, PPCCOM
, { BDM
} },
2574 { "bdzl+", BBO(16,BODZ
,0,1), BBOATBI_MASK
, PPCCOM
, { BDP
} },
2575 { "bdzl", BBO(16,BODZ
,0,1), BBOATBI_MASK
, COM
, { BD
} },
2576 { "bdza-", BBO(16,BODZ
,1,0), BBOATBI_MASK
, PPCCOM
, { BDMA
} },
2577 { "bdza+", BBO(16,BODZ
,1,0), BBOATBI_MASK
, PPCCOM
, { BDPA
} },
2578 { "bdza", BBO(16,BODZ
,1,0), BBOATBI_MASK
, COM
, { BDA
} },
2579 { "bdzla-", BBO(16,BODZ
,1,1), BBOATBI_MASK
, PPCCOM
, { BDMA
} },
2580 { "bdzla+", BBO(16,BODZ
,1,1), BBOATBI_MASK
, PPCCOM
, { BDPA
} },
2581 { "bdzla", BBO(16,BODZ
,1,1), BBOATBI_MASK
, COM
, { BDA
} },
2582 { "blt-", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2583 { "blt+", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2584 { "blt", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, COM
, { CR
, BD
} },
2585 { "bltl-", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2586 { "bltl+", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2587 { "bltl", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, COM
, { CR
, BD
} },
2588 { "blta-", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2589 { "blta+", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2590 { "blta", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2591 { "bltla-", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2592 { "bltla+", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2593 { "bltla", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2594 { "bgt-", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2595 { "bgt+", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2596 { "bgt", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, COM
, { CR
, BD
} },
2597 { "bgtl-", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2598 { "bgtl+", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2599 { "bgtl", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, COM
, { CR
, BD
} },
2600 { "bgta-", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2601 { "bgta+", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2602 { "bgta", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2603 { "bgtla-", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2604 { "bgtla+", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2605 { "bgtla", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2606 { "beq-", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2607 { "beq+", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2608 { "beq", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, COM
, { CR
, BD
} },
2609 { "beql-", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2610 { "beql+", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2611 { "beql", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, COM
, { CR
, BD
} },
2612 { "beqa-", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2613 { "beqa+", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2614 { "beqa", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2615 { "beqla-", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2616 { "beqla+", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2617 { "beqla", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2618 { "bso-", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2619 { "bso+", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2620 { "bso", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, COM
, { CR
, BD
} },
2621 { "bsol-", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2622 { "bsol+", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2623 { "bsol", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, COM
, { CR
, BD
} },
2624 { "bsoa-", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2625 { "bsoa+", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2626 { "bsoa", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2627 { "bsola-", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2628 { "bsola+", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2629 { "bsola", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2630 { "bun-", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2631 { "bun+", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2632 { "bun", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BD
} },
2633 { "bunl-", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2634 { "bunl+", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2635 { "bunl", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BD
} },
2636 { "buna-", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2637 { "buna+", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2638 { "buna", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDA
} },
2639 { "bunla-", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2640 { "bunla+", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2641 { "bunla", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDA
} },
2642 { "bge-", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2643 { "bge+", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2644 { "bge", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, COM
, { CR
, BD
} },
2645 { "bgel-", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2646 { "bgel+", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2647 { "bgel", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, COM
, { CR
, BD
} },
2648 { "bgea-", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2649 { "bgea+", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2650 { "bgea", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2651 { "bgela-", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2652 { "bgela+", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2653 { "bgela", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2654 { "bnl-", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2655 { "bnl+", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2656 { "bnl", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, COM
, { CR
, BD
} },
2657 { "bnll-", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2658 { "bnll+", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2659 { "bnll", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, COM
, { CR
, BD
} },
2660 { "bnla-", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2661 { "bnla+", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2662 { "bnla", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2663 { "bnlla-", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2664 { "bnlla+", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2665 { "bnlla", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2666 { "ble-", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2667 { "ble+", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2668 { "ble", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, COM
, { CR
, BD
} },
2669 { "blel-", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2670 { "blel+", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2671 { "blel", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, COM
, { CR
, BD
} },
2672 { "blea-", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2673 { "blea+", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2674 { "blea", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2675 { "blela-", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2676 { "blela+", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2677 { "blela", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2678 { "bng-", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2679 { "bng+", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2680 { "bng", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, COM
, { CR
, BD
} },
2681 { "bngl-", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2682 { "bngl+", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2683 { "bngl", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, COM
, { CR
, BD
} },
2684 { "bnga-", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2685 { "bnga+", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2686 { "bnga", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2687 { "bngla-", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2688 { "bngla+", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2689 { "bngla", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2690 { "bne-", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2691 { "bne+", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2692 { "bne", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, COM
, { CR
, BD
} },
2693 { "bnel-", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2694 { "bnel+", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2695 { "bnel", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, COM
, { CR
, BD
} },
2696 { "bnea-", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2697 { "bnea+", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2698 { "bnea", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2699 { "bnela-", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2700 { "bnela+", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2701 { "bnela", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2702 { "bns-", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2703 { "bns+", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2704 { "bns", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, COM
, { CR
, BD
} },
2705 { "bnsl-", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2706 { "bnsl+", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2707 { "bnsl", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, COM
, { CR
, BD
} },
2708 { "bnsa-", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2709 { "bnsa+", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2710 { "bnsa", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2711 { "bnsla-", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2712 { "bnsla+", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2713 { "bnsla", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2714 { "bnu-", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2715 { "bnu+", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2716 { "bnu", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BD
} },
2717 { "bnul-", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2718 { "bnul+", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2719 { "bnul", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BD
} },
2720 { "bnua-", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2721 { "bnua+", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2722 { "bnua", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDA
} },
2723 { "bnula-", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2724 { "bnula+", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2725 { "bnula", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDA
} },
2726 { "bdnzt-", BBO(16,BODNZT
,0,0), BBOY_MASK
, NOPOWER4
, { BI
, BDM
} },
2727 { "bdnzt+", BBO(16,BODNZT
,0,0), BBOY_MASK
, NOPOWER4
, { BI
, BDP
} },
2728 { "bdnzt", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, { BI
, BD
} },
2729 { "bdnztl-", BBO(16,BODNZT
,0,1), BBOY_MASK
, NOPOWER4
, { BI
, BDM
} },
2730 { "bdnztl+", BBO(16,BODNZT
,0,1), BBOY_MASK
, NOPOWER4
, { BI
, BDP
} },
2731 { "bdnztl", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, { BI
, BD
} },
2732 { "bdnzta-", BBO(16,BODNZT
,1,0), BBOY_MASK
, NOPOWER4
, { BI
, BDMA
} },
2733 { "bdnzta+", BBO(16,BODNZT
,1,0), BBOY_MASK
, NOPOWER4
, { BI
, BDPA
} },
2734 { "bdnzta", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, { BI
, BDA
} },
2735 { "bdnztla-",BBO(16,BODNZT
,1,1), BBOY_MASK
, NOPOWER4
, { BI
, BDMA
} },
2736 { "bdnztla+",BBO(16,BODNZT
,1,1), BBOY_MASK
, NOPOWER4
, { BI
, BDPA
} },
2737 { "bdnztla", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, { BI
, BDA
} },
2738 { "bdnzf-", BBO(16,BODNZF
,0,0), BBOY_MASK
, NOPOWER4
, { BI
, BDM
} },
2739 { "bdnzf+", BBO(16,BODNZF
,0,0), BBOY_MASK
, NOPOWER4
, { BI
, BDP
} },
2740 { "bdnzf", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, { BI
, BD
} },
2741 { "bdnzfl-", BBO(16,BODNZF
,0,1), BBOY_MASK
, NOPOWER4
, { BI
, BDM
} },
2742 { "bdnzfl+", BBO(16,BODNZF
,0,1), BBOY_MASK
, NOPOWER4
, { BI
, BDP
} },
2743 { "bdnzfl", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, { BI
, BD
} },
2744 { "bdnzfa-", BBO(16,BODNZF
,1,0), BBOY_MASK
, NOPOWER4
, { BI
, BDMA
} },
2745 { "bdnzfa+", BBO(16,BODNZF
,1,0), BBOY_MASK
, NOPOWER4
, { BI
, BDPA
} },
2746 { "bdnzfa", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, { BI
, BDA
} },
2747 { "bdnzfla-",BBO(16,BODNZF
,1,1), BBOY_MASK
, NOPOWER4
, { BI
, BDMA
} },
2748 { "bdnzfla+",BBO(16,BODNZF
,1,1), BBOY_MASK
, NOPOWER4
, { BI
, BDPA
} },
2749 { "bdnzfla", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, { BI
, BDA
} },
2750 { "bt-", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, { BI
, BDM
} },
2751 { "bt+", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, { BI
, BDP
} },
2752 { "bt", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, { BI
, BD
} },
2753 { "bbt", BBO(16,BOT
,0,0), BBOAT_MASK
, PWRCOM
, { BI
, BD
} },
2754 { "btl-", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, { BI
, BDM
} },
2755 { "btl+", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, { BI
, BDP
} },
2756 { "btl", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, { BI
, BD
} },
2757 { "bbtl", BBO(16,BOT
,0,1), BBOAT_MASK
, PWRCOM
, { BI
, BD
} },
2758 { "bta-", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, { BI
, BDMA
} },
2759 { "bta+", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, { BI
, BDPA
} },
2760 { "bta", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, { BI
, BDA
} },
2761 { "bbta", BBO(16,BOT
,1,0), BBOAT_MASK
, PWRCOM
, { BI
, BDA
} },
2762 { "btla-", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, { BI
, BDMA
} },
2763 { "btla+", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, { BI
, BDPA
} },
2764 { "btla", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, { BI
, BDA
} },
2765 { "bbtla", BBO(16,BOT
,1,1), BBOAT_MASK
, PWRCOM
, { BI
, BDA
} },
2766 { "bf-", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, { BI
, BDM
} },
2767 { "bf+", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, { BI
, BDP
} },
2768 { "bf", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, { BI
, BD
} },
2769 { "bbf", BBO(16,BOF
,0,0), BBOAT_MASK
, PWRCOM
, { BI
, BD
} },
2770 { "bfl-", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, { BI
, BDM
} },
2771 { "bfl+", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, { BI
, BDP
} },
2772 { "bfl", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, { BI
, BD
} },
2773 { "bbfl", BBO(16,BOF
,0,1), BBOAT_MASK
, PWRCOM
, { BI
, BD
} },
2774 { "bfa-", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, { BI
, BDMA
} },
2775 { "bfa+", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, { BI
, BDPA
} },
2776 { "bfa", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, { BI
, BDA
} },
2777 { "bbfa", BBO(16,BOF
,1,0), BBOAT_MASK
, PWRCOM
, { BI
, BDA
} },
2778 { "bfla-", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, { BI
, BDMA
} },
2779 { "bfla+", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, { BI
, BDPA
} },
2780 { "bfla", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, { BI
, BDA
} },
2781 { "bbfla", BBO(16,BOF
,1,1), BBOAT_MASK
, PWRCOM
, { BI
, BDA
} },
2782 { "bdzt-", BBO(16,BODZT
,0,0), BBOY_MASK
, NOPOWER4
, { BI
, BDM
} },
2783 { "bdzt+", BBO(16,BODZT
,0,0), BBOY_MASK
, NOPOWER4
, { BI
, BDP
} },
2784 { "bdzt", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, { BI
, BD
} },
2785 { "bdztl-", BBO(16,BODZT
,0,1), BBOY_MASK
, NOPOWER4
, { BI
, BDM
} },
2786 { "bdztl+", BBO(16,BODZT
,0,1), BBOY_MASK
, NOPOWER4
, { BI
, BDP
} },
2787 { "bdztl", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, { BI
, BD
} },
2788 { "bdzta-", BBO(16,BODZT
,1,0), BBOY_MASK
, NOPOWER4
, { BI
, BDMA
} },
2789 { "bdzta+", BBO(16,BODZT
,1,0), BBOY_MASK
, NOPOWER4
, { BI
, BDPA
} },
2790 { "bdzta", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, { BI
, BDA
} },
2791 { "bdztla-", BBO(16,BODZT
,1,1), BBOY_MASK
, NOPOWER4
, { BI
, BDMA
} },
2792 { "bdztla+", BBO(16,BODZT
,1,1), BBOY_MASK
, NOPOWER4
, { BI
, BDPA
} },
2793 { "bdztla", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, { BI
, BDA
} },
2794 { "bdzf-", BBO(16,BODZF
,0,0), BBOY_MASK
, NOPOWER4
, { BI
, BDM
} },
2795 { "bdzf+", BBO(16,BODZF
,0,0), BBOY_MASK
, NOPOWER4
, { BI
, BDP
} },
2796 { "bdzf", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, { BI
, BD
} },
2797 { "bdzfl-", BBO(16,BODZF
,0,1), BBOY_MASK
, NOPOWER4
, { BI
, BDM
} },
2798 { "bdzfl+", BBO(16,BODZF
,0,1), BBOY_MASK
, NOPOWER4
, { BI
, BDP
} },
2799 { "bdzfl", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, { BI
, BD
} },
2800 { "bdzfa-", BBO(16,BODZF
,1,0), BBOY_MASK
, NOPOWER4
, { BI
, BDMA
} },
2801 { "bdzfa+", BBO(16,BODZF
,1,0), BBOY_MASK
, NOPOWER4
, { BI
, BDPA
} },
2802 { "bdzfa", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, { BI
, BDA
} },
2803 { "bdzfla-", BBO(16,BODZF
,1,1), BBOY_MASK
, NOPOWER4
, { BI
, BDMA
} },
2804 { "bdzfla+", BBO(16,BODZF
,1,1), BBOY_MASK
, NOPOWER4
, { BI
, BDPA
} },
2805 { "bdzfla", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, { BI
, BDA
} },
2806 { "bc-", B(16,0,0), B_MASK
, PPCCOM
, { BOE
, BI
, BDM
} },
2807 { "bc+", B(16,0,0), B_MASK
, PPCCOM
, { BOE
, BI
, BDP
} },
2808 { "bc", B(16,0,0), B_MASK
, COM
, { BO
, BI
, BD
} },
2809 { "bcl-", B(16,0,1), B_MASK
, PPCCOM
, { BOE
, BI
, BDM
} },
2810 { "bcl+", B(16,0,1), B_MASK
, PPCCOM
, { BOE
, BI
, BDP
} },
2811 { "bcl", B(16,0,1), B_MASK
, COM
, { BO
, BI
, BD
} },
2812 { "bca-", B(16,1,0), B_MASK
, PPCCOM
, { BOE
, BI
, BDMA
} },
2813 { "bca+", B(16,1,0), B_MASK
, PPCCOM
, { BOE
, BI
, BDPA
} },
2814 { "bca", B(16,1,0), B_MASK
, COM
, { BO
, BI
, BDA
} },
2815 { "bcla-", B(16,1,1), B_MASK
, PPCCOM
, { BOE
, BI
, BDMA
} },
2816 { "bcla+", B(16,1,1), B_MASK
, PPCCOM
, { BOE
, BI
, BDPA
} },
2817 { "bcla", B(16,1,1), B_MASK
, COM
, { BO
, BI
, BDA
} },
2819 { "sc", SC(17,1,0), SC_MASK
, PPC
, { LEV
} },
2820 { "svc", SC(17,0,0), SC_MASK
, POWER
, { SVC_LEV
, FL1
, FL2
} },
2821 { "svcl", SC(17,0,1), SC_MASK
, POWER
, { SVC_LEV
, FL1
, FL2
} },
2822 { "svca", SC(17,1,0), SC_MASK
, PWRCOM
, { SV
} },
2823 { "svcla", SC(17,1,1), SC_MASK
, POWER
, { SV
} },
2825 { "b", B(18,0,0), B_MASK
, COM
, { LI
} },
2826 { "bl", B(18,0,1), B_MASK
, COM
, { LI
} },
2827 { "ba", B(18,1,0), B_MASK
, COM
, { LIA
} },
2828 { "bla", B(18,1,1), B_MASK
, COM
, { LIA
} },
2830 { "mcrf", XL(19,0), XLBB_MASK
|(3 << 21)|(3 << 16), COM
, { BF
, BFA
} },
2832 { "blr", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, PPCCOM
, { 0 } },
2833 { "br", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, PWRCOM
, { 0 } },
2834 { "blrl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, PPCCOM
, { 0 } },
2835 { "brl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, PWRCOM
, { 0 } },
2836 { "bdnzlr", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, { 0 } },
2837 { "bdnzlr-", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, NOPOWER4
, { 0 } },
2838 { "bdnzlr-", XLO(19,BODNZM4
,16,0), XLBOBIBB_MASK
, POWER4
, { 0 } },
2839 { "bdnzlr+", XLO(19,BODNZP
,16,0), XLBOBIBB_MASK
, NOPOWER4
, { 0 } },
2840 { "bdnzlr+", XLO(19,BODNZP4
,16,0), XLBOBIBB_MASK
, POWER4
, { 0 } },
2841 { "bdnzlrl", XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, { 0 } },
2842 { "bdnzlrl-",XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, NOPOWER4
, { 0 } },
2843 { "bdnzlrl-",XLO(19,BODNZM4
,16,1), XLBOBIBB_MASK
, POWER4
, { 0 } },
2844 { "bdnzlrl+",XLO(19,BODNZP
,16,1), XLBOBIBB_MASK
, NOPOWER4
, { 0 } },
2845 { "bdnzlrl+",XLO(19,BODNZP4
,16,1), XLBOBIBB_MASK
, POWER4
, { 0 } },
2846 { "bdzlr", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, { 0 } },
2847 { "bdzlr-", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, NOPOWER4
, { 0 } },
2848 { "bdzlr-", XLO(19,BODZM4
,16,0), XLBOBIBB_MASK
, POWER4
, { 0 } },
2849 { "bdzlr+", XLO(19,BODZP
,16,0), XLBOBIBB_MASK
, NOPOWER4
, { 0 } },
2850 { "bdzlr+", XLO(19,BODZP4
,16,0), XLBOBIBB_MASK
, POWER4
, { 0 } },
2851 { "bdzlrl", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, { 0 } },
2852 { "bdzlrl-", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, NOPOWER4
, { 0 } },
2853 { "bdzlrl-", XLO(19,BODZM4
,16,1), XLBOBIBB_MASK
, POWER4
, { 0 } },
2854 { "bdzlrl+", XLO(19,BODZP
,16,1), XLBOBIBB_MASK
, NOPOWER4
, { 0 } },
2855 { "bdzlrl+", XLO(19,BODZP4
,16,1), XLBOBIBB_MASK
, POWER4
, { 0 } },
2856 { "bltlr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2857 { "bltlr-", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2858 { "bltlr-", XLOCB(19,BOTM4
,CBLT
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2859 { "bltlr+", XLOCB(19,BOTP
,CBLT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2860 { "bltlr+", XLOCB(19,BOTP4
,CBLT
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2861 { "bltr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2862 { "bltlrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2863 { "bltlrl-", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2864 { "bltlrl-", XLOCB(19,BOTM4
,CBLT
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2865 { "bltlrl+", XLOCB(19,BOTP
,CBLT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2866 { "bltlrl+", XLOCB(19,BOTP4
,CBLT
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2867 { "bltrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2868 { "bgtlr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2869 { "bgtlr-", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2870 { "bgtlr-", XLOCB(19,BOTM4
,CBGT
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2871 { "bgtlr+", XLOCB(19,BOTP
,CBGT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2872 { "bgtlr+", XLOCB(19,BOTP4
,CBGT
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2873 { "bgtr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2874 { "bgtlrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2875 { "bgtlrl-", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2876 { "bgtlrl-", XLOCB(19,BOTM4
,CBGT
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2877 { "bgtlrl+", XLOCB(19,BOTP
,CBGT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2878 { "bgtlrl+", XLOCB(19,BOTP4
,CBGT
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2879 { "bgtrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2880 { "beqlr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2881 { "beqlr-", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2882 { "beqlr-", XLOCB(19,BOTM4
,CBEQ
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2883 { "beqlr+", XLOCB(19,BOTP
,CBEQ
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2884 { "beqlr+", XLOCB(19,BOTP4
,CBEQ
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2885 { "beqr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2886 { "beqlrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2887 { "beqlrl-", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2888 { "beqlrl-", XLOCB(19,BOTM4
,CBEQ
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2889 { "beqlrl+", XLOCB(19,BOTP
,CBEQ
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2890 { "beqlrl+", XLOCB(19,BOTP4
,CBEQ
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2891 { "beqrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2892 { "bsolr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2893 { "bsolr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2894 { "bsolr-", XLOCB(19,BOTM4
,CBSO
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2895 { "bsolr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2896 { "bsolr+", XLOCB(19,BOTP4
,CBSO
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2897 { "bsor", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2898 { "bsolrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2899 { "bsolrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2900 { "bsolrl-", XLOCB(19,BOTM4
,CBSO
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2901 { "bsolrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2902 { "bsolrl+", XLOCB(19,BOTP4
,CBSO
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2903 { "bsorl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2904 { "bunlr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2905 { "bunlr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2906 { "bunlr-", XLOCB(19,BOTM4
,CBSO
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2907 { "bunlr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2908 { "bunlr+", XLOCB(19,BOTP4
,CBSO
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2909 { "bunlrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2910 { "bunlrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2911 { "bunlrl-", XLOCB(19,BOTM4
,CBSO
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2912 { "bunlrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2913 { "bunlrl+", XLOCB(19,BOTP4
,CBSO
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2914 { "bgelr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2915 { "bgelr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2916 { "bgelr-", XLOCB(19,BOFM4
,CBLT
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2917 { "bgelr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2918 { "bgelr+", XLOCB(19,BOFP4
,CBLT
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2919 { "bger", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2920 { "bgelrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2921 { "bgelrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2922 { "bgelrl-", XLOCB(19,BOFM4
,CBLT
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2923 { "bgelrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2924 { "bgelrl+", XLOCB(19,BOFP4
,CBLT
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2925 { "bgerl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2926 { "bnllr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2927 { "bnllr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2928 { "bnllr-", XLOCB(19,BOFM4
,CBLT
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2929 { "bnllr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2930 { "bnllr+", XLOCB(19,BOFP4
,CBLT
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2931 { "bnlr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2932 { "bnllrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2933 { "bnllrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2934 { "bnllrl-", XLOCB(19,BOFM4
,CBLT
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2935 { "bnllrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2936 { "bnllrl+", XLOCB(19,BOFP4
,CBLT
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2937 { "bnlrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2938 { "blelr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2939 { "blelr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2940 { "blelr-", XLOCB(19,BOFM4
,CBGT
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2941 { "blelr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2942 { "blelr+", XLOCB(19,BOFP4
,CBGT
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2943 { "bler", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2944 { "blelrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2945 { "blelrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2946 { "blelrl-", XLOCB(19,BOFM4
,CBGT
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2947 { "blelrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2948 { "blelrl+", XLOCB(19,BOFP4
,CBGT
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2949 { "blerl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2950 { "bnglr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2951 { "bnglr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2952 { "bnglr-", XLOCB(19,BOFM4
,CBGT
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2953 { "bnglr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2954 { "bnglr+", XLOCB(19,BOFP4
,CBGT
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2955 { "bngr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2956 { "bnglrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2957 { "bnglrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2958 { "bnglrl-", XLOCB(19,BOFM4
,CBGT
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2959 { "bnglrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2960 { "bnglrl+", XLOCB(19,BOFP4
,CBGT
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2961 { "bngrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2962 { "bnelr", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2963 { "bnelr-", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2964 { "bnelr-", XLOCB(19,BOFM4
,CBEQ
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2965 { "bnelr+", XLOCB(19,BOFP
,CBEQ
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2966 { "bnelr+", XLOCB(19,BOFP4
,CBEQ
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2967 { "bner", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2968 { "bnelrl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2969 { "bnelrl-", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2970 { "bnelrl-", XLOCB(19,BOFM4
,CBEQ
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2971 { "bnelrl+", XLOCB(19,BOFP
,CBEQ
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2972 { "bnelrl+", XLOCB(19,BOFP4
,CBEQ
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2973 { "bnerl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2974 { "bnslr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2975 { "bnslr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2976 { "bnslr-", XLOCB(19,BOFM4
,CBSO
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2977 { "bnslr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2978 { "bnslr+", XLOCB(19,BOFP4
,CBSO
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2979 { "bnsr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2980 { "bnslrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2981 { "bnslrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2982 { "bnslrl-", XLOCB(19,BOFM4
,CBSO
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2983 { "bnslrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2984 { "bnslrl+", XLOCB(19,BOFP4
,CBSO
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2985 { "bnsrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2986 { "bnulr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2987 { "bnulr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2988 { "bnulr-", XLOCB(19,BOFM4
,CBSO
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2989 { "bnulr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2990 { "bnulr+", XLOCB(19,BOFP4
,CBSO
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2991 { "bnulrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2992 { "bnulrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2993 { "bnulrl-", XLOCB(19,BOFM4
,CBSO
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2994 { "bnulrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2995 { "bnulrl+", XLOCB(19,BOFP4
,CBSO
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2996 { "btlr", XLO(19,BOT
,16,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2997 { "btlr-", XLO(19,BOT
,16,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2998 { "btlr-", XLO(19,BOTM4
,16,0), XLBOBB_MASK
, POWER4
, { BI
} },
2999 { "btlr+", XLO(19,BOTP
,16,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3000 { "btlr+", XLO(19,BOTP4
,16,0), XLBOBB_MASK
, POWER4
, { BI
} },
3001 { "bbtr", XLO(19,BOT
,16,0), XLBOBB_MASK
, PWRCOM
, { BI
} },
3002 { "btlrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
3003 { "btlrl-", XLO(19,BOT
,16,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3004 { "btlrl-", XLO(19,BOTM4
,16,1), XLBOBB_MASK
, POWER4
, { BI
} },
3005 { "btlrl+", XLO(19,BOTP
,16,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3006 { "btlrl+", XLO(19,BOTP4
,16,1), XLBOBB_MASK
, POWER4
, { BI
} },
3007 { "bbtrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, PWRCOM
, { BI
} },
3008 { "bflr", XLO(19,BOF
,16,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
3009 { "bflr-", XLO(19,BOF
,16,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3010 { "bflr-", XLO(19,BOFM4
,16,0), XLBOBB_MASK
, POWER4
, { BI
} },
3011 { "bflr+", XLO(19,BOFP
,16,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3012 { "bflr+", XLO(19,BOFP4
,16,0), XLBOBB_MASK
, POWER4
, { BI
} },
3013 { "bbfr", XLO(19,BOF
,16,0), XLBOBB_MASK
, PWRCOM
, { BI
} },
3014 { "bflrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
3015 { "bflrl-", XLO(19,BOF
,16,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3016 { "bflrl-", XLO(19,BOFM4
,16,1), XLBOBB_MASK
, POWER4
, { BI
} },
3017 { "bflrl+", XLO(19,BOFP
,16,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3018 { "bflrl+", XLO(19,BOFP4
,16,1), XLBOBB_MASK
, POWER4
, { BI
} },
3019 { "bbfrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, PWRCOM
, { BI
} },
3020 { "bdnztlr", XLO(19,BODNZT
,16,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
3021 { "bdnztlr-",XLO(19,BODNZT
,16,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3022 { "bdnztlr+",XLO(19,BODNZTP
,16,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3023 { "bdnztlrl",XLO(19,BODNZT
,16,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
3024 { "bdnztlrl-",XLO(19,BODNZT
,16,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3025 { "bdnztlrl+",XLO(19,BODNZTP
,16,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3026 { "bdnzflr", XLO(19,BODNZF
,16,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
3027 { "bdnzflr-",XLO(19,BODNZF
,16,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3028 { "bdnzflr+",XLO(19,BODNZFP
,16,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3029 { "bdnzflrl",XLO(19,BODNZF
,16,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
3030 { "bdnzflrl-",XLO(19,BODNZF
,16,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3031 { "bdnzflrl+",XLO(19,BODNZFP
,16,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3032 { "bdztlr", XLO(19,BODZT
,16,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
3033 { "bdztlr-", XLO(19,BODZT
,16,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3034 { "bdztlr+", XLO(19,BODZTP
,16,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3035 { "bdztlrl", XLO(19,BODZT
,16,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
3036 { "bdztlrl-",XLO(19,BODZT
,16,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3037 { "bdztlrl+",XLO(19,BODZTP
,16,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3038 { "bdzflr", XLO(19,BODZF
,16,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
3039 { "bdzflr-", XLO(19,BODZF
,16,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3040 { "bdzflr+", XLO(19,BODZFP
,16,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3041 { "bdzflrl", XLO(19,BODZF
,16,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
3042 { "bdzflrl-",XLO(19,BODZF
,16,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3043 { "bdzflrl+",XLO(19,BODZFP
,16,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3044 { "bclr+", XLYLK(19,16,1,0), XLYBB_MASK
, PPCCOM
, { BOE
, BI
} },
3045 { "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK
, PPCCOM
, { BOE
, BI
} },
3046 { "bclr-", XLYLK(19,16,0,0), XLYBB_MASK
, PPCCOM
, { BOE
, BI
} },
3047 { "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK
, PPCCOM
, { BOE
, BI
} },
3048 { "bclr", XLLK(19,16,0), XLBH_MASK
, PPCCOM
, { BO
, BI
, BH
} },
3049 { "bclrl", XLLK(19,16,1), XLBH_MASK
, PPCCOM
, { BO
, BI
, BH
} },
3050 { "bcr", XLLK(19,16,0), XLBB_MASK
, PWRCOM
, { BO
, BI
} },
3051 { "bcrl", XLLK(19,16,1), XLBB_MASK
, PWRCOM
, { BO
, BI
} },
3052 { "bclre", XLLK(19,17,0), XLBB_MASK
, BOOKE64
, { BO
, BI
} },
3053 { "bclrel", XLLK(19,17,1), XLBB_MASK
, BOOKE64
, { BO
, BI
} },
3055 { "rfid", XL(19,18), 0xffffffff, PPC64
, { 0 } },
3057 { "crnot", XL(19,33), XL_MASK
, PPCCOM
, { BT
, BA
, BBA
} },
3058 { "crnor", XL(19,33), XL_MASK
, COM
, { BT
, BA
, BB
} },
3059 { "rfmci", X(19,38), 0xffffffff, PPCRFMCI
, { 0 } },
3061 { "rfi", XL(19,50), 0xffffffff, COM
, { 0 } },
3062 { "rfci", XL(19,51), 0xffffffff, PPC403
| BOOKE
, { 0 } },
3064 { "rfsvc", XL(19,82), 0xffffffff, POWER
, { 0 } },
3066 { "crandc", XL(19,129), XL_MASK
, COM
, { BT
, BA
, BB
} },
3068 { "isync", XL(19,150), 0xffffffff, PPCCOM
, { 0 } },
3069 { "ics", XL(19,150), 0xffffffff, PWRCOM
, { 0 } },
3071 { "crclr", XL(19,193), XL_MASK
, PPCCOM
, { BT
, BAT
, BBA
} },
3072 { "crxor", XL(19,193), XL_MASK
, COM
, { BT
, BA
, BB
} },
3074 { "crnand", XL(19,225), XL_MASK
, COM
, { BT
, BA
, BB
} },
3076 { "crand", XL(19,257), XL_MASK
, COM
, { BT
, BA
, BB
} },
3078 { "hrfid", XL(19,274), 0xffffffff, POWER5
| CELL
, { 0 } },
3080 { "crset", XL(19,289), XL_MASK
, PPCCOM
, { BT
, BAT
, BBA
} },
3081 { "creqv", XL(19,289), XL_MASK
, COM
, { BT
, BA
, BB
} },
3083 { "doze", XL(19,402), 0xffffffff, POWER6
, { 0 } },
3085 { "crorc", XL(19,417), XL_MASK
, COM
, { BT
, BA
, BB
} },
3087 { "nap", XL(19,434), 0xffffffff, POWER6
, { 0 } },
3089 { "crmove", XL(19,449), XL_MASK
, PPCCOM
, { BT
, BA
, BBA
} },
3090 { "cror", XL(19,449), XL_MASK
, COM
, { BT
, BA
, BB
} },
3092 { "sleep", XL(19,466), 0xffffffff, POWER6
, { 0 } },
3093 { "rvwinkle", XL(19,498), 0xffffffff, POWER6
, { 0 } },
3095 { "bctr", XLO(19,BOU
,528,0), XLBOBIBB_MASK
, COM
, { 0 } },
3096 { "bctrl", XLO(19,BOU
,528,1), XLBOBIBB_MASK
, COM
, { 0 } },
3097 { "bltctr", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
3098 { "bltctr-", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3099 { "bltctr-", XLOCB(19,BOTM4
,CBLT
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
3100 { "bltctr+", XLOCB(19,BOTP
,CBLT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3101 { "bltctr+", XLOCB(19,BOTP4
,CBLT
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
3102 { "bltctrl", XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
3103 { "bltctrl-",XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3104 { "bltctrl-",XLOCB(19,BOTM4
,CBLT
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
3105 { "bltctrl+",XLOCB(19,BOTP
,CBLT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3106 { "bltctrl+",XLOCB(19,BOTP4
,CBLT
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
3107 { "bgtctr", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
3108 { "bgtctr-", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3109 { "bgtctr-", XLOCB(19,BOTM4
,CBGT
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
3110 { "bgtctr+", XLOCB(19,BOTP
,CBGT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3111 { "bgtctr+", XLOCB(19,BOTP4
,CBGT
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
3112 { "bgtctrl", XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
3113 { "bgtctrl-",XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3114 { "bgtctrl-",XLOCB(19,BOTM4
,CBGT
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
3115 { "bgtctrl+",XLOCB(19,BOTP
,CBGT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3116 { "bgtctrl+",XLOCB(19,BOTP4
,CBGT
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
3117 { "beqctr", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
3118 { "beqctr-", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3119 { "beqctr-", XLOCB(19,BOTM4
,CBEQ
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
3120 { "beqctr+", XLOCB(19,BOTP
,CBEQ
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3121 { "beqctr+", XLOCB(19,BOTP4
,CBEQ
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
3122 { "beqctrl", XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
3123 { "beqctrl-",XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3124 { "beqctrl-",XLOCB(19,BOTM4
,CBEQ
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
3125 { "beqctrl+",XLOCB(19,BOTP
,CBEQ
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3126 { "beqctrl+",XLOCB(19,BOTP4
,CBEQ
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
3127 { "bsoctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
3128 { "bsoctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3129 { "bsoctr-", XLOCB(19,BOTM4
,CBSO
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
3130 { "bsoctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3131 { "bsoctr+", XLOCB(19,BOTP4
,CBSO
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
3132 { "bsoctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
3133 { "bsoctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3134 { "bsoctrl-",XLOCB(19,BOTM4
,CBSO
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
3135 { "bsoctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3136 { "bsoctrl+",XLOCB(19,BOTP4
,CBSO
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
3137 { "bunctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
3138 { "bunctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3139 { "bunctr-", XLOCB(19,BOTM4
,CBSO
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
3140 { "bunctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3141 { "bunctr+", XLOCB(19,BOTP4
,CBSO
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
3142 { "bunctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
3143 { "bunctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3144 { "bunctrl-",XLOCB(19,BOTM4
,CBSO
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
3145 { "bunctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3146 { "bunctrl+",XLOCB(19,BOTP4
,CBSO
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
3147 { "bgectr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
3148 { "bgectr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3149 { "bgectr-", XLOCB(19,BOFM4
,CBLT
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
3150 { "bgectr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3151 { "bgectr+", XLOCB(19,BOFP4
,CBLT
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
3152 { "bgectrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
3153 { "bgectrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3154 { "bgectrl-",XLOCB(19,BOFM4
,CBLT
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
3155 { "bgectrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3156 { "bgectrl+",XLOCB(19,BOFP4
,CBLT
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
3157 { "bnlctr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
3158 { "bnlctr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3159 { "bnlctr-", XLOCB(19,BOFM4
,CBLT
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
3160 { "bnlctr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3161 { "bnlctr+", XLOCB(19,BOFP4
,CBLT
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
3162 { "bnlctrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
3163 { "bnlctrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3164 { "bnlctrl-",XLOCB(19,BOFM4
,CBLT
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
3165 { "bnlctrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3166 { "bnlctrl+",XLOCB(19,BOFP4
,CBLT
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
3167 { "blectr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
3168 { "blectr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3169 { "blectr-", XLOCB(19,BOFM4
,CBGT
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
3170 { "blectr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3171 { "blectr+", XLOCB(19,BOFP4
,CBGT
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
3172 { "blectrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
3173 { "blectrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3174 { "blectrl-",XLOCB(19,BOFM4
,CBGT
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
3175 { "blectrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3176 { "blectrl+",XLOCB(19,BOFP4
,CBGT
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
3177 { "bngctr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
3178 { "bngctr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3179 { "bngctr-", XLOCB(19,BOFM4
,CBGT
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
3180 { "bngctr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3181 { "bngctr+", XLOCB(19,BOFP4
,CBGT
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
3182 { "bngctrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
3183 { "bngctrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3184 { "bngctrl-",XLOCB(19,BOFM4
,CBGT
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
3185 { "bngctrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3186 { "bngctrl+",XLOCB(19,BOFP4
,CBGT
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
3187 { "bnectr", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
3188 { "bnectr-", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3189 { "bnectr-", XLOCB(19,BOFM4
,CBEQ
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
3190 { "bnectr+", XLOCB(19,BOFP
,CBEQ
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3191 { "bnectr+", XLOCB(19,BOFP4
,CBEQ
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
3192 { "bnectrl", XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
3193 { "bnectrl-",XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3194 { "bnectrl-",XLOCB(19,BOFM4
,CBEQ
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
3195 { "bnectrl+",XLOCB(19,BOFP
,CBEQ
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3196 { "bnectrl+",XLOCB(19,BOFP4
,CBEQ
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
3197 { "bnsctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
3198 { "bnsctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3199 { "bnsctr-", XLOCB(19,BOFM4
,CBSO
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
3200 { "bnsctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3201 { "bnsctr+", XLOCB(19,BOFP4
,CBSO
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
3202 { "bnsctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
3203 { "bnsctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3204 { "bnsctrl-",XLOCB(19,BOFM4
,CBSO
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
3205 { "bnsctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3206 { "bnsctrl+",XLOCB(19,BOFP4
,CBSO
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
3207 { "bnuctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
3208 { "bnuctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3209 { "bnuctr-", XLOCB(19,BOFM4
,CBSO
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
3210 { "bnuctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3211 { "bnuctr+", XLOCB(19,BOFP4
,CBSO
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
3212 { "bnuctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
3213 { "bnuctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3214 { "bnuctrl-",XLOCB(19,BOFM4
,CBSO
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
3215 { "bnuctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
3216 { "bnuctrl+",XLOCB(19,BOFP4
,CBSO
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
3217 { "btctr", XLO(19,BOT
,528,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
3218 { "btctr-", XLO(19,BOT
,528,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3219 { "btctr-", XLO(19,BOTM4
,528,0), XLBOBB_MASK
, POWER4
, { BI
} },
3220 { "btctr+", XLO(19,BOTP
,528,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3221 { "btctr+", XLO(19,BOTP4
,528,0), XLBOBB_MASK
, POWER4
, { BI
} },
3222 { "btctrl", XLO(19,BOT
,528,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
3223 { "btctrl-", XLO(19,BOT
,528,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3224 { "btctrl-", XLO(19,BOTM4
,528,1), XLBOBB_MASK
, POWER4
, { BI
} },
3225 { "btctrl+", XLO(19,BOTP
,528,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3226 { "btctrl+", XLO(19,BOTP4
,528,1), XLBOBB_MASK
, POWER4
, { BI
} },
3227 { "bfctr", XLO(19,BOF
,528,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
3228 { "bfctr-", XLO(19,BOF
,528,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3229 { "bfctr-", XLO(19,BOFM4
,528,0), XLBOBB_MASK
, POWER4
, { BI
} },
3230 { "bfctr+", XLO(19,BOFP
,528,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3231 { "bfctr+", XLO(19,BOFP4
,528,0), XLBOBB_MASK
, POWER4
, { BI
} },
3232 { "bfctrl", XLO(19,BOF
,528,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
3233 { "bfctrl-", XLO(19,BOF
,528,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3234 { "bfctrl-", XLO(19,BOFM4
,528,1), XLBOBB_MASK
, POWER4
, { BI
} },
3235 { "bfctrl+", XLO(19,BOFP
,528,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
3236 { "bfctrl+", XLO(19,BOFP4
,528,1), XLBOBB_MASK
, POWER4
, { BI
} },
3237 { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK
, PPCCOM
, { BOE
, BI
} },
3238 { "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK
, PPCCOM
, { BOE
, BI
} },
3239 { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK
, PPCCOM
, { BOE
, BI
} },
3240 { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK
, PPCCOM
, { BOE
, BI
} },
3241 { "bcctr", XLLK(19,528,0), XLBH_MASK
, PPCCOM
, { BO
, BI
, BH
} },
3242 { "bcctrl", XLLK(19,528,1), XLBH_MASK
, PPCCOM
, { BO
, BI
, BH
} },
3243 { "bcc", XLLK(19,528,0), XLBB_MASK
, PWRCOM
, { BO
, BI
} },
3244 { "bccl", XLLK(19,528,1), XLBB_MASK
, PWRCOM
, { BO
, BI
} },
3245 { "bcctre", XLLK(19,529,0), XLYBB_MASK
, BOOKE64
, { BO
, BI
} },
3246 { "bcctrel", XLLK(19,529,1), XLYBB_MASK
, BOOKE64
, { BO
, BI
} },
3248 { "rlwimi", M(20,0), M_MASK
, PPCCOM
, { RA
,RS
,SH
,MBE
,ME
} },
3249 { "rlimi", M(20,0), M_MASK
, PWRCOM
, { RA
,RS
,SH
,MBE
,ME
} },
3251 { "rlwimi.", M(20,1), M_MASK
, PPCCOM
, { RA
,RS
,SH
,MBE
,ME
} },
3252 { "rlimi.", M(20,1), M_MASK
, PWRCOM
, { RA
,RS
,SH
,MBE
,ME
} },
3254 { "rotlwi", MME(21,31,0), MMBME_MASK
, PPCCOM
, { RA
, RS
, SH
} },
3255 { "clrlwi", MME(21,31,0), MSHME_MASK
, PPCCOM
, { RA
, RS
, MB
} },
3256 { "rlwinm", M(21,0), M_MASK
, PPCCOM
, { RA
,RS
,SH
,MBE
,ME
} },
3257 { "rlinm", M(21,0), M_MASK
, PWRCOM
, { RA
,RS
,SH
,MBE
,ME
} },
3258 { "rotlwi.", MME(21,31,1), MMBME_MASK
, PPCCOM
, { RA
,RS
,SH
} },
3259 { "clrlwi.", MME(21,31,1), MSHME_MASK
, PPCCOM
, { RA
, RS
, MB
} },
3260 { "rlwinm.", M(21,1), M_MASK
, PPCCOM
, { RA
,RS
,SH
,MBE
,ME
} },
3261 { "rlinm.", M(21,1), M_MASK
, PWRCOM
, { RA
,RS
,SH
,MBE
,ME
} },
3263 { "rlmi", M(22,0), M_MASK
, M601
, { RA
,RS
,RB
,MBE
,ME
} },
3264 { "rlmi.", M(22,1), M_MASK
, M601
, { RA
,RS
,RB
,MBE
,ME
} },
3266 { "be", B(22,0,0), B_MASK
, BOOKE64
, { LI
} },
3267 { "bel", B(22,0,1), B_MASK
, BOOKE64
, { LI
} },
3268 { "bea", B(22,1,0), B_MASK
, BOOKE64
, { LIA
} },
3269 { "bela", B(22,1,1), B_MASK
, BOOKE64
, { LIA
} },
3271 { "rotlw", MME(23,31,0), MMBME_MASK
, PPCCOM
, { RA
, RS
, RB
} },
3272 { "rlwnm", M(23,0), M_MASK
, PPCCOM
, { RA
,RS
,RB
,MBE
,ME
} },
3273 { "rlnm", M(23,0), M_MASK
, PWRCOM
, { RA
,RS
,RB
,MBE
,ME
} },
3274 { "rotlw.", MME(23,31,1), MMBME_MASK
, PPCCOM
, { RA
, RS
, RB
} },
3275 { "rlwnm.", M(23,1), M_MASK
, PPCCOM
, { RA
,RS
,RB
,MBE
,ME
} },
3276 { "rlnm.", M(23,1), M_MASK
, PWRCOM
, { RA
,RS
,RB
,MBE
,ME
} },
3278 { "nop", OP(24), 0xffffffff, PPCCOM
, { 0 } },
3279 { "ori", OP(24), OP_MASK
, PPCCOM
, { RA
, RS
, UI
} },
3280 { "oril", OP(24), OP_MASK
, PWRCOM
, { RA
, RS
, UI
} },
3282 { "oris", OP(25), OP_MASK
, PPCCOM
, { RA
, RS
, UI
} },
3283 { "oriu", OP(25), OP_MASK
, PWRCOM
, { RA
, RS
, UI
} },
3285 { "xori", OP(26), OP_MASK
, PPCCOM
, { RA
, RS
, UI
} },
3286 { "xoril", OP(26), OP_MASK
, PWRCOM
, { RA
, RS
, UI
} },
3288 { "xoris", OP(27), OP_MASK
, PPCCOM
, { RA
, RS
, UI
} },
3289 { "xoriu", OP(27), OP_MASK
, PWRCOM
, { RA
, RS
, UI
} },
3291 { "andi.", OP(28), OP_MASK
, PPCCOM
, { RA
, RS
, UI
} },
3292 { "andil.", OP(28), OP_MASK
, PWRCOM
, { RA
, RS
, UI
} },
3294 { "andis.", OP(29), OP_MASK
, PPCCOM
, { RA
, RS
, UI
} },
3295 { "andiu.", OP(29), OP_MASK
, PWRCOM
, { RA
, RS
, UI
} },
3297 { "rotldi", MD(30,0,0), MDMB_MASK
, PPC64
, { RA
, RS
, SH6
} },
3298 { "clrldi", MD(30,0,0), MDSH_MASK
, PPC64
, { RA
, RS
, MB6
} },
3299 { "rldicl", MD(30,0,0), MD_MASK
, PPC64
, { RA
, RS
, SH6
, MB6
} },
3300 { "rotldi.", MD(30,0,1), MDMB_MASK
, PPC64
, { RA
, RS
, SH6
} },
3301 { "clrldi.", MD(30,0,1), MDSH_MASK
, PPC64
, { RA
, RS
, MB6
} },
3302 { "rldicl.", MD(30,0,1), MD_MASK
, PPC64
, { RA
, RS
, SH6
, MB6
} },
3304 { "rldicr", MD(30,1,0), MD_MASK
, PPC64
, { RA
, RS
, SH6
, ME6
} },
3305 { "rldicr.", MD(30,1,1), MD_MASK
, PPC64
, { RA
, RS
, SH6
, ME6
} },
3307 { "rldic", MD(30,2,0), MD_MASK
, PPC64
, { RA
, RS
, SH6
, MB6
} },
3308 { "rldic.", MD(30,2,1), MD_MASK
, PPC64
, { RA
, RS
, SH6
, MB6
} },
3310 { "rldimi", MD(30,3,0), MD_MASK
, PPC64
, { RA
, RS
, SH6
, MB6
} },
3311 { "rldimi.", MD(30,3,1), MD_MASK
, PPC64
, { RA
, RS
, SH6
, MB6
} },
3313 { "rotld", MDS(30,8,0), MDSMB_MASK
, PPC64
, { RA
, RS
, RB
} },
3314 { "rldcl", MDS(30,8,0), MDS_MASK
, PPC64
, { RA
, RS
, RB
, MB6
} },
3315 { "rotld.", MDS(30,8,1), MDSMB_MASK
, PPC64
, { RA
, RS
, RB
} },
3316 { "rldcl.", MDS(30,8,1), MDS_MASK
, PPC64
, { RA
, RS
, RB
, MB6
} },
3318 { "rldcr", MDS(30,9,0), MDS_MASK
, PPC64
, { RA
, RS
, RB
, ME6
} },
3319 { "rldcr.", MDS(30,9,1), MDS_MASK
, PPC64
, { RA
, RS
, RB
, ME6
} },
3321 { "cmpw", XOPL(31,0,0), XCMPL_MASK
, PPCCOM
, { OBF
, RA
, RB
} },
3322 { "cmpd", XOPL(31,0,1), XCMPL_MASK
, PPC64
, { OBF
, RA
, RB
} },
3323 { "cmp", X(31,0), XCMP_MASK
, PPC
, { BF
, L
, RA
, RB
} },
3324 { "cmp", X(31,0), XCMPL_MASK
, PWRCOM
, { BF
, RA
, RB
} },
3326 { "twlgt", XTO(31,4,TOLGT
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
3327 { "tlgt", XTO(31,4,TOLGT
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
3328 { "twllt", XTO(31,4,TOLLT
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
3329 { "tllt", XTO(31,4,TOLLT
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
3330 { "tweq", XTO(31,4,TOEQ
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
3331 { "teq", XTO(31,4,TOEQ
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
3332 { "twlge", XTO(31,4,TOLGE
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
3333 { "tlge", XTO(31,4,TOLGE
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
3334 { "twlnl", XTO(31,4,TOLNL
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
3335 { "tlnl", XTO(31,4,TOLNL
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
3336 { "twlle", XTO(31,4,TOLLE
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
3337 { "tlle", XTO(31,4,TOLLE
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
3338 { "twlng", XTO(31,4,TOLNG
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
3339 { "tlng", XTO(31,4,TOLNG
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
3340 { "twgt", XTO(31,4,TOGT
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
3341 { "tgt", XTO(31,4,TOGT
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
3342 { "twge", XTO(31,4,TOGE
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
3343 { "tge", XTO(31,4,TOGE
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
3344 { "twnl", XTO(31,4,TONL
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
3345 { "tnl", XTO(31,4,TONL
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
3346 { "twlt", XTO(31,4,TOLT
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
3347 { "tlt", XTO(31,4,TOLT
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
3348 { "twle", XTO(31,4,TOLE
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
3349 { "tle", XTO(31,4,TOLE
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
3350 { "twng", XTO(31,4,TONG
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
3351 { "tng", XTO(31,4,TONG
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
3352 { "twne", XTO(31,4,TONE
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
3353 { "tne", XTO(31,4,TONE
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
3354 { "trap", XTO(31,4,TOU
), 0xffffffff, PPCCOM
, { 0 } },
3355 { "tw", X(31,4), X_MASK
, PPCCOM
, { TO
, RA
, RB
} },
3356 { "t", X(31,4), X_MASK
, PWRCOM
, { TO
, RA
, RB
} },
3358 { "subfc", XO(31,8,0,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3359 { "sf", XO(31,8,0,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3360 { "subc", XO(31,8,0,0), XO_MASK
, PPC
, { RT
, RB
, RA
} },
3361 { "subfc.", XO(31,8,0,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3362 { "sf.", XO(31,8,0,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3363 { "subc.", XO(31,8,0,1), XO_MASK
, PPCCOM
, { RT
, RB
, RA
} },
3364 { "subfco", XO(31,8,1,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3365 { "sfo", XO(31,8,1,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3366 { "subco", XO(31,8,1,0), XO_MASK
, PPC
, { RT
, RB
, RA
} },
3367 { "subfco.", XO(31,8,1,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3368 { "sfo.", XO(31,8,1,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3369 { "subco.", XO(31,8,1,1), XO_MASK
, PPC
, { RT
, RB
, RA
} },
3371 { "mulhdu", XO(31,9,0,0), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
3372 { "mulhdu.", XO(31,9,0,1), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
3374 { "addc", XO(31,10,0,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3375 { "a", XO(31,10,0,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3376 { "addc.", XO(31,10,0,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3377 { "a.", XO(31,10,0,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3378 { "addco", XO(31,10,1,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3379 { "ao", XO(31,10,1,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3380 { "addco.", XO(31,10,1,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3381 { "ao.", XO(31,10,1,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3383 { "mulhwu", XO(31,11,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
3384 { "mulhwu.", XO(31,11,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
3386 { "isellt", X(31,15), X_MASK
, PPCISEL
, { RT
, RA
, RB
} },
3387 { "iselgt", X(31,47), X_MASK
, PPCISEL
, { RT
, RA
, RB
} },
3388 { "iseleq", X(31,79), X_MASK
, PPCISEL
, { RT
, RA
, RB
} },
3389 { "isel", XISEL(31,15), XISEL_MASK
, PPCISEL
, { RT
, RA
, RB
, CRB
} },
3391 { "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK
, COM
, { RT
, FXM
} },
3392 { "mfcr", X(31,19), XRARB_MASK
, NOPOWER4
| COM
, { RT
} },
3393 { "mfcr", X(31,19), XFXFXM_MASK
, POWER4
, { RT
, FXM4
} },
3395 { "lwarx", X(31,20), XEH_MASK
, PPC
, { RT
, RA0
, RB
, EH
} },
3397 { "ldx", X(31,21), X_MASK
, PPC64
, { RT
, RA0
, RB
} },
3399 { "icbt", X(31,22), X_MASK
, BOOKE
|PPCE300
, { CT
, RA
, RB
} },
3400 { "icbt", X(31,262), XRT_MASK
, PPC403
, { RA
, RB
} },
3402 { "lwzx", X(31,23), X_MASK
, PPCCOM
, { RT
, RA0
, RB
} },
3403 { "lx", X(31,23), X_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3405 { "slw", XRC(31,24,0), X_MASK
, PPCCOM
, { RA
, RS
, RB
} },
3406 { "sl", XRC(31,24,0), X_MASK
, PWRCOM
, { RA
, RS
, RB
} },
3407 { "slw.", XRC(31,24,1), X_MASK
, PPCCOM
, { RA
, RS
, RB
} },
3408 { "sl.", XRC(31,24,1), X_MASK
, PWRCOM
, { RA
, RS
, RB
} },
3410 { "cntlzw", XRC(31,26,0), XRB_MASK
, PPCCOM
, { RA
, RS
} },
3411 { "cntlz", XRC(31,26,0), XRB_MASK
, PWRCOM
, { RA
, RS
} },
3412 { "cntlzw.", XRC(31,26,1), XRB_MASK
, PPCCOM
, { RA
, RS
} },
3413 { "cntlz.", XRC(31,26,1), XRB_MASK
, PWRCOM
, { RA
, RS
} },
3415 { "sld", XRC(31,27,0), X_MASK
, PPC64
, { RA
, RS
, RB
} },
3416 { "sld.", XRC(31,27,1), X_MASK
, PPC64
, { RA
, RS
, RB
} },
3418 { "and", XRC(31,28,0), X_MASK
, COM
, { RA
, RS
, RB
} },
3419 { "and.", XRC(31,28,1), X_MASK
, COM
, { RA
, RS
, RB
} },
3421 { "maskg", XRC(31,29,0), X_MASK
, M601
, { RA
, RS
, RB
} },
3422 { "maskg.", XRC(31,29,1), X_MASK
, M601
, { RA
, RS
, RB
} },
3424 { "icbte", X(31,30), X_MASK
, BOOKE64
, { CT
, RA
, RB
} },
3426 { "lwzxe", X(31,31), X_MASK
, BOOKE64
, { RT
, RA0
, RB
} },
3428 { "cmplw", XOPL(31,32,0), XCMPL_MASK
, PPCCOM
, { OBF
, RA
, RB
} },
3429 { "cmpld", XOPL(31,32,1), XCMPL_MASK
, PPC64
, { OBF
, RA
, RB
} },
3430 { "cmpl", X(31,32), XCMP_MASK
, PPC
, { BF
, L
, RA
, RB
} },
3431 { "cmpl", X(31,32), XCMPL_MASK
, PWRCOM
, { BF
, RA
, RB
} },
3433 { "subf", XO(31,40,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
3434 { "sub", XO(31,40,0,0), XO_MASK
, PPC
, { RT
, RB
, RA
} },
3435 { "subf.", XO(31,40,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
3436 { "sub.", XO(31,40,0,1), XO_MASK
, PPC
, { RT
, RB
, RA
} },
3437 { "subfo", XO(31,40,1,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
3438 { "subo", XO(31,40,1,0), XO_MASK
, PPC
, { RT
, RB
, RA
} },
3439 { "subfo.", XO(31,40,1,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
3440 { "subo.", XO(31,40,1,1), XO_MASK
, PPC
, { RT
, RB
, RA
} },
3442 { "ldux", X(31,53), X_MASK
, PPC64
, { RT
, RAL
, RB
} },
3444 { "dcbst", X(31,54), XRT_MASK
, PPC
, { RA
, RB
} },
3446 { "lwzux", X(31,55), X_MASK
, PPCCOM
, { RT
, RAL
, RB
} },
3447 { "lux", X(31,55), X_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3449 { "dcbste", X(31,62), XRT_MASK
, BOOKE64
, { RA
, RB
} },
3451 { "lwzuxe", X(31,63), X_MASK
, BOOKE64
, { RT
, RAL
, RB
} },
3453 { "cntlzd", XRC(31,58,0), XRB_MASK
, PPC64
, { RA
, RS
} },
3454 { "cntlzd.", XRC(31,58,1), XRB_MASK
, PPC64
, { RA
, RS
} },
3456 { "andc", XRC(31,60,0), X_MASK
, COM
, { RA
, RS
, RB
} },
3457 { "andc.", XRC(31,60,1), X_MASK
, COM
, { RA
, RS
, RB
} },
3459 { "tdlgt", XTO(31,68,TOLGT
), XTO_MASK
, PPC64
, { RA
, RB
} },
3460 { "tdllt", XTO(31,68,TOLLT
), XTO_MASK
, PPC64
, { RA
, RB
} },
3461 { "tdeq", XTO(31,68,TOEQ
), XTO_MASK
, PPC64
, { RA
, RB
} },
3462 { "tdlge", XTO(31,68,TOLGE
), XTO_MASK
, PPC64
, { RA
, RB
} },
3463 { "tdlnl", XTO(31,68,TOLNL
), XTO_MASK
, PPC64
, { RA
, RB
} },
3464 { "tdlle", XTO(31,68,TOLLE
), XTO_MASK
, PPC64
, { RA
, RB
} },
3465 { "tdlng", XTO(31,68,TOLNG
), XTO_MASK
, PPC64
, { RA
, RB
} },
3466 { "tdgt", XTO(31,68,TOGT
), XTO_MASK
, PPC64
, { RA
, RB
} },
3467 { "tdge", XTO(31,68,TOGE
), XTO_MASK
, PPC64
, { RA
, RB
} },
3468 { "tdnl", XTO(31,68,TONL
), XTO_MASK
, PPC64
, { RA
, RB
} },
3469 { "tdlt", XTO(31,68,TOLT
), XTO_MASK
, PPC64
, { RA
, RB
} },
3470 { "tdle", XTO(31,68,TOLE
), XTO_MASK
, PPC64
, { RA
, RB
} },
3471 { "tdng", XTO(31,68,TONG
), XTO_MASK
, PPC64
, { RA
, RB
} },
3472 { "tdne", XTO(31,68,TONE
), XTO_MASK
, PPC64
, { RA
, RB
} },
3473 { "td", X(31,68), X_MASK
, PPC64
, { TO
, RA
, RB
} },
3475 { "mulhd", XO(31,73,0,0), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
3476 { "mulhd.", XO(31,73,0,1), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
3478 { "mulhw", XO(31,75,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
3479 { "mulhw.", XO(31,75,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
3481 { "dlmzb", XRC(31,78,0), X_MASK
, PPC403
|PPC440
, { RA
, RS
, RB
} },
3482 { "dlmzb.", XRC(31,78,1), X_MASK
, PPC403
|PPC440
, { RA
, RS
, RB
} },
3484 { "mtsrd", X(31,82), XRB_MASK
|(1<<20), PPC64
, { SR
, RS
} },
3486 { "mfmsr", X(31,83), XRARB_MASK
, COM
, { RT
} },
3488 { "ldarx", X(31,84), XEH_MASK
, PPC64
, { RT
, RA0
, RB
, EH
} },
3490 { "dcbfl", XOPL(31,86,1), XRT_MASK
, POWER5
, { RA
, RB
} },
3491 { "dcbf", X(31,86), XLRT_MASK
, PPC
, { RA
, RB
, XRT_L
} },
3493 { "lbzx", X(31,87), X_MASK
, COM
, { RT
, RA0
, RB
} },
3495 { "dcbfe", X(31,94), XRT_MASK
, BOOKE64
, { RA
, RB
} },
3497 { "lbzxe", X(31,95), X_MASK
, BOOKE64
, { RT
, RA0
, RB
} },
3499 { "neg", XO(31,104,0,0), XORB_MASK
, COM
, { RT
, RA
} },
3500 { "neg.", XO(31,104,0,1), XORB_MASK
, COM
, { RT
, RA
} },
3501 { "nego", XO(31,104,1,0), XORB_MASK
, COM
, { RT
, RA
} },
3502 { "nego.", XO(31,104,1,1), XORB_MASK
, COM
, { RT
, RA
} },
3504 { "mul", XO(31,107,0,0), XO_MASK
, M601
, { RT
, RA
, RB
} },
3505 { "mul.", XO(31,107,0,1), XO_MASK
, M601
, { RT
, RA
, RB
} },
3506 { "mulo", XO(31,107,1,0), XO_MASK
, M601
, { RT
, RA
, RB
} },
3507 { "mulo.", XO(31,107,1,1), XO_MASK
, M601
, { RT
, RA
, RB
} },
3509 { "mtsrdin", X(31,114), XRA_MASK
, PPC64
, { RS
, RB
} },
3511 { "clf", X(31,118), XTO_MASK
, POWER
, { RA
, RB
} },
3513 { "lbzux", X(31,119), X_MASK
, COM
, { RT
, RAL
, RB
} },
3515 { "popcntb", X(31,122), XRB_MASK
, POWER5
, { RA
, RS
} },
3517 { "not", XRC(31,124,0), X_MASK
, COM
, { RA
, RS
, RBS
} },
3518 { "nor", XRC(31,124,0), X_MASK
, COM
, { RA
, RS
, RB
} },
3519 { "not.", XRC(31,124,1), X_MASK
, COM
, { RA
, RS
, RBS
} },
3520 { "nor.", XRC(31,124,1), X_MASK
, COM
, { RA
, RS
, RB
} },
3522 { "lwarxe", X(31,126), X_MASK
, BOOKE64
, { RT
, RA0
, RB
} },
3524 { "lbzuxe", X(31,127), X_MASK
, BOOKE64
, { RT
, RAL
, RB
} },
3526 { "wrtee", X(31,131), XRARB_MASK
, PPC403
| BOOKE
, { RS
} },
3528 { "dcbtstls",X(31,134), X_MASK
, PPCCHLK
, { CT
, RA
, RB
}},
3530 { "subfe", XO(31,136,0,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3531 { "sfe", XO(31,136,0,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3532 { "subfe.", XO(31,136,0,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3533 { "sfe.", XO(31,136,0,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3534 { "subfeo", XO(31,136,1,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3535 { "sfeo", XO(31,136,1,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3536 { "subfeo.", XO(31,136,1,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3537 { "sfeo.", XO(31,136,1,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3539 { "adde", XO(31,138,0,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3540 { "ae", XO(31,138,0,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3541 { "adde.", XO(31,138,0,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3542 { "ae.", XO(31,138,0,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3543 { "addeo", XO(31,138,1,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3544 { "aeo", XO(31,138,1,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3545 { "addeo.", XO(31,138,1,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3546 { "aeo.", XO(31,138,1,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3548 { "dcbtstlse",X(31,142),X_MASK
, PPCCHLK64
, { CT
, RA
, RB
}},
3550 { "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK
, COM
, { FXM
, RS
} },
3551 { "mtcr", XFXM(31,144,0xff,0), XRARB_MASK
, COM
, { RS
}},
3552 { "mtcrf", X(31,144), XFXFXM_MASK
, COM
, { FXM
, RS
} },
3554 { "mtmsr", X(31,146), XRARB_MASK
, COM
, { RS
} },
3556 { "stdx", X(31,149), X_MASK
, PPC64
, { RS
, RA0
, RB
} },
3558 { "stwcx.", XRC(31,150,1), X_MASK
, PPC
, { RS
, RA0
, RB
} },
3560 { "stwx", X(31,151), X_MASK
, PPCCOM
, { RS
, RA0
, RB
} },
3561 { "stx", X(31,151), X_MASK
, PWRCOM
, { RS
, RA
, RB
} },
3563 { "stwcxe.", XRC(31,158,1), X_MASK
, BOOKE64
, { RS
, RA0
, RB
} },
3565 { "stwxe", X(31,159), X_MASK
, BOOKE64
, { RS
, RA0
, RB
} },
3567 { "slq", XRC(31,152,0), X_MASK
, M601
, { RA
, RS
, RB
} },
3568 { "slq.", XRC(31,152,1), X_MASK
, M601
, { RA
, RS
, RB
} },
3570 { "sle", XRC(31,153,0), X_MASK
, M601
, { RA
, RS
, RB
} },
3571 { "sle.", XRC(31,153,1), X_MASK
, M601
, { RA
, RS
, RB
} },
3573 { "prtyw", X(31,154), XRB_MASK
, POWER6
, { RA
, RS
} },
3575 { "wrteei", X(31,163), XE_MASK
, PPC403
| BOOKE
, { E
} },
3577 { "dcbtls", X(31,166), X_MASK
, PPCCHLK
, { CT
, RA
, RB
}},
3578 { "dcbtlse", X(31,174), X_MASK
, PPCCHLK64
, { CT
, RA
, RB
}},
3580 { "mtmsrd", X(31,178), XRLARB_MASK
, PPC64
, { RS
, MTMSRD_L
} },
3582 { "stdux", X(31,181), X_MASK
, PPC64
, { RS
, RAS
, RB
} },
3584 { "stwux", X(31,183), X_MASK
, PPCCOM
, { RS
, RAS
, RB
} },
3585 { "stux", X(31,183), X_MASK
, PWRCOM
, { RS
, RA0
, RB
} },
3587 { "sliq", XRC(31,184,0), X_MASK
, M601
, { RA
, RS
, SH
} },
3588 { "sliq.", XRC(31,184,1), X_MASK
, M601
, { RA
, RS
, SH
} },
3590 { "prtyd", X(31,186), XRB_MASK
, POWER6
, { RA
, RS
} },
3592 { "stwuxe", X(31,191), X_MASK
, BOOKE64
, { RS
, RAS
, RB
} },
3594 { "subfze", XO(31,200,0,0), XORB_MASK
, PPCCOM
, { RT
, RA
} },
3595 { "sfze", XO(31,200,0,0), XORB_MASK
, PWRCOM
, { RT
, RA
} },
3596 { "subfze.", XO(31,200,0,1), XORB_MASK
, PPCCOM
, { RT
, RA
} },
3597 { "sfze.", XO(31,200,0,1), XORB_MASK
, PWRCOM
, { RT
, RA
} },
3598 { "subfzeo", XO(31,200,1,0), XORB_MASK
, PPCCOM
, { RT
, RA
} },
3599 { "sfzeo", XO(31,200,1,0), XORB_MASK
, PWRCOM
, { RT
, RA
} },
3600 { "subfzeo.",XO(31,200,1,1), XORB_MASK
, PPCCOM
, { RT
, RA
} },
3601 { "sfzeo.", XO(31,200,1,1), XORB_MASK
, PWRCOM
, { RT
, RA
} },
3603 { "addze", XO(31,202,0,0), XORB_MASK
, PPCCOM
, { RT
, RA
} },
3604 { "aze", XO(31,202,0,0), XORB_MASK
, PWRCOM
, { RT
, RA
} },
3605 { "addze.", XO(31,202,0,1), XORB_MASK
, PPCCOM
, { RT
, RA
} },
3606 { "aze.", XO(31,202,0,1), XORB_MASK
, PWRCOM
, { RT
, RA
} },
3607 { "addzeo", XO(31,202,1,0), XORB_MASK
, PPCCOM
, { RT
, RA
} },
3608 { "azeo", XO(31,202,1,0), XORB_MASK
, PWRCOM
, { RT
, RA
} },
3609 { "addzeo.", XO(31,202,1,1), XORB_MASK
, PPCCOM
, { RT
, RA
} },
3610 { "azeo.", XO(31,202,1,1), XORB_MASK
, PWRCOM
, { RT
, RA
} },
3612 { "mtsr", X(31,210), XRB_MASK
|(1<<20), COM32
, { SR
, RS
} },
3614 { "stdcx.", XRC(31,214,1), X_MASK
, PPC64
, { RS
, RA0
, RB
} },
3616 { "stbx", X(31,215), X_MASK
, COM
, { RS
, RA0
, RB
} },
3618 { "sllq", XRC(31,216,0), X_MASK
, M601
, { RA
, RS
, RB
} },
3619 { "sllq.", XRC(31,216,1), X_MASK
, M601
, { RA
, RS
, RB
} },
3621 { "sleq", XRC(31,217,0), X_MASK
, M601
, { RA
, RS
, RB
} },
3622 { "sleq.", XRC(31,217,1), X_MASK
, M601
, { RA
, RS
, RB
} },
3624 { "stbxe", X(31,223), X_MASK
, BOOKE64
, { RS
, RA0
, RB
} },
3626 { "icblc", X(31,230), X_MASK
, PPCCHLK
, { CT
, RA
, RB
}},
3628 { "subfme", XO(31,232,0,0), XORB_MASK
, PPCCOM
, { RT
, RA
} },
3629 { "sfme", XO(31,232,0,0), XORB_MASK
, PWRCOM
, { RT
, RA
} },
3630 { "subfme.", XO(31,232,0,1), XORB_MASK
, PPCCOM
, { RT
, RA
} },
3631 { "sfme.", XO(31,232,0,1), XORB_MASK
, PWRCOM
, { RT
, RA
} },
3632 { "subfmeo", XO(31,232,1,0), XORB_MASK
, PPCCOM
, { RT
, RA
} },
3633 { "sfmeo", XO(31,232,1,0), XORB_MASK
, PWRCOM
, { RT
, RA
} },
3634 { "subfmeo.",XO(31,232,1,1), XORB_MASK
, PPCCOM
, { RT
, RA
} },
3635 { "sfmeo.", XO(31,232,1,1), XORB_MASK
, PWRCOM
, { RT
, RA
} },
3637 { "mulld", XO(31,233,0,0), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
3638 { "mulld.", XO(31,233,0,1), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
3639 { "mulldo", XO(31,233,1,0), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
3640 { "mulldo.", XO(31,233,1,1), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
3642 { "addme", XO(31,234,0,0), XORB_MASK
, PPCCOM
, { RT
, RA
} },
3643 { "ame", XO(31,234,0,0), XORB_MASK
, PWRCOM
, { RT
, RA
} },
3644 { "addme.", XO(31,234,0,1), XORB_MASK
, PPCCOM
, { RT
, RA
} },
3645 { "ame.", XO(31,234,0,1), XORB_MASK
, PWRCOM
, { RT
, RA
} },
3646 { "addmeo", XO(31,234,1,0), XORB_MASK
, PPCCOM
, { RT
, RA
} },
3647 { "ameo", XO(31,234,1,0), XORB_MASK
, PWRCOM
, { RT
, RA
} },
3648 { "addmeo.", XO(31,234,1,1), XORB_MASK
, PPCCOM
, { RT
, RA
} },
3649 { "ameo.", XO(31,234,1,1), XORB_MASK
, PWRCOM
, { RT
, RA
} },
3651 { "mullw", XO(31,235,0,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3652 { "muls", XO(31,235,0,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3653 { "mullw.", XO(31,235,0,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3654 { "muls.", XO(31,235,0,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3655 { "mullwo", XO(31,235,1,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3656 { "mulso", XO(31,235,1,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3657 { "mullwo.", XO(31,235,1,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3658 { "mulso.", XO(31,235,1,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3660 { "icblce", X(31,238), X_MASK
, PPCCHLK64
, { CT
, RA
, RB
}},
3661 { "mtsrin", X(31,242), XRA_MASK
, PPC32
, { RS
, RB
} },
3662 { "mtsri", X(31,242), XRA_MASK
, POWER32
, { RS
, RB
} },
3664 { "dcbtst", X(31,246), X_MASK
, PPC
, { CT
, RA
, RB
} },
3666 { "stbux", X(31,247), X_MASK
, COM
, { RS
, RAS
, RB
} },
3668 { "slliq", XRC(31,248,0), X_MASK
, M601
, { RA
, RS
, SH
} },
3669 { "slliq.", XRC(31,248,1), X_MASK
, M601
, { RA
, RS
, SH
} },
3671 { "dcbtste", X(31,253), X_MASK
, BOOKE64
, { CT
, RA
, RB
} },
3673 { "stbuxe", X(31,255), X_MASK
, BOOKE64
, { RS
, RAS
, RB
} },
3675 { "mfdcrx", X(31,259), X_MASK
, BOOKE
, { RS
, RA
} },
3677 { "doz", XO(31,264,0,0), XO_MASK
, M601
, { RT
, RA
, RB
} },
3678 { "doz.", XO(31,264,0,1), XO_MASK
, M601
, { RT
, RA
, RB
} },
3679 { "dozo", XO(31,264,1,0), XO_MASK
, M601
, { RT
, RA
, RB
} },
3680 { "dozo.", XO(31,264,1,1), XO_MASK
, M601
, { RT
, RA
, RB
} },
3682 { "add", XO(31,266,0,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3683 { "cax", XO(31,266,0,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3684 { "add.", XO(31,266,0,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3685 { "cax.", XO(31,266,0,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3686 { "addo", XO(31,266,1,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3687 { "caxo", XO(31,266,1,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3688 { "addo.", XO(31,266,1,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3689 { "caxo.", XO(31,266,1,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3691 { "tlbiel", X(31,274), XRTLRA_MASK
, POWER4
, { RB
, L
} },
3693 { "mfapidi", X(31,275), X_MASK
, BOOKE
, { RT
, RA
} },
3695 { "lscbx", XRC(31,277,0), X_MASK
, M601
, { RT
, RA
, RB
} },
3696 { "lscbx.", XRC(31,277,1), X_MASK
, M601
, { RT
, RA
, RB
} },
3698 { "dcbt", X(31,278), X_MASK
, PPC
, { CT
, RA
, RB
} },
3700 { "lhzx", X(31,279), X_MASK
, COM
, { RT
, RA0
, RB
} },
3702 { "eqv", XRC(31,284,0), X_MASK
, COM
, { RA
, RS
, RB
} },
3703 { "eqv.", XRC(31,284,1), X_MASK
, COM
, { RA
, RS
, RB
} },
3705 { "dcbte", X(31,286), X_MASK
, BOOKE64
, { CT
, RA
, RB
} },
3707 { "lhzxe", X(31,287), X_MASK
, BOOKE64
, { RT
, RA0
, RB
} },
3709 { "tlbie", X(31,306), XRTLRA_MASK
, PPC
, { RB
, L
} },
3710 { "tlbi", X(31,306), XRT_MASK
, POWER
, { RA0
, RB
} },
3712 { "eciwx", X(31,310), X_MASK
, PPC
, { RT
, RA
, RB
} },
3714 { "lhzux", X(31,311), X_MASK
, COM
, { RT
, RAL
, RB
} },
3716 { "xor", XRC(31,316,0), X_MASK
, COM
, { RA
, RS
, RB
} },
3717 { "xor.", XRC(31,316,1), X_MASK
, COM
, { RA
, RS
, RB
} },
3719 { "lhzuxe", X(31,319), X_MASK
, BOOKE64
, { RT
, RAL
, RB
} },
3721 { "mfexisr", XSPR(31,323,64), XSPR_MASK
, PPC403
, { RT
} },
3722 { "mfexier", XSPR(31,323,66), XSPR_MASK
, PPC403
, { RT
} },
3723 { "mfbr0", XSPR(31,323,128), XSPR_MASK
, PPC403
, { RT
} },
3724 { "mfbr1", XSPR(31,323,129), XSPR_MASK
, PPC403
, { RT
} },
3725 { "mfbr2", XSPR(31,323,130), XSPR_MASK
, PPC403
, { RT
} },
3726 { "mfbr3", XSPR(31,323,131), XSPR_MASK
, PPC403
, { RT
} },
3727 { "mfbr4", XSPR(31,323,132), XSPR_MASK
, PPC403
, { RT
} },
3728 { "mfbr5", XSPR(31,323,133), XSPR_MASK
, PPC403
, { RT
} },
3729 { "mfbr6", XSPR(31,323,134), XSPR_MASK
, PPC403
, { RT
} },
3730 { "mfbr7", XSPR(31,323,135), XSPR_MASK
, PPC403
, { RT
} },
3731 { "mfbear", XSPR(31,323,144), XSPR_MASK
, PPC403
, { RT
} },
3732 { "mfbesr", XSPR(31,323,145), XSPR_MASK
, PPC403
, { RT
} },
3733 { "mfiocr", XSPR(31,323,160), XSPR_MASK
, PPC403
, { RT
} },
3734 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK
, PPC403
, { RT
} },
3735 { "mfdmact0", XSPR(31,323,193), XSPR_MASK
, PPC403
, { RT
} },
3736 { "mfdmada0", XSPR(31,323,194), XSPR_MASK
, PPC403
, { RT
} },
3737 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK
, PPC403
, { RT
} },
3738 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK
, PPC403
, { RT
} },
3739 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK
, PPC403
, { RT
} },
3740 { "mfdmact1", XSPR(31,323,201), XSPR_MASK
, PPC403
, { RT
} },
3741 { "mfdmada1", XSPR(31,323,202), XSPR_MASK
, PPC403
, { RT
} },
3742 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK
, PPC403
, { RT
} },
3743 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK
, PPC403
, { RT
} },
3744 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK
, PPC403
, { RT
} },
3745 { "mfdmact2", XSPR(31,323,209), XSPR_MASK
, PPC403
, { RT
} },
3746 { "mfdmada2", XSPR(31,323,210), XSPR_MASK
, PPC403
, { RT
} },
3747 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK
, PPC403
, { RT
} },
3748 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK
, PPC403
, { RT
} },
3749 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK
, PPC403
, { RT
} },
3750 { "mfdmact3", XSPR(31,323,217), XSPR_MASK
, PPC403
, { RT
} },
3751 { "mfdmada3", XSPR(31,323,218), XSPR_MASK
, PPC403
, { RT
} },
3752 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK
, PPC403
, { RT
} },
3753 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK
, PPC403
, { RT
} },
3754 { "mfdmasr", XSPR(31,323,224), XSPR_MASK
, PPC403
, { RT
} },
3755 { "mfdcr", X(31,323), X_MASK
, PPC403
| BOOKE
, { RT
, SPR
} },
3757 { "div", XO(31,331,0,0), XO_MASK
, M601
, { RT
, RA
, RB
} },
3758 { "div.", XO(31,331,0,1), XO_MASK
, M601
, { RT
, RA
, RB
} },
3759 { "divo", XO(31,331,1,0), XO_MASK
, M601
, { RT
, RA
, RB
} },
3760 { "divo.", XO(31,331,1,1), XO_MASK
, M601
, { RT
, RA
, RB
} },
3762 { "mfpmr", X(31,334), X_MASK
, PPCPMR
, { RT
, PMR
}},
3764 { "mfmq", XSPR(31,339,0), XSPR_MASK
, M601
, { RT
} },
3765 { "mfxer", XSPR(31,339,1), XSPR_MASK
, COM
, { RT
} },
3766 { "mfrtcu", XSPR(31,339,4), XSPR_MASK
, COM
, { RT
} },
3767 { "mfrtcl", XSPR(31,339,5), XSPR_MASK
, COM
, { RT
} },
3768 { "mfdec", XSPR(31,339,6), XSPR_MASK
, MFDEC1
, { RT
} },
3769 { "mfdec", XSPR(31,339,22), XSPR_MASK
, MFDEC2
, { RT
} },
3770 { "mflr", XSPR(31,339,8), XSPR_MASK
, COM
, { RT
} },
3771 { "mfctr", XSPR(31,339,9), XSPR_MASK
, COM
, { RT
} },
3772 { "mftid", XSPR(31,339,17), XSPR_MASK
, POWER
, { RT
} },
3773 { "mfdsisr", XSPR(31,339,18), XSPR_MASK
, COM
, { RT
} },
3774 { "mfdar", XSPR(31,339,19), XSPR_MASK
, COM
, { RT
} },
3775 { "mfsdr0", XSPR(31,339,24), XSPR_MASK
, POWER
, { RT
} },
3776 { "mfsdr1", XSPR(31,339,25), XSPR_MASK
, COM
, { RT
} },
3777 { "mfsrr0", XSPR(31,339,26), XSPR_MASK
, COM
, { RT
} },
3778 { "mfsrr1", XSPR(31,339,27), XSPR_MASK
, COM
, { RT
} },
3779 { "mfcfar", XSPR(31,339,28), XSPR_MASK
, POWER6
, { RT
} },
3780 { "mfpid", XSPR(31,339,48), XSPR_MASK
, BOOKE
, { RT
} },
3781 { "mfpid", XSPR(31,339,945), XSPR_MASK
, PPC403
, { RT
} },
3782 { "mfcsrr0", XSPR(31,339,58), XSPR_MASK
, BOOKE
, { RT
} },
3783 { "mfcsrr1", XSPR(31,339,59), XSPR_MASK
, BOOKE
, { RT
} },
3784 { "mfdear", XSPR(31,339,61), XSPR_MASK
, BOOKE
, { RT
} },
3785 { "mfdear", XSPR(31,339,981), XSPR_MASK
, PPC403
, { RT
} },
3786 { "mfesr", XSPR(31,339,62), XSPR_MASK
, BOOKE
, { RT
} },
3787 { "mfesr", XSPR(31,339,980), XSPR_MASK
, PPC403
, { RT
} },
3788 { "mfivpr", XSPR(31,339,63), XSPR_MASK
, BOOKE
, { RT
} },
3789 { "mfcmpa", XSPR(31,339,144), XSPR_MASK
, PPC860
, { RT
} },
3790 { "mfcmpb", XSPR(31,339,145), XSPR_MASK
, PPC860
, { RT
} },
3791 { "mfcmpc", XSPR(31,339,146), XSPR_MASK
, PPC860
, { RT
} },
3792 { "mfcmpd", XSPR(31,339,147), XSPR_MASK
, PPC860
, { RT
} },
3793 { "mficr", XSPR(31,339,148), XSPR_MASK
, PPC860
, { RT
} },
3794 { "mfder", XSPR(31,339,149), XSPR_MASK
, PPC860
, { RT
} },
3795 { "mfcounta", XSPR(31,339,150), XSPR_MASK
, PPC860
, { RT
} },
3796 { "mfcountb", XSPR(31,339,151), XSPR_MASK
, PPC860
, { RT
} },
3797 { "mfcmpe", XSPR(31,339,152), XSPR_MASK
, PPC860
, { RT
} },
3798 { "mfcmpf", XSPR(31,339,153), XSPR_MASK
, PPC860
, { RT
} },
3799 { "mfcmpg", XSPR(31,339,154), XSPR_MASK
, PPC860
, { RT
} },
3800 { "mfcmph", XSPR(31,339,155), XSPR_MASK
, PPC860
, { RT
} },
3801 { "mflctrl1", XSPR(31,339,156), XSPR_MASK
, PPC860
, { RT
} },
3802 { "mflctrl2", XSPR(31,339,157), XSPR_MASK
, PPC860
, { RT
} },
3803 { "mfictrl", XSPR(31,339,158), XSPR_MASK
, PPC860
, { RT
} },
3804 { "mfbar", XSPR(31,339,159), XSPR_MASK
, PPC860
, { RT
} },
3805 { "mfvrsave", XSPR(31,339,256), XSPR_MASK
, PPCVEC
, { RT
} },
3806 { "mfusprg0", XSPR(31,339,256), XSPR_MASK
, BOOKE
, { RT
} },
3807 { "mftb", X(31,371), X_MASK
, CLASSIC
, { RT
, TBR
} },
3808 { "mftb", XSPR(31,339,268), XSPR_MASK
, BOOKE
, { RT
} },
3809 { "mftbl", XSPR(31,371,268), XSPR_MASK
, CLASSIC
, { RT
} },
3810 { "mftbl", XSPR(31,339,268), XSPR_MASK
, BOOKE
, { RT
} },
3811 { "mftbu", XSPR(31,371,269), XSPR_MASK
, CLASSIC
, { RT
} },
3812 { "mftbu", XSPR(31,339,269), XSPR_MASK
, BOOKE
, { RT
} },
3813 { "mfsprg", XSPR(31,339,256), XSPRG_MASK
, PPC
, { RT
, SPRG
} },
3814 { "mfsprg0", XSPR(31,339,272), XSPR_MASK
, PPC
, { RT
} },
3815 { "mfsprg1", XSPR(31,339,273), XSPR_MASK
, PPC
, { RT
} },
3816 { "mfsprg2", XSPR(31,339,274), XSPR_MASK
, PPC
, { RT
} },
3817 { "mfsprg3", XSPR(31,339,275), XSPR_MASK
, PPC
, { RT
} },
3818 { "mfsprg4", XSPR(31,339,260), XSPR_MASK
, PPC405
| BOOKE
, { RT
} },
3819 { "mfsprg5", XSPR(31,339,261), XSPR_MASK
, PPC405
| BOOKE
, { RT
} },
3820 { "mfsprg6", XSPR(31,339,262), XSPR_MASK
, PPC405
| BOOKE
, { RT
} },
3821 { "mfsprg7", XSPR(31,339,263), XSPR_MASK
, PPC405
| BOOKE
, { RT
} },
3822 { "mfasr", XSPR(31,339,280), XSPR_MASK
, PPC64
, { RT
} },
3823 { "mfear", XSPR(31,339,282), XSPR_MASK
, PPC
, { RT
} },
3824 { "mfpir", XSPR(31,339,286), XSPR_MASK
, BOOKE
, { RT
} },
3825 { "mfpvr", XSPR(31,339,287), XSPR_MASK
, PPC
, { RT
} },
3826 { "mfdbsr", XSPR(31,339,304), XSPR_MASK
, BOOKE
, { RT
} },
3827 { "mfdbsr", XSPR(31,339,1008), XSPR_MASK
, PPC403
, { RT
} },
3828 { "mfdbcr0", XSPR(31,339,308), XSPR_MASK
, BOOKE
, { RT
} },
3829 { "mfdbcr0", XSPR(31,339,1010), XSPR_MASK
, PPC405
, { RT
} },
3830 { "mfdbcr1", XSPR(31,339,309), XSPR_MASK
, BOOKE
, { RT
} },
3831 { "mfdbcr1", XSPR(31,339,957), XSPR_MASK
, PPC405
, { RT
} },
3832 { "mfdbcr2", XSPR(31,339,310), XSPR_MASK
, BOOKE
, { RT
} },
3833 { "mfiac1", XSPR(31,339,312), XSPR_MASK
, BOOKE
, { RT
} },
3834 { "mfiac1", XSPR(31,339,1012), XSPR_MASK
, PPC403
, { RT
} },
3835 { "mfiac2", XSPR(31,339,313), XSPR_MASK
, BOOKE
, { RT
} },
3836 { "mfiac2", XSPR(31,339,1013), XSPR_MASK
, PPC403
, { RT
} },
3837 { "mfiac3", XSPR(31,339,314), XSPR_MASK
, BOOKE
, { RT
} },
3838 { "mfiac3", XSPR(31,339,948), XSPR_MASK
, PPC405
, { RT
} },
3839 { "mfiac4", XSPR(31,339,315), XSPR_MASK
, BOOKE
, { RT
} },
3840 { "mfiac4", XSPR(31,339,949), XSPR_MASK
, PPC405
, { RT
} },
3841 { "mfdac1", XSPR(31,339,316), XSPR_MASK
, BOOKE
, { RT
} },
3842 { "mfdac1", XSPR(31,339,1014), XSPR_MASK
, PPC403
, { RT
} },
3843 { "mfdac2", XSPR(31,339,317), XSPR_MASK
, BOOKE
, { RT
} },
3844 { "mfdac2", XSPR(31,339,1015), XSPR_MASK
, PPC403
, { RT
} },
3845 { "mfdvc1", XSPR(31,339,318), XSPR_MASK
, BOOKE
, { RT
} },
3846 { "mfdvc1", XSPR(31,339,950), XSPR_MASK
, PPC405
, { RT
} },
3847 { "mfdvc2", XSPR(31,339,319), XSPR_MASK
, BOOKE
, { RT
} },
3848 { "mfdvc2", XSPR(31,339,951), XSPR_MASK
, PPC405
, { RT
} },
3849 { "mftsr", XSPR(31,339,336), XSPR_MASK
, BOOKE
, { RT
} },
3850 { "mftsr", XSPR(31,339,984), XSPR_MASK
, PPC403
, { RT
} },
3851 { "mftcr", XSPR(31,339,340), XSPR_MASK
, BOOKE
, { RT
} },
3852 { "mftcr", XSPR(31,339,986), XSPR_MASK
, PPC403
, { RT
} },
3853 { "mfivor0", XSPR(31,339,400), XSPR_MASK
, BOOKE
, { RT
} },
3854 { "mfivor1", XSPR(31,339,401), XSPR_MASK
, BOOKE
, { RT
} },
3855 { "mfivor2", XSPR(31,339,402), XSPR_MASK
, BOOKE
, { RT
} },
3856 { "mfivor3", XSPR(31,339,403), XSPR_MASK
, BOOKE
, { RT
} },
3857 { "mfivor4", XSPR(31,339,404), XSPR_MASK
, BOOKE
, { RT
} },
3858 { "mfivor5", XSPR(31,339,405), XSPR_MASK
, BOOKE
, { RT
} },
3859 { "mfivor6", XSPR(31,339,406), XSPR_MASK
, BOOKE
, { RT
} },
3860 { "mfivor7", XSPR(31,339,407), XSPR_MASK
, BOOKE
, { RT
} },
3861 { "mfivor8", XSPR(31,339,408), XSPR_MASK
, BOOKE
, { RT
} },
3862 { "mfivor9", XSPR(31,339,409), XSPR_MASK
, BOOKE
, { RT
} },
3863 { "mfivor10", XSPR(31,339,410), XSPR_MASK
, BOOKE
, { RT
} },
3864 { "mfivor11", XSPR(31,339,411), XSPR_MASK
, BOOKE
, { RT
} },
3865 { "mfivor12", XSPR(31,339,412), XSPR_MASK
, BOOKE
, { RT
} },
3866 { "mfivor13", XSPR(31,339,413), XSPR_MASK
, BOOKE
, { RT
} },
3867 { "mfivor14", XSPR(31,339,414), XSPR_MASK
, BOOKE
, { RT
} },
3868 { "mfivor15", XSPR(31,339,415), XSPR_MASK
, BOOKE
, { RT
} },
3869 { "mfspefscr", XSPR(31,339,512), XSPR_MASK
, PPCSPE
, { RT
} },
3870 { "mfbbear", XSPR(31,339,513), XSPR_MASK
, PPCBRLK
, { RT
} },
3871 { "mfbbtar", XSPR(31,339,514), XSPR_MASK
, PPCBRLK
, { RT
} },
3872 { "mfivor32", XSPR(31,339,528), XSPR_MASK
, PPCSPE
, { RT
} },
3873 { "mfivor33", XSPR(31,339,529), XSPR_MASK
, PPCSPE
, { RT
} },
3874 { "mfivor34", XSPR(31,339,530), XSPR_MASK
, PPCSPE
, { RT
} },
3875 { "mfivor35", XSPR(31,339,531), XSPR_MASK
, PPCPMR
, { RT
} },
3876 { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK
, PPC
, { RT
, SPRBAT
} },
3877 { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK
, PPC
, { RT
, SPRBAT
} },
3878 { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK
, PPC
, { RT
, SPRBAT
} },
3879 { "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK
, PPC
, { RT
, SPRBAT
} },
3880 { "mfic_cst", XSPR(31,339,560), XSPR_MASK
, PPC860
, { RT
} },
3881 { "mfic_adr", XSPR(31,339,561), XSPR_MASK
, PPC860
, { RT
} },
3882 { "mfic_dat", XSPR(31,339,562), XSPR_MASK
, PPC860
, { RT
} },
3883 { "mfdc_cst", XSPR(31,339,568), XSPR_MASK
, PPC860
, { RT
} },
3884 { "mfdc_adr", XSPR(31,339,569), XSPR_MASK
, PPC860
, { RT
} },
3885 { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK
, PPCRFMCI
, { RT
} },
3886 { "mfdc_dat", XSPR(31,339,570), XSPR_MASK
, PPC860
, { RT
} },
3887 { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK
, PPCRFMCI
, { RT
} },
3888 { "mfmcsr", XSPR(31,339,572), XSPR_MASK
, PPCRFMCI
, { RT
} },
3889 { "mfmcar", XSPR(31,339,573), XSPR_MASK
, PPCRFMCI
, { RT
} },
3890 { "mfdpdr", XSPR(31,339,630), XSPR_MASK
, PPC860
, { RT
} },
3891 { "mfdpir", XSPR(31,339,631), XSPR_MASK
, PPC860
, { RT
} },
3892 { "mfimmr", XSPR(31,339,638), XSPR_MASK
, PPC860
, { RT
} },
3893 { "mfmi_ctr", XSPR(31,339,784), XSPR_MASK
, PPC860
, { RT
} },
3894 { "mfmi_ap", XSPR(31,339,786), XSPR_MASK
, PPC860
, { RT
} },
3895 { "mfmi_epn", XSPR(31,339,787), XSPR_MASK
, PPC860
, { RT
} },
3896 { "mfmi_twc", XSPR(31,339,789), XSPR_MASK
, PPC860
, { RT
} },
3897 { "mfmi_rpn", XSPR(31,339,790), XSPR_MASK
, PPC860
, { RT
} },
3898 { "mfmd_ctr", XSPR(31,339,792), XSPR_MASK
, PPC860
, { RT
} },
3899 { "mfm_casid", XSPR(31,339,793), XSPR_MASK
, PPC860
, { RT
} },
3900 { "mfmd_ap", XSPR(31,339,794), XSPR_MASK
, PPC860
, { RT
} },
3901 { "mfmd_epn", XSPR(31,339,795), XSPR_MASK
, PPC860
, { RT
} },
3902 { "mfmd_twb", XSPR(31,339,796), XSPR_MASK
, PPC860
, { RT
} },
3903 { "mfmd_twc", XSPR(31,339,797), XSPR_MASK
, PPC860
, { RT
} },
3904 { "mfmd_rpn", XSPR(31,339,798), XSPR_MASK
, PPC860
, { RT
} },
3905 { "mfm_tw", XSPR(31,339,799), XSPR_MASK
, PPC860
, { RT
} },
3906 { "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK
, PPC860
, { RT
} },
3907 { "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK
, PPC860
, { RT
} },
3908 { "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK
, PPC860
, { RT
} },
3909 { "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK
, PPC860
, { RT
} },
3910 { "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK
, PPC860
, { RT
} },
3911 { "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK
, PPC860
, { RT
} },
3912 { "mfummcr0", XSPR(31,339,936), XSPR_MASK
, PPC750
, { RT
} },
3913 { "mfupmc1", XSPR(31,339,937), XSPR_MASK
, PPC750
, { RT
} },
3914 { "mfupmc2", XSPR(31,339,938), XSPR_MASK
, PPC750
, { RT
} },
3915 { "mfusia", XSPR(31,339,939), XSPR_MASK
, PPC750
, { RT
} },
3916 { "mfummcr1", XSPR(31,339,940), XSPR_MASK
, PPC750
, { RT
} },
3917 { "mfupmc3", XSPR(31,339,941), XSPR_MASK
, PPC750
, { RT
} },
3918 { "mfupmc4", XSPR(31,339,942), XSPR_MASK
, PPC750
, { RT
} },
3919 { "mfzpr", XSPR(31,339,944), XSPR_MASK
, PPC403
, { RT
} },
3920 { "mfccr0", XSPR(31,339,947), XSPR_MASK
, PPC405
, { RT
} },
3921 { "mfmmcr0", XSPR(31,339,952), XSPR_MASK
, PPC750
, { RT
} },
3922 { "mfpmc1", XSPR(31,339,953), XSPR_MASK
, PPC750
, { RT
} },
3923 { "mfsgr", XSPR(31,339,953), XSPR_MASK
, PPC403
, { RT
} },
3924 { "mfpmc2", XSPR(31,339,954), XSPR_MASK
, PPC750
, { RT
} },
3925 { "mfdcwr", XSPR(31,339,954), XSPR_MASK
, PPC403
, { RT
} },
3926 { "mfsia", XSPR(31,339,955), XSPR_MASK
, PPC750
, { RT
} },
3927 { "mfsler", XSPR(31,339,955), XSPR_MASK
, PPC405
, { RT
} },
3928 { "mfmmcr1", XSPR(31,339,956), XSPR_MASK
, PPC750
, { RT
} },
3929 { "mfsu0r", XSPR(31,339,956), XSPR_MASK
, PPC405
, { RT
} },
3930 { "mfpmc3", XSPR(31,339,957), XSPR_MASK
, PPC750
, { RT
} },
3931 { "mfpmc4", XSPR(31,339,958), XSPR_MASK
, PPC750
, { RT
} },
3932 { "mficdbdr", XSPR(31,339,979), XSPR_MASK
, PPC403
, { RT
} },
3933 { "mfevpr", XSPR(31,339,982), XSPR_MASK
, PPC403
, { RT
} },
3934 { "mfcdbcr", XSPR(31,339,983), XSPR_MASK
, PPC403
, { RT
} },
3935 { "mfpit", XSPR(31,339,987), XSPR_MASK
, PPC403
, { RT
} },
3936 { "mftbhi", XSPR(31,339,988), XSPR_MASK
, PPC403
, { RT
} },
3937 { "mftblo", XSPR(31,339,989), XSPR_MASK
, PPC403
, { RT
} },
3938 { "mfsrr2", XSPR(31,339,990), XSPR_MASK
, PPC403
, { RT
} },
3939 { "mfsrr3", XSPR(31,339,991), XSPR_MASK
, PPC403
, { RT
} },
3940 { "mfl2cr", XSPR(31,339,1017), XSPR_MASK
, PPC750
, { RT
} },
3941 { "mfdccr", XSPR(31,339,1018), XSPR_MASK
, PPC403
, { RT
} },
3942 { "mficcr", XSPR(31,339,1019), XSPR_MASK
, PPC403
, { RT
} },
3943 { "mfictc", XSPR(31,339,1019), XSPR_MASK
, PPC750
, { RT
} },
3944 { "mfpbl1", XSPR(31,339,1020), XSPR_MASK
, PPC403
, { RT
} },
3945 { "mfthrm1", XSPR(31,339,1020), XSPR_MASK
, PPC750
, { RT
} },
3946 { "mfpbu1", XSPR(31,339,1021), XSPR_MASK
, PPC403
, { RT
} },
3947 { "mfthrm2", XSPR(31,339,1021), XSPR_MASK
, PPC750
, { RT
} },
3948 { "mfpbl2", XSPR(31,339,1022), XSPR_MASK
, PPC403
, { RT
} },
3949 { "mfthrm3", XSPR(31,339,1022), XSPR_MASK
, PPC750
, { RT
} },
3950 { "mfpbu2", XSPR(31,339,1023), XSPR_MASK
, PPC403
, { RT
} },
3951 { "mfspr", X(31,339), X_MASK
, COM
, { RT
, SPR
} },
3953 { "lwax", X(31,341), X_MASK
, PPC64
, { RT
, RA0
, RB
} },
3955 { "dst", XDSS(31,342,0), XDSS_MASK
, PPCVEC
, { RA
, RB
, STRM
} },
3956 { "dstt", XDSS(31,342,1), XDSS_MASK
, PPCVEC
, { RA
, RB
, STRM
} },
3958 { "lhax", X(31,343), X_MASK
, COM
, { RT
, RA0
, RB
} },
3960 { "lhaxe", X(31,351), X_MASK
, BOOKE64
, { RT
, RA0
, RB
} },
3962 { "dstst", XDSS(31,374,0), XDSS_MASK
, PPCVEC
, { RA
, RB
, STRM
} },
3963 { "dststt", XDSS(31,374,1), XDSS_MASK
, PPCVEC
, { RA
, RB
, STRM
} },
3965 { "dccci", X(31,454), XRT_MASK
, PPC403
|PPC440
, { RA
, RB
} },
3967 { "abs", XO(31,360,0,0), XORB_MASK
, M601
, { RT
, RA
} },
3968 { "abs.", XO(31,360,0,1), XORB_MASK
, M601
, { RT
, RA
} },
3969 { "abso", XO(31,360,1,0), XORB_MASK
, M601
, { RT
, RA
} },
3970 { "abso.", XO(31,360,1,1), XORB_MASK
, M601
, { RT
, RA
} },
3972 { "divs", XO(31,363,0,0), XO_MASK
, M601
, { RT
, RA
, RB
} },
3973 { "divs.", XO(31,363,0,1), XO_MASK
, M601
, { RT
, RA
, RB
} },
3974 { "divso", XO(31,363,1,0), XO_MASK
, M601
, { RT
, RA
, RB
} },
3975 { "divso.", XO(31,363,1,1), XO_MASK
, M601
, { RT
, RA
, RB
} },
3977 { "tlbia", X(31,370), 0xffffffff, PPC
, { 0 } },
3979 { "lwaux", X(31,373), X_MASK
, PPC64
, { RT
, RAL
, RB
} },
3981 { "lhaux", X(31,375), X_MASK
, COM
, { RT
, RAL
, RB
} },
3983 { "lhauxe", X(31,383), X_MASK
, BOOKE64
, { RT
, RAL
, RB
} },
3985 { "mtdcrx", X(31,387), X_MASK
, BOOKE
, { RA
, RS
} },
3987 { "dcblc", X(31,390), X_MASK
, PPCCHLK
, { CT
, RA
, RB
}},
3989 { "subfe64", XO(31,392,0,0), XO_MASK
, BOOKE64
, { RT
, RA
, RB
} },
3990 { "subfe64o",XO(31,392,1,0), XO_MASK
, BOOKE64
, { RT
, RA
, RB
} },
3992 { "adde64", XO(31,394,0,0), XO_MASK
, BOOKE64
, { RT
, RA
, RB
} },
3993 { "adde64o", XO(31,394,1,0), XO_MASK
, BOOKE64
, { RT
, RA
, RB
} },
3995 { "dcblce", X(31,398), X_MASK
, PPCCHLK64
, { CT
, RA
, RB
}},
3997 { "slbmte", X(31,402), XRA_MASK
, PPC64
, { RS
, RB
} },
3999 { "sthx", X(31,407), X_MASK
, COM
, { RS
, RA0
, RB
} },
4001 { "cmpb", X(31,508), X_MASK
, POWER6
, { RA
, RS
, RB
} },
4003 { "lfqx", X(31,791), X_MASK
, POWER2
, { FRT
, RA
, RB
} },
4005 { "lfdpx", X(31,791), X_MASK
, POWER6
, { FRT
, RA
, RB
} },
4007 { "lfqux", X(31,823), X_MASK
, POWER2
, { FRT
, RA
, RB
} },
4009 { "stfqx", X(31,919), X_MASK
, POWER2
, { FRS
, RA
, RB
} },
4011 { "stfdpx", X(31,919), X_MASK
, POWER6
, { FRS
, RA
, RB
} },
4013 { "stfqux", X(31,951), X_MASK
, POWER2
, { FRS
, RA
, RB
} },
4015 { "orc", XRC(31,412,0), X_MASK
, COM
, { RA
, RS
, RB
} },
4016 { "orc.", XRC(31,412,1), X_MASK
, COM
, { RA
, RS
, RB
} },
4018 { "sradi", XS(31,413,0), XS_MASK
, PPC64
, { RA
, RS
, SH6
} },
4019 { "sradi.", XS(31,413,1), XS_MASK
, PPC64
, { RA
, RS
, SH6
} },
4021 { "sthxe", X(31,415), X_MASK
, BOOKE64
, { RS
, RA0
, RB
} },
4023 { "slbie", X(31,434), XRTRA_MASK
, PPC64
, { RB
} },
4025 { "ecowx", X(31,438), X_MASK
, PPC
, { RT
, RA
, RB
} },
4027 { "sthux", X(31,439), X_MASK
, COM
, { RS
, RAS
, RB
} },
4029 { "sthuxe", X(31,447), X_MASK
, BOOKE64
, { RS
, RAS
, RB
} },
4031 { "cctpl", 0x7c210b78, 0xffffffff, CELL
, { 0 }},
4032 { "cctpm", 0x7c421378, 0xffffffff, CELL
, { 0 }},
4033 { "cctph", 0x7c631b78, 0xffffffff, CELL
, { 0 }},
4034 { "db8cyc", 0x7f9ce378, 0xffffffff, CELL
, { 0 }},
4035 { "db10cyc", 0x7fbdeb78, 0xffffffff, CELL
, { 0 }},
4036 { "db12cyc", 0x7fdef378, 0xffffffff, CELL
, { 0 }},
4037 { "db16cyc", 0x7ffffb78, 0xffffffff, CELL
, { 0 }},
4038 { "mr", XRC(31,444,0), X_MASK
, COM
, { RA
, RS
, RBS
} },
4039 { "or", XRC(31,444,0), X_MASK
, COM
, { RA
, RS
, RB
} },
4040 { "mr.", XRC(31,444,1), X_MASK
, COM
, { RA
, RS
, RBS
} },
4041 { "or.", XRC(31,444,1), X_MASK
, COM
, { RA
, RS
, RB
} },
4043 { "mtexisr", XSPR(31,451,64), XSPR_MASK
, PPC403
, { RS
} },
4044 { "mtexier", XSPR(31,451,66), XSPR_MASK
, PPC403
, { RS
} },
4045 { "mtbr0", XSPR(31,451,128), XSPR_MASK
, PPC403
, { RS
} },
4046 { "mtbr1", XSPR(31,451,129), XSPR_MASK
, PPC403
, { RS
} },
4047 { "mtbr2", XSPR(31,451,130), XSPR_MASK
, PPC403
, { RS
} },
4048 { "mtbr3", XSPR(31,451,131), XSPR_MASK
, PPC403
, { RS
} },
4049 { "mtbr4", XSPR(31,451,132), XSPR_MASK
, PPC403
, { RS
} },
4050 { "mtbr5", XSPR(31,451,133), XSPR_MASK
, PPC403
, { RS
} },
4051 { "mtbr6", XSPR(31,451,134), XSPR_MASK
, PPC403
, { RS
} },
4052 { "mtbr7", XSPR(31,451,135), XSPR_MASK
, PPC403
, { RS
} },
4053 { "mtbear", XSPR(31,451,144), XSPR_MASK
, PPC403
, { RS
} },
4054 { "mtbesr", XSPR(31,451,145), XSPR_MASK
, PPC403
, { RS
} },
4055 { "mtiocr", XSPR(31,451,160), XSPR_MASK
, PPC403
, { RS
} },
4056 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK
, PPC403
, { RS
} },
4057 { "mtdmact0", XSPR(31,451,193), XSPR_MASK
, PPC403
, { RS
} },
4058 { "mtdmada0", XSPR(31,451,194), XSPR_MASK
, PPC403
, { RS
} },
4059 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK
, PPC403
, { RS
} },
4060 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK
, PPC403
, { RS
} },
4061 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK
, PPC403
, { RS
} },
4062 { "mtdmact1", XSPR(31,451,201), XSPR_MASK
, PPC403
, { RS
} },
4063 { "mtdmada1", XSPR(31,451,202), XSPR_MASK
, PPC403
, { RS
} },
4064 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK
, PPC403
, { RS
} },
4065 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK
, PPC403
, { RS
} },
4066 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK
, PPC403
, { RS
} },
4067 { "mtdmact2", XSPR(31,451,209), XSPR_MASK
, PPC403
, { RS
} },
4068 { "mtdmada2", XSPR(31,451,210), XSPR_MASK
, PPC403
, { RS
} },
4069 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK
, PPC403
, { RS
} },
4070 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK
, PPC403
, { RS
} },
4071 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK
, PPC403
, { RS
} },
4072 { "mtdmact3", XSPR(31,451,217), XSPR_MASK
, PPC403
, { RS
} },
4073 { "mtdmada3", XSPR(31,451,218), XSPR_MASK
, PPC403
, { RS
} },
4074 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK
, PPC403
, { RS
} },
4075 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK
, PPC403
, { RS
} },
4076 { "mtdmasr", XSPR(31,451,224), XSPR_MASK
, PPC403
, { RS
} },
4077 { "mtdcr", X(31,451), X_MASK
, PPC403
| BOOKE
, { SPR
, RS
} },
4079 { "subfze64",XO(31,456,0,0), XORB_MASK
, BOOKE64
, { RT
, RA
} },
4080 { "subfze64o",XO(31,456,1,0), XORB_MASK
, BOOKE64
, { RT
, RA
} },
4082 { "divdu", XO(31,457,0,0), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
4083 { "divdu.", XO(31,457,0,1), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
4084 { "divduo", XO(31,457,1,0), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
4085 { "divduo.", XO(31,457,1,1), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
4087 { "addze64", XO(31,458,0,0), XORB_MASK
, BOOKE64
, { RT
, RA
} },
4088 { "addze64o",XO(31,458,1,0), XORB_MASK
, BOOKE64
, { RT
, RA
} },
4090 { "divwu", XO(31,459,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
4091 { "divwu.", XO(31,459,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
4092 { "divwuo", XO(31,459,1,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
4093 { "divwuo.", XO(31,459,1,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
4095 { "mtmq", XSPR(31,467,0), XSPR_MASK
, M601
, { RS
} },
4096 { "mtxer", XSPR(31,467,1), XSPR_MASK
, COM
, { RS
} },
4097 { "mtlr", XSPR(31,467,8), XSPR_MASK
, COM
, { RS
} },
4098 { "mtctr", XSPR(31,467,9), XSPR_MASK
, COM
, { RS
} },
4099 { "mttid", XSPR(31,467,17), XSPR_MASK
, POWER
, { RS
} },
4100 { "mtdsisr", XSPR(31,467,18), XSPR_MASK
, COM
, { RS
} },
4101 { "mtdar", XSPR(31,467,19), XSPR_MASK
, COM
, { RS
} },
4102 { "mtrtcu", XSPR(31,467,20), XSPR_MASK
, COM
, { RS
} },
4103 { "mtrtcl", XSPR(31,467,21), XSPR_MASK
, COM
, { RS
} },
4104 { "mtdec", XSPR(31,467,22), XSPR_MASK
, COM
, { RS
} },
4105 { "mtsdr0", XSPR(31,467,24), XSPR_MASK
, POWER
, { RS
} },
4106 { "mtsdr1", XSPR(31,467,25), XSPR_MASK
, COM
, { RS
} },
4107 { "mtsrr0", XSPR(31,467,26), XSPR_MASK
, COM
, { RS
} },
4108 { "mtsrr1", XSPR(31,467,27), XSPR_MASK
, COM
, { RS
} },
4109 { "mtcfar", XSPR(31,467,28), XSPR_MASK
, POWER6
, { RS
} },
4110 { "mtpid", XSPR(31,467,48), XSPR_MASK
, BOOKE
, { RS
} },
4111 { "mtpid", XSPR(31,467,945), XSPR_MASK
, PPC403
, { RS
} },
4112 { "mtdecar", XSPR(31,467,54), XSPR_MASK
, BOOKE
, { RS
} },
4113 { "mtcsrr0", XSPR(31,467,58), XSPR_MASK
, BOOKE
, { RS
} },
4114 { "mtcsrr1", XSPR(31,467,59), XSPR_MASK
, BOOKE
, { RS
} },
4115 { "mtdear", XSPR(31,467,61), XSPR_MASK
, BOOKE
, { RS
} },
4116 { "mtdear", XSPR(31,467,981), XSPR_MASK
, PPC403
, { RS
} },
4117 { "mtesr", XSPR(31,467,62), XSPR_MASK
, BOOKE
, { RS
} },
4118 { "mtesr", XSPR(31,467,980), XSPR_MASK
, PPC403
, { RS
} },
4119 { "mtivpr", XSPR(31,467,63), XSPR_MASK
, BOOKE
, { RS
} },
4120 { "mtcmpa", XSPR(31,467,144), XSPR_MASK
, PPC860
, { RS
} },
4121 { "mtcmpb", XSPR(31,467,145), XSPR_MASK
, PPC860
, { RS
} },
4122 { "mtcmpc", XSPR(31,467,146), XSPR_MASK
, PPC860
, { RS
} },
4123 { "mtcmpd", XSPR(31,467,147), XSPR_MASK
, PPC860
, { RS
} },
4124 { "mticr", XSPR(31,467,148), XSPR_MASK
, PPC860
, { RS
} },
4125 { "mtder", XSPR(31,467,149), XSPR_MASK
, PPC860
, { RS
} },
4126 { "mtcounta", XSPR(31,467,150), XSPR_MASK
, PPC860
, { RS
} },
4127 { "mtcountb", XSPR(31,467,151), XSPR_MASK
, PPC860
, { RS
} },
4128 { "mtcmpe", XSPR(31,467,152), XSPR_MASK
, PPC860
, { RS
} },
4129 { "mtcmpf", XSPR(31,467,153), XSPR_MASK
, PPC860
, { RS
} },
4130 { "mtcmpg", XSPR(31,467,154), XSPR_MASK
, PPC860
, { RS
} },
4131 { "mtcmph", XSPR(31,467,155), XSPR_MASK
, PPC860
, { RS
} },
4132 { "mtlctrl1", XSPR(31,467,156), XSPR_MASK
, PPC860
, { RS
} },
4133 { "mtlctrl2", XSPR(31,467,157), XSPR_MASK
, PPC860
, { RS
} },
4134 { "mtictrl", XSPR(31,467,158), XSPR_MASK
, PPC860
, { RS
} },
4135 { "mtbar", XSPR(31,467,159), XSPR_MASK
, PPC860
, { RS
} },
4136 { "mtvrsave", XSPR(31,467,256), XSPR_MASK
, PPCVEC
, { RS
} },
4137 { "mtusprg0", XSPR(31,467,256), XSPR_MASK
, BOOKE
, { RS
} },
4138 { "mtsprg", XSPR(31,467,256), XSPRG_MASK
,PPC
, { SPRG
, RS
} },
4139 { "mtsprg0", XSPR(31,467,272), XSPR_MASK
, PPC
, { RS
} },
4140 { "mtsprg1", XSPR(31,467,273), XSPR_MASK
, PPC
, { RS
} },
4141 { "mtsprg2", XSPR(31,467,274), XSPR_MASK
, PPC
, { RS
} },
4142 { "mtsprg3", XSPR(31,467,275), XSPR_MASK
, PPC
, { RS
} },
4143 { "mtsprg4", XSPR(31,467,276), XSPR_MASK
, PPC405
| BOOKE
, { RS
} },
4144 { "mtsprg5", XSPR(31,467,277), XSPR_MASK
, PPC405
| BOOKE
, { RS
} },
4145 { "mtsprg6", XSPR(31,467,278), XSPR_MASK
, PPC405
| BOOKE
, { RS
} },
4146 { "mtsprg7", XSPR(31,467,279), XSPR_MASK
, PPC405
| BOOKE
, { RS
} },
4147 { "mtasr", XSPR(31,467,280), XSPR_MASK
, PPC64
, { RS
} },
4148 { "mtear", XSPR(31,467,282), XSPR_MASK
, PPC
, { RS
} },
4149 { "mttbl", XSPR(31,467,284), XSPR_MASK
, PPC
, { RS
} },
4150 { "mttbu", XSPR(31,467,285), XSPR_MASK
, PPC
, { RS
} },
4151 { "mtdbsr", XSPR(31,467,304), XSPR_MASK
, BOOKE
, { RS
} },
4152 { "mtdbsr", XSPR(31,467,1008), XSPR_MASK
, PPC403
, { RS
} },
4153 { "mtdbcr0", XSPR(31,467,308), XSPR_MASK
, BOOKE
, { RS
} },
4154 { "mtdbcr0", XSPR(31,467,1010), XSPR_MASK
, PPC405
, { RS
} },
4155 { "mtdbcr1", XSPR(31,467,309), XSPR_MASK
, BOOKE
, { RS
} },
4156 { "mtdbcr1", XSPR(31,467,957), XSPR_MASK
, PPC405
, { RS
} },
4157 { "mtdbcr2", XSPR(31,467,310), XSPR_MASK
, BOOKE
, { RS
} },
4158 { "mtiac1", XSPR(31,467,312), XSPR_MASK
, BOOKE
, { RS
} },
4159 { "mtiac1", XSPR(31,467,1012), XSPR_MASK
, PPC403
, { RS
} },
4160 { "mtiac2", XSPR(31,467,313), XSPR_MASK
, BOOKE
, { RS
} },
4161 { "mtiac2", XSPR(31,467,1013), XSPR_MASK
, PPC403
, { RS
} },
4162 { "mtiac3", XSPR(31,467,314), XSPR_MASK
, BOOKE
, { RS
} },
4163 { "mtiac3", XSPR(31,467,948), XSPR_MASK
, PPC405
, { RS
} },
4164 { "mtiac4", XSPR(31,467,315), XSPR_MASK
, BOOKE
, { RS
} },
4165 { "mtiac4", XSPR(31,467,949), XSPR_MASK
, PPC405
, { RS
} },
4166 { "mtdac1", XSPR(31,467,316), XSPR_MASK
, BOOKE
, { RS
} },
4167 { "mtdac1", XSPR(31,467,1014), XSPR_MASK
, PPC403
, { RS
} },
4168 { "mtdac2", XSPR(31,467,317), XSPR_MASK
, BOOKE
, { RS
} },
4169 { "mtdac2", XSPR(31,467,1015), XSPR_MASK
, PPC403
, { RS
} },
4170 { "mtdvc1", XSPR(31,467,318), XSPR_MASK
, BOOKE
, { RS
} },
4171 { "mtdvc1", XSPR(31,467,950), XSPR_MASK
, PPC405
, { RS
} },
4172 { "mtdvc2", XSPR(31,467,319), XSPR_MASK
, BOOKE
, { RS
} },
4173 { "mtdvc2", XSPR(31,467,951), XSPR_MASK
, PPC405
, { RS
} },
4174 { "mttsr", XSPR(31,467,336), XSPR_MASK
, BOOKE
, { RS
} },
4175 { "mttsr", XSPR(31,467,984), XSPR_MASK
, PPC403
, { RS
} },
4176 { "mttcr", XSPR(31,467,340), XSPR_MASK
, BOOKE
, { RS
} },
4177 { "mttcr", XSPR(31,467,986), XSPR_MASK
, PPC403
, { RS
} },
4178 { "mtivor0", XSPR(31,467,400), XSPR_MASK
, BOOKE
, { RS
} },
4179 { "mtivor1", XSPR(31,467,401), XSPR_MASK
, BOOKE
, { RS
} },
4180 { "mtivor2", XSPR(31,467,402), XSPR_MASK
, BOOKE
, { RS
} },
4181 { "mtivor3", XSPR(31,467,403), XSPR_MASK
, BOOKE
, { RS
} },
4182 { "mtivor4", XSPR(31,467,404), XSPR_MASK
, BOOKE
, { RS
} },
4183 { "mtivor5", XSPR(31,467,405), XSPR_MASK
, BOOKE
, { RS
} },
4184 { "mtivor6", XSPR(31,467,406), XSPR_MASK
, BOOKE
, { RS
} },
4185 { "mtivor7", XSPR(31,467,407), XSPR_MASK
, BOOKE
, { RS
} },
4186 { "mtivor8", XSPR(31,467,408), XSPR_MASK
, BOOKE
, { RS
} },
4187 { "mtivor9", XSPR(31,467,409), XSPR_MASK
, BOOKE
, { RS
} },
4188 { "mtivor10", XSPR(31,467,410), XSPR_MASK
, BOOKE
, { RS
} },
4189 { "mtivor11", XSPR(31,467,411), XSPR_MASK
, BOOKE
, { RS
} },
4190 { "mtivor12", XSPR(31,467,412), XSPR_MASK
, BOOKE
, { RS
} },
4191 { "mtivor13", XSPR(31,467,413), XSPR_MASK
, BOOKE
, { RS
} },
4192 { "mtivor14", XSPR(31,467,414), XSPR_MASK
, BOOKE
, { RS
} },
4193 { "mtivor15", XSPR(31,467,415), XSPR_MASK
, BOOKE
, { RS
} },
4194 { "mtspefscr", XSPR(31,467,512), XSPR_MASK
, PPCSPE
, { RS
} },
4195 { "mtbbear", XSPR(31,467,513), XSPR_MASK
, PPCBRLK
, { RS
} },
4196 { "mtbbtar", XSPR(31,467,514), XSPR_MASK
, PPCBRLK
, { RS
} },
4197 { "mtivor32", XSPR(31,467,528), XSPR_MASK
, PPCSPE
, { RS
} },
4198 { "mtivor33", XSPR(31,467,529), XSPR_MASK
, PPCSPE
, { RS
} },
4199 { "mtivor34", XSPR(31,467,530), XSPR_MASK
, PPCSPE
, { RS
} },
4200 { "mtivor35", XSPR(31,467,531), XSPR_MASK
, PPCPMR
, { RS
} },
4201 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK
, PPC
, { SPRBAT
, RS
} },
4202 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK
, PPC
, { SPRBAT
, RS
} },
4203 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK
, PPC
, { SPRBAT
, RS
} },
4204 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK
, PPC
, { SPRBAT
, RS
} },
4205 { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK
, PPCRFMCI
, { RS
} },
4206 { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK
, PPCRFMCI
, { RS
} },
4207 { "mtmcsr", XSPR(31,467,572), XSPR_MASK
, PPCRFMCI
, { RS
} },
4208 { "mtummcr0", XSPR(31,467,936), XSPR_MASK
, PPC750
, { RS
} },
4209 { "mtupmc1", XSPR(31,467,937), XSPR_MASK
, PPC750
, { RS
} },
4210 { "mtupmc2", XSPR(31,467,938), XSPR_MASK
, PPC750
, { RS
} },
4211 { "mtusia", XSPR(31,467,939), XSPR_MASK
, PPC750
, { RS
} },
4212 { "mtummcr1", XSPR(31,467,940), XSPR_MASK
, PPC750
, { RS
} },
4213 { "mtupmc3", XSPR(31,467,941), XSPR_MASK
, PPC750
, { RS
} },
4214 { "mtupmc4", XSPR(31,467,942), XSPR_MASK
, PPC750
, { RS
} },
4215 { "mtzpr", XSPR(31,467,944), XSPR_MASK
, PPC403
, { RS
} },
4216 { "mtccr0", XSPR(31,467,947), XSPR_MASK
, PPC405
, { RS
} },
4217 { "mtmmcr0", XSPR(31,467,952), XSPR_MASK
, PPC750
, { RS
} },
4218 { "mtsgr", XSPR(31,467,953), XSPR_MASK
, PPC403
, { RS
} },
4219 { "mtpmc1", XSPR(31,467,953), XSPR_MASK
, PPC750
, { RS
} },
4220 { "mtdcwr", XSPR(31,467,954), XSPR_MASK
, PPC403
, { RS
} },
4221 { "mtpmc2", XSPR(31,467,954), XSPR_MASK
, PPC750
, { RS
} },
4222 { "mtsler", XSPR(31,467,955), XSPR_MASK
, PPC405
, { RS
} },
4223 { "mtsia", XSPR(31,467,955), XSPR_MASK
, PPC750
, { RS
} },
4224 { "mtsu0r", XSPR(31,467,956), XSPR_MASK
, PPC405
, { RS
} },
4225 { "mtmmcr1", XSPR(31,467,956), XSPR_MASK
, PPC750
, { RS
} },
4226 { "mtpmc3", XSPR(31,467,957), XSPR_MASK
, PPC750
, { RS
} },
4227 { "mtpmc4", XSPR(31,467,958), XSPR_MASK
, PPC750
, { RS
} },
4228 { "mticdbdr", XSPR(31,467,979), XSPR_MASK
, PPC403
, { RS
} },
4229 { "mtevpr", XSPR(31,467,982), XSPR_MASK
, PPC403
, { RS
} },
4230 { "mtcdbcr", XSPR(31,467,983), XSPR_MASK
, PPC403
, { RS
} },
4231 { "mtpit", XSPR(31,467,987), XSPR_MASK
, PPC403
, { RS
} },
4232 { "mttbhi", XSPR(31,467,988), XSPR_MASK
, PPC403
, { RS
} },
4233 { "mttblo", XSPR(31,467,989), XSPR_MASK
, PPC403
, { RS
} },
4234 { "mtsrr2", XSPR(31,467,990), XSPR_MASK
, PPC403
, { RS
} },
4235 { "mtsrr3", XSPR(31,467,991), XSPR_MASK
, PPC403
, { RS
} },
4236 { "mtl2cr", XSPR(31,467,1017), XSPR_MASK
, PPC750
, { RS
} },
4237 { "mtdccr", XSPR(31,467,1018), XSPR_MASK
, PPC403
, { RS
} },
4238 { "mticcr", XSPR(31,467,1019), XSPR_MASK
, PPC403
, { RS
} },
4239 { "mtictc", XSPR(31,467,1019), XSPR_MASK
, PPC750
, { RS
} },
4240 { "mtpbl1", XSPR(31,467,1020), XSPR_MASK
, PPC403
, { RS
} },
4241 { "mtthrm1", XSPR(31,467,1020), XSPR_MASK
, PPC750
, { RS
} },
4242 { "mtpbu1", XSPR(31,467,1021), XSPR_MASK
, PPC403
, { RS
} },
4243 { "mtthrm2", XSPR(31,467,1021), XSPR_MASK
, PPC750
, { RS
} },
4244 { "mtpbl2", XSPR(31,467,1022), XSPR_MASK
, PPC403
, { RS
} },
4245 { "mtthrm3", XSPR(31,467,1022), XSPR_MASK
, PPC750
, { RS
} },
4246 { "mtpbu2", XSPR(31,467,1023), XSPR_MASK
, PPC403
, { RS
} },
4247 { "mtspr", X(31,467), X_MASK
, COM
, { SPR
, RS
} },
4249 { "dcbi", X(31,470), XRT_MASK
, PPC
, { RA
, RB
} },
4251 { "nand", XRC(31,476,0), X_MASK
, COM
, { RA
, RS
, RB
} },
4252 { "nand.", XRC(31,476,1), X_MASK
, COM
, { RA
, RS
, RB
} },
4254 { "dcbie", X(31,478), XRT_MASK
, BOOKE64
, { RA
, RB
} },
4256 { "dcread", X(31,486), X_MASK
, PPC403
|PPC440
, { RT
, RA
, RB
}},
4258 { "mtpmr", X(31,462), X_MASK
, PPCPMR
, { PMR
, RS
}},
4260 { "icbtls", X(31,486), X_MASK
, PPCCHLK
, { CT
, RA
, RB
}},
4262 { "nabs", XO(31,488,0,0), XORB_MASK
, M601
, { RT
, RA
} },
4263 { "subfme64",XO(31,488,0,0), XORB_MASK
, BOOKE64
, { RT
, RA
} },
4264 { "nabs.", XO(31,488,0,1), XORB_MASK
, M601
, { RT
, RA
} },
4265 { "nabso", XO(31,488,1,0), XORB_MASK
, M601
, { RT
, RA
} },
4266 { "subfme64o",XO(31,488,1,0), XORB_MASK
, BOOKE64
, { RT
, RA
} },
4267 { "nabso.", XO(31,488,1,1), XORB_MASK
, M601
, { RT
, RA
} },
4269 { "divd", XO(31,489,0,0), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
4270 { "divd.", XO(31,489,0,1), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
4271 { "divdo", XO(31,489,1,0), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
4272 { "divdo.", XO(31,489,1,1), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
4274 { "addme64", XO(31,490,0,0), XORB_MASK
, BOOKE64
, { RT
, RA
} },
4275 { "addme64o",XO(31,490,1,0), XORB_MASK
, BOOKE64
, { RT
, RA
} },
4277 { "divw", XO(31,491,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
4278 { "divw.", XO(31,491,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
4279 { "divwo", XO(31,491,1,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
4280 { "divwo.", XO(31,491,1,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
4282 { "icbtlse", X(31,494), X_MASK
, PPCCHLK64
, { CT
, RA
, RB
}},
4284 { "slbia", X(31,498), 0xffffffff, PPC64
, { 0 } },
4286 { "cli", X(31,502), XRB_MASK
, POWER
, { RT
, RA
} },
4288 { "stdcxe.", XRC(31,511,1), X_MASK
, BOOKE64
, { RS
, RA
, RB
} },
4290 { "mcrxr", X(31,512), XRARB_MASK
|(3<<21), COM
, { BF
} },
4292 { "bblels", X(31,518), X_MASK
, PPCBRLK
, { 0 }},
4293 { "mcrxr64", X(31,544), XRARB_MASK
|(3<<21), BOOKE64
, { BF
} },
4295 { "clcs", X(31,531), XRB_MASK
, M601
, { RT
, RA
} },
4297 { "ldbrx", X(31,532), X_MASK
, CELL
, { RT
, RA0
, RB
} },
4299 { "lswx", X(31,533), X_MASK
, PPCCOM
, { RT
, RA0
, RB
} },
4300 { "lsx", X(31,533), X_MASK
, PWRCOM
, { RT
, RA
, RB
} },
4302 { "lwbrx", X(31,534), X_MASK
, PPCCOM
, { RT
, RA0
, RB
} },
4303 { "lbrx", X(31,534), X_MASK
, PWRCOM
, { RT
, RA
, RB
} },
4305 { "lfsx", X(31,535), X_MASK
, COM
, { FRT
, RA0
, RB
} },
4307 { "srw", XRC(31,536,0), X_MASK
, PPCCOM
, { RA
, RS
, RB
} },
4308 { "sr", XRC(31,536,0), X_MASK
, PWRCOM
, { RA
, RS
, RB
} },
4309 { "srw.", XRC(31,536,1), X_MASK
, PPCCOM
, { RA
, RS
, RB
} },
4310 { "sr.", XRC(31,536,1), X_MASK
, PWRCOM
, { RA
, RS
, RB
} },
4312 { "rrib", XRC(31,537,0), X_MASK
, M601
, { RA
, RS
, RB
} },
4313 { "rrib.", XRC(31,537,1), X_MASK
, M601
, { RA
, RS
, RB
} },
4315 { "srd", XRC(31,539,0), X_MASK
, PPC64
, { RA
, RS
, RB
} },
4316 { "srd.", XRC(31,539,1), X_MASK
, PPC64
, { RA
, RS
, RB
} },
4318 { "maskir", XRC(31,541,0), X_MASK
, M601
, { RA
, RS
, RB
} },
4319 { "maskir.", XRC(31,541,1), X_MASK
, M601
, { RA
, RS
, RB
} },
4321 { "lwbrxe", X(31,542), X_MASK
, BOOKE64
, { RT
, RA0
, RB
} },
4323 { "lfsxe", X(31,543), X_MASK
, BOOKE64
, { FRT
, RA0
, RB
} },
4325 { "bbelr", X(31,550), X_MASK
, PPCBRLK
, { 0 }},
4327 { "tlbsync", X(31,566), 0xffffffff, PPC
, { 0 } },
4329 { "lfsux", X(31,567), X_MASK
, COM
, { FRT
, RAS
, RB
} },
4331 { "lfsuxe", X(31,575), X_MASK
, BOOKE64
, { FRT
, RAS
, RB
} },
4333 { "mfsr", X(31,595), XRB_MASK
|(1<<20), COM32
, { RT
, SR
} },
4335 { "lswi", X(31,597), X_MASK
, PPCCOM
, { RT
, RA0
, NB
} },
4336 { "lsi", X(31,597), X_MASK
, PWRCOM
, { RT
, RA0
, NB
} },
4338 { "lwsync", XSYNC(31,598,1), 0xffffffff, PPC
, { 0 } },
4339 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64
, { 0 } },
4340 { "msync", X(31,598), 0xffffffff, BOOKE
, { 0 } },
4341 { "sync", X(31,598), XSYNC_MASK
, PPCCOM
, { LS
} },
4342 { "dcs", X(31,598), 0xffffffff, PWRCOM
, { 0 } },
4344 { "lfdx", X(31,599), X_MASK
, COM
, { FRT
, RA0
, RB
} },
4346 { "lfdxe", X(31,607), X_MASK
, BOOKE64
, { FRT
, RA0
, RB
} },
4348 { "mffgpr", XRC(31,607,0), XRA_MASK
, POWER6
, { FRT
, RB
} },
4350 { "mfsri", X(31,627), X_MASK
, PWRCOM
, { RT
, RA
, RB
} },
4352 { "dclst", X(31,630), XRB_MASK
, PWRCOM
, { RS
, RA
} },
4354 { "lfdux", X(31,631), X_MASK
, COM
, { FRT
, RAS
, RB
} },
4356 { "lfduxe", X(31,639), X_MASK
, BOOKE64
, { FRT
, RAS
, RB
} },
4358 { "mfsrin", X(31,659), XRA_MASK
, PPC32
, { RT
, RB
} },
4360 { "stdbrx", X(31,660), X_MASK
, CELL
, { RS
, RA0
, RB
} },
4362 { "stswx", X(31,661), X_MASK
, PPCCOM
, { RS
, RA0
, RB
} },
4363 { "stsx", X(31,661), X_MASK
, PWRCOM
, { RS
, RA0
, RB
} },
4365 { "stwbrx", X(31,662), X_MASK
, PPCCOM
, { RS
, RA0
, RB
} },
4366 { "stbrx", X(31,662), X_MASK
, PWRCOM
, { RS
, RA0
, RB
} },
4368 { "stfsx", X(31,663), X_MASK
, COM
, { FRS
, RA0
, RB
} },
4370 { "srq", XRC(31,664,0), X_MASK
, M601
, { RA
, RS
, RB
} },
4371 { "srq.", XRC(31,664,1), X_MASK
, M601
, { RA
, RS
, RB
} },
4373 { "sre", XRC(31,665,0), X_MASK
, M601
, { RA
, RS
, RB
} },
4374 { "sre.", XRC(31,665,1), X_MASK
, M601
, { RA
, RS
, RB
} },
4376 { "stwbrxe", X(31,670), X_MASK
, BOOKE64
, { RS
, RA0
, RB
} },
4378 { "stfsxe", X(31,671), X_MASK
, BOOKE64
, { FRS
, RA0
, RB
} },
4380 { "stfsux", X(31,695), X_MASK
, COM
, { FRS
, RAS
, RB
} },
4382 { "sriq", XRC(31,696,0), X_MASK
, M601
, { RA
, RS
, SH
} },
4383 { "sriq.", XRC(31,696,1), X_MASK
, M601
, { RA
, RS
, SH
} },
4385 { "stfsuxe", X(31,703), X_MASK
, BOOKE64
, { FRS
, RAS
, RB
} },
4387 { "stswi", X(31,725), X_MASK
, PPCCOM
, { RS
, RA0
, NB
} },
4388 { "stsi", X(31,725), X_MASK
, PWRCOM
, { RS
, RA0
, NB
} },
4390 { "stfdx", X(31,727), X_MASK
, COM
, { FRS
, RA0
, RB
} },
4392 { "srlq", XRC(31,728,0), X_MASK
, M601
, { RA
, RS
, RB
} },
4393 { "srlq.", XRC(31,728,1), X_MASK
, M601
, { RA
, RS
, RB
} },
4395 { "sreq", XRC(31,729,0), X_MASK
, M601
, { RA
, RS
, RB
} },
4396 { "sreq.", XRC(31,729,1), X_MASK
, M601
, { RA
, RS
, RB
} },
4398 { "stfdxe", X(31,735), X_MASK
, BOOKE64
, { FRS
, RA0
, RB
} },
4400 { "mftgpr", XRC(31,735,0), XRA_MASK
, POWER6
, { RT
, FRB
} },
4402 { "dcba", X(31,758), XRT_MASK
, PPC405
| BOOKE
, { RA
, RB
} },
4404 { "stfdux", X(31,759), X_MASK
, COM
, { FRS
, RAS
, RB
} },
4406 { "srliq", XRC(31,760,0), X_MASK
, M601
, { RA
, RS
, SH
} },
4407 { "srliq.", XRC(31,760,1), X_MASK
, M601
, { RA
, RS
, SH
} },
4409 { "dcbae", X(31,766), XRT_MASK
, BOOKE64
, { RA
, RB
} },
4411 { "stfduxe", X(31,767), X_MASK
, BOOKE64
, { FRS
, RAS
, RB
} },
4413 { "tlbivax", X(31,786), XRT_MASK
, BOOKE
, { RA
, RB
} },
4414 { "tlbivaxe",X(31,787), XRT_MASK
, BOOKE64
, { RA
, RB
} },
4416 { "lwzcix", X(31,789), X_MASK
, POWER6
, { RT
, RA0
, RB
} },
4418 { "lhbrx", X(31,790), X_MASK
, COM
, { RT
, RA0
, RB
} },
4420 { "sraw", XRC(31,792,0), X_MASK
, PPCCOM
, { RA
, RS
, RB
} },
4421 { "sra", XRC(31,792,0), X_MASK
, PWRCOM
, { RA
, RS
, RB
} },
4422 { "sraw.", XRC(31,792,1), X_MASK
, PPCCOM
, { RA
, RS
, RB
} },
4423 { "sra.", XRC(31,792,1), X_MASK
, PWRCOM
, { RA
, RS
, RB
} },
4425 { "srad", XRC(31,794,0), X_MASK
, PPC64
, { RA
, RS
, RB
} },
4426 { "srad.", XRC(31,794,1), X_MASK
, PPC64
, { RA
, RS
, RB
} },
4428 { "lhbrxe", X(31,798), X_MASK
, BOOKE64
, { RT
, RA0
, RB
} },
4430 { "ldxe", X(31,799), X_MASK
, BOOKE64
, { RT
, RA0
, RB
} },
4431 { "lduxe", X(31,831), X_MASK
, BOOKE64
, { RT
, RA0
, RB
} },
4433 { "rac", X(31,818), X_MASK
, PWRCOM
, { RT
, RA
, RB
} },
4435 { "lhzcix", X(31,821), X_MASK
, POWER6
, { RT
, RA0
, RB
} },
4437 { "dss", XDSS(31,822,0), XDSS_MASK
, PPCVEC
, { STRM
} },
4438 { "dssall", XDSS(31,822,1), XDSS_MASK
, PPCVEC
, { 0 } },
4440 { "srawi", XRC(31,824,0), X_MASK
, PPCCOM
, { RA
, RS
, SH
} },
4441 { "srai", XRC(31,824,0), X_MASK
, PWRCOM
, { RA
, RS
, SH
} },
4442 { "srawi.", XRC(31,824,1), X_MASK
, PPCCOM
, { RA
, RS
, SH
} },
4443 { "srai.", XRC(31,824,1), X_MASK
, PWRCOM
, { RA
, RS
, SH
} },
4445 { "slbmfev", X(31,851), XRA_MASK
, PPC64
, { RT
, RB
} },
4447 { "lbzcix", X(31,853), X_MASK
, POWER6
, { RT
, RA0
, RB
} },
4449 { "mbar", X(31,854), X_MASK
, BOOKE
, { MO
} },
4450 { "eieio", X(31,854), 0xffffffff, PPC
, { 0 } },
4452 { "lfiwax", X(31,855), X_MASK
, POWER6
, { FRT
, RA0
, RB
} },
4454 { "ldcix", X(31,885), X_MASK
, POWER6
, { RT
, RA0
, RB
} },
4456 { "tlbsx", XRC(31,914,0), X_MASK
, PPC403
|BOOKE
, { RTO
, RA
, RB
} },
4457 { "tlbsx.", XRC(31,914,1), X_MASK
, PPC403
|BOOKE
, { RTO
, RA
, RB
} },
4458 { "tlbsxe", XRC(31,915,0), X_MASK
, BOOKE64
, { RTO
, RA
, RB
} },
4459 { "tlbsxe.", XRC(31,915,1), X_MASK
, BOOKE64
, { RTO
, RA
, RB
} },
4461 { "slbmfee", X(31,915), XRA_MASK
, PPC64
, { RT
, RB
} },
4463 { "stwcix", X(31,917), X_MASK
, POWER6
, { RS
, RA0
, RB
} },
4465 { "sthbrx", X(31,918), X_MASK
, COM
, { RS
, RA0
, RB
} },
4467 { "sraq", XRC(31,920,0), X_MASK
, M601
, { RA
, RS
, RB
} },
4468 { "sraq.", XRC(31,920,1), X_MASK
, M601
, { RA
, RS
, RB
} },
4470 { "srea", XRC(31,921,0), X_MASK
, M601
, { RA
, RS
, RB
} },
4471 { "srea.", XRC(31,921,1), X_MASK
, M601
, { RA
, RS
, RB
} },
4473 { "extsh", XRC(31,922,0), XRB_MASK
, PPCCOM
, { RA
, RS
} },
4474 { "exts", XRC(31,922,0), XRB_MASK
, PWRCOM
, { RA
, RS
} },
4475 { "extsh.", XRC(31,922,1), XRB_MASK
, PPCCOM
, { RA
, RS
} },
4476 { "exts.", XRC(31,922,1), XRB_MASK
, PWRCOM
, { RA
, RS
} },
4478 { "sthbrxe", X(31,926), X_MASK
, BOOKE64
, { RS
, RA0
, RB
} },
4480 { "stdxe", X(31,927), X_MASK
, BOOKE64
, { RS
, RA0
, RB
} },
4482 { "tlbrehi", XTLB(31,946,0), XTLB_MASK
, PPC403
, { RT
, RA
} },
4483 { "tlbrelo", XTLB(31,946,1), XTLB_MASK
, PPC403
, { RT
, RA
} },
4484 { "tlbre", X(31,946), X_MASK
, PPC403
|BOOKE
, { RSO
, RAOPT
, SHO
} },
4486 { "sthcix", X(31,949), X_MASK
, POWER6
, { RS
, RA0
, RB
} },
4488 { "sraiq", XRC(31,952,0), X_MASK
, M601
, { RA
, RS
, SH
} },
4489 { "sraiq.", XRC(31,952,1), X_MASK
, M601
, { RA
, RS
, SH
} },
4491 { "extsb", XRC(31,954,0), XRB_MASK
, PPC
, { RA
, RS
} },
4492 { "extsb.", XRC(31,954,1), XRB_MASK
, PPC
, { RA
, RS
} },
4494 { "stduxe", X(31,959), X_MASK
, BOOKE64
, { RS
, RAS
, RB
} },
4496 { "iccci", X(31,966), XRT_MASK
, PPC403
|PPC440
, { RA
, RB
} },
4498 { "tlbwehi", XTLB(31,978,0), XTLB_MASK
, PPC403
, { RT
, RA
} },
4499 { "tlbwelo", XTLB(31,978,1), XTLB_MASK
, PPC403
, { RT
, RA
} },
4500 { "tlbwe", X(31,978), X_MASK
, PPC403
|BOOKE
, { RSO
, RAOPT
, SHO
} },
4501 { "tlbld", X(31,978), XRTRA_MASK
, PPC
, { RB
} },
4503 { "stbcix", X(31,981), X_MASK
, POWER6
, { RS
, RA0
, RB
} },
4505 { "icbi", X(31,982), XRT_MASK
, PPC
, { RA
, RB
} },
4507 { "stfiwx", X(31,983), X_MASK
, PPC
, { FRS
, RA0
, RB
} },
4509 { "extsw", XRC(31,986,0), XRB_MASK
, PPC64
| BOOKE64
,{ RA
, RS
} },
4510 { "extsw.", XRC(31,986,1), XRB_MASK
, PPC64
, { RA
, RS
} },
4512 { "icread", X(31,998), XRT_MASK
, PPC403
|PPC440
, { RA
, RB
} },
4514 { "icbie", X(31,990), XRT_MASK
, BOOKE64
, { RA
, RB
} },
4515 { "stfiwxe", X(31,991), X_MASK
, BOOKE64
, { FRS
, RA0
, RB
} },
4517 { "tlbli", X(31,1010), XRTRA_MASK
, PPC
, { RB
} },
4519 { "stdcix", X(31,1013), X_MASK
, POWER6
, { RS
, RA0
, RB
} },
4521 { "dcbzl", XOPL(31,1014,1), XRT_MASK
,POWER4
, { RA
, RB
} },
4522 { "dcbz", X(31,1014), XRT_MASK
, PPC
, { RA
, RB
} },
4523 { "dclz", X(31,1014), XRT_MASK
, PPC
, { RA
, RB
} },
4525 { "dcbze", X(31,1022), XRT_MASK
, BOOKE64
, { RA
, RB
} },
4527 { "lvebx", X(31, 7), X_MASK
, PPCVEC
, { VD
, RA
, RB
} },
4528 { "lvehx", X(31, 39), X_MASK
, PPCVEC
, { VD
, RA
, RB
} },
4529 { "lvewx", X(31, 71), X_MASK
, PPCVEC
, { VD
, RA
, RB
} },
4530 { "lvsl", X(31, 6), X_MASK
, PPCVEC
, { VD
, RA
, RB
} },
4531 { "lvsr", X(31, 38), X_MASK
, PPCVEC
, { VD
, RA
, RB
} },
4532 { "lvx", X(31, 103), X_MASK
, PPCVEC
, { VD
, RA
, RB
} },
4533 { "lvxl", X(31, 359), X_MASK
, PPCVEC
, { VD
, RA
, RB
} },
4534 { "stvebx", X(31, 135), X_MASK
, PPCVEC
, { VS
, RA
, RB
} },
4535 { "stvehx", X(31, 167), X_MASK
, PPCVEC
, { VS
, RA
, RB
} },
4536 { "stvewx", X(31, 199), X_MASK
, PPCVEC
, { VS
, RA
, RB
} },
4537 { "stvx", X(31, 231), X_MASK
, PPCVEC
, { VS
, RA
, RB
} },
4538 { "stvxl", X(31, 487), X_MASK
, PPCVEC
, { VS
, RA
, RB
} },
4540 /* New load/store left/right index vector instructions that are in the Cell only. */
4541 { "lvlx", X(31, 519), X_MASK
, CELL
, { VD
, RA0
, RB
} },
4542 { "lvlxl", X(31, 775), X_MASK
, CELL
, { VD
, RA0
, RB
} },
4543 { "lvrx", X(31, 551), X_MASK
, CELL
, { VD
, RA0
, RB
} },
4544 { "lvrxl", X(31, 807), X_MASK
, CELL
, { VD
, RA0
, RB
} },
4545 { "stvlx", X(31, 647), X_MASK
, CELL
, { VS
, RA0
, RB
} },
4546 { "stvlxl", X(31, 903), X_MASK
, CELL
, { VS
, RA0
, RB
} },
4547 { "stvrx", X(31, 679), X_MASK
, CELL
, { VS
, RA0
, RB
} },
4548 { "stvrxl", X(31, 935), X_MASK
, CELL
, { VS
, RA0
, RB
} },
4550 { "lwz", OP(32), OP_MASK
, PPCCOM
, { RT
, D
, RA0
} },
4551 { "l", OP(32), OP_MASK
, PWRCOM
, { RT
, D
, RA0
} },
4553 { "lwzu", OP(33), OP_MASK
, PPCCOM
, { RT
, D
, RAL
} },
4554 { "lu", OP(33), OP_MASK
, PWRCOM
, { RT
, D
, RA0
} },
4556 { "lbz", OP(34), OP_MASK
, COM
, { RT
, D
, RA0
} },
4558 { "lbzu", OP(35), OP_MASK
, COM
, { RT
, D
, RAL
} },
4560 { "stw", OP(36), OP_MASK
, PPCCOM
, { RS
, D
, RA0
} },
4561 { "st", OP(36), OP_MASK
, PWRCOM
, { RS
, D
, RA0
} },
4563 { "stwu", OP(37), OP_MASK
, PPCCOM
, { RS
, D
, RAS
} },
4564 { "stu", OP(37), OP_MASK
, PWRCOM
, { RS
, D
, RA0
} },
4566 { "stb", OP(38), OP_MASK
, COM
, { RS
, D
, RA0
} },
4568 { "stbu", OP(39), OP_MASK
, COM
, { RS
, D
, RAS
} },
4570 { "lhz", OP(40), OP_MASK
, COM
, { RT
, D
, RA0
} },
4572 { "lhzu", OP(41), OP_MASK
, COM
, { RT
, D
, RAL
} },
4574 { "lha", OP(42), OP_MASK
, COM
, { RT
, D
, RA0
} },
4576 { "lhau", OP(43), OP_MASK
, COM
, { RT
, D
, RAL
} },
4578 { "sth", OP(44), OP_MASK
, COM
, { RS
, D
, RA0
} },
4580 { "sthu", OP(45), OP_MASK
, COM
, { RS
, D
, RAS
} },
4582 { "lmw", OP(46), OP_MASK
, PPCCOM
, { RT
, D
, RAM
} },
4583 { "lm", OP(46), OP_MASK
, PWRCOM
, { RT
, D
, RA0
} },
4585 { "stmw", OP(47), OP_MASK
, PPCCOM
, { RS
, D
, RA0
} },
4586 { "stm", OP(47), OP_MASK
, PWRCOM
, { RS
, D
, RA0
} },
4588 { "lfs", OP(48), OP_MASK
, COM
, { FRT
, D
, RA0
} },
4590 { "lfsu", OP(49), OP_MASK
, COM
, { FRT
, D
, RAS
} },
4592 { "lfd", OP(50), OP_MASK
, COM
, { FRT
, D
, RA0
} },
4594 { "lfdu", OP(51), OP_MASK
, COM
, { FRT
, D
, RAS
} },
4596 { "stfs", OP(52), OP_MASK
, COM
, { FRS
, D
, RA0
} },
4598 { "stfsu", OP(53), OP_MASK
, COM
, { FRS
, D
, RAS
} },
4600 { "stfd", OP(54), OP_MASK
, COM
, { FRS
, D
, RA0
} },
4602 { "stfdu", OP(55), OP_MASK
, COM
, { FRS
, D
, RAS
} },
4604 { "lq", OP(56), OP_MASK
, POWER4
, { RTQ
, DQ
, RAQ
} },
4606 { "lfq", OP(56), OP_MASK
, POWER2
, { FRT
, D
, RA0
} },
4608 { "lfqu", OP(57), OP_MASK
, POWER2
, { FRT
, D
, RA0
} },
4610 { "lfdp", OP(57), OP_MASK
, POWER6
, { FRT
, D
, RA0
} },
4612 { "lbze", DEO(58,0), DE_MASK
, BOOKE64
, { RT
, DE
, RA0
} },
4613 { "lbzue", DEO(58,1), DE_MASK
, BOOKE64
, { RT
, DE
, RAL
} },
4614 { "lhze", DEO(58,2), DE_MASK
, BOOKE64
, { RT
, DE
, RA0
} },
4615 { "lhzue", DEO(58,3), DE_MASK
, BOOKE64
, { RT
, DE
, RAL
} },
4616 { "lhae", DEO(58,4), DE_MASK
, BOOKE64
, { RT
, DE
, RA0
} },
4617 { "lhaue", DEO(58,5), DE_MASK
, BOOKE64
, { RT
, DE
, RAL
} },
4618 { "lwze", DEO(58,6), DE_MASK
, BOOKE64
, { RT
, DE
, RA0
} },
4619 { "lwzue", DEO(58,7), DE_MASK
, BOOKE64
, { RT
, DE
, RAL
} },
4620 { "stbe", DEO(58,8), DE_MASK
, BOOKE64
, { RS
, DE
, RA0
} },
4621 { "stbue", DEO(58,9), DE_MASK
, BOOKE64
, { RS
, DE
, RAS
} },
4622 { "sthe", DEO(58,10), DE_MASK
, BOOKE64
, { RS
, DE
, RA0
} },
4623 { "sthue", DEO(58,11), DE_MASK
, BOOKE64
, { RS
, DE
, RAS
} },
4624 { "stwe", DEO(58,14), DE_MASK
, BOOKE64
, { RS
, DE
, RA0
} },
4625 { "stwue", DEO(58,15), DE_MASK
, BOOKE64
, { RS
, DE
, RAS
} },
4627 { "ld", DSO(58,0), DS_MASK
, PPC64
, { RT
, DS
, RA0
} },
4629 { "ldu", DSO(58,1), DS_MASK
, PPC64
, { RT
, DS
, RAL
} },
4631 { "lwa", DSO(58,2), DS_MASK
, PPC64
, { RT
, DS
, RA0
} },
4633 { "dadd", XRC(59,2,0), X_MASK
, POWER6
, { FRT
, FRA
, FRB
} },
4634 { "dadd.", XRC(59,2,1), X_MASK
, POWER6
, { FRT
, FRA
, FRB
} },
4636 { "dqua", ZRC(59,3,0), Z2_MASK
, POWER6
, { FRT
, FRA
, FRB
, RMC
} },
4637 { "dqua.", ZRC(59,3,1), Z2_MASK
, POWER6
, { FRT
, FRA
, FRB
, RMC
} },
4639 { "fdivs", A(59,18,0), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
4640 { "fdivs.", A(59,18,1), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
4642 { "fsubs", A(59,20,0), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
4643 { "fsubs.", A(59,20,1), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
4645 { "fadds", A(59,21,0), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
4646 { "fadds.", A(59,21,1), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
4648 { "fsqrts", A(59,22,0), AFRAFRC_MASK
, PPC
, { FRT
, FRB
} },
4649 { "fsqrts.", A(59,22,1), AFRAFRC_MASK
, PPC
, { FRT
, FRB
} },
4651 { "fres", A(59,24,0), AFRALFRC_MASK
, PPC
, { FRT
, FRB
, A_L
} },
4652 { "fres.", A(59,24,1), AFRALFRC_MASK
, PPC
, { FRT
, FRB
, A_L
} },
4654 { "fmuls", A(59,25,0), AFRB_MASK
, PPC
, { FRT
, FRA
, FRC
} },
4655 { "fmuls.", A(59,25,1), AFRB_MASK
, PPC
, { FRT
, FRA
, FRC
} },
4657 { "frsqrtes", A(59,26,0), AFRALFRC_MASK
,POWER5
, { FRT
, FRB
, A_L
} },
4658 { "frsqrtes.",A(59,26,1), AFRALFRC_MASK
,POWER5
, { FRT
, FRB
, A_L
} },
4660 { "fmsubs", A(59,28,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
4661 { "fmsubs.", A(59,28,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
4663 { "fmadds", A(59,29,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
4664 { "fmadds.", A(59,29,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
4666 { "fnmsubs", A(59,30,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
4667 { "fnmsubs.",A(59,30,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
4669 { "fnmadds", A(59,31,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
4670 { "fnmadds.",A(59,31,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
4672 { "dmul", XRC(59,34,0), X_MASK
, POWER6
, { FRT
, FRA
, FRB
} },
4673 { "dmul.", XRC(59,34,1), X_MASK
, POWER6
, { FRT
, FRA
, FRB
} },
4675 { "drrnd", ZRC(59,35,0), Z2_MASK
, POWER6
, { FRT
, FRA
, FRB
, RMC
} },
4676 { "drrnd.", ZRC(59,35,1), Z2_MASK
, POWER6
, { FRT
, FRA
, FRB
, RMC
} },
4678 { "dscli", ZRC(59,66,0), Z_MASK
, POWER6
, { FRT
, FRA
, SH16
} },
4679 { "dscli.", ZRC(59,66,1), Z_MASK
, POWER6
, { FRT
, FRA
, SH16
} },
4681 { "dquai", ZRC(59,67,0), Z2_MASK
, POWER6
, { TE
, FRT
, FRB
, RMC
} },
4682 { "dquai.", ZRC(59,67,1), Z2_MASK
, POWER6
, { TE
, FRT
, FRB
, RMC
} },
4684 { "dscri", ZRC(59,98,0), Z_MASK
, POWER6
, { FRT
, FRA
, SH16
} },
4685 { "dscri.", ZRC(59,98,1), Z_MASK
, POWER6
, { FRT
, FRA
, SH16
} },
4687 { "drintx", ZRC(59,99,0), Z2_MASK
, POWER6
, { R
, FRT
, FRB
, RMC
} },
4688 { "drintx.", ZRC(59,99,1), Z2_MASK
, POWER6
, { R
, FRT
, FRB
, RMC
} },
4690 { "dcmpo", X(59,130), X_MASK
, POWER6
, { BF
, FRA
, FRB
} },
4692 { "dtstex", X(59,162), X_MASK
, POWER6
, { BF
, FRA
, FRB
} },
4693 { "dtstdc", Z(59,194), Z_MASK
, POWER6
, { BF
, FRA
, DCM
} },
4694 { "dtstdg", Z(59,226), Z_MASK
, POWER6
, { BF
, FRA
, DGM
} },
4696 { "drintn", ZRC(59,227,0), Z2_MASK
, POWER6
, { R
, FRT
, FRB
, RMC
} },
4697 { "drintn.", ZRC(59,227,1), Z2_MASK
, POWER6
, { R
, FRT
, FRB
, RMC
} },
4699 { "dctdp", XRC(59,258,0), X_MASK
, POWER6
, { FRT
, FRB
} },
4700 { "dctdp.", XRC(59,258,1), X_MASK
, POWER6
, { FRT
, FRB
} },
4702 { "dctfix", XRC(59,290,0), X_MASK
, POWER6
, { FRT
, FRB
} },
4703 { "dctfix.", XRC(59,290,1), X_MASK
, POWER6
, { FRT
, FRB
} },
4705 { "ddedpd", XRC(59,322,0), X_MASK
, POWER6
, { SP
, FRT
, FRB
} },
4706 { "ddedpd.", XRC(59,322,1), X_MASK
, POWER6
, { SP
, FRT
, FRB
} },
4708 { "dxex", XRC(59,354,0), X_MASK
, POWER6
, { FRT
, FRB
} },
4709 { "dxex.", XRC(59,354,1), X_MASK
, POWER6
, { FRT
, FRB
} },
4711 { "dsub", XRC(59,514,0), X_MASK
, POWER6
, { FRT
, FRA
, FRB
} },
4712 { "dsub.", XRC(59,514,1), X_MASK
, POWER6
, { FRT
, FRA
, FRB
} },
4714 { "ddiv", XRC(59,546,0), X_MASK
, POWER6
, { FRT
, FRA
, FRB
} },
4715 { "ddiv.", XRC(59,546,1), X_MASK
, POWER6
, { FRT
, FRA
, FRB
} },
4717 { "dcmpu", X(59,642), X_MASK
, POWER6
, { BF
, FRA
, FRB
} },
4719 { "dtstsf", X(59,674), X_MASK
, POWER6
, { BF
, FRA
, FRB
} },
4721 { "drsp", XRC(59,770,0), X_MASK
, POWER6
, { FRT
, FRB
} },
4722 { "drsp.", XRC(59,770,1), X_MASK
, POWER6
, { FRT
, FRB
} },
4724 { "dcffix", XRC(59,802,0), X_MASK
, POWER6
, { FRT
, FRB
} },
4725 { "dcffix.", XRC(59,802,1), X_MASK
, POWER6
, { FRT
, FRB
} },
4727 { "denbcd", XRC(59,834,0), X_MASK
, POWER6
, { S
, FRT
, FRB
} },
4728 { "denbcd.", XRC(59,834,1), X_MASK
, POWER6
, { S
, FRT
, FRB
} },
4730 { "diex", XRC(59,866,0), X_MASK
, POWER6
, { FRT
, FRA
, FRB
} },
4731 { "diex.", XRC(59,866,1), X_MASK
, POWER6
, { FRT
, FRA
, FRB
} },
4733 { "stfq", OP(60), OP_MASK
, POWER2
, { FRS
, D
, RA
} },
4735 { "stfqu", OP(61), OP_MASK
, POWER2
, { FRS
, D
, RA
} },
4737 { "stfdp", OP(61), OP_MASK
, POWER6
, { FRT
, D
, RA0
} },
4739 { "lde", DEO(62,0), DE_MASK
, BOOKE64
, { RT
, DES
, RA0
} },
4740 { "ldue", DEO(62,1), DE_MASK
, BOOKE64
, { RT
, DES
, RA0
} },
4741 { "lfse", DEO(62,4), DE_MASK
, BOOKE64
, { FRT
, DES
, RA0
} },
4742 { "lfsue", DEO(62,5), DE_MASK
, BOOKE64
, { FRT
, DES
, RAS
} },
4743 { "lfde", DEO(62,6), DE_MASK
, BOOKE64
, { FRT
, DES
, RA0
} },
4744 { "lfdue", DEO(62,7), DE_MASK
, BOOKE64
, { FRT
, DES
, RAS
} },
4745 { "stde", DEO(62,8), DE_MASK
, BOOKE64
, { RS
, DES
, RA0
} },
4746 { "stdue", DEO(62,9), DE_MASK
, BOOKE64
, { RS
, DES
, RAS
} },
4747 { "stfse", DEO(62,12), DE_MASK
, BOOKE64
, { FRS
, DES
, RA0
} },
4748 { "stfsue", DEO(62,13), DE_MASK
, BOOKE64
, { FRS
, DES
, RAS
} },
4749 { "stfde", DEO(62,14), DE_MASK
, BOOKE64
, { FRS
, DES
, RA0
} },
4750 { "stfdue", DEO(62,15), DE_MASK
, BOOKE64
, { FRS
, DES
, RAS
} },
4752 { "std", DSO(62,0), DS_MASK
, PPC64
, { RS
, DS
, RA0
} },
4754 { "stdu", DSO(62,1), DS_MASK
, PPC64
, { RS
, DS
, RAS
} },
4756 { "stq", DSO(62,2), DS_MASK
, POWER4
, { RSQ
, DS
, RA0
} },
4758 { "fcmpu", X(63,0), X_MASK
|(3<<21), COM
, { BF
, FRA
, FRB
} },
4760 { "daddq", XRC(63,2,0), X_MASK
, POWER6
, { FRT
, FRA
, FRB
} },
4761 { "daddq.", XRC(63,2,1), X_MASK
, POWER6
, { FRT
, FRA
, FRB
} },
4763 { "dquaq", ZRC(63,3,0), Z2_MASK
, POWER6
, { FRT
, FRA
, FRB
, RMC
} },
4764 { "dquaq.", ZRC(63,3,1), Z2_MASK
, POWER6
, { FRT
, FRA
, FRB
, RMC
} },
4766 { "fcpsgn", XRC(63,8,0), X_MASK
, POWER6
, { FRT
, FRA
, FRB
} },
4767 { "fcpsgn.", XRC(63,8,1), X_MASK
, POWER6
, { FRT
, FRA
, FRB
} },
4769 { "frsp", XRC(63,12,0), XRA_MASK
, COM
, { FRT
, FRB
} },
4770 { "frsp.", XRC(63,12,1), XRA_MASK
, COM
, { FRT
, FRB
} },
4772 { "fctiw", XRC(63,14,0), XRA_MASK
, PPCCOM
, { FRT
, FRB
} },
4773 { "fcir", XRC(63,14,0), XRA_MASK
, POWER2
, { FRT
, FRB
} },
4774 { "fctiw.", XRC(63,14,1), XRA_MASK
, PPCCOM
, { FRT
, FRB
} },
4775 { "fcir.", XRC(63,14,1), XRA_MASK
, POWER2
, { FRT
, FRB
} },
4777 { "fctiwz", XRC(63,15,0), XRA_MASK
, PPCCOM
, { FRT
, FRB
} },
4778 { "fcirz", XRC(63,15,0), XRA_MASK
, POWER2
, { FRT
, FRB
} },
4779 { "fctiwz.", XRC(63,15,1), XRA_MASK
, PPCCOM
, { FRT
, FRB
} },
4780 { "fcirz.", XRC(63,15,1), XRA_MASK
, POWER2
, { FRT
, FRB
} },
4782 { "fdiv", A(63,18,0), AFRC_MASK
, PPCCOM
, { FRT
, FRA
, FRB
} },
4783 { "fd", A(63,18,0), AFRC_MASK
, PWRCOM
, { FRT
, FRA
, FRB
} },
4784 { "fdiv.", A(63,18,1), AFRC_MASK
, PPCCOM
, { FRT
, FRA
, FRB
} },
4785 { "fd.", A(63,18,1), AFRC_MASK
, PWRCOM
, { FRT
, FRA
, FRB
} },
4787 { "fsub", A(63,20,0), AFRC_MASK
, PPCCOM
, { FRT
, FRA
, FRB
} },
4788 { "fs", A(63,20,0), AFRC_MASK
, PWRCOM
, { FRT
, FRA
, FRB
} },
4789 { "fsub.", A(63,20,1), AFRC_MASK
, PPCCOM
, { FRT
, FRA
, FRB
} },
4790 { "fs.", A(63,20,1), AFRC_MASK
, PWRCOM
, { FRT
, FRA
, FRB
} },
4792 { "fadd", A(63,21,0), AFRC_MASK
, PPCCOM
, { FRT
, FRA
, FRB
} },
4793 { "fa", A(63,21,0), AFRC_MASK
, PWRCOM
, { FRT
, FRA
, FRB
} },
4794 { "fadd.", A(63,21,1), AFRC_MASK
, PPCCOM
, { FRT
, FRA
, FRB
} },
4795 { "fa.", A(63,21,1), AFRC_MASK
, PWRCOM
, { FRT
, FRA
, FRB
} },
4797 { "fsqrt", A(63,22,0), AFRAFRC_MASK
, PPCPWR2
, { FRT
, FRB
} },
4798 { "fsqrt.", A(63,22,1), AFRAFRC_MASK
, PPCPWR2
, { FRT
, FRB
} },
4800 { "fsel", A(63,23,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
4801 { "fsel.", A(63,23,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
4803 { "fre", A(63,24,0), AFRALFRC_MASK
, POWER5
, { FRT
, FRB
, A_L
} },
4804 { "fre.", A(63,24,1), AFRALFRC_MASK
, POWER5
, { FRT
, FRB
, A_L
} },
4806 { "fmul", A(63,25,0), AFRB_MASK
, PPCCOM
, { FRT
, FRA
, FRC
} },
4807 { "fm", A(63,25,0), AFRB_MASK
, PWRCOM
, { FRT
, FRA
, FRC
} },
4808 { "fmul.", A(63,25,1), AFRB_MASK
, PPCCOM
, { FRT
, FRA
, FRC
} },
4809 { "fm.", A(63,25,1), AFRB_MASK
, PWRCOM
, { FRT
, FRA
, FRC
} },
4811 { "frsqrte", A(63,26,0), AFRALFRC_MASK
, PPC
, { FRT
, FRB
, A_L
} },
4812 { "frsqrte.",A(63,26,1), AFRALFRC_MASK
, PPC
, { FRT
, FRB
, A_L
} },
4814 { "fmsub", A(63,28,0), A_MASK
, PPCCOM
, { FRT
,FRA
,FRC
,FRB
} },
4815 { "fms", A(63,28,0), A_MASK
, PWRCOM
, { FRT
,FRA
,FRC
,FRB
} },
4816 { "fmsub.", A(63,28,1), A_MASK
, PPCCOM
, { FRT
,FRA
,FRC
,FRB
} },
4817 { "fms.", A(63,28,1), A_MASK
, PWRCOM
, { FRT
,FRA
,FRC
,FRB
} },
4819 { "fmadd", A(63,29,0), A_MASK
, PPCCOM
, { FRT
,FRA
,FRC
,FRB
} },
4820 { "fma", A(63,29,0), A_MASK
, PWRCOM
, { FRT
,FRA
,FRC
,FRB
} },
4821 { "fmadd.", A(63,29,1), A_MASK
, PPCCOM
, { FRT
,FRA
,FRC
,FRB
} },
4822 { "fma.", A(63,29,1), A_MASK
, PWRCOM
, { FRT
,FRA
,FRC
,FRB
} },
4824 { "fnmsub", A(63,30,0), A_MASK
, PPCCOM
, { FRT
,FRA
,FRC
,FRB
} },
4825 { "fnms", A(63,30,0), A_MASK
, PWRCOM
, { FRT
,FRA
,FRC
,FRB
} },
4826 { "fnmsub.", A(63,30,1), A_MASK
, PPCCOM
, { FRT
,FRA
,FRC
,FRB
} },
4827 { "fnms.", A(63,30,1), A_MASK
, PWRCOM
, { FRT
,FRA
,FRC
,FRB
} },
4829 { "fnmadd", A(63,31,0), A_MASK
, PPCCOM
, { FRT
,FRA
,FRC
,FRB
} },
4830 { "fnma", A(63,31,0), A_MASK
, PWRCOM
, { FRT
,FRA
,FRC
,FRB
} },
4831 { "fnmadd.", A(63,31,1), A_MASK
, PPCCOM
, { FRT
,FRA
,FRC
,FRB
} },
4832 { "fnma.", A(63,31,1), A_MASK
, PWRCOM
, { FRT
,FRA
,FRC
,FRB
} },
4834 { "fcmpo", X(63,32), X_MASK
|(3<<21), COM
, { BF
, FRA
, FRB
} },
4836 { "dmulq", XRC(63,34,0), X_MASK
, POWER6
, { FRT
, FRA
, FRB
} },
4837 { "dmulq.", XRC(63,34,1), X_MASK
, POWER6
, { FRT
, FRA
, FRB
} },
4839 { "drrndq", ZRC(63,35,0), Z2_MASK
, POWER6
, { FRT
, FRA
, FRB
, RMC
} },
4840 { "drrndq.", ZRC(63,35,1), Z2_MASK
, POWER6
, { FRT
, FRA
, FRB
, RMC
} },
4842 { "mtfsb1", XRC(63,38,0), XRARB_MASK
, COM
, { BT
} },
4843 { "mtfsb1.", XRC(63,38,1), XRARB_MASK
, COM
, { BT
} },
4845 { "fneg", XRC(63,40,0), XRA_MASK
, COM
, { FRT
, FRB
} },
4846 { "fneg.", XRC(63,40,1), XRA_MASK
, COM
, { FRT
, FRB
} },
4848 { "mcrfs", X(63,64), XRB_MASK
|(3<<21)|(3<<16), COM
, { BF
, BFA
} },
4850 { "dscliq", ZRC(63,66,0), Z_MASK
, POWER6
, { FRT
, FRA
, SH16
} },
4851 { "dscliq.", ZRC(63,66,1), Z_MASK
, POWER6
, { FRT
, FRA
, SH16
} },
4853 { "dquaiq", ZRC(63,67,0), Z2_MASK
, POWER6
, { TE
, FRT
, FRB
, RMC
} },
4854 { "dquaiq.", ZRC(63,67,1), Z2_MASK
, POWER6
, { FRT
, FRA
, FRB
, RMC
} },
4856 { "mtfsb0", XRC(63,70,0), XRARB_MASK
, COM
, { BT
} },
4857 { "mtfsb0.", XRC(63,70,1), XRARB_MASK
, COM
, { BT
} },
4859 { "fmr", XRC(63,72,0), XRA_MASK
, COM
, { FRT
, FRB
} },
4860 { "fmr.", XRC(63,72,1), XRA_MASK
, COM
, { FRT
, FRB
} },
4862 { "dscriq", ZRC(63,98,0), Z_MASK
, POWER6
, { FRT
, FRA
, SH16
} },
4863 { "dscriq.", ZRC(63,98,1), Z_MASK
, POWER6
, { FRT
, FRA
, SH16
} },
4865 { "drintxq", ZRC(63,99,0), Z2_MASK
, POWER6
, { R
, FRT
, FRB
, RMC
} },
4866 { "drintxq.",ZRC(63,99,1), Z2_MASK
, POWER6
, { R
, FRT
, FRB
, RMC
} },
4868 { "dcmpoq", X(63,130), X_MASK
, POWER6
, { BF
, FRA
, FRB
} },
4870 { "mtfsfi", XRC(63,134,0), XRA_MASK
|(3<<21)|(1<<11), COM
, { BF
, U
} },
4871 { "mtfsfi.", XRC(63,134,1), XRA_MASK
|(3<<21)|(1<<11), COM
, { BF
, U
} },
4873 { "fnabs", XRC(63,136,0), XRA_MASK
, COM
, { FRT
, FRB
} },
4874 { "fnabs.", XRC(63,136,1), XRA_MASK
, COM
, { FRT
, FRB
} },
4876 { "dtstexq", X(63,162), X_MASK
, POWER6
, { BF
, FRA
, FRB
} },
4877 { "dtstdcq", Z(63,194), Z_MASK
, POWER6
, { BF
, FRA
, DCM
} },
4878 { "dtstdgq", Z(63,226), Z_MASK
, POWER6
, { BF
, FRA
, DGM
} },
4880 { "drintnq", ZRC(63,227,0), Z2_MASK
, POWER6
, { R
, FRT
, FRB
, RMC
} },
4881 { "drintnq.",ZRC(63,227,1), Z2_MASK
, POWER6
, { R
, FRT
, FRB
, RMC
} },
4883 { "dctqpq", XRC(63,258,0), X_MASK
, POWER6
, { FRT
, FRB
} },
4884 { "dctqpq.", XRC(63,258,1), X_MASK
, POWER6
, { FRT
, FRB
} },
4886 { "fabs", XRC(63,264,0), XRA_MASK
, COM
, { FRT
, FRB
} },
4887 { "fabs.", XRC(63,264,1), XRA_MASK
, COM
, { FRT
, FRB
} },
4889 { "dctfixq", XRC(63,290,0), X_MASK
, POWER6
, { FRT
, FRB
} },
4890 { "dctfixq.",XRC(63,290,1), X_MASK
, POWER6
, { FRT
, FRB
} },
4892 { "ddedpdq", XRC(63,322,0), X_MASK
, POWER6
, { SP
, FRT
, FRB
} },
4893 { "ddedpdq.",XRC(63,322,1), X_MASK
, POWER6
, { SP
, FRT
, FRB
} },
4895 { "dxexq", XRC(63,354,0), X_MASK
, POWER6
, { FRT
, FRB
} },
4896 { "dxexq.", XRC(63,354,1), X_MASK
, POWER6
, { FRT
, FRB
} },
4898 { "frin", XRC(63,392,0), XRA_MASK
, POWER5
, { FRT
, FRB
} },
4899 { "frin.", XRC(63,392,1), XRA_MASK
, POWER5
, { FRT
, FRB
} },
4900 { "friz", XRC(63,424,0), XRA_MASK
, POWER5
, { FRT
, FRB
} },
4901 { "friz.", XRC(63,424,1), XRA_MASK
, POWER5
, { FRT
, FRB
} },
4902 { "frip", XRC(63,456,0), XRA_MASK
, POWER5
, { FRT
, FRB
} },
4903 { "frip.", XRC(63,456,1), XRA_MASK
, POWER5
, { FRT
, FRB
} },
4904 { "frim", XRC(63,488,0), XRA_MASK
, POWER5
, { FRT
, FRB
} },
4905 { "frim.", XRC(63,488,1), XRA_MASK
, POWER5
, { FRT
, FRB
} },
4907 { "dsubq", XRC(63,514,0), X_MASK
, POWER6
, { FRT
, FRA
, FRB
} },
4908 { "dsubq.", XRC(63,514,1), X_MASK
, POWER6
, { FRT
, FRA
, FRB
} },
4910 { "ddivq", XRC(63,546,0), X_MASK
, POWER6
, { FRT
, FRA
, FRB
} },
4911 { "ddivq.", XRC(63,546,1), X_MASK
, POWER6
, { FRT
, FRA
, FRB
} },
4913 { "mffs", XRC(63,583,0), XRARB_MASK
, COM
, { FRT
} },
4914 { "mffs.", XRC(63,583,1), XRARB_MASK
, COM
, { FRT
} },
4916 { "dcmpuq", X(63,642), X_MASK
, POWER6
, { BF
, FRA
, FRB
} },
4918 { "dtstsfq", X(63,674), X_MASK
, POWER6
, { BF
, FRA
, FRB
} },
4920 { "mtfsf", XFL(63,711,0), XFL_MASK
, COM
, { FLM
, FRB
} },
4921 { "mtfsf.", XFL(63,711,1), XFL_MASK
, COM
, { FLM
, FRB
} },
4923 { "drdpq", XRC(63,770,0), X_MASK
, POWER6
, { FRT
, FRB
} },
4924 { "drdpq.", XRC(63,770,1), X_MASK
, POWER6
, { FRT
, FRB
} },
4926 { "dcffixq", XRC(63,802,0), X_MASK
, POWER6
, { FRT
, FRB
} },
4927 { "dcffixq.",XRC(63,802,1), X_MASK
, POWER6
, { FRT
, FRB
} },
4929 { "fctid", XRC(63,814,0), XRA_MASK
, PPC64
, { FRT
, FRB
} },
4930 { "fctid.", XRC(63,814,1), XRA_MASK
, PPC64
, { FRT
, FRB
} },
4932 { "fctidz", XRC(63,815,0), XRA_MASK
, PPC64
, { FRT
, FRB
} },
4933 { "fctidz.", XRC(63,815,1), XRA_MASK
, PPC64
, { FRT
, FRB
} },
4935 { "denbcdq", XRC(63,834,0), X_MASK
, POWER6
, { S
, FRT
, FRB
} },
4936 { "denbcdq.",XRC(63,834,1), X_MASK
, POWER6
, { S
, FRT
, FRB
} },
4938 { "fcfid", XRC(63,846,0), XRA_MASK
, PPC64
, { FRT
, FRB
} },
4939 { "fcfid.", XRC(63,846,1), XRA_MASK
, PPC64
, { FRT
, FRB
} },
4941 { "diexq", XRC(63,866,0), X_MASK
, POWER6
, { FRT
, FRA
, FRB
} },
4942 { "diexq.", XRC(63,866,1), X_MASK
, POWER6
, { FRT
, FRA
, FRB
} },
4946 const int powerpc_num_opcodes
=
4947 sizeof (powerpc_opcodes
) / sizeof (powerpc_opcodes
[0]);
4949 /* The macro table. This is only used by the assembler. */
4951 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4952 when x=0; 32-x when x is between 1 and 31; are negative if x is
4953 negative; and are 32 or more otherwise. This is what you want
4954 when, for instance, you are emulating a right shift by a
4955 rotate-left-and-mask, because the underlying instructions support
4956 shifts of size 0 but not shifts of size 32. By comparison, when
4957 extracting x bits from some word you want to use just 32-x, because
4958 the underlying instructions don't support extracting 0 bits but do
4959 support extracting the whole word (32 bits in this case). */
4961 const struct powerpc_macro powerpc_macros
[] = {
4962 { "extldi", 4, PPC64
, "rldicr %0,%1,%3,(%2)-1" },
4963 { "extldi.", 4, PPC64
, "rldicr. %0,%1,%3,(%2)-1" },
4964 { "extrdi", 4, PPC64
, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4965 { "extrdi.", 4, PPC64
, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4966 { "insrdi", 4, PPC64
, "rldimi %0,%1,64-((%2)+(%3)),%3" },
4967 { "insrdi.", 4, PPC64
, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4968 { "rotrdi", 3, PPC64
, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4969 { "rotrdi.", 3, PPC64
, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4970 { "sldi", 3, PPC64
, "rldicr %0,%1,%2,63-(%2)" },
4971 { "sldi.", 3, PPC64
, "rldicr. %0,%1,%2,63-(%2)" },
4972 { "srdi", 3, PPC64
, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4973 { "srdi.", 3, PPC64
, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4974 { "clrrdi", 3, PPC64
, "rldicr %0,%1,0,63-(%2)" },
4975 { "clrrdi.", 3, PPC64
, "rldicr. %0,%1,0,63-(%2)" },
4976 { "clrlsldi",4, PPC64
, "rldic %0,%1,%3,(%2)-(%3)" },
4977 { "clrlsldi.",4, PPC64
, "rldic. %0,%1,%3,(%2)-(%3)" },
4979 { "extlwi", 4, PPCCOM
, "rlwinm %0,%1,%3,0,(%2)-1" },
4980 { "extlwi.", 4, PPCCOM
, "rlwinm. %0,%1,%3,0,(%2)-1" },
4981 { "extrwi", 4, PPCCOM
, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4982 { "extrwi.", 4, PPCCOM
, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4983 { "inslwi", 4, PPCCOM
, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4984 { "inslwi.", 4, PPCCOM
, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4985 { "insrwi", 4, PPCCOM
, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4986 { "insrwi.", 4, PPCCOM
, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4987 { "rotrwi", 3, PPCCOM
, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4988 { "rotrwi.", 3, PPCCOM
, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4989 { "slwi", 3, PPCCOM
, "rlwinm %0,%1,%2,0,31-(%2)" },
4990 { "sli", 3, PWRCOM
, "rlinm %0,%1,%2,0,31-(%2)" },
4991 { "slwi.", 3, PPCCOM
, "rlwinm. %0,%1,%2,0,31-(%2)" },
4992 { "sli.", 3, PWRCOM
, "rlinm. %0,%1,%2,0,31-(%2)" },
4993 { "srwi", 3, PPCCOM
, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4994 { "sri", 3, PWRCOM
, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4995 { "srwi.", 3, PPCCOM
, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4996 { "sri.", 3, PWRCOM
, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4997 { "clrrwi", 3, PPCCOM
, "rlwinm %0,%1,0,0,31-(%2)" },
4998 { "clrrwi.", 3, PPCCOM
, "rlwinm. %0,%1,0,0,31-(%2)" },
4999 { "clrlslwi",4, PPCCOM
, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
5000 { "clrlslwi.",4, PPCCOM
, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
5003 const int powerpc_num_macros
=
5004 sizeof (powerpc_macros
) / sizeof (powerpc_macros
[0]);