opcodes/ppc-opc.c

   1 /* ppc-opc.c -- PowerPC opcode list
   2    Copyright (C) 1994-2015 Free Software Foundation, Inc.
   3    Written by Ian Lance Taylor, Cygnus Support
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING.  If not, write to the
  19    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  20    MA 02110-1301, USA.  */
  21
  22 #include "sysdep.h"
  23 #include <stdio.h>
  24 #include "opcode/ppc.h"
  25 #include "opintl.h"
  26
  27 /* This file holds the PowerPC opcode table.  The opcode table
  28    includes almost all of the extended instruction mnemonics.  This
  29    permits the disassembler to use them, and simplifies the assembler
  30    logic, at the cost of increasing the table size.  The table is
  31    strictly constant data, so the compiler should be able to put it in
  32    the .text section.
  33
  34    This file also holds the operand table.  All knowledge about
  35    inserting operands into instructions and vice-versa is kept in this
  36    file.  */
  37 \f
  38 /* Local insertion and extraction functions.  */
  39
  40 static unsigned long insert_arx (unsigned long, long, ppc_cpu_t, const char **);
  41 static long extract_arx (unsigned long, ppc_cpu_t, int *);
  42 static unsigned long insert_ary (unsigned long, long, ppc_cpu_t, const char **);
  43 static long extract_ary (unsigned long, ppc_cpu_t, int *);
  44 static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **);
  45 static long extract_bat (unsigned long, ppc_cpu_t, int *);
  46 static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **);
  47 static long extract_bba (unsigned long, ppc_cpu_t, int *);
  48 static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **);
  49 static long extract_bdm (unsigned long, ppc_cpu_t, int *);
  50 static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **);
  51 static long extract_bdp (unsigned long, ppc_cpu_t, int *);
  52 static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **);
  53 static long extract_bo (unsigned long, ppc_cpu_t, int *);
  54 static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **);
  55 static long extract_boe (unsigned long, ppc_cpu_t, int *);
  56 static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
  57 static long extract_fxm (unsigned long, ppc_cpu_t, int *);
  58 static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **);
  59 static long extract_li20 (unsigned long, ppc_cpu_t, int *);
  60 static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **);
  61 static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **);
  62 static long extract_mbe (unsigned long, ppc_cpu_t, int *);
  63 static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **);
  64 static long extract_mb6 (unsigned long, ppc_cpu_t, int *);
  65 static long extract_nb (unsigned long, ppc_cpu_t, int *);
  66 static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t, const char **);
  67 static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **);
  68 static long extract_nsi (unsigned long, ppc_cpu_t, int *);
  69 static unsigned long insert_oimm (unsigned long, long, ppc_cpu_t, const char **);
  70 static long extract_oimm (unsigned long, ppc_cpu_t, int *);
  71 static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **);
  72 static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **);
  73 static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **);
  74 static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **);
  75 static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **);
  76 static long extract_rbs (unsigned long, ppc_cpu_t, int *);
  77 static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t, const char **);
  78 static unsigned long insert_rx (unsigned long, long, ppc_cpu_t, const char **);
  79 static long extract_rx (unsigned long, ppc_cpu_t, int *);
  80 static unsigned long insert_ry (unsigned long, long, ppc_cpu_t, const char **);
  81 static long extract_ry (unsigned long, ppc_cpu_t, int *);
  82 static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **);
  83 static long extract_sh6 (unsigned long, ppc_cpu_t, int *);
  84 static unsigned long insert_sci8 (unsigned long, long, ppc_cpu_t, const char **);
  85 static long extract_sci8 (unsigned long, ppc_cpu_t, int *);
  86 static unsigned long insert_sci8n (unsigned long, long, ppc_cpu_t, const char **);
  87 static long extract_sci8n (unsigned long, ppc_cpu_t, int *);
  88 static unsigned long insert_sd4h (unsigned long, long, ppc_cpu_t, const char **);
  89 static long extract_sd4h (unsigned long, ppc_cpu_t, int *);
  90 static unsigned long insert_sd4w (unsigned long, long, ppc_cpu_t, const char **);
  91 static long extract_sd4w (unsigned long, ppc_cpu_t, int *);
  92 static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **);
  93 static long extract_spr (unsigned long, ppc_cpu_t, int *);
  94 static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **);
  95 static long extract_sprg (unsigned long, ppc_cpu_t, int *);
  96 static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **);
  97 static long extract_tbr (unsigned long, ppc_cpu_t, int *);
  98 static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **);
  99 static long extract_xt6 (unsigned long, ppc_cpu_t, int *);
 100 static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **);
 101 static long extract_xa6 (unsigned long, ppc_cpu_t, int *);
 102 static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **);
 103 static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
 104 static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
 105 static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
 106 static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **);
 107 static long extract_xc6 (unsigned long, ppc_cpu_t, int *);
 108 static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **);
 109 static long extract_dm (unsigned long, ppc_cpu_t, int *);
 110 static unsigned long insert_vlesi (unsigned long, long, ppc_cpu_t, const char **);
 111 static long extract_vlesi (unsigned long, ppc_cpu_t, int *);
 112 static unsigned long insert_vlensi (unsigned long, long, ppc_cpu_t, const char **);
 113 static long extract_vlensi (unsigned long, ppc_cpu_t, int *);
 114 static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t, const char **);
 115 static long extract_vleui (unsigned long, ppc_cpu_t, int *);
 116 static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t, const char **);
 117 static long extract_vleil (unsigned long, ppc_cpu_t, int *);
 118 \f
 119 /* The operands table.
 120
 121    The fields are bitm, shift, insert, extract, flags.
 122
 123    We used to put parens around the various additions, like the one
 124    for BA just below.  However, that caused trouble with feeble
 125    compilers with a limit on depth of a parenthesized expression, like
 126    (reportedly) the compiler in Microsoft Developer Studio 5.  So we
 127    omit the parens, since the macros are never used in a context where
 128    the addition will be ambiguous.  */
 129
 130 const struct powerpc_operand powerpc_operands[] =
 131 {
 132   /* The zero index is used to indicate the end of the list of
 133      operands.  */
 134 #define UNUSED 0
 135   { 0, 0, NULL, NULL, 0 },
 136
 137   /* The BA field in an XL form instruction.  */
 138 #define BA UNUSED + 1
 139   /* The BI field in a B form or XL form instruction.  */
 140 #define BI BA
 141 #define BI_MASK (0x1f << 16)
 142   { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
 143
 144   /* The BA field in an XL form instruction when it must be the same
 145      as the BT field in the same instruction.  */
 146 #define BAT BA + 1
 147   { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
 148
 149   /* The BB field in an XL form instruction.  */
 150 #define BB BAT + 1
 151 #define BB_MASK (0x1f << 11)
 152   { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT },
 153
 154   /* The BB field in an XL form instruction when it must be the same
 155      as the BA field in the same instruction.  */
 156 #define BBA BB + 1
 157   /* The VB field in a VX form instruction when it must be the same
 158      as the VA field in the same instruction.  */
 159 #define VBA BBA
 160   { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
 161
 162   /* The BD field in a B form instruction.  The lower two bits are
 163      forced to zero.  */
 164 #define BD BBA + 1
 165   { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 166
 167   /* The BD field in a B form instruction when absolute addressing is
 168      used.  */
 169 #define BDA BD + 1
 170   { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 171
 172   /* The BD field in a B form instruction when the - modifier is used.
 173      This sets the y bit of the BO field appropriately.  */
 174 #define BDM BDA + 1
 175   { 0xfffc, 0, insert_bdm, extract_bdm,
 176       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 177
 178   /* The BD field in a B form instruction when the - modifier is used
 179      and absolute address is used.  */
 180 #define BDMA BDM + 1
 181   { 0xfffc, 0, insert_bdm, extract_bdm,
 182       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 183
 184   /* The BD field in a B form instruction when the + modifier is used.
 185      This sets the y bit of the BO field appropriately.  */
 186 #define BDP BDMA + 1
 187   { 0xfffc, 0, insert_bdp, extract_bdp,
 188       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 189
 190   /* The BD field in a B form instruction when the + modifier is used
 191      and absolute addressing is used.  */
 192 #define BDPA BDP + 1
 193   { 0xfffc, 0, insert_bdp, extract_bdp,
 194       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 195
 196   /* The BF field in an X or XL form instruction.  */
 197 #define BF BDPA + 1
 198   /* The CRFD field in an X form instruction.  */
 199 #define CRFD BF
 200   /* The CRD field in an XL form instruction.  */
 201 #define CRD BF
 202   { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG },
 203
 204   /* The BF field in an X or XL form instruction.  */
 205 #define BFF BF + 1
 206   { 0x7, 23, NULL, NULL, 0 },
 207
 208   /* An optional BF field.  This is used for comparison instructions,
 209      in which an omitted BF field is taken as zero.  */
 210 #define OBF BFF + 1
 211   { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
 212
 213   /* The BFA field in an X or XL form instruction.  */
 214 #define BFA OBF + 1
 215   { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG },
 216
 217   /* The BO field in a B form instruction.  Certain values are
 218      illegal.  */
 219 #define BO BFA + 1
 220 #define BO_MASK (0x1f << 21)
 221   { 0x1f, 21, insert_bo, extract_bo, 0 },
 222
 223   /* The BO field in a B form instruction when the + or - modifier is
 224      used.  This is like the BO field, but it must be even.  */
 225 #define BOE BO + 1
 226   { 0x1e, 21, insert_boe, extract_boe, 0 },
 227
 228 #define BH BOE + 1
 229   { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
 230
 231   /* The BT field in an X or XL form instruction.  */
 232 #define BT BH + 1
 233   { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT },
 234
 235   /* The BI16 field in a BD8 form instruction.  */
 236 #define BI16 BT + 1
 237   { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT },
 238
 239   /* The BI32 field in a BD15 form instruction.  */
 240 #define BI32 BI16 + 1
 241   { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
 242
 243   /* The BO32 field in a BD15 form instruction.  */
 244 #define BO32 BI32 + 1
 245   { 0x3, 20, NULL, NULL, 0 },
 246
 247   /* The B8 field in a BD8 form instruction.  */
 248 #define B8 BO32 + 1
 249   { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 250
 251   /* The B15 field in a BD15 form instruction.  The lowest bit is
 252      forced to zero.  */
 253 #define B15 B8 + 1
 254   { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 255
 256   /* The B24 field in a BD24 form instruction.  The lowest bit is
 257      forced to zero.  */
 258 #define B24 B15 + 1
 259   { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 260
 261   /* The condition register number portion of the BI field in a B form
 262      or XL form instruction.  This is used for the extended
 263      conditional branch mnemonics, which set the lower two bits of the
 264      BI field.  This field is optional.  */
 265 #define CR B24 + 1
 266   { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
 267
 268   /* The CRB field in an X form instruction.  */
 269 #define CRB CR + 1
 270   /* The MB field in an M form instruction.  */
 271 #define MB CRB
 272 #define MB_MASK (0x1f << 6)
 273   { 0x1f, 6, NULL, NULL, 0 },
 274
 275   /* The CRD32 field in an XL form instruction.  */
 276 #define CRD32 CRB + 1
 277   { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG },
 278
 279   /* The CRFS field in an X form instruction.  */
 280 #define CRFS CRD32 + 1
 281   { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG },
 282
 283 #define CRS CRFS + 1
 284   { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
 285
 286   /* The CT field in an X form instruction.  */
 287 #define CT CRS + 1
 288   /* The MO field in an mbar instruction.  */
 289 #define MO CT
 290   { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 291
 292   /* The D field in a D form instruction.  This is a displacement off
 293      a register, and implies that the next operand is a register in
 294      parentheses.  */
 295 #define D CT + 1
 296   { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 297
 298   /* The D8 field in a D form instruction.  This is a displacement off
 299      a register, and implies that the next operand is a register in
 300      parentheses.  */
 301 #define D8 D + 1
 302   { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 303
 304   /* The DQ field in a DQ form instruction.  This is like D, but the
 305      lower four bits are forced to zero. */
 306 #define DQ D8 + 1
 307   { 0xfff0, 0, NULL, NULL,
 308     PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
 309
 310   /* The DS field in a DS form instruction.  This is like D, but the
 311      lower two bits are forced to zero.  */
 312 #define DS DQ + 1
 313   { 0xfffc, 0, NULL, NULL,
 314     PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
 315
 316   /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits
 317      unsigned imediate */
 318 #define DUIS DS + 1
 319 #define BHRBE DUIS
 320   { 0x3ff, 11, NULL, NULL, 0 },
 321
 322   /* The E field in a wrteei instruction.  */
 323   /* And the W bit in the pair singles instructions.  */
 324   /* And the ST field in a VX form instruction.  */
 325 #define E DUIS + 1
 326 #define PSW E
 327 #define ST E
 328   { 0x1, 15, NULL, NULL, 0 },
 329
 330   /* The FL1 field in a POWER SC form instruction.  */
 331 #define FL1 E + 1
 332   /* The U field in an X form instruction.  */
 333 #define U FL1
 334   { 0xf, 12, NULL, NULL, 0 },
 335
 336   /* The FL2 field in a POWER SC form instruction.  */
 337 #define FL2 FL1 + 1
 338   { 0x7, 2, NULL, NULL, 0 },
 339
 340   /* The FLM field in an XFL form instruction.  */
 341 #define FLM FL2 + 1
 342   { 0xff, 17, NULL, NULL, 0 },
 343
 344   /* The FRA field in an X or A form instruction.  */
 345 #define FRA FLM + 1
 346 #define FRA_MASK (0x1f << 16)
 347   { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
 348
 349   /* The FRAp field of DFP instructions.  */
 350 #define FRAp FRA + 1
 351   { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR },
 352
 353   /* The FRB field in an X or A form instruction.  */
 354 #define FRB FRAp + 1
 355 #define FRB_MASK (0x1f << 11)
 356   { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
 357
 358   /* The FRBp field of DFP instructions.  */
 359 #define FRBp FRB + 1
 360   { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR },
 361
 362   /* The FRC field in an A form instruction.  */
 363 #define FRC FRBp + 1
 364 #define FRC_MASK (0x1f << 6)
 365   { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
 366
 367   /* The FRS field in an X form instruction or the FRT field in a D, X
 368      or A form instruction.  */
 369 #define FRS FRC + 1
 370 #define FRT FRS
 371   { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
 372
 373   /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
 374      instructions.  */
 375 #define FRSp FRS + 1
 376 #define FRTp FRSp
 377   { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR },
 378
 379   /* The FXM field in an XFX instruction.  */
 380 #define FXM FRSp + 1
 381   { 0xff, 12, insert_fxm, extract_fxm, 0 },
 382
 383   /* Power4 version for mfcr.  */
 384 #define FXM4 FXM + 1
 385   { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
 386   /* If the FXM4 operand is ommitted, use the sentinel value -1.  */
 387   { -1, -1, NULL, NULL, 0},
 388
 389   /* The IMM20 field in an LI instruction.  */
 390 #define IMM20 FXM4 + 2
 391   { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED},
 392
 393   /* The L field in a D or X form instruction.  */
 394 #define L IMM20 + 1
 395   /* The R field in a HTM X form instruction.  */
 396 #define HTM_R L
 397   { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 398
 399   /* The LEV field in a POWER SVC form instruction.  */
 400 #define SVC_LEV L + 1
 401   { 0x7f, 5, NULL, NULL, 0 },
 402
 403   /* The LEV field in an SC form instruction.  */
 404 #define LEV SVC_LEV + 1
 405   { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
 406
 407   /* The LI field in an I form instruction.  The lower two bits are
 408      forced to zero.  */
 409 #define LI LEV + 1
 410   { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 411
 412   /* The LI field in an I form instruction when used as an absolute
 413      address.  */
 414 #define LIA LI + 1
 415   { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 416
 417   /* The LS or WC field in an X (sync or wait) form instruction.  */
 418 #define LS LIA + 1
 419 #define WC LS
 420   { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 421
 422   /* The ME field in an M form instruction.  */
 423 #define ME LS + 1
 424 #define ME_MASK (0x1f << 1)
 425   { 0x1f, 1, NULL, NULL, 0 },
 426
 427   /* The MB and ME fields in an M form instruction expressed a single
 428      operand which is a bitmask indicating which bits to select.  This
 429      is a two operand form using PPC_OPERAND_NEXT.  See the
 430      description in opcode/ppc.h for what this means.  */
 431 #define MBE ME + 1
 432   { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
 433   { -1, 0, insert_mbe, extract_mbe, 0 },
 434
 435   /* The MB or ME field in an MD or MDS form instruction.  The high
 436      bit is wrapped to the low end.  */
 437 #define MB6 MBE + 2
 438 #define ME6 MB6
 439 #define MB6_MASK (0x3f << 5)
 440   { 0x3f, 5, insert_mb6, extract_mb6, 0 },
 441
 442   /* The NB field in an X form instruction.  The value 32 is stored as
 443      0.  */
 444 #define NB MB6 + 1
 445   { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
 446
 447   /* The NBI field in an lswi instruction, which has special value
 448      restrictions.  The value 32 is stored as 0.  */
 449 #define NBI NB + 1
 450   { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 },
 451
 452   /* The NSI field in a D form instruction.  This is the same as the
 453      SI field, only negated.  */
 454 #define NSI NBI + 1
 455   { 0xffff, 0, insert_nsi, extract_nsi,
 456       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 457
 458   /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction.  */
 459 #define RA NSI + 1
 460 #define RA_MASK (0x1f << 16)
 461   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
 462
 463   /* As above, but 0 in the RA field means zero, not r0.  */
 464 #define RA0 RA + 1
 465   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
 466
 467   /* The RA field in the DQ form lq or an lswx instruction, which have special
 468      value restrictions.  */
 469 #define RAQ RA0 + 1
 470 #define RAX RAQ
 471   { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
 472
 473   /* The RA field in a D or X form instruction which is an updating
 474      load, which means that the RA field may not be zero and may not
 475      equal the RT field.  */
 476 #define RAL RAQ + 1
 477   { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
 478
 479   /* The RA field in an lmw instruction, which has special value
 480      restrictions.  */
 481 #define RAM RAL + 1
 482   { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
 483
 484   /* The RA field in a D or X form instruction which is an updating
 485      store or an updating floating point load, which means that the RA
 486      field may not be zero.  */
 487 #define RAS RAM + 1
 488   { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
 489
 490   /* The RA field of the tlbwe, dccci and iccci instructions,
 491      which are optional.  */
 492 #define RAOPT RAS + 1
 493   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 494
 495   /* The RB field in an X, XO, M, or MDS form instruction.  */
 496 #define RB RAOPT + 1
 497 #define RB_MASK (0x1f << 11)
 498   { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
 499
 500   /* The RB field in an X form instruction when it must be the same as
 501      the RS field in the instruction.  This is used for extended
 502      mnemonics like mr.  */
 503 #define RBS RB + 1
 504   { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
 505
 506   /* The RB field in an lswx instruction, which has special value
 507      restrictions.  */
 508 #define RBX RBS + 1
 509   { 0x1f, 11, insert_rbx, NULL, PPC_OPERAND_GPR },
 510
 511   /* The RB field of the dccci and iccci instructions, which are optional.  */
 512 #define RBOPT RBX + 1
 513   { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 514
 515   /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
 516      instruction or the RT field in a D, DS, X, XFX or XO form
 517      instruction.  */
 518 #define RS RBOPT + 1
 519 #define RT RS
 520 #define RT_MASK (0x1f << 21)
 521 #define RD RS
 522   { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
 523
 524   /* The RS and RT fields of the DS form stq and DQ form lq instructions,
 525      which have special value restrictions.  */
 526 #define RSQ RS + 1
 527 #define RTQ RSQ
 528   { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR },
 529
 530   /* The RS field of the tlbwe instruction, which is optional.  */
 531 #define RSO RSQ + 1
 532 #define RTO RSO
 533   { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 534
 535   /* The RX field of the SE_RR form instruction.  */
 536 #define RX RSO + 1
 537   { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR },
 538
 539   /* The ARX field of the SE_RR form instruction.  */
 540 #define ARX RX + 1
 541   { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR },
 542
 543   /* The RY field of the SE_RR form instruction.  */
 544 #define RY ARX + 1
 545 #define RZ RY
 546   { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR },
 547
 548   /* The ARY field of the SE_RR form instruction.  */
 549 #define ARY RY + 1
 550   { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR },
 551
 552   /* The SCLSCI8 field in a D form instruction.  */
 553 #define SCLSCI8 ARY + 1
 554   { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 },
 555
 556   /* The SCLSCI8N field in a D form instruction.  This is the same as the
 557      SCLSCI8 field, only negated.  */
 558 #define SCLSCI8N SCLSCI8 + 1
 559   { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n,
 560       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 561
 562   /* The SD field of the SD4 form instruction.  */
 563 #define SE_SD SCLSCI8N + 1
 564   { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS },
 565
 566   /* The SD field of the SD4 form instruction, for halfword.  */
 567 #define SE_SDH SE_SD + 1
 568   { 0x1e, PPC_OPSHIFT_INV, insert_sd4h, extract_sd4h, PPC_OPERAND_PARENS },
 569
 570   /* The SD field of the SD4 form instruction, for word.  */
 571 #define SE_SDW SE_SDH + 1
 572   { 0x3c, PPC_OPSHIFT_INV, insert_sd4w, extract_sd4w, PPC_OPERAND_PARENS },
 573
 574   /* The SH field in an X or M form instruction.  */
 575 #define SH SE_SDW + 1
 576 #define SH_MASK (0x1f << 11)
 577   /* The other UIMM field in a EVX form instruction.  */
 578 #define EVUIMM SH
 579   { 0x1f, 11, NULL, NULL, 0 },
 580
 581   /* The SI field in a HTM X form instruction.  */
 582 #define HTM_SI SH + 1
 583   { 0x1f, 11, NULL, NULL, PPC_OPERAND_SIGNED },
 584
 585   /* The SH field in an MD form instruction.  This is split.  */
 586 #define SH6 HTM_SI + 1
 587 #define SH6_MASK ((0x1f << 11) | (1 << 1))
 588   { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 },
 589
 590   /* The SH field of the tlbwe instruction, which is optional.  */
 591 #define SHO SH6 + 1
 592   { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
 593
 594   /* The SI field in a D form instruction.  */
 595 #define SI SHO + 1
 596   { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
 597
 598   /* The SI field in a D form instruction when we accept a wide range
 599      of positive values.  */
 600 #define SISIGNOPT SI + 1
 601   { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 602
 603   /* The SI8 field in a D form instruction.  */
 604 #define SI8 SISIGNOPT + 1
 605   { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
 606
 607   /* The SPR field in an XFX form instruction.  This is flipped--the
 608      lower 5 bits are stored in the upper 5 and vice- versa.  */
 609 #define SPR SI8 + 1
 610 #define PMR SPR
 611 #define TMR SPR
 612 #define SPR_MASK (0x3ff << 11)
 613   { 0x3ff, 11, insert_spr, extract_spr, 0 },
 614
 615   /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
 616 #define SPRBAT SPR + 1
 617 #define SPRBAT_MASK (0x3 << 17)
 618   { 0x3, 17, NULL, NULL, 0 },
 619
 620   /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
 621 #define SPRG SPRBAT + 1
 622   { 0x1f, 16, insert_sprg, extract_sprg, 0 },
 623
 624   /* The SR field in an X form instruction.  */
 625 #define SR SPRG + 1
 626   /* The 4-bit UIMM field in a VX form instruction.  */
 627 #define UIMM4 SR
 628   { 0xf, 16, NULL, NULL, 0 },
 629
 630   /* The STRM field in an X AltiVec form instruction.  */
 631 #define STRM SR + 1
 632   /* The T field in a tlbilx form instruction.  */
 633 #define T STRM
 634   { 0x3, 21, NULL, NULL, 0 },
 635
 636   /* The ESYNC field in an X (sync) form instruction.  */
 637 #define ESYNC STRM + 1
 638   { 0xf, 16, insert_ls, NULL, PPC_OPERAND_OPTIONAL },
 639
 640   /* The SV field in a POWER SC form instruction.  */
 641 #define SV ESYNC + 1
 642   { 0x3fff, 2, NULL, NULL, 0 },
 643
 644   /* The TBR field in an XFX form instruction.  This is like the SPR
 645      field, but it is optional.  */
 646 #define TBR SV + 1
 647   { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
 648   /* If the TBR operand is ommitted, use the value 268.  */
 649   { -1, 268, NULL, NULL, 0},
 650
 651   /* The TO field in a D or X form instruction.  */
 652 #define TO TBR + 2
 653 #define DUI TO
 654 #define TO_MASK (0x1f << 21)
 655   { 0x1f, 21, NULL, NULL, 0 },
 656
 657   /* The UI field in a D form instruction.  */
 658 #define UI TO + 1
 659   { 0xffff, 0, NULL, NULL, 0 },
 660
 661 #define UISIGNOPT UI + 1
 662   { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNOPT },
 663
 664   /* The IMM field in an SE_IM5 instruction.  */
 665 #define UI5 UISIGNOPT + 1
 666   { 0x1f, 4, NULL, NULL, 0 },
 667
 668   /* The OIMM field in an SE_OIM5 instruction.  */
 669 #define OIMM5 UI5 + 1
 670   { 0x1f, PPC_OPSHIFT_INV, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 },
 671
 672   /* The UI7 field in an SE_LI instruction.  */
 673 #define UI7 OIMM5 + 1
 674   { 0x7f, 4, NULL, NULL, 0 },
 675
 676   /* The VA field in a VA, VX or VXR form instruction.  */
 677 #define VA UI7 + 1
 678   { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
 679
 680   /* The VB field in a VA, VX or VXR form instruction.  */
 681 #define VB VA + 1
 682   { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
 683
 684   /* The VC field in a VA form instruction.  */
 685 #define VC VB + 1
 686   { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
 687
 688   /* The VD or VS field in a VA, VX, VXR or X form instruction.  */
 689 #define VD VC + 1
 690 #define VS VD
 691   { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
 692
 693   /* The SIMM field in a VX form instruction, and TE in Z form.  */
 694 #define SIMM VD + 1
 695 #define TE SIMM
 696   { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
 697
 698   /* The UIMM field in a VX form instruction.  */
 699 #define UIMM SIMM + 1
 700 #define DCTL UIMM
 701   { 0x1f, 16, NULL, NULL, 0 },
 702
 703   /* The 3-bit UIMM field in a VX form instruction.  */
 704 #define UIMM3 UIMM + 1
 705   { 0x7, 16, NULL, NULL, 0 },
 706
 707   /* The SIX field in a VX form instruction.  */
 708 #define SIX UIMM3 + 1
 709   { 0xf, 11, NULL, NULL, 0 },
 710
 711   /* The PS field in a VX form instruction.  */
 712 #define PS SIX + 1
 713   { 0x1, 9, NULL, NULL, 0 },
 714
 715   /* The SHB field in a VA form instruction.  */
 716 #define SHB PS + 1
 717   { 0xf, 6, NULL, NULL, 0 },
 718
 719   /* The other UIMM field in a half word EVX form instruction.  */
 720 #define EVUIMM_2 SHB + 1
 721   { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
 722
 723   /* The other UIMM field in a word EVX form instruction.  */
 724 #define EVUIMM_4 EVUIMM_2 + 1
 725   { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
 726
 727   /* The other UIMM field in a double EVX form instruction.  */
 728 #define EVUIMM_8 EVUIMM_4 + 1
 729   { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
 730
 731   /* The WS field.  */
 732 #define WS EVUIMM_8 + 1
 733   { 0x7, 11, NULL, NULL, 0 },
 734
 735   /* PowerPC paired singles extensions.  */
 736   /* W bit in the pair singles instructions for x type instructions.  */
 737 #define PSWM WS + 1
 738   /* The BO16 field in a BD8 form instruction.  */
 739 #define BO16 PSWM
 740   {  0x1, 10, 0, 0, 0 },
 741
 742   /* IDX bits for quantization in the pair singles instructions.  */
 743 #define PSQ PSWM + 1
 744   {  0x7, 12, 0, 0, 0 },
 745
 746   /* IDX bits for quantization in the pair singles x-type instructions.  */
 747 #define PSQM PSQ + 1
 748   {  0x7, 7, 0, 0, 0 },
 749
 750   /* Smaller D field for quantization in the pair singles instructions.  */
 751 #define PSD PSQM + 1
 752   {  0xfff, 0, 0, 0,  PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 753
 754   /* The L field in an mtmsrd or A form instruction or W in an X form.  */
 755 #define A_L PSD + 1
 756 #define W A_L
 757   { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
 758
 759 #define RMC A_L + 1
 760   { 0x3, 9, NULL, NULL, 0 },
 761
 762 #define R RMC + 1
 763   { 0x1, 16, NULL, NULL, 0 },
 764
 765 #define SP R + 1
 766   { 0x3, 19, NULL, NULL, 0 },
 767
 768 #define S SP + 1
 769   { 0x1, 20, NULL, NULL, 0 },
 770
 771   /* The S field in a XL form instruction.  */
 772 #define SXL S + 1
 773   { 0x1, 11, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
 774   /* If the SXL operand is ommitted, use the value 1.  */
 775   { -1, 1, NULL, NULL, 0},
 776
 777   /* SH field starting at bit position 16.  */
 778 #define SH16 SXL + 2
 779   /* The DCM and DGM fields in a Z form instruction.  */
 780 #define DCM SH16
 781 #define DGM DCM
 782   { 0x3f, 10, NULL, NULL, 0 },
 783
 784   /* The EH field in larx instruction.  */
 785 #define EH SH16 + 1
 786   { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
 787
 788   /* The L field in an mtfsf or XFL form instruction.  */
 789   /* The A field in a HTM X form instruction.  */
 790 #define XFL_L EH + 1
 791 #define HTM_A XFL_L
 792   { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
 793
 794   /* Xilinx APU related masks and macros */
 795 #define FCRT XFL_L + 1
 796 #define FCRT_MASK (0x1f << 21)
 797   { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
 798
 799   /* Xilinx FSL related masks and macros */
 800 #define FSL FCRT + 1
 801 #define FSL_MASK (0x1f << 11)
 802   { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
 803
 804   /* Xilinx UDI related masks and macros */
 805 #define URT FSL + 1
 806   { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
 807
 808 #define URA URT + 1
 809   { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
 810
 811 #define URB URA + 1
 812   { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
 813
 814 #define URC URB + 1
 815   { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
 816
 817   /* The VLESIMM field in a D form instruction.  */
 818 #define VLESIMM URC + 1
 819   { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi,
 820       PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 821
 822   /* The VLENSIMM field in a D form instruction.  */
 823 #define VLENSIMM VLESIMM + 1
 824   { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi,
 825       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 826
 827   /* The VLEUIMM field in a D form instruction.  */
 828 #define VLEUIMM VLENSIMM + 1
 829   { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 },
 830
 831   /* The VLEUIMML field in a D form instruction.  */
 832 #define VLEUIMML VLEUIMM + 1
 833   { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 },
 834
 835   /* The XT and XS fields in an XX1 or XX3 form instruction.  This is split.  */
 836 #define XS6 VLEUIMML + 1
 837 #define XT6 XS6
 838   { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
 839
 840   /* The XA field in an XX3 form instruction.  This is split.  */
 841 #define XA6 XT6 + 1
 842   { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
 843
 844   /* The XB field in an XX2 or XX3 form instruction.  This is split.  */
 845 #define XB6 XA6 + 1
 846   { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
 847
 848   /* The XB field in an XX3 form instruction when it must be the same as
 849      the XA field in the instruction.  This is used in extended mnemonics
 850      like xvmovdp.  This is split.  */
 851 #define XB6S XB6 + 1
 852   { 0x3f, PPC_OPSHIFT_INV, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
 853
 854   /* The XC field in an XX4 form instruction.  This is split.  */
 855 #define XC6 XB6S + 1
 856   { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
 857
 858   /* The DM or SHW field in an XX3 form instruction.  */
 859 #define DM XC6 + 1
 860 #define SHW DM
 861   { 0x3, 8, NULL, NULL, 0 },
 862
 863   /* The DM field in an extended mnemonic XX3 form instruction.  */
 864 #define DMEX DM + 1
 865   { 0x3, 8, insert_dm, extract_dm, 0 },
 866
 867   /* The UIM field in an XX2 form instruction.  */
 868 #define UIM DMEX + 1
 869   /* The 2-bit UIMM field in a VX form instruction.  */
 870 #define UIMM2 UIM
 871   { 0x3, 16, NULL, NULL, 0 },
 872
 873 #define ERAT_T UIM + 1
 874   { 0x7, 21, NULL, NULL, 0 },
 875
 876 #define IH ERAT_T + 1
 877   { 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 878 };
 879
 880 const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
 881                                            / sizeof (powerpc_operands[0]));
 882
 883 /* The functions used to insert and extract complicated operands.  */
 884
 885 /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs.  */
 886
 887 static unsigned long
 888 insert_arx (unsigned long insn,
 889             long value,
 890             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 891             const char **errmsg ATTRIBUTE_UNUSED)
 892 {
 893   if (value >= 8 && value < 24)
 894     return insn | ((value - 8) & 0xf);
 895   else
 896     {
 897       *errmsg = _("invalid register");
 898       return 0;
 899     }
 900 }
 901
 902 static long
 903 extract_arx (unsigned long insn,
 904              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 905              int *invalid ATTRIBUTE_UNUSED)
 906 {
 907   return (insn & 0xf) + 8;
 908 }
 909
 910 static unsigned long
 911 insert_ary (unsigned long insn,
 912             long value,
 913             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 914             const char **errmsg ATTRIBUTE_UNUSED)
 915 {
 916   if (value >= 8 && value < 24)
 917     return insn | (((value - 8) & 0xf) << 4);
 918   else
 919     {
 920       *errmsg = _("invalid register");
 921       return 0;
 922     }
 923 }
 924
 925 static long
 926 extract_ary (unsigned long insn,
 927              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 928              int *invalid ATTRIBUTE_UNUSED)
 929 {
 930   return ((insn >> 4) & 0xf) + 8;
 931 }
 932
 933 static unsigned long
 934 insert_rx (unsigned long insn,
 935            long value,
 936            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 937            const char **errmsg)
 938 {
 939   if (value >= 0 && value < 8)
 940     return insn | value;
 941   else if (value >= 24 && value <= 31)
 942     return insn | (value - 16);
 943   else
 944     {
 945       *errmsg = _("invalid register");
 946       return 0;
 947     }
 948 }
 949
 950 static long
 951 extract_rx (unsigned long insn,
 952             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 953             int *invalid ATTRIBUTE_UNUSED)
 954 {
 955   int value = insn & 0xf;
 956   if (value >= 0 && value < 8)
 957     return value;
 958   else
 959     return value + 16;
 960 }
 961
 962 static unsigned long
 963 insert_ry (unsigned long insn,
 964            long value,
 965            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 966            const char **errmsg)
 967 {
 968   if (value >= 0 && value < 8)
 969     return insn | (value << 4);
 970   else if (value >= 24 && value <= 31)
 971     return insn | ((value - 16) << 4);
 972   else
 973     {
 974       *errmsg = _("invalid register");
 975       return 0;
 976     }
 977 }
 978
 979 static long
 980 extract_ry (unsigned long insn,
 981             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 982             int *invalid ATTRIBUTE_UNUSED)
 983 {
 984   int value = (insn >> 4) & 0xf;
 985   if (value >= 0 && value < 8)
 986     return value;
 987   else
 988     return value + 16;
 989 }
 990
 991 /* The BA field in an XL form instruction when it must be the same as
 992    the BT field in the same instruction.  This operand is marked FAKE.
 993    The insertion function just copies the BT field into the BA field,
 994    and the extraction function just checks that the fields are the
 995    same.  */
 996
 997 static unsigned long
 998 insert_bat (unsigned long insn,
 999             long value ATTRIBUTE_UNUSED,
1000             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1001             const char **errmsg ATTRIBUTE_UNUSED)
1002 {
1003   return insn | (((insn >> 21) & 0x1f) << 16);
1004 }
1005
1006 static long
1007 extract_bat (unsigned long insn,
1008              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1009              int *invalid)
1010 {
1011   if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
1012     *invalid = 1;
1013   return 0;
1014 }
1015
1016 /* The BB field in an XL form instruction when it must be the same as
1017    the BA field in the same instruction.  This operand is marked FAKE.
1018    The insertion function just copies the BA field into the BB field,
1019    and the extraction function just checks that the fields are the
1020    same.  */
1021
1022 static unsigned long
1023 insert_bba (unsigned long insn,
1024             long value ATTRIBUTE_UNUSED,
1025             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1026             const char **errmsg ATTRIBUTE_UNUSED)
1027 {
1028   return insn | (((insn >> 16) & 0x1f) << 11);
1029 }
1030
1031 static long
1032 extract_bba (unsigned long insn,
1033              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1034              int *invalid)
1035 {
1036   if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
1037     *invalid = 1;
1038   return 0;
1039 }
1040
1041 /* The BD field in a B form instruction when the - modifier is used.
1042    This modifier means that the branch is not expected to be taken.
1043    For chips built to versions of the architecture prior to version 2
1044    (ie. not Power4 compatible), we set the y bit of the BO field to 1
1045    if the offset is negative.  When extracting, we require that the y
1046    bit be 1 and that the offset be positive, since if the y bit is 0
1047    we just want to print the normal form of the instruction.
1048    Power4 compatible targets use two bits, "a", and "t", instead of
1049    the "y" bit.  "at" == 00 => no hint, "at" == 01 => unpredictable,
1050    "at" == 10 => not taken, "at" == 11 => taken.  The "t" bit is 00001
1051    in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
1052    for branch on CTR.  We only handle the taken/not-taken hint here.
1053    Note that we don't relax the conditions tested here when
1054    disassembling with -Many because insns using extract_bdm and
1055    extract_bdp always occur in pairs.  One or the other will always
1056    be valid.  */
1057
1058 #define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
1059
1060 static unsigned long
1061 insert_bdm (unsigned long insn,
1062             long value,
1063             ppc_cpu_t dialect,
1064             const char **errmsg ATTRIBUTE_UNUSED)
1065 {
1066   if ((dialect & ISA_V2) == 0)
1067     {
1068       if ((value & 0x8000) != 0)
1069         insn |= 1 << 21;
1070     }
1071   else
1072     {
1073       if ((insn & (0x14 << 21)) == (0x04 << 21))
1074         insn |= 0x02 << 21;
1075       else if ((insn & (0x14 << 21)) == (0x10 << 21))
1076         insn |= 0x08 << 21;
1077     }
1078   return insn | (value & 0xfffc);
1079 }
1080
1081 static long
1082 extract_bdm (unsigned long insn,
1083              ppc_cpu_t dialect,
1084              int *invalid)
1085 {
1086   if ((dialect & ISA_V2) == 0)
1087     {
1088       if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
1089         *invalid = 1;
1090     }
1091   else
1092     {
1093       if ((insn & (0x17 << 21)) != (0x06 << 21)
1094           && (insn & (0x1d << 21)) != (0x18 << 21))
1095         *invalid = 1;
1096     }
1097
1098   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1099 }
1100
1101 /* The BD field in a B form instruction when the + modifier is used.
1102    This is like BDM, above, except that the branch is expected to be
1103    taken.  */
1104
1105 static unsigned long
1106 insert_bdp (unsigned long insn,
1107             long value,
1108             ppc_cpu_t dialect,
1109             const char **errmsg ATTRIBUTE_UNUSED)
1110 {
1111   if ((dialect & ISA_V2) == 0)
1112     {
1113       if ((value & 0x8000) == 0)
1114         insn |= 1 << 21;
1115     }
1116   else
1117     {
1118       if ((insn & (0x14 << 21)) == (0x04 << 21))
1119         insn |= 0x03 << 21;
1120       else if ((insn & (0x14 << 21)) == (0x10 << 21))
1121         insn |= 0x09 << 21;
1122     }
1123   return insn | (value & 0xfffc);
1124 }
1125
1126 static long
1127 extract_bdp (unsigned long insn,
1128              ppc_cpu_t dialect,
1129              int *invalid)
1130 {
1131   if ((dialect & ISA_V2) == 0)
1132     {
1133       if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
1134         *invalid = 1;
1135     }
1136   else
1137     {
1138       if ((insn & (0x17 << 21)) != (0x07 << 21)
1139           && (insn & (0x1d << 21)) != (0x19 << 21))
1140         *invalid = 1;
1141     }
1142
1143   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1144 }
1145
1146 static inline int
1147 valid_bo_pre_v2 (long value)
1148 {
1149   /* Certain encodings have bits that are required to be zero.
1150      These are (z must be zero, y may be anything):
1151          0000y
1152          0001y
1153          001zy
1154          0100y
1155          0101y
1156          011zy
1157          1z00y
1158          1z01y
1159          1z1zz
1160   */
1161   if ((value & 0x14) == 0)
1162     return 1;
1163   else if ((value & 0x14) == 0x4)
1164     return (value & 0x2) == 0;
1165   else if ((value & 0x14) == 0x10)
1166     return (value & 0x8) == 0;
1167   else
1168     return value == 0x14;
1169 }
1170
1171 static inline int
1172 valid_bo_post_v2 (long value)
1173 {
1174   /* Certain encodings have bits that are required to be zero.
1175      These are (z must be zero, a & t may be anything):
1176          0000z
1177          0001z
1178          001at
1179          0100z
1180          0101z
1181          011at
1182          1a00t
1183          1a01t
1184          1z1zz
1185   */
1186   if ((value & 0x14) == 0)
1187     return (value & 0x1) == 0;
1188   else if ((value & 0x14) == 0x14)
1189     return value == 0x14;
1190   else
1191     return 1;
1192 }
1193
1194 /* Check for legal values of a BO field.  */
1195
1196 static int
1197 valid_bo (long value, ppc_cpu_t dialect, int extract)
1198 {
1199   int valid_y = valid_bo_pre_v2 (value);
1200   int valid_at = valid_bo_post_v2 (value);
1201
1202   /* When disassembling with -Many, accept either encoding on the
1203      second pass through opcodes.  */
1204   if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY)
1205     return valid_y || valid_at;
1206   if ((dialect & ISA_V2) == 0)
1207     return valid_y;
1208   else
1209     return valid_at;
1210 }
1211
1212 /* The BO field in a B form instruction.  Warn about attempts to set
1213    the field to an illegal value.  */
1214
1215 static unsigned long
1216 insert_bo (unsigned long insn,
1217            long value,
1218            ppc_cpu_t dialect,
1219            const char **errmsg)
1220 {
1221   if (!valid_bo (value, dialect, 0))
1222     *errmsg = _("invalid conditional option");
1223   else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1224     *errmsg = _("invalid counter access");
1225   return insn | ((value & 0x1f) << 21);
1226 }
1227
1228 static long
1229 extract_bo (unsigned long insn,
1230             ppc_cpu_t dialect,
1231             int *invalid)
1232 {
1233   long value;
1234
1235   value = (insn >> 21) & 0x1f;
1236   if (!valid_bo (value, dialect, 1))
1237     *invalid = 1;
1238   return value;
1239 }
1240
1241 /* The BO field in a B form instruction when the + or - modifier is
1242    used.  This is like the BO field, but it must be even.  When
1243    extracting it, we force it to be even.  */
1244
1245 static unsigned long
1246 insert_boe (unsigned long insn,
1247             long value,
1248             ppc_cpu_t dialect,
1249             const char **errmsg)
1250 {
1251   if (!valid_bo (value, dialect, 0))
1252     *errmsg = _("invalid conditional option");
1253   else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1254     *errmsg = _("invalid counter access");
1255   else if ((value & 1) != 0)
1256     *errmsg = _("attempt to set y bit when using + or - modifier");
1257
1258   return insn | ((value & 0x1f) << 21);
1259 }
1260
1261 static long
1262 extract_boe (unsigned long insn,
1263              ppc_cpu_t dialect,
1264              int *invalid)
1265 {
1266   long value;
1267
1268   value = (insn >> 21) & 0x1f;
1269   if (!valid_bo (value, dialect, 1))
1270     *invalid = 1;
1271   return value & 0x1e;
1272 }
1273
1274 /* FXM mask in mfcr and mtcrf instructions.  */
1275
1276 static unsigned long
1277 insert_fxm (unsigned long insn,
1278             long value,
1279             ppc_cpu_t dialect,
1280             const char **errmsg)
1281 {
1282   /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1283      one bit of the mask field is set.  */
1284   if ((insn & (1 << 20)) != 0)
1285     {
1286       if (value == 0 || (value & -value) != value)
1287         {
1288           *errmsg = _("invalid mask field");
1289           value = 0;
1290         }
1291     }
1292
1293   /* If only one bit of the FXM field is set, we can use the new form
1294      of the instruction, which is faster.  Unlike the Power4 branch hint
1295      encoding, this is not backward compatible.  Do not generate the
1296      new form unless -mpower4 has been given, or -many and the two
1297      operand form of mfcr was used.  */
1298   else if (value > 0
1299            && (value & -value) == value
1300            && ((dialect & PPC_OPCODE_POWER4) != 0
1301                || ((dialect & PPC_OPCODE_ANY) != 0
1302                    && (insn & (0x3ff << 1)) == 19 << 1)))
1303     insn |= 1 << 20;
1304
1305   /* Any other value on mfcr is an error.  */
1306   else if ((insn & (0x3ff << 1)) == 19 << 1)
1307     {
1308       /* A value of -1 means we used the one operand form of
1309          mfcr which is valid.  */
1310       if (value != -1)
1311         *errmsg = _("ignoring invalid mfcr mask");
1312       value = 0;
1313     }
1314
1315   return insn | ((value & 0xff) << 12);
1316 }
1317
1318 static long
1319 extract_fxm (unsigned long insn,
1320              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1321              int *invalid)
1322 {
1323   long mask = (insn >> 12) & 0xff;
1324
1325   /* Is this a Power4 insn?  */
1326   if ((insn & (1 << 20)) != 0)
1327     {
1328       /* Exactly one bit of MASK should be set.  */
1329       if (mask == 0 || (mask & -mask) != mask)
1330         *invalid = 1;
1331     }
1332
1333   /* Check that non-power4 form of mfcr has a zero MASK.  */
1334   else if ((insn & (0x3ff << 1)) == 19 << 1)
1335     {
1336       if (mask != 0)
1337         *invalid = 1;
1338       else
1339         mask = -1;
1340     }
1341
1342   return mask;
1343 }
1344
1345 static unsigned long
1346 insert_li20 (unsigned long insn,
1347              long value,
1348              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1349              const char **errmsg ATTRIBUTE_UNUSED)
1350 {
1351   return insn | ((value & 0xf0000) >> 5) | ((value & 0x0f800) << 5) | (value & 0x7ff);
1352 }
1353
1354 static long
1355 extract_li20 (unsigned long insn,
1356               ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1357               int *invalid ATTRIBUTE_UNUSED)
1358 {
1359   long ext = ((insn & 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000;
1360
1361   return ext
1362          | (((insn >> 11) & 0xf) << 16)
1363          | (((insn >> 17) & 0xf) << 12)
1364          | (((insn >> 16) & 0x1) << 11)
1365          | (insn & 0x7ff);
1366 }
1367
1368 /* The LS field in a sync instruction that accepts 2 operands
1369    Values 2 and 3 are reserved,
1370      must be treated as 0 for future compatibility
1371    Values 0 and 1 can be accepted, if field ESYNC is zero
1372    Otherwise L = complement of ESYNC-bit2 (1<<18) */
1373
1374 static unsigned long
1375 insert_ls (unsigned long insn,
1376            long value,
1377            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1378            const char **errmsg ATTRIBUTE_UNUSED)
1379 {
1380   unsigned long ls;
1381
1382   ls = (insn >> 21) & 0x03;
1383   if (value == 0)
1384     {
1385       if (ls > 1)
1386         return insn & ~(0x3 << 21);
1387       return insn;
1388     }
1389   if ((value & 0x2) != 0)
1390     return (insn & ~(0x3 << 21)) | ((value & 0xf) << 16);
1391   return (insn & ~(0x3 << 21)) | (0x1 << 21) | ((value & 0xf) << 16);
1392 }
1393
1394 /* The MB and ME fields in an M form instruction expressed as a single
1395    operand which is itself a bitmask.  The extraction function always
1396    marks it as invalid, since we never want to recognize an
1397    instruction which uses a field of this type.  */
1398
1399 static unsigned long
1400 insert_mbe (unsigned long insn,
1401             long value,
1402             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1403             const char **errmsg)
1404 {
1405   unsigned long uval, mask;
1406   int mb, me, mx, count, last;
1407
1408   uval = value;
1409
1410   if (uval == 0)
1411     {
1412       *errmsg = _("illegal bitmask");
1413       return insn;
1414     }
1415
1416   mb = 0;
1417   me = 32;
1418   if ((uval & 1) != 0)
1419     last = 1;
1420   else
1421     last = 0;
1422   count = 0;
1423
1424   /* mb: location of last 0->1 transition */
1425   /* me: location of last 1->0 transition */
1426   /* count: # transitions */
1427
1428   for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1429     {
1430       if ((uval & mask) && !last)
1431         {
1432           ++count;
1433           mb = mx;
1434           last = 1;
1435         }
1436       else if (!(uval & mask) && last)
1437         {
1438           ++count;
1439           me = mx;
1440           last = 0;
1441         }
1442     }
1443   if (me == 0)
1444     me = 32;
1445
1446   if (count != 2 && (count != 0 || ! last))
1447     *errmsg = _("illegal bitmask");
1448
1449   return insn | (mb << 6) | ((me - 1) << 1);
1450 }
1451
1452 static long
1453 extract_mbe (unsigned long insn,
1454              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1455              int *invalid)
1456 {
1457   long ret;
1458   int mb, me;
1459   int i;
1460
1461   *invalid = 1;
1462
1463   mb = (insn >> 6) & 0x1f;
1464   me = (insn >> 1) & 0x1f;
1465   if (mb < me + 1)
1466     {
1467       ret = 0;
1468       for (i = mb; i <= me; i++)
1469         ret |= 1L << (31 - i);
1470     }
1471   else if (mb == me + 1)
1472     ret = ~0;
1473   else /* (mb > me + 1) */
1474     {
1475       ret = ~0;
1476       for (i = me + 1; i < mb; i++)
1477         ret &= ~(1L << (31 - i));
1478     }
1479   return ret;
1480 }
1481
1482 /* The MB or ME field in an MD or MDS form instruction.  The high bit
1483    is wrapped to the low end.  */
1484
1485 static unsigned long
1486 insert_mb6 (unsigned long insn,
1487             long value,
1488             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1489             const char **errmsg ATTRIBUTE_UNUSED)
1490 {
1491   return insn | ((value & 0x1f) << 6) | (value & 0x20);
1492 }
1493
1494 static long
1495 extract_mb6 (unsigned long insn,
1496              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1497              int *invalid ATTRIBUTE_UNUSED)
1498 {
1499   return ((insn >> 6) & 0x1f) | (insn & 0x20);
1500 }
1501
1502 /* The NB field in an X form instruction.  The value 32 is stored as
1503    0.  */
1504
1505 static long
1506 extract_nb (unsigned long insn,
1507             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1508             int *invalid ATTRIBUTE_UNUSED)
1509 {
1510   long ret;
1511
1512   ret = (insn >> 11) & 0x1f;
1513   if (ret == 0)
1514     ret = 32;
1515   return ret;
1516 }
1517
1518 /* The NB field in an lswi instruction, which has special value
1519    restrictions.  The value 32 is stored as 0.  */
1520
1521 static unsigned long
1522 insert_nbi (unsigned long insn,
1523             long value,
1524             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1525             const char **errmsg ATTRIBUTE_UNUSED)
1526 {
1527   long rtvalue = (insn & RT_MASK) >> 21;
1528   long ravalue = (insn & RA_MASK) >> 16;
1529
1530   if (value == 0)
1531     value = 32;
1532   if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32
1533                                                      : ravalue))
1534     *errmsg = _("address register in load range");
1535   return insn | ((value & 0x1f) << 11);
1536 }
1537
1538 /* The NSI field in a D form instruction.  This is the same as the SI
1539    field, only negated.  The extraction function always marks it as
1540    invalid, since we never want to recognize an instruction which uses
1541    a field of this type.  */
1542
1543 static unsigned long
1544 insert_nsi (unsigned long insn,
1545             long value,
1546             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1547             const char **errmsg ATTRIBUTE_UNUSED)
1548 {
1549   return insn | (-value & 0xffff);
1550 }
1551
1552 static long
1553 extract_nsi (unsigned long insn,
1554              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1555              int *invalid)
1556 {
1557   *invalid = 1;
1558   return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1559 }
1560
1561 /* The RA field in a D or X form instruction which is an updating
1562    load, which means that the RA field may not be zero and may not
1563    equal the RT field.  */
1564
1565 static unsigned long
1566 insert_ral (unsigned long insn,
1567             long value,
1568             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1569             const char **errmsg)
1570 {
1571   if (value == 0
1572       || (unsigned long) value == ((insn >> 21) & 0x1f))
1573     *errmsg = "invalid register operand when updating";
1574   return insn | ((value & 0x1f) << 16);
1575 }
1576
1577 /* The RA field in an lmw instruction, which has special value
1578    restrictions.  */
1579
1580 static unsigned long
1581 insert_ram (unsigned long insn,
1582             long value,
1583             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1584             const char **errmsg)
1585 {
1586   if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1587     *errmsg = _("index register in load range");
1588   return insn | ((value & 0x1f) << 16);
1589 }
1590
1591 /* The RA field in the DQ form lq or an lswx instruction, which have special
1592    value restrictions.  */
1593
1594 static unsigned long
1595 insert_raq (unsigned long insn,
1596             long value,
1597             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1598             const char **errmsg)
1599 {
1600   long rtvalue = (insn & RT_MASK) >> 21;
1601
1602   if (value == rtvalue)
1603     *errmsg = _("source and target register operands must be different");
1604   return insn | ((value & 0x1f) << 16);
1605 }
1606
1607 /* The RA field in a D or X form instruction which is an updating
1608    store or an updating floating point load, which means that the RA
1609    field may not be zero.  */
1610
1611 static unsigned long
1612 insert_ras (unsigned long insn,
1613             long value,
1614             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1615             const char **errmsg)
1616 {
1617   if (value == 0)
1618     *errmsg = _("invalid register operand when updating");
1619   return insn | ((value & 0x1f) << 16);
1620 }
1621
1622 /* The RB field in an X form instruction when it must be the same as
1623    the RS field in the instruction.  This is used for extended
1624    mnemonics like mr.  This operand is marked FAKE.  The insertion
1625    function just copies the BT field into the BA field, and the
1626    extraction function just checks that the fields are the same.  */
1627
1628 static unsigned long
1629 insert_rbs (unsigned long insn,
1630             long value ATTRIBUTE_UNUSED,
1631             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1632             const char **errmsg ATTRIBUTE_UNUSED)
1633 {
1634   return insn | (((insn >> 21) & 0x1f) << 11);
1635 }
1636
1637 static long
1638 extract_rbs (unsigned long insn,
1639              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1640              int *invalid)
1641 {
1642   if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1643     *invalid = 1;
1644   return 0;
1645 }
1646
1647 /* The RB field in an lswx instruction, which has special value
1648    restrictions.  */
1649
1650 static unsigned long
1651 insert_rbx (unsigned long insn,
1652             long value,
1653             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1654             const char **errmsg)
1655 {
1656   long rtvalue = (insn & RT_MASK) >> 21;
1657
1658   if (value == rtvalue)
1659     *errmsg = _("source and target register operands must be different");
1660   return insn | ((value & 0x1f) << 11);
1661 }
1662
1663 /* The SCI8 field is made up of SCL and {U,N}I8 fields.  */
1664 static unsigned long
1665 insert_sci8 (unsigned long insn,
1666              long value,
1667              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1668              const char **errmsg)
1669 {
1670   unsigned int fill_scale = 0;
1671   unsigned long ui8 = value;
1672
1673   if ((ui8 & 0xffffff00) == 0)
1674     ;
1675   else if ((ui8 & 0xffffff00) == 0xffffff00)
1676     fill_scale = 0x400;
1677   else if ((ui8 & 0xffff00ff) == 0)
1678     {
1679       fill_scale = 1 << 8;
1680       ui8 >>= 8;
1681     }
1682   else if ((ui8 & 0xffff00ff) == 0xffff00ff)
1683     {
1684       fill_scale = 0x400 | (1 << 8);
1685       ui8 >>= 8;
1686     }
1687   else if ((ui8 & 0xff00ffff) == 0)
1688     {
1689       fill_scale = 2 << 8;
1690       ui8 >>= 16;
1691     }
1692   else if ((ui8 & 0xff00ffff) == 0xff00ffff)
1693     {
1694       fill_scale = 0x400 | (2 << 8);
1695       ui8 >>= 16;
1696     }
1697   else if ((ui8 & 0x00ffffff) == 0)
1698     {
1699       fill_scale = 3 << 8;
1700       ui8 >>= 24;
1701     }
1702   else if ((ui8 & 0x00ffffff) == 0x00ffffff)
1703     {
1704       fill_scale = 0x400 | (3 << 8);
1705       ui8 >>= 24;
1706     }
1707   else
1708     {
1709       *errmsg = _("illegal immediate value");
1710       ui8 = 0;
1711     }
1712
1713   return insn | fill_scale | (ui8 & 0xff);
1714 }
1715
1716 static long
1717 extract_sci8 (unsigned long insn,
1718               ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1719               int *invalid ATTRIBUTE_UNUSED)
1720 {
1721   int fill = insn & 0x400;
1722   int scale_factor = (insn & 0x300) >> 5;
1723   long value = (insn & 0xff) << scale_factor;
1724
1725   if (fill != 0)
1726     value |= ~((long) 0xff << scale_factor);
1727   return value;
1728 }
1729
1730 static unsigned long
1731 insert_sci8n (unsigned long insn,
1732               long value,
1733               ppc_cpu_t dialect,
1734               const char **errmsg)
1735 {
1736   return insert_sci8 (insn, -value, dialect, errmsg);
1737 }
1738
1739 static long
1740 extract_sci8n (unsigned long insn,
1741                ppc_cpu_t dialect,
1742                int *invalid)
1743 {
1744   return -extract_sci8 (insn, dialect, invalid);
1745 }
1746
1747 static unsigned long
1748 insert_sd4h (unsigned long insn,
1749              long value,
1750              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1751              const char **errmsg ATTRIBUTE_UNUSED)
1752 {
1753   return insn | ((value & 0x1e) << 7);
1754 }
1755
1756 static long
1757 extract_sd4h (unsigned long insn,
1758               ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1759               int *invalid ATTRIBUTE_UNUSED)
1760 {
1761   return ((insn >> 8) & 0xf) << 1;
1762 }
1763
1764 static unsigned long
1765 insert_sd4w (unsigned long insn,
1766              long value,
1767              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1768              const char **errmsg ATTRIBUTE_UNUSED)
1769 {
1770   return insn | ((value & 0x3c) << 6);
1771 }
1772
1773 static long
1774 extract_sd4w (unsigned long insn,
1775               ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1776               int *invalid ATTRIBUTE_UNUSED)
1777 {
1778   return ((insn >> 8) & 0xf) << 2;
1779 }
1780
1781 static unsigned long
1782 insert_oimm (unsigned long insn,
1783              long value,
1784              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1785              const char **errmsg ATTRIBUTE_UNUSED)
1786 {
1787   return insn | (((value - 1) & 0x1f) << 4);
1788 }
1789
1790 static long
1791 extract_oimm (unsigned long insn,
1792               ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1793               int *invalid ATTRIBUTE_UNUSED)
1794 {
1795   return ((insn >> 4) & 0x1f) + 1;
1796 }
1797
1798 /* The SH field in an MD form instruction.  This is split.  */
1799
1800 static unsigned long
1801 insert_sh6 (unsigned long insn,
1802             long value,
1803             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1804             const char **errmsg ATTRIBUTE_UNUSED)
1805 {
1806   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1807 }
1808
1809 static long
1810 extract_sh6 (unsigned long insn,
1811              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1812              int *invalid ATTRIBUTE_UNUSED)
1813 {
1814   return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1815 }
1816
1817 /* The SPR field in an XFX form instruction.  This is flipped--the
1818    lower 5 bits are stored in the upper 5 and vice- versa.  */
1819
1820 static unsigned long
1821 insert_spr (unsigned long insn,
1822             long value,
1823             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1824             const char **errmsg ATTRIBUTE_UNUSED)
1825 {
1826   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1827 }
1828
1829 static long
1830 extract_spr (unsigned long insn,
1831              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1832              int *invalid ATTRIBUTE_UNUSED)
1833 {
1834   return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1835 }
1836
1837 /* Some dialects have 8 SPRG registers instead of the standard 4.  */
1838 #define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405 | PPC_OPCODE_VLE)
1839
1840 static unsigned long
1841 insert_sprg (unsigned long insn,
1842              long value,
1843              ppc_cpu_t dialect,
1844              const char **errmsg)
1845 {
1846   if (value > 7
1847       || (value > 3 && (dialect & ALLOW8_SPRG) == 0))
1848     *errmsg = _("invalid sprg number");
1849
1850   /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1851      user mode.  Anything else must use spr 272..279.  */
1852   if (value <= 3 || (insn & 0x100) != 0)
1853     value |= 0x10;
1854
1855   return insn | ((value & 0x17) << 16);
1856 }
1857
1858 static long
1859 extract_sprg (unsigned long insn,
1860               ppc_cpu_t dialect,
1861               int *invalid)
1862 {
1863   unsigned long val = (insn >> 16) & 0x1f;
1864
1865   /* mfsprg can use 260..263 and 272..279.  mtsprg only uses spr 272..279
1866      If not BOOKE, 405 or VLE, then both use only 272..275.  */
1867   if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0)
1868       || (val - 0x10 > 7 && (insn & 0x100) != 0)
1869       || val <= 3
1870       || (val & 8) != 0)
1871     *invalid = 1;
1872   return val & 7;
1873 }
1874
1875 /* The TBR field in an XFX instruction.  This is just like SPR, but it
1876    is optional.  */
1877
1878 static unsigned long
1879 insert_tbr (unsigned long insn,
1880             long value,
1881             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1882             const char **errmsg)
1883 {
1884   if (value != 268 && value != 269)
1885     *errmsg = _("invalid tbr number");
1886   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1887 }
1888
1889 static long
1890 extract_tbr (unsigned long insn,
1891              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1892              int *invalid)
1893 {
1894   long ret;
1895
1896   ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1897   if (ret != 268 && ret != 269)
1898     *invalid = 1;
1899   return ret;
1900 }
1901
1902 /* The XT and XS fields in an XX1 or XX3 form instruction.  This is split.  */
1903
1904 static unsigned long
1905 insert_xt6 (unsigned long insn,
1906             long value,
1907             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1908             const char **errmsg ATTRIBUTE_UNUSED)
1909 {
1910   return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5);
1911 }
1912
1913 static long
1914 extract_xt6 (unsigned long insn,
1915              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1916              int *invalid ATTRIBUTE_UNUSED)
1917 {
1918   return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
1919 }
1920
1921 /* The XA field in an XX3 form instruction.  This is split.  */
1922
1923 static unsigned long
1924 insert_xa6 (unsigned long insn,
1925             long value,
1926             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1927             const char **errmsg ATTRIBUTE_UNUSED)
1928 {
1929   return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3);
1930 }
1931
1932 static long
1933 extract_xa6 (unsigned long insn,
1934              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1935              int *invalid ATTRIBUTE_UNUSED)
1936 {
1937   return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
1938 }
1939
1940 /* The XB field in an XX3 form instruction.  This is split.  */
1941
1942 static unsigned long
1943 insert_xb6 (unsigned long insn,
1944             long value,
1945             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1946             const char **errmsg ATTRIBUTE_UNUSED)
1947 {
1948   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1949 }
1950
1951 static long
1952 extract_xb6 (unsigned long insn,
1953              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1954              int *invalid ATTRIBUTE_UNUSED)
1955 {
1956   return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f);
1957 }
1958
1959 /* The XB field in an XX3 form instruction when it must be the same as
1960    the XA field in the instruction.  This is used for extended
1961    mnemonics like xvmovdp.  This operand is marked FAKE.  The insertion
1962    function just copies the XA field into the XB field, and the
1963    extraction function just checks that the fields are the same.  */
1964
1965 static unsigned long
1966 insert_xb6s (unsigned long insn,
1967             long value ATTRIBUTE_UNUSED,
1968             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1969             const char **errmsg ATTRIBUTE_UNUSED)
1970 {
1971   return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1);
1972 }
1973
1974 static long
1975 extract_xb6s (unsigned long insn,
1976              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1977              int *invalid)
1978 {
1979   if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
1980       || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1)))
1981     *invalid = 1;
1982   return 0;
1983 }
1984
1985 /* The XC field in an XX4 form instruction.  This is split.  */
1986
1987 static unsigned long
1988 insert_xc6 (unsigned long insn,
1989             long value,
1990             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1991             const char **errmsg ATTRIBUTE_UNUSED)
1992 {
1993   return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2);
1994 }
1995
1996 static long
1997 extract_xc6 (unsigned long insn,
1998              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1999              int *invalid ATTRIBUTE_UNUSED)
2000 {
2001   return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f);
2002 }
2003
2004 static unsigned long
2005 insert_dm (unsigned long insn,
2006            long value,
2007            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2008            const char **errmsg)
2009 {
2010   if (value != 0 && value != 1)
2011     *errmsg = _("invalid constant");
2012   return insn | (((value) ? 3 : 0) << 8);
2013 }
2014
2015 static long
2016 extract_dm (unsigned long insn,
2017             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2018             int *invalid)
2019 {
2020   long value;
2021
2022   value = (insn >> 8) & 3;
2023   if (value != 0 && value != 3)
2024     *invalid = 1;
2025   return (value) ? 1 : 0;
2026 }
2027 /* The VLESIMM field in an I16A form instruction.  This is split.  */
2028
2029 static unsigned long
2030 insert_vlesi (unsigned long insn,
2031             long value,
2032             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2033             const char **errmsg ATTRIBUTE_UNUSED)
2034 {
2035   return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2036 }
2037
2038 static long
2039 extract_vlesi (unsigned long insn,
2040              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2041              int *invalid ATTRIBUTE_UNUSED)
2042 {
2043   long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2044   value = (value ^ 0x8000) - 0x8000;
2045   return value;
2046 }
2047
2048 static unsigned long
2049 insert_vlensi (unsigned long insn,
2050             long value,
2051             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2052             const char **errmsg ATTRIBUTE_UNUSED)
2053 {
2054   value = -value;
2055   return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2056 }
2057 static long
2058 extract_vlensi (unsigned long insn,
2059              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2060              int *invalid ATTRIBUTE_UNUSED)
2061 {
2062   long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2063   value = (value ^ 0x8000) - 0x8000;
2064   /* Don't use for disassembly.  */
2065   *invalid = 1;
2066   return -value;
2067 }
2068
2069 /* The VLEUIMM field in an I16A form instruction.  This is split.  */
2070
2071 static unsigned long
2072 insert_vleui (unsigned long insn,
2073             long value,
2074             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2075             const char **errmsg ATTRIBUTE_UNUSED)
2076 {
2077   return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2078 }
2079
2080 static long
2081 extract_vleui (unsigned long insn,
2082              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2083              int *invalid ATTRIBUTE_UNUSED)
2084 {
2085   return ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2086 }
2087
2088 /* The VLEUIMML field in an I16L form instruction.  This is split.  */
2089
2090 static unsigned long
2091 insert_vleil (unsigned long insn,
2092             long value,
2093             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2094             const char **errmsg ATTRIBUTE_UNUSED)
2095 {
2096   return insn | ((value & 0xf800) << 5) | (value & 0x7ff);
2097 }
2098
2099 static long
2100 extract_vleil (unsigned long insn,
2101              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2102              int *invalid ATTRIBUTE_UNUSED)
2103 {
2104   return ((insn >> 5) & 0xf800) | (insn & 0x7ff);
2105 }
2106
2107 \f
2108 /* Macros used to form opcodes.  */
2109
2110 /* The main opcode.  */
2111 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
2112 #define OP_MASK OP (0x3f)
2113
2114 /* The main opcode combined with a trap code in the TO field of a D
2115    form instruction.  Used for extended mnemonics for the trap
2116    instructions.  */
2117 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
2118 #define OPTO_MASK (OP_MASK | TO_MASK)
2119
2120 /* The main opcode combined with a comparison size bit in the L field
2121    of a D form or X form instruction.  Used for extended mnemonics for
2122    the comparison instructions.  */
2123 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
2124 #define OPL_MASK OPL (0x3f,1)
2125
2126 /* The main opcode combined with an update code in D form instruction.
2127    Used for extended mnemonics for VLE memory instructions.  */
2128 #define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8))
2129 #define OPVUP_MASK OPVUP (0x3f,  0xff)
2130
2131 /* An A form instruction.  */
2132 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
2133 #define A_MASK A (0x3f, 0x1f, 1)
2134
2135 /* An A_MASK with the FRB field fixed.  */
2136 #define AFRB_MASK (A_MASK | FRB_MASK)
2137
2138 /* An A_MASK with the FRC field fixed.  */
2139 #define AFRC_MASK (A_MASK | FRC_MASK)
2140
2141 /* An A_MASK with the FRA and FRC fields fixed.  */
2142 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
2143
2144 /* An AFRAFRC_MASK, but with L bit clear.  */
2145 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
2146
2147 /* A B form instruction.  */
2148 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
2149 #define B_MASK B (0x3f, 1, 1)
2150
2151 /* A BD8 form instruction.  This is a 16-bit instruction.  */
2152 #define BD8(op, aa, lk) (((((unsigned long)(op)) & 0x3f) << 10) | (((aa) & 1) << 9) | (((lk) & 1) << 8))
2153 #define BD8_MASK BD8 (0x3f, 1, 1)
2154
2155 /* Another BD8 form instruction.  This is a 16-bit instruction.  */
2156 #define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11)
2157 #define BD8IO_MASK BD8IO (0x1f)
2158
2159 /* A BD8 form instruction for simplified mnemonics.  */
2160 #define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
2161 /* A mask that excludes BO32 and BI32.  */
2162 #define EBD8IO1_MASK 0xf800
2163 /* A mask that includes BO32 and excludes BI32.  */
2164 #define EBD8IO2_MASK 0xfc00
2165 /* A mask that include BO32 AND BI32.  */
2166 #define EBD8IO3_MASK 0xff00
2167
2168 /* A BD15 form instruction.  */
2169 #define BD15(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 0xf) << 22) | ((lk) & 1))
2170 #define BD15_MASK BD15 (0x3f, 0xf, 1)
2171
2172 /* A BD15 form instruction for extended conditional branch mnemonics.  */
2173 #define EBD15(op, aa, bo, lk) (((op) & 0x3f) << 26) | (((aa) & 0xf) << 22) | (((bo) & 0x3) << 20) | ((lk) & 1)
2174 #define EBD15_MASK 0xfff00001
2175
2176 /* A BD15 form instruction for extended conditional branch mnemonics with BI.  */
2177 #define EBD15BI(op, aa, bo, bi, lk) (((op) & 0x3f) << 26) \
2178                                     | (((aa) & 0xf) << 22) \
2179                                     | (((bo) & 0x3) << 20) \
2180                                     | (((bi) & 0x3) << 16) \
2181                                     | ((lk) & 1)
2182 #define EBD15BI_MASK  0xfff30001
2183
2184 /* A BD24 form instruction.  */
2185 #define BD24(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 25) | ((lk) & 1))
2186 #define BD24_MASK BD24 (0x3f, 1, 1)
2187
2188 /* A B form instruction setting the BO field.  */
2189 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2190 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
2191
2192 /* A BBO_MASK with the y bit of the BO field removed.  This permits
2193    matching a conditional branch regardless of the setting of the y
2194    bit.  Similarly for the 'at' bits used for power4 branch hints.  */
2195 #define Y_MASK   (((unsigned long) 1) << 21)
2196 #define AT1_MASK (((unsigned long) 3) << 21)
2197 #define AT2_MASK (((unsigned long) 9) << 21)
2198 #define BBOY_MASK  (BBO_MASK &~ Y_MASK)
2199 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
2200
2201 /* A B form instruction setting the BO field and the condition bits of
2202    the BI field.  */
2203 #define BBOCB(op, bo, cb, aa, lk) \
2204   (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
2205 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
2206
2207 /* A BBOCB_MASK with the y bit of the BO field removed.  */
2208 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
2209 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
2210 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
2211
2212 /* A BBOYCB_MASK in which the BI field is fixed.  */
2213 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
2214 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
2215
2216 /* A VLE C form instruction.  */
2217 #define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1))
2218 #define C_LK_MASK C_LK(0x7fff, 1)
2219 #define C(x) ((((unsigned long)(x)) & 0xffff))
2220 #define C_MASK C(0xffff)
2221
2222 /* An Context form instruction.  */
2223 #define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))
2224 #define CTX_MASK CTX(0x3f, 0x7)
2225
2226 /* An User Context form instruction.  */
2227 #define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
2228 #define UCTX_MASK UCTX(0x3f, 0x1f)
2229
2230 /* The main opcode mask with the RA field clear.  */
2231 #define DRA_MASK (OP_MASK | RA_MASK)
2232
2233 /* A DS form instruction.  */
2234 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
2235 #define DS_MASK DSO (0x3f, 3)
2236
2237 /* An EVSEL form instruction.  */
2238 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
2239 #define EVSEL_MASK EVSEL(0x3f, 0xff)
2240
2241 /* An IA16 form instruction.  */
2242 #define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2243 #define IA16_MASK IA16(0x3f, 0x1f)
2244
2245 /* An I16A form instruction.  */
2246 #define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2247 #define I16A_MASK I16A(0x3f, 0x1f)
2248
2249 /* An I16L form instruction.  */
2250 #define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2251 #define I16L_MASK I16L(0x3f, 0x1f)
2252
2253 /* An IM7 form instruction.  */
2254 #define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11)
2255 #define IM7_MASK IM7(0x1f)
2256
2257 /* An M form instruction.  */
2258 #define M(op, rc) (OP (op) | ((rc) & 1))
2259 #define M_MASK M (0x3f, 1)
2260
2261 /* An LI20 form instruction.  */
2262 #define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15)
2263 #define LI20_MASK LI20(0x3f, 0x1)
2264
2265 /* An M form instruction with the ME field specified.  */
2266 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
2267
2268 /* An M_MASK with the MB and ME fields fixed.  */
2269 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
2270
2271 /* An M_MASK with the SH and ME fields fixed.  */
2272 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
2273
2274 /* An MD form instruction.  */
2275 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
2276 #define MD_MASK MD (0x3f, 0x7, 1)
2277
2278 /* An MD_MASK with the MB field fixed.  */
2279 #define MDMB_MASK (MD_MASK | MB6_MASK)
2280
2281 /* An MD_MASK with the SH field fixed.  */
2282 #define MDSH_MASK (MD_MASK | SH6_MASK)
2283
2284 /* An MDS form instruction.  */
2285 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
2286 #define MDS_MASK MDS (0x3f, 0xf, 1)
2287
2288 /* An MDS_MASK with the MB field fixed.  */
2289 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
2290
2291 /* An SC form instruction.  */
2292 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
2293 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
2294
2295 /* An SCI8 form instruction.  */
2296 #define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11))
2297 #define SCI8_MASK SCI8(0x3f, 0x1f)
2298
2299 /* An SCI8 form instruction.  */
2300 #define SCI8BF(op, fop, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11) | (((fop) & 7) << 23))
2301 #define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
2302
2303 /* An SD4 form instruction.  This is a 16-bit instruction.  */
2304 #define SD4(op) ((((unsigned long)(op)) & 0xf) << 12)
2305 #define SD4_MASK SD4(0xf)
2306
2307 /* An SE_IM5 form instruction.  This is a 16-bit instruction.  */
2308 #define SE_IM5(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x1) << 9))
2309 #define SE_IM5_MASK SE_IM5(0x3f, 1)
2310
2311 /* An SE_R form instruction.  This is a 16-bit instruction.  */
2312 #define SE_R(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3f) << 4))
2313 #define SE_R_MASK SE_R(0x3f, 0x3f)
2314
2315 /* An SE_RR form instruction.  This is a 16-bit instruction.  */
2316 #define SE_RR(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3) << 8))
2317 #define SE_RR_MASK SE_RR(0x3f, 3)
2318
2319 /* A VX form instruction.  */
2320 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2321
2322 /* The mask for an VX form instruction.  */
2323 #define VX_MASK VX(0x3f, 0x7ff)
2324
2325 /* A VX_MASK with the VA field fixed.  */
2326 #define VXVA_MASK (VX_MASK | (0x1f << 16))
2327
2328 /* A VX_MASK with the VB field fixed.  */
2329 #define VXVB_MASK (VX_MASK | (0x1f << 11))
2330
2331 /* A VX_MASK with the VA and VB fields fixed.  */
2332 #define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))
2333
2334 /* A VX_MASK with the VD and VA fields fixed.  */
2335 #define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))
2336
2337 /* A VX_MASK with a UIMM4 field.  */
2338 #define VXUIMM4_MASK (VX_MASK | (0x1 << 20))
2339
2340 /* A VX_MASK with a UIMM3 field.  */
2341 #define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
2342
2343 /* A VX_MASK with a UIMM2 field.  */
2344 #define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
2345
2346 /* A VX_MASK with a PS field.  */
2347 #define VXPS_MASK (VX_MASK & ~(0x1 << 9))
2348
2349 /* A VA form instruction.  */
2350 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
2351
2352 /* The mask for an VA form instruction.  */
2353 #define VXA_MASK VXA(0x3f, 0x3f)
2354
2355 /* A VXA_MASK with a SHB field.  */
2356 #define VXASHB_MASK (VXA_MASK | (1 << 10))
2357
2358 /* A VXR form instruction.  */
2359 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
2360
2361 /* The mask for a VXR form instruction.  */
2362 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
2363
2364 /* An X form instruction.  */
2365 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2366
2367 /* An EX form instruction.  */
2368 #define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2369
2370 /* The mask for an EX form instruction.  */
2371 #define EX_MASK EX (0x3f, 0x7ff)
2372
2373 /* An XX2 form instruction.  */
2374 #define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
2375
2376 /* An XX3 form instruction.  */
2377 #define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
2378
2379 /* An XX3 form instruction with the RC bit specified.  */
2380 #define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))
2381
2382 /* An XX4 form instruction.  */
2383 #define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
2384
2385 /* A Z form instruction.  */
2386 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
2387
2388 /* An X form instruction with the RC bit specified.  */
2389 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
2390
2391 /* A Z form instruction with the RC bit specified.  */
2392 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
2393
2394 /* The mask for an X form instruction.  */
2395 #define X_MASK XRC (0x3f, 0x3ff, 1)
2396
2397 /* An X form wait instruction with everything filled in except the WC field.  */
2398 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2399
2400 /* The mask for an XX1 form instruction.  */
2401 #define XX1_MASK X (0x3f, 0x3ff)
2402
2403 /* An XX1_MASK with the RB field fixed.  */
2404 #define XX1RB_MASK (XX1_MASK | RB_MASK)
2405
2406 /* The mask for an XX2 form instruction.  */
2407 #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
2408
2409 /* The mask for an XX2 form instruction with the UIM bits specified.  */
2410 #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
2411
2412 /* The mask for an XX2 form instruction with the BF bits specified.  */
2413 #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
2414
2415 /* The mask for an XX3 form instruction.  */
2416 #define XX3_MASK XX3 (0x3f, 0xff)
2417
2418 /* The mask for an XX3 form instruction with the BF bits specified.  */
2419 #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
2420
2421 /* The mask for an XX3 form instruction with the DM or SHW bits specified.  */
2422 #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
2423 #define XX3SHW_MASK XX3DM_MASK
2424
2425 /* The mask for an XX4 form instruction.  */
2426 #define XX4_MASK XX4 (0x3f, 0x3)
2427
2428 /* An X form wait instruction with everything filled in except the WC field.  */
2429 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2430
2431 /* The mask for a Z form instruction.  */
2432 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
2433 #define Z2_MASK ZRC (0x3f, 0xff, 1)
2434
2435 /* An X_MASK with the RA field fixed.  */
2436 #define XRA_MASK (X_MASK | RA_MASK)
2437
2438 /* An XRA_MASK with the W field clear.  */
2439 #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
2440
2441 /* An X_MASK with the RB field fixed.  */
2442 #define XRB_MASK (X_MASK | RB_MASK)
2443
2444 /* An X_MASK with the RT field fixed.  */
2445 #define XRT_MASK (X_MASK | RT_MASK)
2446
2447 /* An XRT_MASK mask with the L bits clear.  */
2448 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
2449
2450 /* An X_MASK with the RA and RB fields fixed.  */
2451 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
2452
2453 /* An XRARB_MASK, but with the L bit clear.  */
2454 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
2455
2456 /* An X_MASK with the RT and RA fields fixed.  */
2457 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
2458
2459 /* An X_MASK with the RT and RB fields fixed.  */
2460 #define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK)
2461
2462 /* An XRTRA_MASK, but with L bit clear.  */
2463 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
2464
2465 /* An X_MASK with the RT, RA and RB fields fixed.  */
2466 #define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK)
2467
2468 /* An XRTRARB_MASK, but with L bit clear.  */
2469 #define XRTLRARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 21))
2470
2471 /* An XRTRARB_MASK, but with A bit clear.  */
2472 #define XRTARARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 25))
2473
2474 /* An XRTRARB_MASK, but with BF bits clear.  */
2475 #define XRTBFRARB_MASK (XRTRARB_MASK & ~((unsigned long) 7 << 23))
2476
2477 /* An X form instruction with the L bit specified.  */
2478 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
2479
2480 /* An X form instruction with the L bits specified.  */
2481 #define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2482
2483 /* An X form instruction with the L bit and RC bit specified.  */
2484 #define XRCL(op, xop, l, rc) (XRC ((op), (xop), (rc)) | ((((unsigned long)(l)) & 1) << 21))
2485
2486 /* An X form instruction with RT fields specified */
2487 #define XRT(op, xop, rt) (X ((op), (xop)) \
2488         | ((((unsigned long)(rt)) & 0x1f) << 21))
2489
2490 /* An X form instruction with RT and RA fields specified */
2491 #define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
2492         | ((((unsigned long)(rt)) & 0x1f) << 21) \
2493         | ((((unsigned long)(ra)) & 0x1f) << 16))
2494
2495 /* The mask for an X form comparison instruction.  */
2496 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
2497
2498 /* The mask for an X form comparison instruction with the L field
2499    fixed.  */
2500 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
2501
2502 /* An X form trap instruction with the TO field specified.  */
2503 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
2504 #define XTO_MASK (X_MASK | TO_MASK)
2505
2506 /* An X form tlb instruction with the SH field specified.  */
2507 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
2508 #define XTLB_MASK (X_MASK | SH_MASK)
2509
2510 /* An X form sync instruction.  */
2511 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2512
2513 /* An X form sync instruction with everything filled in except the LS field.  */
2514 #define XSYNC_MASK (0xff9fffff)
2515
2516 /* An X form sync instruction with everything filled in except the L and E fields.  */
2517 #define XSYNCLE_MASK (0xff90ffff)
2518
2519 /* An X_MASK, but with the EH bit clear.  */
2520 #define XEH_MASK (X_MASK & ~((unsigned long )1))
2521
2522 /* An X form AltiVec dss instruction.  */
2523 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
2524 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
2525
2526 /* An XFL form instruction.  */
2527 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2528 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
2529
2530 /* An X form isel instruction.  */
2531 #define XISEL(op, xop)  (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2532 #define XISEL_MASK      XISEL(0x3f, 0x1f)
2533
2534 /* An XL form instruction with the LK field set to 0.  */
2535 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2536
2537 /* An XL form instruction which uses the LK field.  */
2538 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
2539
2540 /* The mask for an XL form instruction.  */
2541 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
2542
2543 /* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear.  */
2544 #define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11))
2545
2546 /* An XL form instruction which explicitly sets the BO field.  */
2547 #define XLO(op, bo, xop, lk) \
2548   (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2549 #define XLO_MASK (XL_MASK | BO_MASK)
2550
2551 /* An XL form instruction which explicitly sets the y bit of the BO
2552    field.  */
2553 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
2554 #define XLYLK_MASK (XL_MASK | Y_MASK)
2555
2556 /* An XL form instruction which sets the BO field and the condition
2557    bits of the BI field.  */
2558 #define XLOCB(op, bo, cb, xop, lk) \
2559   (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
2560 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
2561
2562 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
2563 #define XLBB_MASK (XL_MASK | BB_MASK)
2564 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
2565 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
2566
2567 /* A mask for branch instructions using the BH field.  */
2568 #define XLBH_MASK (XL_MASK | (0x1c << 11))
2569
2570 /* An XL_MASK with the BO and BB fields fixed.  */
2571 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
2572
2573 /* An XL_MASK with the BO, BI and BB fields fixed.  */
2574 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
2575
2576 /* An X form mbar instruction with MO field.  */
2577 #define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21))
2578
2579 /* An XO form instruction.  */
2580 #define XO(op, xop, oe, rc) \
2581   (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
2582 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
2583
2584 /* An XO_MASK with the RB field fixed.  */
2585 #define XORB_MASK (XO_MASK | RB_MASK)
2586
2587 /* An XOPS form instruction for paired singles.  */
2588 #define XOPS(op, xop, rc) \
2589   (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2590 #define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
2591
2592
2593 /* An XS form instruction.  */
2594 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
2595 #define XS_MASK XS (0x3f, 0x1ff, 1)
2596
2597 /* A mask for the FXM version of an XFX form instruction.  */
2598 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
2599
2600 /* An XFX form instruction with the FXM field filled in.  */
2601 #define XFXM(op, xop, fxm, p4) \
2602   (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
2603    | ((unsigned long)(p4) << 20))
2604
2605 /* An XFX form instruction with the SPR field filled in.  */
2606 #define XSPR(op, xop, spr) \
2607   (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
2608 #define XSPR_MASK (X_MASK | SPR_MASK)
2609
2610 /* An XFX form instruction with the SPR field filled in except for the
2611    SPRBAT field.  */
2612 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
2613
2614 /* An XFX form instruction with the SPR field filled in except for the
2615    SPRG field.  */
2616 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
2617
2618 /* An X form instruction with everything filled in except the E field.  */
2619 #define XE_MASK (0xffff7fff)
2620
2621 /* An X form user context instruction.  */
2622 #define XUC(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
2623 #define XUC_MASK      XUC(0x3f, 0x1f)
2624
2625 /* An XW form instruction.  */
2626 #define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
2627 /* The mask for a G form instruction. rc not supported at present.  */
2628 #define XW_MASK XW (0x3f, 0x3f, 0)
2629
2630 /* An APU form instruction.  */
2631 #define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
2632
2633 /* The mask for an APU form instruction.  */
2634 #define APU_MASK APU (0x3f, 0x3ff, 1)
2635 #define APU_RT_MASK (APU_MASK | RT_MASK)
2636 #define APU_RA_MASK (APU_MASK | RA_MASK)
2637
2638 /* The BO encodings used in extended conditional branch mnemonics.  */
2639 #define BODNZF  (0x0)
2640 #define BODNZFP (0x1)
2641 #define BODZF   (0x2)
2642 #define BODZFP  (0x3)
2643 #define BODNZT  (0x8)
2644 #define BODNZTP (0x9)
2645 #define BODZT   (0xa)
2646 #define BODZTP  (0xb)
2647
2648 #define BOF     (0x4)
2649 #define BOFP    (0x5)
2650 #define BOFM4   (0x6)
2651 #define BOFP4   (0x7)
2652 #define BOT     (0xc)
2653 #define BOTP    (0xd)
2654 #define BOTM4   (0xe)
2655 #define BOTP4   (0xf)
2656
2657 #define BODNZ   (0x10)
2658 #define BODNZP  (0x11)
2659 #define BODZ    (0x12)
2660 #define BODZP   (0x13)
2661 #define BODNZM4 (0x18)
2662 #define BODNZP4 (0x19)
2663 #define BODZM4  (0x1a)
2664 #define BODZP4  (0x1b)
2665
2666 #define BOU     (0x14)
2667
2668 /* The BO16 encodings used in extended VLE conditional branch mnemonics.  */
2669 #define BO16F   (0x0)
2670 #define BO16T   (0x1)
2671
2672 /* The BO32 encodings used in extended VLE conditional branch mnemonics.  */
2673 #define BO32F   (0x0)
2674 #define BO32T   (0x1)
2675 #define BO32DNZ (0x2)
2676 #define BO32DZ  (0x3)
2677
2678 /* The BI condition bit encodings used in extended conditional branch
2679    mnemonics.  */
2680 #define CBLT    (0)
2681 #define CBGT    (1)
2682 #define CBEQ    (2)
2683 #define CBSO    (3)
2684
2685 /* The TO encodings used in extended trap mnemonics.  */
2686 #define TOLGT   (0x1)
2687 #define TOLLT   (0x2)
2688 #define TOEQ    (0x4)
2689 #define TOLGE   (0x5)
2690 #define TOLNL   (0x5)
2691 #define TOLLE   (0x6)
2692 #define TOLNG   (0x6)
2693 #define TOGT    (0x8)
2694 #define TOGE    (0xc)
2695 #define TONL    (0xc)
2696 #define TOLT    (0x10)
2697 #define TOLE    (0x14)
2698 #define TONG    (0x14)
2699 #define TONE    (0x18)
2700 #define TOU     (0x1f)
2701 \f
2702 /* Smaller names for the flags so each entry in the opcodes table will
2703    fit on a single line.  */
2704 #define PPCNONE 0
2705 #undef  PPC
2706 #define PPC     PPC_OPCODE_PPC
2707 #define PPCCOM  PPC_OPCODE_PPC | PPC_OPCODE_COMMON
2708 #define POWER4  PPC_OPCODE_POWER4
2709 #define POWER5  PPC_OPCODE_POWER5
2710 #define POWER6  PPC_OPCODE_POWER6
2711 #define POWER7  PPC_OPCODE_POWER7
2712 #define POWER8  PPC_OPCODE_POWER8
2713 #define CELL    PPC_OPCODE_CELL
2714 #define PPC64   PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
2715 #define NON32   (PPC_OPCODE_64 | PPC_OPCODE_POWER4      \
2716                  | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
2717 #define PPC403  PPC_OPCODE_403
2718 #define PPC405  PPC_OPCODE_405
2719 #define PPC440  PPC_OPCODE_440
2720 #define PPC464  PPC440
2721 #define PPC476  PPC_OPCODE_476
2722 #define PPC750  PPC
2723 #define PPC7450 PPC
2724 #define PPC860  PPC
2725 #define PPCPS   PPC_OPCODE_PPCPS
2726 #define PPCVEC  PPC_OPCODE_ALTIVEC
2727 #define PPCVEC2 PPC_OPCODE_ALTIVEC2
2728 #define PPCVSX  PPC_OPCODE_VSX
2729 #define PPCVSX2 PPC_OPCODE_VSX
2730 #define POWER   PPC_OPCODE_POWER
2731 #define POWER2  PPC_OPCODE_POWER | PPC_OPCODE_POWER2
2732 #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
2733 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
2734 #define COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
2735 #define M601    PPC_OPCODE_POWER | PPC_OPCODE_601
2736 #define PWRCOM  PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
2737 #define MFDEC1  PPC_OPCODE_POWER
2738 #define MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
2739 #define BOOKE   PPC_OPCODE_BOOKE
2740 #define NO371   PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS | PPC_OPCODE_VLE
2741 #define PPCE300 PPC_OPCODE_E300
2742 #define PPCSPE  PPC_OPCODE_SPE | PPC_OPCODE_VLE
2743 #define PPCISEL PPC_OPCODE_ISEL | PPC_OPCODE_VLE
2744 #define PPCEFS  PPC_OPCODE_EFS | PPC_OPCODE_VLE
2745 #define PPCBRLK PPC_OPCODE_BRLOCK
2746 #define PPCPMR  PPC_OPCODE_PMR
2747 #define PPCTMR  PPC_OPCODE_TMR
2748 #define PPCCHLK PPC_OPCODE_CACHELCK
2749 #define PPCRFMCI        PPC_OPCODE_RFMCI
2750 #define E500MC  PPC_OPCODE_E500MC
2751 #define PPCA2   PPC_OPCODE_A2
2752 #define TITAN   PPC_OPCODE_TITAN
2753 #define MULHW   PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN | PPC_OPCODE_VLE
2754 #define E500    PPC_OPCODE_E500
2755 #define E6500   PPC_OPCODE_E6500
2756 #define PPCVLE  PPC_OPCODE_VLE
2757 #define PPCHTM  PPC_OPCODE_HTM
2758 /* The list of embedded processors that use the embedded operand ordering
2759    for the 3 operand dcbt and dcbtst instructions.  */
2760 #define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
2761                  | PPC_OPCODE_A2 | PPC_OPCODE_VLE)
2762
2763
2764 \f
2765 /* The opcode table.
2766
2767    The format of the opcode table is:
2768
2769    NAME         OPCODE          MASK         FLAGS      ANTI            {OPERANDS}
2770
2771    NAME is the name of the instruction.
2772    OPCODE is the instruction opcode.
2773    MASK is the opcode mask; this is used to tell the disassembler
2774      which bits in the actual opcode must match OPCODE.
2775    FLAGS are flags indicating which processors support the instruction.
2776    ANTI indicates which processors don't support the instruction.
2777    OPERANDS is the list of operands.
2778
2779    The disassembler reads the table in order and prints the first
2780    instruction which matches, so this table is sorted to put more
2781    specific instructions before more general instructions.
2782
2783    This table must be sorted by major opcode.  Please try to keep it
2784    vaguely sorted within major opcode too, except of course where
2785    constrained otherwise by disassembler operation.  */
2786
2787 const struct powerpc_opcode powerpc_opcodes[] = {
2788 {"attn",        X(0,256),       X_MASK,   POWER4|PPCA2, PPC476,         {0}},
2789 {"tdlgti",      OPTO(2,TOLGT),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2790 {"tdllti",      OPTO(2,TOLLT),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2791 {"tdeqi",       OPTO(2,TOEQ),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2792 {"tdlgei",      OPTO(2,TOLGE),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2793 {"tdlnli",      OPTO(2,TOLNL),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2794 {"tdllei",      OPTO(2,TOLLE),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2795 {"tdlngi",      OPTO(2,TOLNG),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2796 {"tdgti",       OPTO(2,TOGT),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2797 {"tdgei",       OPTO(2,TOGE),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2798 {"tdnli",       OPTO(2,TONL),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2799 {"tdlti",       OPTO(2,TOLT),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2800 {"tdlei",       OPTO(2,TOLE),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2801 {"tdngi",       OPTO(2,TONG),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2802 {"tdnei",       OPTO(2,TONE),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2803 {"tdui",        OPTO(2,TOU),    OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2804 {"tdi",         OP(2),          OP_MASK,     PPC64,     PPCNONE,        {TO, RA, SI}},
2805
2806 {"twlgti",      OPTO(3,TOLGT),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2807 {"tlgti",       OPTO(3,TOLGT),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2808 {"twllti",      OPTO(3,TOLLT),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2809 {"tllti",       OPTO(3,TOLLT),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2810 {"tweqi",       OPTO(3,TOEQ),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2811 {"teqi",        OPTO(3,TOEQ),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2812 {"twlgei",      OPTO(3,TOLGE),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2813 {"tlgei",       OPTO(3,TOLGE),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2814 {"twlnli",      OPTO(3,TOLNL),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2815 {"tlnli",       OPTO(3,TOLNL),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2816 {"twllei",      OPTO(3,TOLLE),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2817 {"tllei",       OPTO(3,TOLLE),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2818 {"twlngi",      OPTO(3,TOLNG),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2819 {"tlngi",       OPTO(3,TOLNG),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2820 {"twgti",       OPTO(3,TOGT),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2821 {"tgti",        OPTO(3,TOGT),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2822 {"twgei",       OPTO(3,TOGE),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2823 {"tgei",        OPTO(3,TOGE),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2824 {"twnli",       OPTO(3,TONL),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2825 {"tnli",        OPTO(3,TONL),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2826 {"twlti",       OPTO(3,TOLT),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2827 {"tlti",        OPTO(3,TOLT),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2828 {"twlei",       OPTO(3,TOLE),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2829 {"tlei",        OPTO(3,TOLE),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2830 {"twngi",       OPTO(3,TONG),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2831 {"tngi",        OPTO(3,TONG),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2832 {"twnei",       OPTO(3,TONE),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2833 {"tnei",        OPTO(3,TONE),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2834 {"twui",        OPTO(3,TOU),    OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2835 {"tui",         OPTO(3,TOU),    OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2836 {"twi",         OP(3),          OP_MASK,     PPCCOM,    PPCNONE,        {TO, RA, SI}},
2837 {"ti",          OP(3),          OP_MASK,     PWRCOM,    PPCNONE,        {TO, RA, SI}},
2838
2839 {"ps_cmpu0",    X  (4,   0), X_MASK|(3<<21), PPCPS,     PPCNONE,        {BF, FRA, FRB}},
2840 {"vaddubm",     VX (4,   0),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2841 {"vmaxub",      VX (4,   2),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2842 {"vrlb",        VX (4,   4),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2843 {"vcmpequb",    VXR(4,   6,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2844 {"vmuloub",     VX (4,   8),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2845 {"vaddfp",      VX (4,  10),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2846 {"psq_lx",      XW (4,   6,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRT,RA,RB,PSWM,PSQM}},
2847 {"vmrghb",      VX (4,  12),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2848 {"psq_stx",     XW (4,   7,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRS,RA,RB,PSWM,PSQM}},
2849 {"vpkuhum",     VX (4,  14),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2850 {"mulhhwu",     XRC(4,   8,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2851 {"mulhhwu.",    XRC(4,   8,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2852 {"ps_sum0",     A  (4,  10,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2853 {"ps_sum0.",    A  (4,  10,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2854 {"ps_sum1",     A  (4,  11,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2855 {"ps_sum1.",    A  (4,  11,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2856 {"ps_muls0",    A  (4,  12,0),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2857 {"machhwu",     XO (4,  12,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2858 {"ps_muls0.",   A  (4,  12,1),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2859 {"machhwu.",    XO (4,  12,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2860 {"ps_muls1",    A  (4,  13,0),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2861 {"ps_muls1.",   A  (4,  13,1),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2862 {"ps_madds0",   A  (4,  14,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2863 {"ps_madds0.",  A  (4,  14,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2864 {"ps_madds1",   A  (4,  15,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2865 {"ps_madds1.",  A  (4,  15,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2866 {"vmhaddshs",   VXA(4,  32),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2867 {"vmhraddshs",  VXA(4,  33),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2868 {"vmladduhm",   VXA(4,  34),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2869 {"ps_div",      A  (4,  18,0),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2870 {"vmsumubm",    VXA(4,  36),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2871 {"ps_div.",     A  (4,  18,1),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2872 {"vmsummbm",    VXA(4,  37),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2873 {"vmsumuhm",    VXA(4,  38),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2874 {"vmsumuhs",    VXA(4,  39),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2875 {"ps_sub",      A  (4,  20,0),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2876 {"vmsumshm",    VXA(4,  40),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2877 {"ps_sub.",     A  (4,  20,1),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2878 {"vmsumshs",    VXA(4,  41),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2879 {"ps_add",      A  (4,  21,0),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2880 {"vsel",        VXA(4,  42),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2881 {"ps_add.",     A  (4,  21,1),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2882 {"vperm",       VXA(4,  43),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2883 {"vsldoi",      VXA(4,  44),    VXASHB_MASK, PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, SHB}},
2884 {"ps_sel",      A  (4,  23,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2885 {"vpermxor",    VXA(4,  45),    VXA_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB, VC}},
2886 {"vmaddfp",     VXA(4,  46),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VC, VB}},
2887 {"ps_sel.",     A  (4,  23,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2888 {"vnmsubfp",    VXA(4,  47),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VC, VB}},
2889 {"ps_res",      A  (4,  24,0), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
2890 {"ps_res.",     A  (4,  24,1), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
2891 {"ps_mul",      A  (4,  25,0), AFRB_MASK,    PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2892 {"ps_mul.",     A  (4,  25,1),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2893 {"ps_rsqrte",   A  (4,  26,0), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
2894 {"ps_rsqrte.",  A  (4,  26,1), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
2895 {"ps_msub",     A  (4,  28,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2896 {"ps_msub.",    A  (4,  28,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2897 {"ps_madd",     A  (4,  29,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2898 {"ps_madd.",    A  (4,  29,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2899 {"ps_nmsub",    A  (4,  30,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2900 {"ps_nmsub.",   A  (4,  30,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2901 {"ps_nmadd",    A  (4,  31,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2902 {"ps_nmadd.",   A  (4,  31,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2903 {"ps_cmpo0",    X  (4,  32), X_MASK|(3<<21), PPCPS,     PPCNONE,        {BF, FRA, FRB}},
2904 {"vaddeuqm",    VXA(4,  60),    VXA_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB, VC}},
2905 {"vaddecuq",    VXA(4,  61),    VXA_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB, VC}},
2906 {"vsubeuqm",    VXA(4,  62),    VXA_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB, VC}},
2907 {"vsubecuq",    VXA(4,  63),    VXA_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB, VC}},
2908 {"vadduhm",     VX (4,  64),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2909 {"vmaxuh",      VX (4,  66),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2910 {"vrlh",        VX (4,  68),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2911 {"vcmpequh",    VXR(4,  70,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2912 {"vmulouh",     VX (4,  72),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2913 {"vsubfp",      VX (4,  74),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2914 {"psq_lux",     XW (4,  38,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRT,RA,RB,PSWM,PSQM}},
2915 {"vmrghh",      VX (4,  76),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2916 {"psq_stux",    XW (4,  39,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRS,RA,RB,PSWM,PSQM}},
2917 {"vpkuwum",     VX (4,  78),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2918 {"ps_neg",      XRC(4,  40,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2919 {"mulhhw",      XRC(4,  40,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2920 {"ps_neg.",     XRC(4,  40,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2921 {"mulhhw.",     XRC(4,  40,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2922 {"machhw",      XO (4,  44,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2923 {"machhw.",     XO (4,  44,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2924 {"nmachhw",     XO (4,  46,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2925 {"nmachhw.",    XO (4,  46,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2926 {"ps_cmpu1",    X  (4,  64), X_MASK|(3<<21), PPCPS,     PPCNONE,        {BF, FRA, FRB}},
2927 {"vadduwm",     VX (4,  128),   VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2928 {"vmaxuw",      VX (4,  130),   VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2929 {"vrlw",        VX (4,  132),   VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2930 {"vcmpequw",    VXR(4,  134,0), VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2931 {"vmulouw",     VX (4,  136),   VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
2932 {"vmuluwm",     VX (4,  137),   VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
2933 {"vmrghw",      VX (4,  140),   VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2934 {"vpkuhus",     VX (4,  142),   VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2935 {"ps_mr",       XRC(4,  72,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2936 {"ps_mr.",      XRC(4,  72,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2937 {"machhwsu",    XO (4,  76,0,0),XO_MASK,     MULHW|PPCVLE,  PPCNONE,    {RT, RA, RB}},
2938 {"machhwsu.",   XO (4,  76,0,1),XO_MASK,     MULHW|PPCVLE,  PPCNONE,    {RT, RA, RB}},
2939 {"ps_cmpo1",    X  (4,  96), X_MASK|(3<<21), PPCPS,     PPCNONE,        {BF, FRA, FRB}},
2940 {"vaddudm",     VX (4, 192),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
2941 {"vmaxud",      VX (4, 194),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
2942 {"vrld",        VX (4, 196),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
2943 {"vcmpeqfp",    VXR(4, 198,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2944 {"vcmpequd",    VXR(4, 199,0),  VXR_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB}},
2945 {"vpkuwus",     VX (4, 206),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2946 {"machhws",     XO (4, 108,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2947 {"machhws.",    XO (4, 108,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2948 {"nmachhws",    XO (4, 110,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2949 {"nmachhws.",   XO (4, 110,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2950 {"vadduqm",     VX (4, 256),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
2951 {"vmaxsb",      VX (4, 258),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2952 {"vslb",        VX (4, 260),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2953 {"vmulosb",     VX (4, 264),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2954 {"vrefp",       VX (4, 266),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
2955 {"vmrglb",      VX (4, 268),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2956 {"vpkshus",     VX (4, 270),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2957 {"ps_nabs",     XRC(4, 136,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2958 {"mulchwu",     XRC(4, 136,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2959 {"ps_nabs.",    XRC(4, 136,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2960 {"mulchwu.",    XRC(4, 136,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2961 {"macchwu",     XO (4, 140,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2962 {"macchwu.",    XO (4, 140,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2963 {"vaddcuq",     VX (4, 320),    VX_MASK,     PPCVEC2,      PPCNONE,     {VD, VA, VB}},
2964 {"vmaxsh",      VX (4, 322),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2965 {"vslh",        VX (4, 324),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2966 {"vmulosh",     VX (4, 328),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2967 {"vrsqrtefp",   VX (4, 330),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
2968 {"vmrglh",      VX (4, 332),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2969 {"vpkswus",     VX (4, 334),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2970 {"mulchw",      XRC(4, 168,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2971 {"mulchw.",     XRC(4, 168,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2972 {"macchw",      XO (4, 172,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2973 {"macchw.",     XO (4, 172,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2974 {"nmacchw",     XO (4, 174,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2975 {"nmacchw.",    XO (4, 174,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2976 {"vaddcuw",     VX (4, 384),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2977 {"vmaxsw",      VX (4, 386),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2978 {"vslw",        VX (4, 388),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2979 {"vmulosw",     VX (4, 392),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
2980 {"vexptefp",    VX (4, 394),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
2981 {"vmrglw",      VX (4, 396),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2982 {"vpkshss",     VX (4, 398),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2983 {"macchwsu",    XO (4, 204,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2984 {"macchwsu.",   XO (4, 204,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2985 {"vmaxsd",      VX (4, 450),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
2986 {"vsl",         VX (4, 452),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2987 {"vcmpgefp",    VXR(4, 454,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2988 {"vlogefp",     VX (4, 458),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
2989 {"vpkswss",     VX (4, 462),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2990 {"macchws",     XO (4, 236,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2991 {"macchws.",    XO (4, 236,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2992 {"nmacchws",    XO (4, 238,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2993 {"nmacchws.",   XO (4, 238,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2994 {"evaddw",      VX (4, 512),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2995 {"vaddubs",     VX (4, 512),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2996 {"evaddiw",     VX (4, 514),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB, UIMM}},
2997 {"vminub",      VX (4, 514),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2998 {"evsubfw",     VX (4, 516),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2999 {"evsubw",      VX (4, 516),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB, RA}},
3000 {"vsrb",        VX (4, 516),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3001 {"evsubifw",    VX (4, 518),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, UIMM, RB}},
3002 {"evsubiw",     VX (4, 518),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB, UIMM}},
3003 {"vcmpgtub",    VXR(4, 518,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3004 {"evabs",       VX (4, 520),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3005 {"vmuleub",     VX (4, 520),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3006 {"evneg",       VX (4, 521),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3007 {"evextsb",     VX (4, 522),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3008 {"vrfin",       VX (4, 522),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3009 {"evextsh",     VX (4, 523),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3010 {"evrndw",      VX (4, 524),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3011 {"vspltb",      VX (4, 524),    VXUIMM4_MASK,PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM4}},
3012 {"evcntlzw",    VX (4, 525),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3013 {"evcntlsw",    VX (4, 526),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3014 {"vupkhsb",     VX (4, 526),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3015 {"brinc",       VX (4, 527),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3016 {"ps_abs",      XRC(4, 264,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
3017 {"ps_abs.",     XRC(4, 264,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
3018 {"evand",       VX (4, 529),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3019 {"evandc",      VX (4, 530),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3020 {"evxor",       VX (4, 534),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3021 {"evmr",        VX (4, 535),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, BBA}},
3022 {"evor",        VX (4, 535),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3023 {"evnor",       VX (4, 536),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3024 {"evnot",       VX (4, 536),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, BBA}},
3025 {"get",         APU(4, 268,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
3026 {"eveqv",       VX (4, 537),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3027 {"evorc",       VX (4, 539),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3028 {"evnand",      VX (4, 542),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3029 {"evsrwu",      VX (4, 544),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3030 {"evsrws",      VX (4, 545),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3031 {"evsrwiu",     VX (4, 546),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, EVUIMM}},
3032 {"evsrwis",     VX (4, 547),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, EVUIMM}},
3033 {"evslw",       VX (4, 548),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3034 {"evslwi",      VX (4, 550),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, EVUIMM}},
3035 {"evrlw",       VX (4, 552),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3036 {"evsplati",    VX (4, 553),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, SIMM}},
3037 {"evrlwi",      VX (4, 554),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, EVUIMM}},
3038 {"evsplatfi",   VX (4, 555),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, SIMM}},
3039 {"evmergehi",   VX (4, 556),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3040 {"evmergelo",   VX (4, 557),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3041 {"evmergehilo", VX (4, 558),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3042 {"evmergelohi", VX (4, 559),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3043 {"evcmpgtu",    VX (4, 560),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3044 {"evcmpgts",    VX (4, 561),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3045 {"evcmpltu",    VX (4, 562),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3046 {"evcmplts",    VX (4, 563),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3047 {"evcmpeq",     VX (4, 564),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3048 {"cget",        APU(4, 284,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
3049 {"vadduhs",     VX (4, 576),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3050 {"vminuh",      VX (4, 578),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3051 {"vsrh",        VX (4, 580),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3052 {"vcmpgtuh",    VXR(4, 582,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3053 {"vmuleuh",     VX (4, 584),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3054 {"vrfiz",       VX (4, 586),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3055 {"vsplth",      VX (4, 588),    VXUIMM3_MASK,PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM3}},
3056 {"vupkhsh",     VX (4, 590),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3057 {"nget",        APU(4, 300,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
3058 {"evsel",       EVSEL(4,79),    EVSEL_MASK,  PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB, CRFS}},
3059 {"ncget",       APU(4, 316,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
3060 {"evfsadd",     VX (4, 640),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3061 {"vadduws",     VX (4, 640),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3062 {"evfssub",     VX (4, 641),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3063 {"vminuw",      VX (4, 642),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3064 {"evfsabs",     VX (4, 644),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3065 {"vsrw",        VX (4, 644),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3066 {"evfsnabs",    VX (4, 645),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3067 {"evfsneg",     VX (4, 646),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3068 {"vcmpgtuw",    VXR(4, 646,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3069 {"vmuleuw",     VX (4, 648),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3070 {"evfsmul",     VX (4, 648),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3071 {"evfsdiv",     VX (4, 649),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3072 {"vrfip",       VX (4, 650),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3073 {"evfscmpgt",   VX (4, 652),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3074 {"vspltw",      VX (4, 652),    VXUIMM2_MASK,PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM2}},
3075 {"evfscmplt",   VX (4, 653),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3076 {"evfscmpeq",   VX (4, 654),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3077 {"vupklsb",     VX (4, 654),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3078 {"evfscfui",    VX (4, 656),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3079 {"evfscfsi",    VX (4, 657),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3080 {"evfscfuf",    VX (4, 658),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3081 {"evfscfsf",    VX (4, 659),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3082 {"evfsctui",    VX (4, 660),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3083 {"evfsctsi",    VX (4, 661),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3084 {"evfsctuf",    VX (4, 662),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3085 {"evfsctsf",    VX (4, 663),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3086 {"evfsctuiz",   VX (4, 664),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3087 {"put",         APU(4, 332,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
3088 {"evfsctsiz",   VX (4, 666),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3089 {"evfststgt",   VX (4, 668),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3090 {"evfststlt",   VX (4, 669),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3091 {"evfststeq",   VX (4, 670),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3092 {"cput",        APU(4, 348,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
3093 {"efsadd",      VX (4, 704),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3094 {"efssub",      VX (4, 705),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3095 {"vminud",      VX (4, 706),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3096 {"efsabs",      VX (4, 708),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA}},
3097 {"vsr",         VX (4, 708),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3098 {"efsnabs",     VX (4, 709),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA}},
3099 {"efsneg",      VX (4, 710),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA}},
3100 {"vcmpgtfp",    VXR(4, 710,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3101 {"vcmpgtud",    VXR(4, 711,0),  VXR_MASK,    PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3102 {"efsmul",      VX (4, 712),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3103 {"efsdiv",      VX (4, 713),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3104 {"vrfim",       VX (4, 714),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3105 {"efscmpgt",    VX (4, 716),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3106 {"efscmplt",    VX (4, 717),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3107 {"efscmpeq",    VX (4, 718),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3108 {"vupklsh",     VX (4, 718),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3109 {"efscfd",      VX (4, 719),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3110 {"efscfui",     VX (4, 720),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3111 {"efscfsi",     VX (4, 721),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3112 {"efscfuf",     VX (4, 722),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3113 {"efscfsf",     VX (4, 723),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3114 {"efsctui",     VX (4, 724),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3115 {"efsctsi",     VX (4, 725),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3116 {"efsctuf",     VX (4, 726),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3117 {"efsctsf",     VX (4, 727),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3118 {"efsctuiz",    VX (4, 728),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3119 {"nput",        APU(4, 364,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
3120 {"efsctsiz",    VX (4, 730),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3121 {"efststgt",    VX (4, 732),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3122 {"efststlt",    VX (4, 733),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3123 {"efststeq",    VX (4, 734),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3124 {"efdadd",      VX (4, 736),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3125 {"efdsub",      VX (4, 737),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3126 {"efdcfuid",    VX (4, 738),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3127 {"efdcfsid",    VX (4, 739),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3128 {"efdabs",      VX (4, 740),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA}},
3129 {"efdnabs",     VX (4, 741),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA}},
3130 {"efdneg",      VX (4, 742),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA}},
3131 {"efdmul",      VX (4, 744),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3132 {"efddiv",      VX (4, 745),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3133 {"efdctuidz",   VX (4, 746),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3134 {"efdctsidz",   VX (4, 747),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3135 {"efdcmpgt",    VX (4, 748),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3136 {"efdcmplt",    VX (4, 749),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3137 {"efdcmpeq",    VX (4, 750),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3138 {"efdcfs",      VX (4, 751),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3139 {"efdcfui",     VX (4, 752),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3140 {"efdcfsi",     VX (4, 753),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3141 {"efdcfuf",     VX (4, 754),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3142 {"efdcfsf",     VX (4, 755),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3143 {"efdctui",     VX (4, 756),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3144 {"efdctsi",     VX (4, 757),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3145 {"efdctuf",     VX (4, 758),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3146 {"efdctsf",     VX (4, 759),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3147 {"efdctuiz",    VX (4, 760),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3148 {"ncput",       APU(4, 380,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
3149 {"efdctsiz",    VX (4, 762),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3150 {"efdtstgt",    VX (4, 764),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3151 {"efdtstlt",    VX (4, 765),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3152 {"efdtsteq",    VX (4, 766),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3153 {"evlddx",      VX (4, 768),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3154 {"vaddsbs",     VX (4, 768),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3155 {"evldd",       VX (4, 769),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_8, RA}},
3156 {"evldwx",      VX (4, 770),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3157 {"vminsb",      VX (4, 770),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3158 {"evldw",       VX (4, 771),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_8, RA}},
3159 {"evldhx",      VX (4, 772),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3160 {"vsrab",       VX (4, 772),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3161 {"evldh",       VX (4, 773),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_8, RA}},
3162 {"vcmpgtsb",    VXR(4, 774,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3163 {"evlhhesplatx",VX (4, 776),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3164 {"vmulesb",     VX (4, 776),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3165 {"evlhhesplat", VX (4, 777),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_2, RA}},
3166 {"vcfux",       VX (4, 778),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
3167 {"vcuxwfp",     VX (4, 778),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
3168 {"evlhhousplatx",VX(4, 780),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3169 {"vspltisb",    VX (4, 780),    VXVB_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, SIMM}},
3170 {"evlhhousplat",VX (4, 781),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_2, RA}},
3171 {"evlhhossplatx",VX(4, 782),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3172 {"vpkpx",       VX (4, 782),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3173 {"evlhhossplat",VX (4, 783),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_2, RA}},
3174 {"mullhwu",     XRC(4, 392,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3175 {"evlwhex",     VX (4, 784),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3176 {"mullhwu.",    XRC(4, 392,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3177 {"evlwhe",      VX (4, 785),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3178 {"evlwhoux",    VX (4, 788),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3179 {"evlwhou",     VX (4, 789),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3180 {"evlwhosx",    VX (4, 790),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3181 {"evlwhos",     VX (4, 791),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3182 {"maclhwu",     XO (4, 396,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3183 {"evlwwsplatx", VX (4, 792),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3184 {"maclhwu.",    XO (4, 396,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3185 {"evlwwsplat",  VX (4, 793),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3186 {"evlwhsplatx", VX (4, 796),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3187 {"evlwhsplat",  VX (4, 797),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3188 {"evstddx",     VX (4, 800),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3189 {"evstdd",      VX (4, 801),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_8, RA}},
3190 {"evstdwx",     VX (4, 802),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3191 {"evstdw",      VX (4, 803),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_8, RA}},
3192 {"evstdhx",     VX (4, 804),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3193 {"evstdh",      VX (4, 805),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_8, RA}},
3194 {"evstwhex",    VX (4, 816),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3195 {"evstwhe",     VX (4, 817),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3196 {"evstwhox",    VX (4, 820),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3197 {"evstwho",     VX (4, 821),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3198 {"evstwwex",    VX (4, 824),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3199 {"evstwwe",     VX (4, 825),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3200 {"evstwwox",    VX (4, 828),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3201 {"evstwwo",     VX (4, 829),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3202 {"vaddshs",     VX (4, 832),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3203 {"vminsh",      VX (4, 834),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3204 {"vsrah",       VX (4, 836),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3205 {"vcmpgtsh",    VXR(4, 838,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3206 {"vmulesh",     VX (4, 840),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3207 {"vcfsx",       VX (4, 842),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
3208 {"vcsxwfp",     VX (4, 842),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
3209 {"vspltish",    VX (4, 844),    VXVB_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, SIMM}},
3210 {"vupkhpx",     VX (4, 846),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3211 {"mullhw",      XRC(4, 424,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3212 {"mullhw.",     XRC(4, 424,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3213 {"maclhw",      XO (4, 428,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3214 {"maclhw.",     XO (4, 428,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3215 {"nmaclhw",     XO (4, 430,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3216 {"nmaclhw.",    XO (4, 430,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3217 {"vaddsws",     VX (4, 896),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3218 {"vminsw",      VX (4, 898),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3219 {"vsraw",       VX (4, 900),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3220 {"vcmpgtsw",    VXR(4, 902,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3221 {"vmulesw",     VX (4, 904),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3222 {"vctuxs",      VX (4, 906),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
3223 {"vcfpuxws",    VX (4, 906),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
3224 {"vspltisw",    VX (4, 908),    VXVB_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, SIMM}},
3225 {"maclhwsu",    XO (4, 460,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3226 {"maclhwsu.",   XO (4, 460,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3227 {"vminsd",      VX (4, 962),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3228 {"vsrad",       VX (4, 964),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3229 {"vcmpbfp",     VXR(4, 966,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3230 {"vcmpgtsd",    VXR(4, 967,0),  VXR_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3231 {"vctsxs",      VX (4, 970),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
3232 {"vcfpsxws",    VX (4, 970),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
3233 {"vupklpx",     VX (4, 974),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3234 {"maclhws",     XO (4, 492,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3235 {"maclhws.",    XO (4, 492,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3236 {"nmaclhws",    XO (4, 494,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3237 {"nmaclhws.",   XO (4, 494,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3238 {"vsububm",     VX (4,1024),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3239 {"bcdadd.",     VX (4,1025),    VXPS_MASK,   PPCVEC2,       PPCNONE,    {VD, VA, VB, PS}},
3240 {"vavgub",      VX (4,1026),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3241 {"vabsdub",     VX (4,1027),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3242 {"evmhessf",    VX (4,1027),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3243 {"vand",        VX (4,1028),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3244 {"vcmpequb.",   VXR(4,   6,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3245 {"udi0fcm.",    APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3246 {"udi0fcm",     APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3247 {"evmhossf",    VX (4,1031),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3248 {"vpmsumb",     VX (4,1032),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3249 {"evmheumi",    VX (4,1032),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3250 {"evmhesmi",    VX (4,1033),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3251 {"vmaxfp",      VX (4,1034),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3252 {"evmhesmf",    VX (4,1035),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3253 {"evmhoumi",    VX (4,1036),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3254 {"vslo",        VX (4,1036),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3255 {"evmhosmi",    VX (4,1037),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3256 {"evmhosmf",    VX (4,1039),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3257 {"machhwuo",    XO (4,  12,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3258 {"machhwuo.",   XO (4,  12,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3259 {"ps_merge00",  XOPS(4,528,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3260 {"ps_merge00.", XOPS(4,528,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3261 {"evmhessfa",   VX (4,1059),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3262 {"evmhossfa",   VX (4,1063),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3263 {"evmheumia",   VX (4,1064),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3264 {"evmhesmia",   VX (4,1065),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3265 {"evmhesmfa",   VX (4,1067),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3266 {"evmhoumia",   VX (4,1068),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3267 {"evmhosmia",   VX (4,1069),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3268 {"evmhosmfa",   VX (4,1071),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3269 {"vsubuhm",     VX (4,1088),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3270 {"bcdsub.",     VX (4,1089),    VXPS_MASK,   PPCVEC2,       PPCNONE,    {VD, VA, VB, PS}},
3271 {"vavguh",      VX (4,1090),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3272 {"vabsduh",     VX (4,1091),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3273 {"vandc",       VX (4,1092),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3274 {"vcmpequh.",   VXR(4,  70,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3275 {"udi1fcm.",    APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3276 {"udi1fcm",     APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3277 {"evmwhssf",    VX (4,1095),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3278 {"vpmsumh",     VX (4,1096),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3279 {"evmwlumi",    VX (4,1096),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3280 {"vminfp",      VX (4,1098),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3281 {"evmwhumi",    VX (4,1100),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3282 {"vsro",        VX (4,1100),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3283 {"evmwhsmi",    VX (4,1101),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3284 {"vpkudum",     VX (4,1102),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3285 {"evmwhsmf",    VX (4,1103),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3286 {"evmwssf",     VX (4,1107),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3287 {"machhwo",     XO (4,  44,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3288 {"evmwumi",     VX (4,1112),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3289 {"machhwo.",    XO (4,  44,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3290 {"evmwsmi",     VX (4,1113),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3291 {"evmwsmf",     VX (4,1115),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3292 {"nmachhwo",    XO (4,  46,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3293 {"nmachhwo.",   XO (4,  46,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3294 {"ps_merge01",  XOPS(4,560,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3295 {"ps_merge01.", XOPS(4,560,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3296 {"evmwhssfa",   VX (4,1127),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3297 {"evmwlumia",   VX (4,1128),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3298 {"evmwhumia",   VX (4,1132),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3299 {"evmwhsmia",   VX (4,1133),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3300 {"evmwhsmfa",   VX (4,1135),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3301 {"evmwssfa",    VX (4,1139),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3302 {"evmwumia",    VX (4,1144),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3303 {"evmwsmia",    VX (4,1145),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3304 {"evmwsmfa",    VX (4,1147),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3305 {"vsubuwm",     VX (4,1152),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3306 {"vavguw",      VX (4,1154),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3307 {"vabsduw",     VX (4,1155),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3308 {"vmr",         VX (4,1156),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VBA}},
3309 {"vor",         VX (4,1156),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3310 {"vpmsumw",     VX (4,1160),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3311 {"vcmpequw.",   VXR(4, 134,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3312 {"udi2fcm.",    APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3313 {"udi2fcm",     APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3314 {"machhwsuo",   XO (4,  76,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3315 {"machhwsuo.",  XO (4,  76,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3316 {"ps_merge10",  XOPS(4,592,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3317 {"ps_merge10.", XOPS(4,592,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3318 {"vsubudm",     VX (4,1216),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3319 {"evaddusiaaw", VX (4,1216),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3320 {"evaddssiaaw", VX (4,1217),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3321 {"evsubfusiaaw",VX (4,1218),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3322 {"evsubfssiaaw",VX (4,1219),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3323 {"evmra",       VX (4,1220),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3324 {"vxor",        VX (4,1220),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3325 {"evdivws",     VX (4,1222),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3326 {"vcmpeqfp.",   VXR(4, 198,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3327 {"udi3fcm.",    APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3328 {"vcmpequd.",   VXR(4, 199,1),  VXR_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3329 {"udi3fcm",     APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3330 {"evdivwu",     VX (4,1223),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3331 {"vpmsumd",     VX (4,1224),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3332 {"evaddumiaaw", VX (4,1224),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3333 {"evaddsmiaaw", VX (4,1225),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3334 {"evsubfumiaaw",VX (4,1226),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3335 {"evsubfsmiaaw",VX (4,1227),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3336 {"vpkudus",     VX (4,1230),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3337 {"machhwso",    XO (4, 108,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3338 {"machhwso.",   XO (4, 108,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3339 {"nmachhwso",   XO (4, 110,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3340 {"nmachhwso.",  XO (4, 110,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3341 {"ps_merge11",  XOPS(4,624,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3342 {"ps_merge11.", XOPS(4,624,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3343 {"vsubuqm",     VX (4,1280),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3344 {"evmheusiaaw", VX (4,1280),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3345 {"evmhessiaaw", VX (4,1281),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3346 {"vavgsb",      VX (4,1282),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3347 {"evmhessfaaw", VX (4,1283),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3348 {"evmhousiaaw", VX (4,1284),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3349 {"vnot",        VX (4,1284),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VBA}},
3350 {"vnor",        VX (4,1284),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3351 {"evmhossiaaw", VX (4,1285),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3352 {"udi4fcm.",    APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3353 {"udi4fcm",     APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3354 {"evmhossfaaw", VX (4,1287),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3355 {"evmheumiaaw", VX (4,1288),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3356 {"vcipher",     VX (4,1288),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3357 {"vcipherlast", VX (4,1289),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3358 {"evmhesmiaaw", VX (4,1289),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3359 {"evmhesmfaaw", VX (4,1291),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3360 {"vgbbd",       VX (4,1292),    VXVA_MASK,   PPCVEC2,       PPCNONE,    {VD, VB}},
3361 {"evmhoumiaaw", VX (4,1292),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3362 {"evmhosmiaaw", VX (4,1293),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3363 {"evmhosmfaaw", VX (4,1295),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3364 {"macchwuo",    XO (4, 140,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3365 {"macchwuo.",   XO (4, 140,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3366 {"evmhegumiaa", VX (4,1320),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3367 {"evmhegsmiaa", VX (4,1321),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3368 {"evmhegsmfaa", VX (4,1323),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3369 {"evmhogumiaa", VX (4,1324),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3370 {"evmhogsmiaa", VX (4,1325),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3371 {"evmhogsmfaa", VX (4,1327),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3372 {"vsubcuq",     VX (4,1344),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3373 {"evmwlusiaaw", VX (4,1344),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3374 {"evmwlssiaaw", VX (4,1345),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3375 {"vavgsh",      VX (4,1346),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3376 {"vorc",        VX (4,1348),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3377 {"udi5fcm.",    APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3378 {"udi5fcm",     APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3379 {"vncipher",    VX (4,1352),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3380 {"evmwlumiaaw", VX (4,1352),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3381 {"vncipherlast",VX (4,1353),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3382 {"evmwlsmiaaw", VX (4,1353),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3383 {"vbpermq",     VX (4,1356),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3384 {"vpksdus",     VX (4,1358),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3385 {"evmwssfaa",   VX (4,1363),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3386 {"macchwo",     XO (4, 172,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3387 {"evmwumiaa",   VX (4,1368),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3388 {"macchwo.",    XO (4, 172,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3389 {"evmwsmiaa",   VX (4,1369),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3390 {"evmwsmfaa",   VX (4,1371),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3391 {"nmacchwo",    XO (4, 174,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3392 {"nmacchwo.",   XO (4, 174,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3393 {"evmheusianw", VX (4,1408),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3394 {"vsubcuw",     VX (4,1408),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3395 {"evmhessianw", VX (4,1409),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3396 {"vavgsw",      VX (4,1410),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3397 {"evmhessfanw", VX (4,1411),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3398 {"vnand",       VX (4,1412),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3399 {"evmhousianw", VX (4,1412),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3400 {"evmhossianw", VX (4,1413),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3401 {"udi6fcm.",    APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3402 {"udi6fcm",     APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3403 {"evmhossfanw", VX (4,1415),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3404 {"evmheumianw", VX (4,1416),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3405 {"evmhesmianw", VX (4,1417),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3406 {"evmhesmfanw", VX (4,1419),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3407 {"evmhoumianw", VX (4,1420),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3408 {"evmhosmianw", VX (4,1421),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3409 {"evmhosmfanw", VX (4,1423),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3410 {"macchwsuo",   XO (4, 204,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3411 {"macchwsuo.",  XO (4, 204,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3412 {"evmhegumian", VX (4,1448),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3413 {"evmhegsmian", VX (4,1449),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3414 {"evmhegsmfan", VX (4,1451),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3415 {"evmhogumian", VX (4,1452),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3416 {"evmhogsmian", VX (4,1453),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3417 {"evmhogsmfan", VX (4,1455),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3418 {"evmwlusianw", VX (4,1472),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3419 {"evmwlssianw", VX (4,1473),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3420 {"vsld",        VX (4,1476),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3421 {"vcmpgefp.",   VXR(4, 454,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3422 {"udi7fcm.",    APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3423 {"udi7fcm",     APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3424 {"vsbox",       VX (4,1480),    VXVB_MASK,   PPCVEC2,       PPCNONE,    {VD, VA}},
3425 {"evmwlumianw", VX (4,1480),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3426 {"evmwlsmianw", VX (4,1481),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3427 {"vpksdss",     VX (4,1486),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
3428 {"evmwssfan",   VX (4,1491),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3429 {"macchwso",    XO (4, 236,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3430 {"evmwumian",   VX (4,1496),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3431 {"macchwso.",   XO (4, 236,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3432 {"evmwsmian",   VX (4,1497),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3433 {"evmwsmfan",   VX (4,1499),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3434 {"nmacchwso",   XO (4, 238,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3435 {"nmacchwso.",  XO (4, 238,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3436 {"vsububs",     VX (4,1536),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3437 {"mfvscr",      VX (4,1540),    VXVAVB_MASK, PPCVEC|PPCVLE, PPCNONE,    {VD}},
3438 {"vcmpgtub.",   VXR(4, 518,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3439 {"udi8fcm.",    APU(4, 771,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3440 {"udi8fcm",     APU(4, 771,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3441 {"vsum4ubs",    VX (4,1544),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3442 {"vsubuhs",     VX (4,1600),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3443 {"mtvscr",      VX (4,1604),    VXVDVA_MASK, PPCVEC|PPCVLE, PPCNONE,    {VB}},
3444 {"vcmpgtuh.",   VXR(4, 582,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3445 {"vsum4shs",    VX (4,1608),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3446 {"udi9fcm.",    APU(4, 804,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3447 {"udi9fcm",     APU(4, 804,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3448 {"vupkhsw",     VX (4,1614),    VXVA_MASK,   PPCVEC2,       PPCNONE,    {VD, VB}},
3449 {"vsubuws",     VX (4,1664),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3450 {"vshasigmaw",  VX (4,1666),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, ST, SIX}},
3451 {"veqv",        VX (4,1668),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3452 {"vcmpgtuw.",   VXR(4, 646,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3453 {"udi10fcm.",   APU(4, 835,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3454 {"udi10fcm",    APU(4, 835,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3455 {"vsum2sws",    VX (4,1672),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3456 {"vmrgow",      VX (4,1676),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3457 {"vshasigmad",  VX (4,1730),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, ST, SIX}},
3458 {"vsrd",        VX (4,1732),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3459 {"vcmpgtfp.",   VXR(4, 710,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3460 {"udi11fcm.",   APU(4, 867,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3461 {"vcmpgtud.",   VXR(4, 711,1),  VXR_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3462 {"udi11fcm",    APU(4, 867,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3463 {"vupklsw",     VX (4,1742),    VXVA_MASK,   PPCVEC2,   PPCNONE,        {VD, VB}},
3464 {"vsubsbs",     VX (4,1792),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3465 {"vclzb",       VX (4,1794),    VXVA_MASK,   PPCVEC2,   PPCNONE,        {VD, VB}},
3466 {"vpopcntb",    VX (4,1795),    VXVA_MASK,   PPCVEC2,   PPCNONE,        {VD, VB}},
3467 {"vcmpgtsb.",   VXR(4, 774,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3468 {"udi12fcm.",   APU(4, 899,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3469 {"udi12fcm",    APU(4, 899,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3470 {"vsum4sbs",    VX (4,1800),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3471 {"maclhwuo",    XO (4, 396,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3472 {"maclhwuo.",   XO (4, 396,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3473 {"vsubshs",     VX (4,1856),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3474 {"vclzh",       VX (4,1858),    VXVA_MASK,   PPCVEC2,   PPCNONE,        {VD, VB}},
3475 {"vpopcnth",    VX (4,1859),    VXVA_MASK,   PPCVEC2,   PPCNONE,        {VD, VB}},
3476 {"vcmpgtsh.",   VXR(4, 838,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3477 {"udi13fcm.",   APU(4, 931,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3478 {"udi13fcm",    APU(4, 931,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3479 {"maclhwo",     XO (4, 428,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3480 {"maclhwo.",    XO (4, 428,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3481 {"nmaclhwo",    XO (4, 430,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3482 {"nmaclhwo.",   XO (4, 430,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3483 {"vsubsws",     VX (4,1920),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3484 {"vclzw",       VX (4,1922),    VXVA_MASK,   PPCVEC2,   PPCNONE,        {VD, VB}},
3485 {"vpopcntw",    VX (4,1923),    VXVA_MASK,   PPCVEC2,   PPCNONE,        {VD, VB}},
3486 {"vcmpgtsw.",   VXR(4, 902,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3487 {"udi14fcm.",   APU(4, 963,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3488 {"udi14fcm",    APU(4, 963,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3489 {"vsumsws",     VX (4,1928),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3490 {"vmrgew",      VX (4,1932),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3491 {"maclhwsuo",   XO (4, 460,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3492 {"maclhwsuo.",  XO (4, 460,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3493 {"vclzd",       VX (4,1986),    VXVA_MASK,   PPCVEC2,   PPCNONE,        {VD, VB}},
3494 {"vpopcntd",    VX (4,1987),    VXVA_MASK,   PPCVEC2,   PPCNONE,        {VD, VB}},
3495 {"vcmpbfp.",    VXR(4, 966,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
3496 {"udi15fcm.",   APU(4, 995,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3497 {"vcmpgtsd.",   VXR(4, 967,1),  VXR_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3498 {"udi15fcm",    APU(4, 995,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3499 {"maclhwso",    XO (4, 492,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3500 {"maclhwso.",   XO (4, 492,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3501 {"nmaclhwso",   XO (4, 494,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3502 {"nmaclhwso.",  XO (4, 494,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3503 {"dcbz_l",      X  (4,1014),    XRT_MASK,    PPCPS,     PPCNONE,        {RA, RB}},
3504
3505 {"mulli",       OP(7),          OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
3506 {"muli",        OP(7),          OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
3507
3508 {"subfic",      OP(8),          OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
3509 {"sfi",         OP(8),          OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
3510
3511 {"dozi",        OP(9),          OP_MASK,     M601,      PPCNONE,        {RT, RA, SI}},
3512
3513 {"cmplwi",      OPL(10,0),      OPL_MASK,    PPCCOM,    PPCNONE,        {OBF, RA, UISIGNOPT}},
3514 {"cmpldi",      OPL(10,1),      OPL_MASK,    PPC64,     PPCNONE,        {OBF, RA, UISIGNOPT}},
3515 {"cmpli",       OP(10),         OP_MASK,     PPC,       PPCNONE,        {BF, L, RA, UISIGNOPT}},
3516 {"cmpli",       OP(10),         OP_MASK,     PWRCOM,    PPC,            {BF, RA, UISIGNOPT}},
3517
3518 {"cmpwi",       OPL(11,0),      OPL_MASK,    PPCCOM,    PPCNONE,        {OBF, RA, SI}},
3519 {"cmpdi",       OPL(11,1),      OPL_MASK,    PPC64,     PPCNONE,        {OBF, RA, SI}},
3520 {"cmpi",        OP(11),         OP_MASK,     PPC,       PPCNONE,        {BF, L, RA, SI}},
3521 {"cmpi",        OP(11),         OP_MASK,     PWRCOM,    PPC,            {BF, RA, SI}},
3522
3523 {"addic",       OP(12),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
3524 {"ai",          OP(12),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
3525 {"subic",       OP(12),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, NSI}},
3526
3527 {"addic.",      OP(13),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
3528 {"ai.",         OP(13),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
3529 {"subic.",      OP(13),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, NSI}},
3530
3531 {"li",          OP(14),         DRA_MASK,    PPCCOM,    PPCNONE,        {RT, SI}},
3532 {"lil",         OP(14),         DRA_MASK,    PWRCOM,    PPCNONE,        {RT, SI}},
3533 {"addi",        OP(14),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, SI}},
3534 {"cal",         OP(14),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
3535 {"subi",        OP(14),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, NSI}},
3536 {"la",          OP(14),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RA0}},
3537
3538 {"lis",         OP(15),         DRA_MASK,    PPCCOM,    PPCNONE,        {RT, SISIGNOPT}},
3539 {"liu",         OP(15),         DRA_MASK,    PWRCOM,    PPCNONE,        {RT, SISIGNOPT}},
3540 {"addis",       OP(15),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, SISIGNOPT}},
3541 {"cau",         OP(15),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA0, SISIGNOPT}},
3542 {"subis",       OP(15),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, NSI}},
3543
3544 {"bdnz-",    BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
3545 {"bdnz+",    BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
3546 {"bdnz",     BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BD}},
3547 {"bdn",      BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BD}},
3548 {"bdnzl-",   BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
3549 {"bdnzl+",   BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
3550 {"bdnzl",    BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BD}},
3551 {"bdnl",     BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BD}},
3552 {"bdnza-",   BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
3553 {"bdnza+",   BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
3554 {"bdnza",    BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDA}},
3555 {"bdna",     BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BDA}},
3556 {"bdnzla-",  BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
3557 {"bdnzla+",  BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
3558 {"bdnzla",   BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDA}},
3559 {"bdnla",    BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BDA}},
3560 {"bdz-",     BBO(16,BODZ,0,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
3561 {"bdz+",     BBO(16,BODZ,0,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
3562 {"bdz",      BBO(16,BODZ,0,0),          BBOATBI_MASK,  COM,      PPCNONE,       {BD}},
3563 {"bdzl-",    BBO(16,BODZ,0,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
3564 {"bdzl+",    BBO(16,BODZ,0,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
3565 {"bdzl",     BBO(16,BODZ,0,1),          BBOATBI_MASK,  COM,      PPCNONE,       {BD}},
3566 {"bdza-",    BBO(16,BODZ,1,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
3567 {"bdza+",    BBO(16,BODZ,1,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
3568 {"bdza",     BBO(16,BODZ,1,0),          BBOATBI_MASK,  COM,      PPCNONE,       {BDA}},
3569 {"bdzla-",   BBO(16,BODZ,1,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
3570 {"bdzla+",   BBO(16,BODZ,1,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
3571 {"bdzla",    BBO(16,BODZ,1,1),          BBOATBI_MASK,  COM,      PPCNONE,       {BDA}},
3572
3573 {"bge-",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3574 {"bge+",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3575 {"bge",      BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3576 {"bnl-",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3577 {"bnl+",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3578 {"bnl",      BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3579 {"bgel-",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3580 {"bgel+",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3581 {"bgel",     BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3582 {"bnll-",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3583 {"bnll+",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3584 {"bnll",     BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3585 {"bgea-",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3586 {"bgea+",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3587 {"bgea",     BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3588 {"bnla-",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3589 {"bnla+",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3590 {"bnla",     BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3591 {"bgela-",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3592 {"bgela+",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3593 {"bgela",    BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3594 {"bnlla-",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3595 {"bnlla+",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3596 {"bnlla",    BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3597 {"ble-",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3598 {"ble+",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3599 {"ble",      BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3600 {"bng-",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3601 {"bng+",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3602 {"bng",      BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3603 {"blel-",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3604 {"blel+",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3605 {"blel",     BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3606 {"bngl-",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3607 {"bngl+",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3608 {"bngl",     BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3609 {"blea-",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3610 {"blea+",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3611 {"blea",     BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3612 {"bnga-",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3613 {"bnga+",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3614 {"bnga",     BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3615 {"blela-",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3616 {"blela+",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3617 {"blela",    BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3618 {"bngla-",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3619 {"bngla+",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3620 {"bngla",    BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3621 {"bne-",     BBOCB(16,BOF,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3622 {"bne+",     BBOCB(16,BOF,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3623 {"bne",      BBOCB(16,BOF,CBEQ,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3624 {"bnel-",    BBOCB(16,BOF,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3625 {"bnel+",    BBOCB(16,BOF,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3626 {"bnel",     BBOCB(16,BOF,CBEQ,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3627 {"bnea-",    BBOCB(16,BOF,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3628 {"bnea+",    BBOCB(16,BOF,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3629 {"bnea",     BBOCB(16,BOF,CBEQ,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3630 {"bnela-",   BBOCB(16,BOF,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3631 {"bnela+",   BBOCB(16,BOF,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3632 {"bnela",    BBOCB(16,BOF,CBEQ,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3633 {"bns-",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3634 {"bns+",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3635 {"bns",      BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3636 {"bnu-",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3637 {"bnu+",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3638 {"bnu",      BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
3639 {"bnsl-",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3640 {"bnsl+",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3641 {"bnsl",     BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3642 {"bnul-",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3643 {"bnul+",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3644 {"bnul",     BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
3645 {"bnsa-",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3646 {"bnsa+",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3647 {"bnsa",     BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3648 {"bnua-",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3649 {"bnua+",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3650 {"bnua",     BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
3651 {"bnsla-",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3652 {"bnsla+",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3653 {"bnsla",    BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3654 {"bnula-",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3655 {"bnula+",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3656 {"bnula",    BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
3657
3658 {"blt-",     BBOCB(16,BOT,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3659 {"blt+",     BBOCB(16,BOT,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3660 {"blt",      BBOCB(16,BOT,CBLT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3661 {"bltl-",    BBOCB(16,BOT,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3662 {"bltl+",    BBOCB(16,BOT,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3663 {"bltl",     BBOCB(16,BOT,CBLT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3664 {"blta-",    BBOCB(16,BOT,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3665 {"blta+",    BBOCB(16,BOT,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3666 {"blta",     BBOCB(16,BOT,CBLT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3667 {"bltla-",   BBOCB(16,BOT,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3668 {"bltla+",   BBOCB(16,BOT,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3669 {"bltla",    BBOCB(16,BOT,CBLT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3670 {"bgt-",     BBOCB(16,BOT,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3671 {"bgt+",     BBOCB(16,BOT,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3672 {"bgt",      BBOCB(16,BOT,CBGT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3673 {"bgtl-",    BBOCB(16,BOT,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3674 {"bgtl+",    BBOCB(16,BOT,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3675 {"bgtl",     BBOCB(16,BOT,CBGT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3676 {"bgta-",    BBOCB(16,BOT,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3677 {"bgta+",    BBOCB(16,BOT,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3678 {"bgta",     BBOCB(16,BOT,CBGT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3679 {"bgtla-",   BBOCB(16,BOT,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3680 {"bgtla+",   BBOCB(16,BOT,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3681 {"bgtla",    BBOCB(16,BOT,CBGT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3682 {"beq-",     BBOCB(16,BOT,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3683 {"beq+",     BBOCB(16,BOT,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3684 {"beq",      BBOCB(16,BOT,CBEQ,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3685 {"beql-",    BBOCB(16,BOT,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3686 {"beql+",    BBOCB(16,BOT,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3687 {"beql",     BBOCB(16,BOT,CBEQ,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3688 {"beqa-",    BBOCB(16,BOT,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3689 {"beqa+",    BBOCB(16,BOT,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3690 {"beqa",     BBOCB(16,BOT,CBEQ,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3691 {"beqla-",   BBOCB(16,BOT,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3692 {"beqla+",   BBOCB(16,BOT,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3693 {"beqla",    BBOCB(16,BOT,CBEQ,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3694 {"bso-",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3695 {"bso+",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3696 {"bso",      BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3697 {"bun-",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3698 {"bun+",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3699 {"bun",      BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
3700 {"bsol-",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3701 {"bsol+",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3702 {"bsol",     BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3703 {"bunl-",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3704 {"bunl+",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3705 {"bunl",     BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
3706 {"bsoa-",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3707 {"bsoa+",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3708 {"bsoa",     BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3709 {"buna-",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3710 {"buna+",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3711 {"buna",     BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
3712 {"bsola-",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3713 {"bsola+",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3714 {"bsola",    BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3715 {"bunla-",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3716 {"bunla+",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3717 {"bunla",    BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
3718
3719 {"bdnzf-",   BBO(16,BODNZF,0,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
3720 {"bdnzf+",   BBO(16,BODNZF,0,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
3721 {"bdnzf",    BBO(16,BODNZF,0,0),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
3722 {"bdnzfl-",  BBO(16,BODNZF,0,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
3723 {"bdnzfl+",  BBO(16,BODNZF,0,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
3724 {"bdnzfl",   BBO(16,BODNZF,0,1),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
3725 {"bdnzfa-",  BBO(16,BODNZF,1,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
3726 {"bdnzfa+",  BBO(16,BODNZF,1,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
3727 {"bdnzfa",   BBO(16,BODNZF,1,0),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
3728 {"bdnzfla-", BBO(16,BODNZF,1,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
3729 {"bdnzfla+", BBO(16,BODNZF,1,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
3730 {"bdnzfla",  BBO(16,BODNZF,1,1),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
3731 {"bdzf-",    BBO(16,BODZF,0,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
3732 {"bdzf+",    BBO(16,BODZF,0,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
3733 {"bdzf",     BBO(16,BODZF,0,0),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
3734 {"bdzfl-",   BBO(16,BODZF,0,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
3735 {"bdzfl+",   BBO(16,BODZF,0,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
3736 {"bdzfl",    BBO(16,BODZF,0,1),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
3737 {"bdzfa-",   BBO(16,BODZF,1,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
3738 {"bdzfa+",   BBO(16,BODZF,1,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
3739 {"bdzfa",    BBO(16,BODZF,1,0),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
3740 {"bdzfla-",  BBO(16,BODZF,1,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
3741 {"bdzfla+",  BBO(16,BODZF,1,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
3742 {"bdzfla",   BBO(16,BODZF,1,1),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
3743
3744 {"bf-",      BBO(16,BOF,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
3745 {"bf+",      BBO(16,BOF,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
3746 {"bf",       BBO(16,BOF,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
3747 {"bbf",      BBO(16,BOF,0,0),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
3748 {"bfl-",     BBO(16,BOF,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
3749 {"bfl+",     BBO(16,BOF,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
3750 {"bfl",      BBO(16,BOF,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
3751 {"bbfl",     BBO(16,BOF,0,1),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
3752 {"bfa-",     BBO(16,BOF,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
3753 {"bfa+",     BBO(16,BOF,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
3754 {"bfa",      BBO(16,BOF,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
3755 {"bbfa",     BBO(16,BOF,1,0),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
3756 {"bfla-",    BBO(16,BOF,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
3757 {"bfla+",    BBO(16,BOF,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
3758 {"bfla",     BBO(16,BOF,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
3759 {"bbfla",    BBO(16,BOF,1,1),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
3760
3761 {"bdnzt-",   BBO(16,BODNZT,0,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
3762 {"bdnzt+",   BBO(16,BODNZT,0,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
3763 {"bdnzt",    BBO(16,BODNZT,0,0),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
3764 {"bdnztl-",  BBO(16,BODNZT,0,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
3765 {"bdnztl+",  BBO(16,BODNZT,0,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
3766 {"bdnztl",   BBO(16,BODNZT,0,1),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
3767 {"bdnzta-",  BBO(16,BODNZT,1,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
3768 {"bdnzta+",  BBO(16,BODNZT,1,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
3769 {"bdnzta",   BBO(16,BODNZT,1,0),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
3770 {"bdnztla-", BBO(16,BODNZT,1,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
3771 {"bdnztla+", BBO(16,BODNZT,1,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
3772 {"bdnztla",  BBO(16,BODNZT,1,1),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
3773 {"bdzt-",    BBO(16,BODZT,0,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
3774 {"bdzt+",    BBO(16,BODZT,0,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
3775 {"bdzt",     BBO(16,BODZT,0,0),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
3776 {"bdztl-",   BBO(16,BODZT,0,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
3777 {"bdztl+",   BBO(16,BODZT,0,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
3778 {"bdztl",    BBO(16,BODZT,0,1),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
3779 {"bdzta-",   BBO(16,BODZT,1,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
3780 {"bdzta+",   BBO(16,BODZT,1,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
3781 {"bdzta",    BBO(16,BODZT,1,0),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
3782 {"bdztla-",  BBO(16,BODZT,1,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
3783 {"bdztla+",  BBO(16,BODZT,1,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
3784 {"bdztla",   BBO(16,BODZT,1,1),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
3785
3786 {"bt-",      BBO(16,BOT,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
3787 {"bt+",      BBO(16,BOT,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
3788 {"bt",       BBO(16,BOT,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
3789 {"bbt",      BBO(16,BOT,0,0),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
3790 {"btl-",     BBO(16,BOT,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
3791 {"btl+",     BBO(16,BOT,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
3792 {"btl",      BBO(16,BOT,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
3793 {"bbtl",     BBO(16,BOT,0,1),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
3794 {"bta-",     BBO(16,BOT,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
3795 {"bta+",     BBO(16,BOT,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
3796 {"bta",      BBO(16,BOT,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
3797 {"bbta",     BBO(16,BOT,1,0),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
3798 {"btla-",    BBO(16,BOT,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
3799 {"btla+",    BBO(16,BOT,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
3800 {"btla",     BBO(16,BOT,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
3801 {"bbtla",    BBO(16,BOT,1,1),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
3802
3803 {"bc-",         B(16,0,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDM}},
3804 {"bc+",         B(16,0,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDP}},
3805 {"bc",          B(16,0,0),      B_MASK,      COM,       PPCNONE,        {BO, BI, BD}},
3806 {"bcl-",        B(16,0,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDM}},
3807 {"bcl+",        B(16,0,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDP}},
3808 {"bcl",         B(16,0,1),      B_MASK,      COM,       PPCNONE,        {BO, BI, BD}},
3809 {"bca-",        B(16,1,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDMA}},
3810 {"bca+",        B(16,1,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDPA}},
3811 {"bca",         B(16,1,0),      B_MASK,      COM,       PPCNONE,        {BO, BI, BDA}},
3812 {"bcla-",       B(16,1,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDMA}},
3813 {"bcla+",       B(16,1,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDPA}},
3814 {"bcla",        B(16,1,1),      B_MASK,      COM,       PPCNONE,        {BO, BI, BDA}},
3815
3816 {"svc",         SC(17,0,0),     SC_MASK,     POWER,     PPCNONE,        {SVC_LEV, FL1, FL2}},
3817 {"svcl",        SC(17,0,1),     SC_MASK,     POWER,     PPCNONE,        {SVC_LEV, FL1, FL2}},
3818 {"sc",          SC(17,1,0),     SC_MASK,     PPC,       PPCNONE,        {LEV}},
3819 {"svca",        SC(17,1,0),     SC_MASK,     PWRCOM,    PPCNONE,        {SV}},
3820 {"svcla",       SC(17,1,1),     SC_MASK,     POWER,     PPCNONE,        {SV}},
3821
3822 {"b",           B(18,0,0),      B_MASK,      COM,       PPCNONE,        {LI}},
3823 {"bl",          B(18,0,1),      B_MASK,      COM,       PPCNONE,        {LI}},
3824 {"ba",          B(18,1,0),      B_MASK,      COM,       PPCNONE,        {LIA}},
3825 {"bla",         B(18,1,1),      B_MASK,      COM,       PPCNONE,        {LIA}},
3826
3827 {"mcrf",      XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCNONE,        {BF, BFA}},
3828
3829 {"bdnzlr",   XLO(19,BODNZ,16,0),        XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
3830 {"bdnzlr-",  XLO(19,BODNZ,16,0),        XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
3831 {"bdnzlrl",  XLO(19,BODNZ,16,1),        XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
3832 {"bdnzlrl-", XLO(19,BODNZ,16,1),        XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
3833 {"bdnzlr+",  XLO(19,BODNZP,16,0),       XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
3834 {"bdnzlrl+", XLO(19,BODNZP,16,1),       XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
3835 {"bdzlr",    XLO(19,BODZ,16,0),         XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
3836 {"bdzlr-",   XLO(19,BODZ,16,0),         XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
3837 {"bdzlrl",   XLO(19,BODZ,16,1),         XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
3838 {"bdzlrl-",  XLO(19,BODZ,16,1),         XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
3839 {"bdzlr+",   XLO(19,BODZP,16,0),        XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
3840 {"bdzlrl+",  XLO(19,BODZP,16,1),        XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
3841 {"blr",      XLO(19,BOU,16,0),          XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
3842 {"br",       XLO(19,BOU,16,0),          XLBOBIBB_MASK, PWRCOM,   PPCNONE,       {0}},
3843 {"blrl",     XLO(19,BOU,16,1),          XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
3844 {"brl",      XLO(19,BOU,16,1),          XLBOBIBB_MASK, PWRCOM,   PPCNONE,       {0}},
3845 {"bdnzlr-",  XLO(19,BODNZM4,16,0),      XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
3846 {"bdnzlrl-", XLO(19,BODNZM4,16,1),      XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
3847 {"bdnzlr+",  XLO(19,BODNZP4,16,0),      XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
3848 {"bdnzlrl+", XLO(19,BODNZP4,16,1),      XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
3849 {"bdzlr-",   XLO(19,BODZM4,16,0),       XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
3850 {"bdzlrl-",  XLO(19,BODZM4,16,1),       XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
3851 {"bdzlr+",   XLO(19,BODZP4,16,0),       XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
3852 {"bdzlrl+",  XLO(19,BODZP4,16,1),       XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
3853
3854 {"bgelr",    XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3855 {"bgelr-",   XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3856 {"bger",     XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3857 {"bnllr",    XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3858 {"bnllr-",   XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3859 {"bnlr",     XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3860 {"bgelrl",   XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3861 {"bgelrl-",  XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3862 {"bgerl",    XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3863 {"bnllrl",   XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3864 {"bnllrl-",  XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3865 {"bnlrl",    XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3866 {"blelr",    XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3867 {"blelr-",   XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3868 {"bler",     XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3869 {"bnglr",    XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3870 {"bnglr-",   XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3871 {"bngr",     XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3872 {"blelrl",   XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3873 {"blelrl-",  XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3874 {"blerl",    XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3875 {"bnglrl",   XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3876 {"bnglrl-",  XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3877 {"bngrl",    XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3878 {"bnelr",    XLOCB(19,BOF,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3879 {"bnelr-",   XLOCB(19,BOF,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3880 {"bner",     XLOCB(19,BOF,CBEQ,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3881 {"bnelrl",   XLOCB(19,BOF,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3882 {"bnelrl-",  XLOCB(19,BOF,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3883 {"bnerl",    XLOCB(19,BOF,CBEQ,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3884 {"bnslr",    XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3885 {"bnslr-",   XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3886 {"bnsr",     XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3887 {"bnulr",    XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3888 {"bnulr-",   XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3889 {"bnslrl",   XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3890 {"bnslrl-",  XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3891 {"bnsrl",    XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3892 {"bnulrl",   XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3893 {"bnulrl-",  XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3894 {"bgelr+",   XLOCB(19,BOFP,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3895 {"bnllr+",   XLOCB(19,BOFP,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3896 {"bgelrl+",  XLOCB(19,BOFP,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3897 {"bnllrl+",  XLOCB(19,BOFP,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3898 {"blelr+",   XLOCB(19,BOFP,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3899 {"bnglr+",   XLOCB(19,BOFP,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3900 {"blelrl+",  XLOCB(19,BOFP,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3901 {"bnglrl+",  XLOCB(19,BOFP,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3902 {"bnelr+",   XLOCB(19,BOFP,CBEQ,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3903 {"bnelrl+",  XLOCB(19,BOFP,CBEQ,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3904 {"bnslr+",   XLOCB(19,BOFP,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3905 {"bnulr+",   XLOCB(19,BOFP,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3906 {"bnslrl+",  XLOCB(19,BOFP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3907 {"bnulrl+",  XLOCB(19,BOFP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3908 {"bgelr-",   XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3909 {"bnllr-",   XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3910 {"bgelrl-",  XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3911 {"bnllrl-",  XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3912 {"blelr-",   XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3913 {"bnglr-",   XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3914 {"blelrl-",  XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3915 {"bnglrl-",  XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3916 {"bnelr-",   XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3917 {"bnelrl-",  XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3918 {"bnslr-",   XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3919 {"bnulr-",   XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3920 {"bnslrl-",  XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3921 {"bnulrl-",  XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3922 {"bgelr+",   XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3923 {"bnllr+",   XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3924 {"bgelrl+",  XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3925 {"bnllrl+",  XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3926 {"blelr+",   XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3927 {"bnglr+",   XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3928 {"blelrl+",  XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3929 {"bnglrl+",  XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3930 {"bnelr+",   XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3931 {"bnelrl+",  XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3932 {"bnslr+",   XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3933 {"bnulr+",   XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3934 {"bnslrl+",  XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3935 {"bnulrl+",  XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3936 {"bltlr",    XLOCB(19,BOT,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3937 {"bltlr-",   XLOCB(19,BOT,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3938 {"bltr",     XLOCB(19,BOT,CBLT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3939 {"bltlrl",   XLOCB(19,BOT,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3940 {"bltlrl-",  XLOCB(19,BOT,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3941 {"bltrl",    XLOCB(19,BOT,CBLT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3942 {"bgtlr",    XLOCB(19,BOT,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3943 {"bgtlr-",   XLOCB(19,BOT,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3944 {"bgtr",     XLOCB(19,BOT,CBGT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3945 {"bgtlrl",   XLOCB(19,BOT,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3946 {"bgtlrl-",  XLOCB(19,BOT,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3947 {"bgtrl",    XLOCB(19,BOT,CBGT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3948 {"beqlr",    XLOCB(19,BOT,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3949 {"beqlr-",   XLOCB(19,BOT,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3950 {"beqr",     XLOCB(19,BOT,CBEQ,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3951 {"beqlrl",   XLOCB(19,BOT,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3952 {"beqlrl-",  XLOCB(19,BOT,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3953 {"beqrl",    XLOCB(19,BOT,CBEQ,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3954 {"bsolr",    XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3955 {"bsolr-",   XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3956 {"bsor",     XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3957 {"bunlr",    XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3958 {"bunlr-",   XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3959 {"bsolrl",   XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3960 {"bsolrl-",  XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3961 {"bsorl",    XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3962 {"bunlrl",   XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3963 {"bunlrl-",  XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3964 {"bltlr+",   XLOCB(19,BOTP,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3965 {"bltlrl+",  XLOCB(19,BOTP,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3966 {"bgtlr+",   XLOCB(19,BOTP,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3967 {"bgtlrl+",  XLOCB(19,BOTP,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3968 {"beqlr+",   XLOCB(19,BOTP,CBEQ,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3969 {"beqlrl+",  XLOCB(19,BOTP,CBEQ,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3970 {"bsolr+",   XLOCB(19,BOTP,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3971 {"bunlr+",   XLOCB(19,BOTP,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3972 {"bsolrl+",  XLOCB(19,BOTP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3973 {"bunlrl+",  XLOCB(19,BOTP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3974 {"bltlr-",   XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3975 {"bltlrl-",  XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3976 {"bgtlr-",   XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3977 {"bgtlrl-",  XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3978 {"beqlr-",   XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3979 {"beqlrl-",  XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3980 {"bsolr-",   XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3981 {"bunlr-",   XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3982 {"bsolrl-",  XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3983 {"bunlrl-",  XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3984 {"bltlr+",   XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3985 {"bltlrl+",  XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3986 {"bgtlr+",   XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3987 {"bgtlrl+",  XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3988 {"beqlr+",   XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3989 {"beqlrl+",  XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3990 {"bsolr+",   XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3991 {"bunlr+",   XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3992 {"bsolrl+",  XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3993 {"bunlrl+",  XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3994
3995 {"bdnzflr",  XLO(19,BODNZF,16,0),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3996 {"bdnzflr-", XLO(19,BODNZF,16,0),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3997 {"bdnzflrl", XLO(19,BODNZF,16,1),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3998 {"bdnzflrl-",XLO(19,BODNZF,16,1),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3999 {"bdnzflr+", XLO(19,BODNZFP,16,0),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4000 {"bdnzflrl+",XLO(19,BODNZFP,16,1),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4001 {"bdzflr",   XLO(19,BODZF,16,0),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4002 {"bdzflr-",  XLO(19,BODZF,16,0),        XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4003 {"bdzflrl",  XLO(19,BODZF,16,1),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4004 {"bdzflrl-", XLO(19,BODZF,16,1),        XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4005 {"bdzflr+",  XLO(19,BODZFP,16,0),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4006 {"bdzflrl+", XLO(19,BODZFP,16,1),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4007 {"bflr",     XLO(19,BOF,16,0),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4008 {"bflr-",    XLO(19,BOF,16,0),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4009 {"bbfr",     XLO(19,BOF,16,0),          XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
4010 {"bflrl",    XLO(19,BOF,16,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4011 {"bflrl-",   XLO(19,BOF,16,1),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4012 {"bbfrl",    XLO(19,BOF,16,1),          XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
4013 {"bflr+",    XLO(19,BOFP,16,0),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4014 {"bflrl+",   XLO(19,BOFP,16,1),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4015 {"bflr-",    XLO(19,BOFM4,16,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4016 {"bflrl-",   XLO(19,BOFM4,16,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4017 {"bflr+",    XLO(19,BOFP4,16,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4018 {"bflrl+",   XLO(19,BOFP4,16,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4019 {"bdnztlr",  XLO(19,BODNZT,16,0),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4020 {"bdnztlr-", XLO(19,BODNZT,16,0),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4021 {"bdnztlrl", XLO(19,BODNZT,16,1),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4022 {"bdnztlrl-",XLO(19,BODNZT,16,1),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4023 {"bdnztlr+", XLO(19,BODNZTP,16,0),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4024 {"bdnztlrl+",XLO(19,BODNZTP,16,1),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4025 {"bdztlr",   XLO(19,BODZT,16,0),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4026 {"bdztlr-",  XLO(19,BODZT,16,0),        XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4027 {"bdztlrl",  XLO(19,BODZT,16,1),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4028 {"bdztlrl-", XLO(19,BODZT,16,1),        XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4029 {"bdztlr+",  XLO(19,BODZTP,16,0),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4030 {"bdztlrl+", XLO(19,BODZTP,16,1),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4031 {"btlr",     XLO(19,BOT,16,0),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4032 {"btlr-",    XLO(19,BOT,16,0),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4033 {"bbtr",     XLO(19,BOT,16,0),          XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
4034 {"btlrl",    XLO(19,BOT,16,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4035 {"btlrl-",   XLO(19,BOT,16,1),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4036 {"bbtrl",    XLO(19,BOT,16,1),          XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
4037 {"btlr+",    XLO(19,BOTP,16,0),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4038 {"btlrl+",   XLO(19,BOTP,16,1),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4039 {"btlr-",    XLO(19,BOTM4,16,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4040 {"btlrl-",   XLO(19,BOTM4,16,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4041 {"btlr+",    XLO(19,BOTP4,16,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4042 {"btlrl+",   XLO(19,BOTP4,16,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4043
4044 {"bclr-",    XLYLK(19,16,0,0),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
4045 {"bclrl-",   XLYLK(19,16,0,1),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
4046 {"bclr+",    XLYLK(19,16,1,0),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
4047 {"bclrl+",   XLYLK(19,16,1,1),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
4048 {"bclr",     XLLK(19,16,0),             XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
4049 {"bcr",      XLLK(19,16,0),             XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
4050 {"bclrl",    XLLK(19,16,1),             XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
4051 {"bcrl",     XLLK(19,16,1),             XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
4052
4053 {"rfid",        XL(19,18),      0xffffffff,  PPC64,     PPCNONE,        {0}},
4054
4055 {"crnot",       XL(19,33),      XL_MASK,     PPCCOM,    PPCNONE,        {BT, BA, BBA}},
4056 {"crnor",       XL(19,33),      XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
4057 {"rfmci",       X(19,38),   0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCNONE, {0}},
4058
4059 {"rfdi",        XL(19,39),      0xffffffff,  E500MC,    PPCNONE,        {0}},
4060 {"rfi",         XL(19,50),      0xffffffff,  COM,       PPCNONE,        {0}},
4061 {"rfci",        XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCNONE, {0}},
4062
4063 {"rfsvc",       XL(19,82),      0xffffffff,  POWER,     PPCNONE,        {0}},
4064
4065 {"rfgi",        XL(19,102),   0xffffffff, E500MC|PPCA2, PPCNONE,        {0}},
4066
4067 {"crandc",      XL(19,129),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
4068
4069 {"rfebb",       XL(19,146),     XLS_MASK,    POWER8,    PPCNONE,        {SXL}},
4070
4071 {"isync",       XL(19,150),     0xffffffff,  PPCCOM,    PPCNONE,        {0}},
4072 {"ics",         XL(19,150),     0xffffffff,  PWRCOM,    PPCNONE,        {0}},
4073
4074 {"crclr",       XL(19,193),     XL_MASK,     PPCCOM,    PPCNONE,        {BT, BAT, BBA}},
4075 {"crxor",       XL(19,193),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
4076
4077 {"dnh",         X(19,198),      X_MASK,      E500MC,    PPCNONE,        {DUI, DUIS}},
4078
4079 {"crnand",      XL(19,225),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
4080
4081 {"crand",       XL(19,257),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
4082
4083 {"hrfid",       XL(19,274),     0xffffffff, POWER5|CELL, PPC476,        {0}},
4084
4085 {"crset",       XL(19,289),     XL_MASK,     PPCCOM,    PPCNONE,        {BT, BAT, BBA}},
4086 {"creqv",       XL(19,289),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
4087
4088 {"doze",        XL(19,402),     0xffffffff,  POWER6,    PPCNONE,        {0}},
4089
4090 {"crorc",       XL(19,417),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
4091
4092 {"nap",         XL(19,434),     0xffffffff,  POWER6,    PPCNONE,        {0}},
4093
4094 {"crmove",      XL(19,449),     XL_MASK,     PPCCOM,    PPCNONE,        {BT, BA, BBA}},
4095 {"cror",        XL(19,449),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
4096
4097 {"sleep",       XL(19,466),     0xffffffff,  POWER6,    PPCNONE,        {0}},
4098 {"rvwinkle",    XL(19,498),     0xffffffff,  POWER6,    PPCNONE,        {0}},
4099
4100 {"bctr",    XLO(19,BOU,528,0),          XLBOBIBB_MASK, COM,      PPCNONE,       {0}},
4101 {"bctrl",   XLO(19,BOU,528,1),          XLBOBIBB_MASK, COM,      PPCNONE,       {0}},
4102
4103 {"bgectr",  XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4104 {"bgectr-", XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4105 {"bnlctr",  XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4106 {"bnlctr-", XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4107 {"bgectrl", XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4108 {"bgectrl-",XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4109 {"bnlctrl", XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4110 {"bnlctrl-",XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4111 {"blectr",  XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4112 {"blectr-", XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4113 {"bngctr",  XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4114 {"bngctr-", XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4115 {"blectrl", XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4116 {"blectrl-",XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4117 {"bngctrl", XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4118 {"bngctrl-",XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4119 {"bnectr",  XLOCB(19,BOF,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4120 {"bnectr-", XLOCB(19,BOF,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4121 {"bnectrl", XLOCB(19,BOF,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4122 {"bnectrl-",XLOCB(19,BOF,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4123 {"bnsctr",  XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4124 {"bnsctr-", XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4125 {"bnuctr",  XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4126 {"bnuctr-", XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4127 {"bnsctrl", XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4128 {"bnsctrl-",XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4129 {"bnuctrl", XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4130 {"bnuctrl-",XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4131 {"bgectr+", XLOCB(19,BOFP,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4132 {"bnlctr+", XLOCB(19,BOFP,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4133 {"bgectrl+",XLOCB(19,BOFP,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4134 {"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4135 {"blectr+", XLOCB(19,BOFP,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4136 {"bngctr+", XLOCB(19,BOFP,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4137 {"blectrl+",XLOCB(19,BOFP,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4138 {"bngctrl+",XLOCB(19,BOFP,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4139 {"bnectr+", XLOCB(19,BOFP,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4140 {"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4141 {"bnsctr+", XLOCB(19,BOFP,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4142 {"bnuctr+", XLOCB(19,BOFP,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4143 {"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4144 {"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4145 {"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4146 {"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4147 {"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4148 {"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4149 {"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4150 {"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4151 {"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4152 {"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4153 {"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4154 {"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4155 {"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4156 {"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4157 {"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4158 {"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4159 {"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4160 {"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4161 {"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4162 {"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4163 {"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4164 {"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4165 {"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4166 {"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4167 {"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4168 {"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4169 {"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4170 {"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4171 {"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4172 {"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4173 {"bltctr",  XLOCB(19,BOT,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4174 {"bltctr-", XLOCB(19,BOT,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4175 {"bltctrl", XLOCB(19,BOT,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4176 {"bltctrl-",XLOCB(19,BOT,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4177 {"bgtctr",  XLOCB(19,BOT,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4178 {"bgtctr-", XLOCB(19,BOT,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4179 {"bgtctrl", XLOCB(19,BOT,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4180 {"bgtctrl-",XLOCB(19,BOT,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4181 {"beqctr",  XLOCB(19,BOT,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4182 {"beqctr-", XLOCB(19,BOT,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4183 {"beqctrl", XLOCB(19,BOT,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4184 {"beqctrl-",XLOCB(19,BOT,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4185 {"bsoctr",  XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4186 {"bsoctr-", XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4187 {"bunctr",  XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4188 {"bunctr-", XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4189 {"bsoctrl", XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4190 {"bsoctrl-",XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4191 {"bunctrl", XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4192 {"bunctrl-",XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4193 {"bltctr+", XLOCB(19,BOTP,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4194 {"bltctrl+",XLOCB(19,BOTP,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4195 {"bgtctr+", XLOCB(19,BOTP,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4196 {"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4197 {"beqctr+", XLOCB(19,BOTP,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4198 {"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4199 {"bsoctr+", XLOCB(19,BOTP,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4200 {"bunctr+", XLOCB(19,BOTP,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4201 {"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4202 {"bunctrl+",XLOCB(19,BOTP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4203 {"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4204 {"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4205 {"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4206 {"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4207 {"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4208 {"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4209 {"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4210 {"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4211 {"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4212 {"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4213 {"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4214 {"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4215 {"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4216 {"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4217 {"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4218 {"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4219 {"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4220 {"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4221 {"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4222 {"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4223
4224 {"bfctr",   XLO(19,BOF,528,0),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4225 {"bfctr-",  XLO(19,BOF,528,0),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4226 {"bfctrl",  XLO(19,BOF,528,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4227 {"bfctrl-", XLO(19,BOF,528,1),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4228 {"bfctr+",  XLO(19,BOFP,528,0),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4229 {"bfctrl+", XLO(19,BOFP,528,1),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4230 {"bfctr-",  XLO(19,BOFM4,528,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4231 {"bfctrl-", XLO(19,BOFM4,528,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4232 {"bfctr+",  XLO(19,BOFP4,528,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4233 {"bfctrl+", XLO(19,BOFP4,528,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4234 {"btctr",   XLO(19,BOT,528,0),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4235 {"btctr-",  XLO(19,BOT,528,0),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4236 {"btctrl",  XLO(19,BOT,528,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4237 {"btctrl-", XLO(19,BOT,528,1),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4238 {"btctr+",  XLO(19,BOTP,528,0),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4239 {"btctrl+", XLO(19,BOTP,528,1),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4240 {"btctr-",  XLO(19,BOTM4,528,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4241 {"btctrl-", XLO(19,BOTM4,528,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4242 {"btctr+",  XLO(19,BOTP4,528,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4243 {"btctrl+", XLO(19,BOTP4,528,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4244
4245 {"bcctr-",  XLYLK(19,528,0,0),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
4246 {"bcctrl-", XLYLK(19,528,0,1),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
4247 {"bcctr+",  XLYLK(19,528,1,0),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
4248 {"bcctrl+", XLYLK(19,528,1,1),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
4249 {"bcctr",   XLLK(19,528,0),             XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
4250 {"bcc",     XLLK(19,528,0),             XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
4251 {"bcctrl",  XLLK(19,528,1),             XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
4252 {"bccl",    XLLK(19,528,1),             XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
4253
4254 {"bctar-",  XLYLK(19,560,0,0),          XLYBB_MASK,    POWER8,   PPCNONE,       {BOE, BI}},
4255 {"bctarl-", XLYLK(19,560,0,1),          XLYBB_MASK,    POWER8,   PPCNONE,       {BOE, BI}},
4256 {"bctar+",  XLYLK(19,560,1,0),          XLYBB_MASK,    POWER8,   PPCNONE,       {BOE, BI}},
4257 {"bctarl+", XLYLK(19,560,1,1),          XLYBB_MASK,    POWER8,   PPCNONE,       {BOE, BI}},
4258 {"bctar",   XLLK(19,560,0),             XLBH_MASK,     POWER8,   PPCNONE,       {BO, BI, BH}},
4259 {"bctarl",  XLLK(19,560,1),             XLBH_MASK,     POWER8,   PPCNONE,       {BO, BI, BH}},
4260
4261 {"rlwimi",      M(20,0),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4262 {"rlimi",       M(20,0),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4263
4264 {"rlwimi.",     M(20,1),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4265 {"rlimi.",      M(20,1),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4266
4267 {"rotlwi",      MME(21,31,0),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, SH}},
4268 {"clrlwi",      MME(21,31,0),   MSHME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, MB}},
4269 {"rlwinm",      M(21,0),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4270 {"rlinm",       M(21,0),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4271 {"rotlwi.",     MME(21,31,1),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, SH}},
4272 {"clrlwi.",     MME(21,31,1),   MSHME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, MB}},
4273 {"rlwinm.",     M(21,1),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4274 {"rlinm.",      M(21,1),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4275
4276 {"rlmi",        M(22,0),        M_MASK,      M601,      PPCNONE,        {RA, RS, RB, MBE, ME}},
4277 {"rlmi.",       M(22,1),        M_MASK,      M601,      PPCNONE,        {RA, RS, RB, MBE, ME}},
4278
4279 {"rotlw",       MME(23,31,0),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, RB}},
4280 {"rlwnm",       M(23,0),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
4281 {"rlnm",        M(23,0),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
4282 {"rotlw.",      MME(23,31,1),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, RB}},
4283 {"rlwnm.",      M(23,1),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
4284 {"rlnm.",       M(23,1),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
4285
4286 {"nop",         OP(24),         0xffffffff,  PPCCOM,    PPCNONE,        {0}},
4287 {"ori",         OP(24),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
4288 {"oril",        OP(24),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
4289
4290 {"oris",        OP(25),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
4291 {"oriu",        OP(25),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
4292
4293 {"xnop",        OP(26),         0xffffffff,  PPCCOM,    PPCNONE,        {0}},
4294 {"xori",        OP(26),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
4295 {"xoril",       OP(26),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
4296
4297 {"xoris",       OP(27),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
4298 {"xoriu",       OP(27),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
4299
4300 {"andi.",       OP(28),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
4301 {"andil.",      OP(28),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
4302
4303 {"andis.",      OP(29),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
4304 {"andiu.",      OP(29),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
4305
4306 {"rotldi",      MD(30,0,0),     MDMB_MASK,   PPC64,     PPCNONE,        {RA, RS, SH6}},
4307 {"clrldi",      MD(30,0,0),     MDSH_MASK,   PPC64,     PPCNONE,        {RA, RS, MB6}},
4308 {"rldicl",      MD(30,0,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
4309 {"rotldi.",     MD(30,0,1),     MDMB_MASK,   PPC64,     PPCNONE,        {RA, RS, SH6}},
4310 {"clrldi.",     MD(30,0,1),     MDSH_MASK,   PPC64,     PPCNONE,        {RA, RS, MB6}},
4311 {"rldicl.",     MD(30,0,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
4312
4313 {"rldicr",      MD(30,1,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, ME6}},
4314 {"rldicr.",     MD(30,1,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, ME6}},
4315
4316 {"rldic",       MD(30,2,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
4317 {"rldic.",      MD(30,2,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
4318
4319 {"rldimi",      MD(30,3,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
4320 {"rldimi.",     MD(30,3,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
4321
4322 {"rotld",       MDS(30,8,0),    MDSMB_MASK,  PPC64,     PPCNONE,        {RA, RS, RB}},
4323 {"rldcl",       MDS(30,8,0),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, MB6}},
4324 {"rotld.",      MDS(30,8,1),    MDSMB_MASK,  PPC64,     PPCNONE,        {RA, RS, RB}},
4325 {"rldcl.",      MDS(30,8,1),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, MB6}},
4326
4327 {"rldcr",       MDS(30,9,0),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, ME6}},
4328 {"rldcr.",      MDS(30,9,1),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, ME6}},
4329
4330 {"cmpw",        XOPL(31,0,0),   XCMPL_MASK,  PPCCOM,    PPCNONE,        {OBF, RA, RB}},
4331 {"cmpd",        XOPL(31,0,1),   XCMPL_MASK,  PPC64,     PPCNONE,        {OBF, RA, RB}},
4332 {"cmp",         X(31,0),        XCMP_MASK,   PPC|PPCVLE, PPCNONE,       {BF, L, RA, RB}},
4333 {"cmp",         X(31,0),        XCMPL_MASK,  PWRCOM,    PPC,            {BF, RA, RB}},
4334
4335 {"twlgt",       XTO(31,4,TOLGT), XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4336 {"tlgt",        XTO(31,4,TOLGT), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4337 {"twllt",       XTO(31,4,TOLLT), XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4338 {"tllt",        XTO(31,4,TOLLT), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4339 {"tweq",        XTO(31,4,TOEQ),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4340 {"teq",         XTO(31,4,TOEQ),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4341 {"twlge",       XTO(31,4,TOLGE), XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4342 {"tlge",        XTO(31,4,TOLGE), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4343 {"twlnl",       XTO(31,4,TOLNL), XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4344 {"tlnl",        XTO(31,4,TOLNL), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4345 {"twlle",       XTO(31,4,TOLLE), XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4346 {"tlle",        XTO(31,4,TOLLE), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4347 {"twlng",       XTO(31,4,TOLNG), XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4348 {"tlng",        XTO(31,4,TOLNG), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4349 {"twgt",        XTO(31,4,TOGT),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4350 {"tgt",         XTO(31,4,TOGT),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4351 {"twge",        XTO(31,4,TOGE),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4352 {"tge",         XTO(31,4,TOGE),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4353 {"twnl",        XTO(31,4,TONL),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4354 {"tnl",         XTO(31,4,TONL),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4355 {"twlt",        XTO(31,4,TOLT),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4356 {"tlt",         XTO(31,4,TOLT),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4357 {"twle",        XTO(31,4,TOLE),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4358 {"tle",         XTO(31,4,TOLE),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4359 {"twng",        XTO(31,4,TONG),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4360 {"tng",         XTO(31,4,TONG),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4361 {"twne",        XTO(31,4,TONE),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4362 {"tne",         XTO(31,4,TONE),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4363 {"trap",        XTO(31,4,TOU),   0xffffffff, PPCCOM|PPCVLE, PPCNONE,    {0}},
4364 {"twu",         XTO(31,4,TOU),   XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4365 {"tu",          XTO(31,4,TOU),   XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4366 {"tw",          X(31,4),         X_MASK, PPCCOM|PPCVLE, PPCNONE,        {TO, RA, RB}},
4367 {"t",           X(31,4),         X_MASK,     PWRCOM,    PPCNONE,        {TO, RA, RB}},
4368
4369 {"lvsl",        X(31,6),        X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VD, RA0, RB}},
4370 {"lvebx",       X(31,7),        X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VD, RA0, RB}},
4371 {"lbfcmx",      APU(31,7,0),    APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4372
4373 {"subfc",       XO(31,8,0,0),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4374 {"sf",          XO(31,8,0,0),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4375 {"subc",        XO(31,8,0,0),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RB, RA}},
4376 {"subfc.",      XO(31,8,0,1),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4377 {"sf.",         XO(31,8,0,1),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4378 {"subc.",       XO(31,8,0,1),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RB, RA}},
4379
4380 {"mulhdu",      XO(31,9,0,0),   XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
4381 {"mulhdu.",     XO(31,9,0,1),   XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
4382
4383 {"addc",        XO(31,10,0,0),  XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4384 {"a",           XO(31,10,0,0),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4385 {"addc.",       XO(31,10,0,1),  XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4386 {"a.",          XO(31,10,0,1),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4387
4388 {"mulhwu",      XO(31,11,0,0),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
4389 {"mulhwu.",     XO(31,11,0,1),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
4390
4391 {"lxsiwzx",     X(31,12),       XX1_MASK,    PPCVSX2,   PPCNONE,        {XT6, RA0, RB}},
4392
4393 {"isellt",      X(31,15),       X_MASK,      PPCISEL,   PPCNONE,        {RT, RA0, RB}},
4394
4395 {"tlbilxlpid",  XTO(31,18,0),   XTO_MASK, E500MC|PPCA2, PPCNONE,        {0}},
4396 {"tlbilxpid",   XTO(31,18,1),   XTO_MASK, E500MC|PPCA2, PPCNONE,        {0}},
4397 {"tlbilxva",    XTO(31,18,3),   XTO_MASK, E500MC|PPCA2, PPCNONE,        {RA0, RB}},
4398 {"tlbilx",      X(31,18),       X_MASK,   E500MC|PPCA2, PPCNONE,        {T, RA0, RB}},
4399
4400 {"mfcr",        XFXM(31,19,0,0), XFXFXM_MASK, POWER4,   PPCNONE,        {RT, FXM4}},
4401 {"mfcr",        XFXM(31,19,0,0), XRARB_MASK, COM|PPCVLE, POWER4,        {RT}},
4402 {"mfocrf",      XFXM(31,19,0,1), XFXFXM_MASK, COM|PPCVLE, PPCNONE,      {RT, FXM}},
4403
4404 {"lwarx",       X(31,20),       XEH_MASK,    PPC|PPCVLE, PPCNONE,       {RT, RA0, RB, EH}},
4405
4406 {"ldx",         X(31,21),       X_MASK,      PPC64|PPCVLE, PPCNONE,     {RT, RA0, RB}},
4407
4408 {"icbt",        X(31,22),       X_MASK,      BOOKE|PPCE300|PPCA2|PPC476|PPCVLE, PPCNONE, {CT, RA0, RB}},
4409
4410 {"lwzx",        X(31,23),       X_MASK,      PPCCOM|PPCVLE, PPCNONE,    {RT, RA0, RB}},
4411 {"lx",          X(31,23),       X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
4412
4413 {"slw",         XRC(31,24,0),   X_MASK,      PPCCOM|PPCVLE, PPCNONE,    {RA, RS, RB}},
4414 {"sl",          XRC(31,24,0),   X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
4415 {"slw.",        XRC(31,24,1),   X_MASK,      PPCCOM|PPCVLE, PPCNONE,    {RA, RS, RB}},
4416 {"sl.",         XRC(31,24,1),   X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
4417
4418 {"cntlzw",      XRC(31,26,0),   XRB_MASK,    PPCCOM|PPCVLE, PPCNONE,    {RA, RS}},
4419 {"cntlz",       XRC(31,26,0),   XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
4420 {"cntlzw.",     XRC(31,26,1),   XRB_MASK,    PPCCOM|PPCVLE, PPCNONE,    {RA, RS}},
4421 {"cntlz.",      XRC(31,26,1),   XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
4422
4423 {"sld",         XRC(31,27,0),   X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
4424 {"sld.",        XRC(31,27,1),   X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
4425
4426 {"and",         XRC(31,28,0),   X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4427 {"and.",        XRC(31,28,1),   X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4428
4429 {"maskg",       XRC(31,29,0),   X_MASK,      M601,      PPCA2,          {RA, RS, RB}},
4430 {"maskg.",      XRC(31,29,1),   X_MASK,      M601,      PPCA2,          {RA, RS, RB}},
4431
4432 {"ldepx",       X(31,29),       X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
4433
4434 {"waitasec",    X(31,30),       XRTRARB_MASK,POWER8,    PPCNONE,        {0}},
4435
4436 {"lwepx",       X(31,31),       X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
4437
4438 {"cmplw",       XOPL(31,32,0),  XCMPL_MASK,  PPCCOM|PPCVLE, PPCNONE,    {OBF, RA, RB}},
4439 {"cmpld",       XOPL(31,32,1),  XCMPL_MASK,  PPC64,     PPCNONE,        {OBF, RA, RB}},
4440 {"cmpl",        X(31,32),       XCMP_MASK,   PPC|PPCVLE, PPCNONE,       {BF, L, RA, RB}},
4441 {"cmpl",        X(31,32),       XCMPL_MASK,  PWRCOM,    PPC,            {BF, RA, RB}},
4442
4443 {"lvsr",        X(31,38),       X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VD, RA0, RB}},
4444 {"lvehx",       X(31,39),       X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VD, RA0, RB}},
4445 {"lhfcmx",      APU(31,39,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4446
4447 {"mviwsplt",    X(31,46),       X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA, RB}},
4448
4449 {"iselgt",      X(31,47),       X_MASK,      PPCISEL,   PPCNONE,        {RT, RA0, RB}},
4450
4451 {"lvewx",       X(31,71),       X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VD, RA0, RB}},
4452
4453 {"addg6s",      XO(31,74,0,0),  XO_MASK,     POWER6,    PPCNONE,        {RT, RA, RB}},
4454
4455 {"lxsiwax",     X(31,76),       XX1_MASK,    PPCVSX2,   PPCNONE,        {XT6, RA0, RB}},
4456
4457 {"iseleq",      X(31,79),       X_MASK,      PPCISEL,   PPCNONE,        {RT, RA0, RB}},
4458
4459 {"isel",        XISEL(31,15), XISEL_MASK, PPCISEL|TITAN|PPCVLE, PPCNONE, {RT, RA0, RB, CRB}},
4460
4461 {"subf",        XO(31,40,0,0),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
4462 {"sub",         XO(31,40,0,0),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RB, RA}},
4463 {"subf.",       XO(31,40,0,1),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
4464 {"sub.",        XO(31,40,0,1),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RB, RA}},
4465
4466 {"mfvsrd",      X(31,51),       XX1RB_MASK,   PPCVSX2,  PPCNONE,        {RA, XS6}},
4467 {"mffprd",      X(31,51),       XX1RB_MASK|1, PPCVSX2,  PPCNONE,        {RA, FRS}},
4468 {"mfvrd",       X(31,51)|1,     XX1RB_MASK|1, PPCVSX2,  PPCNONE,        {RA, VS}},
4469 {"eratilx",     X(31,51),       X_MASK,      PPCA2,     PPCNONE,        {ERAT_T, RA, RB}},
4470
4471 {"lbarx",       X(31,52),       XEH_MASK,    POWER8|PPCVLE, PPCNONE,    {RT, RA0, RB, EH}},
4472
4473 {"ldux",        X(31,53),       X_MASK,      PPC64|PPCVLE, PPCNONE,     {RT, RAL, RB}},
4474
4475 {"dcbst",       X(31,54),       XRT_MASK,    PPC|PPCVLE, PPCNONE,       {RA0, RB}},
4476
4477 {"lwzux",       X(31,55),       X_MASK,      PPCCOM|PPCVLE, PPCNONE,    {RT, RAL, RB}},
4478 {"lux",         X(31,55),       X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
4479
4480 {"cntlzd",      XRC(31,58,0),   XRB_MASK,    PPC64|PPCVLE, PPCNONE,     {RA, RS}},
4481 {"cntlzd.",     XRC(31,58,1),   XRB_MASK,    PPC64|PPCVLE, PPCNONE,     {RA, RS}},
4482
4483 {"andc",        XRC(31,60,0),   X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4484 {"andc.",       XRC(31,60,1),   X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4485
4486 {"waitrsv",     X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, PPCNONE,    {0}},
4487 {"waitimpl",    X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, PPCNONE,    {0}},
4488 {"wait",        X(31,62),       XWC_MASK,    E500MC|PPCA2|PPCVLE, PPCNONE, {WC}},
4489
4490 {"dcbstep",     XRT(31,63,0),   XRT_MASK,    E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
4491
4492 {"tdlgt",       XTO(31,68,TOLGT), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4493 {"tdllt",       XTO(31,68,TOLLT), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4494 {"tdeq",        XTO(31,68,TOEQ),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4495 {"tdlge",       XTO(31,68,TOLGE), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4496 {"tdlnl",       XTO(31,68,TOLNL), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4497 {"tdlle",       XTO(31,68,TOLLE), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4498 {"tdlng",       XTO(31,68,TOLNG), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4499 {"tdgt",        XTO(31,68,TOGT),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4500 {"tdge",        XTO(31,68,TOGE),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4501 {"tdnl",        XTO(31,68,TONL),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4502 {"tdlt",        XTO(31,68,TOLT),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4503 {"tdle",        XTO(31,68,TOLE),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4504 {"tdng",        XTO(31,68,TONG),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4505 {"tdne",        XTO(31,68,TONE),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4506 {"tdu",         XTO(31,68,TOU),   XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4507 {"td",          X(31,68),       X_MASK,      PPC64|PPCVLE, PPCNONE,     {TO, RA, RB}},
4508
4509 {"lwfcmx",      APU(31,71,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4510 {"mulhd",       XO(31,73,0,0),  XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
4511 {"mulhd.",      XO(31,73,0,1),  XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
4512
4513 {"mulhw",       XO(31,75,0,0),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
4514 {"mulhw.",      XO(31,75,0,1),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
4515
4516 {"dlmzb",       XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN|PPCVLE, PPCNONE, {RA, RS, RB}},
4517 {"dlmzb.",      XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN|PPCVLE, PPCNONE, {RA, RS, RB}},
4518
4519 {"mtsrd",       X(31,82),  XRB_MASK|(1<<20), PPC64,     PPCNONE,        {SR, RS}},
4520
4521 {"mfmsr",       X(31,83),       XRARB_MASK,  COM|PPCVLE, PPCNONE,       {RT}},
4522
4523 {"ldarx",       X(31,84),       XEH_MASK,    PPC64|PPCVLE, PPCNONE,     {RT, RA0, RB, EH}},
4524
4525 {"dcbfl",       XOPL(31,86,1),  XRT_MASK,    POWER5,    PPC476,         {RA0, RB}},
4526 {"dcbf",        X(31,86),       XLRT_MASK,   PPC|PPCVLE, PPCNONE,       {RA0, RB, L}},
4527
4528 {"lbzx",        X(31,87),       X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RA0, RB}},
4529
4530 {"lbepx",       X(31,95),       X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
4531
4532 {"dni",         XRC(31,97,1),   XRB_MASK,    E6500,     PPCNONE,        {DUI, DCTL}},
4533
4534 {"lvx",         X(31,103),      X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VD, RA0, RB}},
4535 {"lqfcmx",      APU(31,103,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4536
4537 {"neg",         XO(31,104,0,0), XORB_MASK,   COM|PPCVLE, PPCNONE,       {RT, RA}},
4538 {"neg.",        XO(31,104,0,1), XORB_MASK,   COM|PPCVLE, PPCNONE,       {RT, RA}},
4539
4540 {"mul",         XO(31,107,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4541 {"mul.",        XO(31,107,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4542
4543 {"mvidsplt",    X(31,110),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA, RB}},
4544
4545 {"mtsrdin",     X(31,114),      XRA_MASK,    PPC64,     PPCNONE,        {RS, RB}},
4546
4547 {"mffprwz",     X(31,115),      XX1RB_MASK|1, PPCVSX2,  PPCNONE,        {RA, FRS}},
4548 {"mfvrwz",      X(31,115)|1,    XX1RB_MASK|1, PPCVSX2,  PPCNONE,        {RA, VS}},
4549 {"mfvsrwz",     X(31,115),      XX1RB_MASK,   PPCVSX2,  PPCNONE,        {RA, XS6}},
4550
4551 {"lharx",       X(31,116),      XEH_MASK,    POWER8|PPCVLE, PPCNONE,    {RT, RA0, RB, EH}},
4552
4553 {"clf",         X(31,118),      XTO_MASK,    POWER,     PPCNONE,        {RA, RB}},
4554
4555 {"lbzux",       X(31,119),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RAL, RB}},
4556
4557 {"popcntb",     X(31,122),      XRB_MASK,    POWER5|PPCVLE, PPCNONE,    {RA, RS}},
4558
4559 {"not",         XRC(31,124,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RBS}},
4560 {"nor",         XRC(31,124,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4561 {"not.",        XRC(31,124,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RBS}},
4562 {"nor.",        XRC(31,124,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4563
4564 {"dcbfep",      XRT(31,127,0),  XRT_MASK,    E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
4565
4566 {"wrtee",       X(31,131),      XRARB_MASK,  PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RS}},
4567
4568 {"dcbtstls",    X(31,134),      X_MASK,      PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
4569
4570 {"stvebx",      X(31,135),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA0, RB}},
4571 {"stbfcmx",     APU(31,135,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4572
4573 {"subfe",       XO(31,136,0,0), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4574 {"sfe",         XO(31,136,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4575 {"subfe.",      XO(31,136,0,1), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4576 {"sfe.",        XO(31,136,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4577
4578 {"adde",        XO(31,138,0,0), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4579 {"ae",          XO(31,138,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4580 {"adde.",       XO(31,138,0,1), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4581 {"ae.",         XO(31,138,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4582
4583 {"stxsiwx",     X(31,140),      XX1_MASK,    PPCVSX2,   PPCNONE,        {XS6, RA0, RB}},
4584
4585 {"msgsndp",     XRTRA(31,142,0,0), XRTRA_MASK, POWER8,  PPCNONE,        {RB}},
4586 {"dcbtstlse",   X(31,142),      X_MASK,      PPCCHLK,   E500MC,         {CT, RA0, RB}},
4587
4588 {"mtcr",        XFXM(31,144,0xff,0), XRARB_MASK, COM,   PPCNONE,        {RS}},
4589 {"mtcrf",       XFXM(31,144,0,0), XFXFXM_MASK, COM|PPCVLE, PPCNONE,     {FXM, RS}},
4590 {"mtocrf",      XFXM(31,144,0,1), XFXFXM_MASK, COM|PPCVLE, PPCNONE,     {FXM, RS}},
4591
4592 {"mtmsr",       X(31,146),      XRLARB_MASK, COM|PPCVLE, PPCNONE,       {RS, A_L}},
4593
4594 {"mtsle",       X(31,147),    XRTLRARB_MASK, POWER8,    PPCNONE,        {L}},
4595
4596 {"eratsx",      XRC(31,147,0),  X_MASK,      PPCA2,     PPCNONE,        {RT, RA0, RB}},
4597 {"eratsx.",     XRC(31,147,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, RA0, RB}},
4598
4599 {"stdx",        X(31,149),      X_MASK,      PPC64|PPCVLE, PPCNONE,     {RS, RA0, RB}},
4600
4601 {"stwcx.",      XRC(31,150,1),  X_MASK,      PPC|PPCVLE, PPCNONE,       {RS, RA0, RB}},
4602
4603 {"stwx",        X(31,151),      X_MASK,      PPCCOM|PPCVLE, PPCNONE,    {RS, RA0, RB}},
4604 {"stx",         X(31,151),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA, RB}},
4605
4606 {"slq",         XRC(31,152,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4607 {"slq.",        XRC(31,152,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4608
4609 {"sle",         XRC(31,153,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4610 {"sle.",        XRC(31,153,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4611
4612 {"prtyw",       X(31,154),      XRB_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS}},
4613
4614 {"stdepx",      X(31,157),      X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
4615
4616 {"stwepx",      X(31,159),      X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
4617
4618 {"wrteei",      X(31,163),      XE_MASK,     PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {E}},
4619
4620 {"dcbtls",      X(31,166),      X_MASK,      PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
4621
4622 {"stvehx",      X(31,167),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA0, RB}},
4623 {"sthfcmx",     APU(31,167,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4624
4625 {"msgclrp",     XRTRA(31,174,0,0), XRTRA_MASK, POWER8,  PPCNONE,        {RB}},
4626 {"dcbtlse",     X(31,174),      X_MASK,      PPCCHLK,   E500MC,         {CT, RA0, RB}},
4627
4628 {"mtmsrd",      X(31,178),      XRLARB_MASK, PPC64,     PPCNONE,        {RS, A_L}},
4629
4630 {"mtvsrd",      X(31,179),      XX1RB_MASK,   PPCVSX2,  PPCNONE,        {XT6, RA}},
4631 {"mtfprd",      X(31,179),      XX1RB_MASK|1, PPCVSX2,  PPCNONE,        {FRT, RA}},
4632 {"mtvrd",       X(31,179)|1,    XX1RB_MASK|1, PPCVSX2,  PPCNONE,        {VD, RA}},
4633 {"eratre",      X(31,179),      X_MASK,      PPCA2,     PPCNONE,        {RT, RA, WS}},
4634
4635 {"stdux",       X(31,181),      X_MASK,      PPC64|PPCVLE, PPCNONE,     {RS, RAS, RB}},
4636
4637 {"stqcx.",      XRC(31,182,1),  X_MASK,      POWER8,    PPCNONE,        {RSQ, RA0, RB}},
4638 {"wchkall",     X(31,182),      X_MASK,      PPCA2,     PPCNONE,        {OBF}},
4639
4640 {"stwux",       X(31,183),      X_MASK,      PPCCOM|PPCVLE, PPCNONE,    {RS, RAS, RB}},
4641 {"stux",        X(31,183),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, RB}},
4642
4643 {"sliq",        XRC(31,184,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4644 {"sliq.",       XRC(31,184,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4645
4646 {"prtyd",       X(31,186),      XRB_MASK, POWER6|PPCA2, PPCNONE,        {RA, RS}},
4647
4648 {"icblq.",      XRC(31,198,1),  X_MASK,      E6500,     PPCNONE,        {CT, RA0, RB}},
4649
4650 {"stvewx",      X(31,199),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA0, RB}},
4651 {"stwfcmx",     APU(31,199,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4652
4653 {"subfze",      XO(31,200,0,0), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
4654 {"sfze",        XO(31,200,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4655 {"subfze.",     XO(31,200,0,1), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
4656 {"sfze.",       XO(31,200,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4657
4658 {"addze",       XO(31,202,0,0), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
4659 {"aze",         XO(31,202,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4660 {"addze.",      XO(31,202,0,1), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
4661 {"aze.",        XO(31,202,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4662
4663 {"msgsnd",      XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8|PPCVLE, PPCNONE, {RB}},
4664
4665 {"mtsr",        X(31,210), XRB_MASK|(1<<20), COM,       NON32,          {SR, RS}},
4666
4667 {"mtfprwa",     X(31,211),      XX1RB_MASK|1, PPCVSX2,  PPCNONE,        {FRT, RA}},
4668 {"mtvrwa",      X(31,211)|1,    XX1RB_MASK|1, PPCVSX2,  PPCNONE,        {VD, RA}},
4669 {"mtvsrwa",     X(31,211),      XX1RB_MASK,   PPCVSX2,  PPCNONE,        {XT6, RA}},
4670 {"eratwe",      X(31,211),      X_MASK,      PPCA2,     PPCNONE,        {RS, RA, WS}},
4671
4672 {"ldawx.",      XRC(31,212,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, RA0, RB}},
4673
4674 {"stdcx.",      XRC(31,214,1),  X_MASK,      PPC64|PPCVLE, PPCNONE,     {RS, RA0, RB}},
4675
4676 {"stbx",        X(31,215),      X_MASK,      COM|PPCVLE, PPCNONE,       {RS, RA0, RB}},
4677
4678 {"sllq",        XRC(31,216,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4679 {"sllq.",       XRC(31,216,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4680
4681 {"sleq",        XRC(31,217,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4682 {"sleq.",       XRC(31,217,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4683
4684 {"stbepx",      X(31,223),      X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
4685
4686 {"icblc",       X(31,230),      X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
4687
4688 {"stvx",        X(31,231),      X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VS, RA0, RB}},
4689 {"stqfcmx",     APU(31,231,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4690
4691 {"subfme",      XO(31,232,0,0), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
4692 {"sfme",        XO(31,232,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4693 {"subfme.",     XO(31,232,0,1), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
4694 {"sfme.",       XO(31,232,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4695
4696 {"mulld",       XO(31,233,0,0), XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
4697 {"mulld.",      XO(31,233,0,1), XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
4698
4699 {"addme",       XO(31,234,0,0), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
4700 {"ame",         XO(31,234,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4701 {"addme.",      XO(31,234,0,1), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
4702 {"ame.",        XO(31,234,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4703
4704 {"mullw",       XO(31,235,0,0), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4705 {"muls",        XO(31,235,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4706 {"mullw.",      XO(31,235,0,1), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4707 {"muls.",       XO(31,235,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4708
4709 {"icblce",      X(31,238),      X_MASK,      PPCCHLK,   E500MC|PPCA2,   {CT, RA, RB}},
4710 {"msgclr",      XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8|PPCVLE, PPCNONE, {RB}},
4711 {"mtsrin",      X(31,242),      XRA_MASK,    PPC,       NON32,          {RS, RB}},
4712 {"mtsri",       X(31,242),      XRA_MASK,    POWER,     NON32,          {RS, RB}},
4713
4714 {"mtfprwz",     X(31,243),      XX1RB_MASK|1, PPCVSX2,  PPCNONE,        {FRT, RA}},
4715 {"mtvrwz",      X(31,243)|1,    XX1RB_MASK|1, PPCVSX2,  PPCNONE,        {VD, RA}},
4716 {"mtvsrwz",     X(31,243),      XX1RB_MASK,   PPCVSX2,  PPCNONE,        {XT6, RA}},
4717
4718 {"dcbtstt",     XRT(31,246,0x10), XRT_MASK,  POWER7,    PPCNONE,        {RA0, RB}},
4719 {"dcbtst",      X(31,246),      X_MASK,      POWER4,    DCBT_EO,        {RA0, RB, CT}},
4720 {"dcbtst",      X(31,246),      X_MASK,      DCBT_EO,   PPCNONE,        {CT, RA0, RB}},
4721 {"dcbtst",      X(31,246),      X_MASK,      PPC,       POWER4|DCBT_EO, {RA0, RB}},
4722
4723 {"stbux",       X(31,247),      X_MASK,      COM|PPCVLE, PPCNONE,       {RS, RAS, RB}},
4724
4725 {"slliq",       XRC(31,248,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4726 {"slliq.",      XRC(31,248,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4727
4728 {"bpermd",      X(31,252),      X_MASK,   POWER7|PPCA2, PPCNONE,        {RA, RS, RB}},
4729
4730 {"dcbtstep",    XRT(31,255,0),  X_MASK,   E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
4731
4732 {"mfdcrx",      X(31,259),      X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {RS, RA}},
4733 {"mfdcrx.",     XRC(31,259,1),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA}},
4734
4735 {"lvexbx",      X(31,261),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
4736
4737 {"icbt",        X(31,262),      XRT_MASK,    PPC403,    PPCNONE,        {RA, RB}},
4738
4739 {"lvepxl",      X(31,263),      X_MASK,      PPCVEC2|PPCVLE, PPCNONE,   {VD, RA0, RB}},
4740
4741 {"ldfcmx",      APU(31,263,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4742 {"doz",         XO(31,264,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4743 {"doz.",        XO(31,264,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4744
4745 {"add",         XO(31,266,0,0), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4746 {"cax",         XO(31,266,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4747 {"add.",        XO(31,266,0,1), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4748 {"cax.",        XO(31,266,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4749
4750 {"ehpriv",      X(31,270),      0xffffffff, E500MC|PPCA2|PPCVLE, PPCNONE, {0}},
4751
4752 {"tlbiel",      X(31,274),      XRTLRA_MASK, POWER4,    PPC476,         {RB, L}},
4753
4754 {"mfapidi",     X(31,275),      X_MASK,      BOOKE,     TITAN,          {RT, RA}},
4755
4756 {"lqarx",       X(31,276),      XEH_MASK,    POWER8,    PPCNONE,        {RTQ, RAX, RBX, EH}},
4757
4758 {"lscbx",       XRC(31,277,0),  X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
4759 {"lscbx.",      XRC(31,277,1),  X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
4760
4761 {"dcbtt",       XRT(31,278,0x10), XRT_MASK,  POWER7,    PPCNONE,        {RA0, RB}},
4762 {"dcbt",        X(31,278),      X_MASK,      POWER4,    DCBT_EO,        {RA0, RB, CT}},
4763 {"dcbt",        X(31,278),      X_MASK,      DCBT_EO,   PPCNONE,        {CT, RA0, RB}},
4764 {"dcbt",        X(31,278),      X_MASK,      PPC,       POWER4|DCBT_EO, {RA0, RB}},
4765
4766 {"lhzx",        X(31,279),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RA0, RB}},
4767
4768 {"cdtbcd",      X(31,282),      XRB_MASK,    POWER6,    PPCNONE,        {RA, RS}},
4769
4770 {"eqv",         XRC(31,284,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4771 {"eqv.",        XRC(31,284,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4772
4773 {"lhepx",       X(31,287),      X_MASK,   E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
4774
4775 {"mfdcrux",     X(31,291),      X_MASK,      PPC464|PPCVLE, PPCNONE,    {RS, RA}},
4776
4777 {"lvexhx",      X(31,293),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
4778 {"lvepx",       X(31,295),      X_MASK,      PPCVEC2|PPCVLE, PPCNONE,   {VD, RA0, RB}},
4779
4780 {"mfbhrbe",     X(31,302),      X_MASK,      POWER8,    PPCNONE,        {RT, BHRBE}},
4781
4782 {"tlbie",       X(31,306),      XRA_MASK,    POWER7,    TITAN,          {RB, RS}},
4783 {"tlbie",       X(31,306),      XRTLRA_MASK, PPC,       POWER7|TITAN,   {RB, L}},
4784 {"tlbi",        X(31,306),      XRT_MASK,    POWER,     PPCNONE,        {RA0, RB}},
4785
4786 {"eciwx",       X(31,310),      X_MASK,      PPC,       TITAN,          {RT, RA0, RB}},
4787
4788 {"lhzux",       X(31,311),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RAL, RB}},
4789
4790 {"cbcdtd",      X(31,314),      XRB_MASK,    POWER6,    PPCNONE,        {RA, RS}},
4791
4792 {"xor",         XRC(31,316,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4793 {"xor.",        XRC(31,316,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4794
4795 {"dcbtep",      XRT(31,319,0),  X_MASK,   E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
4796
4797 {"mfexisr",     XSPR(31,323, 64), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4798 {"mfexier",     XSPR(31,323, 66), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4799 {"mfbr0",       XSPR(31,323,128), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4800 {"mfbr1",       XSPR(31,323,129), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4801 {"mfbr2",       XSPR(31,323,130), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4802 {"mfbr3",       XSPR(31,323,131), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4803 {"mfbr4",       XSPR(31,323,132), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4804 {"mfbr5",       XSPR(31,323,133), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4805 {"mfbr6",       XSPR(31,323,134), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4806 {"mfbr7",       XSPR(31,323,135), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4807 {"mfbear",      XSPR(31,323,144), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4808 {"mfbesr",      XSPR(31,323,145), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4809 {"mfiocr",      XSPR(31,323,160), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4810 {"mfdmacr0",    XSPR(31,323,192), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4811 {"mfdmact0",    XSPR(31,323,193), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4812 {"mfdmada0",    XSPR(31,323,194), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4813 {"mfdmasa0",    XSPR(31,323,195), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4814 {"mfdmacc0",    XSPR(31,323,196), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4815 {"mfdmacr1",    XSPR(31,323,200), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4816 {"mfdmact1",    XSPR(31,323,201), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4817 {"mfdmada1",    XSPR(31,323,202), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4818 {"mfdmasa1",    XSPR(31,323,203), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4819 {"mfdmacc1",    XSPR(31,323,204), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4820 {"mfdmacr2",    XSPR(31,323,208), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4821 {"mfdmact2",    XSPR(31,323,209), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4822 {"mfdmada2",    XSPR(31,323,210), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4823 {"mfdmasa2",    XSPR(31,323,211), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4824 {"mfdmacc2",    XSPR(31,323,212), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4825 {"mfdmacr3",    XSPR(31,323,216), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4826 {"mfdmact3",    XSPR(31,323,217), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4827 {"mfdmada3",    XSPR(31,323,218), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4828 {"mfdmasa3",    XSPR(31,323,219), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4829 {"mfdmacc3",    XSPR(31,323,220), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4830 {"mfdmasr",     XSPR(31,323,224), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4831 {"mfdcr",       X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {RT, SPR}},
4832 {"mfdcr.",      XRC(31,323,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, SPR}},
4833
4834 {"lvexwx",      X(31,325),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
4835
4836 {"dcread",      X(31,326),      X_MASK,  PPC476|TITAN,  PPCNONE,        {RT, RA0, RB}},
4837
4838 {"div",         XO(31,331,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4839 {"div.",        XO(31,331,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4840
4841 {"lxvdsx",      X(31,332),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA0, RB}},
4842
4843 {"mfpmr",       X(31,334),      X_MASK, PPCPMR|PPCE300|PPCVLE, PPCNONE, {RT, PMR}},
4844 {"mftmr",       X(31,366),      X_MASK, PPCTMR|E6500,   PPCNONE,        {RT, TMR}},
4845
4846 {"mfmq",        XSPR(31,339,  0), XSPR_MASK, M601,      PPCNONE,        {RT}},
4847 {"mfxer",       XSPR(31,339,  1), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RT}},
4848 {"mfrtcu",      XSPR(31,339,  4), XSPR_MASK, COM,       TITAN,          {RT}},
4849 {"mfrtcl",      XSPR(31,339,  5), XSPR_MASK, COM,       TITAN,          {RT}},
4850 {"mfdec",       XSPR(31,339,  6), XSPR_MASK, MFDEC1,    PPCNONE,        {RT}},
4851 {"mflr",        XSPR(31,339,  8), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RT}},
4852 {"mfctr",       XSPR(31,339,  9), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RT}},
4853 {"mftid",       XSPR(31,339, 17), XSPR_MASK, POWER,     PPCNONE,        {RT}},
4854 {"mfdsisr",     XSPR(31,339, 18), XSPR_MASK, COM,       TITAN,          {RT}},
4855 {"mfdar",       XSPR(31,339, 19), XSPR_MASK, COM,       TITAN,          {RT}},
4856 {"mfdec",       XSPR(31,339, 22), XSPR_MASK, MFDEC2,    MFDEC1,         {RT}},
4857 {"mfsdr0",      XSPR(31,339, 24), XSPR_MASK, POWER,     PPCNONE,        {RT}},
4858 {"mfsdr1",      XSPR(31,339, 25), XSPR_MASK, COM,       TITAN,          {RT}},
4859 {"mfsrr0",      XSPR(31,339, 26), XSPR_MASK, COM,       PPCNONE,        {RT}},
4860 {"mfsrr1",      XSPR(31,339, 27), XSPR_MASK, COM,       PPCNONE,        {RT}},
4861 {"mfcfar",      XSPR(31,339, 28), XSPR_MASK, POWER6,    PPCNONE,        {RT}},
4862 {"mfpid",       XSPR(31,339, 48), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4863 {"mfcsrr0",     XSPR(31,339, 58), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4864 {"mfcsrr1",     XSPR(31,339, 59), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4865 {"mfdear",      XSPR(31,339, 61), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4866 {"mfesr",       XSPR(31,339, 62), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4867 {"mfivpr",      XSPR(31,339, 63), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4868 {"mfcmpa",      XSPR(31,339,144), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4869 {"mfcmpb",      XSPR(31,339,145), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4870 {"mfcmpc",      XSPR(31,339,146), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4871 {"mfcmpd",      XSPR(31,339,147), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4872 {"mficr",       XSPR(31,339,148), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4873 {"mfder",       XSPR(31,339,149), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4874 {"mfcounta",    XSPR(31,339,150), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4875 {"mfcountb",    XSPR(31,339,151), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4876 {"mfcmpe",      XSPR(31,339,152), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4877 {"mfcmpf",      XSPR(31,339,153), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4878 {"mfcmpg",      XSPR(31,339,154), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4879 {"mfcmph",      XSPR(31,339,155), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4880 {"mflctrl1",    XSPR(31,339,156), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4881 {"mflctrl2",    XSPR(31,339,157), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4882 {"mfictrl",     XSPR(31,339,158), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4883 {"mfbar",       XSPR(31,339,159), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4884 {"mfvrsave",    XSPR(31,339,256), XSPR_MASK, PPCVEC,    PPCNONE,        {RT}},
4885 {"mfusprg0",    XSPR(31,339,256), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4886 {"mfsprg",      XSPR(31,339,256), XSPRG_MASK, PPC|PPCVLE, PPCNONE,      {RT, SPRG}},
4887 {"mfsprg4",     XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
4888 {"mfsprg5",     XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
4889 {"mfsprg6",     XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
4890 {"mfsprg7",     XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
4891 {"mftbu",       XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE|PPCVLE, PPCNONE, {RT}},
4892 {"mftb",        X(31,339),        X_MASK,    POWER4|BOOKE|PPCVLE, PPCNONE, {RT, TBR}},
4893 {"mftbl",       XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE|PPCVLE, PPCNONE, {RT}},
4894 {"mfsprg0",     XSPR(31,339,272), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RT}},
4895 {"mfsprg1",     XSPR(31,339,273), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RT}},
4896 {"mfsprg2",     XSPR(31,339,274), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RT}},
4897 {"mfsprg3",     XSPR(31,339,275), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RT}},
4898 {"mfasr",       XSPR(31,339,280), XSPR_MASK, PPC64,     PPCNONE,        {RT}},
4899 {"mfear",       XSPR(31,339,282), XSPR_MASK, PPC,       TITAN,          {RT}},
4900 {"mfpir",       XSPR(31,339,286), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4901 {"mfpvr",       XSPR(31,339,287), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RT}},
4902 {"mfdbsr",      XSPR(31,339,304), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4903 {"mfdbcr0",     XSPR(31,339,308), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4904 {"mfdbcr1",     XSPR(31,339,309), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4905 {"mfdbcr2",     XSPR(31,339,310), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4906 {"mfiac1",      XSPR(31,339,312), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4907 {"mfiac2",      XSPR(31,339,313), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4908 {"mfiac3",      XSPR(31,339,314), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4909 {"mfiac4",      XSPR(31,339,315), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4910 {"mfdac1",      XSPR(31,339,316), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4911 {"mfdac2",      XSPR(31,339,317), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4912 {"mfdvc1",      XSPR(31,339,318), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4913 {"mfdvc2",      XSPR(31,339,319), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4914 {"mftsr",       XSPR(31,339,336), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4915 {"mftcr",       XSPR(31,339,340), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4916 {"mfivor0",     XSPR(31,339,400), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4917 {"mfivor1",     XSPR(31,339,401), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4918 {"mfivor2",     XSPR(31,339,402), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4919 {"mfivor3",     XSPR(31,339,403), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4920 {"mfivor4",     XSPR(31,339,404), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4921 {"mfivor5",     XSPR(31,339,405), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4922 {"mfivor6",     XSPR(31,339,406), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4923 {"mfivor7",     XSPR(31,339,407), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4924 {"mfivor8",     XSPR(31,339,408), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4925 {"mfivor9",     XSPR(31,339,409), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4926 {"mfivor10",    XSPR(31,339,410), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4927 {"mfivor11",    XSPR(31,339,411), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4928 {"mfivor12",    XSPR(31,339,412), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4929 {"mfivor13",    XSPR(31,339,413), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4930 {"mfivor14",    XSPR(31,339,414), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4931 {"mfivor15",    XSPR(31,339,415), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4932 {"mfspefscr",   XSPR(31,339,512), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
4933 {"mfbbear",     XSPR(31,339,513), XSPR_MASK, PPCBRLK,   PPCNONE,        {RT}},
4934 {"mfbbtar",     XSPR(31,339,514), XSPR_MASK, PPCBRLK,   PPCNONE,        {RT}},
4935 {"mfivor32",    XSPR(31,339,528), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
4936 {"mfibatu",     XSPR(31,339,528), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
4937 {"mfivor33",    XSPR(31,339,529), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
4938 {"mfibatl",     XSPR(31,339,529), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
4939 {"mfivor34",    XSPR(31,339,530), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
4940 {"mfivor35",    XSPR(31,339,531), XSPR_MASK, PPCPMR,    PPCNONE,        {RT}},
4941 {"mfdbatu",     XSPR(31,339,536), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
4942 {"mfdbatl",     XSPR(31,339,537), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
4943 {"mfic_cst",    XSPR(31,339,560), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4944 {"mfic_adr",    XSPR(31,339,561), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4945 {"mfic_dat",    XSPR(31,339,562), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4946 {"mfdc_cst",    XSPR(31,339,568), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4947 {"mfdc_adr",    XSPR(31,339,569), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4948 {"mfdc_dat",    XSPR(31,339,570), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4949 {"mfmcsrr0",    XSPR(31,339,570), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RT}},
4950 {"mfmcsrr1",    XSPR(31,339,571), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RT}},
4951 {"mfmcsr",      XSPR(31,339,572), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RT}},
4952 {"mfmcar",      XSPR(31,339,573), XSPR_MASK, PPCRFMCI,  TITAN,          {RT}},
4953 {"mfdpdr",      XSPR(31,339,630), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4954 {"mfdpir",      XSPR(31,339,631), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4955 {"mfimmr",      XSPR(31,339,638), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4956 {"mfmi_ctr",    XSPR(31,339,784), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4957 {"mfmi_ap",     XSPR(31,339,786), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4958 {"mfmi_epn",    XSPR(31,339,787), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4959 {"mfmi_twc",    XSPR(31,339,789), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4960 {"mfmi_rpn",    XSPR(31,339,790), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4961 {"mfmd_ctr",    XSPR(31,339,792), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4962 {"mfm_casid",   XSPR(31,339,793), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4963 {"mfmd_ap",     XSPR(31,339,794), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4964 {"mfmd_epn",    XSPR(31,339,795), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4965 {"mfmd_twb",    XSPR(31,339,796), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4966 {"mfmd_twc",    XSPR(31,339,797), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4967 {"mfmd_rpn",    XSPR(31,339,798), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4968 {"mfm_tw",      XSPR(31,339,799), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4969 {"mfmi_dbcam",  XSPR(31,339,816), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4970 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4971 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4972 {"mfmd_dbcam",  XSPR(31,339,824), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4973 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4974 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4975 {"mfivndx",     XSPR(31,339,880), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4976 {"mfdvndx",     XSPR(31,339,881), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4977 {"mfivlim",     XSPR(31,339,882), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4978 {"mfdvlim",     XSPR(31,339,883), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4979 {"mfclcsr",     XSPR(31,339,884), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4980 {"mfccr1",      XSPR(31,339,888), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4981 {"mfppr",       XSPR(31,339,896), XSPR_MASK, POWER7,    PPCNONE,        {RT}},
4982 {"mfppr32",     XSPR(31,339,898), XSPR_MASK, POWER7,    PPCNONE,        {RT}},
4983 {"mfrstcfg",    XSPR(31,339,923), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4984 {"mfdcdbtrl",   XSPR(31,339,924), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4985 {"mfdcdbtrh",   XSPR(31,339,925), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4986 {"mficdbtr",    XSPR(31,339,927), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4987 {"mfummcr0",    XSPR(31,339,936), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4988 {"mfupmc1",     XSPR(31,339,937), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4989 {"mfupmc2",     XSPR(31,339,938), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4990 {"mfusia",      XSPR(31,339,939), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4991 {"mfummcr1",    XSPR(31,339,940), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4992 {"mfupmc3",     XSPR(31,339,941), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4993 {"mfupmc4",     XSPR(31,339,942), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4994 {"mfzpr",       XSPR(31,339,944), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4995 {"mfpid",       XSPR(31,339,945), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4996 {"mfmmucr",     XSPR(31,339,946), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4997 {"mfccr0",      XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, PPCNONE,     {RT}},
4998 {"mfiac3",      XSPR(31,339,948), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4999 {"mfiac4",      XSPR(31,339,949), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
5000 {"mfdvc1",      XSPR(31,339,950), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
5001 {"mfdvc2",      XSPR(31,339,951), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
5002 {"mfmmcr0",     XSPR(31,339,952), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
5003 {"mfpmc1",      XSPR(31,339,953), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
5004 {"mfsgr",       XSPR(31,339,953), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5005 {"mfdcwr",      XSPR(31,339,954), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5006 {"mfpmc2",      XSPR(31,339,954), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
5007 {"mfsia",       XSPR(31,339,955), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
5008 {"mfsler",      XSPR(31,339,955), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
5009 {"mfmmcr1",     XSPR(31,339,956), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
5010 {"mfsu0r",      XSPR(31,339,956), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
5011 {"mfdbcr1",     XSPR(31,339,957), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
5012 {"mfpmc3",      XSPR(31,339,957), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
5013 {"mfpmc4",      XSPR(31,339,958), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
5014 {"mficdbdr",    XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, PPCNONE,     {RT}},
5015 {"mfesr",       XSPR(31,339,980), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5016 {"mfdear",      XSPR(31,339,981), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5017 {"mfevpr",      XSPR(31,339,982), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5018 {"mfcdbcr",     XSPR(31,339,983), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5019 {"mftsr",       XSPR(31,339,984), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5020 {"mftcr",       XSPR(31,339,986), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5021 {"mfpit",       XSPR(31,339,987), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5022 {"mftbhi",      XSPR(31,339,988), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5023 {"mftblo",      XSPR(31,339,989), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5024 {"mfsrr2",      XSPR(31,339,990), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5025 {"mfsrr3",      XSPR(31,339,991), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
5026 {"mfdbsr",      XSPR(31,339,1008), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
5027 {"mfdbcr0",     XSPR(31,339,1010), XSPR_MASK, PPC405,   PPCNONE,        {RT}},
5028 {"mfdbdr",      XSPR(31,339,1011), XSPR_MASK, TITAN,    PPCNONE,        {RS}},
5029 {"mfiac1",      XSPR(31,339,1012), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
5030 {"mfiac2",      XSPR(31,339,1013), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
5031 {"mfdac1",      XSPR(31,339,1014), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
5032 {"mfdac2",      XSPR(31,339,1015), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
5033 {"mfl2cr",      XSPR(31,339,1017), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
5034 {"mfdccr",      XSPR(31,339,1018), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
5035 {"mficcr",      XSPR(31,339,1019), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
5036 {"mfictc",      XSPR(31,339,1019), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
5037 {"mfpbl1",      XSPR(31,339,1020), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
5038 {"mfthrm1",     XSPR(31,339,1020), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
5039 {"mfpbu1",      XSPR(31,339,1021), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
5040 {"mfthrm2",     XSPR(31,339,1021), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
5041 {"mfpbl2",      XSPR(31,339,1022), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
5042 {"mfthrm3",     XSPR(31,339,1022), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
5043 {"mfpbu2",      XSPR(31,339,1023), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
5044 {"mfspr",       X(31,339),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, SPR}},
5045
5046 {"lwax",        X(31,341),      X_MASK,      PPC64|PPCVLE, PPCNONE,     {RT, RA0, RB}},
5047
5048 {"dst",         XDSS(31,342,0), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
5049
5050 {"lhax",        X(31,343),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RA0, RB}},
5051
5052 {"lvxl",        X(31,359),      X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VD, RA0, RB}},
5053
5054 {"abs",         XO(31,360,0,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
5055 {"abs.",        XO(31,360,0,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
5056
5057 {"divs",        XO(31,363,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5058 {"divs.",       XO(31,363,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5059
5060 {"tlbia",       X(31,370),      0xffffffff,  PPC,       TITAN,          {0}},
5061
5062 {"mftbu",       XSPR(31,371,269), XSPR_MASK, PPC,       NO371|POWER4,   {RT}},
5063 {"mftb",        X(31,371),      X_MASK,      PPC,       NO371|POWER4,   {RT, TBR}},
5064 {"mftbl",       XSPR(31,371,268), XSPR_MASK, PPC,       NO371|POWER4,   {RT}},
5065
5066 {"lwaux",       X(31,373),      X_MASK,      PPC64|PPCVLE, PPCNONE,     {RT, RAL, RB}},
5067
5068 {"dstst",       XDSS(31,374,0), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
5069
5070 {"lhaux",       X(31,375),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RAL, RB}},
5071
5072 {"popcntw",     X(31,378),      XRB_MASK, POWER7|PPCA2, PPCNONE,        {RA, RS}},
5073
5074 {"mtdcrx",      X(31,387),      X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {RA, RS}},
5075 {"mtdcrx.",     XRC(31,387,1),  X_MASK,      PPCA2,     PPCNONE,        {RA, RS}},
5076
5077 {"stvexbx",     X(31,389),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5078
5079 {"dcblc",       X(31,390),      X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
5080 {"stdfcmx",     APU(31,391,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5081
5082 {"divdeu",      XO(31,393,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5083 {"divdeu.",     XO(31,393,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5084 {"divweu",      XO(31,395,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5085 {"divweu.",     XO(31,395,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5086
5087 {"dcblce",      X(31,398),      X_MASK,      PPCCHLK,   E500MC,         {CT, RA, RB}},
5088
5089 {"slbmte",      X(31,402),      XRA_MASK,    PPC64,     PPCNONE,        {RS, RB}},
5090
5091 {"pbt.",        XRC(31,404,1),  X_MASK,      POWER8,    PPCNONE,        {RS, RA0, RB}},
5092
5093 {"icswx",       XRC(31,406,0),  X_MASK,   POWER7|PPCA2, PPCNONE,        {RS, RA, RB}},
5094 {"icswx.",      XRC(31,406,1),  X_MASK,   POWER7|PPCA2, PPCNONE,        {RS, RA, RB}},
5095
5096 {"sthx",        X(31,407),      X_MASK,      COM|PPCVLE, PPCNONE,       {RS, RA0, RB}},
5097
5098 {"orc",         XRC(31,412,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
5099 {"orc.",        XRC(31,412,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
5100
5101 {"sthepx",      X(31,415),      X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
5102
5103 {"mtdcrux",     X(31,419),      X_MASK,      PPC464|PPCVLE, PPCNONE,    {RA, RS}},
5104
5105 {"stvexhx",     X(31,421),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5106
5107 {"dcblq.",      XRC(31,422,1),  X_MASK,      E6500,     PPCNONE,        {CT, RA0, RB}},
5108
5109 {"divde",       XO(31,425,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5110 {"divde.",      XO(31,425,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5111 {"divwe",       XO(31,427,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5112 {"divwe.",      XO(31,427,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5113
5114 {"clrbhrb",     X(31,430),      0xffffffff,  POWER8,    PPCNONE,        {0}},
5115
5116 {"slbie",       X(31,434),      XRTRA_MASK,  PPC64,     PPCNONE,        {RB}},
5117
5118 {"ecowx",       X(31,438),      X_MASK,      PPC,       TITAN,          {RT, RA0, RB}},
5119
5120 {"sthux",       X(31,439),      X_MASK,      COM|PPCVLE, PPCNONE,       {RS, RAS, RB}},
5121
5122 {"mdors",       0x7f9ce378,     0xffffffff,  E500MC,    PPCNONE,        {0}},
5123
5124 {"miso",        0x7f5ad378,     0xffffffff,  E6500,     PPCNONE,        {0}},
5125
5126 /* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for
5127    "or rX,rX,rX", with rX being r27, r29 and r30 respectively.  */
5128 {"yield",       0x7f7bdb78,     0xffffffff,  POWER7,     PPCNONE,       {0}},
5129 {"mdoio",       0x7fbdeb78,     0xffffffff,  POWER7,     PPCNONE,       {0}},
5130 {"mdoom",       0x7fdef378,     0xffffffff,  POWER7,     PPCNONE,       {0}},
5131 {"mr",          XRC(31,444,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RBS}},
5132 {"or",          XRC(31,444,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
5133 {"mr.",         XRC(31,444,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RBS}},
5134 {"or.",         XRC(31,444,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
5135
5136 {"mtexisr",     XSPR(31,451, 64), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5137 {"mtexier",     XSPR(31,451, 66), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5138 {"mtbr0",       XSPR(31,451,128), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5139 {"mtbr1",       XSPR(31,451,129), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5140 {"mtbr2",       XSPR(31,451,130), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5141 {"mtbr3",       XSPR(31,451,131), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5142 {"mtbr4",       XSPR(31,451,132), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5143 {"mtbr5",       XSPR(31,451,133), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5144 {"mtbr6",       XSPR(31,451,134), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5145 {"mtbr7",       XSPR(31,451,135), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5146 {"mtbear",      XSPR(31,451,144), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5147 {"mtbesr",      XSPR(31,451,145), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5148 {"mtiocr",      XSPR(31,451,160), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5149 {"mtdmacr0",    XSPR(31,451,192), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5150 {"mtdmact0",    XSPR(31,451,193), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5151 {"mtdmada0",    XSPR(31,451,194), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5152 {"mtdmasa0",    XSPR(31,451,195), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5153 {"mtdmacc0",    XSPR(31,451,196), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5154 {"mtdmacr1",    XSPR(31,451,200), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5155 {"mtdmact1",    XSPR(31,451,201), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5156 {"mtdmada1",    XSPR(31,451,202), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5157 {"mtdmasa1",    XSPR(31,451,203), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5158 {"mtdmacc1",    XSPR(31,451,204), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5159 {"mtdmacr2",    XSPR(31,451,208), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5160 {"mtdmact2",    XSPR(31,451,209), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5161 {"mtdmada2",    XSPR(31,451,210), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5162 {"mtdmasa2",    XSPR(31,451,211), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5163 {"mtdmacc2",    XSPR(31,451,212), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5164 {"mtdmacr3",    XSPR(31,451,216), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5165 {"mtdmact3",    XSPR(31,451,217), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5166 {"mtdmada3",    XSPR(31,451,218), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5167 {"mtdmasa3",    XSPR(31,451,219), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5168 {"mtdmacc3",    XSPR(31,451,220), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5169 {"mtdmasr",     XSPR(31,451,224), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5170 {"mtdcr",       X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {SPR, RS}},
5171 {"mtdcr.",      XRC(31,451,1), X_MASK,       PPCA2,     PPCNONE,        {SPR, RS}},
5172
5173 {"stvexwx",     X(31,453),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5174
5175 {"dccci",       X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
5176 {"dci",         X(31,454),      XRARB_MASK, PPCA2|PPC476|PPCVLE, PPCNONE, {CT}},
5177
5178 {"divdu",       XO(31,457,0,0), XO_MASK,  PPC64|PPCVLE, PPCNONE,        {RT, RA, RB}},
5179 {"divdu.",      XO(31,457,0,1), XO_MASK,  PPC64|PPCVLE, PPCNONE,        {RT, RA, RB}},
5180
5181 {"divwu",       XO(31,459,0,0), XO_MASK,  PPC|PPCVLE,   PPCNONE,        {RT, RA, RB}},
5182 {"divwu.",      XO(31,459,0,1), XO_MASK,  PPC|PPCVLE,   PPCNONE,        {RT, RA, RB}},
5183
5184 {"mtpmr",       X(31,462),      X_MASK, PPCPMR|PPCE300|PPCVLE, PPCNONE, {PMR, RS}},
5185 {"mttmr",       X(31,494),      X_MASK, PPCTMR|E6500,   PPCNONE,        {TMR, RS}},
5186
5187 {"mtmq",        XSPR(31,467,  0), XSPR_MASK, M601,      PPCNONE,        {RS}},
5188 {"mtxer",       XSPR(31,467,  1), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RS}},
5189 {"mtlr",        XSPR(31,467,  8), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RS}},
5190 {"mtctr",       XSPR(31,467,  9), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RS}},
5191 {"mttid",       XSPR(31,467, 17), XSPR_MASK, POWER,     PPCNONE,        {RS}},
5192 {"mtdsisr",     XSPR(31,467, 18), XSPR_MASK, COM,       TITAN,          {RS}},
5193 {"mtdar",       XSPR(31,467, 19), XSPR_MASK, COM,       TITAN,          {RS}},
5194 {"mtrtcu",      XSPR(31,467, 20), XSPR_MASK, COM,       TITAN,          {RS}},
5195 {"mtrtcl",      XSPR(31,467, 21), XSPR_MASK, COM,       TITAN,          {RS}},
5196 {"mtdec",       XSPR(31,467, 22), XSPR_MASK, COM,       PPCNONE,        {RS}},
5197 {"mtsdr0",      XSPR(31,467, 24), XSPR_MASK, POWER,     PPCNONE,        {RS}},
5198 {"mtsdr1",      XSPR(31,467, 25), XSPR_MASK, COM,       TITAN,          {RS}},
5199 {"mtsrr0",      XSPR(31,467, 26), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RS}},
5200 {"mtsrr1",      XSPR(31,467, 27), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RS}},
5201 {"mtcfar",      XSPR(31,467, 28), XSPR_MASK, POWER6,    PPCNONE,        {RS}},
5202 {"mtpid",       XSPR(31,467, 48), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5203 {"mtdecar",     XSPR(31,467, 54), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5204 {"mtcsrr0",     XSPR(31,467, 58), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5205 {"mtcsrr1",     XSPR(31,467, 59), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5206 {"mtdear",      XSPR(31,467, 61), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5207 {"mtesr",       XSPR(31,467, 62), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5208 {"mtivpr",      XSPR(31,467, 63), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5209 {"mtcmpa",      XSPR(31,467,144), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5210 {"mtcmpb",      XSPR(31,467,145), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5211 {"mtcmpc",      XSPR(31,467,146), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5212 {"mtcmpd",      XSPR(31,467,147), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5213 {"mticr",       XSPR(31,467,148), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5214 {"mtder",       XSPR(31,467,149), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5215 {"mtcounta",    XSPR(31,467,150), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5216 {"mtcountb",    XSPR(31,467,151), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5217 {"mtcmpe",      XSPR(31,467,152), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5218 {"mtcmpf",      XSPR(31,467,153), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5219 {"mtcmpg",      XSPR(31,467,154), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5220 {"mtcmph",      XSPR(31,467,155), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5221 {"mtlctrl1",    XSPR(31,467,156), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5222 {"mtlctrl2",    XSPR(31,467,157), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5223 {"mtictrl",     XSPR(31,467,158), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5224 {"mtbar",       XSPR(31,467,159), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5225 {"mtvrsave",    XSPR(31,467,256), XSPR_MASK, PPCVEC,    PPCNONE,        {RS}},
5226 {"mtusprg0",    XSPR(31,467,256), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5227 {"mtsprg",      XSPR(31,467,256), XSPRG_MASK, PPC|PPCVLE, PPCNONE,      {SPRG, RS}},
5228 {"mtsprg0",     XSPR(31,467,272), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RS}},
5229 {"mtsprg1",     XSPR(31,467,273), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RS}},
5230 {"mtsprg2",     XSPR(31,467,274), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RS}},
5231 {"mtsprg3",     XSPR(31,467,275), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RS}},
5232 {"mtsprg4",     XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
5233 {"mtsprg5",     XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
5234 {"mtsprg6",     XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
5235 {"mtsprg7",     XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
5236 {"mtasr",       XSPR(31,467,280), XSPR_MASK, PPC64,     PPCNONE,        {RS}},
5237 {"mtear",       XSPR(31,467,282), XSPR_MASK, PPC,       TITAN,          {RS}},
5238 {"mttbl",       XSPR(31,467,284), XSPR_MASK, PPC,       PPCNONE,        {RS}},
5239 {"mttbu",       XSPR(31,467,285), XSPR_MASK, PPC,       PPCNONE,        {RS}},
5240 {"mtdbsr",      XSPR(31,467,304), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5241 {"mtdbcr0",     XSPR(31,467,308), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5242 {"mtdbcr1",     XSPR(31,467,309), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5243 {"mtdbcr2",     XSPR(31,467,310), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5244 {"mtiac1",      XSPR(31,467,312), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5245 {"mtiac2",      XSPR(31,467,313), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5246 {"mtiac3",      XSPR(31,467,314), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5247 {"mtiac4",      XSPR(31,467,315), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5248 {"mtdac1",      XSPR(31,467,316), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5249 {"mtdac2",      XSPR(31,467,317), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5250 {"mtdvc1",      XSPR(31,467,318), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5251 {"mtdvc2",      XSPR(31,467,319), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5252 {"mttsr",       XSPR(31,467,336), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5253 {"mttcr",       XSPR(31,467,340), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5254 {"mtivor0",     XSPR(31,467,400), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5255 {"mtivor1",     XSPR(31,467,401), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5256 {"mtivor2",     XSPR(31,467,402), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5257 {"mtivor3",     XSPR(31,467,403), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5258 {"mtivor4",     XSPR(31,467,404), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5259 {"mtivor5",     XSPR(31,467,405), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5260 {"mtivor6",     XSPR(31,467,406), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5261 {"mtivor7",     XSPR(31,467,407), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5262 {"mtivor8",     XSPR(31,467,408), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5263 {"mtivor9",     XSPR(31,467,409), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5264 {"mtivor10",    XSPR(31,467,410), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5265 {"mtivor11",    XSPR(31,467,411), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5266 {"mtivor12",    XSPR(31,467,412), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5267 {"mtivor13",    XSPR(31,467,413), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5268 {"mtivor14",    XSPR(31,467,414), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5269 {"mtivor15",    XSPR(31,467,415), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5270 {"mtspefscr",   XSPR(31,467,512), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
5271 {"mtbbear",     XSPR(31,467,513), XSPR_MASK, PPCBRLK,   PPCNONE,        {RS}},
5272 {"mtbbtar",     XSPR(31,467,514), XSPR_MASK, PPCBRLK,   PPCNONE,        {RS}},
5273 {"mtivor32",    XSPR(31,467,528), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
5274 {"mtibatu",     XSPR(31,467,528), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
5275 {"mtivor33",    XSPR(31,467,529), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
5276 {"mtibatl",     XSPR(31,467,529), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
5277 {"mtivor34",    XSPR(31,467,530), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
5278 {"mtivor35",    XSPR(31,467,531), XSPR_MASK, PPCPMR,    PPCNONE,        {RS}},
5279 {"mtdbatu",     XSPR(31,467,536), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
5280 {"mtdbatl",     XSPR(31,467,537), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
5281 {"mtmcsrr0",    XSPR(31,467,570), XSPR_MASK, PPCRFMCI|PPCVLE, PPCNONE,  {RS}},
5282 {"mtmcsrr1",    XSPR(31,467,571), XSPR_MASK, PPCRFMCI|PPCVLE, PPCNONE,  {RS}},
5283 {"mtmcsr",      XSPR(31,467,572), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RS}},
5284 {"mtivndx",     XSPR(31,467,880), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
5285 {"mtdvndx",     XSPR(31,467,881), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
5286 {"mtivlim",     XSPR(31,467,882), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
5287 {"mtdvlim",     XSPR(31,467,883), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
5288 {"mtclcsr",     XSPR(31,467,884), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
5289 {"mtccr1",      XSPR(31,467,888), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
5290 {"mtppr",       XSPR(31,467,896), XSPR_MASK, POWER7,    PPCNONE,        {RS}},
5291 {"mtppr32",     XSPR(31,467,898), XSPR_MASK, POWER7,    PPCNONE,        {RS}},
5292 {"mtummcr0",    XSPR(31,467,936), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5293 {"mtupmc1",     XSPR(31,467,937), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5294 {"mtupmc2",     XSPR(31,467,938), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5295 {"mtusia",      XSPR(31,467,939), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5296 {"mtummcr1",    XSPR(31,467,940), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5297 {"mtupmc3",     XSPR(31,467,941), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5298 {"mtupmc4",     XSPR(31,467,942), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5299 {"mtzpr",       XSPR(31,467,944), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5300 {"mtpid",       XSPR(31,467,945), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5301 {"mtrmmucr",    XSPR(31,467,946), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
5302 {"mtccr0",      XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, PPCNONE,     {RS}},
5303 {"mtiac3",      XSPR(31,467,948), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
5304 {"mtiac4",      XSPR(31,467,949), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
5305 {"mtdvc1",      XSPR(31,467,950), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
5306 {"mtdvc2",      XSPR(31,467,951), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
5307 {"mtmmcr0",     XSPR(31,467,952), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5308 {"mtpmc1",      XSPR(31,467,953), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5309 {"mtsgr",       XSPR(31,467,953), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5310 {"mtdcwr",      XSPR(31,467,954), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5311 {"mtpmc2",      XSPR(31,467,954), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5312 {"mtsia",       XSPR(31,467,955), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5313 {"mtsler",      XSPR(31,467,955), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
5314 {"mtmmcr1",     XSPR(31,467,956), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5315 {"mtsu0r",      XSPR(31,467,956), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
5316 {"mtdbcr1",     XSPR(31,467,957), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
5317 {"mtpmc3",      XSPR(31,467,957), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5318 {"mtpmc4",      XSPR(31,467,958), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5319 {"mticdbdr",    XSPR(31,467,979), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5320 {"mtesr",       XSPR(31,467,980), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5321 {"mtdear",      XSPR(31,467,981), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5322 {"mtevpr",      XSPR(31,467,982), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5323 {"mtcdbcr",     XSPR(31,467,983), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5324 {"mttsr",       XSPR(31,467,984), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5325 {"mttcr",       XSPR(31,467,986), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5326 {"mtpit",       XSPR(31,467,987), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5327 {"mttbhi",      XSPR(31,467,988), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5328 {"mttblo",      XSPR(31,467,989), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5329 {"mtsrr2",      XSPR(31,467,990), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5330 {"mtsrr3",      XSPR(31,467,991), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5331 {"mtdbsr",      XSPR(31,467,1008), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5332 {"mtdbdr",      XSPR(31,467,1011), XSPR_MASK, TITAN,    PPCNONE,        {RS}},
5333 {"mtdbcr0",     XSPR(31,467,1010), XSPR_MASK, PPC405,   PPCNONE,        {RS}},
5334 {"mtiac1",      XSPR(31,467,1012), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5335 {"mtiac2",      XSPR(31,467,1013), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5336 {"mtdac1",      XSPR(31,467,1014), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5337 {"mtdac2",      XSPR(31,467,1015), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5338 {"mtl2cr",      XSPR(31,467,1017), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
5339 {"mtdccr",      XSPR(31,467,1018), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5340 {"mticcr",      XSPR(31,467,1019), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5341 {"mtictc",      XSPR(31,467,1019), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
5342 {"mtpbl1",      XSPR(31,467,1020), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5343 {"mtthrm1",     XSPR(31,467,1020), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
5344 {"mtpbu1",      XSPR(31,467,1021), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5345 {"mtthrm2",     XSPR(31,467,1021), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
5346 {"mtpbl2",      XSPR(31,467,1022), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5347 {"mtthrm3",     XSPR(31,467,1022), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
5348 {"mtpbu2",      XSPR(31,467,1023), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5349 {"mtspr",       X(31,467),      X_MASK,      COM|PPCVLE, PPCNONE,       {SPR, RS}},
5350
5351 {"dcbi",        X(31,470),      XRT_MASK,    PPC|PPCVLE, PPCNONE,       {RA0, RB}},
5352
5353 {"nand",        XRC(31,476,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
5354 {"nand.",       XRC(31,476,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
5355
5356 {"dsn",         X(31,483),      XRT_MASK,    E500MC|PPCVLE, PPCNONE,    {RA, RB}},
5357
5358 {"dcread",      X(31,486),      X_MASK,  PPC403|PPC440|PPCVLE, PPCA2|PPC476, {RT, RA0, RB}},
5359
5360 {"icbtls",      X(31,486),      X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
5361
5362 {"stvxl",       X(31,487),      X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VS, RA0, RB}},
5363
5364 {"nabs",        XO(31,488,0,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
5365 {"nabs.",       XO(31,488,0,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
5366
5367 {"divd",        XO(31,489,0,0), XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
5368 {"divd.",       XO(31,489,0,1), XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
5369
5370 {"divw",        XO(31,491,0,0), XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
5371 {"divw.",       XO(31,491,0,1), XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
5372
5373 {"icbtlse",     X(31,494),      X_MASK,      PPCCHLK,   E500MC,         {CT, RA, RB}},
5374
5375 {"slbia",       X(31,498),      0xff1fffff,  POWER6,    PPCNONE,        {IH}},
5376 {"slbia",       X(31,498),      0xffffffff,  PPC64,     POWER6,         {0}},
5377
5378 {"cli",         X(31,502),      XRB_MASK,    POWER,     PPCNONE,        {RT, RA}},
5379
5380 {"popcntd",     X(31,506),      XRB_MASK, POWER7|PPCA2, PPCNONE,        {RA, RS}},
5381
5382 {"cmpb",        X(31,508),      X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {RA, RS, RB}},
5383
5384 {"mcrxr",       X(31,512), XRARB_MASK|(3<<21), COM|PPCVLE, POWER7,      {BF}},
5385
5386 {"lbdx",        X(31,515),      X_MASK,      E500MC|PPCVLE, PPCNONE,    {RT, RA, RB}},
5387
5388 {"bblels",      X(31,518),      X_MASK,      PPCBRLK,   PPCNONE,        {0}},
5389
5390 {"lvlx",        X(31,519),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
5391 {"lbfcmux",     APU(31,519,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5392
5393 {"subfco",      XO(31,8,1,0),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
5394 {"sfo",         XO(31,8,1,0),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5395 {"subco",       XO(31,8,1,0),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RB, RA}},
5396 {"subfco.",     XO(31,8,1,1),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
5397 {"sfo.",        XO(31,8,1,1),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5398 {"subco.",      XO(31,8,1,1),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RB, RA}},
5399
5400 {"addco",       XO(31,10,1,0),  XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
5401 {"ao",          XO(31,10,1,0),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5402 {"addco.",      XO(31,10,1,1),  XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
5403 {"ao.",         XO(31,10,1,1),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5404
5405 {"lxsspx",      X(31,524),      XX1_MASK,    PPCVSX2,   PPCNONE,        {XT6, RA0, RB}},
5406
5407 {"clcs",        X(31,531),      XRB_MASK,    M601,      PPCNONE,        {RT, RA}},
5408
5409 {"ldbrx",       X(31,532),      X_MASK, CELL|POWER7|PPCA2, PPCNONE,     {RT, RA0, RB}},
5410
5411 {"lswx",        X(31,533),      X_MASK,  PPCCOM|PPCVLE, E500|E500MC,    {RT, RAX, RBX}},
5412 {"lsx",         X(31,533),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
5413
5414 {"lwbrx",       X(31,534),      X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RT, RA0, RB}},
5415 {"lbrx",        X(31,534),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
5416
5417 {"lfsx",        X(31,535),      X_MASK,      COM,       PPCEFS,         {FRT, RA0, RB}},
5418
5419 {"srw",         XRC(31,536,0),  X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RA, RS, RB}},
5420 {"sr",          XRC(31,536,0),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
5421 {"srw.",        XRC(31,536,1),  X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RA, RS, RB}},
5422 {"sr.",         XRC(31,536,1),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
5423
5424 {"rrib",        XRC(31,537,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5425 {"rrib.",       XRC(31,537,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5426
5427 {"srd",         XRC(31,539,0),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
5428 {"srd.",        XRC(31,539,1),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
5429
5430 {"maskir",      XRC(31,541,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5431 {"maskir.",     XRC(31,541,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5432
5433 {"lhdx",        X(31,547),      X_MASK,      E500MC|PPCVLE, PPCNONE,    {RT, RA, RB}},
5434
5435 {"lvtrx",       X(31,549),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
5436
5437 {"bbelr",       X(31,550),      X_MASK,      PPCBRLK,   PPCNONE,        {0}},
5438
5439 {"lvrx",        X(31,551),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
5440 {"lhfcmux",     APU(31,551,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5441
5442 {"subfo",       XO(31,40,1,0),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
5443 {"subo",        XO(31,40,1,0),  XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
5444 {"subfo.",      XO(31,40,1,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
5445 {"subo.",       XO(31,40,1,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
5446
5447 {"tlbsync",     X(31,566),      0xffffffff, PPC|PPCVLE, PPCNONE,        {0}},
5448
5449 {"lfsux",       X(31,567),      X_MASK,      COM,       PPCEFS,         {FRT, RAS, RB}},
5450
5451 {"lwdx",        X(31,579),      X_MASK,      E500MC|PPCVLE, PPCNONE,    {RT, RA, RB}},
5452
5453 {"lvtlx",       X(31,581),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
5454
5455 {"lwfcmux",     APU(31,583,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5456
5457 {"lxsdx",       X(31,588),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA0, RB}},
5458
5459 {"mfsr",        X(31,595), XRB_MASK|(1<<20), COM,       NON32,          {RT, SR}},
5460
5461 {"lswi",        X(31,597),      X_MASK,  PPCCOM|PPCVLE, E500|E500MC,    {RT, RAX, NBI}},
5462 {"lsi",         X(31,597),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA0, NB}},
5463
5464 {"hwsync",      XSYNC(31,598,0), 0xffffffff, POWER4,    BOOKE|PPC476,   {0}},
5465 {"lwsync",      XSYNC(31,598,1), 0xffffffff, PPC,       E500,           {0}},
5466 {"ptesync",     XSYNC(31,598,2), 0xffffffff, PPC64,     PPCNONE,        {0}},
5467 {"sync",        X(31,598),      XSYNCLE_MASK,E6500,     PPCNONE,        {LS, ESYNC}},
5468 {"sync",        X(31,598),      XSYNC_MASK, PPCCOM|PPCVLE, BOOKE|PPC476, {LS}},
5469 {"msync",       X(31,598),      0xffffffff, BOOKE|PPCA2|PPC476, PPCNONE, {0}},
5470 {"sync",        X(31,598),      0xffffffff, BOOKE|PPC476, E6500,        {0}},
5471 {"lwsync",      X(31,598),      0xffffffff, E500,       PPCNONE,        {0}},
5472 {"dcs",         X(31,598),      0xffffffff,  PWRCOM,    PPCNONE,        {0}},
5473
5474 {"lfdx",        X(31,599),      X_MASK,      COM,       PPCEFS,         {FRT, RA0, RB}},
5475
5476 {"mffgpr",      XRC(31,607,0),  XRA_MASK,    POWER6,    POWER7,         {FRT, RB}},
5477 {"lfdepx",      X(31,607),      X_MASK,   E500MC|PPCA2|PPCVLE, PPCNONE, {FRT, RA0, RB}},
5478
5479 {"lddx",        X(31,611),      X_MASK,      E500MC|PPCVLE, PPCNONE,    {RT, RA, RB}},
5480
5481 {"lvswx",       X(31,613),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
5482
5483 {"lqfcmux",     APU(31,615,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5484
5485 {"nego",        XO(31,104,1,0), XORB_MASK,   COM|PPCVLE, PPCNONE,       {RT, RA}},
5486 {"nego.",       XO(31,104,1,1), XORB_MASK,   COM|PPCVLE, PPCNONE,       {RT, RA}},
5487
5488 {"mulo",        XO(31,107,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5489 {"mulo.",       XO(31,107,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5490
5491 {"mfsri",       X(31,627),      X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
5492
5493 {"dclst",       X(31,630),      XRB_MASK,    M601,      PPCNONE,        {RS, RA}},
5494
5495 {"lfdux",       X(31,631),      X_MASK,      COM,       PPCEFS,         {FRT, RAS, RB}},
5496
5497 {"stbdx",       X(31,643),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
5498
5499 {"stvlx",       X(31,647),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
5500 {"stbfcmux",    APU(31,647,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5501
5502 {"stxsspx",     X(31,652),      XX1_MASK,    PPCVSX2,   PPCNONE,        {XS6, RA0, RB}},
5503
5504 {"tbegin.",     XRC(31,654,1), XRTLRARB_MASK,PPCHTM,    PPCNONE,        {HTM_R}},
5505
5506 {"subfeo",      XO(31,136,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE,        {RT, RA, RB}},
5507 {"sfeo",        XO(31,136,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5508 {"subfeo.",     XO(31,136,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE,        {RT, RA, RB}},
5509 {"sfeo.",       XO(31,136,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5510
5511 {"addeo",       XO(31,138,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE,        {RT, RA, RB}},
5512 {"aeo",         XO(31,138,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5513 {"addeo.",      XO(31,138,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE,        {RT, RA, RB}},
5514 {"aeo.",        XO(31,138,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5515
5516 {"mfsrin",      X(31,659),      XRA_MASK,    PPC,       NON32,          {RT, RB}},
5517
5518 {"stdbrx",      X(31,660),      X_MASK, CELL|POWER7|PPCA2, PPCNONE,     {RS, RA0, RB}},
5519
5520 {"stswx",       X(31,661),      X_MASK, PPCCOM|PPCVLE,  E500|E500MC,    {RS, RA0, RB}},
5521 {"stsx",        X(31,661),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, RB}},
5522
5523 {"stwbrx",      X(31,662),      X_MASK, PPCCOM|PPCVLE,  PPCNONE,        {RS, RA0, RB}},
5524 {"stbrx",       X(31,662),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, RB}},
5525
5526 {"stfsx",       X(31,663),      X_MASK,      COM,       PPCEFS,         {FRS, RA0, RB}},
5527
5528 {"srq",         XRC(31,664,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5529 {"srq.",        XRC(31,664,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5530
5531 {"sre",         XRC(31,665,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5532 {"sre.",        XRC(31,665,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5533
5534 {"sthdx",       X(31,675),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
5535
5536 {"stvfrx",      X(31,677),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5537
5538 {"stvrx",       X(31,679),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
5539 {"sthfcmux",    APU(31,679,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5540
5541 {"tendall.",    XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, PPCNONE,   {0}},
5542 {"tend.",       XRC(31,686,1), XRTARARB_MASK, PPCHTM,   PPCNONE,        {HTM_A}},
5543
5544 {"stbcx.",      XRC(31,694,1),  X_MASK,      POWER8,    PPCNONE,        {RS, RA0, RB}},
5545
5546 {"stfsux",      X(31,695),      X_MASK,      COM,       PPCEFS,         {FRS, RAS, RB}},
5547
5548 {"sriq",        XRC(31,696,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
5549 {"sriq.",       XRC(31,696,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
5550
5551 {"stwdx",       X(31,707),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
5552
5553 {"stvflx",      X(31,709),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5554
5555 {"stwfcmux",    APU(31,711,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5556
5557 {"stxsdx",      X(31,716),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA0, RB}},
5558
5559 {"tcheck",      X(31,718),   XRTBFRARB_MASK, PPCHTM,    PPCNONE,        {BF}},
5560
5561 {"subfzeo",     XO(31,200,1,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE,      {RT, RA}},
5562 {"sfzeo",       XO(31,200,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5563 {"subfzeo.",    XO(31,200,1,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE,      {RT, RA}},
5564 {"sfzeo.",      XO(31,200,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5565
5566 {"addzeo",      XO(31,202,1,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE,      {RT, RA}},
5567 {"azeo",        XO(31,202,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5568 {"addzeo.",     XO(31,202,1,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE,      {RT, RA}},
5569 {"azeo.",       XO(31,202,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5570
5571 {"stswi",       X(31,725),      X_MASK, PPCCOM|PPCVLE,  E500|E500MC,    {RS, RA0, NB}},
5572 {"stsi",        X(31,725),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, NB}},
5573
5574 {"sthcx.",      XRC(31,726,1),  X_MASK,      POWER8,    PPCNONE,        {RS, RA0, RB}},
5575
5576 {"stfdx",       X(31,727),      X_MASK,      COM,       PPCEFS,         {FRS, RA0, RB}},
5577
5578 {"srlq",        XRC(31,728,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5579 {"srlq.",       XRC(31,728,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5580
5581 {"sreq",        XRC(31,729,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5582 {"sreq.",       XRC(31,729,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5583
5584 {"mftgpr",      XRC(31,735,0),  XRA_MASK,    POWER6,    POWER7,         {RT, FRB}},
5585 {"stfdepx",     X(31,735),      X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE,   {FRS, RA0, RB}},
5586
5587 {"stddx",       X(31,739),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
5588
5589 {"stvswx",      X(31,741),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5590
5591 {"stqfcmux",    APU(31,743,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5592
5593 {"subfmeo",     XO(31,232,1,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
5594 {"sfmeo",       XO(31,232,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5595 {"subfmeo.",    XO(31,232,1,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
5596 {"sfmeo.",      XO(31,232,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5597
5598 {"mulldo",      XO(31,233,1,0), XO_MASK,  PPC64|PPCVLE, PPCNONE,        {RT, RA, RB}},
5599 {"mulldo.",     XO(31,233,1,1), XO_MASK,  PPC64|PPCVLE, PPCNONE,        {RT, RA, RB}},
5600
5601 {"addmeo",      XO(31,234,1,0), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
5602 {"ameo",        XO(31,234,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5603 {"addmeo.",     XO(31,234,1,1), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
5604 {"ameo.",       XO(31,234,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5605
5606 {"mullwo",      XO(31,235,1,0), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
5607 {"mulso",       XO(31,235,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5608 {"mullwo.",     XO(31,235,1,1), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
5609 {"mulso.",      XO(31,235,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5610
5611 {"tsuspend.",   XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM,  PPCNONE,        {0}},
5612 {"tresume.",    XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM,  PPCNONE,        {0}},
5613 {"tsr.",        XRC(31,750,1),    XRTLRARB_MASK,PPCHTM, PPCNONE,        {L}},
5614
5615 {"dcba",        X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RA0, RB}},
5616 {"dcbal",       XOPL(31,758,1), XRT_MASK,    E500MC,    PPCNONE,        {RA0, RB}},
5617
5618 {"stfdux",      X(31,759),      X_MASK,      COM,       PPCEFS,         {FRS, RAS, RB}},
5619
5620 {"srliq",       XRC(31,760,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
5621 {"srliq.",      XRC(31,760,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
5622
5623 {"lvsm",        X(31,773),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
5624 {"stvepxl",     X(31,775),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5625 {"lvlxl",       X(31,775),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
5626 {"ldfcmux",     APU(31,775,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5627
5628 {"dozo",        XO(31,264,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5629 {"dozo.",       XO(31,264,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5630
5631 {"addo",        XO(31,266,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE,        {RT, RA, RB}},
5632 {"caxo",        XO(31,266,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5633 {"addo.",       XO(31,266,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE,        {RT, RA, RB}},
5634 {"caxo.",       XO(31,266,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5635
5636 {"lxvw4x",      X(31,780),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA0, RB}},
5637
5638 {"tabortwc.",   XRC(31,782,1),  X_MASK,      PPCHTM,    PPCNONE,        {TO, RA, RB}},
5639
5640 {"tlbivax",     X(31,786),      XRT_MASK, BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RA0, RB}},
5641
5642 {"lwzcix",      X(31,789),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
5643
5644 {"lhbrx",       X(31,790),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RA0, RB}},
5645
5646 {"lfdpx",       X(31,791),      X_MASK,      POWER6,    POWER7,         {FRTp, RA0, RB}},
5647 {"lfqx",        X(31,791),      X_MASK,      POWER2,    PPCNONE,        {FRT, RA, RB}},
5648
5649 {"sraw",        XRC(31,792,0),  X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RA, RS, RB}},
5650 {"sra",         XRC(31,792,0),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
5651 {"sraw.",       XRC(31,792,1),  X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RA, RS, RB}},
5652 {"sra.",        XRC(31,792,1),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
5653
5654 {"srad",        XRC(31,794,0),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
5655 {"srad.",       XRC(31,794,1),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
5656
5657 {"lfddx",       X(31,803),      X_MASK,      E500MC|PPCVLE, PPCNONE,    {FRT, RA, RB}},
5658
5659 {"lvtrxl",      X(31,805),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
5660 {"stvepx",      X(31,807),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5661 {"lvrxl",       X(31,807),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
5662
5663 {"tabortdc.",   XRC(31,814,1),  X_MASK,      PPCHTM,    PPCNONE,        {TO, RA, RB}},
5664
5665 {"rac",         X(31,818),      X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
5666
5667 {"erativax",    X(31,819),      X_MASK,      PPCA2,     PPCNONE,        {RS, RA0, RB}},
5668
5669 {"lhzcix",      X(31,821),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
5670
5671 {"dss",         XDSS(31,822,0), XDSS_MASK,   PPCVEC,    PPCNONE,        {STRM}},
5672
5673 {"lfqux",       X(31,823),      X_MASK,      POWER2,    PPCNONE,        {FRT, RA, RB}},
5674
5675 {"srawi",       XRC(31,824,0),  X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RA, RS, SH}},
5676 {"srai",        XRC(31,824,0),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH}},
5677 {"srawi.",      XRC(31,824,1),  X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RA, RS, SH}},
5678 {"srai.",       XRC(31,824,1),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH}},
5679
5680 {"sradi",       XS(31,413,0),   XS_MASK,     PPC64|PPCVLE, PPCNONE,     {RA, RS, SH6}},
5681 {"sradi.",      XS(31,413,1),   XS_MASK,     PPC64|PPCVLE, PPCNONE,     {RA, RS, SH6}},
5682
5683 {"lvtlxl",      X(31,837),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
5684
5685 {"divo",        XO(31,331,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5686 {"divo.",       XO(31,331,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5687
5688 {"lxvd2x",      X(31,844),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA0, RB}},
5689 {"lxvx",        X(31,844),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA0, RB}},
5690
5691 {"tabortwci.",  XRC(31,846,1),  X_MASK,      PPCHTM,    PPCNONE,        {TO, RA, HTM_SI}},
5692
5693 {"tlbsrx.",     XRC(31,850,1),  XRT_MASK,    PPCA2,     PPCNONE,        {RA0, RB}},
5694
5695 {"slbmfev",     X(31,851),      XRA_MASK,    PPC64,     PPCNONE,        {RT, RB}},
5696
5697 {"lbzcix",      X(31,853),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
5698
5699 {"eieio",       X(31,854),      0xffffffff,  PPC,   BOOKE|PPCA2|PPC476, {0}},
5700 {"mbar",        X(31,854),      X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {MO}},
5701 {"eieio",       XMBAR(31,854,1),0xffffffff,  E500,      PPCNONE,        {0}},
5702 {"eieio",       X(31,854),      0xffffffff, PPCA2|PPC476, PPCNONE,      {0}},
5703
5704 {"lfiwax",      X(31,855),      X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, RA0, RB}},
5705
5706 {"lvswxl",      X(31,869),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
5707
5708 {"abso",        XO(31,360,1,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
5709 {"abso.",       XO(31,360,1,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
5710
5711 {"divso",       XO(31,363,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5712 {"divso.",      XO(31,363,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5713
5714 {"tabortdci.",  XRC(31,878,1),  X_MASK,      PPCHTM,    PPCNONE,        {TO, RA, HTM_SI}},
5715
5716 {"ldcix",       X(31,885),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
5717
5718 {"lfiwzx",      X(31,887),      X_MASK,   POWER7|PPCA2, PPCNONE,        {FRT, RA0, RB}},
5719
5720 {"stvlxl",      X(31,903),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
5721 {"stdfcmux",    APU(31,903,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5722
5723 {"divdeuo",     XO(31,393,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5724 {"divdeuo.",    XO(31,393,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5725 {"divweuo",     XO(31,395,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5726 {"divweuo.",    XO(31,395,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5727
5728 {"stxvw4x",     X(31,908),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA0, RB}},
5729
5730 {"tabort.",     XRC(31,910,1),  XRTRB_MASK,  PPCHTM,    PPCNONE,        {RA}},
5731
5732 {"tlbsx",       XRC(31,914,0),  X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA0, RB}},
5733 {"tlbsx.",      XRC(31,914,1),  X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA0, RB}},
5734
5735 {"slbmfee",     X(31,915),      XRA_MASK,    PPC64,     PPCNONE,        {RT, RB}},
5736
5737 {"stwcix",      X(31,917),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
5738
5739 {"sthbrx",      X(31,918),      X_MASK,      COM,       PPCNONE,        {RS, RA0, RB}},
5740
5741 {"stfdpx",      X(31,919),      X_MASK,      POWER6,    POWER7,         {FRSp, RA0, RB}},
5742 {"stfqx",       X(31,919),      X_MASK,      POWER2,    PPCNONE,        {FRS, RA0, RB}},
5743
5744 {"sraq",        XRC(31,920,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5745 {"sraq.",       XRC(31,920,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5746
5747 {"srea",        XRC(31,921,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5748 {"srea.",       XRC(31,921,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5749
5750 {"extsh",       XRC(31,922,0),  XRB_MASK,    PPCCOM|PPCVLE, PPCNONE,    {RA, RS}},
5751 {"exts",        XRC(31,922,0),  XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
5752 {"extsh.",      XRC(31,922,1),  XRB_MASK,    PPCCOM|PPCVLE, PPCNONE,    {RA, RS}},
5753 {"exts.",       XRC(31,922,1),  XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
5754
5755 {"stfddx",      X(31,931),      X_MASK,      E500MC,    PPCNONE,        {FRS, RA, RB}},
5756
5757 {"stvfrxl",     X(31,933),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5758
5759 {"wclrone",     XOPL2(31,934,2),XRT_MASK,    PPCA2,     PPCNONE,        {RA0, RB}},
5760 {"wclrall",     X(31,934),      XRARB_MASK,  PPCA2,     PPCNONE,        {L}},
5761 {"wclr",        X(31,934),      X_MASK,      PPCA2,     PPCNONE,        {L, RA0, RB}},
5762
5763 {"stvrxl",      X(31,935),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
5764
5765 {"divdeo",      XO(31,425,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5766 {"divdeo.",     XO(31,425,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5767 {"divweo",      XO(31,427,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5768 {"divweo.",     XO(31,427,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5769
5770 {"treclaim.",   XRC(31,942,1),  XRTRB_MASK,  PPCHTM,    PPCNONE,        {RA}},
5771
5772 {"tlbrehi",     XTLB(31,946,0), XTLB_MASK,   PPC403,    PPCA2,          {RT, RA}},
5773 {"tlbrelo",     XTLB(31,946,1), XTLB_MASK,   PPC403,    PPCA2,          {RT, RA}},
5774 {"tlbre",       X(31,946),      X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
5775
5776 {"sthcix",      X(31,949),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
5777
5778 {"icswepx",     XRC(31,950,0),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA, RB}},
5779 {"icswepx.",    XRC(31,950,1),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA, RB}},
5780
5781 {"stfqux",      X(31,951),      X_MASK,      POWER2,    PPCNONE,        {FRS, RA, RB}},
5782
5783 {"sraiq",       XRC(31,952,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
5784 {"sraiq.",      XRC(31,952,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
5785
5786 {"extsb",       XRC(31,954,0),  XRB_MASK, PPC|PPCVLE,   PPCNONE,        {RA, RS}},
5787 {"extsb.",      XRC(31,954,1),  XRB_MASK, PPC|PPCVLE,   PPCNONE,        {RA, RS}},
5788
5789 {"stvflxl",     X(31,965),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5790
5791 {"iccci",       X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
5792 {"ici",         X(31,966),      XRARB_MASK,  PPCA2|PPC476|PPCVLE, PPCNONE, {CT}},
5793
5794 {"divduo",      XO(31,457,1,0), XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
5795 {"divduo.",     XO(31,457,1,1), XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
5796
5797 {"divwuo",      XO(31,459,1,0), XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
5798 {"divwuo.",     XO(31,459,1,1), XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
5799
5800 {"stxvd2x",     X(31,972),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA0, RB}},
5801 {"stxvx",       X(31,972),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA0, RB}},
5802
5803 {"tlbld",       X(31,978),      XRTRA_MASK,  PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
5804 {"tlbwehi",     XTLB(31,978,0), XTLB_MASK,   PPC403,    PPCNONE,        {RT, RA}},
5805 {"tlbwelo",     XTLB(31,978,1), XTLB_MASK,   PPC403,    PPCNONE,        {RT, RA}},
5806 {"tlbwe",       X(31,978),      X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
5807
5808 {"slbfee.",     XRC(31,979,1),  XRA_MASK,    POWER6,    PPCNONE,        {RT, RB}},
5809
5810 {"stbcix",      X(31,981),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
5811
5812 {"icbi",        X(31,982),      XRT_MASK,    PPC|PPCVLE, PPCNONE,       {RA0, RB}},
5813
5814 {"stfiwx",      X(31,983),      X_MASK,      PPC,       PPCEFS,         {FRS, RA0, RB}},
5815
5816 {"extsw",       XRC(31,986,0),  XRB_MASK, PPC64|PPCVLE, PPCNONE,        {RA, RS}},
5817 {"extsw.",      XRC(31,986,1),  XRB_MASK, PPC64|PPCVLE, PPCNONE,        {RA, RS}},
5818
5819 {"icbiep",      XRT(31,991,0),  XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
5820
5821 {"stvswxl",     X(31,997),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5822
5823 {"icread",      X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCVLE, PPCNONE, {RA0, RB}},
5824
5825 {"nabso",       XO(31,488,1,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
5826 {"nabso.",      XO(31,488,1,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
5827
5828 {"divdo",       XO(31,489,1,0), XO_MASK,  PPC64|PPCVLE, PPCNONE,        {RT, RA, RB}},
5829 {"divdo.",      XO(31,489,1,1), XO_MASK,  PPC64|PPCVLE, PPCNONE,        {RT, RA, RB}},
5830
5831 {"divwo",       XO(31,491,1,0), XO_MASK,   PPC|PPCVLE,  PPCNONE,        {RT, RA, RB}},
5832 {"divwo.",      XO(31,491,1,1), XO_MASK,   PPC|PPCVLE,  PPCNONE,        {RT, RA, RB}},
5833
5834 {"trechkpt.",   XRC(31,1006,1), XRTRARB_MASK,PPCHTM,    PPCNONE,        {0}},
5835
5836 {"tlbli",       X(31,1010),     XRTRA_MASK,  PPC,       TITAN,          {RB}},
5837
5838 {"stdcix",      X(31,1013),     X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
5839
5840 {"dcbz",        X(31,1014),     XRT_MASK,    PPC|PPCVLE, PPCNONE,       {RA0, RB}},
5841 {"dclz",        X(31,1014),     XRT_MASK,    PPC,       PPCNONE,        {RA0, RB}},
5842
5843 {"dcbzep",      XRT(31,1023,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
5844
5845 {"dcbzl",       XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476,       {RA0, RB}},
5846
5847 {"cctpl",       0x7c210b78,     0xffffffff,  CELL,      PPCNONE,        {0}},
5848 {"cctpm",       0x7c421378,     0xffffffff,  CELL,      PPCNONE,        {0}},
5849 {"cctph",       0x7c631b78,     0xffffffff,  CELL,      PPCNONE,        {0}},
5850
5851 {"dstt",        XDSS(31,342,1), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
5852 {"dststt",      XDSS(31,374,1), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
5853 {"dssall",      XDSS(31,822,1), XDSS_MASK,   PPCVEC,    PPCNONE,        {0}},
5854
5855 {"db8cyc",      0x7f9ce378,     0xffffffff,  CELL,      PPCNONE,        {0}},
5856 {"db10cyc",     0x7fbdeb78,     0xffffffff,  CELL,      PPCNONE,        {0}},
5857 {"db12cyc",     0x7fdef378,     0xffffffff,  CELL,      PPCNONE,        {0}},
5858 {"db16cyc",     0x7ffffb78,     0xffffffff,  CELL,      PPCNONE,        {0}},
5859
5860 {"lwz",         OP(32),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RA0}},
5861 {"l",           OP(32),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
5862
5863 {"lwzu",        OP(33),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RAL}},
5864 {"lu",          OP(33),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
5865
5866 {"lbz",         OP(34),         OP_MASK,     COM,       PPCNONE,        {RT, D, RA0}},
5867
5868 {"lbzu",        OP(35),         OP_MASK,     COM,       PPCNONE,        {RT, D, RAL}},
5869
5870 {"stw",         OP(36),         OP_MASK,     PPCCOM,    PPCNONE,        {RS, D, RA0}},
5871 {"st",          OP(36),         OP_MASK,     PWRCOM,    PPCNONE,        {RS, D, RA0}},
5872
5873 {"stwu",        OP(37),         OP_MASK,     PPCCOM,    PPCNONE,        {RS, D, RAS}},
5874 {"stu",         OP(37),         OP_MASK,     PWRCOM,    PPCNONE,        {RS, D, RA0}},
5875
5876 {"stb",         OP(38),         OP_MASK,     COM,       PPCNONE,        {RS, D, RA0}},
5877
5878 {"stbu",        OP(39),         OP_MASK,     COM,       PPCNONE,        {RS, D, RAS}},
5879
5880 {"lhz",         OP(40),         OP_MASK,     COM,       PPCNONE,        {RT, D, RA0}},
5881
5882 {"lhzu",        OP(41),         OP_MASK,     COM,       PPCNONE,        {RT, D, RAL}},
5883
5884 {"lha",         OP(42),         OP_MASK,     COM,       PPCNONE,        {RT, D, RA0}},
5885
5886 {"lhau",        OP(43),         OP_MASK,     COM,       PPCNONE,        {RT, D, RAL}},
5887
5888 {"sth",         OP(44),         OP_MASK,     COM,       PPCNONE,        {RS, D, RA0}},
5889
5890 {"sthu",        OP(45),         OP_MASK,     COM,       PPCNONE,        {RS, D, RAS}},
5891
5892 {"lmw",         OP(46),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RAM}},
5893 {"lm",          OP(46),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
5894
5895 {"stmw",        OP(47),         OP_MASK,     PPCCOM,    PPCNONE,        {RS, D, RA0}},
5896 {"stm",         OP(47),         OP_MASK,     PWRCOM,    PPCNONE,        {RS, D, RA0}},
5897
5898 {"lfs",         OP(48),         OP_MASK,     COM,       PPCEFS,         {FRT, D, RA0}},
5899
5900 {"lfsu",        OP(49),         OP_MASK,     COM,       PPCEFS,         {FRT, D, RAS}},
5901
5902 {"lfd",         OP(50),         OP_MASK,     COM,       PPCEFS,         {FRT, D, RA0}},
5903
5904 {"lfdu",        OP(51),         OP_MASK,     COM,       PPCEFS,         {FRT, D, RAS}},
5905
5906 {"stfs",        OP(52),         OP_MASK,     COM,       PPCEFS,         {FRS, D, RA0}},
5907
5908 {"stfsu",       OP(53),         OP_MASK,     COM,       PPCEFS,         {FRS, D, RAS}},
5909
5910 {"stfd",        OP(54),         OP_MASK,     COM,       PPCEFS,         {FRS, D, RA0}},
5911
5912 {"stfdu",       OP(55),         OP_MASK,     COM,       PPCEFS,         {FRS, D, RAS}},
5913
5914 {"lq",          OP(56),         OP_MASK,     POWER4,    PPC476,         {RTQ, DQ, RAQ}},
5915 {"psq_l",       OP(56),         OP_MASK,     PPCPS,     PPCNONE,        {FRT,PSD,RA,PSW,PSQ}},
5916 {"lfq",         OP(56),         OP_MASK,     POWER2,    PPCNONE,        {FRT, D, RA0}},
5917
5918 {"lfdp",        OP(57),         OP_MASK,     POWER6,    POWER7,         {FRTp, DS, RA0}},
5919 {"psq_lu",      OP(57),         OP_MASK,     PPCPS,     PPCNONE,        {FRT,PSD,RA,PSW,PSQ}},
5920 {"lfqu",        OP(57),         OP_MASK,     POWER2,    PPCNONE,        {FRT, D, RA0}},
5921
5922 {"ld",          DSO(58,0),      DS_MASK,     PPC64,     PPCNONE,        {RT, DS, RA0}},
5923 {"ldu",         DSO(58,1),      DS_MASK,     PPC64,     PPCNONE,        {RT, DS, RAL}},
5924 {"lwa",         DSO(58,2),      DS_MASK,     PPC64,     PPCNONE,        {RT, DS, RA0}},
5925
5926 {"dadd",        XRC(59,2,0),    X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5927 {"dadd.",       XRC(59,2,1),    X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5928
5929 {"dqua",        ZRC(59,3,0),    Z2_MASK,     POWER6,    PPCNONE,        {FRT,FRA,FRB,RMC}},
5930 {"dqua.",       ZRC(59,3,1),    Z2_MASK,     POWER6,    PPCNONE,        {FRT,FRA,FRB,RMC}},
5931
5932 {"fdivs",       A(59,18,0),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
5933 {"fdivs.",      A(59,18,1),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
5934
5935 {"fsubs",       A(59,20,0),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
5936 {"fsubs.",      A(59,20,1),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
5937
5938 {"fadds",       A(59,21,0),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
5939 {"fadds.",      A(59,21,1),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
5940
5941 {"fsqrts",      A(59,22,0),    AFRAFRC_MASK, PPC,       TITAN,          {FRT, FRB}},
5942 {"fsqrts.",     A(59,22,1),    AFRAFRC_MASK, PPC,       TITAN,          {FRT, FRB}},
5943
5944 {"fres",        A(59,24,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
5945 {"fres",        A(59,24,0),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
5946 {"fres.",       A(59,24,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
5947 {"fres.",       A(59,24,1),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
5948
5949 {"fmuls",       A(59,25,0),     AFRB_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRC}},
5950 {"fmuls.",      A(59,25,1),     AFRB_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRC}},
5951
5952 {"frsqrtes",    A(59,26,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
5953 {"frsqrtes",    A(59,26,0),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
5954 {"frsqrtes.",   A(59,26,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
5955 {"frsqrtes.",   A(59,26,1),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
5956
5957 {"fmsubs",      A(59,28,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
5958 {"fmsubs.",     A(59,28,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
5959
5960 {"fmadds",      A(59,29,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
5961 {"fmadds.",     A(59,29,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
5962
5963 {"fnmsubs",     A(59,30,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
5964 {"fnmsubs.",    A(59,30,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
5965
5966 {"fnmadds",     A(59,31,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
5967 {"fnmadds.",    A(59,31,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
5968
5969 {"dmul",        XRC(59,34,0),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5970 {"dmul.",       XRC(59,34,1),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5971
5972 {"drrnd",       ZRC(59,35,0),   Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
5973 {"drrnd.",      ZRC(59,35,1),   Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
5974
5975 {"dscli",       ZRC(59,66,0),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
5976 {"dscli.",      ZRC(59,66,1),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
5977
5978 {"dquai",       ZRC(59,67,0),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRT,FRB,RMC}},
5979 {"dquai.",      ZRC(59,67,1),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRT,FRB,RMC}},
5980
5981 {"dscri",       ZRC(59,98,0),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
5982 {"dscri.",      ZRC(59,98,1),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
5983
5984 {"drintx",      ZRC(59,99,0),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
5985 {"drintx.",     ZRC(59,99,1),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
5986
5987 {"dcmpo",       X(59,130),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
5988
5989 {"dtstex",      X(59,162),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
5990 {"dtstdc",      Z(59,194),      Z_MASK,      POWER6,    PPCNONE,        {BF,  FRA, DCM}},
5991 {"dtstdg",      Z(59,226),      Z_MASK,      POWER6,    PPCNONE,        {BF,  FRA, DGM}},
5992
5993 {"drintn",      ZRC(59,227,0),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
5994 {"drintn.",     ZRC(59,227,1),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
5995
5996 {"dctdp",       XRC(59,258,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5997 {"dctdp.",      XRC(59,258,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5998
5999 {"dctfix",      XRC(59,290,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
6000 {"dctfix.",     XRC(59,290,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
6001
6002 {"ddedpd",      XRC(59,322,0),  X_MASK,      POWER6,    PPCNONE,        {SP, FRT, FRB}},
6003 {"ddedpd.",     XRC(59,322,1),  X_MASK,      POWER6,    PPCNONE,        {SP, FRT, FRB}},
6004
6005 {"dxex",        XRC(59,354,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
6006 {"dxex.",       XRC(59,354,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
6007
6008 {"dsub",        XRC(59,514,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
6009 {"dsub.",       XRC(59,514,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
6010
6011 {"ddiv",        XRC(59,546,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
6012 {"ddiv.",       XRC(59,546,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
6013
6014 {"dcmpu",       X(59,642),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
6015
6016 {"dtstsf",      X(59,674),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
6017
6018 {"drsp",        XRC(59,770,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
6019 {"drsp.",       XRC(59,770,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
6020
6021 {"dcffix",      XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCNONE,        {FRT, FRB}},
6022 {"dcffix.",     XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCNONE,        {FRT, FRB}},
6023
6024 {"denbcd",      XRC(59,834,0),  X_MASK,      POWER6,    PPCNONE,        {S, FRT, FRB}},
6025 {"denbcd.",     XRC(59,834,1),  X_MASK,      POWER6,    PPCNONE,        {S, FRT, FRB}},
6026
6027 {"fcfids",      XRC(59,846,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6028 {"fcfids.",     XRC(59,846,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6029
6030 {"diex",        XRC(59,866,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
6031 {"diex.",       XRC(59,866,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
6032
6033 {"fcfidus",     XRC(59,974,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6034 {"fcfidus.",    XRC(59,974,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6035
6036 {"xsaddsp",     XX3(60,0),      XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
6037 {"xsmaddasp",   XX3(60,1),      XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
6038 {"xxsldwi",     XX3(60,2),      XX3SHW_MASK, PPCVSX,    PPCNONE,        {XT6, XA6, XB6, SHW}},
6039 {"xxsel",       XX4(60,3),      XX4_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6, XC6}},
6040 {"xssubsp",     XX3(60,8),      XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
6041 {"xsmaddmsp",   XX3(60,9),      XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
6042 {"xxspltd",     XX3(60,10),     XX3DM_MASK,  PPCVSX,    PPCNONE,        {XT6, XA6, XB6S, DMEX}},
6043 {"xxmrghd",     XX3(60,10),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6044 {"xxswapd",     XX3(60,10)|(2<<8), XX3_MASK, PPCVSX,    PPCNONE,        {XT6, XA6, XB6S}},
6045 {"xxmrgld",     XX3(60,10)|(3<<8), XX3_MASK, PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6046 {"xxpermdi",    XX3(60,10),     XX3DM_MASK,  PPCVSX,    PPCNONE,        {XT6, XA6, XB6, DM}},
6047 {"xsrsqrtesp",  XX2(60,10),     XX2_MASK,    PPCVSX2,   PPCNONE,        {XT6, XB6}},
6048 {"xssqrtsp",    XX2(60,11),     XX2_MASK,    PPCVSX2,   PPCNONE,        {XT6, XB6}},
6049 {"xsmulsp",     XX3(60,16),     XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
6050 {"xsmsubasp",   XX3(60,17),     XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
6051 {"xxmrghw",     XX3(60,18),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6052 {"xsdivsp",     XX3(60,24),     XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
6053 {"xsmsubmsp",   XX3(60,25),     XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
6054 {"xsresp",      XX2(60,26),     XX2_MASK,    PPCVSX2,   PPCNONE,        {XT6, XB6}},
6055 {"xsadddp",     XX3(60,32),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6056 {"xsmaddadp",   XX3(60,33),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6057 {"xscmpudp",    XX3(60,35),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
6058 {"xssubdp",     XX3(60,40),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6059 {"xsmaddmdp",   XX3(60,41),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6060 {"xscmpodp",    XX3(60,43),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
6061 {"xsmuldp",     XX3(60,48),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6062 {"xsmsubadp",   XX3(60,49),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6063 {"xxmrglw",     XX3(60,50),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6064 {"xsdivdp",     XX3(60,56),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6065 {"xsmsubmdp",   XX3(60,57),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6066 {"xstdivdp",    XX3(60,61),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
6067 {"xvaddsp",     XX3(60,64),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6068 {"xvmaddasp",   XX3(60,65),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6069 {"xvcmpeqsp",   XX3RC(60,67,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6070 {"xvcmpeqsp.",  XX3RC(60,67,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6071 {"xvsubsp",     XX3(60,72),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6072 {"xscvdpuxws",  XX2(60,72),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6073 {"xvmaddmsp",   XX3(60,73),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6074 {"xsrdpi",      XX2(60,73),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6075 {"xsrsqrtedp",  XX2(60,74),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6076 {"xssqrtdp",    XX2(60,75),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6077 {"xvcmpgtsp",   XX3RC(60,75,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6078 {"xvcmpgtsp.",  XX3RC(60,75,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6079 {"xvmulsp",     XX3(60,80),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6080 {"xvmsubasp",   XX3(60,81),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6081 {"xvcmpgesp",   XX3RC(60,83,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6082 {"xvcmpgesp.",  XX3RC(60,83,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6083 {"xvdivsp",     XX3(60,88),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6084 {"xscvdpsxws",  XX2(60,88),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6085 {"xvmsubmsp",   XX3(60,89),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6086 {"xsrdpiz",     XX2(60,89),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6087 {"xsredp",      XX2(60,90),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6088 {"xvtdivsp",    XX3(60,93),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
6089 {"xvadddp",     XX3(60,96),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6090 {"xvmaddadp",   XX3(60,97),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6091 {"xvcmpeqdp",   XX3RC(60,99,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6092 {"xvcmpeqdp.",  XX3RC(60,99,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6093 {"xvsubdp",     XX3(60,104),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6094 {"xvmaddmdp",   XX3(60,105),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6095 {"xsrdpip",     XX2(60,105),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6096 {"xstsqrtdp",   XX2(60,106),    XX2BF_MASK,  PPCVSX,    PPCNONE,        {BF, XB6}},
6097 {"xsrdpic",     XX2(60,107),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6098 {"xvcmpgtdp",   XX3RC(60,107,0), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6099 {"xvcmpgtdp.",  XX3RC(60,107,1), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6100 {"xvmuldp",     XX3(60,112),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6101 {"xvmsubadp",   XX3(60,113),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6102 {"xvcmpgedp",   XX3RC(60,115,0), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6103 {"xvcmpgedp.",  XX3RC(60,115,1), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6104 {"xvdivdp",     XX3(60,120),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6105 {"xvmsubmdp",   XX3(60,121),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6106 {"xsrdpim",     XX2(60,121),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6107 {"xvtdivdp",    XX3(60,125),    XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
6108 {"xsnmaddasp",  XX3(60,129),    XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
6109 {"xxland",      XX3(60,130),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6110 {"xvcvspuxws",  XX2(60,136),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6111 {"xsnmaddmsp",  XX3(60,137),    XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
6112 {"xvrspi",      XX2(60,137),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6113 {"xxlandc",     XX3(60,138),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6114 {"xvrsqrtesp",  XX2(60,138),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6115 {"xvsqrtsp",    XX2(60,139),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6116 {"xsnmsubasp",  XX3(60,145),    XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
6117 {"xxlor",       XX3(60,146),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6118 {"xvcvspsxws",  XX2(60,152),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6119 {"xsnmsubmsp",  XX3(60,153),    XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
6120 {"xvrspiz",     XX2(60,153),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6121 {"xxlxor",      XX3(60,154),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6122 {"xvresp",      XX2(60,154),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6123 {"xsmaxdp",     XX3(60,160),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6124 {"xsnmaddadp",  XX3(60,161),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6125 {"xxlnor",      XX3(60,162),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6126 {"xxspltw",     XX2(60,164),    XX2UIM_MASK, PPCVSX,    PPCNONE,        {XT6, XB6, UIM}},
6127 {"xsmindp",     XX3(60,168),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6128 {"xvcvuxwsp",   XX2(60,168),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6129 {"xsnmaddmdp",  XX3(60,169),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6130 {"xvrspip",     XX2(60,169),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6131 {"xvtsqrtsp",   XX2(60,170),    XX2BF_MASK,  PPCVSX,    PPCNONE,        {BF, XB6}},
6132 {"xxlorc",      XX3(60,170),    XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
6133 {"xvrspic",     XX2(60,171),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6134 {"xscpsgndp",   XX3(60,176),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6135 {"xsnmsubadp",  XX3(60,177),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6136 {"xxlnand",     XX3(60,178),    XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
6137 {"xvcvsxwsp",   XX2(60,184),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6138 {"xsnmsubmdp",  XX3(60,185),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6139 {"xvrspim",     XX2(60,185),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6140 {"xxleqv",      XX3(60,186),    XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
6141 {"xvmaxsp",     XX3(60,192),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6142 {"xvnmaddasp",  XX3(60,193),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6143 {"xvminsp",     XX3(60,200),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6144 {"xvcvdpuxws",  XX2(60,200),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6145 {"xvnmaddmsp",  XX3(60,201),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6146 {"xvrdpi",      XX2(60,201),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6147 {"xvrsqrtedp",  XX2(60,202),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6148 {"xvsqrtdp",    XX2(60,203),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6149 {"xvmovsp",     XX3(60,208),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6S}},
6150 {"xvcpsgnsp",   XX3(60,208),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6151 {"xvnmsubasp",  XX3(60,209),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6152 {"xvcvdpsxws",  XX2(60,216),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6153 {"xvnmsubmsp",  XX3(60,217),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6154 {"xvrdpiz",     XX2(60,217),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6155 {"xvredp",      XX2(60,218),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6156 {"xvmaxdp",     XX3(60,224),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6157 {"xvnmaddadp",  XX3(60,225),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6158 {"xvmindp",     XX3(60,232),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6159 {"xvnmaddmdp",  XX3(60,233),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6160 {"xvcvuxwdp",   XX2(60,232),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6161 {"xvrdpip",     XX2(60,233),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6162 {"xvtsqrtdp",   XX2(60,234),    XX2BF_MASK,  PPCVSX,    PPCNONE,        {BF, XB6}},
6163 {"xvrdpic",     XX2(60,235),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6164 {"xvmovdp",     XX3(60,240),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6S}},
6165 {"xvcpsgndp",   XX3(60,240),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6166 {"xvnmsubadp",  XX3(60,241),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6167 {"xvcvsxwdp",   XX2(60,248),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6168 {"xvnmsubmdp",  XX3(60,249),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
6169 {"xvrdpim",     XX2(60,249),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6170 {"xscvdpsp",    XX2(60,265),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6171 {"xscvdpspn",   XX2(60,267),    XX2_MASK,    PPCVSX2,   PPCNONE,        {XT6, XB6}},
6172 {"xsrsp",       XX2(60,281),    XX2_MASK,    PPCVSX2,   PPCNONE,        {XT6, XB6}},
6173 {"xscvuxdsp",   XX2(60,296),    XX2_MASK,    PPCVSX2,   PPCNONE,        {XT6, XB6}},
6174 {"xscvsxdsp",   XX2(60,312),    XX2_MASK,    PPCVSX2,   PPCNONE,        {XT6, XB6}},
6175 {"xscvdpuxds",  XX2(60,328),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6176 {"xscvspdp",    XX2(60,329),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6177 {"xscvspdpn",   XX2(60,331),    XX2_MASK,    PPCVSX2,   PPCNONE,        {XT6, XB6}},
6178 {"xscvdpsxds",  XX2(60,344),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6179 {"xsabsdp",     XX2(60,345),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6180 {"xscvuxddp",   XX2(60,360),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6181 {"xsnabsdp",    XX2(60,361),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6182 {"xscvsxddp",   XX2(60,376),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6183 {"xsnegdp",     XX2(60,377),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6184 {"xvcvspuxds",  XX2(60,392),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6185 {"xvcvdpsp",    XX2(60,393),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6186 {"xvcvspsxds",  XX2(60,408),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6187 {"xvabssp",     XX2(60,409),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6188 {"xvcvuxdsp",   XX2(60,424),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6189 {"xvnabssp",    XX2(60,425),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6190 {"xvcvsxdsp",   XX2(60,440),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6191 {"xvnegsp",     XX2(60,441),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6192 {"xvcvdpuxds",  XX2(60,456),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6193 {"xvcvspdp",    XX2(60,457),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6194 {"xvcvdpsxds",  XX2(60,472),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6195 {"xvabsdp",     XX2(60,473),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6196 {"xvcvuxddp",   XX2(60,488),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6197 {"xvnabsdp",    XX2(60,489),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6198 {"xvcvsxddp",   XX2(60,504),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6199 {"xvnegdp",     XX2(60,505),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
6200
6201 {"psq_st",      OP(60),         OP_MASK,     PPCPS,     PPCNONE,        {FRS,PSD,RA,PSW,PSQ}},
6202 {"stfq",        OP(60),         OP_MASK,     POWER2,    PPCNONE,        {FRS, D, RA}},
6203
6204 {"stfdp",       OP(61),         OP_MASK,     POWER6,    POWER7,         {FRSp, DS, RA0}},
6205 {"psq_stu",     OP(61),         OP_MASK,     PPCPS,     PPCNONE,        {FRS,PSD,RA,PSW,PSQ}},
6206 {"stfqu",       OP(61),         OP_MASK,     POWER2,    PPCNONE,        {FRS, D, RA}},
6207
6208 {"std",         DSO(62,0),      DS_MASK,     PPC64,     PPCNONE,        {RS, DS, RA0}},
6209 {"stdu",        DSO(62,1),      DS_MASK,     PPC64,     PPCNONE,        {RS, DS, RAS}},
6210 {"stq",         DSO(62,2),      DS_MASK,     POWER4,    PPC476,         {RSQ, DS, RA0}},
6211
6212 {"fcmpu",       X(63,0),     X_MASK|(3<<21), COM,       PPCEFS,         {BF, FRA, FRB}},
6213
6214 {"daddq",       XRC(63,2,0),    X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
6215 {"daddq.",      XRC(63,2,1),    X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
6216
6217 {"dquaq",       ZRC(63,3,0),    Z2_MASK,     POWER6,    PPCNONE,        {FRTp, FRAp, FRBp, RMC}},
6218 {"dquaq.",      ZRC(63,3,1),    Z2_MASK,     POWER6,    PPCNONE,        {FRTp, FRAp, FRBp, RMC}},
6219
6220 {"fcpsgn",      XRC(63,8,0),    X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, FRA, FRB}},
6221 {"fcpsgn.",     XRC(63,8,1),    X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, FRA, FRB}},
6222
6223 {"frsp",        XRC(63,12,0),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6224 {"frsp.",       XRC(63,12,1),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6225
6226 {"fctiw",       XRC(63,14,0),   XRA_MASK,    PPCCOM,    PPCEFS,         {FRT, FRB}},
6227 {"fcir",        XRC(63,14,0),   XRA_MASK,    PWR2COM,   PPCNONE,        {FRT, FRB}},
6228 {"fctiw.",      XRC(63,14,1),   XRA_MASK,    PPCCOM,    PPCEFS,         {FRT, FRB}},
6229 {"fcir.",       XRC(63,14,1),   XRA_MASK,    PWR2COM,   PPCNONE,        {FRT, FRB}},
6230
6231 {"fctiwz",      XRC(63,15,0),   XRA_MASK,    PPCCOM,    PPCEFS,         {FRT, FRB}},
6232 {"fcirz",       XRC(63,15,0),   XRA_MASK,    PWR2COM,   PPCNONE,        {FRT, FRB}},
6233 {"fctiwz.",     XRC(63,15,1),   XRA_MASK,    PPCCOM,    PPCEFS,         {FRT, FRB}},
6234 {"fcirz.",      XRC(63,15,1),   XRA_MASK,    PWR2COM,   PPCNONE,        {FRT, FRB}},
6235
6236 {"fdiv",        A(63,18,0),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
6237 {"fd",          A(63,18,0),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
6238 {"fdiv.",       A(63,18,1),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
6239 {"fd.",         A(63,18,1),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
6240
6241 {"fsub",        A(63,20,0),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
6242 {"fs",          A(63,20,0),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
6243 {"fsub.",       A(63,20,1),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
6244 {"fs.",         A(63,20,1),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
6245
6246 {"fadd",        A(63,21,0),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
6247 {"fa",          A(63,21,0),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
6248 {"fadd.",       A(63,21,1),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
6249 {"fa.",         A(63,21,1),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
6250
6251 {"fsqrt",       A(63,22,0),    AFRAFRC_MASK, PPCPWR2,   TITAN,          {FRT, FRB}},
6252 {"fsqrt.",      A(63,22,1),    AFRAFRC_MASK, PPCPWR2,   TITAN,          {FRT, FRB}},
6253
6254 {"fsel",        A(63,23,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
6255 {"fsel.",       A(63,23,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
6256
6257 {"fre",         A(63,24,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
6258 {"fre",         A(63,24,0),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
6259 {"fre.",        A(63,24,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
6260 {"fre.",        A(63,24,1),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
6261
6262 {"fmul",        A(63,25,0),     AFRB_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRC}},
6263 {"fm",          A(63,25,0),     AFRB_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRC}},
6264 {"fmul.",       A(63,25,1),     AFRB_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRC}},
6265 {"fm.",         A(63,25,1),     AFRB_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRC}},
6266
6267 {"frsqrte",     A(63,26,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
6268 {"frsqrte",     A(63,26,0),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
6269 {"frsqrte.",    A(63,26,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
6270 {"frsqrte.",    A(63,26,1),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
6271
6272 {"fmsub",       A(63,28,0),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6273 {"fms",         A(63,28,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6274 {"fmsub.",      A(63,28,1),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6275 {"fms.",        A(63,28,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6276
6277 {"fmadd",       A(63,29,0),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6278 {"fma",         A(63,29,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6279 {"fmadd.",      A(63,29,1),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6280 {"fma.",        A(63,29,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6281
6282 {"fnmsub",      A(63,30,0),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6283 {"fnms",        A(63,30,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6284 {"fnmsub.",     A(63,30,1),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6285 {"fnms.",       A(63,30,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6286
6287 {"fnmadd",      A(63,31,0),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6288 {"fnma",        A(63,31,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6289 {"fnmadd.",     A(63,31,1),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6290 {"fnma.",       A(63,31,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6291
6292 {"fcmpo",       X(63,32),    X_MASK|(3<<21), COM,       PPCEFS,         {BF, FRA, FRB}},
6293
6294 {"dmulq",       XRC(63,34,0),   X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
6295 {"dmulq.",      XRC(63,34,1),   X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
6296
6297 {"drrndq",      ZRC(63,35,0),   Z2_MASK,     POWER6,    PPCNONE,        {FRTp, FRA, FRBp, RMC}},
6298 {"drrndq.",     ZRC(63,35,1),   Z2_MASK,     POWER6,    PPCNONE,        {FRTp, FRA, FRBp, RMC}},
6299
6300 {"mtfsb1",      XRC(63,38,0),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
6301 {"mtfsb1.",     XRC(63,38,1),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
6302
6303 {"fneg",        XRC(63,40,0),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6304 {"fneg.",       XRC(63,40,1),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6305
6306 {"mcrfs",      X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCNONE,        {BF, BFA}},
6307
6308 {"dscliq",      ZRC(63,66,0),   Z_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, SH16}},
6309 {"dscliq.",     ZRC(63,66,1),   Z_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, SH16}},
6310
6311 {"dquaiq",      ZRC(63,67,0),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRTp, FRBp, RMC}},
6312 {"dquaiq.",     ZRC(63,67,1),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRTp, FRBp, RMC}},
6313
6314 {"mtfsb0",      XRC(63,70,0),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
6315 {"mtfsb0.",     XRC(63,70,1),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
6316
6317 {"fmr",         XRC(63,72,0),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6318 {"fmr.",        XRC(63,72,1),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6319
6320 {"dscriq",      ZRC(63,98,0),   Z_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, SH16}},
6321 {"dscriq.",     ZRC(63,98,1),   Z_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, SH16}},
6322
6323 {"drintxq",     ZRC(63,99,0),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRTp, FRBp, RMC}},
6324 {"drintxq.",    ZRC(63,99,1),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRTp, FRBp, RMC}},
6325
6326 {"ftdiv",       X(63,128),   X_MASK|(3<<21), POWER7,    PPCNONE,        {BF, FRA, FRB}},
6327
6328 {"dcmpoq",      X(63,130),      X_MASK,      POWER6,    PPCNONE,        {BF, FRAp, FRBp}},
6329
6330 {"mtfsfi",  XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
6331 {"mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
6332 {"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
6333 {"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
6334
6335 {"fnabs",       XRC(63,136,0),  XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6336 {"fnabs.",      XRC(63,136,1),  XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6337
6338 {"fctiwu",      XRC(63,142,0),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
6339 {"fctiwu.",     XRC(63,142,1),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
6340 {"fctiwuz",     XRC(63,143,0),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
6341 {"fctiwuz.",    XRC(63,143,1),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
6342
6343 {"ftsqrt",      X(63,160), X_MASK|(3<<21|FRA_MASK), POWER7, PPCNONE,    {BF, FRB}},
6344
6345 {"dtstexq",     X(63,162),      X_MASK,      POWER6,    PPCNONE,        {BF, FRAp, FRBp}},
6346 {"dtstdcq",     Z(63,194),      Z_MASK,      POWER6,    PPCNONE,        {BF, FRAp, DCM}},
6347 {"dtstdgq",     Z(63,226),      Z_MASK,      POWER6,    PPCNONE,        {BF, FRAp, DGM}},
6348
6349 {"drintnq",     ZRC(63,227,0),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRTp, FRBp, RMC}},
6350 {"drintnq.",    ZRC(63,227,1),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRTp, FRBp, RMC}},
6351
6352 {"dctqpq",      XRC(63,258,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRB}},
6353 {"dctqpq.",     XRC(63,258,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRB}},
6354
6355 {"fabs",        XRC(63,264,0),  XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6356 {"fabs.",       XRC(63,264,1),  XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6357
6358 {"dctfixq",     XRC(63,290,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRBp}},
6359 {"dctfixq.",    XRC(63,290,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRBp}},
6360
6361 {"ddedpdq",     XRC(63,322,0),  X_MASK,      POWER6,    PPCNONE,        {SP, FRTp, FRBp}},
6362 {"ddedpdq.",    XRC(63,322,1),  X_MASK,      POWER6,    PPCNONE,        {SP, FRTp, FRBp}},
6363
6364 {"dxexq",       XRC(63,354,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRBp}},
6365 {"dxexq.",      XRC(63,354,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRBp}},
6366
6367 {"frin",        XRC(63,392,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6368 {"frin.",       XRC(63,392,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6369 {"friz",        XRC(63,424,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6370 {"friz.",       XRC(63,424,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6371 {"frip",        XRC(63,456,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6372 {"frip.",       XRC(63,456,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6373 {"frim",        XRC(63,488,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6374 {"frim.",       XRC(63,488,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6375
6376 {"dsubq",       XRC(63,514,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
6377 {"dsubq.",      XRC(63,514,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
6378
6379 {"ddivq",       XRC(63,546,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
6380 {"ddivq.",      XRC(63,546,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
6381
6382 {"mffs",        XRC(63,583,0),  XRARB_MASK,  COM,       PPCEFS,         {FRT}},
6383 {"mffs.",       XRC(63,583,1),  XRARB_MASK,  COM,       PPCEFS,         {FRT}},
6384
6385 {"dcmpuq",      X(63,642),      X_MASK,      POWER6,    PPCNONE,        {BF, FRAp, FRBp}},
6386
6387 {"dtstsfq",     X(63,674),      X_MASK,      POWER6,    PPCNONE,        {BF, FRA, FRBp}},
6388
6389 {"mtfsf",       XFL(63,711,0),  XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
6390 {"mtfsf",       XFL(63,711,0),  XFL_MASK,    COM, POWER6|PPCA2|PPC476|PPCEFS,   {FLM, FRB}},
6391 {"mtfsf.",      XFL(63,711,1),  XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
6392 {"mtfsf.",      XFL(63,711,1),  XFL_MASK,    COM, POWER6|PPCA2|PPC476|PPCEFS,   {FLM, FRB}},
6393
6394 {"drdpq",       XRC(63,770,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRBp}},
6395 {"drdpq.",      XRC(63,770,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRBp}},
6396
6397 {"dcffixq",     XRC(63,802,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRB}},
6398 {"dcffixq.",    XRC(63,802,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRB}},
6399
6400 {"fctid",       XRC(63,814,0),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
6401 {"fctid",       XRC(63,814,0),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
6402 {"fctid.",      XRC(63,814,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
6403 {"fctid.",      XRC(63,814,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
6404
6405 {"fctidz",      XRC(63,815,0),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
6406 {"fctidz",      XRC(63,815,0),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
6407 {"fctidz.",     XRC(63,815,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
6408 {"fctidz.",     XRC(63,815,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
6409
6410 {"denbcdq",     XRC(63,834,0),  X_MASK,      POWER6,    PPCNONE,        {S, FRTp, FRBp}},
6411 {"denbcdq.",    XRC(63,834,1),  X_MASK,      POWER6,    PPCNONE,        {S, FRTp, FRBp}},
6412
6413 {"fmrgow",      X(63,838),      X_MASK,      PPCVSX2,   PPCNONE,        {FRT, FRA, FRB}},
6414
6415 {"fcfid",       XRC(63,846,0),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
6416 {"fcfid",       XRC(63,846,0),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
6417 {"fcfid.",      XRC(63,846,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
6418 {"fcfid.",      XRC(63,846,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
6419
6420 {"diexq",       XRC(63,866,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRA, FRBp}},
6421 {"diexq.",      XRC(63,866,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRA, FRBp}},
6422
6423 {"fctidu",      XRC(63,942,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6424 {"fctidu.",     XRC(63,942,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6425
6426 {"fctiduz",     XRC(63,943,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6427 {"fctiduz.",    XRC(63,943,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6428
6429 {"fmrgew",      X(63,966),      X_MASK,      PPCVSX2,   PPCNONE,        {FRT, FRA, FRB}},
6430
6431 {"fcfidu",      XRC(63,974,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6432 {"fcfidu.",     XRC(63,974,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6433 };
6434
6435 const int powerpc_num_opcodes =
6436   sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
6437 \f
6438 /* The VLE opcode table.
6439
6440    The format of this opcode table is the same as the main opcode table.  */
6441
6442 const struct powerpc_opcode vle_opcodes[] = {
6443
6444 {"se_illegal",  C(0),           C_MASK,         PPCVLE, PPCNONE,        {}},
6445 {"se_isync",    C(1),           C_MASK,         PPCVLE, PPCNONE,        {}},
6446 {"se_sc",       C(2),           C_MASK,         PPCVLE, PPCNONE,        {}},
6447 {"se_blr",      C_LK(2,0),      C_LK_MASK,      PPCVLE, PPCNONE,        {}},
6448 {"se_blrl",     C_LK(2,1),      C_LK_MASK,      PPCVLE, PPCNONE,        {}},
6449 {"se_bctr",     C_LK(3,0),      C_LK_MASK,      PPCVLE, PPCNONE,        {}},
6450 {"se_bctrl",    C_LK(3,1),      C_LK_MASK,      PPCVLE, PPCNONE,        {}},
6451 {"se_rfi",      C(8),           C_MASK,         PPCVLE, PPCNONE,        {}},
6452 {"se_rfci",     C(9),           C_MASK,         PPCVLE, PPCNONE,        {}},
6453 {"se_rfdi",     C(10),          C_MASK,         PPCVLE, PPCNONE,        {}},
6454 {"se_rfmci",    C(11),          C_MASK,         PPCVLE, PPCNONE,        {}},
6455 {"se_not",      SE_R(0,2),      SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
6456 {"se_neg",      SE_R(0,3),      SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
6457 {"se_mflr",     SE_R(0,8),      SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
6458 {"se_mtlr",     SE_R(0,9),      SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
6459 {"se_mfctr",    SE_R(0,10),     SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
6460 {"se_mtctr",    SE_R(0,11),     SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
6461 {"se_extzb",    SE_R(0,12),     SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
6462 {"se_extsb",    SE_R(0,13),     SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
6463 {"se_extzh",    SE_R(0,14),     SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
6464 {"se_extsh",    SE_R(0,15),     SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
6465 {"se_mr",       SE_RR(0,1),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6466 {"se_mtar",     SE_RR(0,2),     SE_RR_MASK,     PPCVLE, PPCNONE,        {ARX, RY}},
6467 {"se_mfar",     SE_RR(0,3),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, ARY}},
6468 {"se_add",      SE_RR(1,0),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6469 {"se_mullw",    SE_RR(1,1),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6470 {"se_sub",      SE_RR(1,2),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6471 {"se_subf",     SE_RR(1,3),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6472 {"se_cmp",      SE_RR(3,0),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6473 {"se_cmpl",     SE_RR(3,1),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6474 {"se_cmph",     SE_RR(3,2),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6475 {"se_cmphl",    SE_RR(3,3),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6476
6477 {"e_cmpi",      SCI8BF(6,0,21), SCI8BF_MASK,    PPCVLE, PPCNONE,        {CRD32, RA, SCLSCI8}},
6478 {"e_cmpli",     SCI8BF(6,1,21), SCI8BF_MASK,    PPCVLE, PPCNONE,        {CRD32, RA, SCLSCI8}},
6479 {"e_addi",      SCI8(6,16),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
6480 {"e_subi",      SCI8(6,16),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8N}},
6481 {"e_addi.",     SCI8(6,17),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
6482 {"e_addic",     SCI8(6,18),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
6483 {"e_subic",     SCI8(6,18),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8N}},
6484 {"e_addic.",    SCI8(6,19),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
6485 {"e_subic.",    SCI8(6,19),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8N}},
6486 {"e_mulli",     SCI8(6,20),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
6487 {"e_subfic",    SCI8(6,22),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
6488 {"e_subfic.",   SCI8(6,23),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
6489 {"e_andi",      SCI8(6,24),     SCI8_MASK,      PPCVLE, PPCNONE,        {RA, RS, SCLSCI8}},
6490 {"e_andi.",     SCI8(6,25),     SCI8_MASK,      PPCVLE, PPCNONE,        {RA, RS, SCLSCI8}},
6491 {"e_nop",       SCI8(6,26),     0xffffffff,     PPCVLE, PPCNONE,        {0}},
6492 {"e_ori",       SCI8(6,26),     SCI8_MASK,      PPCVLE, PPCNONE,        {RA, RS, SCLSCI8}},
6493 {"e_ori.",      SCI8(6,27),     SCI8_MASK,      PPCVLE, PPCNONE,        {RA, RS, SCLSCI8}},
6494 {"e_xori",      SCI8(6,28),     SCI8_MASK,      PPCVLE, PPCNONE,        {RA, RS, SCLSCI8}},
6495 {"e_xori.",     SCI8(6,29),     SCI8_MASK,      PPCVLE, PPCNONE,        {RA, RS, SCLSCI8}},
6496 {"e_lbzu",      OPVUP(6,0),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
6497 {"e_lhau",      OPVUP(6,3),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
6498 {"e_lhzu",      OPVUP(6,1),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
6499 {"e_lmw",       OPVUP(6,8),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
6500 {"e_lwzu",      OPVUP(6,2),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
6501 {"e_stbu",      OPVUP(6,4),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
6502 {"e_sthu",      OPVUP(6,5),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
6503 {"e_stwu",      OPVUP(6,6),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
6504 {"e_stmw",      OPVUP(6,9),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
6505 {"e_add16i",    OP(7),          OP_MASK,        PPCVLE, PPCNONE,        {RT, RA, SI}},
6506 {"e_la",        OP(7),          OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
6507 {"e_sub16i",    OP(7),          OP_MASK,        PPCVLE, PPCNONE,        {RT, RA, NSI}},
6508
6509 {"se_addi",     SE_IM5(8,0),    SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, OIMM5}},
6510 {"se_cmpli",    SE_IM5(8,1),    SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, OIMM5}},
6511 {"se_subi",     SE_IM5(9,0),    SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, OIMM5}},
6512 {"se_subi.",    SE_IM5(9,1),    SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, OIMM5}},
6513 {"se_cmpi",     SE_IM5(10,1),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
6514 {"se_bmaski",   SE_IM5(11,0),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
6515 {"se_andi",     SE_IM5(11,1),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
6516
6517 {"e_lbz",       OP(12),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
6518 {"e_stb",       OP(13),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
6519 {"e_lha",       OP(14),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
6520
6521 {"se_srw",      SE_RR(16,0),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6522 {"se_sraw",     SE_RR(16,1),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6523 {"se_slw",      SE_RR(16,2),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6524 {"se_nop",      SE_RR(17,0),    0xffff,         PPCVLE, PPCNONE,        {0}},
6525 {"se_or",       SE_RR(17,0),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6526 {"se_andc",     SE_RR(17,1),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6527 {"se_and",      SE_RR(17,2),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6528 {"se_and.",     SE_RR(17,3),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6529 {"se_li",       IM7(9),         IM7_MASK,       PPCVLE, PPCNONE,        {RX, UI7}},
6530
6531 {"e_lwz",       OP(20),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
6532 {"e_stw",       OP(21),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
6533 {"e_lhz",       OP(22),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
6534 {"e_sth",       OP(23),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
6535
6536 {"se_bclri",    SE_IM5(24,0),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
6537 {"se_bgeni",    SE_IM5(24,1),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
6538 {"se_bseti",    SE_IM5(25,0),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
6539 {"se_btsti",    SE_IM5(25,1),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
6540 {"se_srwi",     SE_IM5(26,0),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
6541 {"se_srawi",    SE_IM5(26,1),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
6542 {"se_slwi",     SE_IM5(27,0),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
6543
6544 {"e_lis",       I16L(28,28),    I16L_MASK,      PPCVLE, PPCNONE,        {RD, VLEUIMML}},
6545 {"e_and2is.",   I16L(28,29),    I16L_MASK,      PPCVLE, PPCNONE,        {RD, VLEUIMML}},
6546 {"e_or2is",     I16L(28,26),    I16L_MASK,      PPCVLE, PPCNONE,        {RD, VLEUIMML}},
6547 {"e_and2i.",    I16L(28,25),    I16L_MASK,      PPCVLE, PPCNONE,        {RD, VLEUIMML}},
6548 {"e_or2i",      I16L(28,24),    I16L_MASK,      PPCVLE, PPCNONE,        {RD, VLEUIMML}},
6549 {"e_cmphl16i",  IA16(28,23),    IA16_MASK,      PPCVLE, PPCNONE,        {RA, VLEUIMM}},
6550 {"e_cmph16i",   IA16(28,22),    IA16_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
6551 {"e_cmpl16i",   I16A(28,21),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLEUIMM}},
6552 {"e_cmplwi",    I16A(28,21),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
6553 {"e_mull2i",    I16A(28,20),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
6554 {"e_cmp16i",    IA16(28,19),    IA16_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
6555 {"e_cmpwi",     IA16(28,19),    IA16_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
6556 {"e_sub2is",    I16A(28,18),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLENSIMM}},
6557 {"e_add2is",    I16A(28,18),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
6558 {"e_sub2i.",    I16A(28,17),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLENSIMM}},
6559 {"e_add2i.",    I16A(28,17),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
6560 {"e_li",        LI20(28,0),     LI20_MASK,      PPCVLE, PPCNONE,        {RT, IMM20}},
6561 {"e_rlwimi",    M(29,0),        M_MASK,         PPCVLE, PPCNONE,        {RA, RS, SH, MB, ME}},
6562 {"e_rlwinm",    M(29,1),        M_MASK,         PPCVLE, PPCNONE,        {RA, RT, SH, MBE, ME}},
6563 {"e_b",         BD24(30,0,0),   BD24_MASK,      PPCVLE, PPCNONE,        {B24}},
6564 {"e_bl",        BD24(30,0,1),   BD24_MASK,      PPCVLE, PPCNONE,        {B24}},
6565 {"e_bdnz",      EBD15(30,8,BO32DNZ,0),  EBD15_MASK, PPCVLE, PPCNONE,    {B15}},
6566 {"e_bdnzl",     EBD15(30,8,BO32DNZ,1),  EBD15_MASK, PPCVLE, PPCNONE,    {B15}},
6567 {"e_bdz",       EBD15(30,8,BO32DZ,0),   EBD15_MASK, PPCVLE, PPCNONE,    {B15}},
6568 {"e_bdzl",      EBD15(30,8,BO32DZ,1),   EBD15_MASK, PPCVLE, PPCNONE,    {B15}},
6569 {"e_bge",       EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6570 {"e_bgel",      EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6571 {"e_bnl",       EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6572 {"e_bnll",      EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6573 {"e_blt",       EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6574 {"e_bltl",      EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6575 {"e_bgt",       EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6576 {"e_bgtl",      EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6577 {"e_ble",       EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6578 {"e_blel",      EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6579 {"e_bng",       EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6580 {"e_bngl",      EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6581 {"e_bne",       EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6582 {"e_bnel",      EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6583 {"e_beq",       EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6584 {"e_beql",      EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6585 {"e_bso",       EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6586 {"e_bsol",      EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6587 {"e_bun",       EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6588 {"e_bunl",      EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6589 {"e_bns",       EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6590 {"e_bnsl",      EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6591 {"e_bnu",       EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6592 {"e_bnul",      EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6593 {"e_bc",        BD15(30,8,0),   BD15_MASK,      PPCVLE, PPCNONE,        {BO32, BI32, B15}},
6594 {"e_bcl",       BD15(30,8,1),   BD15_MASK,      PPCVLE, PPCNONE,        {BO32, BI32, B15}},
6595
6596 {"e_bf",        EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, PPCNONE,       {BI32,B15}},
6597 {"e_bfl",       EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, PPCNONE,       {BI32,B15}},
6598 {"e_bt",        EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, PPCNONE,       {BI32,B15}},
6599 {"e_btl",       EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, PPCNONE,       {BI32,B15}},
6600
6601 {"e_cmph",      X(31,14),       X_MASK,         PPCVLE, PPCNONE,        {CRD, RA, RB}},
6602 {"e_cmphl",     X(31,46),       X_MASK,         PPCVLE, PPCNONE,        {CRD, RA, RB}},
6603 {"e_crandc",    XL(31,129),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
6604 {"e_crnand",    XL(31,225),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
6605 {"e_crnot",     XL(31,33),      XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BBA}},
6606 {"e_crnor",     XL(31,33),      XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
6607 {"e_crclr",     XL(31,193),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BAT, BBA}},
6608 {"e_crxor",     XL(31,193),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
6609 {"e_mcrf",      XL(31,16),      XL_MASK,        PPCVLE, PPCNONE,        {CRD, CR}},
6610 {"e_slwi",      EX(31,112),     EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, SH}},
6611 {"e_slwi.",     EX(31,113),     EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, SH}},
6612
6613 {"e_crand",     XL(31,257),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
6614
6615 {"e_rlw",       EX(31,560),     EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, RB}},
6616 {"e_rlw.",      EX(31,561),     EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, RB}},
6617
6618 {"e_crset",     XL(31,289),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BAT, BBA}},
6619 {"e_creqv",     XL(31,289),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
6620
6621 {"e_rlwi",      EX(31,624),     EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, SH}},
6622 {"e_rlwi.",     EX(31,625),     EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, SH}},
6623
6624 {"e_crorc",     XL(31,417),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
6625
6626 {"e_crmove",    XL(31,449),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BBA}},
6627 {"e_cror",      XL(31,449),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
6628
6629 {"mtmas1",      XSPR(31,467,625), XSPR_MASK,    PPCVLE, PPCNONE,        {RS}},
6630
6631 {"e_srwi",      EX(31,1136),    EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, SH}},
6632 {"e_srwi.",     EX(31,1137),    EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, SH}},
6633
6634 {"se_lbz",      SD4(8),         SD4_MASK,       PPCVLE, PPCNONE,        {RZ, SE_SD, RX}},
6635
6636 {"se_stb",      SD4(9),         SD4_MASK,       PPCVLE, PPCNONE,        {RZ, SE_SD, RX}},
6637
6638 {"se_lhz",      SD4(10),        SD4_MASK,       PPCVLE, PPCNONE,        {RZ, SE_SDH, RX}},
6639
6640 {"se_sth",      SD4(11),        SD4_MASK,       PPCVLE, PPCNONE,        {RZ, SE_SDH, RX}},
6641
6642 {"se_lwz",      SD4(12),        SD4_MASK,       PPCVLE, PPCNONE,        {RZ, SE_SDW, RX}},
6643
6644 {"se_stw",      SD4(13),        SD4_MASK,       PPCVLE, PPCNONE,        {RZ, SE_SDW, RX}},
6645
6646 {"se_bge",      EBD8IO(28,0,0), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6647 {"se_bnl",      EBD8IO(28,0,0), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6648 {"se_ble",      EBD8IO(28,0,1), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6649 {"se_bng",      EBD8IO(28,0,1), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6650 {"se_bne",      EBD8IO(28,0,2), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6651 {"se_bns",      EBD8IO(28,0,3), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6652 {"se_bnu",      EBD8IO(28,0,3), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6653 {"se_bf",       EBD8IO(28,0,0), EBD8IO2_MASK,   PPCVLE, PPCNONE,        {BI16, B8}},
6654 {"se_blt",      EBD8IO(28,1,0), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6655 {"se_bgt",      EBD8IO(28,1,1), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6656 {"se_beq",      EBD8IO(28,1,2), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6657 {"se_bso",      EBD8IO(28,1,3), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6658 {"se_bun",      EBD8IO(28,1,3), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6659 {"se_bt",       EBD8IO(28,1,0), EBD8IO2_MASK,   PPCVLE, PPCNONE,        {BI16, B8}},
6660 {"se_bc",       BD8IO(28),      BD8IO_MASK,     PPCVLE, PPCNONE,        {BO16, BI16, B8}},
6661 {"se_b",        BD8(58,0,0),    BD8_MASK,       PPCVLE, PPCNONE,        {B8}},
6662 {"se_bl",       BD8(58,0,1),    BD8_MASK,       PPCVLE, PPCNONE,        {B8}},
6663 };
6664
6665 const int vle_num_opcodes =
6666   sizeof (vle_opcodes) / sizeof (vle_opcodes[0]);
6667 \f
6668 /* The macro table.  This is only used by the assembler.  */
6669
6670 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
6671    when x=0; 32-x when x is between 1 and 31; are negative if x is
6672    negative; and are 32 or more otherwise.  This is what you want
6673    when, for instance, you are emulating a right shift by a
6674    rotate-left-and-mask, because the underlying instructions support
6675    shifts of size 0 but not shifts of size 32.  By comparison, when
6676    extracting x bits from some word you want to use just 32-x, because
6677    the underlying instructions don't support extracting 0 bits but do
6678    support extracting the whole word (32 bits in this case).  */
6679
6680 const struct powerpc_macro powerpc_macros[] = {
6681 {"extldi",   4, PPC64,  "rldicr %0,%1,%3,(%2)-1"},
6682 {"extldi.",  4, PPC64,  "rldicr. %0,%1,%3,(%2)-1"},
6683 {"extrdi",   4, PPC64,  "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
6684 {"extrdi.",  4, PPC64,  "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
6685 {"insrdi",   4, PPC64,  "rldimi %0,%1,64-((%2)+(%3)),%3"},
6686 {"insrdi.",  4, PPC64,  "rldimi. %0,%1,64-((%2)+(%3)),%3"},
6687 {"rotrdi",   3, PPC64,  "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
6688 {"rotrdi.",  3, PPC64,  "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
6689 {"sldi",     3, PPC64,  "rldicr %0,%1,%2,63-(%2)"},
6690 {"sldi.",    3, PPC64,  "rldicr. %0,%1,%2,63-(%2)"},
6691 {"srdi",     3, PPC64,  "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
6692 {"srdi.",    3, PPC64,  "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
6693 {"clrrdi",   3, PPC64,  "rldicr %0,%1,0,63-(%2)"},
6694 {"clrrdi.",  3, PPC64,  "rldicr. %0,%1,0,63-(%2)"},
6695 {"clrlsldi", 4, PPC64,  "rldic %0,%1,%3,(%2)-(%3)"},
6696 {"clrlsldi.",4, PPC64,  "rldic. %0,%1,%3,(%2)-(%3)"},
6697
6698 {"extlwi",   4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
6699 {"extlwi.",  4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
6700 {"extrwi",   4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
6701 {"extrwi.",  4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
6702 {"inslwi",   4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
6703 {"inslwi.",  4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
6704 {"insrwi",   4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
6705 {"insrwi.",  4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
6706 {"rotrwi",   3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
6707 {"rotrwi.",  3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
6708 {"slwi",     3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"},
6709 {"sli",      3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
6710 {"slwi.",    3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"},
6711 {"sli.",     3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"},
6712 {"srwi",     3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6713 {"sri",      3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6714 {"srwi.",    3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6715 {"sri.",     3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6716 {"clrrwi",   3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"},
6717 {"clrrwi.",  3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
6718 {"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
6719 {"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
6720
6721 {"e_extlwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"},
6722 {"e_extrwi", 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
6723 {"e_inslwi", 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
6724 {"e_insrwi", 4, PPCVLE, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
6725 {"e_rotlwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31"},
6726 {"e_rotrwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
6727 {"e_slwi",   3, PPCVLE, "e_rlwinm %0,%1,%2,0,31-(%2)"},
6728 {"e_srwi",   3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6729 {"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"},
6730 {"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"},
6731 {"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
6732 };
6733
6734 const int powerpc_num_macros =
6735   sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);