Cleanup ppc code dealing with opcode dumps.
[deliverable/binutils-gdb.git] / opcodes / ppc-opc.c
1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright (C) 1994-2018 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
4
5 This file is part of the GNU opcodes library.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
22 #include "sysdep.h"
23 #include <stdio.h>
24 #include "opcode/ppc.h"
25 #include "opintl.h"
26
27 /* This file holds the PowerPC opcode table. The opcode table
28 includes almost all of the extended instruction mnemonics. This
29 permits the disassembler to use them, and simplifies the assembler
30 logic, at the cost of increasing the table size. The table is
31 strictly constant data, so the compiler should be able to put it in
32 the text segment.
33
34 This file also holds the operand table. All knowledge about
35 inserting operands into instructions and vice-versa is kept in this
36 file. */
37
38 /* The functions used to insert and extract complicated operands. */
39
40 /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
41
42 static uint64_t
43 insert_arx (uint64_t insn,
44 int64_t value,
45 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
46 const char **errmsg ATTRIBUTE_UNUSED)
47 {
48 if (value >= 8 && value < 24)
49 return insn | ((value - 8) & 0xf);
50 else
51 {
52 *errmsg = _("invalid register");
53 return 0;
54 }
55 }
56
57 static int64_t
58 extract_arx (uint64_t insn,
59 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
60 int *invalid ATTRIBUTE_UNUSED)
61 {
62 return (insn & 0xf) + 8;
63 }
64
65 static uint64_t
66 insert_ary (uint64_t insn,
67 int64_t value,
68 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
69 const char **errmsg ATTRIBUTE_UNUSED)
70 {
71 if (value >= 8 && value < 24)
72 return insn | (((value - 8) & 0xf) << 4);
73 else
74 {
75 *errmsg = _("invalid register");
76 return 0;
77 }
78 }
79
80 static int64_t
81 extract_ary (uint64_t insn,
82 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
83 int *invalid ATTRIBUTE_UNUSED)
84 {
85 return ((insn >> 4) & 0xf) + 8;
86 }
87
88 static uint64_t
89 insert_rx (uint64_t insn,
90 int64_t value,
91 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
92 const char **errmsg)
93 {
94 if (value >= 0 && value < 8)
95 return insn | value;
96 else if (value >= 24 && value <= 31)
97 return insn | (value - 16);
98 else
99 {
100 *errmsg = _("invalid register");
101 return 0;
102 }
103 }
104
105 static int64_t
106 extract_rx (uint64_t insn,
107 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
108 int *invalid ATTRIBUTE_UNUSED)
109 {
110 int64_t value = insn & 0xf;
111 if (value >= 0 && value < 8)
112 return value;
113 else
114 return value + 16;
115 }
116
117 static uint64_t
118 insert_ry (uint64_t insn,
119 int64_t value,
120 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
121 const char **errmsg)
122 {
123 if (value >= 0 && value < 8)
124 return insn | (value << 4);
125 else if (value >= 24 && value <= 31)
126 return insn | ((value - 16) << 4);
127 else
128 {
129 *errmsg = _("invalid register");
130 return 0;
131 }
132 }
133
134 static int64_t
135 extract_ry (uint64_t insn,
136 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
137 int *invalid ATTRIBUTE_UNUSED)
138 {
139 int64_t value = (insn >> 4) & 0xf;
140 if (value >= 0 && value < 8)
141 return value;
142 else
143 return value + 16;
144 }
145
146 /* The BA field in an XL form instruction when it must be the same as
147 the BT field in the same instruction. This operand is marked FAKE.
148 The insertion function just copies the BT field into the BA field,
149 and the extraction function just checks that the fields are the
150 same. */
151
152 static uint64_t
153 insert_bat (uint64_t insn,
154 int64_t value ATTRIBUTE_UNUSED,
155 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
156 const char **errmsg ATTRIBUTE_UNUSED)
157 {
158 return insn | (((insn >> 21) & 0x1f) << 16);
159 }
160
161 static int64_t
162 extract_bat (uint64_t insn,
163 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
164 int *invalid)
165 {
166 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
167 *invalid = 1;
168 return 0;
169 }
170
171 /* The BB field in an XL form instruction when it must be the same as
172 the BA field in the same instruction. This operand is marked FAKE.
173 The insertion function just copies the BA field into the BB field,
174 and the extraction function just checks that the fields are the
175 same. */
176
177 static uint64_t
178 insert_bba (uint64_t insn,
179 int64_t value ATTRIBUTE_UNUSED,
180 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
181 const char **errmsg ATTRIBUTE_UNUSED)
182 {
183 return insn | (((insn >> 16) & 0x1f) << 11);
184 }
185
186 static int64_t
187 extract_bba (uint64_t insn,
188 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
189 int *invalid)
190 {
191 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
192 *invalid = 1;
193 return 0;
194 }
195
196 /* The BD field in a B form instruction when the - modifier is used.
197 This modifier means that the branch is not expected to be taken.
198 For chips built to versions of the architecture prior to version 2
199 (ie. not Power4 compatible), we set the y bit of the BO field to 1
200 if the offset is negative. When extracting, we require that the y
201 bit be 1 and that the offset be positive, since if the y bit is 0
202 we just want to print the normal form of the instruction.
203 Power4 compatible targets use two bits, "a", and "t", instead of
204 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
205 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
206 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
207 for branch on CTR. We only handle the taken/not-taken hint here.
208 Note that we don't relax the conditions tested here when
209 disassembling with -Many because insns using extract_bdm and
210 extract_bdp always occur in pairs. One or the other will always
211 be valid. */
212
213 #define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
214
215 static uint64_t
216 insert_bdm (uint64_t insn,
217 int64_t value,
218 ppc_cpu_t dialect,
219 const char **errmsg ATTRIBUTE_UNUSED)
220 {
221 if ((dialect & ISA_V2) == 0)
222 {
223 if ((value & 0x8000) != 0)
224 insn |= 1 << 21;
225 }
226 else
227 {
228 if ((insn & (0x14 << 21)) == (0x04 << 21))
229 insn |= 0x02 << 21;
230 else if ((insn & (0x14 << 21)) == (0x10 << 21))
231 insn |= 0x08 << 21;
232 }
233 return insn | (value & 0xfffc);
234 }
235
236 static int64_t
237 extract_bdm (uint64_t insn,
238 ppc_cpu_t dialect,
239 int *invalid)
240 {
241 if ((dialect & ISA_V2) == 0)
242 {
243 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
244 *invalid = 1;
245 }
246 else
247 {
248 if ((insn & (0x17 << 21)) != (0x06 << 21)
249 && (insn & (0x1d << 21)) != (0x18 << 21))
250 *invalid = 1;
251 }
252
253 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
254 }
255
256 /* The BD field in a B form instruction when the + modifier is used.
257 This is like BDM, above, except that the branch is expected to be
258 taken. */
259
260 static uint64_t
261 insert_bdp (uint64_t insn,
262 int64_t value,
263 ppc_cpu_t dialect,
264 const char **errmsg ATTRIBUTE_UNUSED)
265 {
266 if ((dialect & ISA_V2) == 0)
267 {
268 if ((value & 0x8000) == 0)
269 insn |= 1 << 21;
270 }
271 else
272 {
273 if ((insn & (0x14 << 21)) == (0x04 << 21))
274 insn |= 0x03 << 21;
275 else if ((insn & (0x14 << 21)) == (0x10 << 21))
276 insn |= 0x09 << 21;
277 }
278 return insn | (value & 0xfffc);
279 }
280
281 static int64_t
282 extract_bdp (uint64_t insn,
283 ppc_cpu_t dialect,
284 int *invalid)
285 {
286 if ((dialect & ISA_V2) == 0)
287 {
288 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
289 *invalid = 1;
290 }
291 else
292 {
293 if ((insn & (0x17 << 21)) != (0x07 << 21)
294 && (insn & (0x1d << 21)) != (0x19 << 21))
295 *invalid = 1;
296 }
297
298 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
299 }
300
301 static inline int
302 valid_bo_pre_v2 (int64_t value)
303 {
304 /* Certain encodings have bits that are required to be zero.
305 These are (z must be zero, y may be anything):
306 0000y
307 0001y
308 001zy
309 0100y
310 0101y
311 011zy
312 1z00y
313 1z01y
314 1z1zz
315 */
316 if ((value & 0x14) == 0)
317 return 1;
318 else if ((value & 0x14) == 0x4)
319 return (value & 0x2) == 0;
320 else if ((value & 0x14) == 0x10)
321 return (value & 0x8) == 0;
322 else
323 return value == 0x14;
324 }
325
326 static inline int
327 valid_bo_post_v2 (int64_t value)
328 {
329 /* Certain encodings have bits that are required to be zero.
330 These are (z must be zero, a & t may be anything):
331 0000z
332 0001z
333 001at
334 0100z
335 0101z
336 011at
337 1a00t
338 1a01t
339 1z1zz
340 */
341 if ((value & 0x14) == 0)
342 return (value & 0x1) == 0;
343 else if ((value & 0x14) == 0x14)
344 return value == 0x14;
345 else
346 return 1;
347 }
348
349 /* Check for legal values of a BO field. */
350
351 static int
352 valid_bo (int64_t value, ppc_cpu_t dialect, int extract)
353 {
354 int valid_y = valid_bo_pre_v2 (value);
355 int valid_at = valid_bo_post_v2 (value);
356
357 /* When disassembling with -Many, accept either encoding on the
358 second pass through opcodes. */
359 if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY)
360 return valid_y || valid_at;
361 if ((dialect & ISA_V2) == 0)
362 return valid_y;
363 else
364 return valid_at;
365 }
366
367 /* The BO field in a B form instruction. Warn about attempts to set
368 the field to an illegal value. */
369
370 static uint64_t
371 insert_bo (uint64_t insn,
372 int64_t value,
373 ppc_cpu_t dialect,
374 const char **errmsg)
375 {
376 if (!valid_bo (value, dialect, 0))
377 *errmsg = _("invalid conditional option");
378 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
379 *errmsg = _("invalid counter access");
380 return insn | ((value & 0x1f) << 21);
381 }
382
383 static int64_t
384 extract_bo (uint64_t insn,
385 ppc_cpu_t dialect,
386 int *invalid)
387 {
388 int64_t value = (insn >> 21) & 0x1f;
389 if (!valid_bo (value, dialect, 1))
390 *invalid = 1;
391 return value;
392 }
393
394 /* The BO field in a B form instruction when the + or - modifier is
395 used. This is like the BO field, but it must be even. When
396 extracting it, we force it to be even. */
397
398 static uint64_t
399 insert_boe (uint64_t insn,
400 int64_t value,
401 ppc_cpu_t dialect,
402 const char **errmsg)
403 {
404 if (!valid_bo (value, dialect, 0))
405 *errmsg = _("invalid conditional option");
406 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
407 *errmsg = _("invalid counter access");
408 else if ((value & 1) != 0)
409 *errmsg = _("attempt to set y bit when using + or - modifier");
410
411 return insn | ((value & 0x1f) << 21);
412 }
413
414 static int64_t
415 extract_boe (uint64_t insn,
416 ppc_cpu_t dialect,
417 int *invalid)
418 {
419 int64_t value = (insn >> 21) & 0x1f;
420 if (!valid_bo (value, dialect, 1))
421 *invalid = 1;
422 return value & 0x1e;
423 }
424
425 /* The DCMX field in a X form instruction when the field is split
426 into separate DC, DM and DX fields. */
427
428 static uint64_t
429 insert_dcmxs (uint64_t insn,
430 int64_t value,
431 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
432 const char **errmsg ATTRIBUTE_UNUSED)
433 {
434 return (insn
435 | ((value & 0x1f) << 16)
436 | ((value & 0x20) >> 3)
437 | (value & 0x40));
438 }
439
440 static int64_t
441 extract_dcmxs (uint64_t insn,
442 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
443 int *invalid ATTRIBUTE_UNUSED)
444 {
445 return (insn & 0x40) | ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
446 }
447
448 /* The D field in a DX form instruction when the field is split
449 into separate D0, D1 and D2 fields. */
450
451 static uint64_t
452 insert_dxd (uint64_t insn,
453 int64_t value,
454 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
455 const char **errmsg ATTRIBUTE_UNUSED)
456 {
457 return insn | (value & 0xffc1) | ((value & 0x3e) << 15);
458 }
459
460 static int64_t
461 extract_dxd (uint64_t insn,
462 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
463 int *invalid ATTRIBUTE_UNUSED)
464 {
465 uint64_t dxd = (insn & 0xffc1) | ((insn >> 15) & 0x3e);
466 return (dxd ^ 0x8000) - 0x8000;
467 }
468
469 static uint64_t
470 insert_dxdn (uint64_t insn,
471 int64_t value,
472 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
473 const char **errmsg ATTRIBUTE_UNUSED)
474 {
475 return insert_dxd (insn, -value, dialect, errmsg);
476 }
477
478 static int64_t
479 extract_dxdn (uint64_t insn,
480 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
481 int *invalid ATTRIBUTE_UNUSED)
482 {
483 return -extract_dxd (insn, dialect, invalid);
484 }
485
486 /* FXM mask in mfcr and mtcrf instructions. */
487
488 static uint64_t
489 insert_fxm (uint64_t insn,
490 int64_t value,
491 ppc_cpu_t dialect,
492 const char **errmsg)
493 {
494 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
495 one bit of the mask field is set. */
496 if ((insn & (1 << 20)) != 0)
497 {
498 if (value == 0 || (value & -value) != value)
499 {
500 *errmsg = _("invalid mask field");
501 value = 0;
502 }
503 }
504
505 /* If only one bit of the FXM field is set, we can use the new form
506 of the instruction, which is faster. Unlike the Power4 branch hint
507 encoding, this is not backward compatible. Do not generate the
508 new form unless -mpower4 has been given, or -many and the two
509 operand form of mfcr was used. */
510 else if (value > 0
511 && (value & -value) == value
512 && ((dialect & PPC_OPCODE_POWER4) != 0
513 || ((dialect & PPC_OPCODE_ANY) != 0
514 && (insn & (0x3ff << 1)) == 19 << 1)))
515 insn |= 1 << 20;
516
517 /* Any other value on mfcr is an error. */
518 else if ((insn & (0x3ff << 1)) == 19 << 1)
519 {
520 /* A value of -1 means we used the one operand form of
521 mfcr which is valid. */
522 if (value != -1)
523 *errmsg = _("invalid mfcr mask");
524 value = 0;
525 }
526
527 return insn | ((value & 0xff) << 12);
528 }
529
530 static int64_t
531 extract_fxm (uint64_t insn,
532 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
533 int *invalid)
534 {
535 int64_t mask = (insn >> 12) & 0xff;
536
537 /* Is this a Power4 insn? */
538 if ((insn & (1 << 20)) != 0)
539 {
540 /* Exactly one bit of MASK should be set. */
541 if (mask == 0 || (mask & -mask) != mask)
542 *invalid = 1;
543 }
544
545 /* Check that non-power4 form of mfcr has a zero MASK. */
546 else if ((insn & (0x3ff << 1)) == 19 << 1)
547 {
548 if (mask != 0)
549 *invalid = 1;
550 else
551 mask = -1;
552 }
553
554 return mask;
555 }
556
557 static uint64_t
558 insert_li20 (uint64_t insn,
559 int64_t value,
560 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
561 const char **errmsg ATTRIBUTE_UNUSED)
562 {
563 return (insn
564 | ((value & 0xf0000) >> 5)
565 | ((value & 0x0f800) << 5)
566 | (value & 0x7ff));
567 }
568
569 static int64_t
570 extract_li20 (uint64_t insn,
571 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
572 int *invalid ATTRIBUTE_UNUSED)
573 {
574 return ((((insn << 5) & 0xf0000)
575 | ((insn >> 5) & 0xf800)
576 | (insn & 0x7ff)) ^ 0x80000) - 0x80000;
577 }
578
579 /* The 2-bit L field in a SYNC or WC field in a WAIT instruction.
580 For SYNC, some L values are reserved:
581 * Value 3 is reserved on newer server cpus.
582 * Values 2 and 3 are reserved on all other cpus. */
583
584 static uint64_t
585 insert_ls (uint64_t insn,
586 int64_t value,
587 ppc_cpu_t dialect,
588 const char **errmsg)
589 {
590 /* For SYNC, some L values are illegal. */
591 if (((insn >> 1) & 0x3ff) == 598)
592 {
593 int64_t max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1;
594 if (value > max_lvalue)
595 {
596 *errmsg = _("illegal L operand value");
597 return insn;
598 }
599 }
600
601 return insn | ((value & 0x3) << 21);
602 }
603
604 static int64_t
605 extract_ls (uint64_t insn,
606 ppc_cpu_t dialect,
607 int *invalid)
608 {
609 uint64_t lvalue = (insn >> 21) & 3;
610
611 if (((insn >> 1) & 0x3ff) == 598)
612 {
613 uint64_t max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1;
614 if (lvalue > max_lvalue)
615 *invalid = 1;
616 }
617 return lvalue;
618 }
619
620 /* The 4-bit E field in a sync instruction that accepts 2 operands.
621 If ESYNC is non-zero, then the L field must be either 0 or 1 and
622 the complement of ESYNC-bit2. */
623
624 static uint64_t
625 insert_esync (uint64_t insn,
626 int64_t value,
627 ppc_cpu_t dialect,
628 const char **errmsg)
629 {
630 uint64_t ls = (insn >> 21) & 0x03;
631
632 if (value == 0)
633 {
634 if (((dialect & PPC_OPCODE_E6500) != 0 && ls > 1)
635 || ((dialect & PPC_OPCODE_POWER9) != 0 && ls > 2))
636 *errmsg = _("illegal L operand value");
637 return insn;
638 }
639
640 if ((ls & ~0x1)
641 || (((value >> 1) & 0x1) ^ ls) == 0)
642 *errmsg = _("incompatible L operand value");
643
644 return insn | ((value & 0xf) << 16);
645 }
646
647 static int64_t
648 extract_esync (uint64_t insn,
649 ppc_cpu_t dialect,
650 int *invalid)
651 {
652 uint64_t ls = (insn >> 21) & 0x3;
653 uint64_t lvalue = (insn >> 16) & 0xf;
654
655 if (lvalue == 0)
656 {
657 if (((dialect & PPC_OPCODE_E6500) != 0 && ls > 1)
658 || ((dialect & PPC_OPCODE_POWER9) != 0 && ls > 2))
659 *invalid = 1;
660 }
661 else if ((ls & ~0x1)
662 || (((lvalue >> 1) & 0x1) ^ ls) == 0)
663 *invalid = 1;
664
665 return lvalue;
666 }
667
668 /* The MB and ME fields in an M form instruction expressed as a single
669 operand which is itself a bitmask. The extraction function always
670 marks it as invalid, since we never want to recognize an
671 instruction which uses a field of this type. */
672
673 static uint64_t
674 insert_mbe (uint64_t insn,
675 int64_t value,
676 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
677 const char **errmsg)
678 {
679 uint64_t uval, mask;
680 long mb, me, mx, count, last;
681
682 uval = value;
683
684 if (uval == 0)
685 {
686 *errmsg = _("illegal bitmask");
687 return insn;
688 }
689
690 mb = 0;
691 me = 32;
692 if ((uval & 1) != 0)
693 last = 1;
694 else
695 last = 0;
696 count = 0;
697
698 /* mb: location of last 0->1 transition */
699 /* me: location of last 1->0 transition */
700 /* count: # transitions */
701
702 for (mx = 0, mask = (uint64_t) 1 << 31; mx < 32; ++mx, mask >>= 1)
703 {
704 if ((uval & mask) && !last)
705 {
706 ++count;
707 mb = mx;
708 last = 1;
709 }
710 else if (!(uval & mask) && last)
711 {
712 ++count;
713 me = mx;
714 last = 0;
715 }
716 }
717 if (me == 0)
718 me = 32;
719
720 if (count != 2 && (count != 0 || ! last))
721 *errmsg = _("illegal bitmask");
722
723 return insn | (mb << 6) | ((me - 1) << 1);
724 }
725
726 static int64_t
727 extract_mbe (uint64_t insn,
728 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
729 int *invalid)
730 {
731 int64_t ret;
732 long mb, me;
733 long i;
734
735 *invalid = 1;
736
737 mb = (insn >> 6) & 0x1f;
738 me = (insn >> 1) & 0x1f;
739 if (mb < me + 1)
740 {
741 ret = 0;
742 for (i = mb; i <= me; i++)
743 ret |= (uint64_t) 1 << (31 - i);
744 }
745 else if (mb == me + 1)
746 ret = ~0;
747 else /* (mb > me + 1) */
748 {
749 ret = ~0;
750 for (i = me + 1; i < mb; i++)
751 ret &= ~((uint64_t) 1 << (31 - i));
752 }
753 return ret;
754 }
755
756 /* The MB or ME field in an MD or MDS form instruction. The high bit
757 is wrapped to the low end. */
758
759 static uint64_t
760 insert_mb6 (uint64_t insn,
761 int64_t value,
762 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
763 const char **errmsg ATTRIBUTE_UNUSED)
764 {
765 return insn | ((value & 0x1f) << 6) | (value & 0x20);
766 }
767
768 static int64_t
769 extract_mb6 (uint64_t insn,
770 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
771 int *invalid ATTRIBUTE_UNUSED)
772 {
773 return ((insn >> 6) & 0x1f) | (insn & 0x20);
774 }
775
776 /* The NB field in an X form instruction. The value 32 is stored as
777 0. */
778
779 static int64_t
780 extract_nb (uint64_t insn,
781 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
782 int *invalid ATTRIBUTE_UNUSED)
783 {
784 int64_t ret;
785
786 ret = (insn >> 11) & 0x1f;
787 if (ret == 0)
788 ret = 32;
789 return ret;
790 }
791
792 /* The NB field in an lswi instruction, which has special value
793 restrictions. The value 32 is stored as 0. */
794
795 static uint64_t
796 insert_nbi (uint64_t insn,
797 int64_t value,
798 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
799 const char **errmsg ATTRIBUTE_UNUSED)
800 {
801 int64_t rtvalue = (insn >> 21) & 0x1f;
802 int64_t ravalue = (insn >> 16) & 0x1f;
803
804 if (value == 0)
805 value = 32;
806 if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32
807 : ravalue))
808 *errmsg = _("address register in load range");
809 return insn | ((value & 0x1f) << 11);
810 }
811
812 /* The NSI field in a D form instruction. This is the same as the SI
813 field, only negated. The extraction function always marks it as
814 invalid, since we never want to recognize an instruction which uses
815 a field of this type. */
816
817 static uint64_t
818 insert_nsi (uint64_t insn,
819 int64_t value,
820 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
821 const char **errmsg ATTRIBUTE_UNUSED)
822 {
823 return insn | (-value & 0xffff);
824 }
825
826 static int64_t
827 extract_nsi (uint64_t insn,
828 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
829 int *invalid)
830 {
831 *invalid = 1;
832 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
833 }
834
835 /* The RA field in a D or X form instruction which is an updating
836 load, which means that the RA field may not be zero and may not
837 equal the RT field. */
838
839 static uint64_t
840 insert_ral (uint64_t insn,
841 int64_t value,
842 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
843 const char **errmsg)
844 {
845 if (value == 0
846 || (uint64_t) value == ((insn >> 21) & 0x1f))
847 *errmsg = "invalid register operand when updating";
848 return insn | ((value & 0x1f) << 16);
849 }
850
851 static int64_t
852 extract_ral (uint64_t insn,
853 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
854 int *invalid)
855 {
856 int64_t rtvalue = (insn >> 21) & 0x1f;
857 int64_t ravalue = (insn >> 16) & 0x1f;
858
859 if (rtvalue == ravalue || ravalue == 0)
860 *invalid = 1;
861 return ravalue;
862 }
863
864 /* The RA field in an lmw instruction, which has special value
865 restrictions. */
866
867 static uint64_t
868 insert_ram (uint64_t insn,
869 int64_t value,
870 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
871 const char **errmsg)
872 {
873 if ((uint64_t) value >= ((insn >> 21) & 0x1f))
874 *errmsg = _("index register in load range");
875 return insn | ((value & 0x1f) << 16);
876 }
877
878 static int64_t
879 extract_ram (uint64_t insn,
880 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
881 int *invalid)
882 {
883 uint64_t rtvalue = (insn >> 21) & 0x1f;
884 uint64_t ravalue = (insn >> 16) & 0x1f;
885
886 if (ravalue >= rtvalue)
887 *invalid = 1;
888 return ravalue;
889 }
890
891 /* The RA field in the DQ form lq or an lswx instruction, which have special
892 value restrictions. */
893
894 static uint64_t
895 insert_raq (uint64_t insn,
896 int64_t value,
897 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
898 const char **errmsg)
899 {
900 int64_t rtvalue = (insn >> 21) & 0x1f;
901
902 if (value == rtvalue)
903 *errmsg = _("source and target register operands must be different");
904 return insn | ((value & 0x1f) << 16);
905 }
906
907 static int64_t
908 extract_raq (uint64_t insn,
909 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
910 int *invalid)
911 {
912 uint64_t rtvalue = (insn >> 21) & 0x1f;
913 uint64_t ravalue = (insn >> 16) & 0x1f;
914
915 if (ravalue == rtvalue)
916 *invalid = 1;
917 return ravalue;
918 }
919
920 /* The RA field in a D or X form instruction which is an updating
921 store or an updating floating point load, which means that the RA
922 field may not be zero. */
923
924 static uint64_t
925 insert_ras (uint64_t insn,
926 int64_t value,
927 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
928 const char **errmsg)
929 {
930 if (value == 0)
931 *errmsg = _("invalid register operand when updating");
932 return insn | ((value & 0x1f) << 16);
933 }
934
935 static int64_t
936 extract_ras (uint64_t insn,
937 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
938 int *invalid)
939 {
940 uint64_t ravalue = (insn >> 16) & 0x1f;
941
942 if (ravalue == 0)
943 *invalid = 1;
944 return ravalue;
945 }
946
947 /* The RB field in an X form instruction when it must be the same as
948 the RS field in the instruction. This is used for extended
949 mnemonics like mr. This operand is marked FAKE. The insertion
950 function just copies the BT field into the BA field, and the
951 extraction function just checks that the fields are the same. */
952
953 static uint64_t
954 insert_rbs (uint64_t insn,
955 int64_t value ATTRIBUTE_UNUSED,
956 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
957 const char **errmsg ATTRIBUTE_UNUSED)
958 {
959 return insn | (((insn >> 21) & 0x1f) << 11);
960 }
961
962 static int64_t
963 extract_rbs (uint64_t insn,
964 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
965 int *invalid)
966 {
967 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
968 *invalid = 1;
969 return 0;
970 }
971
972 /* The RB field in an lswx instruction, which has special value
973 restrictions. */
974
975 static uint64_t
976 insert_rbx (uint64_t insn,
977 int64_t value,
978 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
979 const char **errmsg)
980 {
981 int64_t rtvalue = (insn >> 21) & 0x1f;
982
983 if (value == rtvalue)
984 *errmsg = _("source and target register operands must be different");
985 return insn | ((value & 0x1f) << 11);
986 }
987
988 static int64_t
989 extract_rbx (uint64_t insn,
990 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
991 int *invalid)
992 {
993 uint64_t rtvalue = (insn >> 21) & 0x1f;
994 uint64_t rbvalue = (insn >> 11) & 0x1f;
995
996 if (rbvalue == rtvalue)
997 *invalid = 1;
998 return rbvalue;
999 }
1000
1001 /* The SCI8 field is made up of SCL and {U,N}I8 fields. */
1002 static uint64_t
1003 insert_sci8 (uint64_t insn,
1004 int64_t value,
1005 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1006 const char **errmsg)
1007 {
1008 uint64_t fill_scale = 0;
1009 uint64_t ui8 = value;
1010
1011 if ((ui8 & 0xffffff00) == 0)
1012 ;
1013 else if ((ui8 & 0xffffff00) == 0xffffff00)
1014 fill_scale = 0x400;
1015 else if ((ui8 & 0xffff00ff) == 0)
1016 {
1017 fill_scale = 1 << 8;
1018 ui8 >>= 8;
1019 }
1020 else if ((ui8 & 0xffff00ff) == 0xffff00ff)
1021 {
1022 fill_scale = 0x400 | (1 << 8);
1023 ui8 >>= 8;
1024 }
1025 else if ((ui8 & 0xff00ffff) == 0)
1026 {
1027 fill_scale = 2 << 8;
1028 ui8 >>= 16;
1029 }
1030 else if ((ui8 & 0xff00ffff) == 0xff00ffff)
1031 {
1032 fill_scale = 0x400 | (2 << 8);
1033 ui8 >>= 16;
1034 }
1035 else if ((ui8 & 0x00ffffff) == 0)
1036 {
1037 fill_scale = 3 << 8;
1038 ui8 >>= 24;
1039 }
1040 else if ((ui8 & 0x00ffffff) == 0x00ffffff)
1041 {
1042 fill_scale = 0x400 | (3 << 8);
1043 ui8 >>= 24;
1044 }
1045 else
1046 {
1047 *errmsg = _("illegal immediate value");
1048 ui8 = 0;
1049 }
1050
1051 return insn | fill_scale | (ui8 & 0xff);
1052 }
1053
1054 static int64_t
1055 extract_sci8 (uint64_t insn,
1056 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1057 int *invalid ATTRIBUTE_UNUSED)
1058 {
1059 int64_t fill = insn & 0x400;
1060 int64_t scale_factor = (insn & 0x300) >> 5;
1061 int64_t value = (insn & 0xff) << scale_factor;
1062
1063 if (fill != 0)
1064 value |= ~((int64_t) 0xff << scale_factor);
1065 return value;
1066 }
1067
1068 static uint64_t
1069 insert_sci8n (uint64_t insn,
1070 int64_t value,
1071 ppc_cpu_t dialect,
1072 const char **errmsg)
1073 {
1074 return insert_sci8 (insn, -value, dialect, errmsg);
1075 }
1076
1077 static int64_t
1078 extract_sci8n (uint64_t insn,
1079 ppc_cpu_t dialect,
1080 int *invalid)
1081 {
1082 return -extract_sci8 (insn, dialect, invalid);
1083 }
1084
1085 static uint64_t
1086 insert_sd4h (uint64_t insn,
1087 int64_t value,
1088 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1089 const char **errmsg ATTRIBUTE_UNUSED)
1090 {
1091 return insn | ((value & 0x1e) << 7);
1092 }
1093
1094 static int64_t
1095 extract_sd4h (uint64_t insn,
1096 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1097 int *invalid ATTRIBUTE_UNUSED)
1098 {
1099 return ((insn >> 8) & 0xf) << 1;
1100 }
1101
1102 static uint64_t
1103 insert_sd4w (uint64_t insn,
1104 int64_t value,
1105 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1106 const char **errmsg ATTRIBUTE_UNUSED)
1107 {
1108 return insn | ((value & 0x3c) << 6);
1109 }
1110
1111 static int64_t
1112 extract_sd4w (uint64_t insn,
1113 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1114 int *invalid ATTRIBUTE_UNUSED)
1115 {
1116 return ((insn >> 8) & 0xf) << 2;
1117 }
1118
1119 static uint64_t
1120 insert_oimm (uint64_t insn,
1121 int64_t value,
1122 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1123 const char **errmsg ATTRIBUTE_UNUSED)
1124 {
1125 return insn | (((value - 1) & 0x1f) << 4);
1126 }
1127
1128 static int64_t
1129 extract_oimm (uint64_t insn,
1130 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1131 int *invalid ATTRIBUTE_UNUSED)
1132 {
1133 return ((insn >> 4) & 0x1f) + 1;
1134 }
1135
1136 /* The SH field in an MD form instruction. This is split. */
1137
1138 static uint64_t
1139 insert_sh6 (uint64_t insn,
1140 int64_t value,
1141 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1142 const char **errmsg ATTRIBUTE_UNUSED)
1143 {
1144 /* SH6 operand in the rldixor instructions. */
1145 if (PPC_OP (insn) == 4)
1146 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 5);
1147 else
1148 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1149 }
1150
1151 static int64_t
1152 extract_sh6 (uint64_t insn,
1153 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1154 int *invalid ATTRIBUTE_UNUSED)
1155 {
1156 /* SH6 operand in the rldixor instructions. */
1157 if (PPC_OP (insn) == 4)
1158 return ((insn >> 6) & 0x1f) | ((insn << 5) & 0x20);
1159 else
1160 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1161 }
1162
1163 /* The SPR field in an XFX form instruction. This is flipped--the
1164 lower 5 bits are stored in the upper 5 and vice- versa. */
1165
1166 static uint64_t
1167 insert_spr (uint64_t insn,
1168 int64_t value,
1169 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1170 const char **errmsg ATTRIBUTE_UNUSED)
1171 {
1172 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1173 }
1174
1175 static int64_t
1176 extract_spr (uint64_t insn,
1177 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1178 int *invalid ATTRIBUTE_UNUSED)
1179 {
1180 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1181 }
1182
1183 /* Some dialects have 8 SPRG registers instead of the standard 4. */
1184 #define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405)
1185
1186 static uint64_t
1187 insert_sprg (uint64_t insn,
1188 int64_t value,
1189 ppc_cpu_t dialect,
1190 const char **errmsg)
1191 {
1192 if (value > 7
1193 || (value > 3 && (dialect & ALLOW8_SPRG) == 0))
1194 *errmsg = _("invalid sprg number");
1195
1196 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1197 user mode. Anything else must use spr 272..279. */
1198 if (value <= 3 || (insn & 0x100) != 0)
1199 value |= 0x10;
1200
1201 return insn | ((value & 0x17) << 16);
1202 }
1203
1204 static int64_t
1205 extract_sprg (uint64_t insn,
1206 ppc_cpu_t dialect,
1207 int *invalid)
1208 {
1209 uint64_t val = (insn >> 16) & 0x1f;
1210
1211 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1212 If not BOOKE, 405 or VLE, then both use only 272..275. */
1213 if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0)
1214 || (val - 0x10 > 7 && (insn & 0x100) != 0)
1215 || val <= 3
1216 || (val & 8) != 0)
1217 *invalid = 1;
1218 return val & 7;
1219 }
1220
1221 /* The TBR field in an XFX instruction. This is just like SPR, but it
1222 is optional. */
1223
1224 static uint64_t
1225 insert_tbr (uint64_t insn,
1226 int64_t value,
1227 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1228 const char **errmsg)
1229 {
1230 if (value != 268 && value != 269)
1231 *errmsg = _("invalid tbr number");
1232 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1233 }
1234
1235 static int64_t
1236 extract_tbr (uint64_t insn,
1237 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1238 int *invalid)
1239 {
1240 int64_t ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1241 if (ret != 268 && ret != 269)
1242 *invalid = 1;
1243 return ret;
1244 }
1245
1246 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
1247
1248 static uint64_t
1249 insert_xt6 (uint64_t insn,
1250 int64_t value,
1251 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1252 const char **errmsg ATTRIBUTE_UNUSED)
1253 {
1254 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5);
1255 }
1256
1257 static int64_t
1258 extract_xt6 (uint64_t insn,
1259 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1260 int *invalid ATTRIBUTE_UNUSED)
1261 {
1262 return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
1263 }
1264
1265 /* The XT and XS fields in an DQ form VSX instruction. This is split. */
1266 static uint64_t
1267 insert_xtq6 (uint64_t insn,
1268 int64_t value,
1269 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1270 const char **errmsg ATTRIBUTE_UNUSED)
1271 {
1272 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 2);
1273 }
1274
1275 static int64_t
1276 extract_xtq6 (uint64_t insn,
1277 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1278 int *invalid ATTRIBUTE_UNUSED)
1279 {
1280 return ((insn << 2) & 0x20) | ((insn >> 21) & 0x1f);
1281 }
1282
1283 /* The XA field in an XX3 form instruction. This is split. */
1284
1285 static uint64_t
1286 insert_xa6 (uint64_t insn,
1287 int64_t value,
1288 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1289 const char **errmsg ATTRIBUTE_UNUSED)
1290 {
1291 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3);
1292 }
1293
1294 static int64_t
1295 extract_xa6 (uint64_t insn,
1296 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1297 int *invalid ATTRIBUTE_UNUSED)
1298 {
1299 return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
1300 }
1301
1302 /* The XB field in an XX3 form instruction. This is split. */
1303
1304 static uint64_t
1305 insert_xb6 (uint64_t insn,
1306 int64_t value,
1307 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1308 const char **errmsg ATTRIBUTE_UNUSED)
1309 {
1310 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1311 }
1312
1313 static int64_t
1314 extract_xb6 (uint64_t insn,
1315 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1316 int *invalid ATTRIBUTE_UNUSED)
1317 {
1318 return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f);
1319 }
1320
1321 /* The XB field in an XX3 form instruction when it must be the same as
1322 the XA field in the instruction. This is used for extended
1323 mnemonics like xvmovdp. This operand is marked FAKE. The insertion
1324 function just copies the XA field into the XB field, and the
1325 extraction function just checks that the fields are the same. */
1326
1327 static uint64_t
1328 insert_xb6s (uint64_t insn,
1329 int64_t value ATTRIBUTE_UNUSED,
1330 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1331 const char **errmsg ATTRIBUTE_UNUSED)
1332 {
1333 return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1);
1334 }
1335
1336 static int64_t
1337 extract_xb6s (uint64_t insn,
1338 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1339 int *invalid)
1340 {
1341 if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
1342 || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1)))
1343 *invalid = 1;
1344 return 0;
1345 }
1346
1347 /* The XC field in an XX4 form instruction. This is split. */
1348
1349 static uint64_t
1350 insert_xc6 (uint64_t insn,
1351 int64_t value,
1352 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1353 const char **errmsg ATTRIBUTE_UNUSED)
1354 {
1355 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2);
1356 }
1357
1358 static int64_t
1359 extract_xc6 (uint64_t insn,
1360 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1361 int *invalid ATTRIBUTE_UNUSED)
1362 {
1363 return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f);
1364 }
1365
1366 static uint64_t
1367 insert_dm (uint64_t insn,
1368 int64_t value,
1369 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1370 const char **errmsg)
1371 {
1372 if (value != 0 && value != 1)
1373 *errmsg = _("invalid constant");
1374 return insn | (((value) ? 3 : 0) << 8);
1375 }
1376
1377 static int64_t
1378 extract_dm (uint64_t insn,
1379 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1380 int *invalid)
1381 {
1382 int64_t value = (insn >> 8) & 3;
1383 if (value != 0 && value != 3)
1384 *invalid = 1;
1385 return (value) ? 1 : 0;
1386 }
1387
1388 /* The VLESIMM field in an I16A form instruction. This is split. */
1389
1390 static uint64_t
1391 insert_vlesi (uint64_t insn,
1392 int64_t value,
1393 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1394 const char **errmsg ATTRIBUTE_UNUSED)
1395 {
1396 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
1397 }
1398
1399 static int64_t
1400 extract_vlesi (uint64_t insn,
1401 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1402 int *invalid ATTRIBUTE_UNUSED)
1403 {
1404 int64_t value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
1405 value = (value ^ 0x8000) - 0x8000;
1406 return value;
1407 }
1408
1409 static uint64_t
1410 insert_vlensi (uint64_t insn,
1411 int64_t value,
1412 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1413 const char **errmsg ATTRIBUTE_UNUSED)
1414 {
1415 value = -value;
1416 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
1417 }
1418 static int64_t
1419 extract_vlensi (uint64_t insn,
1420 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1421 int *invalid ATTRIBUTE_UNUSED)
1422 {
1423 int64_t value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
1424 value = (value ^ 0x8000) - 0x8000;
1425 /* Don't use for disassembly. */
1426 *invalid = 1;
1427 return -value;
1428 }
1429
1430 /* The VLEUIMM field in an I16A form instruction. This is split. */
1431
1432 static uint64_t
1433 insert_vleui (uint64_t insn,
1434 int64_t value,
1435 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1436 const char **errmsg ATTRIBUTE_UNUSED)
1437 {
1438 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
1439 }
1440
1441 static int64_t
1442 extract_vleui (uint64_t insn,
1443 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1444 int *invalid ATTRIBUTE_UNUSED)
1445 {
1446 return ((insn >> 10) & 0xf800) | (insn & 0x7ff);
1447 }
1448
1449 /* The VLEUIMML field in an I16L form instruction. This is split. */
1450
1451 static uint64_t
1452 insert_vleil (uint64_t insn,
1453 int64_t value,
1454 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1455 const char **errmsg ATTRIBUTE_UNUSED)
1456 {
1457 return insn | ((value & 0xf800) << 5) | (value & 0x7ff);
1458 }
1459
1460 static int64_t
1461 extract_vleil (uint64_t insn,
1462 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1463 int *invalid ATTRIBUTE_UNUSED)
1464 {
1465 return ((insn >> 5) & 0xf800) | (insn & 0x7ff);
1466 }
1467
1468 static uint64_t
1469 insert_evuimm1_ex0 (uint64_t insn,
1470 int64_t value,
1471 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1472 const char **errmsg)
1473 {
1474 if (value > 0 && value <= 0x1f)
1475 return insn | ((value & 0x1f) << 11);
1476 else
1477 {
1478 *errmsg = _("UIMM = 00000 is illegal");
1479 return 0;
1480 }
1481 }
1482
1483 static int64_t
1484 extract_evuimm1_ex0 (uint64_t insn,
1485 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1486 int *invalid)
1487 {
1488 int64_t value = ((insn >> 11) & 0x1f);
1489 if (value == 0)
1490 *invalid = 1;
1491
1492 return value;
1493 }
1494
1495 static uint64_t
1496 insert_evuimm2_ex0 (uint64_t insn,
1497 int64_t value,
1498 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1499 const char **errmsg)
1500 {
1501 if (value > 0 && value <= 0x3e)
1502 return insn | ((value & 0x3e) << 10);
1503 else
1504 {
1505 *errmsg = _("UIMM = 00000 is illegal");
1506 return 0;
1507 }
1508 }
1509
1510 static int64_t
1511 extract_evuimm2_ex0 (uint64_t insn,
1512 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1513 int *invalid)
1514 {
1515 int64_t value = ((insn >> 10) & 0x3e);
1516 if (value == 0)
1517 *invalid = 1;
1518
1519 return value;
1520 }
1521
1522 static uint64_t
1523 insert_evuimm4_ex0 (uint64_t insn,
1524 int64_t value,
1525 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1526 const char **errmsg)
1527 {
1528 if (value > 0 && value <= 0x7c)
1529 return insn | ((value & 0x7c) << 9);
1530 else
1531 {
1532 *errmsg = _("UIMM = 00000 is illegal");
1533 return 0;
1534 }
1535 }
1536
1537 static int64_t
1538 extract_evuimm4_ex0 (uint64_t insn,
1539 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1540 int *invalid)
1541 {
1542 int64_t value = ((insn >> 9) & 0x7c);
1543 if (value == 0)
1544 *invalid = 1;
1545
1546 return value;
1547 }
1548
1549 static uint64_t
1550 insert_evuimm8_ex0 (uint64_t insn,
1551 int64_t value,
1552 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1553 const char **errmsg)
1554 {
1555 if (value > 0 && value <= 0xf8)
1556 return insn | ((value & 0xf8) << 8);
1557 else
1558 {
1559 *errmsg = _("UIMM = 00000 is illegal");
1560 return 0;
1561 }
1562 }
1563
1564 static int64_t
1565 extract_evuimm8_ex0 (uint64_t insn,
1566 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1567 int *invalid)
1568 {
1569 int64_t value = ((insn >> 8) & 0xf8);
1570 if (value == 0)
1571 *invalid = 1;
1572
1573 return value;
1574 }
1575
1576 static uint64_t
1577 insert_evuimm_lt8 (uint64_t insn,
1578 int64_t value,
1579 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1580 const char **errmsg)
1581 {
1582 if (value >= 0 && value <= 7)
1583 return insn | ((value & 0x7) << 11);
1584 else
1585 {
1586 *errmsg = _("UIMM values >7 are illegal");
1587 return 0;
1588 }
1589 }
1590
1591 static int64_t
1592 extract_evuimm_lt8 (uint64_t insn,
1593 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1594 int *invalid)
1595 {
1596 int64_t value = ((insn >> 11) & 0x1f);
1597 if (value > 7)
1598 *invalid = 1;
1599
1600 return value;
1601 }
1602
1603 static uint64_t
1604 insert_evuimm_lt16 (uint64_t insn,
1605 int64_t value,
1606 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1607 const char **errmsg)
1608 {
1609 if (value >= 0 && value <= 15)
1610 return insn | ((value & 0xf) << 11);
1611 else
1612 {
1613 *errmsg = _("UIMM values >15 are illegal");
1614 return 0;
1615 }
1616 }
1617
1618 static int64_t
1619 extract_evuimm_lt16 (uint64_t insn,
1620 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1621 int *invalid)
1622 {
1623 int64_t value = ((insn >> 11) & 0x1f);
1624 if (value > 15)
1625 *invalid = 1;
1626
1627 return value;
1628 }
1629
1630 static uint64_t
1631 insert_rD_rS_even (uint64_t insn,
1632 int64_t value,
1633 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1634 const char **errmsg)
1635 {
1636 if ((value & 0x1) == 0)
1637 return insn | ((value & 0x1e) << 21);
1638 else
1639 {
1640 *errmsg = _("GPR odd is illegal");
1641 return 0;
1642 }
1643 }
1644
1645 static int64_t
1646 extract_rD_rS_even (uint64_t insn,
1647 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1648 int *invalid)
1649 {
1650 int64_t value = ((insn >> 21) & 0x1f);
1651 if ((value & 0x1) != 0)
1652 *invalid = 1;
1653
1654 return value;
1655 }
1656
1657 static uint64_t
1658 insert_off_lsp (uint64_t insn,
1659 int64_t value,
1660 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1661 const char **errmsg)
1662 {
1663 if (value > 0 && value <= 0x3)
1664 return insn | (value & 0x3);
1665 else
1666 {
1667 *errmsg = _("invalid offset");
1668 return 0;
1669 }
1670 }
1671
1672 static int64_t
1673 extract_off_lsp (uint64_t insn,
1674 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1675 int *invalid)
1676 {
1677 int64_t value = (insn & 0x3);
1678 if (value == 0)
1679 *invalid = 1;
1680
1681 return value;
1682 }
1683
1684 static uint64_t
1685 insert_off_spe2 (uint64_t insn,
1686 int64_t value,
1687 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1688 const char **errmsg)
1689 {
1690 if (value > 0 && value <= 0x7)
1691 return insn | (value & 0x7);
1692 else
1693 {
1694 *errmsg = _("invalid offset");
1695 return 0;
1696 }
1697 }
1698
1699 static int64_t
1700 extract_off_spe2 (uint64_t insn,
1701 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1702 int *invalid)
1703 {
1704 int64_t value = (insn & 0x7);
1705 if (value == 0)
1706 *invalid = 1;
1707
1708 return value;
1709 }
1710
1711 static uint64_t
1712 insert_Ddd (uint64_t insn,
1713 int64_t value,
1714 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1715 const char **errmsg)
1716 {
1717 if (value >= 0 && value <= 0x7)
1718 return insn | ((value & 0x3) << 11) | ((value & 0x4) >> 2);
1719 else
1720 {
1721 *errmsg = _("invalid Ddd value");
1722 return 0;
1723 }
1724 }
1725
1726 static int64_t
1727 extract_Ddd (uint64_t insn,
1728 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1729 int *invalid ATTRIBUTE_UNUSED)
1730 {
1731 return ((insn >> 11) & 0x3) | ((insn << 2) & 0x4);
1732 }
1733 \f
1734 /* The operands table.
1735
1736 The fields are bitm, shift, insert, extract, flags.
1737
1738 We used to put parens around the various additions, like the one
1739 for BA just below. However, that caused trouble with feeble
1740 compilers with a limit on depth of a parenthesized expression, like
1741 (reportedly) the compiler in Microsoft Developer Studio 5. So we
1742 omit the parens, since the macros are never used in a context where
1743 the addition will be ambiguous. */
1744
1745 const struct powerpc_operand powerpc_operands[] =
1746 {
1747 /* The zero index is used to indicate the end of the list of
1748 operands. */
1749 #define UNUSED 0
1750 { 0, 0, NULL, NULL, 0 },
1751
1752 /* The BA field in an XL form instruction. */
1753 #define BA UNUSED + 1
1754 /* The BI field in a B form or XL form instruction. */
1755 #define BI BA
1756 #define BI_MASK (0x1f << 16)
1757 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
1758
1759 /* The BA field in an XL form instruction when it must be the same
1760 as the BT field in the same instruction. */
1761 #define BAT BA + 1
1762 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
1763
1764 /* The BB field in an XL form instruction. */
1765 #define BB BAT + 1
1766 #define BB_MASK (0x1f << 11)
1767 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT },
1768
1769 /* The BB field in an XL form instruction when it must be the same
1770 as the BA field in the same instruction. */
1771 #define BBA BB + 1
1772 /* The VB field in a VX form instruction when it must be the same
1773 as the VA field in the same instruction. */
1774 #define VBA BBA
1775 { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
1776
1777 /* The BD field in a B form instruction. The lower two bits are
1778 forced to zero. */
1779 #define BD BBA + 1
1780 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
1781
1782 /* The BD field in a B form instruction when absolute addressing is
1783 used. */
1784 #define BDA BD + 1
1785 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
1786
1787 /* The BD field in a B form instruction when the - modifier is used.
1788 This sets the y bit of the BO field appropriately. */
1789 #define BDM BDA + 1
1790 { 0xfffc, 0, insert_bdm, extract_bdm,
1791 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
1792
1793 /* The BD field in a B form instruction when the - modifier is used
1794 and absolute address is used. */
1795 #define BDMA BDM + 1
1796 { 0xfffc, 0, insert_bdm, extract_bdm,
1797 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
1798
1799 /* The BD field in a B form instruction when the + modifier is used.
1800 This sets the y bit of the BO field appropriately. */
1801 #define BDP BDMA + 1
1802 { 0xfffc, 0, insert_bdp, extract_bdp,
1803 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
1804
1805 /* The BD field in a B form instruction when the + modifier is used
1806 and absolute addressing is used. */
1807 #define BDPA BDP + 1
1808 { 0xfffc, 0, insert_bdp, extract_bdp,
1809 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
1810
1811 /* The BF field in an X or XL form instruction. */
1812 #define BF BDPA + 1
1813 /* The CRFD field in an X form instruction. */
1814 #define CRFD BF
1815 /* The CRD field in an XL form instruction. */
1816 #define CRD BF
1817 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG },
1818
1819 /* The BF field in an X or XL form instruction. */
1820 #define BFF BF + 1
1821 { 0x7, 23, NULL, NULL, 0 },
1822
1823 /* An optional BF field. This is used for comparison instructions,
1824 in which an omitted BF field is taken as zero. */
1825 #define OBF BFF + 1
1826 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
1827
1828 /* The BFA field in an X or XL form instruction. */
1829 #define BFA OBF + 1
1830 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG },
1831
1832 /* The BO field in a B form instruction. Certain values are
1833 illegal. */
1834 #define BO BFA + 1
1835 #define BO_MASK (0x1f << 21)
1836 { 0x1f, 21, insert_bo, extract_bo, 0 },
1837
1838 /* The BO field in a B form instruction when the + or - modifier is
1839 used. This is like the BO field, but it must be even. */
1840 #define BOE BO + 1
1841 { 0x1e, 21, insert_boe, extract_boe, 0 },
1842
1843 /* The RM field in an X form instruction. */
1844 #define RM BOE + 1
1845 #define DD RM
1846 { 0x3, 11, NULL, NULL, 0 },
1847
1848 #define BH RM + 1
1849 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
1850
1851 /* The BT field in an X or XL form instruction. */
1852 #define BT BH + 1
1853 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT },
1854
1855 /* The BI16 field in a BD8 form instruction. */
1856 #define BI16 BT + 1
1857 { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT },
1858
1859 /* The BI32 field in a BD15 form instruction. */
1860 #define BI32 BI16 + 1
1861 { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
1862
1863 /* The BO32 field in a BD15 form instruction. */
1864 #define BO32 BI32 + 1
1865 { 0x3, 20, NULL, NULL, 0 },
1866
1867 /* The B8 field in a BD8 form instruction. */
1868 #define B8 BO32 + 1
1869 { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
1870
1871 /* The B15 field in a BD15 form instruction. The lowest bit is
1872 forced to zero. */
1873 #define B15 B8 + 1
1874 { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
1875
1876 /* The B24 field in a BD24 form instruction. The lowest bit is
1877 forced to zero. */
1878 #define B24 B15 + 1
1879 { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
1880
1881 /* The condition register number portion of the BI field in a B form
1882 or XL form instruction. This is used for the extended
1883 conditional branch mnemonics, which set the lower two bits of the
1884 BI field. This field is optional. */
1885 #define CR B24 + 1
1886 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
1887
1888 /* The CRB field in an X form instruction. */
1889 #define CRB CR + 1
1890 /* The MB field in an M form instruction. */
1891 #define MB CRB
1892 #define MB_MASK (0x1f << 6)
1893 { 0x1f, 6, NULL, NULL, 0 },
1894
1895 /* The CRD32 field in an XL form instruction. */
1896 #define CRD32 CRB + 1
1897 { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG },
1898
1899 /* The CRFS field in an X form instruction. */
1900 #define CRFS CRD32 + 1
1901 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG },
1902
1903 #define CRS CRFS + 1
1904 { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
1905
1906 /* The CT field in an X form instruction. */
1907 #define CT CRS + 1
1908 /* The MO field in an mbar instruction. */
1909 #define MO CT
1910 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
1911
1912 /* The D field in a D form instruction. This is a displacement off
1913 a register, and implies that the next operand is a register in
1914 parentheses. */
1915 #define D CT + 1
1916 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
1917
1918 /* The D8 field in a D form instruction. This is a displacement off
1919 a register, and implies that the next operand is a register in
1920 parentheses. */
1921 #define D8 D + 1
1922 { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
1923
1924 /* The DCMX field in an X form instruction. */
1925 #define DCMX D8 + 1
1926 { 0x7f, 16, NULL, NULL, 0 },
1927
1928 /* The split DCMX field in an X form instruction. */
1929 #define DCMXS DCMX + 1
1930 { 0x7f, PPC_OPSHIFT_INV, insert_dcmxs, extract_dcmxs, 0 },
1931
1932 /* The DQ field in a DQ form instruction. This is like D, but the
1933 lower four bits are forced to zero. */
1934 #define DQ DCMXS + 1
1935 { 0xfff0, 0, NULL, NULL,
1936 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
1937
1938 /* The DS field in a DS form instruction. This is like D, but the
1939 lower two bits are forced to zero. */
1940 #define DS DQ + 1
1941 { 0xfffc, 0, NULL, NULL,
1942 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
1943
1944 /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits
1945 unsigned imediate */
1946 #define DUIS DS + 1
1947 #define BHRBE DUIS
1948 { 0x3ff, 11, NULL, NULL, 0 },
1949
1950 /* The split D field in a DX form instruction. */
1951 #define DXD DUIS + 1
1952 { 0xffff, PPC_OPSHIFT_INV, insert_dxd, extract_dxd,
1953 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
1954
1955 /* The split ND field in a DX form instruction.
1956 This is the same as the DX field, only negated. */
1957 #define NDXD DXD + 1
1958 { 0xffff, PPC_OPSHIFT_INV, insert_dxdn, extract_dxdn,
1959 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
1960
1961 /* The E field in a wrteei instruction. */
1962 /* And the W bit in the pair singles instructions. */
1963 /* And the ST field in a VX form instruction. */
1964 #define E NDXD + 1
1965 #define PSW E
1966 #define ST E
1967 { 0x1, 15, NULL, NULL, 0 },
1968
1969 /* The FL1 field in a POWER SC form instruction. */
1970 #define FL1 E + 1
1971 /* The U field in an X form instruction. */
1972 #define U FL1
1973 { 0xf, 12, NULL, NULL, 0 },
1974
1975 /* The FL2 field in a POWER SC form instruction. */
1976 #define FL2 FL1 + 1
1977 { 0x7, 2, NULL, NULL, 0 },
1978
1979 /* The FLM field in an XFL form instruction. */
1980 #define FLM FL2 + 1
1981 { 0xff, 17, NULL, NULL, 0 },
1982
1983 /* The FRA field in an X or A form instruction. */
1984 #define FRA FLM + 1
1985 #define FRA_MASK (0x1f << 16)
1986 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
1987
1988 /* The FRAp field of DFP instructions. */
1989 #define FRAp FRA + 1
1990 { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR },
1991
1992 /* The FRB field in an X or A form instruction. */
1993 #define FRB FRAp + 1
1994 #define FRB_MASK (0x1f << 11)
1995 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
1996
1997 /* The FRBp field of DFP instructions. */
1998 #define FRBp FRB + 1
1999 { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR },
2000
2001 /* The FRC field in an A form instruction. */
2002 #define FRC FRBp + 1
2003 #define FRC_MASK (0x1f << 6)
2004 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
2005
2006 /* The FRS field in an X form instruction or the FRT field in a D, X
2007 or A form instruction. */
2008 #define FRS FRC + 1
2009 #define FRT FRS
2010 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
2011
2012 /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
2013 instructions. */
2014 #define FRSp FRS + 1
2015 #define FRTp FRSp
2016 { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR },
2017
2018 /* The FXM field in an XFX instruction. */
2019 #define FXM FRSp + 1
2020 { 0xff, 12, insert_fxm, extract_fxm, 0 },
2021
2022 /* Power4 version for mfcr. */
2023 #define FXM4 FXM + 1
2024 { 0xff, 12, insert_fxm, extract_fxm,
2025 PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
2026 /* If the FXM4 operand is ommitted, use the sentinel value -1. */
2027 { -1, -1, NULL, NULL, 0},
2028
2029 /* The IMM20 field in an LI instruction. */
2030 #define IMM20 FXM4 + 2
2031 { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED},
2032
2033 /* The L field in a D or X form instruction. */
2034 #define L IMM20 + 1
2035 { 0x1, 21, NULL, NULL, 0 },
2036
2037 /* The optional L field in tlbie and tlbiel instructions. */
2038 #define LOPT L + 1
2039 /* The R field in a HTM X form instruction. */
2040 #define HTM_R LOPT
2041 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
2042
2043 /* The optional (for 32-bit) L field in cmp[l][i] instructions. */
2044 #define L32OPT LOPT + 1
2045 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL32 },
2046
2047 /* The L field in dcbf instruction. */
2048 #define L2OPT L32OPT + 1
2049 { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
2050
2051 /* The LEV field in a POWER SVC / POWER9 SCV form instruction. */
2052 #define SVC_LEV L2OPT + 1
2053 { 0x7f, 5, NULL, NULL, 0 },
2054
2055 /* The LEV field in an SC form instruction. */
2056 #define LEV SVC_LEV + 1
2057 { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
2058
2059 /* The LI field in an I form instruction. The lower two bits are
2060 forced to zero. */
2061 #define LI LEV + 1
2062 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
2063
2064 /* The LI field in an I form instruction when used as an absolute
2065 address. */
2066 #define LIA LI + 1
2067 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
2068
2069 /* The LS or WC field in an X (sync or wait) form instruction. */
2070 #define LS LIA + 1
2071 #define WC LS
2072 { 0x3, 21, insert_ls, extract_ls, PPC_OPERAND_OPTIONAL },
2073
2074 /* The ME field in an M form instruction. */
2075 #define ME LS + 1
2076 #define ME_MASK (0x1f << 1)
2077 { 0x1f, 1, NULL, NULL, 0 },
2078
2079 /* The MB and ME fields in an M form instruction expressed a single
2080 operand which is a bitmask indicating which bits to select. This
2081 is a two operand form using PPC_OPERAND_NEXT. See the
2082 description in opcode/ppc.h for what this means. */
2083 #define MBE ME + 1
2084 { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
2085 { -1, 0, insert_mbe, extract_mbe, 0 },
2086
2087 /* The MB or ME field in an MD or MDS form instruction. The high
2088 bit is wrapped to the low end. */
2089 #define MB6 MBE + 2
2090 #define ME6 MB6
2091 #define MB6_MASK (0x3f << 5)
2092 { 0x3f, 5, insert_mb6, extract_mb6, 0 },
2093
2094 /* The NB field in an X form instruction. The value 32 is stored as
2095 0. */
2096 #define NB MB6 + 1
2097 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
2098
2099 /* The NBI field in an lswi instruction, which has special value
2100 restrictions. The value 32 is stored as 0. */
2101 #define NBI NB + 1
2102 { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 },
2103
2104 /* The NSI field in a D form instruction. This is the same as the
2105 SI field, only negated. */
2106 #define NSI NBI + 1
2107 { 0xffff, 0, insert_nsi, extract_nsi,
2108 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
2109
2110 /* The NSI field in a D form instruction when we accept a wide range
2111 of positive values. */
2112 #define NSISIGNOPT NSI + 1
2113 { 0xffff, 0, insert_nsi, extract_nsi,
2114 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
2115
2116 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
2117 #define RA NSISIGNOPT + 1
2118 #define RA_MASK (0x1f << 16)
2119 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
2120
2121 /* As above, but 0 in the RA field means zero, not r0. */
2122 #define RA0 RA + 1
2123 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
2124
2125 /* The RA field in the DQ form lq or an lswx instruction, which have
2126 special value restrictions. */
2127 #define RAQ RA0 + 1
2128 #define RAX RAQ
2129 { 0x1f, 16, insert_raq, extract_raq, PPC_OPERAND_GPR_0 },
2130
2131 /* The RA field in a D or X form instruction which is an updating
2132 load, which means that the RA field may not be zero and may not
2133 equal the RT field. */
2134 #define RAL RAQ + 1
2135 { 0x1f, 16, insert_ral, extract_ral, PPC_OPERAND_GPR_0 },
2136
2137 /* The RA field in an lmw instruction, which has special value
2138 restrictions. */
2139 #define RAM RAL + 1
2140 { 0x1f, 16, insert_ram, extract_ram, PPC_OPERAND_GPR_0 },
2141
2142 /* The RA field in a D or X form instruction which is an updating
2143 store or an updating floating point load, which means that the RA
2144 field may not be zero. */
2145 #define RAS RAM + 1
2146 { 0x1f, 16, insert_ras, extract_ras, PPC_OPERAND_GPR_0 },
2147
2148 /* The RA field of the tlbwe, dccci and iccci instructions,
2149 which are optional. */
2150 #define RAOPT RAS + 1
2151 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
2152
2153 /* The RB field in an X, XO, M, or MDS form instruction. */
2154 #define RB RAOPT + 1
2155 #define RB_MASK (0x1f << 11)
2156 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
2157
2158 /* The RB field in an X form instruction when it must be the same as
2159 the RS field in the instruction. This is used for extended
2160 mnemonics like mr. */
2161 #define RBS RB + 1
2162 { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
2163
2164 /* The RB field in an lswx instruction, which has special value
2165 restrictions. */
2166 #define RBX RBS + 1
2167 { 0x1f, 11, insert_rbx, extract_rbx, PPC_OPERAND_GPR },
2168
2169 /* The RB field of the dccci and iccci instructions, which are optional. */
2170 #define RBOPT RBX + 1
2171 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
2172
2173 /* The RC register field in an maddld, maddhd or maddhdu instruction. */
2174 #define RC RBOPT + 1
2175 { 0x1f, 6, NULL, NULL, PPC_OPERAND_GPR },
2176
2177 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
2178 instruction or the RT field in a D, DS, X, XFX or XO form
2179 instruction. */
2180 #define RS RC + 1
2181 #define RT RS
2182 #define RT_MASK (0x1f << 21)
2183 #define RD RS
2184 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
2185
2186 #define RD_EVEN RS + 1
2187 #define RS_EVEN RD_EVEN
2188 { 0x1f, 21, insert_rD_rS_even, extract_rD_rS_even, PPC_OPERAND_GPR },
2189
2190 /* The RS and RT fields of the DS form stq and DQ form lq instructions,
2191 which have special value restrictions. */
2192 #define RSQ RS_EVEN + 1
2193 #define RTQ RSQ
2194 #define Q_MASK (1 << 21)
2195 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR },
2196
2197 /* The RS field of the tlbwe instruction, which is optional. */
2198 #define RSO RSQ + 1
2199 #define RTO RSO
2200 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
2201
2202 /* The RX field of the SE_RR form instruction. */
2203 #define RX RSO + 1
2204 { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR },
2205
2206 /* The ARX field of the SE_RR form instruction. */
2207 #define ARX RX + 1
2208 { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR },
2209
2210 /* The RY field of the SE_RR form instruction. */
2211 #define RY ARX + 1
2212 #define RZ RY
2213 { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR },
2214
2215 /* The ARY field of the SE_RR form instruction. */
2216 #define ARY RY + 1
2217 { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR },
2218
2219 /* The SCLSCI8 field in a D form instruction. */
2220 #define SCLSCI8 ARY + 1
2221 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 },
2222
2223 /* The SCLSCI8N field in a D form instruction. This is the same as the
2224 SCLSCI8 field, only negated. */
2225 #define SCLSCI8N SCLSCI8 + 1
2226 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n,
2227 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
2228
2229 /* The SD field of the SD4 form instruction. */
2230 #define SE_SD SCLSCI8N + 1
2231 { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS },
2232
2233 /* The SD field of the SD4 form instruction, for halfword. */
2234 #define SE_SDH SE_SD + 1
2235 { 0x1e, PPC_OPSHIFT_INV, insert_sd4h, extract_sd4h, PPC_OPERAND_PARENS },
2236
2237 /* The SD field of the SD4 form instruction, for word. */
2238 #define SE_SDW SE_SDH + 1
2239 { 0x3c, PPC_OPSHIFT_INV, insert_sd4w, extract_sd4w, PPC_OPERAND_PARENS },
2240
2241 /* The SH field in an X or M form instruction. */
2242 #define SH SE_SDW + 1
2243 #define SH_MASK (0x1f << 11)
2244 /* The other UIMM field in a EVX form instruction. */
2245 #define EVUIMM SH
2246 /* The FC field in an atomic X form instruction. */
2247 #define FC SH
2248 { 0x1f, 11, NULL, NULL, 0 },
2249
2250 #define EVUIMM_LT8 SH + 1
2251 { 0x1f, 11, insert_evuimm_lt8, extract_evuimm_lt8, 0 },
2252
2253 #define EVUIMM_LT16 EVUIMM_LT8 + 1
2254 { 0x1f, 11, insert_evuimm_lt16, extract_evuimm_lt16, 0 },
2255
2256 /* The SI field in a HTM X form instruction. */
2257 #define HTM_SI EVUIMM_LT16 + 1
2258 { 0x1f, 11, NULL, NULL, PPC_OPERAND_SIGNED },
2259
2260 /* The SH field in an MD form instruction. This is split. */
2261 #define SH6 HTM_SI + 1
2262 #define SH6_MASK ((0x1f << 11) | (1 << 1))
2263 { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 },
2264
2265 /* The SH field of some variants of the tlbre and tlbwe
2266 instructions, and the ELEV field of the e_sc instruction. */
2267 #define SHO SH6 + 1
2268 #define ELEV SHO
2269 { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
2270
2271 /* The SI field in a D form instruction. */
2272 #define SI SHO + 1
2273 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
2274
2275 /* The SI field in a D form instruction when we accept a wide range
2276 of positive values. */
2277 #define SISIGNOPT SI + 1
2278 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
2279
2280 /* The SI8 field in a D form instruction. */
2281 #define SI8 SISIGNOPT + 1
2282 { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
2283
2284 /* The SPR field in an XFX form instruction. This is flipped--the
2285 lower 5 bits are stored in the upper 5 and vice- versa. */
2286 #define SPR SI8 + 1
2287 #define PMR SPR
2288 #define TMR SPR
2289 #define SPR_MASK (0x3ff << 11)
2290 { 0x3ff, 11, insert_spr, extract_spr, PPC_OPERAND_SPR },
2291
2292 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
2293 #define SPRBAT SPR + 1
2294 #define SPRBAT_MASK (0x3 << 17)
2295 { 0x3, 17, NULL, NULL, 0 },
2296
2297 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
2298 #define SPRG SPRBAT + 1
2299 { 0x1f, 16, insert_sprg, extract_sprg, PPC_OPERAND_SPR },
2300
2301 /* The SR field in an X form instruction. */
2302 #define SR SPRG + 1
2303 /* The 4-bit UIMM field in a VX form instruction. */
2304 #define UIMM4 SR
2305 { 0xf, 16, NULL, NULL, 0 },
2306
2307 /* The STRM field in an X AltiVec form instruction. */
2308 #define STRM SR + 1
2309 /* The T field in a tlbilx form instruction. */
2310 #define T STRM
2311 /* The L field in wclr instructions. */
2312 #define L2 STRM
2313 { 0x3, 21, NULL, NULL, 0 },
2314
2315 /* The ESYNC field in an X (sync) form instruction. */
2316 #define ESYNC STRM + 1
2317 { 0xf, 16, insert_esync, extract_esync, PPC_OPERAND_OPTIONAL },
2318
2319 /* The SV field in a POWER SC form instruction. */
2320 #define SV ESYNC + 1
2321 { 0x3fff, 2, NULL, NULL, 0 },
2322
2323 /* The TBR field in an XFX form instruction. This is like the SPR
2324 field, but it is optional. */
2325 #define TBR SV + 1
2326 { 0x3ff, 11, insert_tbr, extract_tbr,
2327 PPC_OPERAND_SPR | PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
2328 /* If the TBR operand is ommitted, use the value 268. */
2329 { -1, 268, NULL, NULL, 0},
2330
2331 /* The TO field in a D or X form instruction. */
2332 #define TO TBR + 2
2333 #define DUI TO
2334 #define TO_MASK (0x1f << 21)
2335 { 0x1f, 21, NULL, NULL, 0 },
2336
2337 /* The UI field in a D form instruction. */
2338 #define UI TO + 1
2339 { 0xffff, 0, NULL, NULL, 0 },
2340
2341 #define UISIGNOPT UI + 1
2342 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNOPT },
2343
2344 /* The IMM field in an SE_IM5 instruction. */
2345 #define UI5 UISIGNOPT + 1
2346 { 0x1f, 4, NULL, NULL, 0 },
2347
2348 /* The OIMM field in an SE_OIM5 instruction. */
2349 #define OIMM5 UI5 + 1
2350 { 0x1f, PPC_OPSHIFT_INV, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 },
2351
2352 /* The UI7 field in an SE_LI instruction. */
2353 #define UI7 OIMM5 + 1
2354 { 0x7f, 4, NULL, NULL, 0 },
2355
2356 /* The VA field in a VA, VX or VXR form instruction. */
2357 #define VA UI7 + 1
2358 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
2359
2360 /* The VB field in a VA, VX or VXR form instruction. */
2361 #define VB VA + 1
2362 { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
2363
2364 /* The VC field in a VA form instruction. */
2365 #define VC VB + 1
2366 { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
2367
2368 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
2369 #define VD VC + 1
2370 #define VS VD
2371 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
2372
2373 /* The SIMM field in a VX form instruction, and TE in Z form. */
2374 #define SIMM VD + 1
2375 #define TE SIMM
2376 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
2377
2378 /* The UIMM field in a VX form instruction. */
2379 #define UIMM SIMM + 1
2380 #define DCTL UIMM
2381 { 0x1f, 16, NULL, NULL, 0 },
2382
2383 /* The 3-bit UIMM field in a VX form instruction. */
2384 #define UIMM3 UIMM + 1
2385 { 0x7, 16, NULL, NULL, 0 },
2386
2387 /* The 6-bit UIM field in a X form instruction. */
2388 #define UIM6 UIMM3 + 1
2389 { 0x3f, 16, NULL, NULL, 0 },
2390
2391 /* The SIX field in a VX form instruction. */
2392 #define SIX UIM6 + 1
2393 #define MMMM SIX
2394 { 0xf, 11, NULL, NULL, 0 },
2395
2396 /* The PS field in a VX form instruction. */
2397 #define PS SIX + 1
2398 { 0x1, 9, NULL, NULL, 0 },
2399
2400 /* The SHB field in a VA form instruction. */
2401 #define SHB PS + 1
2402 { 0xf, 6, NULL, NULL, 0 },
2403
2404 /* The other UIMM field in a half word EVX form instruction. */
2405 #define EVUIMM_1 SHB + 1
2406 { 0x1f, 11, NULL, NULL, PPC_OPERAND_PARENS },
2407
2408 #define EVUIMM_1_EX0 EVUIMM_1 + 1
2409 { 0x1f, 11, insert_evuimm1_ex0, extract_evuimm1_ex0, PPC_OPERAND_PARENS },
2410
2411 #define EVUIMM_2 EVUIMM_1_EX0 + 1
2412 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
2413
2414 #define EVUIMM_2_EX0 EVUIMM_2 + 1
2415 { 0x3e, 10, insert_evuimm2_ex0, extract_evuimm2_ex0, PPC_OPERAND_PARENS },
2416
2417 /* The other UIMM field in a word EVX form instruction. */
2418 #define EVUIMM_4 EVUIMM_2_EX0 + 1
2419 { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
2420
2421 #define EVUIMM_4_EX0 EVUIMM_4 + 1
2422 { 0x7c, 9, insert_evuimm4_ex0, extract_evuimm4_ex0, PPC_OPERAND_PARENS },
2423
2424 /* The other UIMM field in a double EVX form instruction. */
2425 #define EVUIMM_8 EVUIMM_4_EX0 + 1
2426 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
2427
2428 #define EVUIMM_8_EX0 EVUIMM_8 + 1
2429 { 0xf8, 8, insert_evuimm8_ex0, extract_evuimm8_ex0, PPC_OPERAND_PARENS },
2430
2431 /* The WS or DRM field in an X form instruction. */
2432 #define WS EVUIMM_8_EX0 + 1
2433 #define DRM WS
2434 /* The NNN field in a VX form instruction for SPE2 */
2435 #define NNN WS
2436 { 0x7, 11, NULL, NULL, 0 },
2437
2438 /* PowerPC paired singles extensions. */
2439 /* W bit in the pair singles instructions for x type instructions. */
2440 #define PSWM WS + 1
2441 /* The BO16 field in a BD8 form instruction. */
2442 #define BO16 PSWM
2443 { 0x1, 10, 0, 0, 0 },
2444
2445 /* IDX bits for quantization in the pair singles instructions. */
2446 #define PSQ PSWM + 1
2447 { 0x7, 12, 0, 0, PPC_OPERAND_GQR },
2448
2449 /* IDX bits for quantization in the pair singles x-type instructions. */
2450 #define PSQM PSQ + 1
2451 { 0x7, 7, 0, 0, PPC_OPERAND_GQR },
2452
2453 /* Smaller D field for quantization in the pair singles instructions. */
2454 #define PSD PSQM + 1
2455 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
2456
2457 /* The L field in an mtmsrd or A form instruction or R or W in an
2458 X form. */
2459 #define A_L PSD + 1
2460 #define W A_L
2461 #define X_R A_L
2462 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
2463
2464 /* The RMC or CY field in a Z23 form instruction. */
2465 #define RMC A_L + 1
2466 #define CY RMC
2467 { 0x3, 9, NULL, NULL, 0 },
2468
2469 #define R RMC + 1
2470 { 0x1, 16, NULL, NULL, 0 },
2471
2472 #define RIC R + 1
2473 { 0x3, 18, NULL, NULL, PPC_OPERAND_OPTIONAL },
2474
2475 #define PRS RIC + 1
2476 { 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL },
2477
2478 #define SP PRS + 1
2479 { 0x3, 19, NULL, NULL, 0 },
2480
2481 #define S SP + 1
2482 { 0x1, 20, NULL, NULL, 0 },
2483
2484 /* The S field in a XL form instruction. */
2485 #define SXL S + 1
2486 { 0x1, 11, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
2487 /* If the SXL operand is ommitted, use the value 1. */
2488 { -1, 1, NULL, NULL, 0},
2489
2490 /* SH field starting at bit position 16. */
2491 #define SH16 SXL + 2
2492 /* The DCM and DGM fields in a Z form instruction. */
2493 #define DCM SH16
2494 #define DGM DCM
2495 { 0x3f, 10, NULL, NULL, 0 },
2496
2497 /* The EH field in larx instruction. */
2498 #define EH SH16 + 1
2499 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
2500
2501 /* The L field in an mtfsf or XFL form instruction. */
2502 /* The A field in a HTM X form instruction. */
2503 #define XFL_L EH + 1
2504 #define HTM_A XFL_L
2505 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
2506
2507 /* Xilinx APU related masks and macros */
2508 #define FCRT XFL_L + 1
2509 #define FCRT_MASK (0x1f << 21)
2510 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
2511
2512 /* Xilinx FSL related masks and macros */
2513 #define FSL FCRT + 1
2514 #define FSL_MASK (0x1f << 11)
2515 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
2516
2517 /* Xilinx UDI related masks and macros */
2518 #define URT FSL + 1
2519 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
2520
2521 #define URA URT + 1
2522 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
2523
2524 #define URB URA + 1
2525 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
2526
2527 #define URC URB + 1
2528 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
2529
2530 /* The VLESIMM field in a D form instruction. */
2531 #define VLESIMM URC + 1
2532 { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi,
2533 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
2534
2535 /* The VLENSIMM field in a D form instruction. */
2536 #define VLENSIMM VLESIMM + 1
2537 { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi,
2538 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
2539
2540 /* The VLEUIMM field in a D form instruction. */
2541 #define VLEUIMM VLENSIMM + 1
2542 { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 },
2543
2544 /* The VLEUIMML field in a D form instruction. */
2545 #define VLEUIMML VLEUIMM + 1
2546 { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 },
2547
2548 /* The XT and XS fields in an XX1 or XX3 form instruction. This is
2549 split. */
2550 #define XS6 VLEUIMML + 1
2551 #define XT6 XS6
2552 { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
2553
2554 /* The XT and XS fields in an DQ form VSX instruction. This is split. */
2555 #define XSQ6 XT6 + 1
2556 #define XTQ6 XSQ6
2557 { 0x3f, PPC_OPSHIFT_INV, insert_xtq6, extract_xtq6, PPC_OPERAND_VSR },
2558
2559 /* The XA field in an XX3 form instruction. This is split. */
2560 #define XA6 XTQ6 + 1
2561 { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
2562
2563 /* The XB field in an XX2 or XX3 form instruction. This is split. */
2564 #define XB6 XA6 + 1
2565 { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
2566
2567 /* The XB field in an XX3 form instruction when it must be the same as
2568 the XA field in the instruction. This is used in extended mnemonics
2569 like xvmovdp. This is split. */
2570 #define XB6S XB6 + 1
2571 { 0x3f, PPC_OPSHIFT_INV, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
2572
2573 /* The XC field in an XX4 form instruction. This is split. */
2574 #define XC6 XB6S + 1
2575 { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
2576
2577 /* The DM or SHW field in an XX3 form instruction. */
2578 #define DM XC6 + 1
2579 #define SHW DM
2580 { 0x3, 8, NULL, NULL, 0 },
2581
2582 /* The DM field in an extended mnemonic XX3 form instruction. */
2583 #define DMEX DM + 1
2584 { 0x3, 8, insert_dm, extract_dm, 0 },
2585
2586 /* The UIM field in an XX2 form instruction. */
2587 #define UIM DMEX + 1
2588 /* The 2-bit UIMM field in a VX form instruction. */
2589 #define UIMM2 UIM
2590 /* The 2-bit L field in a darn instruction. */
2591 #define LRAND UIM
2592 { 0x3, 16, NULL, NULL, 0 },
2593
2594 #define ERAT_T UIM + 1
2595 { 0x7, 21, NULL, NULL, 0 },
2596
2597 #define IH ERAT_T + 1
2598 { 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
2599
2600 /* The 8-bit IMM8 field in a XX1 form instruction. */
2601 #define IMM8 IH + 1
2602 { 0xff, 11, NULL, NULL, PPC_OPERAND_SIGNOPT },
2603
2604 #define VX_OFF IMM8 + 1
2605 { 0x3, 0, insert_off_lsp, extract_off_lsp, 0 },
2606
2607 #define VX_OFF_SPE2 VX_OFF + 1
2608 { 0x7, 0, insert_off_spe2, extract_off_spe2, 0 },
2609
2610 #define BBB VX_OFF_SPE2 + 1
2611 { 0x7, 13, NULL, NULL, 0 },
2612
2613 #define DDD BBB + 1
2614 #define VX_MASK_DDD (VX_MASK & ~0x1)
2615 { 0x7, PPC_OPSHIFT_INV, insert_Ddd, extract_Ddd, 0 },
2616
2617 #define HH DDD + 1
2618 { 0x3, 13, NULL, NULL, 0 },
2619 };
2620
2621 const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
2622 / sizeof (powerpc_operands[0]));
2623 \f
2624 /* Macros used to form opcodes. */
2625
2626 /* The main opcode. */
2627 #define OP(x) ((((uint64_t)(x)) & 0x3f) << 26)
2628 #define OP_MASK OP (0x3f)
2629
2630 /* The main opcode combined with a trap code in the TO field of a D
2631 form instruction. Used for extended mnemonics for the trap
2632 instructions. */
2633 #define OPTO(x,to) (OP (x) | ((((uint64_t)(to)) & 0x1f) << 21))
2634 #define OPTO_MASK (OP_MASK | TO_MASK)
2635
2636 /* The main opcode combined with a comparison size bit in the L field
2637 of a D form or X form instruction. Used for extended mnemonics for
2638 the comparison instructions. */
2639 #define OPL(x,l) (OP (x) | ((((uint64_t)(l)) & 1) << 21))
2640 #define OPL_MASK OPL (0x3f,1)
2641
2642 /* The main opcode combined with an update code in D form instruction.
2643 Used for extended mnemonics for VLE memory instructions. */
2644 #define OPVUP(x,vup) (OP (x) | ((((uint64_t)(vup)) & 0xff) << 8))
2645 #define OPVUP_MASK OPVUP (0x3f, 0xff)
2646
2647 /* The main opcode combined with an update code and the RT fields
2648 specified in D form instruction. Used for VLE volatile context
2649 save/restore instructions. */
2650 #define OPVUPRT(x,vup,rt) \
2651 (OPVUP (x, vup) \
2652 | ((((uint64_t)(rt)) & 0x1f) << 21))
2653 #define OPVUPRT_MASK OPVUPRT (0x3f, 0xff, 0x1f)
2654
2655 /* An A form instruction. */
2656 #define A(op, xop, rc) \
2657 (OP (op) \
2658 | ((((uint64_t)(xop)) & 0x1f) << 1) \
2659 | (((uint64_t)(rc)) & 1))
2660 #define A_MASK A (0x3f, 0x1f, 1)
2661
2662 /* An A_MASK with the FRB field fixed. */
2663 #define AFRB_MASK (A_MASK | FRB_MASK)
2664
2665 /* An A_MASK with the FRC field fixed. */
2666 #define AFRC_MASK (A_MASK | FRC_MASK)
2667
2668 /* An A_MASK with the FRA and FRC fields fixed. */
2669 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
2670
2671 /* An AFRAFRC_MASK, but with L bit clear. */
2672 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((uint64_t) 1 << 16))
2673
2674 /* A B form instruction. */
2675 #define B(op, aa, lk) \
2676 (OP (op) \
2677 | ((((uint64_t)(aa)) & 1) << 1) \
2678 | ((lk) & 1))
2679 #define B_MASK B (0x3f, 1, 1)
2680
2681 /* A BD8 form instruction. This is a 16-bit instruction. */
2682 #define BD8(op, aa, lk) \
2683 (((((uint64_t)(op)) & 0x3f) << 10) \
2684 | (((aa) & 1) << 9) \
2685 | (((lk) & 1) << 8))
2686 #define BD8_MASK BD8 (0x3f, 1, 1)
2687
2688 /* Another BD8 form instruction. This is a 16-bit instruction. */
2689 #define BD8IO(op) ((((uint64_t)(op)) & 0x1f) << 11)
2690 #define BD8IO_MASK BD8IO (0x1f)
2691
2692 /* A BD8 form instruction for simplified mnemonics. */
2693 #define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
2694 /* A mask that excludes BO32 and BI32. */
2695 #define EBD8IO1_MASK 0xf800
2696 /* A mask that includes BO32 and excludes BI32. */
2697 #define EBD8IO2_MASK 0xfc00
2698 /* A mask that include BO32 AND BI32. */
2699 #define EBD8IO3_MASK 0xff00
2700
2701 /* A BD15 form instruction. */
2702 #define BD15(op, aa, lk) \
2703 (OP (op) \
2704 | ((((uint64_t)(aa)) & 0xf) << 22) \
2705 | ((lk) & 1))
2706 #define BD15_MASK BD15 (0x3f, 0xf, 1)
2707
2708 /* A BD15 form instruction for extended conditional branch mnemonics. */
2709 #define EBD15(op, aa, bo, lk) \
2710 (((op) & 0x3f) << 26) \
2711 | (((aa) & 0xf) << 22) \
2712 | (((bo) & 0x3) << 20) \
2713 | ((lk) & 1)
2714 #define EBD15_MASK 0xfff00001
2715
2716 /* A BD15 form instruction for extended conditional branch mnemonics
2717 with BI. */
2718 #define EBD15BI(op, aa, bo, bi, lk) \
2719 ((((op) & 0x3f) << 26) \
2720 | (((aa) & 0xf) << 22) \
2721 | (((bo) & 0x3) << 20) \
2722 | (((bi) & 0x3) << 16) \
2723 | ((lk) & 1))
2724
2725 #define EBD15BI_MASK 0xfff30001
2726
2727 /* A BD24 form instruction. */
2728 #define BD24(op, aa, lk) \
2729 (OP (op) \
2730 | ((((uint64_t)(aa)) & 1) << 25) \
2731 | ((lk) & 1))
2732 #define BD24_MASK BD24 (0x3f, 1, 1)
2733
2734 /* A B form instruction setting the BO field. */
2735 #define BBO(op, bo, aa, lk) \
2736 (B ((op), (aa), (lk)) \
2737 | ((((uint64_t)(bo)) & 0x1f) << 21))
2738 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
2739
2740 /* A BBO_MASK with the y bit of the BO field removed. This permits
2741 matching a conditional branch regardless of the setting of the y
2742 bit. Similarly for the 'at' bits used for power4 branch hints. */
2743 #define Y_MASK (((uint64_t) 1) << 21)
2744 #define AT1_MASK (((uint64_t) 3) << 21)
2745 #define AT2_MASK (((uint64_t) 9) << 21)
2746 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
2747 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
2748
2749 /* A B form instruction setting the BO field and the condition bits of
2750 the BI field. */
2751 #define BBOCB(op, bo, cb, aa, lk) \
2752 (BBO ((op), (bo), (aa), (lk)) | ((((uint64_t)(cb)) & 0x3) << 16))
2753 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
2754
2755 /* A BBOCB_MASK with the y bit of the BO field removed. */
2756 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
2757 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
2758 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
2759
2760 /* A BBOYCB_MASK in which the BI field is fixed. */
2761 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
2762 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
2763
2764 /* A VLE C form instruction. */
2765 #define C_LK(x, lk) (((((uint64_t)(x)) & 0x7fff) << 1) | ((lk) & 1))
2766 #define C_LK_MASK C_LK(0x7fff, 1)
2767 #define C(x) ((((uint64_t)(x)) & 0xffff))
2768 #define C_MASK C(0xffff)
2769
2770 /* An Context form instruction. */
2771 #define CTX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7))
2772 #define CTX_MASK CTX(0x3f, 0x7)
2773
2774 /* An User Context form instruction. */
2775 #define UCTX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f))
2776 #define UCTX_MASK UCTX(0x3f, 0x1f)
2777
2778 /* The main opcode mask with the RA field clear. */
2779 #define DRA_MASK (OP_MASK | RA_MASK)
2780
2781 /* A DQ form VSX instruction. */
2782 #define DQX(op, xop) (OP (op) | ((xop) & 0x7))
2783 #define DQX_MASK DQX (0x3f, 7)
2784
2785 /* A DS form instruction. */
2786 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
2787 #define DS_MASK DSO (0x3f, 3)
2788
2789 /* An DX form instruction. */
2790 #define DX(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 1))
2791 #define DX_MASK DX (0x3f, 0x1f)
2792 /* An DX form instruction with the D bits specified. */
2793 #define NODX_MASK (DX_MASK | 0x1fffc1)
2794
2795 /* An EVSEL form instruction. */
2796 #define EVSEL(op, xop) (OP (op) | (((uint64_t)(xop)) & 0xff) << 3)
2797 #define EVSEL_MASK EVSEL(0x3f, 0xff)
2798
2799 /* An IA16 form instruction. */
2800 #define IA16(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11)
2801 #define IA16_MASK IA16(0x3f, 0x1f)
2802
2803 /* An I16A form instruction. */
2804 #define I16A(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11)
2805 #define I16A_MASK I16A(0x3f, 0x1f)
2806
2807 /* An I16L form instruction. */
2808 #define I16L(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11)
2809 #define I16L_MASK I16L(0x3f, 0x1f)
2810
2811 /* An IM7 form instruction. */
2812 #define IM7(op) ((((uint64_t)(op)) & 0x1f) << 11)
2813 #define IM7_MASK IM7(0x1f)
2814
2815 /* An M form instruction. */
2816 #define M(op, rc) (OP (op) | ((rc) & 1))
2817 #define M_MASK M (0x3f, 1)
2818
2819 /* An LI20 form instruction. */
2820 #define LI20(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1) << 15)
2821 #define LI20_MASK LI20(0x3f, 0x1)
2822
2823 /* An M form instruction with the ME field specified. */
2824 #define MME(op, me, rc) \
2825 (M ((op), (rc)) \
2826 | ((((uint64_t)(me)) & 0x1f) << 1))
2827
2828 /* An M_MASK with the MB and ME fields fixed. */
2829 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
2830
2831 /* An M_MASK with the SH and ME fields fixed. */
2832 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
2833
2834 /* An MD form instruction. */
2835 #define MD(op, xop, rc) \
2836 (OP (op) \
2837 | ((((uint64_t)(xop)) & 0x7) << 2) \
2838 | ((rc) & 1))
2839 #define MD_MASK MD (0x3f, 0x7, 1)
2840
2841 /* An MD_MASK with the MB field fixed. */
2842 #define MDMB_MASK (MD_MASK | MB6_MASK)
2843
2844 /* An MD_MASK with the SH field fixed. */
2845 #define MDSH_MASK (MD_MASK | SH6_MASK)
2846
2847 /* An MDS form instruction. */
2848 #define MDS(op, xop, rc) \
2849 (OP (op) \
2850 | ((((uint64_t)(xop)) & 0xf) << 1) \
2851 | ((rc) & 1))
2852 #define MDS_MASK MDS (0x3f, 0xf, 1)
2853
2854 /* An MDS_MASK with the MB field fixed. */
2855 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
2856
2857 /* An SC form instruction. */
2858 #define SC(op, sa, lk) \
2859 (OP (op) \
2860 | ((((uint64_t)(sa)) & 1) << 1) \
2861 | ((lk) & 1))
2862 #define SC_MASK \
2863 (OP_MASK \
2864 | (((uint64_t) 0x3ff) << 16) \
2865 | (((uint64_t) 1) << 1) \
2866 | 1)
2867
2868 /* An SCI8 form instruction. */
2869 #define SCI8(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 11))
2870 #define SCI8_MASK SCI8(0x3f, 0x1f)
2871
2872 /* An SCI8 form instruction. */
2873 #define SCI8BF(op, fop, xop) \
2874 (OP (op) \
2875 | ((((uint64_t)(xop)) & 0x1f) << 11) \
2876 | (((fop) & 7) << 23))
2877 #define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
2878
2879 /* An SD4 form instruction. This is a 16-bit instruction. */
2880 #define SD4(op) ((((uint64_t)(op)) & 0xf) << 12)
2881 #define SD4_MASK SD4(0xf)
2882
2883 /* An SE_IM5 form instruction. This is a 16-bit instruction. */
2884 #define SE_IM5(op, xop) \
2885 (((((uint64_t)(op)) & 0x3f) << 10) \
2886 | (((xop) & 0x1) << 9))
2887 #define SE_IM5_MASK SE_IM5(0x3f, 1)
2888
2889 /* An SE_R form instruction. This is a 16-bit instruction. */
2890 #define SE_R(op, xop) \
2891 (((((uint64_t)(op)) & 0x3f) << 10) \
2892 | (((xop) & 0x3f) << 4))
2893 #define SE_R_MASK SE_R(0x3f, 0x3f)
2894
2895 /* An SE_RR form instruction. This is a 16-bit instruction. */
2896 #define SE_RR(op, xop) \
2897 (((((uint64_t)(op)) & 0x3f) << 10) \
2898 | (((xop) & 0x3) << 8))
2899 #define SE_RR_MASK SE_RR(0x3f, 3)
2900
2901 /* A VX form instruction. */
2902 #define VX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7ff))
2903
2904 /* The mask for an VX form instruction. */
2905 #define VX_MASK VX(0x3f, 0x7ff)
2906
2907 /* A VX LSP form instruction. */
2908 #define VX_LSP(op, xop) (OP (op) | (((uint64_t)(xop)) & 0xffff))
2909
2910 /* The mask for an VX LSP form instruction. */
2911 #define VX_LSP_MASK VX_LSP(0x3f, 0xffff)
2912 #define VX_LSP_OFF_MASK VX_LSP(0x3f, 0x7fc)
2913
2914 /* Additional format of VX SPE2 form instruction. */
2915 #define VX_RA_CONST(op, xop, bits11_15) \
2916 (OP (op) \
2917 | (((uint64_t)(bits11_15) & 0x1f) << 16) \
2918 | (((uint64_t)(xop)) & 0x7ff))
2919 #define VX_RA_CONST_MASK VX_RA_CONST(0x3f, 0x7ff, 0x1f)
2920
2921 #define VX_RB_CONST(op, xop, bits16_20) \
2922 (OP (op) \
2923 | (((uint64_t)(bits16_20) & 0x1f) << 11) \
2924 | (((uint64_t)(xop)) & 0x7ff))
2925 #define VX_RB_CONST_MASK VX_RB_CONST(0x3f, 0x7ff, 0x1f)
2926
2927 #define VX_OFF_SPE2_MASK VX(0x3f, 0x7f8)
2928
2929 #define VX_SPE_CRFD(op, xop, bits9_10) \
2930 (OP (op) \
2931 | (((uint64_t)(bits9_10) & 0x3) << 21) \
2932 | (((uint64_t)(xop)) & 0x7ff))
2933 #define VX_SPE_CRFD_MASK VX_SPE_CRFD(0x3f, 0x7ff, 0x3)
2934
2935 #define VX_SPE2_CLR(op, xop, bit16) \
2936 (OP (op) \
2937 | (((uint64_t)(bit16) & 0x1) << 15) \
2938 | (((uint64_t)(xop)) & 0x7ff))
2939 #define VX_SPE2_CLR_MASK VX_SPE2_CLR(0x3f, 0x7ff, 0x1)
2940
2941 #define VX_SPE2_SPLATB(op, xop, bits19_20) \
2942 (OP (op) \
2943 | (((uint64_t)(bits19_20) & 0x3) << 11) \
2944 | (((uint64_t)(xop)) & 0x7ff))
2945 #define VX_SPE2_SPLATB_MASK VX_SPE2_SPLATB(0x3f, 0x7ff, 0x3)
2946
2947 #define VX_SPE2_OCTET(op, xop, bits16_17) \
2948 (OP (op) \
2949 | (((uint64_t)(bits16_17) & 0x3) << 14) \
2950 | (((uint64_t)(xop)) & 0x7ff))
2951 #define VX_SPE2_OCTET_MASK VX_SPE2_OCTET(0x3f, 0x7ff, 0x7)
2952
2953 #define VX_SPE2_DDHH(op, xop, bit16) \
2954 (OP (op) \
2955 | (((uint64_t)(bit16) & 0x1) << 15) \
2956 | (((uint64_t)(xop)) & 0x7ff))
2957 #define VX_SPE2_DDHH_MASK VX_SPE2_DDHH(0x3f, 0x7ff, 0x1)
2958
2959 #define VX_SPE2_HH(op, xop, bit16, bits19_20) \
2960 (OP (op) \
2961 | (((uint64_t)(bit16) & 0x1) << 15) \
2962 | (((uint64_t)(bits19_20) & 0x3) << 11) \
2963 | (((uint64_t)(xop)) & 0x7ff))
2964 #define VX_SPE2_HH_MASK VX_SPE2_HH(0x3f, 0x7ff, 0x1, 0x3)
2965
2966 #define VX_SPE2_EVMAR(op, xop) \
2967 (OP (op) \
2968 | ((uint64_t)(0x1) << 11) \
2969 | (((uint64_t)(xop)) & 0x7ff))
2970 #define VX_SPE2_EVMAR_MASK \
2971 (VX_SPE2_EVMAR(0x3f, 0x7ff) \
2972 | ((uint64_t)(0x1) << 11))
2973
2974 /* A VX_MASK with the VA field fixed. */
2975 #define VXVA_MASK (VX_MASK | (0x1f << 16))
2976
2977 /* A VX_MASK with the VB field fixed. */
2978 #define VXVB_MASK (VX_MASK | (0x1f << 11))
2979
2980 /* A VX_MASK with the VA and VB fields fixed. */
2981 #define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))
2982
2983 /* A VX_MASK with the VD and VA fields fixed. */
2984 #define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))
2985
2986 /* A VX_MASK with a UIMM4 field. */
2987 #define VXUIMM4_MASK (VX_MASK | (0x1 << 20))
2988
2989 /* A VX_MASK with a UIMM3 field. */
2990 #define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
2991
2992 /* A VX_MASK with a UIMM2 field. */
2993 #define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
2994
2995 /* A VX_MASK with a PS field. */
2996 #define VXPS_MASK (VX_MASK & ~(0x1 << 9))
2997
2998 /* A VX_MASK with the VA field fixed with a PS field. */
2999 #define VXVAPS_MASK ((VX_MASK | (0x1f << 16)) & ~(0x1 << 9))
3000
3001 /* A VA form instruction. */
3002 #define VXA(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x03f))
3003
3004 /* The mask for an VA form instruction. */
3005 #define VXA_MASK VXA(0x3f, 0x3f)
3006
3007 /* A VXA_MASK with a SHB field. */
3008 #define VXASHB_MASK (VXA_MASK | (1 << 10))
3009
3010 /* A VXR form instruction. */
3011 #define VXR(op, xop, rc) \
3012 (OP (op) \
3013 | (((uint64_t)(rc) & 1) << 10) \
3014 | (((uint64_t)(xop)) & 0x3ff))
3015
3016 /* The mask for a VXR form instruction. */
3017 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
3018
3019 /* A VX form instruction with a VA tertiary opcode. */
3020 #define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16))
3021
3022 #define VXASH(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 1))
3023 #define VXASH_MASK VXASH (0x3f, 0x1f)
3024
3025 /* An X form instruction. */
3026 #define X(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3ff) << 1))
3027
3028 /* A X form instruction for Quad-Precision FP Instructions. */
3029 #define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16))
3030
3031 /* An EX form instruction. */
3032 #define EX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7ff))
3033
3034 /* The mask for an EX form instruction. */
3035 #define EX_MASK EX (0x3f, 0x7ff)
3036
3037 /* An XX2 form instruction. */
3038 #define XX2(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1ff) << 2))
3039
3040 /* A XX2 form instruction with the VA bits specified. */
3041 #define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16))
3042
3043 /* An XX3 form instruction. */
3044 #define XX3(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0xff) << 3))
3045
3046 /* An XX3 form instruction with the RC bit specified. */
3047 #define XX3RC(op, xop, rc) \
3048 (OP (op) \
3049 | (((uint64_t)(rc) & 1) << 10) \
3050 | ((((uint64_t)(xop)) & 0x7f) << 3))
3051
3052 /* An XX4 form instruction. */
3053 #define XX4(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3) << 4))
3054
3055 /* A Z form instruction. */
3056 #define Z(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1ff) << 1))
3057
3058 /* An X form instruction with the RC bit specified. */
3059 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
3060
3061 /* A X form instruction for Quad-Precision FP Instructions with RC bit. */
3062 #define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1))
3063
3064 /* An X form instruction with the RA bits specified as two ops. */
3065 #define XMMF(op, xop, mop0, mop1) \
3066 (X ((op), (xop)) \
3067 | ((mop0) & 3) << 19 \
3068 | ((mop1) & 7) << 16)
3069
3070 /* A Z form instruction with the RC bit specified. */
3071 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
3072
3073 /* The mask for an X form instruction. */
3074 #define X_MASK XRC (0x3f, 0x3ff, 1)
3075
3076 /* The mask for an X form instruction with the BF bits specified. */
3077 #define XBF_MASK (X_MASK | (3 << 21))
3078
3079 /* An X form wait instruction with everything filled in except the WC
3080 field. */
3081 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
3082
3083 /* The mask for an XX1 form instruction. */
3084 #define XX1_MASK X (0x3f, 0x3ff)
3085
3086 /* An XX1_MASK with the RB field fixed. */
3087 #define XX1RB_MASK (XX1_MASK | RB_MASK)
3088
3089 /* The mask for an XX2 form instruction. */
3090 #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
3091
3092 /* The mask for an XX2 form instruction with the UIM bits specified. */
3093 #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
3094
3095 /* The mask for an XX2 form instruction with the 4 UIM bits specified. */
3096 #define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20))
3097
3098 /* The mask for an XX2 form instruction with the BF bits specified. */
3099 #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
3100
3101 /* The mask for an XX2 form instruction with the BF and DCMX bits
3102 specified. */
3103 #define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1)
3104
3105 /* The mask for an XX2 form instruction with a split DCMX bits
3106 specified. */
3107 #define XX2DCMXS_MASK XX2 (0x3f, 0x1ee)
3108
3109 /* The mask for an XX3 form instruction. */
3110 #define XX3_MASK XX3 (0x3f, 0xff)
3111
3112 /* The mask for an XX3 form instruction with the BF bits specified. */
3113 #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
3114
3115 /* The mask for an XX3 form instruction with the DM or SHW bits
3116 specified. */
3117 #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
3118 #define XX3SHW_MASK XX3DM_MASK
3119
3120 /* The mask for an XX4 form instruction. */
3121 #define XX4_MASK XX4 (0x3f, 0x3)
3122
3123 /* An X form wait instruction with everything filled in except the WC
3124 field. */
3125 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
3126
3127 /* The mask for an XMMF form instruction. */
3128 #define XMMF_MASK (XMMF (0x3f, 0x3ff, 3, 7) | (1))
3129
3130 /* The mask for a Z form instruction. */
3131 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
3132 #define Z2_MASK ZRC (0x3f, 0xff, 1)
3133
3134 /* An X_MASK with the RA/VA field fixed. */
3135 #define XRA_MASK (X_MASK | RA_MASK)
3136 #define XVA_MASK XRA_MASK
3137
3138 /* An XRA_MASK with the A_L/W field clear. */
3139 #define XWRA_MASK (XRA_MASK & ~((uint64_t) 1 << 16))
3140 #define XRLA_MASK XWRA_MASK
3141
3142 /* An X_MASK with the RB field fixed. */
3143 #define XRB_MASK (X_MASK | RB_MASK)
3144
3145 /* An X_MASK with the RT field fixed. */
3146 #define XRT_MASK (X_MASK | RT_MASK)
3147
3148 /* An XRT_MASK mask with the L bits clear. */
3149 #define XLRT_MASK (XRT_MASK & ~((uint64_t) 0x3 << 21))
3150
3151 /* An X_MASK with the RA and RB fields fixed. */
3152 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
3153
3154 /* An XBF_MASK with the RA and RB fields fixed. */
3155 #define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK)
3156
3157 /* An XRARB_MASK, but with the L bit clear. */
3158 #define XRLARB_MASK (XRARB_MASK & ~((uint64_t) 1 << 16))
3159
3160 /* An XRARB_MASK, but with the L bits in a darn instruction clear. */
3161 #define XLRAND_MASK (XRARB_MASK & ~((uint64_t) 3 << 16))
3162
3163 /* An X_MASK with the RT and RA fields fixed. */
3164 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
3165
3166 /* An X_MASK with the RT and RB fields fixed. */
3167 #define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK)
3168
3169 /* An XRTRA_MASK, but with L bit clear. */
3170 #define XRTLRA_MASK (XRTRA_MASK & ~((uint64_t) 1 << 21))
3171
3172 /* An X_MASK with the RT, RA and RB fields fixed. */
3173 #define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK)
3174
3175 /* An XRTRARB_MASK, but with L bit clear. */
3176 #define XRTLRARB_MASK (XRTRARB_MASK & ~((uint64_t) 1 << 21))
3177
3178 /* An XRTRARB_MASK, but with A bit clear. */
3179 #define XRTARARB_MASK (XRTRARB_MASK & ~((uint64_t) 1 << 25))
3180
3181 /* An XRTRARB_MASK, but with BF bits clear. */
3182 #define XRTBFRARB_MASK (XRTRARB_MASK & ~((uint64_t) 7 << 23))
3183
3184 /* An X form instruction with the L bit specified. */
3185 #define XOPL(op, xop, l) \
3186 (X ((op), (xop)) \
3187 | ((((uint64_t)(l)) & 1) << 21))
3188
3189 /* An X form instruction with the L bits specified. */
3190 #define XOPL2(op, xop, l) \
3191 (X ((op), (xop)) \
3192 | ((((uint64_t)(l)) & 3) << 21))
3193
3194 /* An X form instruction with the L bit and RC bit specified. */
3195 #define XRCL(op, xop, l, rc) \
3196 (XRC ((op), (xop), (rc)) \
3197 | ((((uint64_t)(l)) & 1) << 21))
3198
3199 /* An X form instruction with RT fields specified */
3200 #define XRT(op, xop, rt) \
3201 (X ((op), (xop)) \
3202 | ((((uint64_t)(rt)) & 0x1f) << 21))
3203
3204 /* An X form instruction with RT and RA fields specified */
3205 #define XRTRA(op, xop, rt, ra) \
3206 (X ((op), (xop)) \
3207 | ((((uint64_t)(rt)) & 0x1f) << 21) \
3208 | ((((uint64_t)(ra)) & 0x1f) << 16))
3209
3210 /* The mask for an X form comparison instruction. */
3211 #define XCMP_MASK (X_MASK | (((uint64_t)1) << 22))
3212
3213 /* The mask for an X form comparison instruction with the L field
3214 fixed. */
3215 #define XCMPL_MASK (XCMP_MASK | (((uint64_t)1) << 21))
3216
3217 /* An X form trap instruction with the TO field specified. */
3218 #define XTO(op, xop, to) \
3219 (X ((op), (xop)) \
3220 | ((((uint64_t)(to)) & 0x1f) << 21))
3221 #define XTO_MASK (X_MASK | TO_MASK)
3222
3223 /* An X form tlb instruction with the SH field specified. */
3224 #define XTLB(op, xop, sh) \
3225 (X ((op), (xop)) \
3226 | ((((uint64_t)(sh)) & 0x1f) << 11))
3227 #define XTLB_MASK (X_MASK | SH_MASK)
3228
3229 /* An X form sync instruction. */
3230 #define XSYNC(op, xop, l) \
3231 (X ((op), (xop)) \
3232 | ((((uint64_t)(l)) & 3) << 21))
3233
3234 /* An X form sync instruction with everything filled in except the LS
3235 field. */
3236 #define XSYNC_MASK (0xff9fffff)
3237
3238 /* An X form sync instruction with everything filled in except the L
3239 and E fields. */
3240 #define XSYNCLE_MASK (0xff90ffff)
3241
3242 /* An X_MASK, but with the EH bit clear. */
3243 #define XEH_MASK (X_MASK & ~((uint64_t )1))
3244
3245 /* An X form AltiVec dss instruction. */
3246 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((uint64_t)(a)) & 1) << 25))
3247 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
3248
3249 /* An XFL form instruction. */
3250 #define XFL(op, xop, rc) \
3251 (OP (op) \
3252 | ((((uint64_t)(xop)) & 0x3ff) << 1) \
3253 | (((uint64_t)(rc)) & 1))
3254 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
3255
3256 /* An X form isel instruction. */
3257 #define XISEL(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 1))
3258 #define XISEL_MASK XISEL(0x3f, 0x1f)
3259
3260 /* An XL form instruction with the LK field set to 0. */
3261 #define XL(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3ff) << 1))
3262
3263 /* An XL form instruction which uses the LK field. */
3264 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
3265
3266 /* The mask for an XL form instruction. */
3267 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
3268
3269 /* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */
3270 #define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11))
3271
3272 /* An XL form instruction which explicitly sets the BO field. */
3273 #define XLO(op, bo, xop, lk) \
3274 (XLLK ((op), (xop), (lk)) | ((((uint64_t)(bo)) & 0x1f) << 21))
3275 #define XLO_MASK (XL_MASK | BO_MASK)
3276
3277 /* An XL form instruction which explicitly sets the y bit of the BO
3278 field. */
3279 #define XLYLK(op, xop, y, lk) \
3280 (XLLK ((op), (xop), (lk)) \
3281 | ((((uint64_t)(y)) & 1) << 21))
3282 #define XLYLK_MASK (XL_MASK | Y_MASK)
3283
3284 /* An XL form instruction which sets the BO field and the condition
3285 bits of the BI field. */
3286 #define XLOCB(op, bo, cb, xop, lk) \
3287 (XLO ((op), (bo), (xop), (lk)) | ((((uint64_t)(cb)) & 3) << 16))
3288 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
3289
3290 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
3291 #define XLBB_MASK (XL_MASK | BB_MASK)
3292 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
3293 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
3294
3295 /* A mask for branch instructions using the BH field. */
3296 #define XLBH_MASK (XL_MASK | (0x1c << 11))
3297
3298 /* An XL_MASK with the BO and BB fields fixed. */
3299 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
3300
3301 /* An XL_MASK with the BO, BI and BB fields fixed. */
3302 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
3303
3304 /* An X form mbar instruction with MO field. */
3305 #define XMBAR(op, xop, mo) \
3306 (X ((op), (xop)) \
3307 | ((((uint64_t)(mo)) & 1) << 21))
3308
3309 /* An XO form instruction. */
3310 #define XO(op, xop, oe, rc) \
3311 (OP (op) \
3312 | ((((uint64_t)(xop)) & 0x1ff) << 1) \
3313 | ((((uint64_t)(oe)) & 1) << 10) \
3314 | (((unsigned long)(rc)) & 1))
3315 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
3316
3317 /* An XO_MASK with the RB field fixed. */
3318 #define XORB_MASK (XO_MASK | RB_MASK)
3319
3320 /* An XOPS form instruction for paired singles. */
3321 #define XOPS(op, xop, rc) \
3322 (OP (op) \
3323 | ((((uint64_t)(xop)) & 0x3ff) << 1) \
3324 | (((uint64_t)(rc)) & 1))
3325 #define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
3326
3327
3328 /* An XS form instruction. */
3329 #define XS(op, xop, rc) \
3330 (OP (op) \
3331 | ((((uint64_t)(xop)) & 0x1ff) << 2) \
3332 | (((uint64_t)(rc)) & 1))
3333 #define XS_MASK XS (0x3f, 0x1ff, 1)
3334
3335 /* A mask for the FXM version of an XFX form instruction. */
3336 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
3337
3338 /* An XFX form instruction with the FXM field filled in. */
3339 #define XFXM(op, xop, fxm, p4) \
3340 (X ((op), (xop)) \
3341 | ((((uint64_t)(fxm)) & 0xff) << 12) \
3342 | ((uint64_t)(p4) << 20))
3343
3344 /* An XFX form instruction with the SPR field filled in. */
3345 #define XSPR(op, xop, spr) \
3346 (X ((op), (xop)) \
3347 | ((((uint64_t)(spr)) & 0x1f) << 16) \
3348 | ((((uint64_t)(spr)) & 0x3e0) << 6))
3349 #define XSPR_MASK (X_MASK | SPR_MASK)
3350
3351 /* An XFX form instruction with the SPR field filled in except for the
3352 SPRBAT field. */
3353 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
3354
3355 /* An XFX form instruction with the SPR field filled in except for the
3356 SPRG field. */
3357 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
3358
3359 /* An X form instruction with everything filled in except the E field. */
3360 #define XE_MASK (0xffff7fff)
3361
3362 /* An X form user context instruction. */
3363 #define XUC(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f))
3364 #define XUC_MASK XUC(0x3f, 0x1f)
3365
3366 /* An XW form instruction. */
3367 #define XW(op, xop, rc) \
3368 (OP (op) \
3369 | ((((uint64_t)(xop)) & 0x3f) << 1) \
3370 | ((rc) & 1))
3371 /* The mask for a G form instruction. rc not supported at present. */
3372 #define XW_MASK XW (0x3f, 0x3f, 0)
3373
3374 /* An APU form instruction. */
3375 #define APU(op, xop, rc) \
3376 (OP (op) \
3377 | (((uint64_t)(xop)) & 0x3ff) << 1 \
3378 | ((rc) & 1))
3379
3380 /* The mask for an APU form instruction. */
3381 #define APU_MASK APU (0x3f, 0x3ff, 1)
3382 #define APU_RT_MASK (APU_MASK | RT_MASK)
3383 #define APU_RA_MASK (APU_MASK | RA_MASK)
3384
3385 /* The BO encodings used in extended conditional branch mnemonics. */
3386 #define BODNZF (0x0)
3387 #define BODNZFP (0x1)
3388 #define BODZF (0x2)
3389 #define BODZFP (0x3)
3390 #define BODNZT (0x8)
3391 #define BODNZTP (0x9)
3392 #define BODZT (0xa)
3393 #define BODZTP (0xb)
3394
3395 #define BOF (0x4)
3396 #define BOFP (0x5)
3397 #define BOFM4 (0x6)
3398 #define BOFP4 (0x7)
3399 #define BOT (0xc)
3400 #define BOTP (0xd)
3401 #define BOTM4 (0xe)
3402 #define BOTP4 (0xf)
3403
3404 #define BODNZ (0x10)
3405 #define BODNZP (0x11)
3406 #define BODZ (0x12)
3407 #define BODZP (0x13)
3408 #define BODNZM4 (0x18)
3409 #define BODNZP4 (0x19)
3410 #define BODZM4 (0x1a)
3411 #define BODZP4 (0x1b)
3412
3413 #define BOU (0x14)
3414
3415 /* The BO16 encodings used in extended VLE conditional branch mnemonics. */
3416 #define BO16F (0x0)
3417 #define BO16T (0x1)
3418
3419 /* The BO32 encodings used in extended VLE conditional branch mnemonics. */
3420 #define BO32F (0x0)
3421 #define BO32T (0x1)
3422 #define BO32DNZ (0x2)
3423 #define BO32DZ (0x3)
3424
3425 /* The BI condition bit encodings used in extended conditional branch
3426 mnemonics. */
3427 #define CBLT (0)
3428 #define CBGT (1)
3429 #define CBEQ (2)
3430 #define CBSO (3)
3431
3432 /* The TO encodings used in extended trap mnemonics. */
3433 #define TOLGT (0x1)
3434 #define TOLLT (0x2)
3435 #define TOEQ (0x4)
3436 #define TOLGE (0x5)
3437 #define TOLNL (0x5)
3438 #define TOLLE (0x6)
3439 #define TOLNG (0x6)
3440 #define TOGT (0x8)
3441 #define TOGE (0xc)
3442 #define TONL (0xc)
3443 #define TOLT (0x10)
3444 #define TOLE (0x14)
3445 #define TONG (0x14)
3446 #define TONE (0x18)
3447 #define TOU (0x1f)
3448 \f
3449 /* Smaller names for the flags so each entry in the opcodes table will
3450 fit on a single line. */
3451 #undef PPC
3452 #define PPC PPC_OPCODE_PPC
3453 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
3454 #define POWER4 PPC_OPCODE_POWER4
3455 #define POWER5 PPC_OPCODE_POWER5
3456 #define POWER6 PPC_OPCODE_POWER6
3457 #define POWER7 PPC_OPCODE_POWER7
3458 #define POWER8 PPC_OPCODE_POWER8
3459 #define POWER9 PPC_OPCODE_POWER9
3460 #define CELL PPC_OPCODE_CELL
3461 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
3462 #define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \
3463 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
3464 #define PPC403 PPC_OPCODE_403
3465 #define PPC405 PPC_OPCODE_405
3466 #define PPC440 PPC_OPCODE_440
3467 #define PPC464 PPC440
3468 #define PPC476 PPC_OPCODE_476
3469 #define PPC750 PPC_OPCODE_750
3470 #define PPC7450 PPC_OPCODE_7450
3471 #define PPC860 PPC_OPCODE_860
3472 #define PPCPS PPC_OPCODE_PPCPS
3473 #define PPCVEC PPC_OPCODE_ALTIVEC
3474 #define PPCVEC2 (PPC_OPCODE_POWER8 | PPC_OPCODE_E6500)
3475 #define PPCVEC3 PPC_OPCODE_POWER9
3476 #define PPCVSX PPC_OPCODE_VSX
3477 #define PPCVSX2 PPC_OPCODE_POWER8
3478 #define PPCVSX3 PPC_OPCODE_POWER9
3479 #define POWER PPC_OPCODE_POWER
3480 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
3481 #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
3482 #define PPCPWR2 (PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 \
3483 | PPC_OPCODE_COMMON)
3484 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
3485 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
3486 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
3487 #define MFDEC1 PPC_OPCODE_POWER
3488 #define MFDEC2 (PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE \
3489 | PPC_OPCODE_TITAN)
3490 #define BOOKE PPC_OPCODE_BOOKE
3491 #define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS
3492 #define PPCE300 PPC_OPCODE_E300
3493 #define PPCSPE PPC_OPCODE_SPE
3494 #define PPCSPE2 PPC_OPCODE_SPE2
3495 #define PPCISEL PPC_OPCODE_ISEL
3496 #define PPCEFS PPC_OPCODE_EFS
3497 #define PPCEFS2 PPC_OPCODE_EFS2
3498 #define PPCBRLK PPC_OPCODE_BRLOCK
3499 #define PPCPMR PPC_OPCODE_PMR
3500 #define PPCTMR PPC_OPCODE_TMR
3501 #define PPCCHLK PPC_OPCODE_CACHELCK
3502 #define PPCRFMCI PPC_OPCODE_RFMCI
3503 #define E500MC PPC_OPCODE_E500MC
3504 #define PPCA2 PPC_OPCODE_A2
3505 #define TITAN PPC_OPCODE_TITAN
3506 #define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | PPC_OPCODE_476 | TITAN
3507 #define E500 PPC_OPCODE_E500
3508 #define E6500 PPC_OPCODE_E6500
3509 #define PPCVLE PPC_OPCODE_VLE
3510 #define PPCHTM PPC_OPCODE_POWER8
3511 #define E200Z4 PPC_OPCODE_E200Z4
3512 #define PPCLSP PPC_OPCODE_LSP
3513 /* The list of embedded processors that use the embedded operand ordering
3514 for the 3 operand dcbt and dcbtst instructions. */
3515 #define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
3516 | PPC_OPCODE_A2)
3517
3518
3519 \f
3520 /* The opcode table.
3521
3522 The format of the opcode table is:
3523
3524 NAME OPCODE MASK FLAGS ANTI {OPERANDS}
3525
3526 NAME is the name of the instruction.
3527 OPCODE is the instruction opcode.
3528 MASK is the opcode mask; this is used to tell the disassembler
3529 which bits in the actual opcode must match OPCODE.
3530 FLAGS are flags indicating which processors support the instruction.
3531 ANTI indicates which processors don't support the instruction.
3532 OPERANDS is the list of operands.
3533
3534 The disassembler reads the table in order and prints the first
3535 instruction which matches, so this table is sorted to put more
3536 specific instructions before more general instructions.
3537
3538 This table must be sorted by major opcode. Please try to keep it
3539 vaguely sorted within major opcode too, except of course where
3540 constrained otherwise by disassembler operation. */
3541
3542 const struct powerpc_opcode powerpc_opcodes[] = {
3543 {"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476|PPCVLE, {0}},
3544 {"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3545 {"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3546 {"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3547 {"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3548 {"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3549 {"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3550 {"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3551 {"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3552 {"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3553 {"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3554 {"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3555 {"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3556 {"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3557 {"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3558 {"tdui", OPTO(2,TOU), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3559 {"tdi", OP(2), OP_MASK, PPC64, PPCVLE, {TO, RA, SI}},
3560
3561 {"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3562 {"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3563 {"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3564 {"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3565 {"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3566 {"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3567 {"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3568 {"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3569 {"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3570 {"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3571 {"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3572 {"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3573 {"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3574 {"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3575 {"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3576 {"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3577 {"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3578 {"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3579 {"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3580 {"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3581 {"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3582 {"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3583 {"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3584 {"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3585 {"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3586 {"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3587 {"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3588 {"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3589 {"twui", OPTO(3,TOU), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3590 {"tui", OPTO(3,TOU), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3591 {"twi", OP(3), OP_MASK, PPCCOM, PPCVLE, {TO, RA, SI}},
3592 {"ti", OP(3), OP_MASK, PWRCOM, PPCVLE, {TO, RA, SI}},
3593
3594 {"ps_cmpu0", X (4, 0), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3595 {"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3596 {"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
3597 {"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3598 {"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3599 {"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3600 {"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3601 {"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3602 {"vaddfp", VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3603 {"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
3604 {"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3605 {"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
3606 {"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3607 {"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3608 {"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3609 {"ps_sum0", A (4, 10,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3610 {"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3611 {"ps_sum1", A (4, 11,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3612 {"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3613 {"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3614 {"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3615 {"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3616 {"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3617 {"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3618 {"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3619 {"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3620 {"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3621 {"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3622 {"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3623 {"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3624 {"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3625 {"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3626 {"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
3627 {"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3628 {"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3629 {"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3630 {"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3631 {"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3632 {"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3633 {"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3634 {"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3635 {"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3636 {"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3637 {"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3638 {"vsel", VXA(4, 42), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3639 {"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3640 {"vperm", VXA(4, 43), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3641 {"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC, 0, {VD, VA, VB, SHB}},
3642 {"vpermxor", VXA(4, 45), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3643 {"ps_sel", A (4, 23,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3644 {"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
3645 {"ps_sel.", A (4, 23,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3646 {"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
3647 {"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3648 {"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3649 {"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3650 {"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3651 {"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3652 {"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3653 {"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3654 {"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3655 {"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3656 {"ps_msub", A (4, 28,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3657 {"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3658 {"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3659 {"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3660 {"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
3661 {"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3662 {"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3663 {"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3664 {"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3665 {"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3666 {"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3667 {"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3668 {"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3669 {"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3670 {"vadduhm", VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3671 {"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3672 {"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3673 {"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3674 {"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3675 {"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3676 {"vmulouh", VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3677 {"vsubfp", VX (4, 74), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3678 {"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
3679 {"vmrghh", VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3680 {"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
3681 {"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3682 {"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3683 {"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3684 {"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3685 {"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3686 {"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3687 {"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3688 {"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3689 {"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3690 {"ps_cmpu1", X (4, 64), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3691 {"vadduwm", VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3692 {"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3693 {"vrlw", VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3694 {"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3695 {"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3696 {"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3697 {"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3698 {"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3699 {"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3700 {"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3701 {"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3702 {"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3703 {"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3704 {"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3705 {"ps_cmpo1", X (4, 96), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3706 {"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3707 {"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3708 {"vrld", VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3709 {"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3710 {"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3711 {"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3712 {"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3713 {"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3714 {"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3715 {"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3716 {"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3717 {"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3718 {"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3719 {"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3720 {"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3721 {"vmulosb", VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3722 {"vrefp", VX (4, 266), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3723 {"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3724 {"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3725 {"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3726 {"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3727 {"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3728 {"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3729 {"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3730 {"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3731 {"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3732 {"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3733 {"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3734 {"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3735 {"vmulosh", VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3736 {"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3737 {"vmrglh", VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3738 {"vpkswus", VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3739 {"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3740 {"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3741 {"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3742 {"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3743 {"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3744 {"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3745 {"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3746 {"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3747 {"vslw", VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3748 {"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3749 {"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3750 {"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3751 {"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3752 {"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3753 {"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3754 {"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3755 {"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3756 {"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3757 {"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3758 {"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3759 {"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3760 {"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3761 {"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3762 {"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3763 {"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3764 {"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3765 {"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3766 {"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3767 {"vaddubs", VX (4, 512), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3768 {"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
3769 {"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
3770 {"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3771 {"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3772 {"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}},
3773 {"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3774 {"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}},
3775 {"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
3776 {"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3777 {"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}},
3778 {"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3779 {"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}},
3780 {"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}},
3781 {"vrfin", VX (4, 522), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3782 {"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}},
3783 {"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}},
3784 {"vspltb", VX (4, 524), VXUIMM4_MASK, PPCVEC, 0, {VD, VB, UIMM4}},
3785 {"vextractub", VX (4, 525), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3786 {"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}},
3787 {"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}},
3788 {"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3789 {"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3790 {"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3791 {"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3792 {"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3793 {"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3794 {"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3795 {"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
3796 {"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3797 {"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3798 {"evnot", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
3799 {"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3800 {"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3801 {"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3802 {"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3803 {"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3804 {"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3805 {"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3806 {"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3807 {"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3808 {"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3809 {"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3810 {"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}},
3811 {"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3812 {"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}},
3813 {"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3814 {"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3815 {"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3816 {"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3817 {"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3818 {"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3819 {"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3820 {"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3821 {"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3822 {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3823 {"vadduhs", VX (4, 576), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3824 {"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3825 {"vminuh", VX (4, 578), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3826 {"vsrh", VX (4, 580), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3827 {"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3828 {"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3829 {"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3830 {"vsplth", VX (4, 588), VXUIMM3_MASK, PPCVEC, 0, {VD, VB, UIMM3}},
3831 {"vextractuh", VX (4, 589), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3832 {"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3833 {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3834 {"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}},
3835 {"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3836 {"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3837 {"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3838 {"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3839 {"evfsmadd", VX (4, 642), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3840 {"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3841 {"evfsmsub", VX (4, 643), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3842 {"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}},
3843 {"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3844 {"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}},
3845 {"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}},
3846 {"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3847 {"evfssqrt", VX_RB_CONST(4, 647, 0), VX_RB_CONST_MASK, PPCEFS2, 0, {RD, RA}},
3848 {"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3849 {"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3850 {"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3851 {"evfsnmadd", VX (4, 650), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3852 {"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3853 {"evfsnmsub", VX (4, 651), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3854 {"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3855 {"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}},
3856 {"vextractuw", VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3857 {"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3858 {"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3859 {"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3860 {"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}},
3861 {"evfscfh", VX_RA_CONST(4, 657, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
3862 {"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}},
3863 {"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}},
3864 {"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}},
3865 {"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}},
3866 {"evfscth", VX_RA_CONST(4, 661, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
3867 {"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}},
3868 {"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}},
3869 {"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}},
3870 {"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}},
3871 {"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3872 {"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}},
3873 {"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3874 {"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3875 {"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3876 {"evfsmax", VX (4, 672), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
3877 {"evfsmin", VX (4, 673), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
3878 {"evfsaddsub", VX (4, 674), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
3879 {"evfssubadd", VX (4, 675), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
3880 {"evfssum", VX (4, 676), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
3881 {"evfsdiff", VX (4, 677), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
3882 {"evfssumdiff", VX (4, 678), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
3883 {"evfsdiffsum", VX (4, 679), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
3884 {"evfsaddx", VX (4, 680), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
3885 {"evfssubx", VX (4, 681), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
3886 {"evfsaddsubx", VX (4, 682), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
3887 {"evfssubaddx", VX (4, 683), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
3888 {"evfsmulx", VX (4, 684), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
3889 {"evfsmule", VX (4, 686), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
3890 {"evfsmulo", VX (4, 687), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
3891 {"efsmax", VX (4, 688), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
3892 {"efsmin", VX (4, 689), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
3893 {"efdmax", VX (4, 696), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
3894 {"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3895 {"efdmin", VX (4, 697), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
3896 {"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3897 {"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3898 {"efsmadd", VX (4, 706), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
3899 {"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3900 {"efsmsub", VX (4, 707), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
3901 {"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
3902 {"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3903 {"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
3904 {"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
3905 {"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3906 {"efssqrt", VX_RB_CONST(4, 711, 0), VX_RB_CONST_MASK,PPCEFS2, 0, {RD, RA}},
3907 {"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3908 {"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3909 {"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3910 {"efsnmadd", VX (4, 714), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
3911 {"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3912 {"efsnmsub", VX (4, 715), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
3913 {"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3914 {"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3915 {"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3916 {"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3917 {"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3918 {"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}},
3919 {"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
3920 {"efscfh", VX_RA_CONST(4, 721, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
3921 {"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
3922 {"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
3923 {"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
3924 {"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
3925 {"efscth", VX_RA_CONST(4, 725, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
3926 {"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
3927 {"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
3928 {"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
3929 {"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},
3930 {"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3931 {"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},
3932 {"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3933 {"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3934 {"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3935 {"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3936 {"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3937 {"efdmadd", VX (4, 738), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}},
3938 {"efdcfuid", VX (4, 738), VX_MASK, E500|E500MC,0, {RS, RB}},
3939 {"efdmsub", VX (4, 739), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}},
3940 {"efdcfsid", VX (4, 739), VX_MASK, E500|E500MC,0, {RS, RB}},
3941 {"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}},
3942 {"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}},
3943 {"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}},
3944 {"efdsqrt", VX_RB_CONST(4, 743, 0), VX_RB_CONST_MASK, PPCEFS2, 0, {RD, RA}},
3945 {"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3946 {"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3947 {"efdnmadd", VX (4, 746), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}},
3948 {"efdctuidz", VX (4, 746), VX_MASK, E500|E500MC,0, {RS, RB}},
3949 {"efdnmsub", VX (4, 747), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}},
3950 {"efdctsidz", VX (4, 747), VX_MASK, E500|E500MC,0, {RS, RB}},
3951 {"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3952 {"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3953 {"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3954 {"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}},
3955 {"efdcfui", VX_RA_CONST(4, 752, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}},
3956 {"efdcfuid", VX_RA_CONST(4, 752, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}},
3957 {"efdcfsi", VX_RA_CONST(4, 753, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}},
3958 {"efdcfsid", VX_RA_CONST(4, 753, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}},
3959 {"efdcfh", VX_RA_CONST(4, 753, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
3960 {"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}},
3961 {"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}},
3962 {"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}},
3963 {"efdcth", VX_RA_CONST(4, 757, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
3964 {"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}},
3965 {"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}},
3966 {"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}},
3967 {"efdctuiz", VX_RA_CONST(4, 760, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}},
3968 {"efdctuidz", VX_RA_CONST(4, 760, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}},
3969 {"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3970 {"efdctsiz", VX_RA_CONST(4, 762, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}},
3971 {"efdctsidz", VX_RA_CONST(4, 762, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}},
3972 {"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3973 {"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3974 {"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3975 {"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3976 {"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3977 {"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3978 {"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3979 {"vminsb", VX (4, 770), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3980 {"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3981 {"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3982 {"vsrab", VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3983 {"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3984 {"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3985 {"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3986 {"vmulesb", VX (4, 776), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3987 {"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
3988 {"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3989 {"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3990 {"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3991 {"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
3992 {"vinsertb", VX (4, 781), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3993 {"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
3994 {"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3995 {"vpkpx", VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3996 {"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
3997 {"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3998 {"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3999 {"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}},
4000 {"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
4001 {"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4002 {"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
4003 {"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4004 {"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
4005 {"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
4006 {"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4007 {"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
4008 {"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
4009 {"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4010 {"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
4011 {"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4012 {"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
4013 {"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4014 {"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
4015 {"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4016 {"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
4017 {"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4018 {"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
4019 {"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4020 {"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
4021 {"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4022 {"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
4023 {"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4024 {"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
4025 {"vaddshs", VX (4, 832), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4026 {"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
4027 {"vminsh", VX (4, 834), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4028 {"vsrah", VX (4, 836), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4029 {"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
4030 {"vmulesh", VX (4, 840), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4031 {"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
4032 {"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
4033 {"vspltish", VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
4034 {"vinserth", VX (4, 845), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
4035 {"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC, 0, {VD, VB}},
4036 {"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}},
4037 {"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}},
4038 {"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
4039 {"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
4040 {"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
4041 {"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
4042 {"vaddsws", VX (4, 896), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4043 {"vminsw", VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4044 {"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4045 {"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
4046 {"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4047 {"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
4048 {"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
4049 {"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
4050 {"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
4051 {"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
4052 {"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4053 {"vminsd", VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4054 {"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4055 {"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
4056 {"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
4057 {"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
4058 {"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
4059 {"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
4060 {"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}},
4061 {"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
4062 {"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4063 {"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
4064 {"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4065 {"vsububm", VX (4,1024), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4066 {"bcdadd.", VX (4,1025), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
4067 {"vavgub", VX (4,1026), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4068 {"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4069 {"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4070 {"vand", VX (4,1028), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4071 {"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
4072 {"vcmpneb.", VXR(4, 7,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
4073 {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
4074 {"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
4075 {"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4076 {"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4077 {"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4078 {"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4079 {"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4080 {"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4081 {"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4082 {"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4083 {"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4084 {"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4085 {"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
4086 {"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4087 {"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
4088 {"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
4089 {"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4090 {"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4091 {"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4092 {"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4093 {"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4094 {"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4095 {"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4096 {"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4097 {"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4098 {"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
4099 {"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4100 {"evmwlssf", VX (4,1091), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
4101 {"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4102 {"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4103 {"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
4104 {"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
4105 {"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
4106 {"vcmpneh.", VXR(4, 71,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
4107 {"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4108 {"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4109 {"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4110 {"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4111 {"evmwlsmf", VX (4,1099), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
4112 {"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4113 {"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4114 {"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4115 {"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4116 {"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4117 {"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4118 {"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
4119 {"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4120 {"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4121 {"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4122 {"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4123 {"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
4124 {"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4125 {"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
4126 {"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
4127 {"evmwlssfa", VX (4,1123), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
4128 {"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4129 {"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4130 {"evmwlsmfa", VX (4,1131), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
4131 {"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4132 {"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4133 {"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4134 {"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4135 {"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4136 {"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4137 {"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4138 {"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4139 {"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
4140 {"vavguw", VX (4,1154), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4141 {"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4142 {"vmr", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
4143 {"vor", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4144 {"vcmpnew.", VXR(4, 135,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
4145 {"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4146 {"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
4147 {"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
4148 {"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
4149 {"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
4150 {"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4151 {"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
4152 {"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
4153 {"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4154 {"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}},
4155 {"bcds.", VX (4,1217), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
4156 {"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}},
4157 {"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}},
4158 {"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}},
4159 {"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}},
4160 {"vxor", VX (4,1220), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4161 {"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4162 {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
4163 {"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
4164 {"vcmpequd.", VXR(4, 199,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
4165 {"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
4166 {"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4167 {"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4168 {"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}},
4169 {"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}},
4170 {"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}},
4171 {"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}},
4172 {"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4173 {"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
4174 {"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4175 {"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
4176 {"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4177 {"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
4178 {"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
4179 {"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4180 {"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4181 {"bcdtrunc.", VX (4,1281), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
4182 {"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4183 {"vavgsb", VX (4,1282), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4184 {"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4185 {"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4186 {"vnot", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
4187 {"vnor", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4188 {"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4189 {"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
4190 {"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
4191 {"vcmpnezb.", VXR(4, 263,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
4192 {"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4193 {"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4194 {"vcipher", VX (4,1288), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4195 {"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4196 {"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4197 {"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4198 {"vgbbd", VX (4,1292), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
4199 {"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4200 {"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4201 {"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4202 {"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
4203 {"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4204 {"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4205 {"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4206 {"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4207 {"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4208 {"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4209 {"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4210 {"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4211 {"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4212 {"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
4213 {"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4214 {"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4215 {"evmwlssfaaw", VX (4,1347), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
4216 {"evmwhusiaa", VX (4,1348), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
4217 {"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4218 {"evmwhssmaa", VX (4,1349), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
4219 {"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
4220 {"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
4221 {"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
4222 {"evmwhssfaa", VX (4,1351), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
4223 {"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4224 {"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4225 {"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4226 {"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4227 {"evmwlsmfaaw", VX (4,1355), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
4228 {"evmwhumiaa", VX (4,1356), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
4229 {"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4230 {"evmwhsmiaa", VX (4,1357), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
4231 {"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4232 {"evmwhsmfaa", VX (4,1359), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
4233 {"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4234 {"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
4235 {"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4236 {"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4237 {"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4238 {"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4239 {"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
4240 {"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4241 {"evmwhgumiaa", VX (4,1380), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
4242 {"evmwhgsmiaa", VX (4,1381), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
4243 {"evmwhgssfaa", VX (4,1383), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
4244 {"evmwhgsmfaa", VX (4,1391), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
4245 {"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4246 {"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4247 {"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4248 {"bcdctsq.", VXVA(4,1409,0), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4249 {"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
4250 {"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
4251 {"bcdctn.", VXVA(4,1409,5), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4252 {"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
4253 {"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
4254 {"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
4255 {"vavgsw", VX (4,1410), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4256 {"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4257 {"vnand", VX (4,1412), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4258 {"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4259 {"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4260 {"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
4261 {"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
4262 {"vcmpnezw.", VXR(4, 391,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
4263 {"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4264 {"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4265 {"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4266 {"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4267 {"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4268 {"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4269 {"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4270 {"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
4271 {"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4272 {"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4273 {"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4274 {"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4275 {"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4276 {"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4277 {"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4278 {"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4279 {"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
4280 {"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4281 {"evmwlssfanw", VX (4,1475), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
4282 {"evmwhusian", VX (4,1476), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
4283 {"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4284 {"evmwhssian", VX (4,1477), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
4285 {"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
4286 {"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
4287 {"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
4288 {"evmwhssfan", VX (4,1479), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
4289 {"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}},
4290 {"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4291 {"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4292 {"evmwlsmfanw", VX (4,1483), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
4293 {"evmwhumian", VX (4,1484), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
4294 {"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
4295 {"evmwhsmian", VX (4,1485), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
4296 {"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4297 {"evmwhsmfan", VX (4,1487), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
4298 {"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4299 {"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
4300 {"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4301 {"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4302 {"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4303 {"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4304 {"evmwhgumian", VX (4,1508), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
4305 {"evmwhgsmian", VX (4,1509), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
4306 {"evmwhgssfan", VX (4,1511), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
4307 {"evmwhgsmfan", VX (4,1519), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
4308 {"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
4309 {"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4310 {"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4311 {"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
4312 {"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
4313 {"vnegw", VXVA(4,1538,6), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4314 {"vnegd", VXVA(4,1538,7), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4315 {"vprtybw", VXVA(4,1538,8), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4316 {"vprtybd", VXVA(4,1538,9), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4317 {"vprtybq", VXVA(4,1538,10), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4318 {"vextsb2w", VXVA(4,1538,16), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4319 {"vextsh2w", VXVA(4,1538,17), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4320 {"vextsb2d", VXVA(4,1538,24), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4321 {"vextsh2d", VXVA(4,1538,25), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4322 {"vextsw2d", VXVA(4,1538,26), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4323 {"vctzb", VXVA(4,1538,28), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4324 {"vctzh", VXVA(4,1538,29), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4325 {"vctzw", VXVA(4,1538,30), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4326 {"vctzd", VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4327 {"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC, 0, {VD}},
4328 {"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
4329 {"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
4330 {"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
4331 {"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4332 {"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
4333 {"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4334 {"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC, 0, {VB}},
4335 {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
4336 {"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4337 {"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
4338 {"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
4339 {"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
4340 {"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
4341 {"vsubuws", VX (4,1664), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4342 {"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
4343 {"veqv", VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4344 {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
4345 {"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
4346 {"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
4347 {"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4348 {"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4349 {"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
4350 {"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
4351 {"vsrd", VX (4,1732), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4352 {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
4353 {"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
4354 {"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
4355 {"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
4356 {"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
4357 {"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4358 {"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
4359 {"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
4360 {"vsrv", VX (4,1796), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
4361 {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
4362 {"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
4363 {"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
4364 {"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4365 {"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
4366 {"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
4367 {"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4368 {"vsubshs", VX (4,1856), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4369 {"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
4370 {"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
4371 {"vslv", VX (4,1860), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
4372 {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
4373 {"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
4374 {"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
4375 {"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
4376 {"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
4377 {"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4378 {"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
4379 {"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4380 {"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4381 {"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
4382 {"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
4383 {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
4384 {"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
4385 {"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
4386 {"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4387 {"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4388 {"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
4389 {"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
4390 {"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4391 {"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
4392 {"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
4393 {"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
4394 {"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
4395 {"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
4396 {"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
4397 {"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
4398 {"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4399 {"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
4400 {"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4401 {"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}},
4402
4403 {"mulli", OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
4404 {"muli", OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
4405
4406 {"subfic", OP(8), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
4407 {"sfi", OP(8), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
4408
4409 {"dozi", OP(9), OP_MASK, M601, PPCVLE, {RT, RA, SI}},
4410
4411 {"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, UISIGNOPT}},
4412 {"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, UISIGNOPT}},
4413 {"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, UISIGNOPT}},
4414 {"cmpli", OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}},
4415
4416 {"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, SI}},
4417 {"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, SI}},
4418 {"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, SI}},
4419 {"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}},
4420
4421 {"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
4422 {"ai", OP(12), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
4423 {"subic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
4424
4425 {"addic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
4426 {"ai.", OP(13), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
4427 {"subic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
4428
4429 {"li", OP(14), DRA_MASK, PPCCOM, PPCVLE, {RT, SI}},
4430 {"lil", OP(14), DRA_MASK, PWRCOM, PPCVLE, {RT, SI}},
4431 {"addi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SI}},
4432 {"cal", OP(14), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
4433 {"subi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSI}},
4434 {"la", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
4435
4436 {"lis", OP(15), DRA_MASK, PPCCOM, PPCVLE, {RT, SISIGNOPT}},
4437 {"liu", OP(15), DRA_MASK, PWRCOM, PPCVLE, {RT, SISIGNOPT}},
4438 {"addis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
4439 {"cau", OP(15), OP_MASK, PWRCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
4440 {"subis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSISIGNOPT}},
4441
4442 {"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
4443 {"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
4444 {"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}},
4445 {"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}},
4446 {"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
4447 {"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
4448 {"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}},
4449 {"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}},
4450 {"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
4451 {"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
4452 {"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}},
4453 {"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}},
4454 {"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
4455 {"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
4456 {"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}},
4457 {"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}},
4458 {"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
4459 {"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
4460 {"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCVLE, {BD}},
4461 {"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
4462 {"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
4463 {"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCVLE, {BD}},
4464 {"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
4465 {"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
4466 {"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCVLE, {BDA}},
4467 {"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
4468 {"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
4469 {"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCVLE, {BDA}},
4470
4471 {"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4472 {"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4473 {"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4474 {"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4475 {"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4476 {"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4477 {"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4478 {"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4479 {"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4480 {"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4481 {"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4482 {"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4483 {"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4484 {"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4485 {"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4486 {"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4487 {"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4488 {"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4489 {"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4490 {"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4491 {"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4492 {"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4493 {"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4494 {"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4495 {"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4496 {"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4497 {"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4498 {"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4499 {"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4500 {"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4501 {"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4502 {"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4503 {"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4504 {"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4505 {"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4506 {"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4507 {"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4508 {"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4509 {"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4510 {"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4511 {"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4512 {"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4513 {"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4514 {"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4515 {"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4516 {"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4517 {"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4518 {"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4519 {"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4520 {"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4521 {"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4522 {"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4523 {"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4524 {"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4525 {"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4526 {"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4527 {"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4528 {"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4529 {"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4530 {"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4531 {"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4532 {"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4533 {"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4534 {"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4535 {"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4536 {"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4537 {"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4538 {"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4539 {"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4540 {"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4541 {"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4542 {"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4543 {"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4544 {"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4545 {"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4546 {"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4547 {"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4548 {"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4549 {"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4550 {"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4551 {"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4552 {"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4553 {"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4554 {"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4555
4556 {"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4557 {"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4558 {"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4559 {"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4560 {"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4561 {"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4562 {"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4563 {"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4564 {"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4565 {"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4566 {"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4567 {"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4568 {"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4569 {"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4570 {"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4571 {"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4572 {"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4573 {"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4574 {"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4575 {"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4576 {"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4577 {"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4578 {"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4579 {"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4580 {"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4581 {"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4582 {"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4583 {"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4584 {"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4585 {"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4586 {"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4587 {"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4588 {"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4589 {"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4590 {"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4591 {"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4592 {"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4593 {"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4594 {"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4595 {"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4596 {"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4597 {"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4598 {"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4599 {"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4600 {"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4601 {"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4602 {"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4603 {"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4604 {"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4605 {"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4606 {"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4607 {"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4608 {"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4609 {"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4610 {"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4611 {"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4612 {"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4613 {"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4614 {"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4615 {"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4616
4617 {"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4618 {"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4619 {"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4620 {"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4621 {"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4622 {"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4623 {"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4624 {"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4625 {"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4626 {"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4627 {"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4628 {"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4629 {"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4630 {"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4631 {"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4632 {"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4633 {"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4634 {"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4635 {"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4636 {"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4637 {"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4638 {"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4639 {"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4640 {"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4641
4642 {"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4643 {"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4644 {"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4645 {"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4646 {"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4647 {"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4648 {"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4649 {"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4650 {"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4651 {"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4652 {"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4653 {"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4654 {"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4655 {"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4656 {"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4657 {"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4658
4659 {"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4660 {"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4661 {"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4662 {"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4663 {"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4664 {"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4665 {"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4666 {"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4667 {"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4668 {"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4669 {"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4670 {"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4671 {"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4672 {"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4673 {"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4674 {"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4675 {"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4676 {"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4677 {"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4678 {"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4679 {"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4680 {"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4681 {"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4682 {"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4683
4684 {"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4685 {"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4686 {"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4687 {"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4688 {"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4689 {"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4690 {"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4691 {"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4692 {"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4693 {"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4694 {"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4695 {"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4696 {"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4697 {"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4698 {"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4699 {"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4700
4701 {"bc-", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}},
4702 {"bc+", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}},
4703 {"bc", B(16,0,0), B_MASK, COM, PPCVLE, {BO, BI, BD}},
4704 {"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}},
4705 {"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}},
4706 {"bcl", B(16,0,1), B_MASK, COM, PPCVLE, {BO, BI, BD}},
4707 {"bca-", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}},
4708 {"bca+", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}},
4709 {"bca", B(16,1,0), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
4710 {"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}},
4711 {"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}},
4712 {"bcla", B(16,1,1), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
4713
4714 {"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
4715 {"scv", SC(17,0,1), SC_MASK, POWER9, PPCVLE, {SVC_LEV}},
4716 {"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
4717 {"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}},
4718 {"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}},
4719 {"svcla", SC(17,1,1), SC_MASK, POWER, PPCVLE, {SV}},
4720
4721 {"b", B(18,0,0), B_MASK, COM, PPCVLE, {LI}},
4722 {"bl", B(18,0,1), B_MASK, COM, PPCVLE, {LI}},
4723 {"ba", B(18,1,0), B_MASK, COM, PPCVLE, {LIA}},
4724 {"bla", B(18,1,1), B_MASK, COM, PPCVLE, {LIA}},
4725
4726 {"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
4727
4728 {"lnia", DX(19,2), NODX_MASK, POWER9, PPCVLE, {RT}},
4729 {"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}},
4730 {"subpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, NDXD}},
4731
4732 {"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4733 {"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4734 {"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4735 {"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4736 {"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4737 {"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4738 {"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4739 {"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4740 {"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4741 {"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4742 {"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4743 {"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4744 {"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4745 {"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}},
4746 {"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4747 {"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}},
4748 {"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4749 {"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4750 {"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4751 {"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4752 {"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4753 {"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4754 {"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4755 {"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4756
4757 {"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4758 {"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4759 {"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4760 {"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4761 {"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4762 {"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4763 {"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4764 {"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4765 {"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4766 {"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4767 {"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4768 {"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4769 {"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4770 {"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4771 {"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4772 {"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4773 {"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4774 {"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4775 {"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4776 {"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4777 {"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4778 {"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4779 {"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4780 {"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4781 {"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4782 {"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4783 {"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4784 {"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4785 {"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4786 {"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4787 {"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4788 {"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4789 {"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4790 {"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4791 {"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4792 {"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4793 {"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4794 {"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4795 {"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4796 {"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4797 {"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4798 {"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4799 {"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4800 {"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4801 {"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4802 {"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4803 {"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4804 {"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4805 {"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4806 {"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4807 {"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4808 {"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4809 {"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4810 {"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4811 {"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4812 {"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4813 {"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4814 {"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4815 {"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4816 {"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4817 {"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4818 {"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4819 {"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4820 {"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4821 {"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4822 {"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4823 {"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4824 {"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4825 {"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4826 {"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4827 {"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4828 {"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4829 {"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4830 {"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4831 {"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4832 {"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4833 {"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4834 {"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4835 {"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4836 {"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4837 {"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4838 {"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4839 {"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4840 {"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4841 {"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4842 {"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4843 {"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4844 {"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4845 {"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4846 {"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4847 {"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4848 {"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4849 {"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4850 {"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4851 {"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4852 {"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4853 {"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4854 {"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4855 {"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4856 {"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4857 {"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4858 {"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4859 {"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4860 {"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4861 {"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4862 {"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4863 {"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4864 {"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4865 {"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4866 {"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4867 {"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4868 {"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4869 {"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4870 {"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4871 {"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4872 {"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4873 {"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4874 {"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4875 {"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4876 {"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4877 {"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4878 {"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4879 {"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4880 {"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4881 {"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4882 {"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4883 {"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4884 {"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4885 {"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4886 {"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4887 {"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4888 {"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4889 {"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4890 {"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4891 {"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4892 {"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4893 {"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4894 {"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4895 {"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4896 {"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4897
4898 {"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4899 {"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4900 {"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4901 {"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4902 {"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4903 {"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4904 {"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4905 {"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4906 {"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4907 {"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4908 {"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4909 {"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4910 {"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4911 {"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4912 {"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4913 {"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4914 {"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4915 {"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4916 {"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4917 {"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4918 {"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4919 {"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4920 {"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4921 {"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4922 {"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4923 {"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4924 {"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4925 {"bdnztlrl-", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4926 {"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4927 {"bdnztlrl+", XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4928 {"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4929 {"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4930 {"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4931 {"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4932 {"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4933 {"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4934 {"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4935 {"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4936 {"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4937 {"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4938 {"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4939 {"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4940 {"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4941 {"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4942 {"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4943 {"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4944 {"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4945 {"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4946
4947 {"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4948 {"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4949 {"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4950 {"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4951 {"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4952 {"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4953 {"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4954 {"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4955
4956 {"rfid", XL(19,18), 0xffffffff, PPC64, PPCVLE, {0}},
4957
4958 {"crnot", XL(19,33), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}},
4959 {"crnor", XL(19,33), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4960 {"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCVLE, {0}},
4961
4962 {"rfdi", XL(19,39), 0xffffffff, E500MC, PPCVLE, {0}},
4963 {"rfi", XL(19,50), 0xffffffff, COM, PPCVLE, {0}},
4964 {"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}},
4965
4966 {"rfscv", XL(19,82), 0xffffffff, POWER9, PPCVLE, {0}},
4967 {"rfsvc", XL(19,82), 0xffffffff, POWER, PPCVLE, {0}},
4968
4969 {"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCVLE, {0}},
4970
4971 {"crandc", XL(19,129), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4972
4973 {"rfebb", XL(19,146), XLS_MASK, POWER8, PPCVLE, {SXL}},
4974
4975 {"isync", XL(19,150), 0xffffffff, PPCCOM, PPCVLE, {0}},
4976 {"ics", XL(19,150), 0xffffffff, PWRCOM, PPCVLE, {0}},
4977
4978 {"crclr", XL(19,193), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}},
4979 {"crxor", XL(19,193), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4980
4981 {"dnh", X(19,198), X_MASK, E500MC, PPCVLE, {DUI, DUIS}},
4982
4983 {"crnand", XL(19,225), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4984
4985 {"crand", XL(19,257), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4986
4987 {"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPC476|PPCVLE, {0}},
4988
4989 {"crset", XL(19,289), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}},
4990 {"creqv", XL(19,289), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4991
4992 {"urfid", XL(19,306), 0xffffffff, POWER9, PPCVLE, {0}},
4993 {"stop", XL(19,370), 0xffffffff, POWER9, PPCVLE, {0}},
4994
4995 {"doze", XL(19,402), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4996
4997 {"crorc", XL(19,417), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4998
4999 {"nap", XL(19,434), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
5000
5001 {"crmove", XL(19,449), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}},
5002 {"cror", XL(19,449), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
5003
5004 {"sleep", XL(19,466), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
5005 {"rvwinkle", XL(19,498), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
5006
5007 {"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCVLE, {0}},
5008 {"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCVLE, {0}},
5009
5010 {"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
5011 {"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5012 {"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
5013 {"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5014 {"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
5015 {"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5016 {"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
5017 {"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5018 {"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
5019 {"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5020 {"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
5021 {"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5022 {"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
5023 {"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5024 {"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
5025 {"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5026 {"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
5027 {"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5028 {"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
5029 {"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5030 {"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
5031 {"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5032 {"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
5033 {"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5034 {"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
5035 {"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5036 {"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
5037 {"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5038 {"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5039 {"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5040 {"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5041 {"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5042 {"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5043 {"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5044 {"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5045 {"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5046 {"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5047 {"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5048 {"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5049 {"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5050 {"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5051 {"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5052 {"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5053 {"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5054 {"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5055 {"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5056 {"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5057 {"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5058 {"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5059 {"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5060 {"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5061 {"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5062 {"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5063 {"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5064 {"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5065 {"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5066 {"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5067 {"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5068 {"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5069 {"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5070 {"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5071 {"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5072 {"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5073 {"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5074 {"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5075 {"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5076 {"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5077 {"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5078 {"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5079 {"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5080 {"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
5081 {"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5082 {"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
5083 {"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5084 {"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
5085 {"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5086 {"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
5087 {"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5088 {"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
5089 {"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5090 {"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
5091 {"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5092 {"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
5093 {"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5094 {"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
5095 {"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5096 {"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
5097 {"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5098 {"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
5099 {"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5100 {"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5101 {"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5102 {"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5103 {"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5104 {"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5105 {"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5106 {"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5107 {"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5108 {"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5109 {"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
5110 {"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5111 {"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5112 {"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5113 {"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5114 {"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5115 {"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5116 {"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5117 {"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5118 {"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5119 {"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5120 {"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5121 {"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5122 {"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5123 {"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5124 {"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5125 {"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5126 {"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5127 {"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5128 {"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5129 {"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
5130
5131 {"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
5132 {"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
5133 {"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
5134 {"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
5135 {"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
5136 {"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
5137 {"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
5138 {"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
5139 {"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
5140 {"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
5141 {"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
5142 {"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
5143 {"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
5144 {"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
5145 {"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
5146 {"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
5147 {"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
5148 {"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
5149 {"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
5150 {"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
5151
5152 {"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
5153 {"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
5154 {"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
5155 {"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
5156 {"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
5157 {"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
5158 {"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
5159 {"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
5160
5161 {"bctar-", XLYLK(19,560,0,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
5162 {"bctarl-", XLYLK(19,560,0,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
5163 {"bctar+", XLYLK(19,560,1,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
5164 {"bctarl+", XLYLK(19,560,1,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
5165 {"bctar", XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}},
5166 {"bctarl", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}},
5167
5168 {"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
5169 {"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
5170
5171 {"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
5172 {"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
5173
5174 {"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
5175 {"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},
5176 {"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
5177 {"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
5178 {"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
5179 {"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},
5180 {"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
5181 {"rlinm.", M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
5182
5183 {"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
5184 {"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
5185
5186 {"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
5187 {"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
5188 {"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
5189 {"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
5190 {"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
5191 {"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
5192
5193 {"nop", OP(24), 0xffffffff, PPCCOM, PPCVLE, {0}},
5194 {"ori", OP(24), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
5195 {"oril", OP(24), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
5196
5197 {"oris", OP(25), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
5198 {"oriu", OP(25), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
5199
5200 {"xnop", OP(26), 0xffffffff, PPCCOM, PPCVLE, {0}},
5201 {"xori", OP(26), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
5202 {"xoril", OP(26), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
5203
5204 {"xoris", OP(27), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
5205 {"xoriu", OP(27), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
5206
5207 {"andi.", OP(28), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
5208 {"andil.", OP(28), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
5209
5210 {"andis.", OP(29), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
5211 {"andiu.", OP(29), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
5212
5213 {"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}},
5214 {"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}},
5215 {"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
5216 {"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}},
5217 {"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}},
5218 {"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
5219
5220 {"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
5221 {"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
5222
5223 {"rldic", MD(30,2,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
5224 {"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
5225
5226 {"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
5227 {"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
5228
5229 {"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},
5230 {"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
5231 {"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},
5232 {"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
5233
5234 {"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
5235 {"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
5236
5237 {"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
5238 {"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
5239 {"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
5240 {"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
5241
5242 {"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
5243 {"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
5244 {"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
5245 {"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
5246 {"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, 0, {RA, RB}},
5247 {"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, 0, {RA, RB}},
5248 {"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
5249 {"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
5250 {"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, 0, {RA, RB}},
5251 {"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, 0, {RA, RB}},
5252 {"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
5253 {"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
5254 {"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, 0, {RA, RB}},
5255 {"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, 0, {RA, RB}},
5256 {"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
5257 {"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
5258 {"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
5259 {"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
5260 {"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, 0, {RA, RB}},
5261 {"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, 0, {RA, RB}},
5262 {"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
5263 {"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
5264 {"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
5265 {"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
5266 {"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, 0, {RA, RB}},
5267 {"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, 0, {RA, RB}},
5268 {"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, 0, {RA, RB}},
5269 {"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, 0, {RA, RB}},
5270 {"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, 0, {0}},
5271 {"twu", XTO(31,4,TOU), XTO_MASK, PPCCOM, 0, {RA, RB}},
5272 {"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}},
5273 {"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}},
5274 {"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}},
5275
5276 {"lvsl", X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
5277 {"lvebx", X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
5278 {"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5279
5280 {"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5281 {"sf", XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5282 {"subc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
5283 {"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5284 {"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5285 {"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
5286
5287 {"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5288 {"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5289
5290 {"addc", XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5291 {"a", XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5292 {"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5293 {"a.", XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5294
5295 {"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5296 {"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5297
5298 {"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
5299
5300 {"isellt", X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
5301
5302 {"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, 0, {0}},
5303 {"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, 0, {0}},
5304 {"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, 0, {RA0, RB}},
5305 {"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}},
5306
5307 {"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, COM, 0, {RT, FXM4}},
5308 {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, 0, {RT, FXM}},
5309
5310 {"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}},
5311
5312 {"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}},
5313
5314 {"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, 0, {CT, RA0, RB}},
5315
5316 {"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
5317 {"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},
5318
5319 {"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
5320 {"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
5321 {"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
5322 {"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
5323
5324 {"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
5325 {"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
5326 {"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
5327 {"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
5328
5329 {"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}},
5330 {"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}},
5331
5332 {"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}},
5333 {"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}},
5334
5335 {"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}},
5336 {"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}},
5337
5338 {"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
5339
5340 {"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}},
5341 {"wait", X(31,30), XWC_MASK, POWER9, 0, {WC}},
5342
5343 {"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
5344
5345 {"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
5346 {"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
5347 {"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
5348 {"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
5349
5350 {"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
5351 {"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
5352 {"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5353
5354 {"mviwsplt", X(31,46), X_MASK, E6500, 0, {VD, RA, RB}},
5355
5356 {"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
5357
5358 {"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
5359
5360 {"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}},
5361
5362 {"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
5363
5364 {"iseleq", X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
5365
5366 {"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, CRB}},
5367
5368 {"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5369 {"sub", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RB, RA}},
5370 {"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5371 {"sub.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}},
5372
5373 {"mfvsrd", X(31,51), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
5374 {"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
5375 {"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
5376 {"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}},
5377
5378 {"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
5379
5380 {"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}},
5381
5382 {"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}},
5383
5384 {"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}},
5385 {"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}},
5386
5387 {"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, 0, {RA, RS}},
5388 {"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, 0, {RA, RS}},
5389
5390 {"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}},
5391 {"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}},
5392
5393 {"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, 0, {0}},
5394 {"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, 0, {0}},
5395 {"wait", X(31,62), XWC_MASK, E500MC|PPCA2, 0, {WC}},
5396
5397 {"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
5398
5399 {"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, 0, {RA, RB}},
5400 {"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, 0, {RA, RB}},
5401 {"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, 0, {RA, RB}},
5402 {"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, 0, {RA, RB}},
5403 {"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, 0, {RA, RB}},
5404 {"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, 0, {RA, RB}},
5405 {"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, 0, {RA, RB}},
5406 {"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, 0, {RA, RB}},
5407 {"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, 0, {RA, RB}},
5408 {"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, 0, {RA, RB}},
5409 {"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, 0, {RA, RB}},
5410 {"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, 0, {RA, RB}},
5411 {"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, 0, {RA, RB}},
5412 {"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, 0, {RA, RB}},
5413 {"tdu", XTO(31,68,TOU), XTO_MASK, PPC64, 0, {RA, RB}},
5414 {"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}},
5415
5416 {"lwfcmx", APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5417 {"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5418 {"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5419
5420 {"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5421 {"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5422
5423 {"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA, RS, RB}},
5424 {"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA, RS, RB}},
5425
5426 {"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, 0, {SR, RS}},
5427
5428 {"mfmsr", X(31,83), XRARB_MASK, COM, 0, {RT}},
5429
5430 {"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}},
5431
5432 {"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}},
5433 {"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L2OPT}},
5434
5435 {"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}},
5436
5437 {"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
5438
5439 {"dni", XRC(31,97,1), XRB_MASK, E6500, 0, {DUI, DCTL}},
5440
5441 {"lvx", X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
5442 {"lqfcmx", APU(31,103,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5443
5444 {"neg", XO(31,104,0,0), XORB_MASK, COM, 0, {RT, RA}},
5445 {"neg.", XO(31,104,0,1), XORB_MASK, COM, 0, {RT, RA}},
5446
5447 {"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5448 {"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5449
5450 {"mvidsplt", X(31,110), X_MASK, E6500, 0, {VD, RA, RB}},
5451
5452 {"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}},
5453
5454 {"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
5455 {"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
5456 {"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
5457
5458 {"lharx", X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
5459
5460 {"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}},
5461
5462 {"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}},
5463
5464 {"popcntb", X(31,122), XRB_MASK, POWER5, 0, {RA, RS}},
5465
5466 {"not", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RBS}},
5467 {"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}},
5468 {"not.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RBS}},
5469 {"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}},
5470
5471 {"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
5472
5473 {"setb", X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}},
5474
5475 {"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}},
5476
5477 {"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5478
5479 {"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5480 {"stbfcmx", APU(31,135,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5481
5482 {"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5483 {"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5484 {"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5485 {"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5486
5487 {"adde", XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5488 {"ae", XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5489 {"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5490 {"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5491
5492 {"stxsiwx", X(31,140), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
5493
5494 {"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK, POWER8, 0, {RB}},
5495 {"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
5496
5497 {"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, 0, {RS}},
5498 {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, 0, {FXM, RS}},
5499 {"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, 0, {FXM, RS}},
5500
5501 {"mtmsr", X(31,146), XRLARB_MASK, COM, 0, {RS, A_L}},
5502
5503 {"mtsle", X(31,147), XRTLRARB_MASK, POWER8, 0, {L}},
5504
5505 {"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}},
5506 {"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
5507
5508 {"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}},
5509
5510 {"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}},
5511
5512 {"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
5513 {"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}},
5514
5515 {"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}},
5516 {"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}},
5517
5518 {"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}},
5519 {"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}},
5520
5521 {"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}},
5522
5523 {"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
5524
5525 {"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
5526
5527 {"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {E}},
5528
5529 {"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5530
5531 {"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5532 {"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5533
5534 {"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
5535
5536 {"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}},
5537 {"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
5538
5539 {"mtmsrd", X(31,178), XRLARB_MASK, PPC64, 0, {RS, A_L}},
5540
5541 {"mtvsrd", X(31,179), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
5542 {"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
5543 {"mtvrd", X(31,179)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5544 {"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}},
5545
5546 {"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}},
5547
5548 {"stqcx.", XRC(31,182,1), X_MASK|Q_MASK, POWER8, 0, {RSQ, RA0, RB}},
5549 {"wchkall", X(31,182), X_MASK, PPCA2, 0, {OBF}},
5550
5551 {"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}},
5552 {"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
5553
5554 {"sliq", XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}},
5555 {"sliq.", XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}},
5556
5557 {"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}},
5558
5559 {"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}},
5560
5561 {"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}},
5562
5563 {"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5564 {"stwfcmx", APU(31,199,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5565
5566 {"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5567 {"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5568 {"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5569 {"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5570
5571 {"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5572 {"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5573 {"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5574 {"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5575
5576 {"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
5577
5578 {"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}},
5579
5580 {"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
5581 {"mtvrwa", X(31,211)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5582 {"mtvsrwa", X(31,211), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
5583 {"eratwe", X(31,211), X_MASK, PPCA2, 0, {RS, RA, WS}},
5584
5585 {"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
5586
5587 {"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}},
5588
5589 {"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}},
5590
5591 {"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}},
5592 {"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}},
5593
5594 {"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}},
5595 {"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}},
5596
5597 {"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
5598
5599 {"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}},
5600
5601 {"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5602
5603 {"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5604 {"stqfcmx", APU(31,231,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5605
5606 {"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5607 {"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5608 {"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5609 {"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5610
5611 {"mulld", XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5612 {"mulld.", XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5613
5614 {"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5615 {"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5616 {"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5617 {"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5618
5619 {"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5620 {"muls", XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5621 {"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5622 {"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5623
5624 {"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
5625 {"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
5626 {"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},
5627 {"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}},
5628
5629 {"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
5630 {"mtvrwz", X(31,243)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5631 {"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
5632
5633 {"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
5634 {"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
5635 {"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
5636 {"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
5637
5638 {"stbux", X(31,247), X_MASK, COM, 0, {RS, RAS, RB}},
5639
5640 {"slliq", XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}},
5641 {"slliq.", XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}},
5642
5643 {"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}},
5644
5645 {"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
5646
5647 {"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}},
5648 {"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}},
5649
5650 {"lvexbx", X(31,261), X_MASK, E6500, 0, {VD, RA0, RB}},
5651
5652 {"icbt", X(31,262), XRT_MASK, PPC403, 0, {RA, RB}},
5653
5654 {"lvepxl", X(31,263), X_MASK, E6500, 0, {VD, RA0, RB}},
5655
5656 {"ldfcmx", APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5657 {"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5658 {"doz.", XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5659
5660 {"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}},
5661
5662 {"add", XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5663 {"cax", XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5664 {"add.", XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5665 {"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5666
5667 {"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}},
5668
5669 {"lxvx", X(31,268), XX1_MASK|1<<6, PPCVSX3, 0, {XT6, RA0, RB}},
5670 {"lxvl", X(31,269), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5671
5672 {"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, 0, {0}},
5673
5674 {"tlbiel", X(31,274), X_MASK|1<<20,POWER9, 0, {RB, RSO, RIC, PRS, X_R}},
5675 {"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, LOPT}},
5676
5677 {"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
5678
5679 {"lqarx", X(31,276), XEH_MASK|Q_MASK, POWER8, 0, {RTQ, RAX, RBX, EH}},
5680
5681 {"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}},
5682 {"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}},
5683
5684 {"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
5685 {"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
5686 {"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
5687 {"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
5688
5689 {"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}},
5690
5691 {"cdtbcd", X(31,282), XRB_MASK, POWER6, 0, {RA, RS}},
5692
5693 {"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}},
5694 {"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}},
5695
5696 {"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
5697
5698 {"mfdcrux", X(31,291), X_MASK, PPC464|PPC476, 0, {RS, RA}},
5699
5700 {"lvexhx", X(31,293), X_MASK, E6500, 0, {VD, RA0, RB}},
5701 {"lvepx", X(31,295), X_MASK, E6500, 0, {VD, RA0, RB}},
5702
5703 {"lxvll", X(31,301), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5704
5705 {"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}},
5706
5707 {"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}},
5708 {"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}},
5709 {"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, LOPT}},
5710 {"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}},
5711
5712 {"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}},
5713
5714 {"ldmx", X(31,309), X_MASK, POWER9, 0, {RT, RA0, RB}},
5715
5716 {"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
5717
5718 {"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}},
5719
5720 {"cbcdtd", X(31,314), XRB_MASK, POWER6, 0, {RA, RS}},
5721
5722 {"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}},
5723 {"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}},
5724
5725 {"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
5726
5727 {"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, 0, {RT}},
5728 {"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, 0, {RT}},
5729 {"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, 0, {RT}},
5730 {"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, 0, {RT}},
5731 {"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, 0, {RT}},
5732 {"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, 0, {RT}},
5733 {"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, 0, {RT}},
5734 {"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, 0, {RT}},
5735 {"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, 0, {RT}},
5736 {"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, 0, {RT}},
5737 {"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, 0, {RT}},
5738 {"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, 0, {RT}},
5739 {"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, 0, {RT}},
5740 {"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, 0, {RT}},
5741 {"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, 0, {RT}},
5742 {"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, 0, {RT}},
5743 {"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, 0, {RT}},
5744 {"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, 0, {RT}},
5745 {"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, 0, {RT}},
5746 {"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, 0, {RT}},
5747 {"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, 0, {RT}},
5748 {"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, 0, {RT}},
5749 {"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, 0, {RT}},
5750 {"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, 0, {RT}},
5751 {"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, 0, {RT}},
5752 {"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, 0, {RT}},
5753 {"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, 0, {RT}},
5754 {"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, 0, {RT}},
5755 {"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, 0, {RT}},
5756 {"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, 0, {RT}},
5757 {"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, 0, {RT}},
5758 {"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, 0, {RT}},
5759 {"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, 0, {RT}},
5760 {"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, 0, {RT}},
5761 {"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}},
5762 {"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}},
5763
5764 {"lvexwx", X(31,325), X_MASK, E6500, 0, {VD, RA0, RB}},
5765
5766 {"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}},
5767
5768 {"div", XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5769 {"div.", XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5770
5771 {"lxvdsx", X(31,332), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
5772
5773 {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}},
5774 {"mftmr", X(31,366), X_MASK, PPCTMR, 0, {RT, TMR}},
5775
5776 {"slbsync", X(31,338), 0xffffffff, POWER9, 0, {0}},
5777
5778 {"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, 0, {RT}},
5779 {"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, 0, {RT}},
5780 {"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}},
5781 {"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}},
5782 {"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, 0, {RT}},
5783 {"mflr", XSPR(31,339, 8), XSPR_MASK, COM, 0, {RT}},
5784 {"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, 0, {RT}},
5785 {"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, 0, {RT}},
5786 {"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, 0, {RT}},
5787 {"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}},
5788 {"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}},
5789 {"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}},
5790 {"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, 0, {RT}},
5791 {"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}},
5792 {"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, 0, {RT}},
5793 {"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, 0, {RT}},
5794 {"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, 0, {RT}},
5795 {"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, 0, {RT}},
5796 {"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, 0, {RT}},
5797 {"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, 0, {RT}},
5798 {"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, 0, {RT}},
5799 {"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, 0, {RT}},
5800 {"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, 0, {RT}},
5801 {"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, 0, {RT}},
5802 {"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, 0, {RT}},
5803 {"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, 0, {RT}},
5804 {"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, 0, {RT}},
5805 {"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, 0, {RT}},
5806 {"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, 0, {RT}},
5807 {"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, 0, {RT}},
5808 {"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, 0, {RT}},
5809 {"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, 0, {RT}},
5810 {"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, 0, {RT}},
5811 {"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, 0, {RT}},
5812 {"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, 0, {RT}},
5813 {"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, 0, {RT}},
5814 {"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, 0, {RT}},
5815 {"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, 0, {RT}},
5816 {"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, 0, {RT}},
5817 {"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, 0, {RT}},
5818 {"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, 0, {RT}},
5819 {"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, 0, {RT}},
5820 {"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, 0, {RT, SPRG}},
5821 {"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5822 {"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5823 {"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5824 {"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5825 {"mftbu", XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
5826 {"mftb", X(31,339), X_MASK, POWER4|BOOKE, 0, {RT, TBR}},
5827 {"mftbl", XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
5828 {"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, 0, {RT}},
5829 {"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, 0, {RT}},
5830 {"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, 0, {RT}},
5831 {"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, 0, {RT}},
5832 {"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, 0, {RT}},
5833 {"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}},
5834 {"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, 0, {RT}},
5835 {"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, 0, {RT}},
5836 {"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, 0, {RT}},
5837 {"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, 0, {RT}},
5838 {"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, 0, {RT}},
5839 {"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, 0, {RT}},
5840 {"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, 0, {RT}},
5841 {"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, 0, {RT}},
5842 {"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, 0, {RT}},
5843 {"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, 0, {RT}},
5844 {"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, 0, {RT}},
5845 {"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, 0, {RT}},
5846 {"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, 0, {RT}},
5847 {"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, 0, {RT}},
5848 {"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, 0, {RT}},
5849 {"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, 0, {RT}},
5850 {"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, 0, {RT}},
5851 {"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, 0, {RT}},
5852 {"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, 0, {RT}},
5853 {"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, 0, {RT}},
5854 {"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, 0, {RT}},
5855 {"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, 0, {RT}},
5856 {"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, 0, {RT}},
5857 {"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, 0, {RT}},
5858 {"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, 0, {RT}},
5859 {"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, 0, {RT}},
5860 {"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, 0, {RT}},
5861 {"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, 0, {RT}},
5862 {"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, 0, {RT}},
5863 {"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, 0, {RT}},
5864 {"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, 0, {RT}},
5865 {"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, 0, {RT}},
5866 {"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, 0, {RT}},
5867 {"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, 0, {RT}},
5868 {"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, 0, {RT}},
5869 {"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE|E6500, 0, {RT}},
5870 {"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE|E6500, 0, {RT}},
5871 {"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, 0, {RT}},
5872 {"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}},
5873 {"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5874 {"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5875 {"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5876 {"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5877 {"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, 0, {RT}},
5878 {"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, 0, {RT}},
5879 {"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, 0, {RT}},
5880 {"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, 0, {RT}},
5881 {"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, 0, {RT}},
5882 {"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, 0, {RT}},
5883 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, 0, {RT}},
5884 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, 0, {RT}},
5885 {"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, 0, {RT}},
5886 {"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}},
5887 {"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, 0, {RT}},
5888 {"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, 0, {RT}},
5889 {"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, 0, {RT}},
5890 {"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, 0, {RT}},
5891 {"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, 0, {RT}},
5892 {"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, 0, {RT}},
5893 {"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, 0, {RT}},
5894 {"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, 0, {RT}},
5895 {"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, 0, {RT}},
5896 {"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, 0, {RT}},
5897 {"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, 0, {RT}},
5898 {"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, 0, {RT}},
5899 {"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, 0, {RT}},
5900 {"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, 0, {RT}},
5901 {"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, 0, {RT}},
5902 {"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, 0, {RT}},
5903 {"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, 0, {RT}},
5904 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, 0, {RT}},
5905 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, 0, {RT}},
5906 {"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, 0, {RT}},
5907 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, 0, {RT}},
5908 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, 0, {RT}},
5909 {"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, 0, {RT}},
5910 {"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, 0, {RT}},
5911 {"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, 0, {RT}},
5912 {"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, 0, {RT}},
5913 {"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, 0, {RT}},
5914 {"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, 0, {RT}},
5915 {"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, 0, {RT}},
5916 {"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, 0, {RT}},
5917 {"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, 0, {RT}},
5918 {"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, 0, {RT}},
5919 {"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, 0, {RT}},
5920 {"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, 0, {RT}},
5921 {"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, 0, {RT}},
5922 {"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, 0, {RT}},
5923 {"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, 0, {RT}},
5924 {"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, 0, {RT}},
5925 {"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, 0, {RT}},
5926 {"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, 0, {RT}},
5927 {"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, 0, {RT}},
5928 {"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, 0, {RT}},
5929 {"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, 0, {RT}},
5930 {"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, 0, {RT}},
5931 {"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, 0, {RT}},
5932 {"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, 0, {RT}},
5933 {"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, 0, {RT}},
5934 {"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, 0, {RT}},
5935 {"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, 0, {RT}},
5936 {"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, 0, {RT}},
5937 {"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, 0, {RT}},
5938 {"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, 0, {RT}},
5939 {"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, 0, {RT}},
5940 {"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, 0, {RT}},
5941 {"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, 0, {RT}},
5942 {"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, 0, {RT}},
5943 {"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, 0, {RT}},
5944 {"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, 0, {RT}},
5945 {"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, 0, {RT}},
5946 {"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, 0, {RT}},
5947 {"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, 0, {RT}},
5948 {"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, 0, {RT}},
5949 {"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, 0, {RT}},
5950 {"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, 0, {RT}},
5951 {"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, 0, {RT}},
5952 {"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, 0, {RT}},
5953 {"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, 0, {RT}},
5954 {"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, 0, {RT}},
5955 {"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, 0, {RT}},
5956 {"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, 0, {RT}},
5957 {"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, 0, {RT}},
5958 {"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, 0, {RT}},
5959 {"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, 0, {RT}},
5960 {"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, 0, {RT}},
5961 {"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, 0, {RT}},
5962 {"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, 0, {RS}},
5963 {"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, 0, {RT}},
5964 {"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, 0, {RT}},
5965 {"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, 0, {RT}},
5966 {"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, 0, {RT}},
5967 {"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, 0, {RT}},
5968 {"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, 0, {RT}},
5969 {"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, 0, {RT}},
5970 {"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, 0, {RT}},
5971 {"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, 0, {RT}},
5972 {"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, 0, {RT}},
5973 {"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, 0, {RT}},
5974 {"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, 0, {RT}},
5975 {"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, 0, {RT}},
5976 {"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, 0, {RT}},
5977 {"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, 0, {RT}},
5978 {"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}},
5979
5980 {"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}},
5981
5982 {"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
5983
5984 {"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}},
5985
5986 {"lvxl", X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
5987
5988 {"abs", XO(31,360,0,0), XORB_MASK, M601, 0, {RT, RA}},
5989 {"abs.", XO(31,360,0,1), XORB_MASK, M601, 0, {RT, RA}},
5990
5991 {"divs", XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5992 {"divs.", XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5993
5994 {"lxvwsx", X(31,364), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5995
5996 {"tlbia", X(31,370), 0xffffffff, PPC, E500|TITAN, {0}},
5997
5998 {"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}},
5999 {"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}},
6000 {"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371|POWER4, {RT}},
6001
6002 {"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}},
6003
6004 {"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
6005
6006 {"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}},
6007
6008 {"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
6009
6010 {"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}},
6011 {"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}},
6012
6013 {"stvexbx", X(31,389), X_MASK, E6500, 0, {VS, RA0, RB}},
6014
6015 {"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
6016 {"stdfcmx", APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
6017
6018 {"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6019 {"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6020 {"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6021 {"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6022
6023 {"stxvx", X(31,396), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6024 {"stxvl", X(31,397), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6025
6026 {"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
6027
6028 {"slbmte", X(31,402), XRA_MASK, PPC64, 0, {RS, RB}},
6029
6030 {"mtvsrws", X(31,403), XX1RB_MASK, PPCVSX3, 0, {XT6, RA}},
6031
6032 {"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}},
6033
6034 {"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
6035 {"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
6036
6037 {"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}},
6038
6039 {"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}},
6040 {"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}},
6041
6042 {"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
6043
6044 {"mtdcrux", X(31,419), X_MASK, PPC464|PPC476, 0, {RA, RS}},
6045
6046 {"stvexhx", X(31,421), X_MASK, E6500, 0, {VS, RA0, RB}},
6047
6048 {"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}},
6049
6050 {"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6051 {"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6052 {"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6053 {"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6054
6055 {"stxvll", X(31,429), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6056
6057 {"clrbhrb", X(31,430), 0xffffffff, POWER8, 0, {0}},
6058
6059 {"slbie", X(31,434), XRTRA_MASK, PPC64, 0, {RB}},
6060
6061 {"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6062
6063 {"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
6064
6065 {"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}},
6066
6067 {"mdors", 0x7f9ce378, 0xffffffff, E500MC, 0, {0}},
6068
6069 {"miso", 0x7f5ad378, 0xffffffff, E6500, 0, {0}},
6070
6071 /* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for
6072 "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */
6073 {"yield", 0x7f7bdb78, 0xffffffff, POWER7, 0, {0}},
6074 {"mdoio", 0x7fbdeb78, 0xffffffff, POWER7, 0, {0}},
6075 {"mdoom", 0x7fdef378, 0xffffffff, POWER7, 0, {0}},
6076 {"mr", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RBS}},
6077 {"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}},
6078 {"mr.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RBS}},
6079 {"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}},
6080
6081 {"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, 0, {RS}},
6082 {"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, 0, {RS}},
6083 {"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, 0, {RS}},
6084 {"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, 0, {RS}},
6085 {"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, 0, {RS}},
6086 {"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, 0, {RS}},
6087 {"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, 0, {RS}},
6088 {"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, 0, {RS}},
6089 {"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, 0, {RS}},
6090 {"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, 0, {RS}},
6091 {"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, 0, {RS}},
6092 {"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, 0, {RS}},
6093 {"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, 0, {RS}},
6094 {"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, 0, {RS}},
6095 {"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, 0, {RS}},
6096 {"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, 0, {RS}},
6097 {"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, 0, {RS}},
6098 {"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, 0, {RS}},
6099 {"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, 0, {RS}},
6100 {"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, 0, {RS}},
6101 {"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, 0, {RS}},
6102 {"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, 0, {RS}},
6103 {"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, 0, {RS}},
6104 {"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, 0, {RS}},
6105 {"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, 0, {RS}},
6106 {"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, 0, {RS}},
6107 {"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, 0, {RS}},
6108 {"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, 0, {RS}},
6109 {"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, 0, {RS}},
6110 {"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, 0, {RS}},
6111 {"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, 0, {RS}},
6112 {"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, 0, {RS}},
6113 {"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, 0, {RS}},
6114 {"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, 0, {RS}},
6115 {"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}},
6116 {"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, 0, {SPR, RS}},
6117
6118 {"stvexwx", X(31,453), X_MASK, E6500, 0, {VS, RA0, RB}},
6119
6120 {"dccci", X(31,454), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
6121 {"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, 0, {CT}},
6122
6123 {"divdu", XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6124 {"divdu.", XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
6125
6126 {"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6127 {"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
6128
6129 {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}},
6130 {"mttmr", X(31,494), X_MASK, PPCTMR, 0, {TMR, RS}},
6131
6132 {"slbieg", X(31,466), XRA_MASK, POWER9, 0, {RS, RB}},
6133
6134 {"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, 0, {RS}},
6135 {"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, 0, {RS}},
6136 {"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, 0, {RS}},
6137 {"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, 0, {RS}},
6138 {"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, 0, {RS}},
6139 {"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, 0, {RS}},
6140 {"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}},
6141 {"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}},
6142 {"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, TITAN, {RS}},
6143 {"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, TITAN, {RS}},
6144 {"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, 0, {RS}},
6145 {"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, 0, {RS}},
6146 {"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN, {RS}},
6147 {"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, 0, {RS}},
6148 {"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, 0, {RS}},
6149 {"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, 0, {RS}},
6150 {"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, 0, {RS}},
6151 {"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, 0, {RS}},
6152 {"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, 0, {RS}},
6153 {"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, 0, {RS}},
6154 {"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, 0, {RS}},
6155 {"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, 0, {RS}},
6156 {"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, 0, {RS}},
6157 {"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, 0, {RS}},
6158 {"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, 0, {RS}},
6159 {"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, 0, {RS}},
6160 {"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, 0, {RS}},
6161 {"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, 0, {RS}},
6162 {"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, 0, {RS}},
6163 {"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, 0, {RS}},
6164 {"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, 0, {RS}},
6165 {"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, 0, {RS}},
6166 {"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, 0, {RS}},
6167 {"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, 0, {RS}},
6168 {"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, 0, {RS}},
6169 {"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, 0, {RS}},
6170 {"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, 0, {RS}},
6171 {"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, 0, {RS}},
6172 {"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, 0, {RS}},
6173 {"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, 0, {RS}},
6174 {"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, 0, {RS}},
6175 {"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, 0, {RS}},
6176 {"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC, 0, {SPRG, RS}},
6177 {"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, 0, {RS}},
6178 {"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, 0, {RS}},
6179 {"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, 0, {RS}},
6180 {"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, 0, {RS}},
6181 {"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
6182 {"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
6183 {"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
6184 {"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
6185 {"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, 0, {RS}},
6186 {"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}},
6187 {"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, 0, {RS}},
6188 {"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, 0, {RS}},
6189 {"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, 0, {RS}},
6190 {"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, 0, {RS}},
6191 {"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, 0, {RS}},
6192 {"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, 0, {RS}},
6193 {"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, 0, {RS}},
6194 {"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, 0, {RS}},
6195 {"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, 0, {RS}},
6196 {"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, 0, {RS}},
6197 {"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, 0, {RS}},
6198 {"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, 0, {RS}},
6199 {"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, 0, {RS}},
6200 {"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, 0, {RS}},
6201 {"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, 0, {RS}},
6202 {"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, 0, {RS}},
6203 {"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, 0, {RS}},
6204 {"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, 0, {RS}},
6205 {"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, 0, {RS}},
6206 {"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, 0, {RS}},
6207 {"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, 0, {RS}},
6208 {"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, 0, {RS}},
6209 {"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, 0, {RS}},
6210 {"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, 0, {RS}},
6211 {"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, 0, {RS}},
6212 {"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, 0, {RS}},
6213 {"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, 0, {RS}},
6214 {"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, 0, {RS}},
6215 {"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, 0, {RS}},
6216 {"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, 0, {RS}},
6217 {"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, 0, {RS}},
6218 {"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, 0, {RS}},
6219 {"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, 0, {RS}},
6220 {"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, 0, {RS}},
6221 {"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, 0, {RS}},
6222 {"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE|E6500, 0, {RS}},
6223 {"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE|E6500, 0, {RS}},
6224 {"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, 0, {RS}},
6225 {"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, 0, {RS}},
6226 {"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
6227 {"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
6228 {"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
6229 {"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
6230 {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}},
6231 {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}},
6232 {"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}},
6233 {"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, 0, {RS}},
6234 {"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, 0, {RS}},
6235 {"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, 0, {RS}},
6236 {"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, 0, {RS}},
6237 {"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, 0, {RS}},
6238 {"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, 0, {RS}},
6239 {"mtppr", XSPR(31,467,896), XSPR_MASK, POWER7, 0, {RS}},
6240 {"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER7, 0, {RS}},
6241 {"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, 0, {RS}},
6242 {"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, 0, {RS}},
6243 {"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, 0, {RS}},
6244 {"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, 0, {RS}},
6245 {"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, 0, {RS}},
6246 {"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, 0, {RS}},
6247 {"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, 0, {RS}},
6248 {"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, 0, {RS}},
6249 {"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, 0, {RS}},
6250 {"mtrmmucr", XSPR(31,467,946), XSPR_MASK, TITAN, 0, {RS}},
6251 {"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, 0, {RS}},
6252 {"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, 0, {RS}},
6253 {"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, 0, {RS}},
6254 {"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, 0, {RS}},
6255 {"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, 0, {RS}},
6256 {"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, 0, {RS}},
6257 {"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, 0, {RS}},
6258 {"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, 0, {RS}},
6259 {"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, 0, {RS}},
6260 {"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, 0, {RS}},
6261 {"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, 0, {RS}},
6262 {"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, 0, {RS}},
6263 {"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, 0, {RS}},
6264 {"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, 0, {RS}},
6265 {"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, 0, {RS}},
6266 {"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, 0, {RS}},
6267 {"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, 0, {RS}},
6268 {"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, 0, {RS}},
6269 {"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, 0, {RS}},
6270 {"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, 0, {RS}},
6271 {"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, 0, {RS}},
6272 {"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, 0, {RS}},
6273 {"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, 0, {RS}},
6274 {"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, 0, {RS}},
6275 {"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, 0, {RS}},
6276 {"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, 0, {RS}},
6277 {"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, 0, {RS}},
6278 {"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, 0, {RS}},
6279 {"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, 0, {RS}},
6280 {"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, 0, {RS}},
6281 {"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, 0, {RS}},
6282 {"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, 0, {RS}},
6283 {"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, 0, {RS}},
6284 {"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, 0, {RS}},
6285 {"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, 0, {RS}},
6286 {"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, 0, {RS}},
6287 {"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, 0, {RS}},
6288 {"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, 0, {RS}},
6289 {"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, 0, {RS}},
6290 {"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, 0, {RS}},
6291 {"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, 0, {RS}},
6292 {"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, 0, {RS}},
6293 {"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, 0, {RS}},
6294 {"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, 0, {RS}},
6295 {"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, 0, {RS}},
6296 {"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, 0, {RS}},
6297 {"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, 0, {RS}},
6298 {"mtspr", X(31,467), X_MASK, COM, 0, {SPR, RS}},
6299
6300 {"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}},
6301
6302 {"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}},
6303 {"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}},
6304
6305 {"dsn", X(31,483), XRT_MASK, E500MC, 0, {RA, RB}},
6306
6307 {"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2, {RT, RA0, RB}},
6308
6309 {"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
6310
6311 {"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
6312
6313 {"nabs", XO(31,488,0,0), XORB_MASK, M601, 0, {RT, RA}},
6314 {"nabs.", XO(31,488,0,1), XORB_MASK, M601, 0, {RT, RA}},
6315
6316 {"divd", XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6317 {"divd.", XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
6318
6319 {"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6320 {"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
6321
6322 {"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
6323
6324 {"slbia", X(31,498), 0xff1fffff, POWER6, 0, {IH}},
6325 {"slbia", X(31,498), 0xffffffff, PPC64, POWER6, {0}},
6326
6327 {"cli", X(31,502), XRB_MASK, POWER, 0, {RT, RA}},
6328
6329 {"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
6330
6331 {"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}},
6332
6333 {"mcrxr", X(31,512), XBFRARB_MASK, COM, POWER7, {BF}},
6334
6335 {"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}},
6336 {"lbdx", X(31,515), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}},
6337
6338 {"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}},
6339
6340 {"lvlx", X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}},
6341 {"lbfcmux", APU(31,519,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
6342
6343 {"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6344 {"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6345 {"subco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
6346 {"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6347 {"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6348 {"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
6349
6350 {"addco", XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6351 {"ao", XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6352 {"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6353 {"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6354
6355 {"lxsspx", X(31,524), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
6356
6357 {"clcs", X(31,531), XRB_MASK, M601, 0, {RT, RA}},
6358
6359 {"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}},
6360
6361 {"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}},
6362 {"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}},
6363
6364 {"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
6365 {"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}},
6366
6367 {"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
6368
6369 {"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6370 {"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
6371 {"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6372 {"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
6373
6374 {"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}},
6375 {"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}},
6376
6377 {"cnttzw", XRC(31,538,0), XRB_MASK, POWER9, 0, {RA, RS}},
6378 {"cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, 0, {RA, RS}},
6379
6380 {"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}},
6381 {"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}},
6382
6383 {"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}},
6384 {"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}},
6385
6386 {"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}},
6387 {"lhdx", X(31,547), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}},
6388
6389 {"lvtrx", X(31,549), X_MASK, E6500, 0, {VD, RA0, RB}},
6390
6391 {"bbelr", X(31,550), X_MASK, PPCBRLK, 0, {0}},
6392
6393 {"lvrx", X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}},
6394 {"lhfcmux", APU(31,551,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
6395
6396 {"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6397 {"subo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RB, RA}},
6398 {"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
6399 {"subo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RB, RA}},
6400
6401 {"tlbsync", X(31,566), 0xffffffff, PPC, 0, {0}},
6402
6403 {"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
6404
6405 {"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, 0, {RA, RS}},
6406 {"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, 0, {RA, RS}},
6407
6408 {"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}},
6409
6410 {"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}},
6411 {"lwdx", X(31,579), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}},
6412
6413 {"lvtlx", X(31,581), X_MASK, E6500, 0, {VD, RA0, RB}},
6414
6415 {"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}},
6416
6417 {"lwfcmux", APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
6418
6419 {"lxsdx", X(31,588), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
6420
6421 {"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}},
6422
6423 {"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, NBI}},
6424 {"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}},
6425
6426 {"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}},
6427 {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
6428 {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, 0, {0}},
6429 {"sync", X(31,598), XSYNCLE_MASK, E6500, 0, {LS, ESYNC}},
6430 {"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}},
6431 {"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, 0, {0}},
6432 {"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}},
6433 {"lwsync", X(31,598), 0xffffffff, E500, 0, {0}},
6434 {"dcs", X(31,598), 0xffffffff, PWRCOM, 0, {0}},
6435
6436 {"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
6437
6438 {"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}},
6439 {"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}},
6440
6441 {"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}},
6442
6443 {"lvswx", X(31,613), X_MASK, E6500, 0, {VD, RA0, RB}},
6444
6445 {"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}},
6446
6447 {"lqfcmux", APU(31,615,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
6448
6449 {"nego", XO(31,104,1,0), XORB_MASK, COM, 0, {RT, RA}},
6450 {"nego.", XO(31,104,1,1), XORB_MASK, COM, 0, {RT, RA}},
6451
6452 {"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6453 {"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
6454
6455 {"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}},
6456
6457 {"dclst", X(31,630), XRB_MASK, M601, 0, {RS, RA}},
6458
6459 {"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
6460
6461 {"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}},
6462 {"stbdx", X(31,643), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}},
6463
6464 {"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}},
6465 {"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
6466
6467 {"stxsspx", X(31,652), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
6468
6469 {"tbegin.", XRC(31,654,1), XRTLRARB_MASK, PPCHTM, 0, {HTM_R}},
6470
6471 {"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6472 {"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6473 {"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6474 {"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6475
6476 {"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6477 {"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6478 {"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6479 {"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6480
6481 {"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}},
6482
6483 {"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}},
6484
6485 {"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}},
6486 {"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
6487
6488 {"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
6489 {"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
6490
6491 {"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
6492
6493 {"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}},
6494 {"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}},
6495
6496 {"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}},
6497 {"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}},
6498
6499 {"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}},
6500 {"sthdx", X(31,675), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}},
6501
6502 {"stvfrx", X(31,677), X_MASK, E6500, 0, {VS, RA0, RB}},
6503
6504 {"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}},
6505 {"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
6506
6507 {"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, 0, {0}},
6508 {"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, 0, {HTM_A}},
6509
6510 {"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
6511
6512 {"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
6513
6514 {"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}},
6515 {"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}},
6516
6517 {"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}},
6518 {"stwdx", X(31,707), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}},
6519
6520 {"stvflx", X(31,709), X_MASK, E6500, 0, {VS, RA0, RB}},
6521
6522 {"stwat", X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}},
6523
6524 {"stwfcmux", APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
6525
6526 {"stxsdx", X(31,716), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
6527
6528 {"tcheck", X(31,718), XRTBFRARB_MASK, PPCHTM, 0, {BF}},
6529
6530 {"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
6531 {"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
6532 {"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
6533 {"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
6534
6535 {"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
6536 {"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
6537 {"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
6538 {"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
6539
6540 {"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}},
6541 {"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}},
6542
6543 {"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
6544
6545 {"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
6546
6547 {"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}},
6548 {"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}},
6549
6550 {"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}},
6551 {"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}},
6552
6553 {"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}},
6554 {"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}},
6555
6556 {"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}},
6557
6558 {"stvswx", X(31,741), X_MASK, E6500, 0, {VS, RA0, RB}},
6559
6560 {"stdat", X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}},
6561
6562 {"stqfcmux", APU(31,743,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
6563
6564 {"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
6565 {"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
6566 {"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
6567 {"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
6568
6569 {"mulldo", XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6570 {"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
6571
6572 {"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
6573 {"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
6574 {"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
6575 {"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
6576
6577 {"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6578 {"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6579 {"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6580 {"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6581
6582 {"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM, 0, {0}},
6583 {"tresume.", XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, 0, {0}},
6584 {"tsr.", XRC(31,750,1), XRTLRARB_MASK,PPCHTM, 0, {L}},
6585
6586 {"darn", X(31,755), XLRAND_MASK, POWER9, 0, {RT, LRAND}},
6587
6588 {"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
6589 {"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, 0, {RA0, RB}},
6590
6591 {"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
6592
6593 {"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}},
6594 {"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}},
6595
6596 {"lvsm", X(31,773), X_MASK, E6500, 0, {VD, RA0, RB}},
6597
6598 {"copy", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}},
6599
6600 {"stvepxl", X(31,775), X_MASK, E6500, 0, {VS, RA0, RB}},
6601 {"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}},
6602 {"ldfcmux", APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
6603
6604 {"dozo", XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6605 {"dozo.", XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
6606
6607 {"addo", XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6608 {"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6609 {"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6610 {"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6611
6612 {"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}},
6613 {"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}},
6614
6615 {"lxvw4x", X(31,780), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
6616 {"lxsibzx", X(31,781), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6617
6618 {"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
6619
6620 {"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
6621
6622 {"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}},
6623
6624 {"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}},
6625
6626 {"lfdpx", X(31,791), X_MASK|Q_MASK, POWER6, POWER7, {FRTp, RA0, RB}},
6627 {"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}},
6628
6629 {"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6630 {"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
6631 {"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6632 {"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
6633
6634 {"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}},
6635 {"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}},
6636
6637 {"evlddepx", VX (31, 1598), VX_MASK, PPCSPE, 0, {RT, RA, RB}},
6638 {"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}},
6639
6640 {"lvtrxl", X(31,805), X_MASK, E6500, 0, {VD, RA0, RB}},
6641 {"stvepx", X(31,807), X_MASK, E6500, 0, {VS, RA0, RB}},
6642 {"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}},
6643
6644 {"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6645 {"lxsihzx", X(31,813), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6646
6647 {"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
6648
6649 {"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}},
6650
6651 {"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}},
6652
6653 {"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}},
6654
6655 {"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, 0, {STRM}},
6656
6657 {"lfqux", X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}},
6658
6659 {"srawi", XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}},
6660 {"srai", XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}},
6661 {"srawi.", XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}},
6662 {"srai.", XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}},
6663
6664 {"sradi", XS(31,413,0), XS_MASK, PPC64, 0, {RA, RS, SH6}},
6665 {"sradi.", XS(31,413,1), XS_MASK, PPC64, 0, {RA, RS, SH6}},
6666
6667 {"lvtlxl", X(31,837), X_MASK, E6500, 0, {VD, RA0, RB}},
6668
6669 {"cpabort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}},
6670
6671 {"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6672 {"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
6673
6674 {"lxvd2x", X(31,844), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
6675 {"lxvx", X(31,844), XX1_MASK, POWER8, POWER9|PPCVSX3, {XT6, RA0, RB}},
6676
6677 {"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
6678
6679 {"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}},
6680
6681 {"slbiag", X(31,850), XRARB_MASK, POWER9, 0, {RS}},
6682 {"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
6683 {"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}},
6684
6685 {"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}},
6686
6687 {"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}},
6688 {"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, 0, {MO}},
6689 {"eieio", XMBAR(31,854,1),0xffffffff, E500, 0, {0}},
6690 {"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, 0, {0}},
6691
6692 {"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}},
6693
6694 {"lvswxl", X(31,869), X_MASK, E6500, 0, {VD, RA0, RB}},
6695
6696 {"abso", XO(31,360,1,0), XORB_MASK, M601, 0, {RT, RA}},
6697 {"abso.", XO(31,360,1,1), XORB_MASK, M601, 0, {RT, RA}},
6698
6699 {"divso", XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6700 {"divso.", XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
6701
6702 {"lxvb16x", X(31,876), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6703
6704 {"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
6705
6706 {"rmieg", X(31,882), XRTRA_MASK, POWER9, 0, {RB}},
6707
6708 {"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}},
6709
6710 {"msgsync", X(31,886), 0xffffffff, POWER9, 0, {0}},
6711
6712 {"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}},
6713
6714 {"extswsli", XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}},
6715 {"extswsli.", XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}},
6716
6717 {"paste.", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}},
6718
6719 {"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}},
6720 {"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
6721
6722 {"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6723 {"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6724 {"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6725 {"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6726
6727 {"stxvw4x", X(31,908), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
6728 {"stxsibx", X(31,909), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6729
6730 {"tabort.", XRC(31,910,1), XRTRB_MASK, PPCHTM, 0, {RA}},
6731
6732 {"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
6733 {"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
6734
6735 {"slbmfee", X(31,915), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
6736 {"slbmfee", X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}},
6737
6738 {"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}},
6739
6740 {"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}},
6741
6742 {"stfdpx", X(31,919), X_MASK|Q_MASK, POWER6, POWER7, {FRSp, RA0, RB}},
6743 {"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}},
6744
6745 {"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}},
6746 {"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}},
6747
6748 {"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}},
6749 {"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}},
6750
6751 {"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
6752 {"exts", XRC(31,922,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
6753 {"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
6754 {"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
6755
6756 {"evstddepx", VX (31, 1854), VX_MASK, PPCSPE, 0, {RT, RA, RB}},
6757 {"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}},
6758
6759 {"stvfrxl", X(31,933), X_MASK, E6500, 0, {VS, RA0, RB}},
6760
6761 {"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}},
6762 {"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L2}},
6763 {"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}},
6764
6765 {"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}},
6766
6767 {"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6768 {"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6769 {"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6770 {"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6771
6772 {"stxvh8x", X(31,940), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6773 {"stxsihx", X(31,941), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6774
6775 {"treclaim.", XRC(31,942,1), XRTRB_MASK, PPCHTM, 0, {RA}},
6776
6777 {"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
6778 {"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
6779 {"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
6780
6781 {"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}},
6782
6783 {"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}},
6784 {"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}},
6785
6786 {"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}},
6787
6788 {"sraiq", XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}},
6789 {"sraiq.", XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}},
6790
6791 {"extsb", XRC(31,954,0), XRB_MASK, PPC, 0, {RA, RS}},
6792 {"extsb.", XRC(31,954,1), XRB_MASK, PPC, 0, {RA, RS}},
6793
6794 {"stvflxl", X(31,965), X_MASK, E6500, 0, {VS, RA0, RB}},
6795
6796 {"iccci", X(31,966), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
6797 {"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, 0, {CT}},
6798
6799 {"divduo", XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6800 {"divduo.", XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
6801
6802 {"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6803 {"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
6804
6805 {"stxvd2x", X(31,972), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
6806 {"stxvx", X(31,972), XX1_MASK, POWER8, POWER9|PPCVSX3, {XS6, RA0, RB}},
6807
6808 {"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
6809 {"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, 0, {RT, RA}},
6810 {"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, 0, {RT, RA}},
6811 {"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
6812
6813 {"slbfee.", XRC(31,979,1), XRA_MASK, POWER6, 0, {RT, RB}},
6814
6815 {"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}},
6816
6817 {"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}},
6818
6819 {"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}},
6820
6821 {"extsw", XRC(31,986,0), XRB_MASK, PPC64, 0, {RA, RS}},
6822 {"extsw.", XRC(31,986,1), XRB_MASK, PPC64, 0, {RA, RS}},
6823
6824 {"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
6825
6826 {"stvswxl", X(31,997), X_MASK, E6500, 0, {VS, RA0, RB}},
6827
6828 {"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}},
6829
6830 {"nabso", XO(31,488,1,0), XORB_MASK, M601, 0, {RT, RA}},
6831 {"nabso.", XO(31,488,1,1), XORB_MASK, M601, 0, {RT, RA}},
6832
6833 {"divdo", XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6834 {"divdo.", XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
6835
6836 {"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6837 {"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
6838
6839 {"stxvb16x", X(31,1004), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6840
6841 {"trechkpt.", XRC(31,1006,1), XRTRARB_MASK,PPCHTM, 0, {0}},
6842
6843 {"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}},
6844
6845 {"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}},
6846
6847 {"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
6848 {"dclz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
6849
6850 {"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
6851
6852 {"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}},
6853
6854 {"cctpl", 0x7c210b78, 0xffffffff, CELL, 0, {0}},
6855 {"cctpm", 0x7c421378, 0xffffffff, CELL, 0, {0}},
6856 {"cctph", 0x7c631b78, 0xffffffff, CELL, 0, {0}},
6857
6858 {"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
6859 {"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
6860 {"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, 0, {0}},
6861
6862 {"db8cyc", 0x7f9ce378, 0xffffffff, CELL, 0, {0}},
6863 {"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, 0, {0}},
6864 {"db12cyc", 0x7fdef378, 0xffffffff, CELL, 0, {0}},
6865 {"db16cyc", 0x7ffffb78, 0xffffffff, CELL, 0, {0}},
6866
6867 {"lwz", OP(32), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
6868 {"l", OP(32), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
6869
6870 {"lwzu", OP(33), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAL}},
6871 {"lu", OP(33), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
6872
6873 {"lbz", OP(34), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
6874
6875 {"lbzu", OP(35), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
6876
6877 {"stw", OP(36), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},
6878 {"st", OP(36), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
6879
6880 {"stwu", OP(37), OP_MASK, PPCCOM, PPCVLE, {RS, D, RAS}},
6881 {"stu", OP(37), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
6882
6883 {"stb", OP(38), OP_MASK, COM, PPCVLE, {RS, D, RA0}},
6884
6885 {"stbu", OP(39), OP_MASK, COM, PPCVLE, {RS, D, RAS}},
6886
6887 {"lhz", OP(40), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
6888
6889 {"lhzu", OP(41), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
6890
6891 {"lha", OP(42), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
6892
6893 {"lhau", OP(43), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
6894
6895 {"sth", OP(44), OP_MASK, COM, PPCVLE, {RS, D, RA0}},
6896
6897 {"sthu", OP(45), OP_MASK, COM, PPCVLE, {RS, D, RAS}},
6898
6899 {"lmw", OP(46), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAM}},
6900 {"lm", OP(46), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
6901
6902 {"stmw", OP(47), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},
6903 {"stm", OP(47), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
6904
6905 {"lfs", OP(48), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},
6906
6907 {"lfsu", OP(49), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}},
6908
6909 {"lfd", OP(50), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},
6910
6911 {"lfdu", OP(51), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}},
6912
6913 {"stfs", OP(52), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
6914
6915 {"stfsu", OP(53), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
6916
6917 {"stfd", OP(54), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
6918
6919 {"stfdu", OP(55), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
6920
6921 {"lq", OP(56), OP_MASK|Q_MASK, POWER4, PPC476|PPCVLE, {RTQ, DQ, RAQ}},
6922 {"psq_l", OP(56), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
6923 {"lfq", OP(56), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},
6924
6925 {"lxsd", DSO(57,2), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}},
6926 {"lxssp", DSO(57,3), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}},
6927 {"lfdp", OP(57), OP_MASK|Q_MASK, POWER6, POWER7|PPCVLE, {FRTp, DS, RA0}},
6928 {"psq_lu", OP(57), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
6929 {"lfqu", OP(57), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},
6930
6931 {"ld", DSO(58,0), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
6932 {"ldu", DSO(58,1), DS_MASK, PPC64, PPCVLE, {RT, DS, RAL}},
6933 {"lwa", DSO(58,2), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
6934
6935 {"dadd", XRC(59,2,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6936 {"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6937
6938 {"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
6939 {"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
6940
6941 {"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6942 {"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6943
6944 {"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6945 {"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6946
6947 {"fadds", A(59,21,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6948 {"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6949
6950 {"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}},
6951 {"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}},
6952
6953 {"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6954 {"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6955 {"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6956 {"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6957
6958 {"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6959 {"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6960
6961 {"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6962 {"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6963 {"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6964 {"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6965
6966 {"fmsubs", A(59,28,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6967 {"fmsubs.", A(59,28,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6968
6969 {"fmadds", A(59,29,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6970 {"fmadds.", A(59,29,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6971
6972 {"fnmsubs", A(59,30,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6973 {"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6974
6975 {"fnmadds", A(59,31,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6976 {"fnmadds.", A(59,31,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6977
6978 {"dmul", XRC(59,34,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6979 {"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6980
6981 {"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
6982 {"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
6983
6984 {"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6985 {"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6986
6987 {"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
6988 {"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
6989
6990 {"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6991 {"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6992
6993 {"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6994 {"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6995
6996 {"dcmpo", X(59,130), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6997
6998 {"dtstex", X(59,162), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6999 {"dtstdc", Z(59,194), Z_MASK, POWER6, PPCVLE, {BF, FRA, DCM}},
7000 {"dtstdg", Z(59,226), Z_MASK, POWER6, PPCVLE, {BF, FRA, DGM}},
7001
7002 {"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
7003 {"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
7004
7005 {"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
7006 {"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
7007
7008 {"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
7009 {"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
7010
7011 {"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
7012 {"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
7013
7014 {"dxex", XRC(59,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
7015 {"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
7016
7017 {"dsub", XRC(59,514,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
7018 {"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
7019
7020 {"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
7021 {"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
7022
7023 {"dcmpu", X(59,642), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
7024
7025 {"dtstsf", X(59,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
7026 {"dtstsfi", X(59,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRB}},
7027
7028 {"drsp", XRC(59,770,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
7029 {"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
7030
7031 {"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
7032 {"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
7033
7034 {"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
7035 {"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
7036
7037 {"fcfids", XRC(59,846,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
7038 {"fcfids.", XRC(59,846,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
7039
7040 {"diex", XRC(59,866,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
7041 {"diex.", XRC(59,866,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
7042
7043 {"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
7044 {"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
7045
7046 {"xsaddsp", XX3(60,0), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
7047 {"xsmaddasp", XX3(60,1), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
7048 {"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, SHW}},
7049 {"xscmpeqdp", XX3(60,3), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
7050 {"xsrsqrtesp", XX2(60,10), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
7051 {"xssqrtsp", XX2(60,11), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
7052 {"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, XC6}},
7053 {"xssubsp", XX3(60,8), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
7054 {"xsmaddmsp", XX3(60,9), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
7055 {"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S, DMEX}},
7056 {"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7057 {"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
7058 {"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7059 {"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, DM}},
7060 {"xscmpgtdp", XX3(60,11), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
7061 {"xsresp", XX2(60,26), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
7062 {"xsmulsp", XX3(60,16), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
7063 {"xsmsubasp", XX3(60,17), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
7064 {"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7065 {"xscmpgedp", XX3(60,19), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
7066 {"xsdivsp", XX3(60,24), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
7067 {"xsmsubmsp", XX3(60,25), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
7068 {"xxperm", XX3(60,26), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
7069 {"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7070 {"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7071 {"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
7072 {"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7073 {"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7074 {"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7075 {"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7076 {"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7077 {"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7078 {"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
7079 {"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7080 {"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7081 {"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7082 {"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7083 {"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7084 {"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7085 {"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7086 {"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
7087 {"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7088 {"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7089 {"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7090 {"xxpermr", XX3(60,58), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
7091 {"xscmpexpdp", XX3(60,59), XX3BF_MASK, PPCVSX3, PPCVLE, {BF, XA6, XB6}},
7092 {"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7093 {"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
7094 {"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7095 {"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7096 {"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7097 {"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7098 {"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7099 {"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7100 {"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7101 {"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7102 {"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7103 {"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7104 {"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7105 {"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7106 {"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7107 {"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7108 {"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7109 {"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7110 {"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7111 {"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCVLE, {XT6, XB6, UIM}},
7112 {"xxextractuw", XX2(60,165), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}},
7113 {"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7114 {"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7115 {"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7116 {"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7117 {"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
7118 {"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7119 {"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7120 {"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7121 {"xxspltib", X(60,360), XX1_MASK|3<<19, PPCVSX3, PPCVLE, {XT6, IMM8}},
7122 {"xxinsertw", XX2(60,181), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}},
7123 {"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7124 {"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7125 {"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
7126 {"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7127 {"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7128 {"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7129 {"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7130 {"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7131 {"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7132 {"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7133 {"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7134 {"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7135 {"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7136 {"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7137 {"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7138 {"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7139 {"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7140 {"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7141 {"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7142 {"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7143 {"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7144 {"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7145 {"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7146 {"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7147 {"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
7148 {"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7149 {"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7150 {"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7151 {"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7152 {"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7153 {"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
7154 {"xsmaxcdp", XX3(60,128), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
7155 {"xsnmaddasp", XX3(60,129), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
7156 {"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7157 {"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7158 {"xscvdpspn", XX2(60,267), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
7159 {"xsmincdp", XX3(60,136), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
7160 {"xsnmaddmsp", XX3(60,137), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
7161 {"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7162 {"xsrsp", XX2(60,281), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
7163 {"xsmaxjdp", XX3(60,144), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
7164 {"xsnmsubasp", XX3(60,145), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
7165 {"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7166 {"xscvuxdsp", XX2(60,296), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
7167 {"xststdcsp", XX2(60,298), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}},
7168 {"xsminjdp", XX3(60,152), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
7169 {"xsnmsubmsp", XX3(60,153), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
7170 {"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7171 {"xscvsxdsp", XX2(60,312), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
7172 {"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7173 {"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7174 {"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7175 {"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7176 {"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7177 {"xscvspdpn", XX2(60,331), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
7178 {"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7179 {"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7180 {"xxlorc", XX3(60,170), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
7181 {"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7182 {"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7183 {"xsxexpdp", XX2VA(60,347,0),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
7184 {"xsxsigdp", XX2VA(60,347,1),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
7185 {"xscvhpdp", XX2VA(60,347,16),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
7186 {"xscvdphp", XX2VA(60,347,17),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
7187 {"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7188 {"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7189 {"xxlnand", XX3(60,178), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
7190 {"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7191 {"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7192 {"xststdcdp", XX2(60,362), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}},
7193 {"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7194 {"xxleqv", XX3(60,186), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
7195 {"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7196 {"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7197 {"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7198 {"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7199 {"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7200 {"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7201 {"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7202 {"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7203 {"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7204 {"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7205 {"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
7206 {"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7207 {"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7208 {"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7209 {"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7210 {"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}},
7211 {"xviexpsp", XX3(60,216), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
7212 {"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7213 {"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7214 {"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7215 {"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7216 {"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7217 {"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7218 {"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7219 {"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCVLE, {XT6, RA, RB}},
7220 {"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7221 {"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7222 {"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7223 {"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7224 {"xvxexpdp", XX2VA(60,475,0),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
7225 {"xvxsigdp", XX2VA(60,475,1),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
7226 {"xxbrh", XX2VA(60,475,7),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
7227 {"xvxexpsp", XX2VA(60,475,8),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
7228 {"xvxsigsp", XX2VA(60,475,9),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
7229 {"xxbrw", XX2VA(60,475,15),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
7230 {"xxbrd", XX2VA(60,475,23),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
7231 {"xvcvhpsp", XX2VA(60,475,24),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
7232 {"xvcvsphp", XX2VA(60,475,25),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
7233 {"xxbrq", XX2VA(60,475,31),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
7234 {"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
7235 {"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7236 {"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7237 {"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7238 {"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7239 {"xvtstdcdp", XX2(60,490), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}},
7240 {"xviexpdp", XX3(60,248), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
7241 {"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
7242 {"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7243 {"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
7244
7245 {"psq_st", OP(60), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
7246 {"stfq", OP(60), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
7247
7248 {"lxv", DQX(61,1), DQX_MASK, PPCVSX3, PPCVLE, {XTQ6, DQ, RA0}},
7249 {"stxv", DQX(61,5), DQX_MASK, PPCVSX3, PPCVLE, {XSQ6, DQ, RA0}},
7250 {"stxsd", DSO(61,2), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},
7251 {"stxssp", DSO(61,3), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},
7252 {"stfdp", OP(61), OP_MASK|Q_MASK, POWER6, POWER7|PPCVLE, {FRSp, DS, RA0}},
7253 {"psq_stu", OP(61), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
7254 {"stfqu", OP(61), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
7255
7256 {"std", DSO(62,0), DS_MASK, PPC64, PPCVLE, {RS, DS, RA0}},
7257 {"stdu", DSO(62,1), DS_MASK, PPC64, PPCVLE, {RS, DS, RAS}},
7258 {"stq", DSO(62,2), DS_MASK|Q_MASK, POWER4, PPC476|PPCVLE, {RSQ, DS, RA0}},
7259
7260 {"fcmpu", X(63,0), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}},
7261
7262 {"daddq", XRC(63,2,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
7263 {"daddq.", XRC(63,2,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
7264
7265 {"dquaq", ZRC(63,3,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}},
7266 {"dquaq.", ZRC(63,3,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}},
7267
7268 {"xsaddqp", XRC(63,4,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7269 {"xsaddqpo", XRC(63,4,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7270
7271 {"xsrqpi", ZRC(63,5,0), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
7272 {"xsrqpix", ZRC(63,5,1), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
7273
7274 {"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
7275 {"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
7276
7277 {"frsp", XRC(63,12,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
7278 {"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
7279
7280 {"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
7281 {"fcir", XRC(63,14,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
7282 {"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
7283 {"fcir.", XRC(63,14,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
7284
7285 {"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
7286 {"fcirz", XRC(63,15,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
7287 {"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
7288 {"fcirz.", XRC(63,15,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
7289
7290 {"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
7291 {"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
7292 {"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
7293 {"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
7294
7295 {"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
7296 {"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
7297 {"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
7298 {"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
7299
7300 {"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
7301 {"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
7302 {"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
7303 {"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
7304
7305 {"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}},
7306 {"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}},
7307
7308 {"fsel", A(63,23,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
7309 {"fsel.", A(63,23,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
7310
7311 {"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
7312 {"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
7313 {"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
7314 {"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
7315
7316 {"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
7317 {"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}},
7318 {"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
7319 {"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}},
7320
7321 {"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
7322 {"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
7323 {"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
7324 {"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
7325
7326 {"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
7327 {"fms", A(63,28,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
7328 {"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
7329 {"fms.", A(63,28,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
7330
7331 {"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
7332 {"fma", A(63,29,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
7333 {"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
7334 {"fma.", A(63,29,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
7335
7336 {"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
7337 {"fnms", A(63,30,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
7338 {"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
7339 {"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
7340
7341 {"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
7342 {"fnma", A(63,31,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
7343 {"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
7344 {"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
7345
7346 {"fcmpo", X(63,32), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}},
7347
7348 {"dmulq", XRC(63,34,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
7349 {"dmulq.", XRC(63,34,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
7350
7351 {"drrndq", ZRC(63,35,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}},
7352 {"drrndq.", ZRC(63,35,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}},
7353
7354 {"xsmulqp", XRC(63,36,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7355 {"xsmulqpo", XRC(63,36,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7356
7357 {"xsrqpxp", Z(63,37), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
7358
7359 {"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCVLE, {BT}},
7360 {"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCVLE, {BT}},
7361
7362 {"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
7363 {"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
7364
7365 {"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
7366
7367 {"dscliq", ZRC(63,66,0), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
7368 {"dscliq.", ZRC(63,66,1), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
7369
7370 {"dquaiq", ZRC(63,67,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
7371 {"dquaiq.", ZRC(63,67,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
7372
7373 {"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCVLE, {BT}},
7374 {"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCVLE, {BT}},
7375
7376 {"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
7377 {"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
7378
7379 {"dscriq", ZRC(63,98,0), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
7380 {"dscriq.", ZRC(63,98,1), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
7381
7382 {"drintxq", ZRC(63,99,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
7383 {"drintxq.", ZRC(63,99,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
7384
7385 {"xscpsgnqp", X(63,100), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7386
7387 {"ftdiv", X(63,128), XBF_MASK, POWER7, PPCVLE, {BF, FRA, FRB}},
7388
7389 {"dcmpoq", X(63,130), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
7390
7391 {"xscmpoqp", X(63,132), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
7392
7393 {"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}},
7394 {"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}},
7395 {"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}},
7396 {"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}},
7397
7398 {"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
7399 {"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
7400
7401 {"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
7402 {"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
7403 {"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
7404 {"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
7405
7406 {"ftsqrt", X(63,160), XBF_MASK|FRA_MASK, POWER7, PPCVLE, {BF, FRB}},
7407
7408 {"dtstexq", X(63,162), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
7409
7410 {"xscmpexpqp", X(63,164), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
7411
7412 {"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DCM}},
7413 {"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DGM}},
7414
7415 {"drintnq", ZRC(63,227,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
7416 {"drintnq.", ZRC(63,227,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
7417
7418 {"dctqpq", XRC(63,258,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
7419 {"dctqpq.", XRC(63,258,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
7420
7421 {"fabs", XRC(63,264,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
7422 {"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
7423
7424 {"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
7425 {"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
7426
7427 {"ddedpdq", XRC(63,322,0), X_MASK|Q_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
7428 {"ddedpdq.", XRC(63,322,1), X_MASK|Q_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
7429
7430 {"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
7431 {"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
7432
7433 {"xsmaddqp", XRC(63,388,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7434 {"xsmaddqpo", XRC(63,388,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7435
7436 {"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
7437 {"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
7438
7439 {"xsmsubqp", XRC(63,420,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7440 {"xsmsubqpo", XRC(63,420,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7441
7442 {"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
7443 {"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
7444
7445 {"xsnmaddqp", XRC(63,452,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7446 {"xsnmaddqpo", XRC(63,452,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7447
7448 {"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
7449 {"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
7450
7451 {"xsnmsubqp", XRC(63,484,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7452 {"xsnmsubqpo", XRC(63,484,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7453
7454 {"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
7455 {"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
7456
7457 {"dsubq", XRC(63,514,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
7458 {"dsubq.", XRC(63,514,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
7459
7460 {"xssubqp", XRC(63,516,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7461 {"xssubqpo", XRC(63,516,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7462
7463 {"ddivq", XRC(63,546,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
7464 {"ddivq.", XRC(63,546,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
7465
7466 {"xsdivqp", XRC(63,548,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7467 {"xsdivqpo", XRC(63,548,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7468
7469 {"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}},
7470 {"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}},
7471
7472 {"mffsce", XMMF(63,583,0,1), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}},
7473 {"mffscdrn", XMMF(63,583,2,4), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}},
7474 {"mffscdrni", XMMF(63,583,2,5), XMMF_MASK|(3<<14), POWER9, PPCVLE, {FRT, DRM}},
7475 {"mffscrn", XMMF(63,583,2,6), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}},
7476 {"mffscrni", XMMF(63,583,2,7), XMMF_MASK|(7<<13), POWER9, PPCVLE, {FRT, RM}},
7477 {"mffsl", XMMF(63,583,3,0), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}},
7478
7479 {"dcmpuq", X(63,642), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
7480
7481 {"xscmpuqp", X(63,644), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
7482
7483 {"dtstsfq", X(63,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRBp}},
7484 {"dtstsfiq", X(63,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRBp}},
7485
7486 {"xststdcqp", X(63,708), X_MASK, PPCVSX3, PPCVLE, {BF, VB, DCMX}},
7487
7488 {"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}},
7489 {"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
7490 {"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}},
7491 {"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
7492
7493 {"drdpq", XRC(63,770,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
7494 {"drdpq.", XRC(63,770,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
7495
7496 {"dcffixq", XRC(63,802,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
7497 {"dcffixq.", XRC(63,802,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
7498
7499 {"xsabsqp", XVA(63,804,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7500 {"xsxexpqp", XVA(63,804,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7501 {"xsnabsqp", XVA(63,804,8), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7502 {"xsnegqp", XVA(63,804,16), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7503 {"xsxsigqp", XVA(63,804,18), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7504 {"xssqrtqp", XVARC(63,804,27,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7505 {"xssqrtqpo", XVARC(63,804,27,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7506
7507 {"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7508 {"fctid", XRC(63,814,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
7509 {"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7510 {"fctid.", XRC(63,814,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
7511
7512 {"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7513 {"fctidz", XRC(63,815,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
7514 {"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7515 {"fctidz.", XRC(63,815,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
7516
7517 {"denbcdq", XRC(63,834,0), X_MASK|Q_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
7518 {"denbcdq.", XRC(63,834,1), X_MASK|Q_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
7519
7520 {"xscvqpuwz", XVA(63,836,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7521 {"xscvudqp", XVA(63,836,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7522 {"xscvqpswz", XVA(63,836,9), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7523 {"xscvsdqp", XVA(63,836,10), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7524 {"xscvqpudz", XVA(63,836,17), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7525 {"xscvqpdp", XVARC(63,836,20,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7526 {"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7527 {"xscvdpqp", XVA(63,836,22), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7528 {"xscvqpsdz", XVA(63,836,25), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7529
7530 {"fmrgow", X(63,838), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
7531
7532 {"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7533 {"fcfid", XRC(63,846,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
7534 {"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7535 {"fcfid.", XRC(63,846,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
7536
7537 {"diexq", XRC(63,866,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
7538 {"diexq.", XRC(63,866,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
7539
7540 {"xsiexpqp", X(63,868), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7541
7542 {"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
7543 {"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
7544
7545 {"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
7546 {"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
7547
7548 {"fmrgew", X(63,966), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
7549
7550 {"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
7551 {"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
7552 };
7553
7554 const unsigned int powerpc_num_opcodes =
7555 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
7556 \f
7557 /* The VLE opcode table.
7558
7559 The format of this opcode table is the same as the main opcode table. */
7560
7561 const struct powerpc_opcode vle_opcodes[] = {
7562 {"se_illegal", C(0), C_MASK, PPCVLE, 0, {}},
7563 {"se_isync", C(1), C_MASK, PPCVLE, 0, {}},
7564 {"se_sc", C(2), C_MASK, PPCVLE, 0, {}},
7565 {"se_blr", C_LK(2,0), C_LK_MASK, PPCVLE, 0, {}},
7566 {"se_blrl", C_LK(2,1), C_LK_MASK, PPCVLE, 0, {}},
7567 {"se_bctr", C_LK(3,0), C_LK_MASK, PPCVLE, 0, {}},
7568 {"se_bctrl", C_LK(3,1), C_LK_MASK, PPCVLE, 0, {}},
7569 {"se_rfi", C(8), C_MASK, PPCVLE, 0, {}},
7570 {"se_rfci", C(9), C_MASK, PPCVLE, 0, {}},
7571 {"se_rfdi", C(10), C_MASK, PPCVLE, 0, {}},
7572 {"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}},
7573 {"se_rfgi", C(12), C_MASK, PPCVLE, 0, {}},
7574 {"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, 0, {RX}},
7575 {"se_neg", SE_R(0,3), SE_R_MASK, PPCVLE, 0, {RX}},
7576 {"se_mflr", SE_R(0,8), SE_R_MASK, PPCVLE, 0, {RX}},
7577 {"se_mtlr", SE_R(0,9), SE_R_MASK, PPCVLE, 0, {RX}},
7578 {"se_mfctr", SE_R(0,10), SE_R_MASK, PPCVLE, 0, {RX}},
7579 {"se_mtctr", SE_R(0,11), SE_R_MASK, PPCVLE, 0, {RX}},
7580 {"se_extzb", SE_R(0,12), SE_R_MASK, PPCVLE, 0, {RX}},
7581 {"se_extsb", SE_R(0,13), SE_R_MASK, PPCVLE, 0, {RX}},
7582 {"se_extzh", SE_R(0,14), SE_R_MASK, PPCVLE, 0, {RX}},
7583 {"se_extsh", SE_R(0,15), SE_R_MASK, PPCVLE, 0, {RX}},
7584 {"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7585 {"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, 0, {ARX, RY}},
7586 {"se_mfar", SE_RR(0,3), SE_RR_MASK, PPCVLE, 0, {RX, ARY}},
7587 {"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7588 {"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7589 {"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7590 {"se_subf", SE_RR(1,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7591 {"se_cmp", SE_RR(3,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7592 {"se_cmpl", SE_RR(3,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7593 {"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7594 {"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7595
7596 /* by major opcode */
7597 {"zvaddih", VX(4, 0x200), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}},
7598 {"zvsubifh", VX(4, 0x201), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}},
7599 {"zvaddh", VX(4, 0x204), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7600 {"zvsubfh", VX(4, 0x205), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7601 {"zvaddsubfh", VX(4, 0x206), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7602 {"zvsubfaddh", VX(4, 0x207), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7603 {"zvaddhx", VX(4, 0x20C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7604 {"zvsubfhx", VX(4, 0x20D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7605 {"zvaddsubfhx", VX(4, 0x20E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7606 {"zvsubfaddhx", VX(4, 0x20F), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7607 {"zaddwus", VX(4, 0x210), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7608 {"zsubfwus", VX(4, 0x211), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7609 {"zaddwss", VX(4, 0x212), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7610 {"zsubfwss", VX(4, 0x213), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7611 {"zvaddhus", VX(4, 0x214), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7612 {"zvsubfhus", VX(4, 0x215), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7613 {"zvaddhss", VX(4, 0x216), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7614 {"zvsubfhss", VX(4, 0x217), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7615 {"zvaddsubfhss", VX(4, 0x21A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7616 {"zvsubfaddhss", VX(4, 0x21B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7617 {"zvaddhxss", VX(4, 0x21C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7618 {"zvsubfhxss", VX(4, 0x21D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7619 {"zvaddsubfhxss", VX(4, 0x21E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7620 {"zvsubfaddhxss", VX(4, 0x21F), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7621 {"zaddheuw", VX(4, 0x220), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7622 {"zsubfheuw", VX(4, 0x221), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7623 {"zaddhesw", VX(4, 0x222), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7624 {"zsubfhesw", VX(4, 0x223), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7625 {"zaddhouw", VX(4, 0x224), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7626 {"zsubfhouw", VX(4, 0x225), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7627 {"zaddhosw", VX(4, 0x226), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7628 {"zsubfhosw", VX(4, 0x227), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7629 {"zvmergehih", VX(4, 0x22C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7630 {"zvmergeloh", VX(4, 0x22D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7631 {"zvmergehiloh", VX(4, 0x22E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7632 {"zvmergelohih", VX(4, 0x22F), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7633 {"zvcmpgthu", VX(4, 0x230), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}},
7634 {"zvcmpgths", VX(4, 0x230), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}},
7635 {"zvcmplthu", VX(4, 0x231), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}},
7636 {"zvcmplths", VX(4, 0x231), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}},
7637 {"zvcmpeqh", VX(4, 0x232), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}},
7638 {"zpkswgshfrs", VX(4, 0x238), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7639 {"zpkswgswfrs", VX(4, 0x239), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7640 {"zvpkshgwshfrs", VX(4, 0x23A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7641 {"zvpkswshfrs", VX(4, 0x23B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7642 {"zvpkswuhs", VX(4, 0x23C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7643 {"zvpkswshs", VX(4, 0x23D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7644 {"zvpkuwuhs", VX(4, 0x23E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7645 {"zvsplatih", VX_LSP(4, 0x23F), VX_LSP_MASK, PPCLSP, 0, {RD, SIMM}},
7646 {"zvsplatfih", VX_LSP(4, 0xA3F), VX_LSP_MASK, PPCLSP, 0, {RD, SIMM}},
7647 {"zcntlsw", VX_LSP(4, 0x2A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7648 {"zvcntlzh", VX_LSP(4, 0x323F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7649 {"zvcntlsh", VX_LSP(4, 0x3A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7650 {"znegws", VX_LSP(4, 0x4A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7651 {"zvnegh", VX_LSP(4, 0x523F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7652 {"zvneghs", VX_LSP(4, 0x5A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7653 {"zvnegho", VX_LSP(4, 0x623F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7654 {"zvneghos", VX_LSP(4, 0x6A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7655 {"zrndwh", VX_LSP(4, 0x823F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7656 {"zrndwhss", VX_LSP(4, 0x8A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7657 {"zvabsh", VX_LSP(4, 0xA23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7658 {"zvabshs", VX_LSP(4, 0xAA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7659 {"zabsw", VX_LSP(4, 0xB23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7660 {"zabsws", VX_LSP(4, 0xBA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7661 {"zsatswuw", VX_LSP(4, 0xC23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7662 {"zsatuwsw", VX_LSP(4, 0xCA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7663 {"zsatswuh", VX_LSP(4, 0xD23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7664 {"zsatswsh", VX_LSP(4, 0xDA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7665 {"zvsatshuh", VX_LSP(4, 0xE23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7666 {"zvsatuhsh", VX_LSP(4, 0xEA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7667 {"zsatuwuh", VX_LSP(4, 0xF23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7668 {"zsatuwsh", VX_LSP(4, 0xFA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7669 {"zsatsduw", VX(4, 0x260), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7670 {"zsatsdsw", VX(4, 0x261), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7671 {"zsatuduw", VX(4, 0x262), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7672 {"zvselh", VX(4, 0x264), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7673 {"zxtrw", VX(4, 0x264), VX_LSP_OFF_MASK, PPCLSP, 0, {RD, RA, RB, VX_OFF}},
7674 {"zbrminc", VX(4, 0x268), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7675 {"zcircinc", VX(4, 0x269), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7676 {"zdivwsf", VX(4, 0x26B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7677 {"zvsrhu", VX(4, 0x270), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7678 {"zvsrhs", VX(4, 0x271), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7679 {"zvsrhiu", VX(4, 0x272), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
7680 {"zvsrhis", VX(4, 0x273), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
7681 {"zvslh", VX(4, 0x274), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7682 {"zvrlh", VX(4, 0x275), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7683 {"zvslhi", VX(4, 0x276), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
7684 {"zvrlhi", VX(4, 0x277), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
7685 {"zvslhus", VX(4, 0x278), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7686 {"zvslhss", VX(4, 0x279), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7687 {"zvslhius", VX(4, 0x27A), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
7688 {"zvslhiss", VX(4, 0x27B), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
7689 {"zslwus", VX(4, 0x27C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7690 {"zslwss", VX(4, 0x27D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7691 {"zslwius", VX(4, 0x27E), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}},
7692 {"zslwiss", VX(4, 0x27F), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}},
7693 {"zaddwgui", VX(4, 0x460), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7694 {"zsubfwgui", VX(4, 0x461), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7695 {"zaddd", VX(4, 0x462), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7696 {"zsubfd", VX(4, 0x463), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7697 {"zvaddsubfw", VX(4, 0x464), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7698 {"zvsubfaddw", VX(4, 0x465), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7699 {"zvaddw", VX(4, 0x466), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7700 {"zvsubfw", VX(4, 0x467), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7701 {"zaddwgsi", VX(4, 0x468), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7702 {"zsubfwgsi", VX(4, 0x469), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7703 {"zadddss", VX(4, 0x46A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7704 {"zsubfdss", VX(4, 0x46B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7705 {"zvaddsubfwss", VX(4, 0x46C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7706 {"zvsubfaddwss", VX(4, 0x46D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7707 {"zvaddwss", VX(4, 0x46E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7708 {"zvsubfwss", VX(4, 0x46F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7709 {"zaddwgsf", VX(4, 0x470), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7710 {"zsubfwgsf", VX(4, 0x471), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7711 {"zadddus", VX(4, 0x472), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7712 {"zsubfdus", VX(4, 0x473), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7713 {"zvaddwus", VX(4, 0x476), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7714 {"zvsubfwus", VX(4, 0x477), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7715 {"zvunpkhgwsf", VX_LSP(4, 0x478), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}},
7716 {"zvunpkhsf", VX_LSP(4, 0xC78), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}},
7717 {"zvunpkhui", VX_LSP(4, 0x1478), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}},
7718 {"zvunpkhsi", VX_LSP(4, 0x1C78), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}},
7719 {"zunpkwgsf", VX_LSP(4, 0x2478), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}},
7720 {"zvdotphgwasmf", VX(4, 0x488), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7721 {"zvdotphgwasmfr", VX(4, 0x489), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7722 {"zvdotphgwasmfaa", VX(4, 0x48A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7723 {"zvdotphgwasmfraa", VX(4, 0x48B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7724 {"zvdotphgwasmfan", VX(4, 0x48C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7725 {"zvdotphgwasmfran", VX(4, 0x48D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7726 {"zvmhulgwsmf", VX(4, 0x490), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7727 {"zvmhulgwsmfr", VX(4, 0x491), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7728 {"zvmhulgwsmfaa", VX(4, 0x492), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7729 {"zvmhulgwsmfraa", VX(4, 0x493), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7730 {"zvmhulgwsmfan", VX(4, 0x494), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7731 {"zvmhulgwsmfran", VX(4, 0x495), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7732 {"zvmhulgwsmfanp", VX(4, 0x496), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7733 {"zvmhulgwsmfranp", VX(4, 0x497), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7734 {"zmhegwsmf", VX(4, 0x498), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7735 {"zmhegwsmfr", VX(4, 0x499), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7736 {"zmhegwsmfaa", VX(4, 0x49A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7737 {"zmhegwsmfraa", VX(4, 0x49B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7738 {"zmhegwsmfan", VX(4, 0x49C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7739 {"zmhegwsmfran", VX(4, 0x49D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7740 {"zvdotphxgwasmf", VX(4, 0x4A8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7741 {"zvdotphxgwasmfr", VX(4, 0x4A9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7742 {"zvdotphxgwasmfaa", VX(4, 0x4AA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7743 {"zvdotphxgwasmfraa", VX(4, 0x4AB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7744 {"zvdotphxgwasmfan", VX(4, 0x4AC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7745 {"zvdotphxgwasmfran", VX(4, 0x4AD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7746 {"zvmhllgwsmf", VX(4, 0x4B0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7747 {"zvmhllgwsmfr", VX(4, 0x4B1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7748 {"zvmhllgwsmfaa", VX(4, 0x4B2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7749 {"zvmhllgwsmfraa", VX(4, 0x4B3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7750 {"zvmhllgwsmfan", VX(4, 0x4B4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7751 {"zvmhllgwsmfran", VX(4, 0x4B5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7752 {"zvmhllgwsmfanp", VX(4, 0x4B6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7753 {"zvmhllgwsmfranp", VX(4, 0x4B7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7754 {"zmheogwsmf", VX(4, 0x4B8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7755 {"zmheogwsmfr", VX(4, 0x4B9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7756 {"zmheogwsmfaa", VX(4, 0x4BA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7757 {"zmheogwsmfraa", VX(4, 0x4BB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7758 {"zmheogwsmfan", VX(4, 0x4BC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7759 {"zmheogwsmfran", VX(4, 0x4BD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7760 {"zvdotphgwssmf", VX(4, 0x4C8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7761 {"zvdotphgwssmfr", VX(4, 0x4C9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7762 {"zvdotphgwssmfaa", VX(4, 0x4CA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7763 {"zvdotphgwssmfraa", VX(4, 0x4CB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7764 {"zvdotphgwssmfan", VX(4, 0x4CC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7765 {"zvdotphgwssmfran", VX(4, 0x4CD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7766 {"zvmhuugwsmf", VX(4, 0x4D0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7767 {"zvmhuugwsmfr", VX(4, 0x4D1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7768 {"zvmhuugwsmfaa", VX(4, 0x4D2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7769 {"zvmhuugwsmfraa", VX(4, 0x4D3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7770 {"zvmhuugwsmfan", VX(4, 0x4D4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7771 {"zvmhuugwsmfran", VX(4, 0x4D5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7772 {"zvmhuugwsmfanp", VX(4, 0x4D6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7773 {"zvmhuugwsmfranp", VX(4, 0x4D7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7774 {"zmhogwsmf", VX(4, 0x4D8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7775 {"zmhogwsmfr", VX(4, 0x4D9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7776 {"zmhogwsmfaa", VX(4, 0x4DA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7777 {"zmhogwsmfraa", VX(4, 0x4DB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7778 {"zmhogwsmfan", VX(4, 0x4DC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7779 {"zmhogwsmfran", VX(4, 0x4DD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7780 {"zvmhxlgwsmf", VX(4, 0x4F0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7781 {"zvmhxlgwsmfr", VX(4, 0x4F1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7782 {"zvmhxlgwsmfaa", VX(4, 0x4F2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7783 {"zvmhxlgwsmfraa", VX(4, 0x4F3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7784 {"zvmhxlgwsmfan", VX(4, 0x4F4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7785 {"zvmhxlgwsmfran", VX(4, 0x4F5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7786 {"zvmhxlgwsmfanp", VX(4, 0x4F6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7787 {"zvmhxlgwsmfranp", VX(4, 0x4F7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7788 {"zmhegui", VX(4, 0x500), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7789 {"zvdotphgaui", VX(4, 0x501), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7790 {"zmheguiaa", VX(4, 0x502), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7791 {"zvdotphgauiaa", VX(4, 0x503), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7792 {"zmheguian", VX(4, 0x504), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7793 {"zvdotphgauian", VX(4, 0x505), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7794 {"zmhegsi", VX(4, 0x508), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7795 {"zvdotphgasi", VX(4, 0x509), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7796 {"zmhegsiaa", VX(4, 0x50A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7797 {"zvdotphgasiaa", VX(4, 0x50B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7798 {"zmhegsian", VX(4, 0x50C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7799 {"zvdotphgasian", VX(4, 0x50D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7800 {"zmhegsui", VX(4, 0x510), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7801 {"zvdotphgasui", VX(4, 0x511), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7802 {"zmhegsuiaa", VX(4, 0x512), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7803 {"zvdotphgasuiaa", VX(4, 0x513), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7804 {"zmhegsuian", VX(4, 0x514), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7805 {"zvdotphgasuian", VX(4, 0x515), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7806 {"zmhegsmf", VX(4, 0x518), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7807 {"zvdotphgasmf", VX(4, 0x519), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7808 {"zmhegsmfaa", VX(4, 0x51A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7809 {"zvdotphgasmfaa", VX(4, 0x51B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7810 {"zmhegsmfan", VX(4, 0x51C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7811 {"zvdotphgasmfan", VX(4, 0x51D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7812 {"zmheogui", VX(4, 0x520), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7813 {"zvdotphxgaui", VX(4, 0x521), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7814 {"zmheoguiaa", VX(4, 0x522), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7815 {"zvdotphxgauiaa", VX(4, 0x523), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7816 {"zmheoguian", VX(4, 0x524), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7817 {"zvdotphxgauian", VX(4, 0x525), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7818 {"zmheogsi", VX(4, 0x528), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7819 {"zvdotphxgasi", VX(4, 0x529), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7820 {"zmheogsiaa", VX(4, 0x52A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7821 {"zvdotphxgasiaa", VX(4, 0x52B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7822 {"zmheogsian", VX(4, 0x52C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7823 {"zvdotphxgasian", VX(4, 0x52D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7824 {"zmheogsui", VX(4, 0x530), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7825 {"zvdotphxgasui", VX(4, 0x531), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7826 {"zmheogsuiaa", VX(4, 0x532), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7827 {"zvdotphxgasuiaa", VX(4, 0x533), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7828 {"zmheogsuian", VX(4, 0x534), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7829 {"zvdotphxgasuian", VX(4, 0x535), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7830 {"zmheogsmf", VX(4, 0x538), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7831 {"zvdotphxgasmf", VX(4, 0x539), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7832 {"zmheogsmfaa", VX(4, 0x53A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7833 {"zvdotphxgasmfaa", VX(4, 0x53B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7834 {"zmheogsmfan", VX(4, 0x53C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7835 {"zvdotphxgasmfan", VX(4, 0x53D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7836 {"zmhogui", VX(4, 0x540), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7837 {"zvdotphgsui", VX(4, 0x541), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7838 {"zmhoguiaa", VX(4, 0x542), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7839 {"zvdotphgsuiaa", VX(4, 0x543), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7840 {"zmhoguian", VX(4, 0x544), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7841 {"zvdotphgsuian", VX(4, 0x545), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7842 {"zmhogsi", VX(4, 0x548), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7843 {"zvdotphgssi", VX(4, 0x549), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7844 {"zmhogsiaa", VX(4, 0x54A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7845 {"zvdotphgssiaa", VX(4, 0x54B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7846 {"zmhogsian", VX(4, 0x54C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7847 {"zvdotphgssian", VX(4, 0x54D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7848 {"zmhogsui", VX(4, 0x550), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7849 {"zvdotphgssui", VX(4, 0x551), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7850 {"zmhogsuiaa", VX(4, 0x552), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7851 {"zvdotphgssuiaa", VX(4, 0x553), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7852 {"zmhogsuian", VX(4, 0x554), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7853 {"zvdotphgssuian", VX(4, 0x555), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7854 {"zmhogsmf", VX(4, 0x558), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7855 {"zvdotphgssmf", VX(4, 0x559), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7856 {"zmhogsmfaa", VX(4, 0x55A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7857 {"zvdotphgssmfaa", VX(4, 0x55B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7858 {"zmhogsmfan", VX(4, 0x55C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7859 {"zvdotphgssmfan", VX(4, 0x55D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7860 {"zmwgui", VX(4, 0x560), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7861 {"zmwguiaa", VX(4, 0x562), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7862 {"zmwguiaas", VX(4, 0x563), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7863 {"zmwguian", VX(4, 0x564), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7864 {"zmwguians", VX(4, 0x565), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7865 {"zmwgsi", VX(4, 0x568), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7866 {"zmwgsiaa", VX(4, 0x56A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7867 {"zmwgsiaas", VX(4, 0x56B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7868 {"zmwgsian", VX(4, 0x56C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7869 {"zmwgsians", VX(4, 0x56D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7870 {"zmwgsui", VX(4, 0x570), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7871 {"zmwgsuiaa", VX(4, 0x572), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7872 {"zmwgsuiaas", VX(4, 0x573), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7873 {"zmwgsuian", VX(4, 0x574), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7874 {"zmwgsuians", VX(4, 0x575), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7875 {"zmwgsmf", VX(4, 0x578), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7876 {"zmwgsmfr", VX(4, 0x579), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7877 {"zmwgsmfaa", VX(4, 0x57A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7878 {"zmwgsmfraa", VX(4, 0x57B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7879 {"zmwgsmfan", VX(4, 0x57C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7880 {"zmwgsmfran", VX(4, 0x57D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7881 {"zvmhului", VX(4, 0x580), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7882 {"zvmhuluiaa", VX(4, 0x582), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7883 {"zvmhuluiaas", VX(4, 0x583), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7884 {"zvmhuluian", VX(4, 0x584), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7885 {"zvmhuluians", VX(4, 0x585), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7886 {"zvmhuluianp", VX(4, 0x586), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7887 {"zvmhuluianps", VX(4, 0x587), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7888 {"zvmhulsi", VX(4, 0x588), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7889 {"zvmhulsiaa", VX(4, 0x58A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7890 {"zvmhulsiaas", VX(4, 0x58B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7891 {"zvmhulsian", VX(4, 0x58C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7892 {"zvmhulsians", VX(4, 0x58D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7893 {"zvmhulsianp", VX(4, 0x58E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7894 {"zvmhulsianps", VX(4, 0x58F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7895 {"zvmhulsui", VX(4, 0x590), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7896 {"zvmhulsuiaa", VX(4, 0x592), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7897 {"zvmhulsuiaas", VX(4, 0x593), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7898 {"zvmhulsuian", VX(4, 0x594), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7899 {"zvmhulsuians", VX(4, 0x595), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7900 {"zvmhulsuianp", VX(4, 0x596), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7901 {"zvmhulsuianps", VX(4, 0x597), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7902 {"zvmhulsf", VX(4, 0x598), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7903 {"zvmhulsfr", VX(4, 0x599), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7904 {"zvmhulsfaas", VX(4, 0x59A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7905 {"zvmhulsfraas", VX(4, 0x59B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7906 {"zvmhulsfans", VX(4, 0x59C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7907 {"zvmhulsfrans", VX(4, 0x59D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7908 {"zvmhulsfanps", VX(4, 0x59E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7909 {"zvmhulsfranps", VX(4, 0x59F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7910 {"zvmhllui", VX(4, 0x5A0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7911 {"zvmhlluiaa", VX(4, 0x5A2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7912 {"zvmhlluiaas", VX(4, 0x5A3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7913 {"zvmhlluian", VX(4, 0x5A4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7914 {"zvmhlluians", VX(4, 0x5A5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7915 {"zvmhlluianp", VX(4, 0x5A6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7916 {"zvmhlluianps", VX(4, 0x5A7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7917 {"zvmhllsi", VX(4, 0x5A8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7918 {"zvmhllsiaa", VX(4, 0x5AA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7919 {"zvmhllsiaas", VX(4, 0x5AB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7920 {"zvmhllsian", VX(4, 0x5AC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7921 {"zvmhllsians", VX(4, 0x5AD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7922 {"zvmhllsianp", VX(4, 0x5AE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7923 {"zvmhllsianps", VX(4, 0x5AF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7924 {"zvmhllsui", VX(4, 0x5B0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7925 {"zvmhllsuiaa", VX(4, 0x5B2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7926 {"zvmhllsuiaas", VX(4, 0x5B3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7927 {"zvmhllsuian", VX(4, 0x5B4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7928 {"zvmhllsuians", VX(4, 0x5B5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7929 {"zvmhllsuianp", VX(4, 0x5B6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7930 {"zvmhllsuianps", VX(4, 0x5B7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7931 {"zvmhllsf", VX(4, 0x5B8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7932 {"zvmhllsfr", VX(4, 0x5B9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7933 {"zvmhllsfaas", VX(4, 0x5BA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7934 {"zvmhllsfraas", VX(4, 0x5BB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7935 {"zvmhllsfans", VX(4, 0x5BC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7936 {"zvmhllsfrans", VX(4, 0x5BD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7937 {"zvmhllsfanps", VX(4, 0x5BE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7938 {"zvmhllsfranps", VX(4, 0x5BF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7939 {"zvmhuuui", VX(4, 0x5C0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7940 {"zvmhuuuiaa", VX(4, 0x5C2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7941 {"zvmhuuuiaas", VX(4, 0x5C3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7942 {"zvmhuuuian", VX(4, 0x5C4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7943 {"zvmhuuuians", VX(4, 0x5C5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7944 {"zvmhuuuianp", VX(4, 0x5C6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7945 {"zvmhuuuianps", VX(4, 0x5C7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7946 {"zvmhuusi", VX(4, 0x5C8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7947 {"zvmhuusiaa", VX(4, 0x5CA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7948 {"zvmhuusiaas", VX(4, 0x5CB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7949 {"zvmhuusian", VX(4, 0x5CC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7950 {"zvmhuusians", VX(4, 0x5CD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7951 {"zvmhuusianp", VX(4, 0x5CE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7952 {"zvmhuusianps", VX(4, 0x5CF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7953 {"zvmhuusui", VX(4, 0x5D0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7954 {"zvmhuusuiaa", VX(4, 0x5D2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7955 {"zvmhuusuiaas", VX(4, 0x5D3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7956 {"zvmhuusuian", VX(4, 0x5D4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7957 {"zvmhuusuians", VX(4, 0x5D5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7958 {"zvmhuusuianp", VX(4, 0x5D6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7959 {"zvmhuusuianps", VX(4, 0x5D7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7960 {"zvmhuusf", VX(4, 0x5D8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7961 {"zvmhuusfr", VX(4, 0x5D9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7962 {"zvmhuusfaas", VX(4, 0x5DA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7963 {"zvmhuusfraas", VX(4, 0x5DB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7964 {"zvmhuusfans", VX(4, 0x5DC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7965 {"zvmhuusfrans", VX(4, 0x5DD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7966 {"zvmhuusfanps", VX(4, 0x5DE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7967 {"zvmhuusfranps", VX(4, 0x5DF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7968 {"zvmhxlui", VX(4, 0x5E0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7969 {"zvmhxluiaa", VX(4, 0x5E2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7970 {"zvmhxluiaas", VX(4, 0x5E3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7971 {"zvmhxluian", VX(4, 0x5E4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7972 {"zvmhxluians", VX(4, 0x5E5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7973 {"zvmhxluianp", VX(4, 0x5E6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7974 {"zvmhxluianps", VX(4, 0x5E7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7975 {"zvmhxlsi", VX(4, 0x5E8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7976 {"zvmhxlsiaa", VX(4, 0x5EA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7977 {"zvmhxlsiaas", VX(4, 0x5EB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7978 {"zvmhxlsian", VX(4, 0x5EC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7979 {"zvmhxlsians", VX(4, 0x5ED), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7980 {"zvmhxlsianp", VX(4, 0x5EE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7981 {"zvmhxlsianps", VX(4, 0x5EF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7982 {"zvmhxlsui", VX(4, 0x5F0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7983 {"zvmhxlsuiaa", VX(4, 0x5F2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7984 {"zvmhxlsuiaas", VX(4, 0x5F3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7985 {"zvmhxlsuian", VX(4, 0x5F4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7986 {"zvmhxlsuians", VX(4, 0x5F5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7987 {"zvmhxlsuianp", VX(4, 0x5F6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7988 {"zvmhxlsuianps", VX(4, 0x5F7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7989 {"zvmhxlsf", VX(4, 0x5F8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7990 {"zvmhxlsfr", VX(4, 0x5F9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7991 {"zvmhxlsfaas", VX(4, 0x5FA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7992 {"zvmhxlsfraas", VX(4, 0x5FB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7993 {"zvmhxlsfans", VX(4, 0x5FC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7994 {"zvmhxlsfrans", VX(4, 0x5FD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7995 {"zvmhxlsfanps", VX(4, 0x5FE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7996 {"zvmhxlsfranps", VX(4, 0x5FF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7997 {"zmheui", VX(4, 0x600), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7998 {"zmheuiaa", VX(4, 0x602), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7999 {"zmheuiaas", VX(4, 0x603), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8000 {"zmheuian", VX(4, 0x604), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8001 {"zmheuians", VX(4, 0x605), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8002 {"zmhesi", VX(4, 0x608), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8003 {"zmhesiaa", VX(4, 0x60A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8004 {"zmhesiaas", VX(4, 0x60B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8005 {"zmhesian", VX(4, 0x60C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8006 {"zmhesians", VX(4, 0x60D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8007 {"zmhesui", VX(4, 0x610), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8008 {"zmhesuiaa", VX(4, 0x612), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8009 {"zmhesuiaas", VX(4, 0x613), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8010 {"zmhesuian", VX(4, 0x614), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8011 {"zmhesuians", VX(4, 0x615), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8012 {"zmhesf", VX(4, 0x618), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8013 {"zmhesfr", VX(4, 0x619), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8014 {"zmhesfaas", VX(4, 0x61A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8015 {"zmhesfraas", VX(4, 0x61B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8016 {"zmhesfans", VX(4, 0x61C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8017 {"zmhesfrans", VX(4, 0x61D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8018 {"zmheoui", VX(4, 0x620), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8019 {"zmheouiaa", VX(4, 0x622), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8020 {"zmheouiaas", VX(4, 0x623), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8021 {"zmheouian", VX(4, 0x624), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8022 {"zmheouians", VX(4, 0x625), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8023 {"zmheosi", VX(4, 0x628), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8024 {"zmheosiaa", VX(4, 0x62A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8025 {"zmheosiaas", VX(4, 0x62B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8026 {"zmheosian", VX(4, 0x62C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8027 {"zmheosians", VX(4, 0x62D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8028 {"zmheosui", VX(4, 0x630), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8029 {"zmheosuiaa", VX(4, 0x632), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8030 {"zmheosuiaas", VX(4, 0x633), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8031 {"zmheosuian", VX(4, 0x634), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8032 {"zmheosuians", VX(4, 0x635), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8033 {"zmheosf", VX(4, 0x638), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8034 {"zmheosfr", VX(4, 0x639), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8035 {"zmheosfaas", VX(4, 0x63A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8036 {"zmheosfraas", VX(4, 0x63B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8037 {"zmheosfans", VX(4, 0x63C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8038 {"zmheosfrans", VX(4, 0x63D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8039 {"zmhoui", VX(4, 0x640), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8040 {"zmhouiaa", VX(4, 0x642), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8041 {"zmhouiaas", VX(4, 0x643), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8042 {"zmhouian", VX(4, 0x644), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8043 {"zmhouians", VX(4, 0x645), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8044 {"zmhosi", VX(4, 0x648), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8045 {"zmhosiaa", VX(4, 0x64A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8046 {"zmhosiaas", VX(4, 0x64B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8047 {"zmhosian", VX(4, 0x64C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8048 {"zmhosians", VX(4, 0x64D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8049 {"zmhosui", VX(4, 0x650), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8050 {"zmhosuiaa", VX(4, 0x652), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8051 {"zmhosuiaas", VX(4, 0x653), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8052 {"zmhosuian", VX(4, 0x654), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8053 {"zmhosuians", VX(4, 0x655), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8054 {"zmhosf", VX(4, 0x658), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8055 {"zmhosfr", VX(4, 0x659), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8056 {"zmhosfaas", VX(4, 0x65A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8057 {"zmhosfraas", VX(4, 0x65B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8058 {"zmhosfans", VX(4, 0x65C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8059 {"zmhosfrans", VX(4, 0x65D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8060 {"zvmhuih", VX(4, 0x660), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8061 {"zvmhuihs", VX(4, 0x661), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8062 {"zvmhuiaah", VX(4, 0x662), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8063 {"zvmhuiaahs", VX(4, 0x663), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8064 {"zvmhuianh", VX(4, 0x664), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8065 {"zvmhuianhs", VX(4, 0x665), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8066 {"zvmhsihs", VX(4, 0x669), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8067 {"zvmhsiaahs", VX(4, 0x66B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8068 {"zvmhsianhs", VX(4, 0x66D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8069 {"zvmhsuihs", VX(4, 0x671), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8070 {"zvmhsuiaahs", VX(4, 0x673), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8071 {"zvmhsuianhs", VX(4, 0x675), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8072 {"zvmhsfh", VX(4, 0x678), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8073 {"zvmhsfrh", VX(4, 0x679), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8074 {"zvmhsfaahs", VX(4, 0x67A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8075 {"zvmhsfraahs", VX(4, 0x67B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8076 {"zvmhsfanhs", VX(4, 0x67C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8077 {"zvmhsfranhs", VX(4, 0x67D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8078 {"zvdotphaui", VX(4, 0x680), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8079 {"zvdotphauis", VX(4, 0x681), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8080 {"zvdotphauiaa", VX(4, 0x682), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8081 {"zvdotphauiaas", VX(4, 0x683), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8082 {"zvdotphauian", VX(4, 0x684), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8083 {"zvdotphauians", VX(4, 0x685), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8084 {"zvdotphasi", VX(4, 0x688), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8085 {"zvdotphasis", VX(4, 0x689), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8086 {"zvdotphasiaa", VX(4, 0x68A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8087 {"zvdotphasiaas", VX(4, 0x68B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8088 {"zvdotphasian", VX(4, 0x68C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8089 {"zvdotphasians", VX(4, 0x68D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8090 {"zvdotphasui", VX(4, 0x690), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8091 {"zvdotphasuis", VX(4, 0x691), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8092 {"zvdotphasuiaa", VX(4, 0x692), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8093 {"zvdotphasuiaas", VX(4, 0x693), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8094 {"zvdotphasuian", VX(4, 0x694), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8095 {"zvdotphasuians", VX(4, 0x695), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8096 {"zvdotphasfs", VX(4, 0x698), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8097 {"zvdotphasfrs", VX(4, 0x699), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8098 {"zvdotphasfaas", VX(4, 0x69A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8099 {"zvdotphasfraas", VX(4, 0x69B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8100 {"zvdotphasfans", VX(4, 0x69C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8101 {"zvdotphasfrans", VX(4, 0x69D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8102 {"zvdotphxaui", VX(4, 0x6A0), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8103 {"zvdotphxauis", VX(4, 0x6A1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8104 {"zvdotphxauiaa", VX(4, 0x6A2), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8105 {"zvdotphxauiaas", VX(4, 0x6A3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8106 {"zvdotphxauian", VX(4, 0x6A4), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8107 {"zvdotphxauians", VX(4, 0x6A5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8108 {"zvdotphxasi", VX(4, 0x6A8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8109 {"zvdotphxasis", VX(4, 0x6A9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8110 {"zvdotphxasiaa", VX(4, 0x6AA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8111 {"zvdotphxasiaas", VX(4, 0x6AB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8112 {"zvdotphxasian", VX(4, 0x6AC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8113 {"zvdotphxasians", VX(4, 0x6AD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8114 {"zvdotphxasui", VX(4, 0x6B0), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8115 {"zvdotphxasuis", VX(4, 0x6B1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8116 {"zvdotphxasuiaa", VX(4, 0x6B2), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8117 {"zvdotphxasuiaas", VX(4, 0x6B3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8118 {"zvdotphxasuian", VX(4, 0x6B4), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8119 {"zvdotphxasuians", VX(4, 0x6B5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8120 {"zvdotphxasfs", VX(4, 0x6B8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8121 {"zvdotphxasfrs", VX(4, 0x6B9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8122 {"zvdotphxasfaas", VX(4, 0x6BA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8123 {"zvdotphxasfraas", VX(4, 0x6BB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8124 {"zvdotphxasfans", VX(4, 0x6BC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8125 {"zvdotphxasfrans", VX(4, 0x6BD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8126 {"zvdotphsui", VX(4, 0x6C0), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8127 {"zvdotphsuis", VX(4, 0x6C1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8128 {"zvdotphsuiaa", VX(4, 0x6C2), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8129 {"zvdotphsuiaas", VX(4, 0x6C3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8130 {"zvdotphsuian", VX(4, 0x6C4), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8131 {"zvdotphsuians", VX(4, 0x6C5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8132 {"zvdotphssi", VX(4, 0x6C8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8133 {"zvdotphssis", VX(4, 0x6C9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8134 {"zvdotphssiaa", VX(4, 0x6CA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8135 {"zvdotphssiaas", VX(4, 0x6CB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8136 {"zvdotphssian", VX(4, 0x6CC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8137 {"zvdotphssians", VX(4, 0x6CD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8138 {"zvdotphssui", VX(4, 0x6D0), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8139 {"zvdotphssuis", VX(4, 0x6D1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8140 {"zvdotphssuiaa", VX(4, 0x6D2), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8141 {"zvdotphssuiaas", VX(4, 0x6D3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8142 {"zvdotphssuian", VX(4, 0x6D4), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8143 {"zvdotphssuians", VX(4, 0x6D5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8144 {"zvdotphssfs", VX(4, 0x6D8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8145 {"zvdotphssfrs", VX(4, 0x6D9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8146 {"zvdotphssfaas", VX(4, 0x6DA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8147 {"zvdotphssfraas", VX(4, 0x6DB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8148 {"zvdotphssfans", VX(4, 0x6DC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8149 {"zvdotphssfrans", VX(4, 0x6DD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8150 {"zmwluis", VX(4, 0x6E1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8151 {"zmwluiaa", VX(4, 0x6E2), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8152 {"zmwluiaas", VX(4, 0x6E3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8153 {"zmwluian", VX(4, 0x6E4), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8154 {"zmwluians", VX(4, 0x6E5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8155 {"zmwlsis", VX(4, 0x6E9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8156 {"zmwlsiaas", VX(4, 0x6EB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8157 {"zmwlsians", VX(4, 0x6ED), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8158 {"zmwlsuis", VX(4, 0x6F1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8159 {"zmwlsuiaas", VX(4, 0x6F3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8160 {"zmwlsuians", VX(4, 0x6F5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8161 {"zmwsf", VX(4, 0x6F8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8162 {"zmwsfr", VX(4, 0x6F9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8163 {"zmwsfaas", VX(4, 0x6FA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8164 {"zmwsfraas", VX(4, 0x6FB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8165 {"zmwsfans", VX(4, 0x6FC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8166 {"zmwsfrans", VX(4, 0x6FD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8167 {"zlddx", VX(4, 0x300), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
8168 {"zldd", VX(4, 0x301), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}},
8169 {"zldwx", VX(4, 0x302), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
8170 {"zldw", VX(4, 0x303), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}},
8171 {"zldhx", VX(4, 0x304), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
8172 {"zldh", VX(4, 0x305), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}},
8173 {"zlwgsfdx", VX(4, 0x308), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
8174 {"zlwgsfd", VX(4, 0x309), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
8175 {"zlwwosdx", VX(4, 0x30A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
8176 {"zlwwosd", VX(4, 0x30B), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
8177 {"zlwhsplatwdx", VX(4, 0x30C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
8178 {"zlwhsplatwd", VX(4, 0x30D), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
8179 {"zlwhsplatdx", VX(4, 0x30E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
8180 {"zlwhsplatd", VX(4, 0x30F), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
8181 {"zlwhgwsfdx", VX(4, 0x310), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
8182 {"zlwhgwsfd", VX(4, 0x311), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
8183 {"zlwhedx", VX(4, 0x312), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
8184 {"zlwhed", VX(4, 0x313), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
8185 {"zlwhosdx", VX(4, 0x314), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
8186 {"zlwhosd", VX(4, 0x315), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
8187 {"zlwhoudx", VX(4, 0x316), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
8188 {"zlwhoud", VX(4, 0x317), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
8189 {"zlwhx", VX(4, 0x318), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8190 {"zlwh", VX(4, 0x319), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4, RA}},
8191 {"zlwwx", VX(4, 0x31A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8192 {"zlww", VX(4, 0x31B), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4, RA}},
8193 {"zlhgwsfx", VX(4, 0x31C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8194 {"zlhgwsf", VX(4, 0x31D), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
8195 {"zlhhsplatx", VX(4, 0x31E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8196 {"zlhhsplat", VX(4, 0x31F), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
8197 {"zstddx", VX(4, 0x320), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
8198 {"zstdd", VX(4, 0x321), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}},
8199 {"zstdwx", VX(4, 0x322), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
8200 {"zstdw", VX(4, 0x323), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}},
8201 {"zstdhx", VX(4, 0x324), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
8202 {"zstdh", VX(4, 0x325), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}},
8203 {"zstwhedx", VX(4, 0x328), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
8204 {"zstwhed", VX(4, 0x329), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4, RA}},
8205 {"zstwhodx", VX(4, 0x32A), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
8206 {"zstwhod", VX(4, 0x32B), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4, RA}},
8207 {"zlhhex", VX(4, 0x330), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8208 {"zlhhe", VX(4, 0x331), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
8209 {"zlhhosx", VX(4, 0x332), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8210 {"zlhhos", VX(4, 0x333), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
8211 {"zlhhoux", VX(4, 0x334), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8212 {"zlhhou", VX(4, 0x335), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
8213 {"zsthex", VX(4, 0x338), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
8214 {"zsthe", VX(4, 0x339), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2, RA}},
8215 {"zsthox", VX(4, 0x33A), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
8216 {"zstho", VX(4, 0x33B), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2, RA}},
8217 {"zstwhx", VX(4, 0x33C), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
8218 {"zstwh", VX(4, 0x33D), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4, RA}},
8219 {"zstwwx", VX(4, 0x33E), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
8220 {"zstww", VX(4, 0x33F), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4, RA}},
8221 {"zlddmx", VX(4, 0x340), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
8222 {"zlddu", VX(4, 0x341), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}},
8223 {"zldwmx", VX(4, 0x342), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
8224 {"zldwu", VX(4, 0x343), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}},
8225 {"zldhmx", VX(4, 0x344), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
8226 {"zldhu", VX(4, 0x345), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}},
8227 {"zlwgsfdmx", VX(4, 0x348), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
8228 {"zlwgsfdu", VX(4, 0x349), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
8229 {"zlwwosdmx", VX(4, 0x34A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
8230 {"zlwwosdu", VX(4, 0x34B), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
8231 {"zlwhsplatwdmx", VX(4, 0x34C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
8232 {"zlwhsplatwdu", VX(4, 0x34D), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
8233 {"zlwhsplatdmx", VX(4, 0x34E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
8234 {"zlwhsplatdu", VX(4, 0x34F), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
8235 {"zlwhgwsfdmx", VX(4, 0x350), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
8236 {"zlwhgwsfdu", VX(4, 0x351), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
8237 {"zlwhedmx", VX(4, 0x352), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
8238 {"zlwhedu", VX(4, 0x353), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
8239 {"zlwhosdmx", VX(4, 0x354), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
8240 {"zlwhosdu", VX(4, 0x355), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
8241 {"zlwhoudmx", VX(4, 0x356), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
8242 {"zlwhoudu", VX(4, 0x357), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
8243 {"zlwhmx", VX(4, 0x358), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8244 {"zlwhu", VX(4, 0x359), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4_EX0, RA}},
8245 {"zlwwmx", VX(4, 0x35A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8246 {"zlwwu", VX(4, 0x35B), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4_EX0, RA}},
8247 {"zlhgwsfmx", VX(4, 0x35C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8248 {"zlhgwsfu", VX(4, 0x35D), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
8249 {"zlhhsplatmx", VX(4, 0x35E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8250 {"zlhhsplatu", VX(4, 0x35F), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
8251 {"zstddmx", VX(4, 0x360), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
8252 {"zstddu", VX(4, 0x361), VX_MASK, PPCLSP, 0, {RS, EVUIMM_8_EX0, RA}},
8253 {"zstdwmx", VX(4, 0x362), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
8254 {"zstdwu", VX(4, 0x363), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8_EX0, RA}},
8255 {"zstdhmx", VX(4, 0x364), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
8256 {"zstdhu", VX(4, 0x365), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8_EX0, RA}},
8257 {"zstwhedmx", VX(4, 0x368), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
8258 {"zstwhedu", VX(4, 0x369), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4_EX0, RA}},
8259 {"zstwhodmx", VX(4, 0x36A), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
8260 {"zstwhodu", VX(4, 0x36B), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4_EX0, RA}},
8261 {"zlhhemx", VX(4, 0x370), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8262 {"zlhheu", VX(4, 0x371), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
8263 {"zlhhosmx", VX(4, 0x372), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8264 {"zlhhosu", VX(4, 0x373), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
8265 {"zlhhoumx", VX(4, 0x374), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8266 {"zlhhouu", VX(4, 0x375), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
8267 {"zsthemx", VX(4, 0x378), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
8268 {"zstheu", VX(4, 0x379), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2_EX0, RA}},
8269 {"zsthomx", VX(4, 0x37A), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
8270 {"zsthou", VX(4, 0x37B), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2_EX0, RA}},
8271 {"zstwhmx", VX(4, 0x37C), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
8272 {"zstwhu", VX(4, 0x37D), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4_EX0, RA}},
8273 {"zstwwmx", VX(4, 0x37E), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
8274 {"zstwwu", VX(4, 0x37F), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4_EX0, RA}},
8275
8276 {"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
8277 {"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
8278 {"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
8279 {"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
8280 {"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
8281 {"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
8282 {"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
8283 {"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
8284 {"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
8285 {"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
8286 {"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
8287 {"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
8288 {"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
8289 {"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
8290 {"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
8291 {"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
8292 {"e_nop", SCI8(6,26), 0xffffffff, PPCVLE, 0, {0}},
8293 {"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
8294 {"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
8295 {"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
8296 {"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
8297 {"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
8298 {"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
8299 {"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
8300 {"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
8301 {"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
8302 {"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
8303 {"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
8304 {"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
8305 {"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
8306 {"e_lmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
8307 {"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
8308 {"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
8309 {"e_lmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
8310 {"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
8311 {"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
8312 {"e_lmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
8313 {"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
8314 {"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
8315 {"e_lmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
8316 {"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
8317 {"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
8318 {"e_lmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
8319 {"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
8320 {"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
8321 {"e_lmvmcsrrw", OPVUPRT(6,16,7),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
8322 {"e_stmvmcsrrw", OPVUPRT(6,17,7),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
8323 {"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}},
8324 {"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
8325 {"e_sub16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}},
8326
8327 {"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
8328 {"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
8329 {"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
8330 {"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
8331 {"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
8332 {"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
8333 {"se_andi", SE_IM5(11,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
8334
8335 {"e_lbz", OP(12), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
8336 {"e_stb", OP(13), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
8337 {"e_lha", OP(14), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
8338
8339 {"se_srw", SE_RR(16,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
8340 {"se_sraw", SE_RR(16,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
8341 {"se_slw", SE_RR(16,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
8342 {"se_nop", SE_RR(17,0), 0xffff, PPCVLE, 0, {0}},
8343 {"se_or", SE_RR(17,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
8344 {"se_andc", SE_RR(17,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
8345 {"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
8346 {"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
8347 {"se_li", IM7(9), IM7_MASK, PPCVLE, 0, {RX, UI7}},
8348
8349 {"e_lwz", OP(20), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
8350 {"e_stw", OP(21), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
8351 {"e_lhz", OP(22), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
8352 {"e_sth", OP(23), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
8353
8354 {"se_bclri", SE_IM5(24,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
8355 {"se_bgeni", SE_IM5(24,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
8356 {"se_bseti", SE_IM5(25,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
8357 {"se_btsti", SE_IM5(25,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
8358 {"se_srwi", SE_IM5(26,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
8359 {"se_srawi", SE_IM5(26,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
8360 {"se_slwi", SE_IM5(27,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
8361
8362 {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
8363 {"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
8364 {"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
8365 {"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
8366 {"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
8367 {"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
8368 {"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
8369 {"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
8370 {"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
8371 {"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
8372 {"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
8373 {"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
8374 {"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
8375 {"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
8376 {"e_li", LI20(28,0), LI20_MASK, PPCVLE, 0, {RT, IMM20}},
8377 {"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}},
8378 {"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RT, SH, MBE, ME}},
8379 {"e_b", BD24(30,0,0), BD24_MASK, PPCVLE, 0, {B24}},
8380 {"e_bl", BD24(30,0,1), BD24_MASK, PPCVLE, 0, {B24}},
8381 {"e_bdnz", EBD15(30,8,BO32DNZ,0), EBD15_MASK, PPCVLE, 0, {B15}},
8382 {"e_bdnzl", EBD15(30,8,BO32DNZ,1), EBD15_MASK, PPCVLE, 0, {B15}},
8383 {"e_bdz", EBD15(30,8,BO32DZ,0), EBD15_MASK, PPCVLE, 0, {B15}},
8384 {"e_bdzl", EBD15(30,8,BO32DZ,1), EBD15_MASK, PPCVLE, 0, {B15}},
8385 {"e_bge", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8386 {"e_bgel", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8387 {"e_bnl", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8388 {"e_bnll", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8389 {"e_blt", EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8390 {"e_bltl", EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8391 {"e_bgt", EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8392 {"e_bgtl", EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8393 {"e_ble", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8394 {"e_blel", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8395 {"e_bng", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8396 {"e_bngl", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8397 {"e_bne", EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8398 {"e_bnel", EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8399 {"e_beq", EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8400 {"e_beql", EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8401 {"e_bso", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8402 {"e_bsol", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8403 {"e_bun", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8404 {"e_bunl", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8405 {"e_bns", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8406 {"e_bnsl", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8407 {"e_bnu", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8408 {"e_bnul", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8409 {"e_bc", BD15(30,8,0), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
8410 {"e_bcl", BD15(30,8,1), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
8411
8412 {"e_bf", EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
8413 {"e_bfl", EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
8414 {"e_bt", EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
8415 {"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
8416
8417 {"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
8418 {"e_sc", X(31,36), XRTRA_MASK, PPCVLE, 0, {ELEV}},
8419 {"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
8420 {"e_crandc", XL(31,129), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
8421 {"e_crnand", XL(31,225), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
8422 {"e_crnot", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BBA}},
8423 {"e_crnor", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
8424 {"e_crclr", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}},
8425 {"e_crxor", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
8426 {"e_mcrf", XL(31,16), XL_MASK, PPCVLE, 0, {CRD, CR}},
8427 {"e_slwi", EX(31,112), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
8428 {"e_slwi.", EX(31,113), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
8429
8430 {"e_crand", XL(31,257), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
8431
8432 {"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
8433 {"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
8434
8435 {"e_crset", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}},
8436 {"e_creqv", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
8437
8438 {"e_rlwi", EX(31,624), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
8439 {"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
8440
8441 {"e_crorc", XL(31,417), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
8442
8443 {"e_crmove", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BBA}},
8444 {"e_cror", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
8445
8446 {"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, 0, {RS}},
8447
8448 {"e_srwi", EX(31,1136), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
8449 {"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
8450
8451 {"se_lbz", SD4(8), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
8452
8453 {"se_stb", SD4(9), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
8454
8455 {"se_lhz", SD4(10), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
8456
8457 {"se_sth", SD4(11), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
8458
8459 {"se_lwz", SD4(12), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
8460
8461 {"se_stw", SD4(13), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
8462
8463 {"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
8464 {"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
8465 {"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
8466 {"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
8467 {"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK, PPCVLE, 0, {B8}},
8468 {"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
8469 {"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
8470 {"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}},
8471 {"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
8472 {"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
8473 {"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK, PPCVLE, 0, {B8}},
8474 {"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
8475 {"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
8476 {"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}},
8477 {"se_bc", BD8IO(28), BD8IO_MASK, PPCVLE, 0, {BO16, BI16, B8}},
8478 {"se_b", BD8(58,0,0), BD8_MASK, PPCVLE, 0, {B8}},
8479 {"se_bl", BD8(58,0,1), BD8_MASK, PPCVLE, 0, {B8}},
8480 };
8481
8482 const unsigned int vle_num_opcodes =
8483 sizeof (vle_opcodes) / sizeof (vle_opcodes[0]);
8484 \f
8485 /* The macro table. This is only used by the assembler. */
8486
8487 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
8488 when x=0; 32-x when x is between 1 and 31; are negative if x is
8489 negative; and are 32 or more otherwise. This is what you want
8490 when, for instance, you are emulating a right shift by a
8491 rotate-left-and-mask, because the underlying instructions support
8492 shifts of size 0 but not shifts of size 32. By comparison, when
8493 extracting x bits from some word you want to use just 32-x, because
8494 the underlying instructions don't support extracting 0 bits but do
8495 support extracting the whole word (32 bits in this case). */
8496
8497 const struct powerpc_macro powerpc_macros[] = {
8498 {"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"},
8499 {"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"},
8500 {"extrdi", 4, PPC64, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
8501 {"extrdi.", 4, PPC64, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
8502 {"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"},
8503 {"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"},
8504 {"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
8505 {"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
8506 {"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"},
8507 {"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"},
8508 {"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
8509 {"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
8510 {"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"},
8511 {"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"},
8512 {"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"},
8513 {"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"},
8514
8515 {"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
8516 {"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
8517 {"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
8518 {"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
8519 {"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
8520 {"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
8521 {"insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
8522 {"insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
8523 {"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
8524 {"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
8525 {"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"},
8526 {"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
8527 {"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"},
8528 {"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"},
8529 {"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
8530 {"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
8531 {"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
8532 {"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
8533 {"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"},
8534 {"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
8535 {"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
8536 {"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
8537
8538 {"e_extlwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"},
8539 {"e_extrwi", 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
8540 {"e_inslwi", 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
8541 {"e_insrwi", 4, PPCVLE, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
8542 {"e_rotlwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31"},
8543 {"e_rotrwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
8544 {"e_slwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31-(%2)"},
8545 {"e_srwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
8546 {"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"},
8547 {"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"},
8548 {"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
8549
8550 /* old SPE instructions have new names with the same opcodes */
8551 {"evsadd", 3, PPCSPE|PPCVLE, "efsadd %0,%1,%2"},
8552 {"evssub", 3, PPCSPE|PPCVLE, "efssub %0,%1,%2"},
8553 {"evsabs", 2, PPCSPE|PPCVLE, "efsabs %0,%1"},
8554 {"evsnabs", 2, PPCSPE|PPCVLE, "efsnabs %0,%1"},
8555 {"evsneg", 2, PPCSPE|PPCVLE, "efsneg %0,%1"},
8556 {"evsmul", 3, PPCSPE|PPCVLE, "efsmul %0,%1,%2"},
8557 {"evsdiv", 3, PPCSPE|PPCVLE, "efsdiv %0,%1,%2"},
8558 {"evscmpgt", 3, PPCSPE|PPCVLE, "efscmpgt %0,%1,%2"},
8559 {"evsgmplt", 3, PPCSPE|PPCVLE, "efscmplt %0,%1,%2"},
8560 {"evsgmpeq", 3, PPCSPE|PPCVLE, "efscmpeq %0,%1,%2"},
8561 {"evscfui", 2, PPCSPE|PPCVLE, "efscfui %0,%1"},
8562 {"evscfsi", 2, PPCSPE|PPCVLE, "efscfsi %0,%1"},
8563 {"evscfuf", 2, PPCSPE|PPCVLE, "efscfuf %0,%1"},
8564 {"evscfsf", 2, PPCSPE|PPCVLE, "efscfsf %0,%1"},
8565 {"evsctui", 2, PPCSPE|PPCVLE, "efsctui %0,%1"},
8566 {"evsctsi", 2, PPCSPE|PPCVLE, "efsctsi %0,%1"},
8567 {"evsctuf", 2, PPCSPE|PPCVLE, "efsctuf %0,%1"},
8568 {"evsctsf", 2, PPCSPE|PPCVLE, "efsctsf %0,%1"},
8569 {"evsctuiz", 2, PPCSPE|PPCVLE, "efsctuiz %0,%1"},
8570 {"evsctsiz", 2, PPCSPE|PPCVLE, "efsctsiz %0,%1"},
8571 {"evststgt", 3, PPCSPE|PPCVLE, "efststgt %0,%1,%2"},
8572 {"evststlt", 3, PPCSPE|PPCVLE, "efststlt %0,%1,%2"},
8573 {"evststeq", 3, PPCSPE|PPCVLE, "efststeq %0,%1,%2"},
8574
8575 /* SPE2 instructions which just are mapped to SPE2 */
8576 {"evdotphsssi", 3, PPCSPE2, "evdotphssmi %0,%1,%2"},
8577 {"evdotphsssia", 3, PPCSPE2, "evdotphssmia %0,%1,%2"},
8578 {"evdotpwsssi", 3, PPCSPE2, "evdotpwssmi %0,%1,%2"},
8579 {"evdotpwsssia", 3, PPCSPE2, "evdotpwssmia %0,%1,%2"}
8580 };
8581
8582 const int powerpc_num_macros =
8583 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
8584
8585 /* SPE v2 instruction set from SPE2PIM Rev. 2 08/2011 */
8586 const struct powerpc_opcode spe2_opcodes[] = {
8587 {"evdotpwcssi", VX (4, 128), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8588 {"evdotpwcsmi", VX (4, 129), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8589 {"evdotpwcssfr", VX (4, 130), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8590 {"evdotpwcssf", VX (4, 131), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8591 {"evdotpwgasmf", VX (4, 136), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8592 {"evdotpwxgasmf", VX (4, 137), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8593 {"evdotpwgasmfr", VX (4, 138), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8594 {"evdotpwxgasmfr", VX (4, 139), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8595 {"evdotpwgssmf", VX (4, 140), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8596 {"evdotpwxgssmf", VX (4, 141), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8597 {"evdotpwgssmfr", VX (4, 142), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8598 {"evdotpwxgssmfr", VX (4, 143), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8599 {"evdotpwcssiaaw3", VX (4, 144), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8600 {"evdotpwcsmiaaw3", VX (4, 145), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8601 {"evdotpwcssfraaw3", VX (4, 146), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8602 {"evdotpwcssfaaw3", VX (4, 147), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8603 {"evdotpwgasmfaa3", VX (4, 152), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8604 {"evdotpwxgasmfaa3", VX (4, 153), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8605 {"evdotpwgasmfraa3", VX (4, 154), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8606 {"evdotpwxgasmfraa3", VX (4, 155), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8607 {"evdotpwgssmfaa3", VX (4, 156), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8608 {"evdotpwxgssmfaa3", VX (4, 157), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8609 {"evdotpwgssmfraa3", VX (4, 158), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8610 {"evdotpwxgssmfraa3", VX (4, 159), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8611 {"evdotpwcssia", VX (4, 160), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8612 {"evdotpwcsmia", VX (4, 161), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8613 {"evdotpwcssfra", VX (4, 162), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8614 {"evdotpwcssfa", VX (4, 163), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8615 {"evdotpwgasmfa", VX (4, 168), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8616 {"evdotpwxgasmfa", VX (4, 169), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8617 {"evdotpwgasmfra", VX (4, 170), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8618 {"evdotpwxgasmfra", VX (4, 171), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8619 {"evdotpwgssmfa", VX (4, 172), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8620 {"evdotpwxgssmfa", VX (4, 173), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8621 {"evdotpwgssmfra", VX (4, 174), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8622 {"evdotpwxgssmfra", VX (4, 175), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8623 {"evdotpwcssiaaw", VX (4, 176), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8624 {"evdotpwcsmiaaw", VX (4, 177), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8625 {"evdotpwcssfraaw", VX (4, 178), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8626 {"evdotpwcssfaaw", VX (4, 179), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8627 {"evdotpwgasmfaa", VX (4, 184), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8628 {"evdotpwxgasmfaa", VX (4, 185), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8629 {"evdotpwgasmfraa", VX (4, 186), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8630 {"evdotpwxgasmfraa", VX (4, 187), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8631 {"evdotpwgssmfaa", VX (4, 188), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8632 {"evdotpwxgssmfaa", VX (4, 189), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8633 {"evdotpwgssmfraa", VX (4, 190), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8634 {"evdotpwxgssmfraa", VX (4, 191), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8635 {"evdotphihcssi", VX (4, 256), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8636 {"evdotplohcssi", VX (4, 257), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8637 {"evdotphihcssf", VX (4, 258), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8638 {"evdotplohcssf", VX (4, 259), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8639 {"evdotphihcsmi", VX (4, 264), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8640 {"evdotplohcsmi", VX (4, 265), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8641 {"evdotphihcssfr", VX (4, 266), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8642 {"evdotplohcssfr", VX (4, 267), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8643 {"evdotphihcssiaaw3", VX (4, 272), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8644 {"evdotplohcssiaaw3", VX (4, 273), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8645 {"evdotphihcssfaaw3", VX (4, 274), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8646 {"evdotplohcssfaaw3", VX (4, 275), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8647 {"evdotphihcsmiaaw3", VX (4, 280), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8648 {"evdotplohcsmiaaw3", VX (4, 281), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8649 {"evdotphihcssfraaw3", VX (4, 282), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8650 {"evdotplohcssfraaw3", VX (4, 283), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8651 {"evdotphihcssia", VX (4, 288), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8652 {"evdotplohcssia", VX (4, 289), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8653 {"evdotphihcssfa", VX (4, 290), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8654 {"evdotplohcssfa", VX (4, 291), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8655 {"evdotphihcsmia", VX (4, 296), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8656 {"evdotplohcsmia", VX (4, 297), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8657 {"evdotphihcssfra", VX (4, 298), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8658 {"evdotplohcssfra", VX (4, 299), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8659 {"evdotphihcssiaaw", VX (4, 304), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8660 {"evdotplohcssiaaw", VX (4, 305), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8661 {"evdotphihcssfaaw", VX (4, 306), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8662 {"evdotplohcssfaaw", VX (4, 307), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8663 {"evdotphihcsmiaaw", VX (4, 312), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8664 {"evdotplohcsmiaaw", VX (4, 313), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8665 {"evdotphihcssfraaw", VX (4, 314), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8666 {"evdotplohcssfraaw", VX (4, 315), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8667 {"evdotphausi", VX (4, 320), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8668 {"evdotphassi", VX (4, 321), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8669 {"evdotphasusi", VX (4, 322), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8670 {"evdotphassf", VX (4, 323), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8671 {"evdotphsssf", VX (4, 327), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8672 {"evdotphaumi", VX (4, 328), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8673 {"evdotphasmi", VX (4, 329), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8674 {"evdotphasumi", VX (4, 330), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8675 {"evdotphassfr", VX (4, 331), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8676 {"evdotphssmi", VX (4, 333), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8677 {"evdotphsssfr", VX (4, 335), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8678 {"evdotphausiaaw3", VX (4, 336), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8679 {"evdotphassiaaw3", VX (4, 337), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8680 {"evdotphasusiaaw3", VX (4, 338), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8681 {"evdotphassfaaw3", VX (4, 339), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8682 {"evdotphsssiaaw3", VX (4, 341), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8683 {"evdotphsssfaaw3", VX (4, 343), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8684 {"evdotphaumiaaw3", VX (4, 344), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8685 {"evdotphasmiaaw3", VX (4, 345), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8686 {"evdotphasumiaaw3", VX (4, 346), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8687 {"evdotphassfraaw3", VX (4, 347), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8688 {"evdotphssmiaaw3", VX (4, 349), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8689 {"evdotphsssfraaw3", VX (4, 351), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8690 {"evdotphausia", VX (4, 352), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8691 {"evdotphassia", VX (4, 353), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8692 {"evdotphasusia", VX (4, 354), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8693 {"evdotphassfa", VX (4, 355), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8694 {"evdotphsssfa", VX (4, 359), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8695 {"evdotphaumia", VX (4, 360), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8696 {"evdotphasmia", VX (4, 361), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8697 {"evdotphasumia", VX (4, 362), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8698 {"evdotphassfra", VX (4, 363), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8699 {"evdotphssmia", VX (4, 365), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8700 {"evdotphsssfra", VX (4, 367), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8701 {"evdotphausiaaw", VX (4, 368), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8702 {"evdotphassiaaw", VX (4, 369), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8703 {"evdotphasusiaaw", VX (4, 370), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8704 {"evdotphassfaaw", VX (4, 371), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8705 {"evdotphsssiaaw", VX (4, 373), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8706 {"evdotphsssfaaw", VX (4, 375), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8707 {"evdotphaumiaaw", VX (4, 376), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8708 {"evdotphasmiaaw", VX (4, 377), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8709 {"evdotphasumiaaw", VX (4, 378), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8710 {"evdotphassfraaw", VX (4, 379), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8711 {"evdotphssmiaaw", VX (4, 381), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8712 {"evdotphsssfraaw", VX (4, 383), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8713 {"evdotp4hgaumi", VX (4, 384), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8714 {"evdotp4hgasmi", VX (4, 385), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8715 {"evdotp4hgasumi", VX (4, 386), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8716 {"evdotp4hgasmf", VX (4, 387), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8717 {"evdotp4hgssmi", VX (4, 388), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8718 {"evdotp4hgssmf", VX (4, 389), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8719 {"evdotp4hxgasmi", VX (4, 390), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8720 {"evdotp4hxgasmf", VX (4, 391), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8721 {"evdotpbaumi", VX (4, 392), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8722 {"evdotpbasmi", VX (4, 393), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8723 {"evdotpbasumi", VX (4, 394), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8724 {"evdotp4hxgssmi", VX (4, 398), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8725 {"evdotp4hxgssmf", VX (4, 399), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8726 {"evdotp4hgaumiaa3", VX (4, 400), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8727 {"evdotp4hgasmiaa3", VX (4, 401), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8728 {"evdotp4hgasumiaa3", VX (4, 402), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8729 {"evdotp4hgasmfaa3", VX (4, 403), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8730 {"evdotp4hgssmiaa3", VX (4, 404), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8731 {"evdotp4hgssmfaa3", VX (4, 405), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8732 {"evdotp4hxgasmiaa3", VX (4, 406), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8733 {"evdotp4hxgasmfaa3", VX (4, 407), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8734 {"evdotpbaumiaaw3", VX (4, 408), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8735 {"evdotpbasmiaaw3", VX (4, 409), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8736 {"evdotpbasumiaaw3", VX (4, 410), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8737 {"evdotp4hxgssmiaa3", VX (4, 414), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8738 {"evdotp4hxgssmfaa3", VX (4, 415), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8739 {"evdotp4hgaumia", VX (4, 416), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8740 {"evdotp4hgasmia", VX (4, 417), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8741 {"evdotp4hgasumia", VX (4, 418), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8742 {"evdotp4hgasmfa", VX (4, 419), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8743 {"evdotp4hgssmia", VX (4, 420), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8744 {"evdotp4hgssmfa", VX (4, 421), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8745 {"evdotp4hxgasmia", VX (4, 422), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8746 {"evdotp4hxgasmfa", VX (4, 423), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8747 {"evdotpbaumia", VX (4, 424), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8748 {"evdotpbasmia", VX (4, 425), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8749 {"evdotpbasumia", VX (4, 426), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8750 {"evdotp4hxgssmia", VX (4, 430), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8751 {"evdotp4hxgssmfa", VX (4, 431), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8752 {"evdotp4hgaumiaa", VX (4, 432), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8753 {"evdotp4hgasmiaa", VX (4, 433), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8754 {"evdotp4hgasumiaa", VX (4, 434), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8755 {"evdotp4hgasmfaa", VX (4, 435), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8756 {"evdotp4hgssmiaa", VX (4, 436), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8757 {"evdotp4hgssmfaa", VX (4, 437), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8758 {"evdotp4hxgasmiaa", VX (4, 438), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8759 {"evdotp4hxgasmfaa", VX (4, 439), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8760 {"evdotpbaumiaaw", VX (4, 440), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8761 {"evdotpbasmiaaw", VX (4, 441), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8762 {"evdotpbasumiaaw", VX (4, 442), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8763 {"evdotp4hxgssmiaa", VX (4, 446), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8764 {"evdotp4hxgssmfaa", VX (4, 447), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8765 {"evdotpwausi", VX (4, 448), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8766 {"evdotpwassi", VX (4, 449), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8767 {"evdotpwasusi", VX (4, 450), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8768 {"evdotpwaumi", VX (4, 456), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8769 {"evdotpwasmi", VX (4, 457), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8770 {"evdotpwasumi", VX (4, 458), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8771 {"evdotpwssmi", VX (4, 461), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8772 {"evdotpwausiaa3", VX (4, 464), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8773 {"evdotpwassiaa3", VX (4, 465), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8774 {"evdotpwasusiaa3", VX (4, 466), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8775 {"evdotpwsssiaa3", VX (4, 469), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8776 {"evdotpwaumiaa3", VX (4, 472), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8777 {"evdotpwasmiaa3", VX (4, 473), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8778 {"evdotpwasumiaa3", VX (4, 474), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8779 {"evdotpwssmiaa3", VX (4, 477), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8780 {"evdotpwausia", VX (4, 480), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8781 {"evdotpwassia", VX (4, 481), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8782 {"evdotpwasusia", VX (4, 482), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8783 {"evdotpwaumia", VX (4, 488), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8784 {"evdotpwasmia", VX (4, 489), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8785 {"evdotpwasumia", VX (4, 490), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8786 {"evdotpwssmia", VX (4, 493), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8787 {"evdotpwausiaa", VX (4, 496), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8788 {"evdotpwassiaa", VX (4, 497), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8789 {"evdotpwasusiaa", VX (4, 498), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8790 {"evdotpwsssiaa", VX (4, 501), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8791 {"evdotpwaumiaa", VX (4, 504), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8792 {"evdotpwasmiaa", VX (4, 505), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8793 {"evdotpwasumiaa", VX (4, 506), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8794 {"evdotpwssmiaa", VX (4, 509), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8795 {"evaddib", VX (4, 515), VX_MASK, PPCSPE2, 0, {RD, RB, UIMM}},
8796 {"evaddih", VX (4, 513), VX_MASK, PPCSPE2, 0, {RD, RB, UIMM}},
8797 {"evsubifh", VX (4, 517), VX_MASK, PPCSPE2, 0, {RD, UIMM, RB}},
8798 {"evsubifb", VX (4, 519), VX_MASK, PPCSPE2, 0, {RD, UIMM, RB}},
8799 {"evabsb", VX_RB_CONST(4, 520, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8800 {"evabsh", VX_RB_CONST(4, 520, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8801 {"evabsd", VX_RB_CONST(4, 520, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8802 {"evabss", VX_RB_CONST(4, 520, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8803 {"evabsbs", VX_RB_CONST(4, 520, 10), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8804 {"evabshs", VX_RB_CONST(4, 520, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8805 {"evabsds", VX_RB_CONST(4, 520, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8806 {"evnegwo", VX_RB_CONST(4, 521, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8807 {"evnegb", VX_RB_CONST(4, 521, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8808 {"evnegbo", VX_RB_CONST(4, 521, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8809 {"evnegh", VX_RB_CONST(4, 521, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8810 {"evnegho", VX_RB_CONST(4, 521, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8811 {"evnegd", VX_RB_CONST(4, 521, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8812 {"evnegs", VX_RB_CONST(4, 521, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8813 {"evnegwos", VX_RB_CONST(4, 521, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8814 {"evnegbs", VX_RB_CONST(4, 521, 10), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8815 {"evnegbos", VX_RB_CONST(4, 521, 11), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8816 {"evneghs", VX_RB_CONST(4, 521, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8817 {"evneghos", VX_RB_CONST(4, 521, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8818 {"evnegds", VX_RB_CONST(4, 521, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8819 {"evextzb", VX_RB_CONST(4, 522, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8820 {"evextsbh", VX_RB_CONST(4, 522, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8821 {"evextsw", VX_RB_CONST(4, 523, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8822 {"evrndwh", VX_RB_CONST(4, 524, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8823 {"evrndhb", VX_RB_CONST(4, 524, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8824 {"evrnddw", VX_RB_CONST(4, 524, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8825 {"evrndwhus", VX_RB_CONST(4, 524, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8826 {"evrndwhss", VX_RB_CONST(4, 524, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8827 {"evrndhbus", VX_RB_CONST(4, 524, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8828 {"evrndhbss", VX_RB_CONST(4, 524, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8829 {"evrnddwus", VX_RB_CONST(4, 524, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8830 {"evrnddwss", VX_RB_CONST(4, 524, 15), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8831 {"evrndwnh", VX_RB_CONST(4, 524, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8832 {"evrndhnb", VX_RB_CONST(4, 524, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8833 {"evrnddnw", VX_RB_CONST(4, 524, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8834 {"evrndwnhus", VX_RB_CONST(4, 524, 24), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8835 {"evrndwnhss", VX_RB_CONST(4, 524, 25), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8836 {"evrndhnbus", VX_RB_CONST(4, 524, 28), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8837 {"evrndhnbss", VX_RB_CONST(4, 524, 29), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8838 {"evrnddnwus", VX_RB_CONST(4, 524, 30), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8839 {"evrnddnwss", VX_RB_CONST(4, 524, 31), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8840 {"evcntlzh", VX_RB_CONST(4, 525, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8841 {"evcntlsh", VX_RB_CONST(4, 526, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8842 {"evpopcntb", VX_RB_CONST(4, 526, 26), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8843 {"circinc", VX (4, 528), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8844 {"evunpkhibui", VX_RB_CONST(4, 540, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8845 {"evunpkhibsi", VX_RB_CONST(4, 540, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8846 {"evunpkhihui", VX_RB_CONST(4, 540, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8847 {"evunpkhihsi", VX_RB_CONST(4, 540, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8848 {"evunpklobui", VX_RB_CONST(4, 540, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8849 {"evunpklobsi", VX_RB_CONST(4, 540, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8850 {"evunpklohui", VX_RB_CONST(4, 540, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8851 {"evunpklohsi", VX_RB_CONST(4, 540, 7), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8852 {"evunpklohf", VX_RB_CONST(4, 540, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8853 {"evunpkhihf", VX_RB_CONST(4, 540, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8854 {"evunpklowgsf", VX_RB_CONST(4, 540, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8855 {"evunpkhiwgsf", VX_RB_CONST(4, 540, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8856 {"evsatsduw", VX_RB_CONST(4, 540, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8857 {"evsatsdsw", VX_RB_CONST(4, 540, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8858 {"evsatshub", VX_RB_CONST(4, 540, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8859 {"evsatshsb", VX_RB_CONST(4, 540, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8860 {"evsatuwuh", VX_RB_CONST(4, 540, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8861 {"evsatswsh", VX_RB_CONST(4, 540, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8862 {"evsatswuh", VX_RB_CONST(4, 540, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8863 {"evsatuhub", VX_RB_CONST(4, 540, 23), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8864 {"evsatuduw", VX_RB_CONST(4, 540, 24), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8865 {"evsatuwsw", VX_RB_CONST(4, 540, 25), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8866 {"evsatshuh", VX_RB_CONST(4, 540, 26), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8867 {"evsatuhsh", VX_RB_CONST(4, 540, 27), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8868 {"evsatswuw", VX_RB_CONST(4, 540, 28), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8869 {"evsatswgsdf", VX_RB_CONST(4, 540, 29), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8870 {"evsatsbub", VX_RB_CONST(4, 540, 30), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8871 {"evsatubsb", VX_RB_CONST(4, 540, 31), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8872 {"evmaxhpuw", VX_RB_CONST(4, 541, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8873 {"evmaxhpsw", VX_RB_CONST(4, 541, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8874 {"evmaxbpuh", VX_RB_CONST(4, 541, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8875 {"evmaxbpsh", VX_RB_CONST(4, 541, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8876 {"evmaxwpud", VX_RB_CONST(4, 541, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8877 {"evmaxwpsd", VX_RB_CONST(4, 541, 7), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8878 {"evminhpuw", VX_RB_CONST(4, 541, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8879 {"evminhpsw", VX_RB_CONST(4, 541, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8880 {"evminbpuh", VX_RB_CONST(4, 541, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8881 {"evminbpsh", VX_RB_CONST(4, 541, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8882 {"evminwpud", VX_RB_CONST(4, 541, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8883 {"evminwpsd", VX_RB_CONST(4, 541, 15), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
8884 {"evmaxmagws", VX (4, 543), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8885 {"evsl", VX (4, 549), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8886 {"evsli", VX (4, 551), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}},
8887 {"evsplatie", VX_RB_CONST (4, 553, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
8888 {"evsplatib", VX_RB_CONST (4, 553, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
8889 {"evsplatibe", VX_RB_CONST (4, 553, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
8890 {"evsplatih", VX_RB_CONST (4, 553, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
8891 {"evsplatihe", VX_RB_CONST (4, 553, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
8892 {"evsplatid", VX_RB_CONST (4, 553, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
8893 {"evsplatia", VX_RB_CONST (4, 553, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
8894 {"evsplatiea", VX_RB_CONST (4, 553, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
8895 {"evsplatiba", VX_RB_CONST (4, 553, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
8896 {"evsplatibea", VX_RB_CONST (4, 553, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
8897 {"evsplatiha", VX_RB_CONST (4, 553, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
8898 {"evsplatihea", VX_RB_CONST (4, 553, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
8899 {"evsplatida", VX_RB_CONST (4, 553, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
8900 {"evsplatfio", VX_RB_CONST (4, 555, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
8901 {"evsplatfib", VX_RB_CONST (4, 555, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
8902 {"evsplatfibo", VX_RB_CONST (4, 555, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
8903 {"evsplatfih", VX_RB_CONST (4, 555, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
8904 {"evsplatfiho", VX_RB_CONST (4, 555, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
8905 {"evsplatfid", VX_RB_CONST (4, 555, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
8906 {"evsplatfia", VX_RB_CONST (4, 555, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
8907 {"evsplatfioa", VX_RB_CONST (4, 555, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
8908 {"evsplatfiba", VX_RB_CONST (4, 555, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
8909 {"evsplatfiboa", VX_RB_CONST (4, 555, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
8910 {"evsplatfiha", VX_RB_CONST (4, 555, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
8911 {"evsplatfihoa", VX_RB_CONST (4, 555, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
8912 {"evsplatfida", VX_RB_CONST (4, 555, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
8913 {"evcmpgtdu", VX_SPE_CRFD (4, 560, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}},
8914 {"evcmpgtds", VX_SPE_CRFD (4, 561, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}},
8915 {"evcmpltdu", VX_SPE_CRFD (4, 562, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}},
8916 {"evcmpltds", VX_SPE_CRFD (4, 563, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}},
8917 {"evcmpeqd", VX_SPE_CRFD (4, 564, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}},
8918 {"evswapbhilo", VX (4, 568), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8919 {"evswapblohi", VX (4, 569), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8920 {"evswaphhilo", VX (4, 570), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8921 {"evswaphlohi", VX (4, 571), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8922 {"evswaphe", VX (4, 572), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8923 {"evswaphhi", VX (4, 573), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8924 {"evswaphlo", VX (4, 574), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8925 {"evswapho", VX (4, 575), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8926 {"evinsb", VX (4, 584), VX_MASK_DDD, PPCSPE2, 0, {RD, RA, DDD, BBB}},
8927 {"evxtrb", VX (4, 586), VX_MASK_DDD, PPCSPE2, 0, {RD, RA, DDD, BBB}},
8928 {"evsplath", VX_SPE2_HH (4, 588, 0, 0), VX_SPE2_HH_MASK, PPCSPE2, 0, {RD, RA, HH}},
8929 {"evsplatb", VX_SPE2_SPLATB (4, 588, 2), VX_SPE2_SPLATB_MASK, PPCSPE2, 0, {RD, RA, BBB}},
8930 {"evinsh", VX_SPE2_DDHH (4, 589, 0), VX_SPE2_DDHH_MASK, PPCSPE2, 0, {RD, RA, DD, HH}},
8931 {"evclrbe", VX_SPE2_CLR (4, 590, 0), VX_SPE2_CLR_MASK, PPCSPE2, 0, {RD, RA, MMMM}},
8932 {"evclrbo", VX_SPE2_CLR (4, 590, 1), VX_SPE2_CLR_MASK, PPCSPE2, 0, {RD, RA, MMMM}},
8933 {"evclrh", VX_SPE2_CLR (4, 591, 1), VX_SPE2_CLR_MASK, PPCSPE2, 0, {RD, RA, MMMM}},
8934 {"evxtrh", VX_SPE2_DDHH (4, 591, 0), VX_SPE2_DDHH_MASK, PPCSPE2, 0, {RD, RA, DD, HH}},
8935 {"evselbitm0", VX (4, 592), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8936 {"evselbitm1", VX (4, 593), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8937 {"evselbit", VX (4, 594), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8938 {"evperm", VX (4, 596), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8939 {"evperm2", VX (4, 597), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8940 {"evperm3", VX (4, 598), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8941 {"evxtrd", VX (4, 600), VX_OFF_SPE2_MASK, PPCSPE2, 0, {RD, RA, RB, VX_OFF_SPE2}},
8942 {"evsrbu", VX (4, 608), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8943 {"evsrbs", VX (4, 609), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8944 {"evsrbiu", VX (4, 610), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}},
8945 {"evsrbis", VX (4, 611), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}},
8946 {"evslb", VX (4, 612), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8947 {"evrlb", VX (4, 613), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8948 {"evslbi", VX (4, 614), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}},
8949 {"evrlbi", VX (4, 615), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}},
8950 {"evsrhu", VX (4, 616), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8951 {"evsrhs", VX (4, 617), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8952 {"evsrhiu", VX (4, 618), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}},
8953 {"evsrhis", VX (4, 619), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}},
8954 {"evslh", VX (4, 620), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8955 {"evrlh", VX (4, 621), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8956 {"evslhi", VX (4, 622), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}},
8957 {"evrlhi", VX (4, 623), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}},
8958 {"evsru", VX (4, 624), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8959 {"evsrs", VX (4, 625), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8960 {"evsriu", VX (4, 626), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}},
8961 {"evsris", VX (4, 627), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}},
8962 {"evlvsl", VX (4, 628), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8963 {"evlvsr", VX (4, 629), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8964 {"evsroiu", VX_SPE2_OCTET (4, 631, 0), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}},
8965 {"evsrois", VX_SPE2_OCTET (4, 631, 1), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}},
8966 {"evsloi", VX_SPE2_OCTET (4, 631, 2), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}},
8967 {"evldbx", VX (4, 774), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8968 {"evldb", VX (4, 775), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8, RA}},
8969 {"evlhhsplathx", VX (4, 778), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8970 {"evlhhsplath", VX (4, 779), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2, RA}},
8971 {"evlwbsplatwx", VX (4, 786), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8972 {"evlwbsplatw", VX (4, 787), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}},
8973 {"evlwhsplatwx", VX (4, 794), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8974 {"evlwhsplatw", VX (4, 795), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}},
8975 {"evlbbsplatbx", VX (4, 798), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8976 {"evlbbsplatb", VX (4, 799), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_1, RA}},
8977 {"evstdbx", VX (4, 806), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
8978 {"evstdb", VX (4, 807), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8, RA}},
8979 {"evlwbex", VX (4, 810), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8980 {"evlwbe", VX (4, 811), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}},
8981 {"evlwboux", VX (4, 812), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8982 {"evlwbou", VX (4, 813), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}},
8983 {"evlwbosx", VX (4, 814), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8984 {"evlwbos", VX (4, 815), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}},
8985 {"evstwbex", VX (4, 818), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
8986 {"evstwbe", VX (4, 819), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}},
8987 {"evstwbox", VX (4, 822), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
8988 {"evstwbo", VX (4, 823), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}},
8989 {"evstwbx", VX (4, 826), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
8990 {"evstwb", VX (4, 827), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}},
8991 {"evsthbx", VX (4, 830), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
8992 {"evsthb", VX (4, 831), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_2, RA}},
8993 {"evlddmx", VX (4, 832), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8994 {"evlddu", VX (4, 833), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}},
8995 {"evldwmx", VX (4, 834), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8996 {"evldwu", VX (4, 835), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}},
8997 {"evldhmx", VX (4, 836), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
8998 {"evldhu", VX (4, 837), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}},
8999 {"evldbmx", VX (4, 838), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9000 {"evldbu", VX (4, 839), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}},
9001 {"evlhhesplatmx", VX (4, 840), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9002 {"evlhhesplatu", VX (4, 841), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}},
9003 {"evlhhsplathmx", VX (4, 842), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9004 {"evlhhsplathu", VX (4, 843), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}},
9005 {"evlhhousplatmx", VX (4, 844), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9006 {"evlhhousplatu", VX (4, 845), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}},
9007 {"evlhhossplatmx", VX (4, 846), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9008 {"evlhhossplatu", VX (4, 847), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}},
9009 {"evlwhemx", VX (4, 848), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9010 {"evlwheu", VX (4, 849), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
9011 {"evlwbsplatwmx", VX (4, 850), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9012 {"evlwbsplatwu", VX (4, 851), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
9013 {"evlwhoumx", VX (4, 852), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9014 {"evlwhouu", VX (4, 853), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
9015 {"evlwhosmx", VX (4, 854), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9016 {"evlwhosu", VX (4, 855), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
9017 {"evlwwsplatmx", VX (4, 856), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9018 {"evlwwsplatu", VX (4, 857), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
9019 {"evlwhsplatwmx", VX (4, 858), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9020 {"evlwhsplatwu", VX (4, 859), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
9021 {"evlwhsplatmx", VX (4, 860), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9022 {"evlwhsplatu", VX (4, 861), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
9023 {"evlbbsplatbmx", VX (4, 862), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9024 {"evlbbsplatbu", VX (4, 863), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_1_EX0, RA}},
9025 {"evstddmx", VX (4, 864), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
9026 {"evstddu", VX (4, 865), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}},
9027 {"evstdwmx", VX (4, 866), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
9028 {"evstdwu", VX (4, 867), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}},
9029 {"evstdhmx", VX (4, 868), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
9030 {"evstdhu", VX (4, 869), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}},
9031 {"evstdbmx", VX (4, 870), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
9032 {"evstdbu", VX (4, 871), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}},
9033 {"evlwbemx", VX (4, 874), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9034 {"evlwbeu", VX (4, 875), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
9035 {"evlwboumx", VX (4, 876), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9036 {"evlwbouu", VX (4, 877), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
9037 {"evlwbosmx", VX (4, 878), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9038 {"evlwbosu", VX (4, 879), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
9039 {"evstwhemx", VX (4, 880), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
9040 {"evstwheu", VX (4, 881), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
9041 {"evstwbemx", VX (4, 882), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
9042 {"evstwbeu", VX (4, 883), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
9043 {"evstwhomx", VX (4, 884), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
9044 {"evstwhou", VX (4, 885), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
9045 {"evstwbomx", VX (4, 886), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
9046 {"evstwbou", VX (4, 887), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
9047 {"evstwwemx", VX (4, 888), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
9048 {"evstwweu", VX (4, 889), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
9049 {"evstwbmx", VX (4, 890), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
9050 {"evstwbu", VX (4, 891), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
9051 {"evstwwomx", VX (4, 892), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
9052 {"evstwwou", VX (4, 893), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
9053 {"evsthbmx", VX (4, 894), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
9054 {"evsthbu", VX (4, 895), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_2_EX0, RA}},
9055 {"evmhusi", VX (4, 1024), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9056 {"evmhssi", VX (4, 1025), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9057 {"evmhsusi", VX (4, 1026), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9058 {"evmhssf", VX (4, 1028), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9059 {"evmhumi", VX (4, 1029), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9060 {"evmhssfr", VX (4, 1030), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9061 {"evmhesumi", VX (4, 1034), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9062 {"evmhosumi", VX (4, 1038), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9063 {"evmbeumi", VX (4, 1048), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9064 {"evmbesmi", VX (4, 1049), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9065 {"evmbesumi", VX (4, 1050), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9066 {"evmboumi", VX (4, 1052), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9067 {"evmbosmi", VX (4, 1053), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9068 {"evmbosumi", VX (4, 1054), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9069 {"evmhesumia", VX (4, 1066), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9070 {"evmhosumia", VX (4, 1070), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9071 {"evmbeumia", VX (4, 1080), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9072 {"evmbesmia", VX (4, 1081), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9073 {"evmbesumia", VX (4, 1082), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9074 {"evmboumia", VX (4, 1084), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9075 {"evmbosmia", VX (4, 1085), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9076 {"evmbosumia", VX (4, 1086), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9077 {"evmwusiw", VX (4, 1088), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9078 {"evmwssiw", VX (4, 1089), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9079 {"evmwhssfr", VX (4, 1094), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9080 {"evmwehgsmfr", VX (4, 1110), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9081 {"evmwehgsmf", VX (4, 1111), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9082 {"evmwohgsmfr", VX (4, 1118), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9083 {"evmwohgsmf", VX (4, 1119), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9084 {"evmwhssfra", VX (4, 1126), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9085 {"evmwehgsmfra", VX (4, 1142), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9086 {"evmwehgsmfa", VX (4, 1143), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9087 {"evmwohgsmfra", VX (4, 1150), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9088 {"evmwohgsmfa", VX (4, 1151), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9089 {"evaddusiaa", VX_RB_CONST(4, 1152, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
9090 {"evaddssiaa", VX_RB_CONST(4, 1153, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
9091 {"evsubfusiaa", VX_RB_CONST(4, 1154, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
9092 {"evsubfssiaa", VX_RB_CONST(4, 1155, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
9093 {"evaddsmiaa", VX_RB_CONST(4, 1156, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
9094 {"evsubfsmiaa", VX_RB_CONST(4, 1158, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
9095 {"evaddh", VX (4, 1160), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9096 {"evaddhss", VX (4, 1161), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9097 {"evsubfh", VX (4, 1162), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9098 {"evsubfhss", VX (4, 1163), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9099 {"evaddhx", VX (4, 1164), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9100 {"evaddhxss", VX (4, 1165), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9101 {"evsubfhx", VX (4, 1166), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9102 {"evsubfhxss", VX (4, 1167), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9103 {"evaddd", VX (4, 1168), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9104 {"evadddss", VX (4, 1169), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9105 {"evsubfd", VX (4, 1170), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9106 {"evsubfdss", VX (4, 1171), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9107 {"evaddb", VX (4, 1172), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9108 {"evaddbss", VX (4, 1173), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9109 {"evsubfb", VX (4, 1174), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9110 {"evsubfbss", VX (4, 1175), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9111 {"evaddsubfh", VX (4, 1176), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9112 {"evaddsubfhss", VX (4, 1177), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9113 {"evsubfaddh", VX (4, 1178), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9114 {"evsubfaddhss", VX (4, 1179), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9115 {"evaddsubfhx", VX (4, 1180), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9116 {"evaddsubfhxss", VX (4, 1181), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9117 {"evsubfaddhx", VX (4, 1182), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9118 {"evsubfaddhxss", VX (4, 1183), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9119 {"evadddus", VX (4, 1184), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9120 {"evaddbus", VX (4, 1185), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9121 {"evsubfdus", VX (4, 1186), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9122 {"evsubfbus", VX (4, 1187), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9123 {"evaddwus", VX (4, 1188), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9124 {"evaddwxus", VX (4, 1189), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9125 {"evsubfwus", VX (4, 1190), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9126 {"evsubfwxus", VX (4, 1191), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9127 {"evadd2subf2h", VX (4, 1192), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9128 {"evadd2subf2hss", VX (4, 1193), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9129 {"evsubf2add2h", VX (4, 1194), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9130 {"evsubf2add2hss", VX (4, 1195), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9131 {"evaddhus", VX (4, 1196), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9132 {"evaddhxus", VX (4, 1197), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9133 {"evsubfhus", VX (4, 1198), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9134 {"evsubfhxus", VX (4, 1199), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9135 {"evaddwss", VX (4, 1201), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9136 {"evsubfwss", VX (4, 1203), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9137 {"evaddwx", VX (4, 1204), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9138 {"evaddwxss", VX (4, 1205), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9139 {"evsubfwx", VX (4, 1206), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9140 {"evsubfwxss", VX (4, 1207), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9141 {"evaddsubfw", VX (4, 1208), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9142 {"evaddsubfwss", VX (4, 1209), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9143 {"evsubfaddw", VX (4, 1210), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9144 {"evsubfaddwss", VX (4, 1211), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9145 {"evaddsubfwx", VX (4, 1212), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9146 {"evaddsubfwxss", VX (4, 1213), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9147 {"evsubfaddwx", VX (4, 1214), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9148 {"evsubfaddwxss", VX (4, 1215), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9149 {"evmar", VX_SPE2_EVMAR (4, 1220), VX_SPE2_EVMAR_MASK, PPCSPE2, 0, {RD}},
9150 {"evsumwu", VX_RB_CONST(4, 1221, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
9151 {"evsumws", VX_RB_CONST(4, 1221, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
9152 {"evsum4bu", VX_RB_CONST(4, 1221, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
9153 {"evsum4bs", VX_RB_CONST(4, 1221, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
9154 {"evsum2hu", VX_RB_CONST(4, 1221, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
9155 {"evsum2hs", VX_RB_CONST(4, 1221, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
9156 {"evdiff2his", VX_RB_CONST(4, 1221, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
9157 {"evsum2his", VX_RB_CONST(4, 1221, 7), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
9158 {"evsumwua", VX_RB_CONST(4, 1221, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
9159 {"evsumwsa", VX_RB_CONST(4, 1221, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
9160 {"evsum4bua", VX_RB_CONST(4, 1221, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
9161 {"evsum4bsa", VX_RB_CONST(4, 1221, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
9162 {"evsum2hua", VX_RB_CONST(4, 1221, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
9163 {"evsum2hsa", VX_RB_CONST(4, 1221, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
9164 {"evdiff2hisa", VX_RB_CONST(4, 1221, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
9165 {"evsum2hisa", VX_RB_CONST(4, 1221, 23), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
9166 {"evsumwuaa", VX_RB_CONST(4, 1221, 24), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
9167 {"evsumwsaa", VX_RB_CONST(4, 1221, 25), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
9168 {"evsum4buaaw", VX_RB_CONST(4, 1221, 26), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
9169 {"evsum4bsaaw", VX_RB_CONST(4, 1221, 27), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
9170 {"evsum2huaaw", VX_RB_CONST(4, 1221, 28), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
9171 {"evsum2hsaaw", VX_RB_CONST(4, 1221, 29), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
9172 {"evdiff2hisaaw", VX_RB_CONST(4, 1221, 30), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
9173 {"evsum2hisaaw", VX_RB_CONST(4, 1221, 31), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
9174 {"evdivwsf", VX (4, 1228), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9175 {"evdivwuf", VX (4, 1229), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9176 {"evdivs", VX (4, 1230), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9177 {"evdivu", VX (4, 1231), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9178 {"evaddwegsi", VX (4, 1232), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9179 {"evaddwegsf", VX (4, 1233), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9180 {"evsubfwegsi", VX (4, 1234), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9181 {"evsubfwegsf", VX (4, 1235), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9182 {"evaddwogsi", VX (4, 1236), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9183 {"evaddwogsf", VX (4, 1237), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9184 {"evsubfwogsi", VX (4, 1238), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9185 {"evsubfwogsf", VX (4, 1239), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9186 {"evaddhhiuw", VX (4, 1240), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9187 {"evaddhhisw", VX (4, 1241), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9188 {"evsubfhhiuw", VX (4, 1242), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9189 {"evsubfhhisw", VX (4, 1243), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9190 {"evaddhlouw", VX (4, 1244), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9191 {"evaddhlosw", VX (4, 1245), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9192 {"evsubfhlouw", VX (4, 1246), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9193 {"evsubfhlosw", VX (4, 1247), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9194 {"evmhesusiaaw", VX (4, 1282), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9195 {"evmhosusiaaw", VX (4, 1286), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9196 {"evmhesumiaaw", VX (4, 1290), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9197 {"evmhosumiaaw", VX (4, 1294), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9198 {"evmbeusiaah", VX (4, 1296), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9199 {"evmbessiaah", VX (4, 1297), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9200 {"evmbesusiaah", VX (4, 1298), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9201 {"evmbousiaah", VX (4, 1300), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9202 {"evmbossiaah", VX (4, 1301), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9203 {"evmbosusiaah", VX (4, 1302), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9204 {"evmbeumiaah", VX (4, 1304), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9205 {"evmbesmiaah", VX (4, 1305), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9206 {"evmbesumiaah", VX (4, 1306), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9207 {"evmboumiaah", VX (4, 1308), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9208 {"evmbosmiaah", VX (4, 1309), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9209 {"evmbosumiaah", VX (4, 1310), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9210 {"evmwlusiaaw3", VX (4, 1346), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9211 {"evmwlssiaaw3", VX (4, 1347), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9212 {"evmwhssfraaw3", VX (4, 1348), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9213 {"evmwhssfaaw3", VX (4, 1349), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9214 {"evmwhssfraaw", VX (4, 1350), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9215 {"evmwhssfaaw", VX (4, 1351), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9216 {"evmwlumiaaw3", VX (4, 1354), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9217 {"evmwlsmiaaw3", VX (4, 1355), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9218 {"evmwusiaa", VX (4, 1360), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9219 {"evmwssiaa", VX (4, 1361), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9220 {"evmwehgsmfraa", VX (4, 1366), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9221 {"evmwehgsmfaa", VX (4, 1367), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9222 {"evmwohgsmfraa", VX (4, 1374), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9223 {"evmwohgsmfaa", VX (4, 1375), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9224 {"evmhesusianw", VX (4, 1410), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9225 {"evmhosusianw", VX (4, 1414), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9226 {"evmhesumianw", VX (4, 1418), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9227 {"evmhosumianw", VX (4, 1422), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9228 {"evmbeusianh", VX (4, 1424), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9229 {"evmbessianh", VX (4, 1425), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9230 {"evmbesusianh", VX (4, 1426), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9231 {"evmbousianh", VX (4, 1428), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9232 {"evmbossianh", VX (4, 1429), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9233 {"evmbosusianh", VX (4, 1430), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9234 {"evmbeumianh", VX (4, 1432), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9235 {"evmbesmianh", VX (4, 1433), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9236 {"evmbesumianh", VX (4, 1434), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9237 {"evmboumianh", VX (4, 1436), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9238 {"evmbosmianh", VX (4, 1437), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9239 {"evmbosumianh", VX (4, 1438), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9240 {"evmwlusianw3", VX (4, 1474), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9241 {"evmwlssianw3", VX (4, 1475), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9242 {"evmwhssfranw3", VX (4, 1476), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9243 {"evmwhssfanw3", VX (4, 1477), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9244 {"evmwhssfranw", VX (4, 1478), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9245 {"evmwhssfanw", VX (4, 1479), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9246 {"evmwlumianw3", VX (4, 1482), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9247 {"evmwlsmianw3", VX (4, 1483), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9248 {"evmwusian", VX (4, 1488), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9249 {"evmwssian", VX (4, 1489), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9250 {"evmwehgsmfran", VX (4, 1494), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9251 {"evmwehgsmfan", VX (4, 1495), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9252 {"evmwohgsmfran", VX (4, 1502), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9253 {"evmwohgsmfan", VX (4, 1503), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9254 {"evseteqb", VX (4, 1536), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9255 {"evseteqb.", VX (4, 1537), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9256 {"evseteqh", VX (4, 1538), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9257 {"evseteqh.", VX (4, 1539), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9258 {"evseteqw", VX (4, 1540), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9259 {"evseteqw.", VX (4, 1541), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9260 {"evsetgthu", VX (4, 1544), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9261 {"evsetgthu.", VX (4, 1545), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9262 {"evsetgths", VX (4, 1546), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9263 {"evsetgths.", VX (4, 1547), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9264 {"evsetgtwu", VX (4, 1548), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9265 {"evsetgtwu.", VX (4, 1549), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9266 {"evsetgtws", VX (4, 1550), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9267 {"evsetgtws.", VX (4, 1551), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9268 {"evsetgtbu", VX (4, 1552), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9269 {"evsetgtbu.", VX (4, 1553), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9270 {"evsetgtbs", VX (4, 1554), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9271 {"evsetgtbs.", VX (4, 1555), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9272 {"evsetltbu", VX (4, 1556), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9273 {"evsetltbu.", VX (4, 1557), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9274 {"evsetltbs", VX (4, 1558), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9275 {"evsetltbs.", VX (4, 1559), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9276 {"evsetlthu", VX (4, 1560), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9277 {"evsetlthu.", VX (4, 1561), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9278 {"evsetlths", VX (4, 1562), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9279 {"evsetlths.", VX (4, 1563), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9280 {"evsetltwu", VX (4, 1564), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9281 {"evsetltwu.", VX (4, 1565), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9282 {"evsetltws", VX (4, 1566), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9283 {"evsetltws.", VX (4, 1567), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9284 {"evsaduw", VX (4, 1568), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9285 {"evsadsw", VX (4, 1569), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9286 {"evsad4ub", VX (4, 1570), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9287 {"evsad4sb", VX (4, 1571), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9288 {"evsad2uh", VX (4, 1572), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9289 {"evsad2sh", VX (4, 1573), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9290 {"evsaduwa", VX (4, 1576), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9291 {"evsadswa", VX (4, 1577), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9292 {"evsad4uba", VX (4, 1578), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9293 {"evsad4sba", VX (4, 1579), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9294 {"evsad2uha", VX (4, 1580), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9295 {"evsad2sha", VX (4, 1581), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9296 {"evabsdifuw", VX (4, 1584), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9297 {"evabsdifsw", VX (4, 1585), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9298 {"evabsdifub", VX (4, 1586), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9299 {"evabsdifsb", VX (4, 1587), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9300 {"evabsdifuh", VX (4, 1588), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9301 {"evabsdifsh", VX (4, 1589), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9302 {"evsaduwaa", VX (4, 1592), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9303 {"evsadswaa", VX (4, 1593), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9304 {"evsad4ubaaw", VX (4, 1594), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9305 {"evsad4sbaaw", VX (4, 1595), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9306 {"evsad2uhaaw", VX (4, 1596), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9307 {"evsad2shaaw", VX (4, 1597), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9308 {"evpkshubs", VX (4, 1600), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9309 {"evpkshsbs", VX (4, 1601), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9310 {"evpkswuhs", VX (4, 1602), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9311 {"evpkswshs", VX (4, 1603), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9312 {"evpkuhubs", VX (4, 1604), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9313 {"evpkuwuhs", VX (4, 1605), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9314 {"evpkswshilvs", VX (4, 1606), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9315 {"evpkswgshefrs", VX (4, 1607), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9316 {"evpkswshfrs", VX (4, 1608), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9317 {"evpkswshilvfrs", VX (4, 1609), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9318 {"evpksdswfrs", VX (4, 1610), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9319 {"evpksdshefrs", VX (4, 1611), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9320 {"evpkuduws", VX (4, 1612), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9321 {"evpksdsws", VX (4, 1613), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9322 {"evpkswgswfrs", VX (4, 1614), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9323 {"evilveh", VX (4, 1616), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9324 {"evilveoh", VX (4, 1617), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9325 {"evilvhih", VX (4, 1618), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9326 {"evilvhiloh", VX (4, 1619), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9327 {"evilvloh", VX (4, 1620), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9328 {"evilvlohih", VX (4, 1621), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9329 {"evilvoeh", VX (4, 1622), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9330 {"evilvoh", VX (4, 1623), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9331 {"evdlveb", VX (4, 1624), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9332 {"evdlveh", VX (4, 1625), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9333 {"evdlveob", VX (4, 1626), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9334 {"evdlveoh", VX (4, 1627), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9335 {"evdlvob", VX (4, 1628), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9336 {"evdlvoh", VX (4, 1629), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9337 {"evdlvoeb", VX (4, 1630), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9338 {"evdlvoeh", VX (4, 1631), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9339 {"evmaxbu", VX (4, 1632), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9340 {"evmaxbs", VX (4, 1633), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9341 {"evmaxhu", VX (4, 1634), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9342 {"evmaxhs", VX (4, 1635), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9343 {"evmaxwu", VX (4, 1636), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9344 {"evmaxws", VX (4, 1637), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9345 {"evmaxdu", VX (4, 1638), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9346 {"evmaxds", VX (4, 1639), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9347 {"evminbu", VX (4, 1640), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9348 {"evminbs", VX (4, 1641), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9349 {"evminhu", VX (4, 1642), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9350 {"evminhs", VX (4, 1643), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9351 {"evminwu", VX (4, 1644), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9352 {"evminws", VX (4, 1645), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9353 {"evmindu", VX (4, 1646), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9354 {"evminds", VX (4, 1647), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9355 {"evavgwu", VX (4, 1648), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9356 {"evavgws", VX (4, 1649), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9357 {"evavgbu", VX (4, 1650), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9358 {"evavgbs", VX (4, 1651), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9359 {"evavghu", VX (4, 1652), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9360 {"evavghs", VX (4, 1653), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9361 {"evavgdu", VX (4, 1654), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9362 {"evavgds", VX (4, 1655), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9363 {"evavgwur", VX (4, 1656), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9364 {"evavgwsr", VX (4, 1657), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9365 {"evavgbur", VX (4, 1658), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9366 {"evavgbsr", VX (4, 1659), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9367 {"evavghur", VX (4, 1660), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9368 {"evavghsr", VX (4, 1661), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9369 {"evavgdur", VX (4, 1662), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9370 {"evavgdsr", VX (4, 1663), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
9371 };
9372
9373 const unsigned int spe2_num_opcodes =
9374 sizeof (spe2_opcodes) / sizeof (spe2_opcodes[0]);
This page took 0.413876 seconds and 5 git commands to generate.