opcodes/ppc-opc.c

   1 /* ppc-opc.c -- PowerPC opcode list
   2    Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
   3    2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
   4    Free Software Foundation, Inc.
   5    Written by Ian Lance Taylor, Cygnus Support
   6
   7    This file is part of the GNU opcodes library.
   8
   9    This library is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    It is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this file; see the file COPYING.  If not, write to the
  21    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  22    MA 02110-1301, USA.  */
  23
  24 #include "sysdep.h"
  25 #include <stdio.h>
  26 #include "opcode/ppc.h"
  27 #include "opintl.h"
  28
  29 /* This file holds the PowerPC opcode table.  The opcode table
  30    includes almost all of the extended instruction mnemonics.  This
  31    permits the disassembler to use them, and simplifies the assembler
  32    logic, at the cost of increasing the table size.  The table is
  33    strictly constant data, so the compiler should be able to put it in
  34    the .text section.
  35
  36    This file also holds the operand table.  All knowledge about
  37    inserting operands into instructions and vice-versa is kept in this
  38    file.  */
  39 \f
  40 /* Local insertion and extraction functions.  */
  41
  42 static unsigned long insert_arx (unsigned long, long, ppc_cpu_t, const char **);
  43 static long extract_arx (unsigned long, ppc_cpu_t, int *);
  44 static unsigned long insert_ary (unsigned long, long, ppc_cpu_t, const char **);
  45 static long extract_ary (unsigned long, ppc_cpu_t, int *);
  46 static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **);
  47 static long extract_bat (unsigned long, ppc_cpu_t, int *);
  48 static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **);
  49 static long extract_bba (unsigned long, ppc_cpu_t, int *);
  50 static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **);
  51 static long extract_bdm (unsigned long, ppc_cpu_t, int *);
  52 static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **);
  53 static long extract_bdp (unsigned long, ppc_cpu_t, int *);
  54 static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **);
  55 static long extract_bo (unsigned long, ppc_cpu_t, int *);
  56 static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **);
  57 static long extract_boe (unsigned long, ppc_cpu_t, int *);
  58 static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
  59 static long extract_fxm (unsigned long, ppc_cpu_t, int *);
  60 static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **);
  61 static long extract_li20 (unsigned long, ppc_cpu_t, int *);
  62 static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **);
  63 static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **);
  64 static long extract_mbe (unsigned long, ppc_cpu_t, int *);
  65 static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **);
  66 static long extract_mb6 (unsigned long, ppc_cpu_t, int *);
  67 static long extract_nb (unsigned long, ppc_cpu_t, int *);
  68 static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t, const char **);
  69 static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **);
  70 static long extract_nsi (unsigned long, ppc_cpu_t, int *);
  71 static unsigned long insert_oimm (unsigned long, long, ppc_cpu_t, const char **);
  72 static long extract_oimm (unsigned long, ppc_cpu_t, int *);
  73 static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **);
  74 static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **);
  75 static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **);
  76 static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **);
  77 static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **);
  78 static long extract_rbs (unsigned long, ppc_cpu_t, int *);
  79 static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t, const char **);
  80 static unsigned long insert_rx (unsigned long, long, ppc_cpu_t, const char **);
  81 static long extract_rx (unsigned long, ppc_cpu_t, int *);
  82 static unsigned long insert_ry (unsigned long, long, ppc_cpu_t, const char **);
  83 static long extract_ry (unsigned long, ppc_cpu_t, int *);
  84 static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **);
  85 static long extract_sh6 (unsigned long, ppc_cpu_t, int *);
  86 static unsigned long insert_sci8 (unsigned long, long, ppc_cpu_t, const char **);
  87 static long extract_sci8 (unsigned long, ppc_cpu_t, int *);
  88 static unsigned long insert_sci8n (unsigned long, long, ppc_cpu_t, const char **);
  89 static long extract_sci8n (unsigned long, ppc_cpu_t, int *);
  90 static unsigned long insert_sd4h (unsigned long, long, ppc_cpu_t, const char **);
  91 static long extract_sd4h (unsigned long, ppc_cpu_t, int *);
  92 static unsigned long insert_sd4w (unsigned long, long, ppc_cpu_t, const char **);
  93 static long extract_sd4w (unsigned long, ppc_cpu_t, int *);
  94 static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **);
  95 static long extract_spr (unsigned long, ppc_cpu_t, int *);
  96 static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **);
  97 static long extract_sprg (unsigned long, ppc_cpu_t, int *);
  98 static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **);
  99 static long extract_tbr (unsigned long, ppc_cpu_t, int *);
 100 static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **);
 101 static long extract_xt6 (unsigned long, ppc_cpu_t, int *);
 102 static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **);
 103 static long extract_xa6 (unsigned long, ppc_cpu_t, int *);
 104 static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **);
 105 static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
 106 static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
 107 static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
 108 static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **);
 109 static long extract_xc6 (unsigned long, ppc_cpu_t, int *);
 110 static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **);
 111 static long extract_dm (unsigned long, ppc_cpu_t, int *);
 112 static unsigned long insert_vlesi (unsigned long, long, ppc_cpu_t, const char **);
 113 static long extract_vlesi (unsigned long, ppc_cpu_t, int *);
 114 static unsigned long insert_vlensi (unsigned long, long, ppc_cpu_t, const char **);
 115 static long extract_vlensi (unsigned long, ppc_cpu_t, int *);
 116 static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t, const char **);
 117 static long extract_vleui (unsigned long, ppc_cpu_t, int *);
 118 static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t, const char **);
 119 static long extract_vleil (unsigned long, ppc_cpu_t, int *);
 120 \f
 121 /* The operands table.
 122
 123    The fields are bitm, shift, insert, extract, flags.
 124
 125    We used to put parens around the various additions, like the one
 126    for BA just below.  However, that caused trouble with feeble
 127    compilers with a limit on depth of a parenthesized expression, like
 128    (reportedly) the compiler in Microsoft Developer Studio 5.  So we
 129    omit the parens, since the macros are never used in a context where
 130    the addition will be ambiguous.  */
 131
 132 const struct powerpc_operand powerpc_operands[] =
 133 {
 134   /* The zero index is used to indicate the end of the list of
 135      operands.  */
 136 #define UNUSED 0
 137   { 0, 0, NULL, NULL, 0 },
 138
 139   /* The BA field in an XL form instruction.  */
 140 #define BA UNUSED + 1
 141   /* The BI field in a B form or XL form instruction.  */
 142 #define BI BA
 143 #define BI_MASK (0x1f << 16)
 144   { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
 145
 146   /* The BA field in an XL form instruction when it must be the same
 147      as the BT field in the same instruction.  */
 148 #define BAT BA + 1
 149   { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
 150
 151   /* The BB field in an XL form instruction.  */
 152 #define BB BAT + 1
 153 #define BB_MASK (0x1f << 11)
 154   { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT },
 155
 156   /* The BB field in an XL form instruction when it must be the same
 157      as the BA field in the same instruction.  */
 158 #define BBA BB + 1
 159   { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
 160
 161   /* The BD field in a B form instruction.  The lower two bits are
 162      forced to zero.  */
 163 #define BD BBA + 1
 164   { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 165
 166   /* The BD field in a B form instruction when absolute addressing is
 167      used.  */
 168 #define BDA BD + 1
 169   { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 170
 171   /* The BD field in a B form instruction when the - modifier is used.
 172      This sets the y bit of the BO field appropriately.  */
 173 #define BDM BDA + 1
 174   { 0xfffc, 0, insert_bdm, extract_bdm,
 175       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 176
 177   /* The BD field in a B form instruction when the - modifier is used
 178      and absolute address is used.  */
 179 #define BDMA BDM + 1
 180   { 0xfffc, 0, insert_bdm, extract_bdm,
 181       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 182
 183   /* The BD field in a B form instruction when the + modifier is used.
 184      This sets the y bit of the BO field appropriately.  */
 185 #define BDP BDMA + 1
 186   { 0xfffc, 0, insert_bdp, extract_bdp,
 187       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 188
 189   /* The BD field in a B form instruction when the + modifier is used
 190      and absolute addressing is used.  */
 191 #define BDPA BDP + 1
 192   { 0xfffc, 0, insert_bdp, extract_bdp,
 193       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 194
 195   /* The BF field in an X or XL form instruction.  */
 196 #define BF BDPA + 1
 197   /* The CRFD field in an X form instruction.  */
 198 #define CRFD BF
 199   /* The CRD field in an XL form instruction.  */
 200 #define CRD BF
 201   { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG },
 202
 203   /* The BF field in an X or XL form instruction.  */
 204 #define BFF BF + 1
 205   { 0x7, 23, NULL, NULL, 0 },
 206
 207   /* An optional BF field.  This is used for comparison instructions,
 208      in which an omitted BF field is taken as zero.  */
 209 #define OBF BFF + 1
 210   { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
 211
 212   /* The BFA field in an X or XL form instruction.  */
 213 #define BFA OBF + 1
 214   { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG },
 215
 216   /* The BO field in a B form instruction.  Certain values are
 217      illegal.  */
 218 #define BO BFA + 1
 219 #define BO_MASK (0x1f << 21)
 220   { 0x1f, 21, insert_bo, extract_bo, 0 },
 221
 222   /* The BO field in a B form instruction when the + or - modifier is
 223      used.  This is like the BO field, but it must be even.  */
 224 #define BOE BO + 1
 225   { 0x1e, 21, insert_boe, extract_boe, 0 },
 226
 227 #define BH BOE + 1
 228   { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
 229
 230   /* The BT field in an X or XL form instruction.  */
 231 #define BT BH + 1
 232   { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT },
 233
 234   /* The BI16 field in a BD8 form instruction.  */
 235 #define BI16 BT + 1
 236   { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT },
 237
 238   /* The BI32 field in a BD15 form instruction.  */
 239 #define BI32 BI16 + 1
 240   { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
 241
 242   /* The BO32 field in a BD15 form instruction.  */
 243 #define BO32 BI32 + 1
 244   { 0x3, 20, NULL, NULL, 0 },
 245
 246   /* The B8 field in a BD8 form instruction.  */
 247 #define B8 BO32 + 1
 248   { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 249
 250   /* The B15 field in a BD15 form instruction.  The lowest bit is
 251      forced to zero.  */
 252 #define B15 B8 + 1
 253   { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 254
 255   /* The B24 field in a BD24 form instruction.  The lowest bit is
 256      forced to zero.  */
 257 #define B24 B15 + 1
 258   { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 259
 260   /* The condition register number portion of the BI field in a B form
 261      or XL form instruction.  This is used for the extended
 262      conditional branch mnemonics, which set the lower two bits of the
 263      BI field.  This field is optional.  */
 264 #define CR B24 + 1
 265   { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
 266
 267   /* The CRB field in an X form instruction.  */
 268 #define CRB CR + 1
 269   /* The MB field in an M form instruction.  */
 270 #define MB CRB
 271 #define MB_MASK (0x1f << 6)
 272   { 0x1f, 6, NULL, NULL, 0 },
 273
 274   /* The CRD32 field in an XL form instruction.  */
 275 #define CRD32 CRB + 1
 276   { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG },
 277
 278   /* The CRFS field in an X form instruction.  */
 279 #define CRFS CRD32 + 1
 280   { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG },
 281
 282 #define CRS CRFS + 1
 283   { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
 284
 285   /* The CT field in an X form instruction.  */
 286 #define CT CRS + 1
 287   /* The MO field in an mbar instruction.  */
 288 #define MO CT
 289   { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 290
 291   /* The D field in a D form instruction.  This is a displacement off
 292      a register, and implies that the next operand is a register in
 293      parentheses.  */
 294 #define D CT + 1
 295   { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 296
 297   /* The D8 field in a D form instruction.  This is a displacement off
 298      a register, and implies that the next operand is a register in
 299      parentheses.  */
 300 #define D8 D + 1
 301   { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 302
 303   /* The DQ field in a DQ form instruction.  This is like D, but the
 304      lower four bits are forced to zero. */
 305 #define DQ D8 + 1
 306   { 0xfff0, 0, NULL, NULL,
 307     PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
 308
 309   /* The DS field in a DS form instruction.  This is like D, but the
 310      lower two bits are forced to zero.  */
 311 #define DS DQ + 1
 312   { 0xfffc, 0, NULL, NULL,
 313     PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
 314
 315   /* The DUIS field in a XFX form instruction, 10 bits unsigned imediate */
 316 #define DUIS DS + 1
 317   { 0x3ff, 11, NULL, NULL, 0 },
 318
 319   /* The E field in a wrteei instruction.  */
 320   /* And the W bit in the pair singles instructions.  */
 321 #define E DUIS + 1
 322 #define PSW E
 323   { 0x1, 15, NULL, NULL, 0 },
 324
 325   /* The FL1 field in a POWER SC form instruction.  */
 326 #define FL1 E + 1
 327   /* The U field in an X form instruction.  */
 328 #define U FL1
 329   { 0xf, 12, NULL, NULL, 0 },
 330
 331   /* The FL2 field in a POWER SC form instruction.  */
 332 #define FL2 FL1 + 1
 333   { 0x7, 2, NULL, NULL, 0 },
 334
 335   /* The FLM field in an XFL form instruction.  */
 336 #define FLM FL2 + 1
 337   { 0xff, 17, NULL, NULL, 0 },
 338
 339   /* The FRA field in an X or A form instruction.  */
 340 #define FRA FLM + 1
 341 #define FRA_MASK (0x1f << 16)
 342   { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
 343
 344   /* The FRAp field of DFP instructions.  */
 345 #define FRAp FRA + 1
 346   { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR },
 347
 348   /* The FRB field in an X or A form instruction.  */
 349 #define FRB FRAp + 1
 350 #define FRB_MASK (0x1f << 11)
 351   { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
 352
 353   /* The FRBp field of DFP instructions.  */
 354 #define FRBp FRB + 1
 355   { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR },
 356
 357   /* The FRC field in an A form instruction.  */
 358 #define FRC FRBp + 1
 359 #define FRC_MASK (0x1f << 6)
 360   { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
 361
 362   /* The FRS field in an X form instruction or the FRT field in a D, X
 363      or A form instruction.  */
 364 #define FRS FRC + 1
 365 #define FRT FRS
 366   { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
 367
 368   /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
 369      instructions.  */
 370 #define FRSp FRS + 1
 371 #define FRTp FRSp
 372   { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR },
 373
 374   /* The FXM field in an XFX instruction.  */
 375 #define FXM FRSp + 1
 376   { 0xff, 12, insert_fxm, extract_fxm, 0 },
 377
 378   /* Power4 version for mfcr.  */
 379 #define FXM4 FXM + 1
 380   { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
 381
 382   /* The IMM20 field in an LI instruction.  */
 383 #define IMM20 FXM4 + 1
 384   { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED},
 385
 386   /* The L field in a D or X form instruction.  */
 387 #define L IMM20 + 1
 388   { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 389
 390   /* The LEV field in a POWER SVC form instruction.  */
 391 #define SVC_LEV L + 1
 392   { 0x7f, 5, NULL, NULL, 0 },
 393
 394   /* The LEV field in an SC form instruction.  */
 395 #define LEV SVC_LEV + 1
 396   { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
 397
 398   /* The LI field in an I form instruction.  The lower two bits are
 399      forced to zero.  */
 400 #define LI LEV + 1
 401   { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 402
 403   /* The LI field in an I form instruction when used as an absolute
 404      address.  */
 405 #define LIA LI + 1
 406   { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 407
 408   /* The LS or WC field in an X (sync or wait) form instruction.  */
 409 #define LS LIA + 1
 410 #define WC LS
 411   { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 412
 413   /* The ME field in an M form instruction.  */
 414 #define ME LS + 1
 415 #define ME_MASK (0x1f << 1)
 416   { 0x1f, 1, NULL, NULL, 0 },
 417
 418   /* The MB and ME fields in an M form instruction expressed a single
 419      operand which is a bitmask indicating which bits to select.  This
 420      is a two operand form using PPC_OPERAND_NEXT.  See the
 421      description in opcode/ppc.h for what this means.  */
 422 #define MBE ME + 1
 423   { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
 424   { -1, 0, insert_mbe, extract_mbe, 0 },
 425
 426   /* The MB or ME field in an MD or MDS form instruction.  The high
 427      bit is wrapped to the low end.  */
 428 #define MB6 MBE + 2
 429 #define ME6 MB6
 430 #define MB6_MASK (0x3f << 5)
 431   { 0x3f, 5, insert_mb6, extract_mb6, 0 },
 432
 433   /* The NB field in an X form instruction.  The value 32 is stored as
 434      0.  */
 435 #define NB MB6 + 1
 436   { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
 437
 438   /* The NBI field in an lswi instruction, which has special value
 439      restrictions.  The value 32 is stored as 0.  */
 440 #define NBI NB + 1
 441   { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 },
 442
 443   /* The NSI field in a D form instruction.  This is the same as the
 444      SI field, only negated.  */
 445 #define NSI NBI + 1
 446   { 0xffff, 0, insert_nsi, extract_nsi,
 447       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 448
 449   /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction.  */
 450 #define RA NSI + 1
 451 #define RA_MASK (0x1f << 16)
 452   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
 453
 454   /* As above, but 0 in the RA field means zero, not r0.  */
 455 #define RA0 RA + 1
 456   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
 457
 458   /* The RA field in the DQ form lq or an lswx instruction, which have special
 459      value restrictions.  */
 460 #define RAQ RA0 + 1
 461 #define RAX RAQ
 462   { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
 463
 464   /* The RA field in a D or X form instruction which is an updating
 465      load, which means that the RA field may not be zero and may not
 466      equal the RT field.  */
 467 #define RAL RAQ + 1
 468   { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
 469
 470   /* The RA field in an lmw instruction, which has special value
 471      restrictions.  */
 472 #define RAM RAL + 1
 473   { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
 474
 475   /* The RA field in a D or X form instruction which is an updating
 476      store or an updating floating point load, which means that the RA
 477      field may not be zero.  */
 478 #define RAS RAM + 1
 479   { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
 480
 481   /* The RA field of the tlbwe, dccci and iccci instructions,
 482      which are optional.  */
 483 #define RAOPT RAS + 1
 484   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 485
 486   /* The RB field in an X, XO, M, or MDS form instruction.  */
 487 #define RB RAOPT + 1
 488 #define RB_MASK (0x1f << 11)
 489   { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
 490
 491   /* The RB field in an X form instruction when it must be the same as
 492      the RS field in the instruction.  This is used for extended
 493      mnemonics like mr.  */
 494 #define RBS RB + 1
 495   { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
 496
 497   /* The RB field in an lswx instruction, which has special value
 498      restrictions.  */
 499 #define RBX RBS + 1
 500   { 0x1f, 11, insert_rbx, NULL, PPC_OPERAND_GPR },
 501
 502   /* The RB field of the dccci and iccci instructions, which are optional.  */
 503 #define RBOPT RBX + 1
 504   { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 505
 506   /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
 507      instruction or the RT field in a D, DS, X, XFX or XO form
 508      instruction.  */
 509 #define RS RBOPT + 1
 510 #define RT RS
 511 #define RT_MASK (0x1f << 21)
 512 #define RD RS
 513   { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
 514
 515   /* The RS and RT fields of the DS form stq instruction, which have
 516      special value restrictions.  */
 517 #define RSQ RS + 1
 518 #define RTQ RSQ
 519   { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
 520
 521   /* The RS field of the tlbwe instruction, which is optional.  */
 522 #define RSO RSQ + 1
 523 #define RTO RSO
 524   { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 525
 526   /* The RX field of the SE_RR form instruction.  */
 527 #define RX RSO + 1
 528   { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR },
 529
 530   /* The ARX field of the SE_RR form instruction.  */
 531 #define ARX RX + 1
 532   { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR },
 533
 534   /* The RY field of the SE_RR form instruction.  */
 535 #define RY ARX + 1
 536 #define RZ RY
 537   { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR },
 538
 539   /* The ARY field of the SE_RR form instruction.  */
 540 #define ARY RY + 1
 541   { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR },
 542
 543   /* The SCLSCI8 field in a D form instruction.  */
 544 #define SCLSCI8 ARY + 1
 545   { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 },
 546
 547   /* The SCLSCI8N field in a D form instruction.  This is the same as the
 548      SCLSCI8 field, only negated.  */
 549 #define SCLSCI8N SCLSCI8 + 1
 550   { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n,
 551       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 552
 553   /* The SD field of the SD4 form instruction.  */
 554 #define SE_SD SCLSCI8N + 1
 555   { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS },
 556
 557   /* The SD field of the SD4 form instruction, for halfword.  */
 558 #define SE_SDH SE_SD + 1
 559   { 0x1e, PPC_OPSHIFT_INV, insert_sd4h, extract_sd4h, PPC_OPERAND_PARENS },
 560
 561   /* The SD field of the SD4 form instruction, for word.  */
 562 #define SE_SDW SE_SDH + 1
 563   { 0x3c, PPC_OPSHIFT_INV, insert_sd4w, extract_sd4w, PPC_OPERAND_PARENS },
 564
 565   /* The SH field in an X or M form instruction.  */
 566 #define SH SE_SDW + 1
 567 #define SH_MASK (0x1f << 11)
 568   /* The other UIMM field in a EVX form instruction.  */
 569 #define EVUIMM SH
 570   { 0x1f, 11, NULL, NULL, 0 },
 571
 572   /* The SH field in an MD form instruction.  This is split.  */
 573 #define SH6 SH + 1
 574 #define SH6_MASK ((0x1f << 11) | (1 << 1))
 575   { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 },
 576
 577   /* The SH field of the tlbwe instruction, which is optional.  */
 578 #define SHO SH6 + 1
 579   { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
 580
 581   /* The SI field in a D form instruction.  */
 582 #define SI SHO + 1
 583   { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
 584
 585   /* The SI field in a D form instruction when we accept a wide range
 586      of positive values.  */
 587 #define SISIGNOPT SI + 1
 588   { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 589
 590   /* The SI8 field in a D form instruction.  */
 591 #define SI8 SISIGNOPT + 1
 592   { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
 593
 594   /* The SPR field in an XFX form instruction.  This is flipped--the
 595      lower 5 bits are stored in the upper 5 and vice- versa.  */
 596 #define SPR SI8 + 1
 597 #define PMR SPR
 598 #define TMR SPR
 599 #define SPR_MASK (0x3ff << 11)
 600   { 0x3ff, 11, insert_spr, extract_spr, 0 },
 601
 602   /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
 603 #define SPRBAT SPR + 1
 604 #define SPRBAT_MASK (0x3 << 17)
 605   { 0x3, 17, NULL, NULL, 0 },
 606
 607   /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
 608 #define SPRG SPRBAT + 1
 609   { 0x1f, 16, insert_sprg, extract_sprg, 0 },
 610
 611   /* The SR field in an X form instruction.  */
 612 #define SR SPRG + 1
 613   { 0xf, 16, NULL, NULL, 0 },
 614
 615   /* The STRM field in an X AltiVec form instruction.  */
 616 #define STRM SR + 1
 617   /* The T field in a tlbilx form instruction.  */
 618 #define T STRM
 619   { 0x3, 21, NULL, NULL, 0 },
 620
 621   /* The ESYNC field in an X (sync) form instruction.  */
 622 #define ESYNC STRM + 1
 623   { 0xf, 16, insert_ls, NULL, PPC_OPERAND_OPTIONAL },
 624
 625   /* The SV field in a POWER SC form instruction.  */
 626 #define SV ESYNC + 1
 627   { 0x3fff, 2, NULL, NULL, 0 },
 628
 629   /* The TBR field in an XFX form instruction.  This is like the SPR
 630      field, but it is optional.  */
 631 #define TBR SV + 1
 632   { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
 633
 634   /* The TO field in a D or X form instruction.  */
 635 #define TO TBR + 1
 636 #define DUI TO
 637 #define TO_MASK (0x1f << 21)
 638   { 0x1f, 21, NULL, NULL, 0 },
 639
 640   /* The UI field in a D form instruction.  */
 641 #define UI TO + 1
 642   { 0xffff, 0, NULL, NULL, 0 },
 643
 644   /* The IMM field in an SE_IM5 instruction.  */
 645 #define UI5 UI + 1
 646   { 0x1f, 4, NULL, NULL, 0 },
 647
 648   /* The OIMM field in an SE_OIM5 instruction.  */
 649 #define OIMM5 UI5 + 1
 650   { 0x1f, PPC_OPSHIFT_INV, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 },
 651
 652   /* The UI7 field in an SE_LI instruction.  */
 653 #define UI7 OIMM5 + 1
 654   { 0x7f, 4, NULL, NULL, 0 },
 655
 656   /* The VA field in a VA, VX or VXR form instruction.  */
 657 #define VA UI7 + 1
 658   { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
 659
 660   /* The VB field in a VA, VX or VXR form instruction.  */
 661 #define VB VA + 1
 662   { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
 663
 664   /* The VC field in a VA form instruction.  */
 665 #define VC VB + 1
 666   { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
 667
 668   /* The VD or VS field in a VA, VX, VXR or X form instruction.  */
 669 #define VD VC + 1
 670 #define VS VD
 671   { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
 672
 673   /* The SIMM field in a VX form instruction, and TE in Z form.  */
 674 #define SIMM VD + 1
 675 #define TE SIMM
 676   { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
 677
 678   /* The UIMM field in a VX form instruction.  */
 679 #define UIMM SIMM + 1
 680 #define DCTL UIMM
 681   { 0x1f, 16, NULL, NULL, 0 },
 682
 683   /* The SHB field in a VA form instruction.  */
 684 #define SHB UIMM + 1
 685   { 0xf, 6, NULL, NULL, 0 },
 686
 687   /* The other UIMM field in a half word EVX form instruction.  */
 688 #define EVUIMM_2 SHB + 1
 689   { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
 690
 691   /* The other UIMM field in a word EVX form instruction.  */
 692 #define EVUIMM_4 EVUIMM_2 + 1
 693   { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
 694
 695   /* The other UIMM field in a double EVX form instruction.  */
 696 #define EVUIMM_8 EVUIMM_4 + 1
 697   { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
 698
 699   /* The WS field.  */
 700 #define WS EVUIMM_8 + 1
 701   { 0x7, 11, NULL, NULL, 0 },
 702
 703   /* PowerPC paired singles extensions.  */
 704   /* W bit in the pair singles instructions for x type instructions.  */
 705 #define PSWM WS + 1
 706   /* The BO16 field in a BD8 form instruction.  */
 707 #define BO16 PSWM
 708   {  0x1, 10, 0, 0, 0 },
 709
 710   /* IDX bits for quantization in the pair singles instructions.  */
 711 #define PSQ PSWM + 1
 712   {  0x7, 12, 0, 0, 0 },
 713
 714   /* IDX bits for quantization in the pair singles x-type instructions.  */
 715 #define PSQM PSQ + 1
 716   {  0x7, 7, 0, 0, 0 },
 717
 718   /* Smaller D field for quantization in the pair singles instructions.  */
 719 #define PSD PSQM + 1
 720   {  0xfff, 0, 0, 0,  PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 721
 722 #define A_L PSD + 1
 723 #define W A_L
 724 #define MTMSRD_L W
 725   { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
 726
 727 #define RMC MTMSRD_L + 1
 728   { 0x3, 9, NULL, NULL, 0 },
 729
 730 #define R RMC + 1
 731   { 0x1, 16, NULL, NULL, 0 },
 732
 733 #define SP R + 1
 734   { 0x3, 19, NULL, NULL, 0 },
 735
 736 #define S SP + 1
 737   { 0x1, 20, NULL, NULL, 0 },
 738
 739   /* SH field starting at bit position 16.  */
 740 #define SH16 S + 1
 741   /* The DCM and DGM fields in a Z form instruction.  */
 742 #define DCM SH16
 743 #define DGM DCM
 744   { 0x3f, 10, NULL, NULL, 0 },
 745
 746   /* The EH field in larx instruction.  */
 747 #define EH SH16 + 1
 748   { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
 749
 750   /* The L field in an mtfsf or XFL form instruction.  */
 751 #define XFL_L EH + 1
 752   { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
 753
 754   /* Xilinx APU related masks and macros */
 755 #define FCRT XFL_L + 1
 756 #define FCRT_MASK (0x1f << 21)
 757   { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
 758
 759   /* Xilinx FSL related masks and macros */
 760 #define FSL FCRT + 1
 761 #define FSL_MASK (0x1f << 11)
 762   { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
 763
 764   /* Xilinx UDI related masks and macros */
 765 #define URT FSL + 1
 766   { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
 767
 768 #define URA URT + 1
 769   { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
 770
 771 #define URB URA + 1
 772   { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
 773
 774 #define URC URB + 1
 775   { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
 776
 777   /* The VLESIMM field in a D form instruction.  */
 778 #define VLESIMM URC + 1
 779   { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi,
 780       PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 781
 782   /* The VLENSIMM field in a D form instruction.  */
 783 #define VLENSIMM VLESIMM + 1
 784   { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi,
 785       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 786
 787   /* The VLEUIMM field in a D form instruction.  */
 788 #define VLEUIMM VLENSIMM + 1
 789   { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 },
 790
 791   /* The VLEUIMML field in a D form instruction.  */
 792 #define VLEUIMML VLEUIMM + 1
 793   { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 },
 794
 795   /* The XT and XS fields in an XX1 or XX3 form instruction.  This is split.  */
 796 #define XS6 VLEUIMML + 1
 797 #define XT6 XS6
 798   { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
 799
 800   /* The XA field in an XX3 form instruction.  This is split.  */
 801 #define XA6 XT6 + 1
 802   { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
 803
 804   /* The XB field in an XX2 or XX3 form instruction.  This is split.  */
 805 #define XB6 XA6 + 1
 806   { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
 807
 808   /* The XB field in an XX3 form instruction when it must be the same as
 809      the XA field in the instruction.  This is used in extended mnemonics
 810      like xvmovdp.  This is split.  */
 811 #define XB6S XB6 + 1
 812   { 0x3f, PPC_OPSHIFT_INV, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
 813
 814   /* The XC field in an XX4 form instruction.  This is split.  */
 815 #define XC6 XB6S + 1
 816   { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
 817
 818   /* The DM or SHW field in an XX3 form instruction.  */
 819 #define DM XC6 + 1
 820 #define SHW DM
 821   { 0x3, 8, NULL, NULL, 0 },
 822
 823   /* The DM field in an extended mnemonic XX3 form instruction.  */
 824 #define DMEX DM + 1
 825   { 0x3, 8, insert_dm, extract_dm, 0 },
 826
 827   /* The UIM field in an XX2 form instruction.  */
 828 #define UIM DMEX + 1
 829   { 0x3, 16, NULL, NULL, 0 },
 830
 831 #define ERAT_T UIM + 1
 832   { 0x7, 21, NULL, NULL, 0 },
 833 };
 834
 835 const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
 836                                            / sizeof (powerpc_operands[0]));
 837
 838 /* The functions used to insert and extract complicated operands.  */
 839
 840 /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs.  */
 841
 842 static unsigned long
 843 insert_arx (unsigned long insn,
 844             long value,
 845             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 846             const char **errmsg ATTRIBUTE_UNUSED)
 847 {
 848   if (value >= 8 && value < 24)
 849     return insn | ((value - 8) & 0xf);
 850   else
 851     {
 852       *errmsg = _("invalid register");
 853       return 0;
 854     }
 855 }
 856
 857 static long
 858 extract_arx (unsigned long insn,
 859              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 860              int *invalid ATTRIBUTE_UNUSED)
 861 {
 862   return (insn & 0xf) + 8;
 863 }
 864
 865 static unsigned long
 866 insert_ary (unsigned long insn,
 867             long value,
 868             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 869             const char **errmsg ATTRIBUTE_UNUSED)
 870 {
 871   if (value >= 8 && value < 24)
 872     return insn | (((value - 8) & 0xf) << 4);
 873   else
 874     {
 875       *errmsg = _("invalid register");
 876       return 0;
 877     }
 878 }
 879
 880 static long
 881 extract_ary (unsigned long insn,
 882              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 883              int *invalid ATTRIBUTE_UNUSED)
 884 {
 885   return ((insn >> 4) & 0xf) + 8;
 886 }
 887
 888 static unsigned long
 889 insert_rx (unsigned long insn,
 890            long value,
 891            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 892            const char **errmsg)
 893 {
 894   if (value >= 0 && value < 8)
 895     return insn | value;
 896   else if (value >= 24 && value <= 31)
 897     return insn | (value - 16);
 898   else
 899     {
 900       *errmsg = _("invalid register");
 901       return 0;
 902     }
 903 }
 904
 905 static long
 906 extract_rx (unsigned long insn,
 907             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 908             int *invalid ATTRIBUTE_UNUSED)
 909 {
 910   int value = insn & 0xf;
 911   if (value >= 0 && value < 8)
 912     return value;
 913   else
 914     return value + 16;
 915 }
 916
 917 static unsigned long
 918 insert_ry (unsigned long insn,
 919            long value,
 920            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 921            const char **errmsg)
 922 {
 923   if (value >= 0 && value < 8)
 924     return insn | (value << 4);
 925   else if (value >= 24 && value <= 31)
 926     return insn | ((value - 16) << 4);
 927   else
 928     {
 929       *errmsg = _("invalid register");
 930       return 0;
 931     }
 932 }
 933
 934 static long
 935 extract_ry (unsigned long insn,
 936             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 937             int *invalid ATTRIBUTE_UNUSED)
 938 {
 939   int value = (insn >> 4) & 0xf;
 940   if (value >= 0 && value < 8)
 941     return value;
 942   else
 943     return value + 16;
 944 }
 945
 946 /* The BA field in an XL form instruction when it must be the same as
 947    the BT field in the same instruction.  This operand is marked FAKE.
 948    The insertion function just copies the BT field into the BA field,
 949    and the extraction function just checks that the fields are the
 950    same.  */
 951
 952 static unsigned long
 953 insert_bat (unsigned long insn,
 954             long value ATTRIBUTE_UNUSED,
 955             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 956             const char **errmsg ATTRIBUTE_UNUSED)
 957 {
 958   return insn | (((insn >> 21) & 0x1f) << 16);
 959 }
 960
 961 static long
 962 extract_bat (unsigned long insn,
 963              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 964              int *invalid)
 965 {
 966   if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
 967     *invalid = 1;
 968   return 0;
 969 }
 970
 971 /* The BB field in an XL form instruction when it must be the same as
 972    the BA field in the same instruction.  This operand is marked FAKE.
 973    The insertion function just copies the BA field into the BB field,
 974    and the extraction function just checks that the fields are the
 975    same.  */
 976
 977 static unsigned long
 978 insert_bba (unsigned long insn,
 979             long value ATTRIBUTE_UNUSED,
 980             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 981             const char **errmsg ATTRIBUTE_UNUSED)
 982 {
 983   return insn | (((insn >> 16) & 0x1f) << 11);
 984 }
 985
 986 static long
 987 extract_bba (unsigned long insn,
 988              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 989              int *invalid)
 990 {
 991   if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
 992     *invalid = 1;
 993   return 0;
 994 }
 995
 996 /* The BD field in a B form instruction when the - modifier is used.
 997    This modifier means that the branch is not expected to be taken.
 998    For chips built to versions of the architecture prior to version 2
 999    (ie. not Power4 compatible), we set the y bit of the BO field to 1
1000    if the offset is negative.  When extracting, we require that the y
1001    bit be 1 and that the offset be positive, since if the y bit is 0
1002    we just want to print the normal form of the instruction.
1003    Power4 compatible targets use two bits, "a", and "t", instead of
1004    the "y" bit.  "at" == 00 => no hint, "at" == 01 => unpredictable,
1005    "at" == 10 => not taken, "at" == 11 => taken.  The "t" bit is 00001
1006    in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
1007    for branch on CTR.  We only handle the taken/not-taken hint here.
1008    Note that we don't relax the conditions tested here when
1009    disassembling with -Many because insns using extract_bdm and
1010    extract_bdp always occur in pairs.  One or the other will always
1011    be valid.  */
1012
1013 #define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
1014
1015 static unsigned long
1016 insert_bdm (unsigned long insn,
1017             long value,
1018             ppc_cpu_t dialect,
1019             const char **errmsg ATTRIBUTE_UNUSED)
1020 {
1021   if ((dialect & ISA_V2) == 0)
1022     {
1023       if ((value & 0x8000) != 0)
1024         insn |= 1 << 21;
1025     }
1026   else
1027     {
1028       if ((insn & (0x14 << 21)) == (0x04 << 21))
1029         insn |= 0x02 << 21;
1030       else if ((insn & (0x14 << 21)) == (0x10 << 21))
1031         insn |= 0x08 << 21;
1032     }
1033   return insn | (value & 0xfffc);
1034 }
1035
1036 static long
1037 extract_bdm (unsigned long insn,
1038              ppc_cpu_t dialect,
1039              int *invalid)
1040 {
1041   if ((dialect & ISA_V2) == 0)
1042     {
1043       if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
1044         *invalid = 1;
1045     }
1046   else
1047     {
1048       if ((insn & (0x17 << 21)) != (0x06 << 21)
1049           && (insn & (0x1d << 21)) != (0x18 << 21))
1050         *invalid = 1;
1051     }
1052
1053   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1054 }
1055
1056 /* The BD field in a B form instruction when the + modifier is used.
1057    This is like BDM, above, except that the branch is expected to be
1058    taken.  */
1059
1060 static unsigned long
1061 insert_bdp (unsigned long insn,
1062             long value,
1063             ppc_cpu_t dialect,
1064             const char **errmsg ATTRIBUTE_UNUSED)
1065 {
1066   if ((dialect & ISA_V2) == 0)
1067     {
1068       if ((value & 0x8000) == 0)
1069         insn |= 1 << 21;
1070     }
1071   else
1072     {
1073       if ((insn & (0x14 << 21)) == (0x04 << 21))
1074         insn |= 0x03 << 21;
1075       else if ((insn & (0x14 << 21)) == (0x10 << 21))
1076         insn |= 0x09 << 21;
1077     }
1078   return insn | (value & 0xfffc);
1079 }
1080
1081 static long
1082 extract_bdp (unsigned long insn,
1083              ppc_cpu_t dialect,
1084              int *invalid)
1085 {
1086   if ((dialect & ISA_V2) == 0)
1087     {
1088       if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
1089         *invalid = 1;
1090     }
1091   else
1092     {
1093       if ((insn & (0x17 << 21)) != (0x07 << 21)
1094           && (insn & (0x1d << 21)) != (0x19 << 21))
1095         *invalid = 1;
1096     }
1097
1098   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1099 }
1100
1101 static inline int
1102 valid_bo_pre_v2 (long value)
1103 {
1104   /* Certain encodings have bits that are required to be zero.
1105      These are (z must be zero, y may be anything):
1106          0000y
1107          0001y
1108          001zy
1109          0100y
1110          0101y
1111          011zy
1112          1z00y
1113          1z01y
1114          1z1zz
1115   */
1116   if ((value & 0x14) == 0)
1117     return 1;
1118   else if ((value & 0x14) == 0x4)
1119     return (value & 0x2) == 0;
1120   else if ((value & 0x14) == 0x10)
1121     return (value & 0x8) == 0;
1122   else
1123     return value == 0x14;
1124 }
1125
1126 static inline int
1127 valid_bo_post_v2 (long value)
1128 {
1129   /* Certain encodings have bits that are required to be zero.
1130      These are (z must be zero, a & t may be anything):
1131          0000z
1132          0001z
1133          001at
1134          0100z
1135          0101z
1136          011at
1137          1a00t
1138          1a01t
1139          1z1zz
1140   */
1141   if ((value & 0x14) == 0)
1142     return (value & 0x1) == 0;
1143   else if ((value & 0x14) == 0x14)
1144     return value == 0x14;
1145   else
1146     return 1;
1147 }
1148
1149 /* Check for legal values of a BO field.  */
1150
1151 static int
1152 valid_bo (long value, ppc_cpu_t dialect, int extract)
1153 {
1154   int valid_y = valid_bo_pre_v2 (value);
1155   int valid_at = valid_bo_post_v2 (value);
1156
1157   /* When disassembling with -Many, accept either encoding on the
1158      second pass through opcodes.  */
1159   if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY)
1160     return valid_y || valid_at;
1161   if ((dialect & ISA_V2) == 0)
1162     return valid_y;
1163   else
1164     return valid_at;
1165 }
1166
1167 /* The BO field in a B form instruction.  Warn about attempts to set
1168    the field to an illegal value.  */
1169
1170 static unsigned long
1171 insert_bo (unsigned long insn,
1172            long value,
1173            ppc_cpu_t dialect,
1174            const char **errmsg)
1175 {
1176   if (!valid_bo (value, dialect, 0))
1177     *errmsg = _("invalid conditional option");
1178   else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1179     *errmsg = _("invalid counter access");
1180   return insn | ((value & 0x1f) << 21);
1181 }
1182
1183 static long
1184 extract_bo (unsigned long insn,
1185             ppc_cpu_t dialect,
1186             int *invalid)
1187 {
1188   long value;
1189
1190   value = (insn >> 21) & 0x1f;
1191   if (!valid_bo (value, dialect, 1))
1192     *invalid = 1;
1193   return value;
1194 }
1195
1196 /* The BO field in a B form instruction when the + or - modifier is
1197    used.  This is like the BO field, but it must be even.  When
1198    extracting it, we force it to be even.  */
1199
1200 static unsigned long
1201 insert_boe (unsigned long insn,
1202             long value,
1203             ppc_cpu_t dialect,
1204             const char **errmsg)
1205 {
1206   if (!valid_bo (value, dialect, 0))
1207     *errmsg = _("invalid conditional option");
1208   else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1209     *errmsg = _("invalid counter access");
1210   else if ((value & 1) != 0)
1211     *errmsg = _("attempt to set y bit when using + or - modifier");
1212
1213   return insn | ((value & 0x1f) << 21);
1214 }
1215
1216 static long
1217 extract_boe (unsigned long insn,
1218              ppc_cpu_t dialect,
1219              int *invalid)
1220 {
1221   long value;
1222
1223   value = (insn >> 21) & 0x1f;
1224   if (!valid_bo (value, dialect, 1))
1225     *invalid = 1;
1226   return value & 0x1e;
1227 }
1228
1229 /* FXM mask in mfcr and mtcrf instructions.  */
1230
1231 static unsigned long
1232 insert_fxm (unsigned long insn,
1233             long value,
1234             ppc_cpu_t dialect,
1235             const char **errmsg)
1236 {
1237   /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1238      one bit of the mask field is set.  */
1239   if ((insn & (1 << 20)) != 0)
1240     {
1241       if (value == 0 || (value & -value) != value)
1242         {
1243           *errmsg = _("invalid mask field");
1244           value = 0;
1245         }
1246     }
1247
1248   /* If the optional field on mfcr is missing that means we want to use
1249      the old form of the instruction that moves the whole cr.  In that
1250      case we'll have VALUE zero.  There doesn't seem to be a way to
1251      distinguish this from the case where someone writes mfcr %r3,0.  */
1252   else if (value == 0)
1253     ;
1254
1255   /* If only one bit of the FXM field is set, we can use the new form
1256      of the instruction, which is faster.  Unlike the Power4 branch hint
1257      encoding, this is not backward compatible.  Do not generate the
1258      new form unless -mpower4 has been given, or -many and the two
1259      operand form of mfcr was used.  */
1260   else if ((value & -value) == value
1261            && ((dialect & PPC_OPCODE_POWER4) != 0
1262                || ((dialect & PPC_OPCODE_ANY) != 0
1263                    && (insn & (0x3ff << 1)) == 19 << 1)))
1264     insn |= 1 << 20;
1265
1266   /* Any other value on mfcr is an error.  */
1267   else if ((insn & (0x3ff << 1)) == 19 << 1)
1268     {
1269       *errmsg = _("ignoring invalid mfcr mask");
1270       value = 0;
1271     }
1272
1273   return insn | ((value & 0xff) << 12);
1274 }
1275
1276 static long
1277 extract_fxm (unsigned long insn,
1278              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1279              int *invalid)
1280 {
1281   long mask = (insn >> 12) & 0xff;
1282
1283   /* Is this a Power4 insn?  */
1284   if ((insn & (1 << 20)) != 0)
1285     {
1286       /* Exactly one bit of MASK should be set.  */
1287       if (mask == 0 || (mask & -mask) != mask)
1288         *invalid = 1;
1289     }
1290
1291   /* Check that non-power4 form of mfcr has a zero MASK.  */
1292   else if ((insn & (0x3ff << 1)) == 19 << 1)
1293     {
1294       if (mask != 0)
1295         *invalid = 1;
1296     }
1297
1298   return mask;
1299 }
1300
1301 static unsigned long
1302 insert_li20 (unsigned long insn,
1303              long value,
1304              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1305              const char **errmsg ATTRIBUTE_UNUSED)
1306 {
1307   return insn | ((value & 0xf0000) >> 5) | ((value & 0x0f800) << 5) | (value & 0x7ff);
1308 }
1309
1310 static long
1311 extract_li20 (unsigned long insn,
1312               ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1313               int *invalid ATTRIBUTE_UNUSED)
1314 {
1315   long ext = ((insn & 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000;
1316
1317   return ext
1318          | (((insn >> 11) & 0xf) << 16)
1319          | (((insn >> 17) & 0xf) << 12)
1320          | (((insn >> 16) & 0x1) << 11)
1321          | (insn & 0x7ff);
1322 }
1323
1324 /* The LS field in a sync instruction that accepts 2 operands
1325    Values 2 and 3 are reserved,
1326      must be treated as 0 for future compatibility
1327    Values 0 and 1 can be accepted, if field ESYNC is zero
1328    Otherwise L = complement of ESYNC-bit2 (1<<18) */
1329
1330 static unsigned long
1331 insert_ls (unsigned long insn,
1332            long value,
1333            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1334            const char **errmsg ATTRIBUTE_UNUSED)
1335 {
1336   unsigned long ls;
1337
1338   ls = (insn >> 21) & 0x03;
1339   if (value == 0)
1340     {
1341       if (ls > 1)
1342         return insn & ~(0x3 << 21);
1343       return insn;
1344     }
1345   if ((value & 0x2) != 0)
1346     return (insn & ~(0x3 << 21)) | ((value & 0xf) << 16);
1347   return (insn & ~(0x3 << 21)) | (0x1 << 21) | ((value & 0xf) << 16);
1348 }
1349
1350 /* The MB and ME fields in an M form instruction expressed as a single
1351    operand which is itself a bitmask.  The extraction function always
1352    marks it as invalid, since we never want to recognize an
1353    instruction which uses a field of this type.  */
1354
1355 static unsigned long
1356 insert_mbe (unsigned long insn,
1357             long value,
1358             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1359             const char **errmsg)
1360 {
1361   unsigned long uval, mask;
1362   int mb, me, mx, count, last;
1363
1364   uval = value;
1365
1366   if (uval == 0)
1367     {
1368       *errmsg = _("illegal bitmask");
1369       return insn;
1370     }
1371
1372   mb = 0;
1373   me = 32;
1374   if ((uval & 1) != 0)
1375     last = 1;
1376   else
1377     last = 0;
1378   count = 0;
1379
1380   /* mb: location of last 0->1 transition */
1381   /* me: location of last 1->0 transition */
1382   /* count: # transitions */
1383
1384   for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1385     {
1386       if ((uval & mask) && !last)
1387         {
1388           ++count;
1389           mb = mx;
1390           last = 1;
1391         }
1392       else if (!(uval & mask) && last)
1393         {
1394           ++count;
1395           me = mx;
1396           last = 0;
1397         }
1398     }
1399   if (me == 0)
1400     me = 32;
1401
1402   if (count != 2 && (count != 0 || ! last))
1403     *errmsg = _("illegal bitmask");
1404
1405   return insn | (mb << 6) | ((me - 1) << 1);
1406 }
1407
1408 static long
1409 extract_mbe (unsigned long insn,
1410              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1411              int *invalid)
1412 {
1413   long ret;
1414   int mb, me;
1415   int i;
1416
1417   *invalid = 1;
1418
1419   mb = (insn >> 6) & 0x1f;
1420   me = (insn >> 1) & 0x1f;
1421   if (mb < me + 1)
1422     {
1423       ret = 0;
1424       for (i = mb; i <= me; i++)
1425         ret |= 1L << (31 - i);
1426     }
1427   else if (mb == me + 1)
1428     ret = ~0;
1429   else /* (mb > me + 1) */
1430     {
1431       ret = ~0;
1432       for (i = me + 1; i < mb; i++)
1433         ret &= ~(1L << (31 - i));
1434     }
1435   return ret;
1436 }
1437
1438 /* The MB or ME field in an MD or MDS form instruction.  The high bit
1439    is wrapped to the low end.  */
1440
1441 static unsigned long
1442 insert_mb6 (unsigned long insn,
1443             long value,
1444             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1445             const char **errmsg ATTRIBUTE_UNUSED)
1446 {
1447   return insn | ((value & 0x1f) << 6) | (value & 0x20);
1448 }
1449
1450 static long
1451 extract_mb6 (unsigned long insn,
1452              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1453              int *invalid ATTRIBUTE_UNUSED)
1454 {
1455   return ((insn >> 6) & 0x1f) | (insn & 0x20);
1456 }
1457
1458 /* The NB field in an X form instruction.  The value 32 is stored as
1459    0.  */
1460
1461 static long
1462 extract_nb (unsigned long insn,
1463             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1464             int *invalid ATTRIBUTE_UNUSED)
1465 {
1466   long ret;
1467
1468   ret = (insn >> 11) & 0x1f;
1469   if (ret == 0)
1470     ret = 32;
1471   return ret;
1472 }
1473
1474 /* The NB field in an lswi instruction, which has special value
1475    restrictions.  The value 32 is stored as 0.  */
1476
1477 static unsigned long
1478 insert_nbi (unsigned long insn,
1479             long value,
1480             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1481             const char **errmsg ATTRIBUTE_UNUSED)
1482 {
1483   long rtvalue = (insn & RT_MASK) >> 21;
1484   long ravalue = (insn & RA_MASK) >> 16;
1485
1486   if (value == 0)
1487     value = 32;
1488   if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32
1489                                                      : ravalue))
1490     *errmsg = _("address register in load range");
1491   return insn | ((value & 0x1f) << 11);
1492 }
1493
1494 /* The NSI field in a D form instruction.  This is the same as the SI
1495    field, only negated.  The extraction function always marks it as
1496    invalid, since we never want to recognize an instruction which uses
1497    a field of this type.  */
1498
1499 static unsigned long
1500 insert_nsi (unsigned long insn,
1501             long value,
1502             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1503             const char **errmsg ATTRIBUTE_UNUSED)
1504 {
1505   return insn | (-value & 0xffff);
1506 }
1507
1508 static long
1509 extract_nsi (unsigned long insn,
1510              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1511              int *invalid)
1512 {
1513   *invalid = 1;
1514   return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1515 }
1516
1517 /* The RA field in a D or X form instruction which is an updating
1518    load, which means that the RA field may not be zero and may not
1519    equal the RT field.  */
1520
1521 static unsigned long
1522 insert_ral (unsigned long insn,
1523             long value,
1524             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1525             const char **errmsg)
1526 {
1527   if (value == 0
1528       || (unsigned long) value == ((insn >> 21) & 0x1f))
1529     *errmsg = "invalid register operand when updating";
1530   return insn | ((value & 0x1f) << 16);
1531 }
1532
1533 /* The RA field in an lmw instruction, which has special value
1534    restrictions.  */
1535
1536 static unsigned long
1537 insert_ram (unsigned long insn,
1538             long value,
1539             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1540             const char **errmsg)
1541 {
1542   if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1543     *errmsg = _("index register in load range");
1544   return insn | ((value & 0x1f) << 16);
1545 }
1546
1547 /* The RA field in the DQ form lq or an lswx instruction, which have special
1548    value restrictions.  */
1549
1550 static unsigned long
1551 insert_raq (unsigned long insn,
1552             long value,
1553             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1554             const char **errmsg)
1555 {
1556   long rtvalue = (insn & RT_MASK) >> 21;
1557
1558   if (value == rtvalue)
1559     *errmsg = _("source and target register operands must be different");
1560   return insn | ((value & 0x1f) << 16);
1561 }
1562
1563 /* The RA field in a D or X form instruction which is an updating
1564    store or an updating floating point load, which means that the RA
1565    field may not be zero.  */
1566
1567 static unsigned long
1568 insert_ras (unsigned long insn,
1569             long value,
1570             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1571             const char **errmsg)
1572 {
1573   if (value == 0)
1574     *errmsg = _("invalid register operand when updating");
1575   return insn | ((value & 0x1f) << 16);
1576 }
1577
1578 /* The RB field in an X form instruction when it must be the same as
1579    the RS field in the instruction.  This is used for extended
1580    mnemonics like mr.  This operand is marked FAKE.  The insertion
1581    function just copies the BT field into the BA field, and the
1582    extraction function just checks that the fields are the same.  */
1583
1584 static unsigned long
1585 insert_rbs (unsigned long insn,
1586             long value ATTRIBUTE_UNUSED,
1587             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1588             const char **errmsg ATTRIBUTE_UNUSED)
1589 {
1590   return insn | (((insn >> 21) & 0x1f) << 11);
1591 }
1592
1593 static long
1594 extract_rbs (unsigned long insn,
1595              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1596              int *invalid)
1597 {
1598   if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1599     *invalid = 1;
1600   return 0;
1601 }
1602
1603 /* The RB field in an lswx instruction, which has special value
1604    restrictions.  */
1605
1606 static unsigned long
1607 insert_rbx (unsigned long insn,
1608             long value,
1609             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1610             const char **errmsg)
1611 {
1612   long rtvalue = (insn & RT_MASK) >> 21;
1613
1614   if (value == rtvalue)
1615     *errmsg = _("source and target register operands must be different");
1616   return insn | ((value & 0x1f) << 11);
1617 }
1618
1619 /* The SCI8 field is made up of SCL and {U,N}I8 fields.  */
1620 static unsigned long
1621 insert_sci8 (unsigned long insn,
1622              long value,
1623              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1624              const char **errmsg)
1625 {
1626   int fill = 0;
1627   int scale_factor = 0;
1628   long ui8 = value;
1629
1630   if ((value & 0xff000000) == (unsigned int) value)
1631     {
1632       scale_factor = 3;
1633       ui8 = value >> 24;
1634       fill = 0;
1635     }
1636   else if ((value & 0xff0000) == (unsigned int) value)
1637     {
1638       scale_factor = 2;
1639       ui8 = value >> 16;
1640       fill = 0;
1641     }
1642   else if ((value & 0xff00) == (unsigned int) value)
1643     {
1644       scale_factor = 1;
1645       ui8 = value >> 8;
1646       fill = 0;
1647     }
1648   else if ((value & 0xff) == value)
1649     {
1650       scale_factor = 0;
1651       ui8 = value;
1652       fill = 0;
1653     }
1654   else if ((value & 0xffffff00) == 0xffffff00)
1655     {
1656       scale_factor = 0;
1657       ui8 = (value & 0xff);
1658       fill = 1;
1659     }
1660   else if ((value & 0xffff00ff) == 0xffff00ff)
1661     {
1662       scale_factor = 1;
1663       ui8 = (value & 0xff00) >> 8;
1664       fill = 1;
1665     }
1666   else if ((value & 0xff00ffff) == 0xff00ffff)
1667     {
1668       scale_factor = 2;
1669       ui8 = (value & 0xff0000) >> 16;
1670       fill = 1;
1671     }
1672   else if ((value & 0x00ffffff) == 0x00ffffff)
1673     {
1674       scale_factor = 3;
1675       ui8 = (value & 0xff000000) >> 24;
1676       fill = 1;
1677     }
1678   else
1679     *errmsg = _("illegal immediate value");
1680
1681   return insn | (fill << 10) | (scale_factor << 8) | (ui8 & 0xff);
1682 }
1683
1684 static long
1685 extract_sci8 (unsigned long insn,
1686               ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1687               int *invalid ATTRIBUTE_UNUSED)
1688 {
1689   int scale_factor, fill;
1690   scale_factor = (insn & 0x300) >> 8;
1691   fill = (insn & 0x00000400) >> 10;
1692
1693   if (fill == 0)
1694     return (insn & 0xff) << (scale_factor << 3);
1695
1696   /* Fill is one.  */
1697   if (scale_factor == 0)
1698     return (insn & 0xff) | 0xffffff00;
1699   else if (scale_factor == 1)
1700     return 0xffff00ff | ((insn & 0xff) << (scale_factor << 3));
1701   else if (scale_factor == 2)
1702     return 0xff00ffff | (insn & 0xff << (scale_factor << 3));
1703   else /* scale_factor 3 */
1704     return 0x00ffffff | (insn & 0xff << (scale_factor << 3));
1705 }
1706
1707 static unsigned long
1708 insert_sci8n (unsigned long insn,
1709               long value,
1710               ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1711               const char **errmsg)
1712 {
1713   insn = insert_sci8 (insn, -(value & 0xff) & 0xff, 0, errmsg);
1714   /* Set the F bit.  */
1715   return insn | 0x400;
1716 }
1717
1718 static long
1719 extract_sci8n (unsigned long insn,
1720                ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1721                int *invalid ATTRIBUTE_UNUSED)
1722 {
1723   int scale_factor;
1724   scale_factor = (insn & 0x300) >> 8;
1725   return -(((insn & 0xff) ^ 0x80) - 0x80) << (scale_factor << 3);
1726 }
1727
1728 static unsigned long
1729 insert_sd4h (unsigned long insn,
1730              long value,
1731              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1732              const char **errmsg ATTRIBUTE_UNUSED)
1733 {
1734   return insn | ((value & 0x1e) << 7);
1735 }
1736
1737 static long
1738 extract_sd4h (unsigned long insn,
1739               ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1740               int *invalid ATTRIBUTE_UNUSED)
1741 {
1742   return ((insn >> 8) & 0xf) << 1;
1743 }
1744
1745 static unsigned long
1746 insert_sd4w (unsigned long insn,
1747              long value,
1748              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1749              const char **errmsg ATTRIBUTE_UNUSED)
1750 {
1751   return insn | ((value & 0x3c) << 6);
1752 }
1753
1754 static long
1755 extract_sd4w (unsigned long insn,
1756               ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1757               int *invalid ATTRIBUTE_UNUSED)
1758 {
1759   return ((insn >> 8) & 0xf) << 2;
1760 }
1761
1762 static unsigned long
1763 insert_oimm (unsigned long insn,
1764              long value,
1765              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1766              const char **errmsg ATTRIBUTE_UNUSED)
1767 {
1768   return insn | (((value - 1) & 0x1f) << 4);
1769 }
1770
1771 static long
1772 extract_oimm (unsigned long insn,
1773               ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1774               int *invalid ATTRIBUTE_UNUSED)
1775 {
1776   return ((insn >> 4) & 0x1f) + 1;
1777 }
1778
1779 /* The SH field in an MD form instruction.  This is split.  */
1780
1781 static unsigned long
1782 insert_sh6 (unsigned long insn,
1783             long value,
1784             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1785             const char **errmsg ATTRIBUTE_UNUSED)
1786 {
1787   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1788 }
1789
1790 static long
1791 extract_sh6 (unsigned long insn,
1792              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1793              int *invalid ATTRIBUTE_UNUSED)
1794 {
1795   return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1796 }
1797
1798 /* The SPR field in an XFX form instruction.  This is flipped--the
1799    lower 5 bits are stored in the upper 5 and vice- versa.  */
1800
1801 static unsigned long
1802 insert_spr (unsigned long insn,
1803             long value,
1804             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1805             const char **errmsg ATTRIBUTE_UNUSED)
1806 {
1807   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1808 }
1809
1810 static long
1811 extract_spr (unsigned long insn,
1812              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1813              int *invalid ATTRIBUTE_UNUSED)
1814 {
1815   return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1816 }
1817
1818 /* Some dialects have 8 SPRG registers instead of the standard 4.  */
1819 #define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405 | PPC_OPCODE_VLE)
1820
1821 static unsigned long
1822 insert_sprg (unsigned long insn,
1823              long value,
1824              ppc_cpu_t dialect,
1825              const char **errmsg)
1826 {
1827   if (value > 7
1828       || (value > 3 && (dialect & ALLOW8_SPRG) == 0))
1829     *errmsg = _("invalid sprg number");
1830
1831   /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1832      user mode.  Anything else must use spr 272..279.  */
1833   if (value <= 3 || (insn & 0x100) != 0)
1834     value |= 0x10;
1835
1836   return insn | ((value & 0x17) << 16);
1837 }
1838
1839 static long
1840 extract_sprg (unsigned long insn,
1841               ppc_cpu_t dialect,
1842               int *invalid)
1843 {
1844   unsigned long val = (insn >> 16) & 0x1f;
1845
1846   /* mfsprg can use 260..263 and 272..279.  mtsprg only uses spr 272..279
1847      If not BOOKE, 405 or VLE, then both use only 272..275.  */
1848   if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0)
1849       || (val - 0x10 > 7 && (insn & 0x100) != 0)
1850       || val <= 3
1851       || (val & 8) != 0)
1852     *invalid = 1;
1853   return val & 7;
1854 }
1855
1856 /* The TBR field in an XFX instruction.  This is just like SPR, but it
1857    is optional.  When TBR is omitted, it must be inserted as 268 (the
1858    magic number of the TB register).  These functions treat 0
1859    (indicating an omitted optional operand) as 268.  This means that
1860    ``mftb 4,0'' is not handled correctly.  This does not matter very
1861    much, since the architecture manual does not define mftb as
1862    accepting any values other than 268 or 269.  */
1863
1864 #define TB (268)
1865
1866 static unsigned long
1867 insert_tbr (unsigned long insn,
1868             long value,
1869             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1870             const char **errmsg ATTRIBUTE_UNUSED)
1871 {
1872   if (value == 0)
1873     value = TB;
1874   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1875 }
1876
1877 static long
1878 extract_tbr (unsigned long insn,
1879              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1880              int *invalid ATTRIBUTE_UNUSED)
1881 {
1882   long ret;
1883
1884   ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1885   if (ret == TB)
1886     ret = 0;
1887   return ret;
1888 }
1889
1890 /* The XT and XS fields in an XX1 or XX3 form instruction.  This is split.  */
1891
1892 static unsigned long
1893 insert_xt6 (unsigned long insn,
1894             long value,
1895             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1896             const char **errmsg ATTRIBUTE_UNUSED)
1897 {
1898   return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5);
1899 }
1900
1901 static long
1902 extract_xt6 (unsigned long insn,
1903              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1904              int *invalid ATTRIBUTE_UNUSED)
1905 {
1906   return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
1907 }
1908
1909 /* The XA field in an XX3 form instruction.  This is split.  */
1910
1911 static unsigned long
1912 insert_xa6 (unsigned long insn,
1913             long value,
1914             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1915             const char **errmsg ATTRIBUTE_UNUSED)
1916 {
1917   return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3);
1918 }
1919
1920 static long
1921 extract_xa6 (unsigned long insn,
1922              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1923              int *invalid ATTRIBUTE_UNUSED)
1924 {
1925   return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
1926 }
1927
1928 /* The XB field in an XX3 form instruction.  This is split.  */
1929
1930 static unsigned long
1931 insert_xb6 (unsigned long insn,
1932             long value,
1933             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1934             const char **errmsg ATTRIBUTE_UNUSED)
1935 {
1936   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1937 }
1938
1939 static long
1940 extract_xb6 (unsigned long insn,
1941              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1942              int *invalid ATTRIBUTE_UNUSED)
1943 {
1944   return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f);
1945 }
1946
1947 /* The XB field in an XX3 form instruction when it must be the same as
1948    the XA field in the instruction.  This is used for extended
1949    mnemonics like xvmovdp.  This operand is marked FAKE.  The insertion
1950    function just copies the XA field into the XB field, and the
1951    extraction function just checks that the fields are the same.  */
1952
1953 static unsigned long
1954 insert_xb6s (unsigned long insn,
1955             long value ATTRIBUTE_UNUSED,
1956             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1957             const char **errmsg ATTRIBUTE_UNUSED)
1958 {
1959   return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1);
1960 }
1961
1962 static long
1963 extract_xb6s (unsigned long insn,
1964              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1965              int *invalid)
1966 {
1967   if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
1968       || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1)))
1969     *invalid = 1;
1970   return 0;
1971 }
1972
1973 /* The XC field in an XX4 form instruction.  This is split.  */
1974
1975 static unsigned long
1976 insert_xc6 (unsigned long insn,
1977             long value,
1978             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1979             const char **errmsg ATTRIBUTE_UNUSED)
1980 {
1981   return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2);
1982 }
1983
1984 static long
1985 extract_xc6 (unsigned long insn,
1986              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1987              int *invalid ATTRIBUTE_UNUSED)
1988 {
1989   return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f);
1990 }
1991
1992 static unsigned long
1993 insert_dm (unsigned long insn,
1994            long value,
1995            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1996            const char **errmsg)
1997 {
1998   if (value != 0 && value != 1)
1999     *errmsg = _("invalid constant");
2000   return insn | (((value) ? 3 : 0) << 8);
2001 }
2002
2003 static long
2004 extract_dm (unsigned long insn,
2005             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2006             int *invalid)
2007 {
2008   long value;
2009
2010   value = (insn >> 8) & 3;
2011   if (value != 0 && value != 3)
2012     *invalid = 1;
2013   return (value) ? 1 : 0;
2014 }
2015 /* The VLESIMM field in an I16A form instruction.  This is split.  */
2016
2017 static unsigned long
2018 insert_vlesi (unsigned long insn,
2019             long value,
2020             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2021             const char **errmsg ATTRIBUTE_UNUSED)
2022 {
2023   return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2024 }
2025
2026 static long
2027 extract_vlesi (unsigned long insn,
2028              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2029              int *invalid ATTRIBUTE_UNUSED)
2030 {
2031   /* RWRW Because I don't know how to make int be 16 and long be 32 */
2032   /* I can't rely on casting an int to long to get sign extension. */
2033   long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2034   if (value & 0x8000)
2035     value |= 0xffff0000;
2036   return value;
2037 }
2038
2039 static unsigned long
2040 insert_vlensi (unsigned long insn,
2041             long value,
2042             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2043             const char **errmsg ATTRIBUTE_UNUSED)
2044 {
2045   value = -value;
2046   return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2047 }
2048 static long
2049 extract_vlensi (unsigned long insn,
2050              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2051              int *invalid ATTRIBUTE_UNUSED)
2052 {
2053   long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2054   if (value & 0x8000)
2055     value |= 0xffff0000;
2056   *invalid = 1;
2057   return -value;
2058 }
2059
2060 /* The VLEUIMM field in an I16A form instruction.  This is split.  */
2061
2062 static unsigned long
2063 insert_vleui (unsigned long insn,
2064             long value,
2065             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2066             const char **errmsg ATTRIBUTE_UNUSED)
2067 {
2068   return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2069 }
2070
2071 static long
2072 extract_vleui (unsigned long insn,
2073              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2074              int *invalid ATTRIBUTE_UNUSED)
2075 {
2076   return ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2077 }
2078
2079 /* The VLEUIMML field in an I16L form instruction.  This is split.  */
2080
2081 static unsigned long
2082 insert_vleil (unsigned long insn,
2083             long value,
2084             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2085             const char **errmsg ATTRIBUTE_UNUSED)
2086 {
2087   return insn | ((value & 0xf800) << 5) | (value & 0x7ff);
2088 }
2089
2090 static long
2091 extract_vleil (unsigned long insn,
2092              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2093              int *invalid ATTRIBUTE_UNUSED)
2094 {
2095   return ((insn >> 5) & 0xf800) | (insn & 0x7ff);
2096 }
2097
2098 \f
2099 /* Macros used to form opcodes.  */
2100
2101 /* The main opcode.  */
2102 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
2103 #define OP_MASK OP (0x3f)
2104
2105 /* The main opcode combined with a trap code in the TO field of a D
2106    form instruction.  Used for extended mnemonics for the trap
2107    instructions.  */
2108 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
2109 #define OPTO_MASK (OP_MASK | TO_MASK)
2110
2111 /* The main opcode combined with a comparison size bit in the L field
2112    of a D form or X form instruction.  Used for extended mnemonics for
2113    the comparison instructions.  */
2114 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
2115 #define OPL_MASK OPL (0x3f,1)
2116
2117 /* The main opcode combined with an update code in D form instruction.
2118    Used for extended mnemonics for VLE memory instructions.  */
2119 #define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8))
2120 #define OPVUP_MASK OPVUP (0x3f,  0xff)
2121
2122 /* An A form instruction.  */
2123 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
2124 #define A_MASK A (0x3f, 0x1f, 1)
2125
2126 /* An A_MASK with the FRB field fixed.  */
2127 #define AFRB_MASK (A_MASK | FRB_MASK)
2128
2129 /* An A_MASK with the FRC field fixed.  */
2130 #define AFRC_MASK (A_MASK | FRC_MASK)
2131
2132 /* An A_MASK with the FRA and FRC fields fixed.  */
2133 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
2134
2135 /* An AFRAFRC_MASK, but with L bit clear.  */
2136 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
2137
2138 /* A B form instruction.  */
2139 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
2140 #define B_MASK B (0x3f, 1, 1)
2141
2142 /* A BD8 form instruction.  This is a 16-bit instruction.  */
2143 #define BD8(op, aa, lk) (((((unsigned long)(op)) & 0x3f) << 10) | (((aa) & 1) << 9) | (((lk) & 1) << 8))
2144 #define BD8_MASK BD8 (0x3f, 1, 1)
2145
2146 /* Another BD8 form instruction.  This is a 16-bit instruction.  */
2147 #define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11)
2148 #define BD8IO_MASK BD8IO (0x1f)
2149
2150 /* A BD8 form instruction for simplified mnemonics.  */
2151 #define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
2152 /* A mask that excludes BO32 and BI32.  */
2153 #define EBD8IO1_MASK 0xf800
2154 /* A mask that includes BO32 and excludes BI32.  */
2155 #define EBD8IO2_MASK 0xfc00
2156 /* A mask that include BO32 AND BI32.  */
2157 #define EBD8IO3_MASK 0xff00
2158
2159 /* A BD15 form instruction.  */
2160 #define BD15(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 0xf) << 22) | ((lk) & 1))
2161 #define BD15_MASK BD15 (0x3f, 0xf, 1)
2162
2163 /* A BD15 form instruction for extended conditional branch mnemonics.  */
2164 #define EBD15(op, aa, bo, lk) (((op) & 0x3f) << 26) | (((aa) & 0xf) << 22) | (((bo) & 0x3) << 20) | ((lk) & 1)
2165 #define EBD15_MASK 0xfff00001
2166
2167 /* A BD15 form instruction for extended conditional branch mnemonics with BI.  */
2168 #define EBD15BI(op, aa, bo, bi, lk) (((op) & 0x3f) << 26) \
2169                                     | (((aa) & 0xf) << 22) \
2170                                     | (((bo) & 0x3) << 20) \
2171                                     | (((bi) & 0x3) << 16) \
2172                                     | ((lk) & 1)
2173 #define EBD15BI_MASK  0xfff30001
2174
2175 /* A BD24 form instruction.  */
2176 #define BD24(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 25) | ((lk) & 1))
2177 #define BD24_MASK BD24 (0x3f, 1, 1)
2178
2179 /* A B form instruction setting the BO field.  */
2180 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2181 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
2182
2183 /* A BBO_MASK with the y bit of the BO field removed.  This permits
2184    matching a conditional branch regardless of the setting of the y
2185    bit.  Similarly for the 'at' bits used for power4 branch hints.  */
2186 #define Y_MASK   (((unsigned long) 1) << 21)
2187 #define AT1_MASK (((unsigned long) 3) << 21)
2188 #define AT2_MASK (((unsigned long) 9) << 21)
2189 #define BBOY_MASK  (BBO_MASK &~ Y_MASK)
2190 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
2191
2192 /* A B form instruction setting the BO field and the condition bits of
2193    the BI field.  */
2194 #define BBOCB(op, bo, cb, aa, lk) \
2195   (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
2196 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
2197
2198 /* A BBOCB_MASK with the y bit of the BO field removed.  */
2199 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
2200 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
2201 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
2202
2203 /* A BBOYCB_MASK in which the BI field is fixed.  */
2204 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
2205 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
2206
2207 /* A VLE C form instruction.  */
2208 #define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1))
2209 #define C_LK_MASK C_LK(0x7fff, 1)
2210 #define C(x) ((((unsigned long)(x)) & 0xffff))
2211 #define C_MASK C(0xffff)
2212
2213 /* An Context form instruction.  */
2214 #define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))
2215 #define CTX_MASK CTX(0x3f, 0x7)
2216
2217 /* An User Context form instruction.  */
2218 #define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
2219 #define UCTX_MASK UCTX(0x3f, 0x1f)
2220
2221 /* The main opcode mask with the RA field clear.  */
2222 #define DRA_MASK (OP_MASK | RA_MASK)
2223
2224 /* A DS form instruction.  */
2225 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
2226 #define DS_MASK DSO (0x3f, 3)
2227
2228 /* An EVSEL form instruction.  */
2229 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
2230 #define EVSEL_MASK EVSEL(0x3f, 0xff)
2231
2232 /* An IA16 form instruction.  */
2233 #define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2234 #define IA16_MASK IA16(0x3f, 0x1f)
2235
2236 /* An I16A form instruction.  */
2237 #define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2238 #define I16A_MASK I16A(0x3f, 0x1f)
2239
2240 /* An I16L form instruction.  */
2241 #define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2242 #define I16L_MASK I16L(0x3f, 0x1f)
2243
2244 /* An IM7 form instruction.  */
2245 #define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11)
2246 #define IM7_MASK IM7(0x1f)
2247
2248 /* An M form instruction.  */
2249 #define M(op, rc) (OP (op) | ((rc) & 1))
2250 #define M_MASK M (0x3f, 1)
2251
2252 /* An LI20 form instruction.  */
2253 #define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15)
2254 #define LI20_MASK LI20(0x3f, 0x1)
2255
2256 /* An M form instruction with the ME field specified.  */
2257 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
2258
2259 /* An M_MASK with the MB and ME fields fixed.  */
2260 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
2261
2262 /* An M_MASK with the SH and ME fields fixed.  */
2263 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
2264
2265 /* An MD form instruction.  */
2266 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
2267 #define MD_MASK MD (0x3f, 0x7, 1)
2268
2269 /* An MD_MASK with the MB field fixed.  */
2270 #define MDMB_MASK (MD_MASK | MB6_MASK)
2271
2272 /* An MD_MASK with the SH field fixed.  */
2273 #define MDSH_MASK (MD_MASK | SH6_MASK)
2274
2275 /* An MDS form instruction.  */
2276 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
2277 #define MDS_MASK MDS (0x3f, 0xf, 1)
2278
2279 /* An MDS_MASK with the MB field fixed.  */
2280 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
2281
2282 /* An SC form instruction.  */
2283 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
2284 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
2285
2286 /* An SCI8 form instruction.  */
2287 #define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11))
2288 #define SCI8_MASK SCI8(0x3f, 0x1f)
2289
2290 /* An SCI8 form instruction.  */
2291 #define SCI8BF(op, fop, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11) | (((fop) & 7) << 23))
2292 #define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
2293
2294 /* An SD4 form instruction.  This is a 16-bit instruction.  */
2295 #define SD4(op) ((((unsigned long)(op)) & 0xf) << 12)
2296 #define SD4_MASK SD4(0xf)
2297
2298 /* An SE_IM5 form instruction.  This is a 16-bit instruction.  */
2299 #define SE_IM5(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x1) << 9))
2300 #define SE_IM5_MASK SE_IM5(0x3f, 1)
2301
2302 /* An SE_R form instruction.  This is a 16-bit instruction.  */
2303 #define SE_R(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3f) << 4))
2304 #define SE_R_MASK SE_R(0x3f, 0x3f)
2305
2306 /* An SE_RR form instruction.  This is a 16-bit instruction.  */
2307 #define SE_RR(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3) << 8))
2308 #define SE_RR_MASK SE_RR(0x3f, 3)
2309
2310 /* A VX form instruction.  */
2311 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2312
2313 /* The mask for an VX form instruction.  */
2314 #define VX_MASK VX(0x3f, 0x7ff)
2315
2316 /* A VA form instruction.  */
2317 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
2318
2319 /* The mask for an VA form instruction.  */
2320 #define VXA_MASK VXA(0x3f, 0x3f)
2321
2322 /* A VXR form instruction.  */
2323 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
2324
2325 /* The mask for a VXR form instruction.  */
2326 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
2327
2328 /* An X form instruction.  */
2329 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2330
2331 /* An EX form instruction.  */
2332 #define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2333
2334 /* The mask for an EX form instruction.  */
2335 #define EX_MASK EX (0x3f, 0x7ff)
2336
2337 /* An XX2 form instruction.  */
2338 #define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
2339
2340 /* An XX3 form instruction.  */
2341 #define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
2342
2343 /* An XX3 form instruction with the RC bit specified.  */
2344 #define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))
2345
2346 /* An XX4 form instruction.  */
2347 #define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
2348
2349 /* A Z form instruction.  */
2350 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
2351
2352 /* An X form instruction with the RC bit specified.  */
2353 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
2354
2355 /* A Z form instruction with the RC bit specified.  */
2356 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
2357
2358 /* The mask for an X form instruction.  */
2359 #define X_MASK XRC (0x3f, 0x3ff, 1)
2360
2361 /* An X form wait instruction with everything filled in except the WC field.  */
2362 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2363
2364 /* The mask for an XX1 form instruction.  */
2365 #define XX1_MASK X (0x3f, 0x3ff)
2366
2367 /* The mask for an XX2 form instruction.  */
2368 #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
2369
2370 /* The mask for an XX2 form instruction with the UIM bits specified.  */
2371 #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
2372
2373 /* The mask for an XX2 form instruction with the BF bits specified.  */
2374 #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
2375
2376 /* The mask for an XX3 form instruction.  */
2377 #define XX3_MASK XX3 (0x3f, 0xff)
2378
2379 /* The mask for an XX3 form instruction with the BF bits specified.  */
2380 #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
2381
2382 /* The mask for an XX3 form instruction with the DM or SHW bits specified.  */
2383 #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
2384 #define XX3SHW_MASK XX3DM_MASK
2385
2386 /* The mask for an XX4 form instruction.  */
2387 #define XX4_MASK XX4 (0x3f, 0x3)
2388
2389 /* An X form wait instruction with everything filled in except the WC field.  */
2390 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2391
2392 /* The mask for a Z form instruction.  */
2393 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
2394 #define Z2_MASK ZRC (0x3f, 0xff, 1)
2395
2396 /* An X_MASK with the RA field fixed.  */
2397 #define XRA_MASK (X_MASK | RA_MASK)
2398
2399 /* An XRA_MASK with the W field clear.  */
2400 #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
2401
2402 /* An X_MASK with the RB field fixed.  */
2403 #define XRB_MASK (X_MASK | RB_MASK)
2404
2405 /* An X_MASK with the RT field fixed.  */
2406 #define XRT_MASK (X_MASK | RT_MASK)
2407
2408 /* An XRT_MASK mask with the L bits clear.  */
2409 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
2410
2411 /* An X_MASK with the RA and RB fields fixed.  */
2412 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
2413
2414 /* An XRARB_MASK, but with the L bit clear.  */
2415 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
2416
2417 /* An X_MASK with the RT and RA fields fixed.  */
2418 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
2419
2420 /* An XRTRA_MASK, but with L bit clear.  */
2421 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
2422
2423 /* An X form instruction with the L bit specified.  */
2424 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
2425
2426 /* An X form instruction with the L bits specified.  */
2427 #define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2428
2429 /* An X form instruction with RT fields specified */
2430 #define XRT(op, xop, rt) (X ((op), (xop)) \
2431         | ((((unsigned long)(rt)) & 0x1f) << 21))
2432
2433 /* An X form instruction with RT and RA fields specified */
2434 #define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
2435         | ((((unsigned long)(rt)) & 0x1f) << 21) \
2436         | ((((unsigned long)(ra)) & 0x1f) << 16))
2437
2438 /* The mask for an X form comparison instruction.  */
2439 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
2440
2441 /* The mask for an X form comparison instruction with the L field
2442    fixed.  */
2443 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
2444
2445 /* An X form trap instruction with the TO field specified.  */
2446 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
2447 #define XTO_MASK (X_MASK | TO_MASK)
2448
2449 /* An X form tlb instruction with the SH field specified.  */
2450 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
2451 #define XTLB_MASK (X_MASK | SH_MASK)
2452
2453 /* An X form sync instruction.  */
2454 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2455
2456 /* An X form sync instruction with everything filled in except the LS field.  */
2457 #define XSYNC_MASK (0xff9fffff)
2458
2459 /* An X form sync instruction with everything filled in except the L and E fields.  */
2460 #define XSYNCLE_MASK (0xff90ffff)
2461
2462 /* An X_MASK, but with the EH bit clear.  */
2463 #define XEH_MASK (X_MASK & ~((unsigned long )1))
2464
2465 /* An X form AltiVec dss instruction.  */
2466 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
2467 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
2468
2469 /* An XFL form instruction.  */
2470 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2471 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
2472
2473 /* An X form isel instruction.  */
2474 #define XISEL(op, xop)  (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2475 #define XISEL_MASK      XISEL(0x3f, 0x1f)
2476
2477 /* An XL form instruction with the LK field set to 0.  */
2478 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2479
2480 /* An XL form instruction which uses the LK field.  */
2481 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
2482
2483 /* The mask for an XL form instruction.  */
2484 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
2485
2486 /* An XL form instruction which explicitly sets the BO field.  */
2487 #define XLO(op, bo, xop, lk) \
2488   (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2489 #define XLO_MASK (XL_MASK | BO_MASK)
2490
2491 /* An XL form instruction which explicitly sets the y bit of the BO
2492    field.  */
2493 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
2494 #define XLYLK_MASK (XL_MASK | Y_MASK)
2495
2496 /* An XL form instruction which sets the BO field and the condition
2497    bits of the BI field.  */
2498 #define XLOCB(op, bo, cb, xop, lk) \
2499   (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
2500 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
2501
2502 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
2503 #define XLBB_MASK (XL_MASK | BB_MASK)
2504 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
2505 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
2506
2507 /* A mask for branch instructions using the BH field.  */
2508 #define XLBH_MASK (XL_MASK | (0x1c << 11))
2509
2510 /* An XL_MASK with the BO and BB fields fixed.  */
2511 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
2512
2513 /* An XL_MASK with the BO, BI and BB fields fixed.  */
2514 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
2515
2516 /* An X form mbar instruction with MO field.  */
2517 #define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21))
2518
2519 /* An XO form instruction.  */
2520 #define XO(op, xop, oe, rc) \
2521   (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
2522 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
2523
2524 /* An XO_MASK with the RB field fixed.  */
2525 #define XORB_MASK (XO_MASK | RB_MASK)
2526
2527 /* An XOPS form instruction for paired singles.  */
2528 #define XOPS(op, xop, rc) \
2529   (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2530 #define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
2531
2532
2533 /* An XS form instruction.  */
2534 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
2535 #define XS_MASK XS (0x3f, 0x1ff, 1)
2536
2537 /* A mask for the FXM version of an XFX form instruction.  */
2538 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
2539
2540 /* An XFX form instruction with the FXM field filled in.  */
2541 #define XFXM(op, xop, fxm, p4) \
2542   (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
2543    | ((unsigned long)(p4) << 20))
2544
2545 /* An XFX form instruction with the SPR field filled in.  */
2546 #define XSPR(op, xop, spr) \
2547   (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
2548 #define XSPR_MASK (X_MASK | SPR_MASK)
2549
2550 /* An XFX form instruction with the SPR field filled in except for the
2551    SPRBAT field.  */
2552 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
2553
2554 /* An XFX form instruction with the SPR field filled in except for the
2555    SPRG field.  */
2556 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
2557
2558 /* An X form instruction with everything filled in except the E field.  */
2559 #define XE_MASK (0xffff7fff)
2560
2561 /* An X form user context instruction.  */
2562 #define XUC(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
2563 #define XUC_MASK      XUC(0x3f, 0x1f)
2564
2565 /* An XW form instruction.  */
2566 #define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
2567 /* The mask for a G form instruction. rc not supported at present.  */
2568 #define XW_MASK XW (0x3f, 0x3f, 0)
2569
2570 /* An APU form instruction.  */
2571 #define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
2572
2573 /* The mask for an APU form instruction.  */
2574 #define APU_MASK APU (0x3f, 0x3ff, 1)
2575 #define APU_RT_MASK (APU_MASK | RT_MASK)
2576 #define APU_RA_MASK (APU_MASK | RA_MASK)
2577
2578 /* The BO encodings used in extended conditional branch mnemonics.  */
2579 #define BODNZF  (0x0)
2580 #define BODNZFP (0x1)
2581 #define BODZF   (0x2)
2582 #define BODZFP  (0x3)
2583 #define BODNZT  (0x8)
2584 #define BODNZTP (0x9)
2585 #define BODZT   (0xa)
2586 #define BODZTP  (0xb)
2587
2588 #define BOF     (0x4)
2589 #define BOFP    (0x5)
2590 #define BOFM4   (0x6)
2591 #define BOFP4   (0x7)
2592 #define BOT     (0xc)
2593 #define BOTP    (0xd)
2594 #define BOTM4   (0xe)
2595 #define BOTP4   (0xf)
2596
2597 #define BODNZ   (0x10)
2598 #define BODNZP  (0x11)
2599 #define BODZ    (0x12)
2600 #define BODZP   (0x13)
2601 #define BODNZM4 (0x18)
2602 #define BODNZP4 (0x19)
2603 #define BODZM4  (0x1a)
2604 #define BODZP4  (0x1b)
2605
2606 #define BOU     (0x14)
2607
2608 /* The BO16 encodings used in extended VLE conditional branch mnemonics.  */
2609 #define BO16F   (0x0)
2610 #define BO16T   (0x1)
2611
2612 /* The BO32 encodings used in extended VLE conditional branch mnemonics.  */
2613 #define BO32F   (0x0)
2614 #define BO32T   (0x1)
2615 #define BO32DNZ (0x2)
2616 #define BO32DZ  (0x3)
2617
2618 /* The BI condition bit encodings used in extended conditional branch
2619    mnemonics.  */
2620 #define CBLT    (0)
2621 #define CBGT    (1)
2622 #define CBEQ    (2)
2623 #define CBSO    (3)
2624
2625 /* The TO encodings used in extended trap mnemonics.  */
2626 #define TOLGT   (0x1)
2627 #define TOLLT   (0x2)
2628 #define TOEQ    (0x4)
2629 #define TOLGE   (0x5)
2630 #define TOLNL   (0x5)
2631 #define TOLLE   (0x6)
2632 #define TOLNG   (0x6)
2633 #define TOGT    (0x8)
2634 #define TOGE    (0xc)
2635 #define TONL    (0xc)
2636 #define TOLT    (0x10)
2637 #define TOLE    (0x14)
2638 #define TONG    (0x14)
2639 #define TONE    (0x18)
2640 #define TOU     (0x1f)
2641 \f
2642 /* Smaller names for the flags so each entry in the opcodes table will
2643    fit on a single line.  */
2644 #define PPCNONE 0
2645 #undef  PPC
2646 #define PPC     PPC_OPCODE_PPC
2647 #define PPCCOM  PPC_OPCODE_PPC | PPC_OPCODE_COMMON
2648 #define POWER4  PPC_OPCODE_POWER4
2649 #define POWER5  PPC_OPCODE_POWER5
2650 #define POWER6  PPC_OPCODE_POWER6
2651 #define POWER7  PPC_OPCODE_POWER7
2652 #define CELL    PPC_OPCODE_CELL
2653 #define PPC64   PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
2654 #define NON32   (PPC_OPCODE_64 | PPC_OPCODE_POWER4      \
2655                  | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
2656 #define PPC403  PPC_OPCODE_403
2657 #define PPC405  PPC_OPCODE_405
2658 #define PPC440  PPC_OPCODE_440
2659 #define PPC464  PPC440
2660 #define PPC476  PPC_OPCODE_476
2661 #define PPC750  PPC
2662 #define PPC7450 PPC
2663 #define PPC860  PPC
2664 #define PPCPS   PPC_OPCODE_PPCPS
2665 #define PPCVEC  PPC_OPCODE_ALTIVEC
2666 #define PPCVEC2 PPC_OPCODE_ALTIVEC2
2667 #define PPCVSX  PPC_OPCODE_VSX
2668 #define POWER   PPC_OPCODE_POWER
2669 #define POWER2  PPC_OPCODE_POWER | PPC_OPCODE_POWER2
2670 #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
2671 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
2672 #define COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
2673 #define M601    PPC_OPCODE_POWER | PPC_OPCODE_601
2674 #define PWRCOM  PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
2675 #define MFDEC1  PPC_OPCODE_POWER
2676 #define MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
2677 #define BOOKE   PPC_OPCODE_BOOKE
2678 #define NO371   PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS | PPC_OPCODE_VLE
2679 #define PPCE300 PPC_OPCODE_E300
2680 #define PPCSPE  PPC_OPCODE_SPE | PPC_OPCODE_VLE
2681 #define PPCISEL PPC_OPCODE_ISEL | PPC_OPCODE_VLE
2682 #define PPCEFS  PPC_OPCODE_EFS | PPC_OPCODE_VLE
2683 #define PPCBRLK PPC_OPCODE_BRLOCK
2684 #define PPCPMR  PPC_OPCODE_PMR
2685 #define PPCTMR  PPC_OPCODE_TMR
2686 #define PPCCHLK PPC_OPCODE_CACHELCK
2687 #define PPCRFMCI        PPC_OPCODE_RFMCI
2688 #define E500MC  PPC_OPCODE_E500MC
2689 #define PPCA2   PPC_OPCODE_A2
2690 #define TITAN   PPC_OPCODE_TITAN
2691 #define MULHW   PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN | PPC_OPCODE_VLE
2692 #define E500    PPC_OPCODE_E500
2693 #define E6500   PPC_OPCODE_E6500
2694 #define PPCVLE  PPC_OPCODE_VLE
2695 \f
2696 /* The opcode table.
2697
2698    The format of the opcode table is:
2699
2700    NAME         OPCODE          MASK         FLAGS      ANTI            {OPERANDS}
2701
2702    NAME is the name of the instruction.
2703    OPCODE is the instruction opcode.
2704    MASK is the opcode mask; this is used to tell the disassembler
2705      which bits in the actual opcode must match OPCODE.
2706    FLAGS are flags indicating which processors support the instruction.
2707    ANTI indicates which processors don't support the instruction.
2708    OPERANDS is the list of operands.
2709
2710    The disassembler reads the table in order and prints the first
2711    instruction which matches, so this table is sorted to put more
2712    specific instructions before more general instructions.
2713
2714    This table must be sorted by major opcode.  Please try to keep it
2715    vaguely sorted within major opcode too, except of course where
2716    constrained otherwise by disassembler operation.  */
2717
2718 const struct powerpc_opcode powerpc_opcodes[] = {
2719 {"attn",        X(0,256),       X_MASK,   POWER4|PPCA2, PPC476,         {0}},
2720 {"tdlgti",      OPTO(2,TOLGT),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2721 {"tdllti",      OPTO(2,TOLLT),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2722 {"tdeqi",       OPTO(2,TOEQ),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2723 {"tdlgei",      OPTO(2,TOLGE),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2724 {"tdlnli",      OPTO(2,TOLNL),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2725 {"tdllei",      OPTO(2,TOLLE),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2726 {"tdlngi",      OPTO(2,TOLNG),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2727 {"tdgti",       OPTO(2,TOGT),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2728 {"tdgei",       OPTO(2,TOGE),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2729 {"tdnli",       OPTO(2,TONL),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2730 {"tdlti",       OPTO(2,TOLT),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2731 {"tdlei",       OPTO(2,TOLE),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2732 {"tdngi",       OPTO(2,TONG),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2733 {"tdnei",       OPTO(2,TONE),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2734 {"tdi",         OP(2),          OP_MASK,     PPC64,     PPCNONE,        {TO, RA, SI}},
2735
2736 {"twlgti",      OPTO(3,TOLGT),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2737 {"tlgti",       OPTO(3,TOLGT),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2738 {"twllti",      OPTO(3,TOLLT),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2739 {"tllti",       OPTO(3,TOLLT),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2740 {"tweqi",       OPTO(3,TOEQ),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2741 {"teqi",        OPTO(3,TOEQ),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2742 {"twlgei",      OPTO(3,TOLGE),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2743 {"tlgei",       OPTO(3,TOLGE),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2744 {"twlnli",      OPTO(3,TOLNL),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2745 {"tlnli",       OPTO(3,TOLNL),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2746 {"twllei",      OPTO(3,TOLLE),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2747 {"tllei",       OPTO(3,TOLLE),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2748 {"twlngi",      OPTO(3,TOLNG),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2749 {"tlngi",       OPTO(3,TOLNG),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2750 {"twgti",       OPTO(3,TOGT),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2751 {"tgti",        OPTO(3,TOGT),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2752 {"twgei",       OPTO(3,TOGE),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2753 {"tgei",        OPTO(3,TOGE),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2754 {"twnli",       OPTO(3,TONL),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2755 {"tnli",        OPTO(3,TONL),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2756 {"twlti",       OPTO(3,TOLT),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2757 {"tlti",        OPTO(3,TOLT),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2758 {"twlei",       OPTO(3,TOLE),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2759 {"tlei",        OPTO(3,TOLE),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2760 {"twngi",       OPTO(3,TONG),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2761 {"tngi",        OPTO(3,TONG),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2762 {"twnei",       OPTO(3,TONE),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2763 {"tnei",        OPTO(3,TONE),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2764 {"twi",         OP(3),          OP_MASK,     PPCCOM,    PPCNONE,        {TO, RA, SI}},
2765 {"ti",          OP(3),          OP_MASK,     PWRCOM,    PPCNONE,        {TO, RA, SI}},
2766
2767 {"ps_cmpu0",    X  (4,   0), X_MASK|(3<<21), PPCPS,     PPCNONE,        {BF, FRA, FRB}},
2768 {"vaddubm",     VX (4,   0),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2769 {"vmaxub",      VX (4,   2),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2770 {"vrlb",        VX (4,   4),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2771 {"vcmpequb",    VXR(4,   6,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2772 {"vmuloub",     VX (4,   8),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2773 {"vaddfp",      VX (4,  10),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2774 {"psq_lx",      XW (4,   6,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRT,RA,RB,PSWM,PSQM}},
2775 {"vmrghb",      VX (4,  12),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2776 {"psq_stx",     XW (4,   7,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRS,RA,RB,PSWM,PSQM}},
2777 {"vpkuhum",     VX (4,  14),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2778 {"mulhhwu",     XRC(4,   8,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2779 {"mulhhwu.",    XRC(4,   8,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2780 {"ps_sum0",     A  (4,  10,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2781 {"ps_sum0.",    A  (4,  10,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2782 {"ps_sum1",     A  (4,  11,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2783 {"ps_sum1.",    A  (4,  11,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2784 {"ps_muls0",    A  (4,  12,0),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2785 {"machhwu",     XO (4,  12,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2786 {"ps_muls0.",   A  (4,  12,1),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2787 {"machhwu.",    XO (4,  12,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2788 {"ps_muls1",    A  (4,  13,0),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2789 {"ps_muls1.",   A  (4,  13,1),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2790 {"ps_madds0",   A  (4,  14,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2791 {"ps_madds0.",  A  (4,  14,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2792 {"ps_madds1",   A  (4,  15,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2793 {"ps_madds1.",  A  (4,  15,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2794 {"vmhaddshs",   VXA(4,  32),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2795 {"vmhraddshs",  VXA(4,  33),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2796 {"vmladduhm",   VXA(4,  34),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2797 {"ps_div",      A  (4,  18,0),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2798 {"vmsumubm",    VXA(4,  36),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2799 {"ps_div.",     A  (4,  18,1),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2800 {"vmsummbm",    VXA(4,  37),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2801 {"vmsumuhm",    VXA(4,  38),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2802 {"vmsumuhs",    VXA(4,  39),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2803 {"ps_sub",      A  (4,  20,0),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2804 {"vmsumshm",    VXA(4,  40),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2805 {"ps_sub.",     A  (4,  20,1),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2806 {"vmsumshs",    VXA(4,  41),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2807 {"ps_add",      A  (4,  21,0),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2808 {"vsel",        VXA(4,  42),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2809 {"ps_add.",     A  (4,  21,1),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2810 {"vperm",       VXA(4,  43),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2811 {"vsldoi",      VXA(4,  44),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, SHB}},
2812 {"ps_sel",      A  (4,  23,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2813 {"vmaddfp",     VXA(4,  46),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VC, VB}},
2814 {"ps_sel.",     A  (4,  23,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2815 {"vnmsubfp",    VXA(4,  47),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VC, VB}},
2816 {"ps_res",      A  (4,  24,0), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
2817 {"ps_res.",     A  (4,  24,1), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
2818 {"ps_mul",      A  (4,  25,0), AFRB_MASK,    PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2819 {"ps_mul.",     A  (4,  25,1),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2820 {"ps_rsqrte",   A  (4,  26,0), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
2821 {"ps_rsqrte.",  A  (4,  26,1), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
2822 {"ps_msub",     A  (4,  28,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2823 {"ps_msub.",    A  (4,  28,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2824 {"ps_madd",     A  (4,  29,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2825 {"ps_madd.",    A  (4,  29,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2826 {"ps_nmsub",    A  (4,  30,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2827 {"ps_nmsub.",   A  (4,  30,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2828 {"ps_nmadd",    A  (4,  31,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2829 {"ps_nmadd.",   A  (4,  31,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2830 {"ps_cmpo0",    X  (4,  32), X_MASK|(3<<21), PPCPS,     PPCNONE,        {BF, FRA, FRB}},
2831 {"vadduhm",     VX (4,  64),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2832 {"vmaxuh",      VX (4,  66),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2833 {"vrlh",        VX (4,  68),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2834 {"vcmpequh",    VXR(4,  70,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2835 {"vmulouh",     VX (4,  72),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2836 {"vsubfp",      VX (4,  74),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2837 {"psq_lux",     XW (4,  38,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRT,RA,RB,PSWM,PSQM}},
2838 {"vmrghh",      VX (4,  76),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2839 {"psq_stux",    XW (4,  39,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRS,RA,RB,PSWM,PSQM}},
2840 {"vpkuwum",     VX (4,  78),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2841 {"ps_neg",      XRC(4,  40,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2842 {"mulhhw",      XRC(4,  40,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2843 {"ps_neg.",     XRC(4,  40,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2844 {"mulhhw.",     XRC(4,  40,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2845 {"machhw",      XO (4,  44,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2846 {"machhw.",     XO (4,  44,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2847 {"nmachhw",     XO (4,  46,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2848 {"nmachhw.",    XO (4,  46,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2849 {"ps_cmpu1",    X  (4,  64), X_MASK|(3<<21), PPCPS,     PPCNONE,        {BF, FRA, FRB}},
2850 {"vadduwm",     VX (4,  128),   VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2851 {"vmaxuw",      VX (4,  130),   VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2852 {"vrlw",        VX (4,  132),   VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2853 {"vcmpequw",    VXR(4,  134,0), VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2854 {"vmrghw",      VX (4,  140),   VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2855 {"vpkuhus",     VX (4,  142),   VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2856 {"ps_mr",       XRC(4,  72,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2857 {"ps_mr.",      XRC(4,  72,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2858 {"machhwsu",    XO (4,  76,0,0),XO_MASK,     MULHW|PPCVLE,  PPCNONE,    {RT, RA, RB}},
2859 {"machhwsu.",   XO (4,  76,0,1),XO_MASK,     MULHW|PPCVLE,  PPCNONE,    {RT, RA, RB}},
2860 {"ps_cmpo1",    X  (4,  96), X_MASK|(3<<21), PPCPS,     PPCNONE,        {BF, FRA, FRB}},
2861 {"vabsdub",     VX (4, 192),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
2862 {"vcmpeqfp",    VXR(4, 198,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2863 {"vpkuwus",     VX (4, 206),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2864 {"machhws",     XO (4, 108,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2865 {"machhws.",    XO (4, 108,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2866 {"nmachhws",    XO (4, 110,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2867 {"nmachhws.",   XO (4, 110,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2868 {"vabsduh",     VX (4, 256),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
2869 {"vmaxsb",      VX (4, 258),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2870 {"vslb",        VX (4, 260),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2871 {"vmulosb",     VX (4, 264),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2872 {"vrefp",       VX (4, 266),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
2873 {"vmrglb",      VX (4, 268),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2874 {"vpkshus",     VX (4, 270),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2875 {"ps_nabs",     XRC(4, 136,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2876 {"mulchwu",     XRC(4, 136,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2877 {"ps_nabs.",    XRC(4, 136,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2878 {"mulchwu.",    XRC(4, 136,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2879 {"macchwu",     XO (4, 140,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2880 {"macchwu.",    XO (4, 140,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2881 {"vabsduw",     VX (4, 320),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
2882 {"vmaxsh",      VX (4, 322),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2883 {"vslh",        VX (4, 324),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2884 {"vmulosh",     VX (4, 328),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2885 {"vrsqrtefp",   VX (4, 330),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
2886 {"vmrglh",      VX (4, 332),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2887 {"vpkswus",     VX (4, 334),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2888 {"mulchw",      XRC(4, 168,0),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2889 {"mulchw.",     XRC(4, 168,1),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2890 {"macchw",      XO (4, 172,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2891 {"macchw.",     XO (4, 172,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2892 {"nmacchw",     XO (4, 174,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2893 {"nmacchw.",    XO (4, 174,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2894 {"vaddcuw",     VX (4, 384),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2895 {"vmaxsw",      VX (4, 386),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2896 {"vslw",        VX (4, 388),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2897 {"vexptefp",    VX (4, 394),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
2898 {"vmrglw",      VX (4, 396),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2899 {"vpkshss",     VX (4, 398),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2900 {"macchwsu",    XO (4, 204,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2901 {"macchwsu.",   XO (4, 204,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2902 {"vsl",         VX (4, 452),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2903 {"vcmpgefp",    VXR(4, 454,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2904 {"vlogefp",     VX (4, 458),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
2905 {"vpkswss",     VX (4, 462),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2906 {"macchws",     XO (4, 236,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2907 {"macchws.",    XO (4, 236,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2908 {"nmacchws",    XO (4, 238,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2909 {"nmacchws.",   XO (4, 238,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2910 {"evaddw",      VX (4, 512),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2911 {"vaddubs",     VX (4, 512),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2912 {"evaddiw",     VX (4, 514),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB, UIMM}},
2913 {"vminub",      VX (4, 514),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2914 {"evsubfw",     VX (4, 516),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2915 {"evsubw",      VX (4, 516),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB, RA}},
2916 {"vsrb",        VX (4, 516),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2917 {"evsubifw",    VX (4, 518),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, UIMM, RB}},
2918 {"evsubiw",     VX (4, 518),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB, UIMM}},
2919 {"vcmpgtub",    VXR(4, 518,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2920 {"evabs",       VX (4, 520),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
2921 {"vmuleub",     VX (4, 520),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2922 {"evneg",       VX (4, 521),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
2923 {"evextsb",     VX (4, 522),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
2924 {"vrfin",       VX (4, 522),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
2925 {"evextsh",     VX (4, 523),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
2926 {"evrndw",      VX (4, 524),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
2927 {"vspltb",      VX (4, 524),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
2928 {"evcntlzw",    VX (4, 525),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
2929 {"evcntlsw",    VX (4, 526),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
2930 {"vupkhsb",     VX (4, 526),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
2931 {"brinc",       VX (4, 527),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2932 {"ps_abs",      XRC(4, 264,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2933 {"ps_abs.",     XRC(4, 264,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2934 {"evand",       VX (4, 529),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2935 {"evandc",      VX (4, 530),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2936 {"evxor",       VX (4, 534),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2937 {"evmr",        VX (4, 535),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, BBA}},
2938 {"evor",        VX (4, 535),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2939 {"evnor",       VX (4, 536),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2940 {"evnot",       VX (4, 536),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, BBA}},
2941 {"get",         APU(4, 268,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
2942 {"eveqv",       VX (4, 537),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2943 {"evorc",       VX (4, 539),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2944 {"evnand",      VX (4, 542),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2945 {"evsrwu",      VX (4, 544),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2946 {"evsrws",      VX (4, 545),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2947 {"evsrwiu",     VX (4, 546),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, EVUIMM}},
2948 {"evsrwis",     VX (4, 547),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, EVUIMM}},
2949 {"evslw",       VX (4, 548),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2950 {"evslwi",      VX (4, 550),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, EVUIMM}},
2951 {"evrlw",       VX (4, 552),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2952 {"evsplati",    VX (4, 553),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, SIMM}},
2953 {"evrlwi",      VX (4, 554),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, EVUIMM}},
2954 {"evsplatfi",   VX (4, 555),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, SIMM}},
2955 {"evmergehi",   VX (4, 556),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2956 {"evmergelo",   VX (4, 557),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2957 {"evmergehilo", VX (4, 558),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2958 {"evmergelohi", VX (4, 559),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2959 {"evcmpgtu",    VX (4, 560),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
2960 {"evcmpgts",    VX (4, 561),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
2961 {"evcmpltu",    VX (4, 562),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
2962 {"evcmplts",    VX (4, 563),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
2963 {"evcmpeq",     VX (4, 564),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
2964 {"cget",        APU(4, 284,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
2965 {"vadduhs",     VX (4, 576),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2966 {"vminuh",      VX (4, 578),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2967 {"vsrh",        VX (4, 580),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2968 {"vcmpgtuh",    VXR(4, 582,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2969 {"vmuleuh",     VX (4, 584),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2970 {"vrfiz",       VX (4, 586),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
2971 {"vsplth",      VX (4, 588),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
2972 {"vupkhsh",     VX (4, 590),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
2973 {"nget",        APU(4, 300,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
2974 {"evsel",       EVSEL(4,79),    EVSEL_MASK,  PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB, CRFS}},
2975 {"ncget",       APU(4, 316,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
2976 {"evfsadd",     VX (4, 640),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2977 {"vadduws",     VX (4, 640),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2978 {"evfssub",     VX (4, 641),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2979 {"vminuw",      VX (4, 642),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2980 {"evfsabs",     VX (4, 644),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
2981 {"vsrw",        VX (4, 644),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2982 {"evfsnabs",    VX (4, 645),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
2983 {"evfsneg",     VX (4, 646),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
2984 {"vcmpgtuw",    VXR(4, 646,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2985 {"evfsmul",     VX (4, 648),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2986 {"evfsdiv",     VX (4, 649),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2987 {"vrfip",       VX (4, 650),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
2988 {"evfscmpgt",   VX (4, 652),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
2989 {"vspltw",      VX (4, 652),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
2990 {"evfscmplt",   VX (4, 653),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
2991 {"evfscmpeq",   VX (4, 654),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
2992 {"vupklsb",     VX (4, 654),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
2993 {"evfscfui",    VX (4, 656),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
2994 {"evfscfsi",    VX (4, 657),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
2995 {"evfscfuf",    VX (4, 658),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
2996 {"evfscfsf",    VX (4, 659),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
2997 {"evfsctui",    VX (4, 660),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
2998 {"evfsctsi",    VX (4, 661),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
2999 {"evfsctuf",    VX (4, 662),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3000 {"evfsctsf",    VX (4, 663),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3001 {"evfsctuiz",   VX (4, 664),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3002 {"put",         APU(4, 332,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
3003 {"evfsctsiz",   VX (4, 666),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3004 {"evfststgt",   VX (4, 668),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3005 {"evfststlt",   VX (4, 669),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3006 {"evfststeq",   VX (4, 670),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3007 {"cput",        APU(4, 348,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
3008 {"efsadd",      VX (4, 704),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3009 {"efssub",      VX (4, 705),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3010 {"efsabs",      VX (4, 708),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA}},
3011 {"vsr",         VX (4, 708),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3012 {"efsnabs",     VX (4, 709),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA}},
3013 {"efsneg",      VX (4, 710),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA}},
3014 {"vcmpgtfp",    VXR(4, 710,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3015 {"efsmul",      VX (4, 712),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3016 {"efsdiv",      VX (4, 713),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3017 {"vrfim",       VX (4, 714),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3018 {"efscmpgt",    VX (4, 716),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3019 {"efscmplt",    VX (4, 717),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3020 {"efscmpeq",    VX (4, 718),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3021 {"vupklsh",     VX (4, 718),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3022 {"efscfd",      VX (4, 719),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3023 {"efscfui",     VX (4, 720),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3024 {"efscfsi",     VX (4, 721),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3025 {"efscfuf",     VX (4, 722),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3026 {"efscfsf",     VX (4, 723),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3027 {"efsctui",     VX (4, 724),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3028 {"efsctsi",     VX (4, 725),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3029 {"efsctuf",     VX (4, 726),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3030 {"efsctsf",     VX (4, 727),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3031 {"efsctuiz",    VX (4, 728),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3032 {"nput",        APU(4, 364,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
3033 {"efsctsiz",    VX (4, 730),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3034 {"efststgt",    VX (4, 732),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3035 {"efststlt",    VX (4, 733),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3036 {"efststeq",    VX (4, 734),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3037 {"efdadd",      VX (4, 736),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3038 {"efdsub",      VX (4, 737),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3039 {"efdcfuid",    VX (4, 738),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3040 {"efdcfsid",    VX (4, 739),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3041 {"efdabs",      VX (4, 740),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA}},
3042 {"efdnabs",     VX (4, 741),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA}},
3043 {"efdneg",      VX (4, 742),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA}},
3044 {"efdmul",      VX (4, 744),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3045 {"efddiv",      VX (4, 745),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3046 {"efdctuidz",   VX (4, 746),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3047 {"efdctsidz",   VX (4, 747),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3048 {"efdcmpgt",    VX (4, 748),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3049 {"efdcmplt",    VX (4, 749),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3050 {"efdcmpeq",    VX (4, 750),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3051 {"efdcfs",      VX (4, 751),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3052 {"efdcfui",     VX (4, 752),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3053 {"efdcfsi",     VX (4, 753),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3054 {"efdcfuf",     VX (4, 754),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3055 {"efdcfsf",     VX (4, 755),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3056 {"efdctui",     VX (4, 756),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3057 {"efdctsi",     VX (4, 757),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3058 {"efdctuf",     VX (4, 758),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3059 {"efdctsf",     VX (4, 759),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3060 {"efdctuiz",    VX (4, 760),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3061 {"ncput",       APU(4, 380,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
3062 {"efdctsiz",    VX (4, 762),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3063 {"efdtstgt",    VX (4, 764),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3064 {"efdtstlt",    VX (4, 765),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3065 {"efdtsteq",    VX (4, 766),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3066 {"evlddx",      VX (4, 768),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3067 {"vaddsbs",     VX (4, 768),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3068 {"evldd",       VX (4, 769),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_8, RA}},
3069 {"evldwx",      VX (4, 770),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3070 {"vminsb",      VX (4, 770),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3071 {"evldw",       VX (4, 771),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_8, RA}},
3072 {"evldhx",      VX (4, 772),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3073 {"vsrab",       VX (4, 772),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3074 {"evldh",       VX (4, 773),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_8, RA}},
3075 {"vcmpgtsb",    VXR(4, 774,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3076 {"evlhhesplatx",VX (4, 776),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3077 {"vmulesb",     VX (4, 776),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3078 {"evlhhesplat", VX (4, 777),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_2, RA}},
3079 {"vcfux",       VX (4, 778),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
3080 {"evlhhousplatx",VX(4, 780),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3081 {"vspltisb",    VX (4, 780),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, SIMM}},
3082 {"evlhhousplat",VX (4, 781),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_2, RA}},
3083 {"evlhhossplatx",VX(4, 782),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3084 {"vpkpx",       VX (4, 782),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3085 {"evlhhossplat",VX (4, 783),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_2, RA}},
3086 {"mullhwu",     XRC(4, 392,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3087 {"evlwhex",     VX (4, 784),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3088 {"mullhwu.",    XRC(4, 392,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3089 {"evlwhe",      VX (4, 785),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3090 {"evlwhoux",    VX (4, 788),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3091 {"evlwhou",     VX (4, 789),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3092 {"evlwhosx",    VX (4, 790),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3093 {"evlwhos",     VX (4, 791),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3094 {"maclhwu",     XO (4, 396,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3095 {"evlwwsplatx", VX (4, 792),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3096 {"maclhwu.",    XO (4, 396,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3097 {"evlwwsplat",  VX (4, 793),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3098 {"evlwhsplatx", VX (4, 796),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3099 {"evlwhsplat",  VX (4, 797),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3100 {"evstddx",     VX (4, 800),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3101 {"evstdd",      VX (4, 801),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_8, RA}},
3102 {"evstdwx",     VX (4, 802),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3103 {"evstdw",      VX (4, 803),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_8, RA}},
3104 {"evstdhx",     VX (4, 804),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3105 {"evstdh",      VX (4, 805),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_8, RA}},
3106 {"evstwhex",    VX (4, 816),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3107 {"evstwhe",     VX (4, 817),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3108 {"evstwhox",    VX (4, 820),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3109 {"evstwho",     VX (4, 821),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3110 {"evstwwex",    VX (4, 824),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3111 {"evstwwe",     VX (4, 825),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3112 {"evstwwox",    VX (4, 828),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3113 {"evstwwo",     VX (4, 829),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3114 {"vaddshs",     VX (4, 832),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3115 {"vminsh",      VX (4, 834),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3116 {"vsrah",       VX (4, 836),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3117 {"vcmpgtsh",    VXR(4, 838,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3118 {"vmulesh",     VX (4, 840),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3119 {"vcfsx",       VX (4, 842),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
3120 {"vspltish",    VX (4, 844),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, SIMM}},
3121 {"vupkhpx",     VX (4, 846),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3122 {"mullhw",      XRC(4, 424,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3123 {"mullhw.",     XRC(4, 424,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3124 {"maclhw",      XO (4, 428,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3125 {"maclhw.",     XO (4, 428,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3126 {"nmaclhw",     XO (4, 430,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3127 {"nmaclhw.",    XO (4, 430,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3128 {"vaddsws",     VX (4, 896),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3129 {"vminsw",      VX (4, 898),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3130 {"vsraw",       VX (4, 900),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3131 {"vcmpgtsw",    VXR(4, 902,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3132 {"vctuxs",      VX (4, 906),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
3133 {"vspltisw",    VX (4, 908),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, SIMM}},
3134 {"maclhwsu",    XO (4, 460,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3135 {"maclhwsu.",   XO (4, 460,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3136 {"vcmpbfp",     VXR(4, 966,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3137 {"vctsxs",      VX (4, 970),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
3138 {"vupklpx",     VX (4, 974),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3139 {"maclhws",     XO (4, 492,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3140 {"maclhws.",    XO (4, 492,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3141 {"nmaclhws",    XO (4, 494,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3142 {"nmaclhws.",   XO (4, 494,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3143 {"vsububm",     VX (4,1024),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3144 {"vavgub",      VX (4,1026),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3145 {"evmhessf",    VX (4,1027),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3146 {"vand",        VX (4,1028),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3147 {"vcmpequb.",   VXR(4,   6,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3148 {"udi0fcm.",    APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3149 {"udi0fcm",     APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3150 {"evmhossf",    VX (4,1031),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3151 {"evmheumi",    VX (4,1032),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3152 {"evmhesmi",    VX (4,1033),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3153 {"vmaxfp",      VX (4,1034),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3154 {"evmhesmf",    VX (4,1035),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3155 {"evmhoumi",    VX (4,1036),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3156 {"vslo",        VX (4,1036),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3157 {"evmhosmi",    VX (4,1037),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3158 {"evmhosmf",    VX (4,1039),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3159 {"machhwuo",    XO (4,  12,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3160 {"machhwuo.",   XO (4,  12,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3161 {"ps_merge00",  XOPS(4,528,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3162 {"ps_merge00.", XOPS(4,528,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3163 {"evmhessfa",   VX (4,1059),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3164 {"evmhossfa",   VX (4,1063),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3165 {"evmheumia",   VX (4,1064),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3166 {"evmhesmia",   VX (4,1065),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3167 {"evmhesmfa",   VX (4,1067),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3168 {"evmhoumia",   VX (4,1068),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3169 {"evmhosmia",   VX (4,1069),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3170 {"evmhosmfa",   VX (4,1071),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3171 {"vsubuhm",     VX (4,1088),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3172 {"vavguh",      VX (4,1090),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3173 {"vandc",       VX (4,1092),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3174 {"vcmpequh.",   VXR(4,  70,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3175 {"udi1fcm.",    APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3176 {"udi1fcm",     APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3177 {"evmwhssf",    VX (4,1095),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3178 {"evmwlumi",    VX (4,1096),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3179 {"vminfp",      VX (4,1098),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3180 {"evmwhumi",    VX (4,1100),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3181 {"vsro",        VX (4,1100),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3182 {"evmwhsmi",    VX (4,1101),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3183 {"evmwhsmf",    VX (4,1103),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3184 {"evmwssf",     VX (4,1107),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3185 {"machhwo",     XO (4,  44,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3186 {"evmwumi",     VX (4,1112),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3187 {"machhwo.",    XO (4,  44,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3188 {"evmwsmi",     VX (4,1113),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3189 {"evmwsmf",     VX (4,1115),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3190 {"nmachhwo",    XO (4,  46,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3191 {"nmachhwo.",   XO (4,  46,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3192 {"ps_merge01",  XOPS(4,560,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3193 {"ps_merge01.", XOPS(4,560,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3194 {"evmwhssfa",   VX (4,1127),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3195 {"evmwlumia",   VX (4,1128),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3196 {"evmwhumia",   VX (4,1132),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3197 {"evmwhsmia",   VX (4,1133),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3198 {"evmwhsmfa",   VX (4,1135),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3199 {"evmwssfa",    VX (4,1139),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3200 {"evmwumia",    VX (4,1144),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3201 {"evmwsmia",    VX (4,1145),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3202 {"evmwsmfa",    VX (4,1147),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3203 {"vsubuwm",     VX (4,1152),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3204 {"vavguw",      VX (4,1154),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3205 {"vor",         VX (4,1156),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3206 {"vcmpequw.",   VXR(4, 134,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3207 {"udi2fcm.",    APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3208 {"udi2fcm",     APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3209 {"machhwsuo",   XO (4,  76,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3210 {"machhwsuo.",  XO (4,  76,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3211 {"ps_merge10",  XOPS(4,592,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3212 {"ps_merge10.", XOPS(4,592,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3213 {"evaddusiaaw", VX (4,1216),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3214 {"evaddssiaaw", VX (4,1217),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3215 {"evsubfusiaaw",VX (4,1218),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3216 {"evsubfssiaaw",VX (4,1219),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3217 {"evmra",       VX (4,1220),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3218 {"vxor",        VX (4,1220),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3219 {"evdivws",     VX (4,1222),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3220 {"vcmpeqfp.",   VXR(4, 198,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3221 {"udi3fcm.",    APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3222 {"udi3fcm",     APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3223 {"evdivwu",     VX (4,1223),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3224 {"evaddumiaaw", VX (4,1224),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3225 {"evaddsmiaaw", VX (4,1225),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3226 {"evsubfumiaaw",VX (4,1226),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3227 {"evsubfsmiaaw",VX (4,1227),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3228 {"machhwso",    XO (4, 108,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3229 {"machhwso.",   XO (4, 108,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3230 {"nmachhwso",   XO (4, 110,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3231 {"nmachhwso.",  XO (4, 110,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3232 {"ps_merge11",  XOPS(4,624,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3233 {"ps_merge11.", XOPS(4,624,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3234 {"evmheusiaaw", VX (4,1280),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3235 {"evmhessiaaw", VX (4,1281),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3236 {"vavgsb",      VX (4,1282),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3237 {"evmhessfaaw", VX (4,1283),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3238 {"evmhousiaaw", VX (4,1284),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3239 {"vnor",        VX (4,1284),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3240 {"evmhossiaaw", VX (4,1285),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3241 {"udi4fcm.",    APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3242 {"udi4fcm",     APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3243 {"evmhossfaaw", VX (4,1287),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3244 {"evmheumiaaw", VX (4,1288),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3245 {"evmhesmiaaw", VX (4,1289),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3246 {"evmhesmfaaw", VX (4,1291),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3247 {"evmhoumiaaw", VX (4,1292),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3248 {"evmhosmiaaw", VX (4,1293),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3249 {"evmhosmfaaw", VX (4,1295),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3250 {"macchwuo",    XO (4, 140,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3251 {"macchwuo.",   XO (4, 140,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3252 {"evmhegumiaa", VX (4,1320),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3253 {"evmhegsmiaa", VX (4,1321),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3254 {"evmhegsmfaa", VX (4,1323),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3255 {"evmhogumiaa", VX (4,1324),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3256 {"evmhogsmiaa", VX (4,1325),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3257 {"evmhogsmfaa", VX (4,1327),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3258 {"evmwlusiaaw", VX (4,1344),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3259 {"evmwlssiaaw", VX (4,1345),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3260 {"vavgsh",      VX (4,1346),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3261 {"udi5fcm.",    APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3262 {"udi5fcm",     APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3263 {"evmwlumiaaw", VX (4,1352),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3264 {"evmwlsmiaaw", VX (4,1353),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3265 {"evmwssfaa",   VX (4,1363),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3266 {"macchwo",     XO (4, 172,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3267 {"evmwumiaa",   VX (4,1368),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3268 {"macchwo.",    XO (4, 172,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3269 {"evmwsmiaa",   VX (4,1369),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3270 {"evmwsmfaa",   VX (4,1371),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3271 {"nmacchwo",    XO (4, 174,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3272 {"nmacchwo.",   XO (4, 174,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3273 {"evmheusianw", VX (4,1408),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3274 {"vsubcuw",     VX (4,1408),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3275 {"evmhessianw", VX (4,1409),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3276 {"vavgsw",      VX (4,1410),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3277 {"evmhessfanw", VX (4,1411),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3278 {"evmhousianw", VX (4,1412),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3279 {"evmhossianw", VX (4,1413),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3280 {"udi6fcm.",    APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3281 {"udi6fcm",     APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3282 {"evmhossfanw", VX (4,1415),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3283 {"evmheumianw", VX (4,1416),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3284 {"evmhesmianw", VX (4,1417),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3285 {"evmhesmfanw", VX (4,1419),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3286 {"evmhoumianw", VX (4,1420),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3287 {"evmhosmianw", VX (4,1421),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3288 {"evmhosmfanw", VX (4,1423),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3289 {"macchwsuo",   XO (4, 204,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3290 {"macchwsuo.",  XO (4, 204,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3291 {"evmhegumian", VX (4,1448),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3292 {"evmhegsmian", VX (4,1449),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3293 {"evmhegsmfan", VX (4,1451),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3294 {"evmhogumian", VX (4,1452),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3295 {"evmhogsmian", VX (4,1453),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3296 {"evmhogsmfan", VX (4,1455),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3297 {"evmwlusianw", VX (4,1472),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3298 {"evmwlssianw", VX (4,1473),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3299 {"vcmpgefp.",   VXR(4, 454,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3300 {"udi7fcm.",    APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3301 {"udi7fcm",     APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3302 {"evmwlumianw", VX (4,1480),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3303 {"evmwlsmianw", VX (4,1481),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3304 {"evmwssfan",   VX (4,1491),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3305 {"macchwso",    XO (4, 236,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3306 {"evmwumian",   VX (4,1496),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3307 {"macchwso.",   XO (4, 236,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3308 {"evmwsmian",   VX (4,1497),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3309 {"evmwsmfan",   VX (4,1499),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3310 {"nmacchwso",   XO (4, 238,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3311 {"nmacchwso.",  XO (4, 238,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3312 {"vsububs",     VX (4,1536),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3313 {"mfvscr",      VX (4,1540),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD}},
3314 {"vcmpgtub.",   VXR(4, 518,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3315 {"udi8fcm.",    APU(4, 771,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3316 {"udi8fcm",     APU(4, 771,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3317 {"vsum4ubs",    VX (4,1544),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3318 {"vsubuhs",     VX (4,1600),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3319 {"mtvscr",      VX (4,1604),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VB}},
3320 {"vcmpgtuh.",   VXR(4, 582,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3321 {"vsum4shs",    VX (4,1608),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3322 {"udi9fcm.",    APU(4, 804,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3323 {"udi9fcm",     APU(4, 804,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3324 {"vsubuws",     VX (4,1664),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3325 {"vcmpgtuw.",   VXR(4, 646,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3326 {"udi10fcm.",   APU(4, 835,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3327 {"udi10fcm",    APU(4, 835,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3328 {"vsum2sws",    VX (4,1672),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3329 {"vcmpgtfp.",   VXR(4, 710,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3330 {"udi11fcm.",   APU(4, 867,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3331 {"udi11fcm",    APU(4, 867,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3332 {"vsubsbs",     VX (4,1792),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3333 {"vcmpgtsb.",   VXR(4, 774,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3334 {"udi12fcm.",   APU(4, 899,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3335 {"udi12fcm",    APU(4, 899,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3336 {"vsum4sbs",    VX (4,1800),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3337 {"maclhwuo",    XO (4, 396,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3338 {"maclhwuo.",   XO (4, 396,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3339 {"vsubshs",     VX (4,1856),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3340 {"vcmpgtsh.",   VXR(4, 838,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3341 {"udi13fcm.",   APU(4, 931,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3342 {"udi13fcm",    APU(4, 931,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3343 {"maclhwo",     XO (4, 428,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3344 {"maclhwo.",    XO (4, 428,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3345 {"nmaclhwo",    XO (4, 430,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3346 {"nmaclhwo.",   XO (4, 430,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3347 {"vsubsws",     VX (4,1920),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3348 {"vcmpgtsw.",   VXR(4, 902,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3349 {"udi14fcm.",   APU(4, 963,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3350 {"udi14fcm",    APU(4, 963,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3351 {"vsumsws",     VX (4,1928),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3352 {"maclhwsuo",   XO (4, 460,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3353 {"maclhwsuo.",  XO (4, 460,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3354 {"vcmpbfp.",    VXR(4, 966,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
3355 {"udi15fcm.",   APU(4, 995,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3356 {"udi15fcm",    APU(4, 995,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3357 {"maclhwso",    XO (4, 492,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3358 {"maclhwso.",   XO (4, 492,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3359 {"nmaclhwso",   XO (4, 494,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3360 {"nmaclhwso.",  XO (4, 494,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3361 {"dcbz_l",      X  (4,1014),    XRT_MASK,    PPCPS,     PPCNONE,        {RA, RB}},
3362
3363 {"mulli",       OP(7),          OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
3364 {"muli",        OP(7),          OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
3365
3366 {"subfic",      OP(8),          OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
3367 {"sfi",         OP(8),          OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
3368
3369 {"dozi",        OP(9),          OP_MASK,     M601,      PPCNONE,        {RT, RA, SI}},
3370
3371 {"cmplwi",      OPL(10,0),      OPL_MASK,    PPCCOM,    PPCNONE,        {OBF, RA, UI}},
3372 {"cmpldi",      OPL(10,1),      OPL_MASK,    PPC64,     PPCNONE,        {OBF, RA, UI}},
3373 {"cmpli",       OP(10),         OP_MASK,     PPC,       PPCNONE,        {BF, L, RA, UI}},
3374 {"cmpli",       OP(10),         OP_MASK,     PWRCOM,    PPC,            {BF, RA, UI}},
3375
3376 {"cmpwi",       OPL(11,0),      OPL_MASK,    PPCCOM,    PPCNONE,        {OBF, RA, SI}},
3377 {"cmpdi",       OPL(11,1),      OPL_MASK,    PPC64,     PPCNONE,        {OBF, RA, SI}},
3378 {"cmpi",        OP(11),         OP_MASK,     PPC,       PPCNONE,        {BF, L, RA, SI}},
3379 {"cmpi",        OP(11),         OP_MASK,     PWRCOM,    PPC,            {BF, RA, SI}},
3380
3381 {"addic",       OP(12),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
3382 {"ai",          OP(12),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
3383 {"subic",       OP(12),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, NSI}},
3384
3385 {"addic.",      OP(13),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
3386 {"ai.",         OP(13),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
3387 {"subic.",      OP(13),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, NSI}},
3388
3389 {"li",          OP(14),         DRA_MASK,    PPCCOM,    PPCNONE,        {RT, SI}},
3390 {"lil",         OP(14),         DRA_MASK,    PWRCOM,    PPCNONE,        {RT, SI}},
3391 {"addi",        OP(14),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, SI}},
3392 {"cal",         OP(14),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
3393 {"subi",        OP(14),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, NSI}},
3394 {"la",          OP(14),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RA0}},
3395
3396 {"lis",         OP(15),         DRA_MASK,    PPCCOM,    PPCNONE,        {RT, SISIGNOPT}},
3397 {"liu",         OP(15),         DRA_MASK,    PWRCOM,    PPCNONE,        {RT, SISIGNOPT}},
3398 {"addis",       OP(15),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, SISIGNOPT}},
3399 {"cau",         OP(15),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA0, SISIGNOPT}},
3400 {"subis",       OP(15),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, NSI}},
3401
3402 {"bdnz-",    BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
3403 {"bdnz+",    BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
3404 {"bdnz",     BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BD}},
3405 {"bdn",      BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BD}},
3406 {"bdnzl-",   BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
3407 {"bdnzl+",   BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
3408 {"bdnzl",    BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BD}},
3409 {"bdnl",     BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BD}},
3410 {"bdnza-",   BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
3411 {"bdnza+",   BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
3412 {"bdnza",    BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDA}},
3413 {"bdna",     BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BDA}},
3414 {"bdnzla-",  BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
3415 {"bdnzla+",  BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
3416 {"bdnzla",   BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDA}},
3417 {"bdnla",    BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BDA}},
3418 {"bdz-",     BBO(16,BODZ,0,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
3419 {"bdz+",     BBO(16,BODZ,0,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
3420 {"bdz",      BBO(16,BODZ,0,0),          BBOATBI_MASK,  COM,      PPCNONE,       {BD}},
3421 {"bdzl-",    BBO(16,BODZ,0,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
3422 {"bdzl+",    BBO(16,BODZ,0,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
3423 {"bdzl",     BBO(16,BODZ,0,1),          BBOATBI_MASK,  COM,      PPCNONE,       {BD}},
3424 {"bdza-",    BBO(16,BODZ,1,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
3425 {"bdza+",    BBO(16,BODZ,1,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
3426 {"bdza",     BBO(16,BODZ,1,0),          BBOATBI_MASK,  COM,      PPCNONE,       {BDA}},
3427 {"bdzla-",   BBO(16,BODZ,1,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
3428 {"bdzla+",   BBO(16,BODZ,1,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
3429 {"bdzla",    BBO(16,BODZ,1,1),          BBOATBI_MASK,  COM,      PPCNONE,       {BDA}},
3430
3431 {"bge-",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3432 {"bge+",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3433 {"bge",      BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3434 {"bnl-",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3435 {"bnl+",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3436 {"bnl",      BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3437 {"bgel-",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3438 {"bgel+",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3439 {"bgel",     BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3440 {"bnll-",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3441 {"bnll+",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3442 {"bnll",     BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3443 {"bgea-",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3444 {"bgea+",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3445 {"bgea",     BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3446 {"bnla-",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3447 {"bnla+",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3448 {"bnla",     BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3449 {"bgela-",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3450 {"bgela+",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3451 {"bgela",    BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3452 {"bnlla-",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3453 {"bnlla+",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3454 {"bnlla",    BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3455 {"ble-",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3456 {"ble+",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3457 {"ble",      BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3458 {"bng-",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3459 {"bng+",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3460 {"bng",      BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3461 {"blel-",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3462 {"blel+",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3463 {"blel",     BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3464 {"bngl-",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3465 {"bngl+",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3466 {"bngl",     BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3467 {"blea-",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3468 {"blea+",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3469 {"blea",     BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3470 {"bnga-",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3471 {"bnga+",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3472 {"bnga",     BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3473 {"blela-",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3474 {"blela+",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3475 {"blela",    BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3476 {"bngla-",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3477 {"bngla+",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3478 {"bngla",    BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3479 {"bne-",     BBOCB(16,BOF,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3480 {"bne+",     BBOCB(16,BOF,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3481 {"bne",      BBOCB(16,BOF,CBEQ,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3482 {"bnel-",    BBOCB(16,BOF,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3483 {"bnel+",    BBOCB(16,BOF,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3484 {"bnel",     BBOCB(16,BOF,CBEQ,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3485 {"bnea-",    BBOCB(16,BOF,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3486 {"bnea+",    BBOCB(16,BOF,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3487 {"bnea",     BBOCB(16,BOF,CBEQ,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3488 {"bnela-",   BBOCB(16,BOF,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3489 {"bnela+",   BBOCB(16,BOF,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3490 {"bnela",    BBOCB(16,BOF,CBEQ,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3491 {"bns-",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3492 {"bns+",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3493 {"bns",      BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3494 {"bnu-",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3495 {"bnu+",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3496 {"bnu",      BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
3497 {"bnsl-",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3498 {"bnsl+",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3499 {"bnsl",     BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3500 {"bnul-",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3501 {"bnul+",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3502 {"bnul",     BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
3503 {"bnsa-",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3504 {"bnsa+",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3505 {"bnsa",     BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3506 {"bnua-",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3507 {"bnua+",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3508 {"bnua",     BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
3509 {"bnsla-",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3510 {"bnsla+",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3511 {"bnsla",    BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3512 {"bnula-",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3513 {"bnula+",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3514 {"bnula",    BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
3515
3516 {"blt-",     BBOCB(16,BOT,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3517 {"blt+",     BBOCB(16,BOT,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3518 {"blt",      BBOCB(16,BOT,CBLT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3519 {"bltl-",    BBOCB(16,BOT,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3520 {"bltl+",    BBOCB(16,BOT,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3521 {"bltl",     BBOCB(16,BOT,CBLT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3522 {"blta-",    BBOCB(16,BOT,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3523 {"blta+",    BBOCB(16,BOT,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3524 {"blta",     BBOCB(16,BOT,CBLT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3525 {"bltla-",   BBOCB(16,BOT,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3526 {"bltla+",   BBOCB(16,BOT,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3527 {"bltla",    BBOCB(16,BOT,CBLT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3528 {"bgt-",     BBOCB(16,BOT,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3529 {"bgt+",     BBOCB(16,BOT,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3530 {"bgt",      BBOCB(16,BOT,CBGT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3531 {"bgtl-",    BBOCB(16,BOT,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3532 {"bgtl+",    BBOCB(16,BOT,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3533 {"bgtl",     BBOCB(16,BOT,CBGT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3534 {"bgta-",    BBOCB(16,BOT,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3535 {"bgta+",    BBOCB(16,BOT,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3536 {"bgta",     BBOCB(16,BOT,CBGT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3537 {"bgtla-",   BBOCB(16,BOT,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3538 {"bgtla+",   BBOCB(16,BOT,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3539 {"bgtla",    BBOCB(16,BOT,CBGT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3540 {"beq-",     BBOCB(16,BOT,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3541 {"beq+",     BBOCB(16,BOT,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3542 {"beq",      BBOCB(16,BOT,CBEQ,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3543 {"beql-",    BBOCB(16,BOT,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3544 {"beql+",    BBOCB(16,BOT,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3545 {"beql",     BBOCB(16,BOT,CBEQ,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3546 {"beqa-",    BBOCB(16,BOT,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3547 {"beqa+",    BBOCB(16,BOT,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3548 {"beqa",     BBOCB(16,BOT,CBEQ,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3549 {"beqla-",   BBOCB(16,BOT,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3550 {"beqla+",   BBOCB(16,BOT,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3551 {"beqla",    BBOCB(16,BOT,CBEQ,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3552 {"bso-",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3553 {"bso+",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3554 {"bso",      BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3555 {"bun-",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3556 {"bun+",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3557 {"bun",      BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
3558 {"bsol-",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3559 {"bsol+",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3560 {"bsol",     BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3561 {"bunl-",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3562 {"bunl+",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3563 {"bunl",     BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
3564 {"bsoa-",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3565 {"bsoa+",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3566 {"bsoa",     BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3567 {"buna-",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3568 {"buna+",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3569 {"buna",     BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
3570 {"bsola-",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3571 {"bsola+",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3572 {"bsola",    BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3573 {"bunla-",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3574 {"bunla+",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3575 {"bunla",    BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
3576
3577 {"bdnzf-",   BBO(16,BODNZF,0,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
3578 {"bdnzf+",   BBO(16,BODNZF,0,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
3579 {"bdnzf",    BBO(16,BODNZF,0,0),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
3580 {"bdnzfl-",  BBO(16,BODNZF,0,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
3581 {"bdnzfl+",  BBO(16,BODNZF,0,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
3582 {"bdnzfl",   BBO(16,BODNZF,0,1),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
3583 {"bdnzfa-",  BBO(16,BODNZF,1,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
3584 {"bdnzfa+",  BBO(16,BODNZF,1,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
3585 {"bdnzfa",   BBO(16,BODNZF,1,0),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
3586 {"bdnzfla-", BBO(16,BODNZF,1,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
3587 {"bdnzfla+", BBO(16,BODNZF,1,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
3588 {"bdnzfla",  BBO(16,BODNZF,1,1),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
3589 {"bdzf-",    BBO(16,BODZF,0,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
3590 {"bdzf+",    BBO(16,BODZF,0,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
3591 {"bdzf",     BBO(16,BODZF,0,0),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
3592 {"bdzfl-",   BBO(16,BODZF,0,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
3593 {"bdzfl+",   BBO(16,BODZF,0,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
3594 {"bdzfl",    BBO(16,BODZF,0,1),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
3595 {"bdzfa-",   BBO(16,BODZF,1,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
3596 {"bdzfa+",   BBO(16,BODZF,1,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
3597 {"bdzfa",    BBO(16,BODZF,1,0),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
3598 {"bdzfla-",  BBO(16,BODZF,1,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
3599 {"bdzfla+",  BBO(16,BODZF,1,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
3600 {"bdzfla",   BBO(16,BODZF,1,1),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
3601
3602 {"bf-",      BBO(16,BOF,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
3603 {"bf+",      BBO(16,BOF,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
3604 {"bf",       BBO(16,BOF,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
3605 {"bbf",      BBO(16,BOF,0,0),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
3606 {"bfl-",     BBO(16,BOF,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
3607 {"bfl+",     BBO(16,BOF,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
3608 {"bfl",      BBO(16,BOF,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
3609 {"bbfl",     BBO(16,BOF,0,1),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
3610 {"bfa-",     BBO(16,BOF,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
3611 {"bfa+",     BBO(16,BOF,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
3612 {"bfa",      BBO(16,BOF,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
3613 {"bbfa",     BBO(16,BOF,1,0),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
3614 {"bfla-",    BBO(16,BOF,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
3615 {"bfla+",    BBO(16,BOF,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
3616 {"bfla",     BBO(16,BOF,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
3617 {"bbfla",    BBO(16,BOF,1,1),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
3618
3619 {"bdnzt-",   BBO(16,BODNZT,0,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
3620 {"bdnzt+",   BBO(16,BODNZT,0,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
3621 {"bdnzt",    BBO(16,BODNZT,0,0),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
3622 {"bdnztl-",  BBO(16,BODNZT,0,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
3623 {"bdnztl+",  BBO(16,BODNZT,0,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
3624 {"bdnztl",   BBO(16,BODNZT,0,1),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
3625 {"bdnzta-",  BBO(16,BODNZT,1,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
3626 {"bdnzta+",  BBO(16,BODNZT,1,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
3627 {"bdnzta",   BBO(16,BODNZT,1,0),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
3628 {"bdnztla-", BBO(16,BODNZT,1,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
3629 {"bdnztla+", BBO(16,BODNZT,1,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
3630 {"bdnztla",  BBO(16,BODNZT,1,1),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
3631 {"bdzt-",    BBO(16,BODZT,0,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
3632 {"bdzt+",    BBO(16,BODZT,0,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
3633 {"bdzt",     BBO(16,BODZT,0,0),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
3634 {"bdztl-",   BBO(16,BODZT,0,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
3635 {"bdztl+",   BBO(16,BODZT,0,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
3636 {"bdztl",    BBO(16,BODZT,0,1),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
3637 {"bdzta-",   BBO(16,BODZT,1,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
3638 {"bdzta+",   BBO(16,BODZT,1,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
3639 {"bdzta",    BBO(16,BODZT,1,0),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
3640 {"bdztla-",  BBO(16,BODZT,1,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
3641 {"bdztla+",  BBO(16,BODZT,1,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
3642 {"bdztla",   BBO(16,BODZT,1,1),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
3643
3644 {"bt-",      BBO(16,BOT,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
3645 {"bt+",      BBO(16,BOT,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
3646 {"bt",       BBO(16,BOT,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
3647 {"bbt",      BBO(16,BOT,0,0),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
3648 {"btl-",     BBO(16,BOT,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
3649 {"btl+",     BBO(16,BOT,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
3650 {"btl",      BBO(16,BOT,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
3651 {"bbtl",     BBO(16,BOT,0,1),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
3652 {"bta-",     BBO(16,BOT,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
3653 {"bta+",     BBO(16,BOT,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
3654 {"bta",      BBO(16,BOT,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
3655 {"bbta",     BBO(16,BOT,1,0),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
3656 {"btla-",    BBO(16,BOT,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
3657 {"btla+",    BBO(16,BOT,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
3658 {"btla",     BBO(16,BOT,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
3659 {"bbtla",    BBO(16,BOT,1,1),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
3660
3661 {"bc-",         B(16,0,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDM}},
3662 {"bc+",         B(16,0,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDP}},
3663 {"bc",          B(16,0,0),      B_MASK,      COM,       PPCNONE,        {BO, BI, BD}},
3664 {"bcl-",        B(16,0,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDM}},
3665 {"bcl+",        B(16,0,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDP}},
3666 {"bcl",         B(16,0,1),      B_MASK,      COM,       PPCNONE,        {BO, BI, BD}},
3667 {"bca-",        B(16,1,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDMA}},
3668 {"bca+",        B(16,1,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDPA}},
3669 {"bca",         B(16,1,0),      B_MASK,      COM,       PPCNONE,        {BO, BI, BDA}},
3670 {"bcla-",       B(16,1,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDMA}},
3671 {"bcla+",       B(16,1,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDPA}},
3672 {"bcla",        B(16,1,1),      B_MASK,      COM,       PPCNONE,        {BO, BI, BDA}},
3673
3674 {"svc",         SC(17,0,0),     SC_MASK,     POWER,     PPCNONE,        {SVC_LEV, FL1, FL2}},
3675 {"svcl",        SC(17,0,1),     SC_MASK,     POWER,     PPCNONE,        {SVC_LEV, FL1, FL2}},
3676 {"sc",          SC(17,1,0),     SC_MASK,     PPC,       PPCNONE,        {LEV}},
3677 {"svca",        SC(17,1,0),     SC_MASK,     PWRCOM,    PPCNONE,        {SV}},
3678 {"svcla",       SC(17,1,1),     SC_MASK,     POWER,     PPCNONE,        {SV}},
3679
3680 {"b",           B(18,0,0),      B_MASK,      COM,       PPCNONE,        {LI}},
3681 {"bl",          B(18,0,1),      B_MASK,      COM,       PPCNONE,        {LI}},
3682 {"ba",          B(18,1,0),      B_MASK,      COM,       PPCNONE,        {LIA}},
3683 {"bla",         B(18,1,1),      B_MASK,      COM,       PPCNONE,        {LIA}},
3684
3685 {"mcrf",      XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCNONE,        {BF, BFA}},
3686
3687 {"bdnzlr",   XLO(19,BODNZ,16,0),        XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
3688 {"bdnzlr-",  XLO(19,BODNZ,16,0),        XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
3689 {"bdnzlrl",  XLO(19,BODNZ,16,1),        XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
3690 {"bdnzlrl-", XLO(19,BODNZ,16,1),        XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
3691 {"bdnzlr+",  XLO(19,BODNZP,16,0),       XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
3692 {"bdnzlrl+", XLO(19,BODNZP,16,1),       XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
3693 {"bdzlr",    XLO(19,BODZ,16,0),         XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
3694 {"bdzlr-",   XLO(19,BODZ,16,0),         XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
3695 {"bdzlrl",   XLO(19,BODZ,16,1),         XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
3696 {"bdzlrl-",  XLO(19,BODZ,16,1),         XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
3697 {"bdzlr+",   XLO(19,BODZP,16,0),        XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
3698 {"bdzlrl+",  XLO(19,BODZP,16,1),        XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
3699 {"blr",      XLO(19,BOU,16,0),          XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
3700 {"br",       XLO(19,BOU,16,0),          XLBOBIBB_MASK, PWRCOM,   PPCNONE,       {0}},
3701 {"blrl",     XLO(19,BOU,16,1),          XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
3702 {"brl",      XLO(19,BOU,16,1),          XLBOBIBB_MASK, PWRCOM,   PPCNONE,       {0}},
3703 {"bdnzlr-",  XLO(19,BODNZM4,16,0),      XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
3704 {"bdnzlrl-", XLO(19,BODNZM4,16,1),      XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
3705 {"bdnzlr+",  XLO(19,BODNZP4,16,0),      XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
3706 {"bdnzlrl+", XLO(19,BODNZP4,16,1),      XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
3707 {"bdzlr-",   XLO(19,BODZM4,16,0),       XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
3708 {"bdzlrl-",  XLO(19,BODZM4,16,1),       XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
3709 {"bdzlr+",   XLO(19,BODZP4,16,0),       XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
3710 {"bdzlrl+",  XLO(19,BODZP4,16,1),       XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
3711
3712 {"bgelr",    XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3713 {"bgelr-",   XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3714 {"bger",     XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3715 {"bnllr",    XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3716 {"bnllr-",   XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3717 {"bnlr",     XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3718 {"bgelrl",   XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3719 {"bgelrl-",  XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3720 {"bgerl",    XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3721 {"bnllrl",   XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3722 {"bnllrl-",  XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3723 {"bnlrl",    XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3724 {"blelr",    XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3725 {"blelr-",   XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3726 {"bler",     XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3727 {"bnglr",    XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3728 {"bnglr-",   XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3729 {"bngr",     XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3730 {"blelrl",   XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3731 {"blelrl-",  XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3732 {"blerl",    XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3733 {"bnglrl",   XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3734 {"bnglrl-",  XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3735 {"bngrl",    XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3736 {"bnelr",    XLOCB(19,BOF,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3737 {"bnelr-",   XLOCB(19,BOF,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3738 {"bner",     XLOCB(19,BOF,CBEQ,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3739 {"bnelrl",   XLOCB(19,BOF,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3740 {"bnelrl-",  XLOCB(19,BOF,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3741 {"bnerl",    XLOCB(19,BOF,CBEQ,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3742 {"bnslr",    XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3743 {"bnslr-",   XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3744 {"bnsr",     XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3745 {"bnulr",    XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3746 {"bnulr-",   XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3747 {"bnslrl",   XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3748 {"bnslrl-",  XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3749 {"bnsrl",    XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3750 {"bnulrl",   XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3751 {"bnulrl-",  XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3752 {"bgelr+",   XLOCB(19,BOFP,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3753 {"bnllr+",   XLOCB(19,BOFP,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3754 {"bgelrl+",  XLOCB(19,BOFP,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3755 {"bnllrl+",  XLOCB(19,BOFP,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3756 {"blelr+",   XLOCB(19,BOFP,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3757 {"bnglr+",   XLOCB(19,BOFP,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3758 {"blelrl+",  XLOCB(19,BOFP,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3759 {"bnglrl+",  XLOCB(19,BOFP,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3760 {"bnelr+",   XLOCB(19,BOFP,CBEQ,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3761 {"bnelrl+",  XLOCB(19,BOFP,CBEQ,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3762 {"bnslr+",   XLOCB(19,BOFP,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3763 {"bnulr+",   XLOCB(19,BOFP,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3764 {"bnslrl+",  XLOCB(19,BOFP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3765 {"bnulrl+",  XLOCB(19,BOFP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3766 {"bgelr-",   XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3767 {"bnllr-",   XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3768 {"bgelrl-",  XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3769 {"bnllrl-",  XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3770 {"blelr-",   XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3771 {"bnglr-",   XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3772 {"blelrl-",  XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3773 {"bnglrl-",  XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3774 {"bnelr-",   XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3775 {"bnelrl-",  XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3776 {"bnslr-",   XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3777 {"bnulr-",   XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3778 {"bnslrl-",  XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3779 {"bnulrl-",  XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3780 {"bgelr+",   XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3781 {"bnllr+",   XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3782 {"bgelrl+",  XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3783 {"bnllrl+",  XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3784 {"blelr+",   XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3785 {"bnglr+",   XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3786 {"blelrl+",  XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3787 {"bnglrl+",  XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3788 {"bnelr+",   XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3789 {"bnelrl+",  XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3790 {"bnslr+",   XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3791 {"bnulr+",   XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3792 {"bnslrl+",  XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3793 {"bnulrl+",  XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3794 {"bltlr",    XLOCB(19,BOT,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3795 {"bltlr-",   XLOCB(19,BOT,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3796 {"bltr",     XLOCB(19,BOT,CBLT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3797 {"bltlrl",   XLOCB(19,BOT,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3798 {"bltlrl-",  XLOCB(19,BOT,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3799 {"bltrl",    XLOCB(19,BOT,CBLT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3800 {"bgtlr",    XLOCB(19,BOT,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3801 {"bgtlr-",   XLOCB(19,BOT,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3802 {"bgtr",     XLOCB(19,BOT,CBGT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3803 {"bgtlrl",   XLOCB(19,BOT,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3804 {"bgtlrl-",  XLOCB(19,BOT,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3805 {"bgtrl",    XLOCB(19,BOT,CBGT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3806 {"beqlr",    XLOCB(19,BOT,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3807 {"beqlr-",   XLOCB(19,BOT,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3808 {"beqr",     XLOCB(19,BOT,CBEQ,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3809 {"beqlrl",   XLOCB(19,BOT,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3810 {"beqlrl-",  XLOCB(19,BOT,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3811 {"beqrl",    XLOCB(19,BOT,CBEQ,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3812 {"bsolr",    XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3813 {"bsolr-",   XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3814 {"bsor",     XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3815 {"bunlr",    XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3816 {"bunlr-",   XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3817 {"bsolrl",   XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3818 {"bsolrl-",  XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3819 {"bsorl",    XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3820 {"bunlrl",   XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3821 {"bunlrl-",  XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3822 {"bltlr+",   XLOCB(19,BOTP,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3823 {"bltlrl+",  XLOCB(19,BOTP,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3824 {"bgtlr+",   XLOCB(19,BOTP,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3825 {"bgtlrl+",  XLOCB(19,BOTP,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3826 {"beqlr+",   XLOCB(19,BOTP,CBEQ,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3827 {"beqlrl+",  XLOCB(19,BOTP,CBEQ,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3828 {"bsolr+",   XLOCB(19,BOTP,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3829 {"bunlr+",   XLOCB(19,BOTP,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3830 {"bsolrl+",  XLOCB(19,BOTP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3831 {"bunlrl+",  XLOCB(19,BOTP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3832 {"bltlr-",   XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3833 {"bltlrl-",  XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3834 {"bgtlr-",   XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3835 {"bgtlrl-",  XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3836 {"beqlr-",   XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3837 {"beqlrl-",  XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3838 {"bsolr-",   XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3839 {"bunlr-",   XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3840 {"bsolrl-",  XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3841 {"bunlrl-",  XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3842 {"bltlr+",   XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3843 {"bltlrl+",  XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3844 {"bgtlr+",   XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3845 {"bgtlrl+",  XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3846 {"beqlr+",   XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3847 {"beqlrl+",  XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3848 {"bsolr+",   XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3849 {"bunlr+",   XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3850 {"bsolrl+",  XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3851 {"bunlrl+",  XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3852
3853 {"bdnzflr",  XLO(19,BODNZF,16,0),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3854 {"bdnzflr-", XLO(19,BODNZF,16,0),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3855 {"bdnzflrl", XLO(19,BODNZF,16,1),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3856 {"bdnzflrl-",XLO(19,BODNZF,16,1),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3857 {"bdnzflr+", XLO(19,BODNZFP,16,0),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3858 {"bdnzflrl+",XLO(19,BODNZFP,16,1),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3859 {"bdzflr",   XLO(19,BODZF,16,0),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3860 {"bdzflr-",  XLO(19,BODZF,16,0),        XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3861 {"bdzflrl",  XLO(19,BODZF,16,1),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3862 {"bdzflrl-", XLO(19,BODZF,16,1),        XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3863 {"bdzflr+",  XLO(19,BODZFP,16,0),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3864 {"bdzflrl+", XLO(19,BODZFP,16,1),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3865 {"bflr",     XLO(19,BOF,16,0),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3866 {"bflr-",    XLO(19,BOF,16,0),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3867 {"bbfr",     XLO(19,BOF,16,0),          XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
3868 {"bflrl",    XLO(19,BOF,16,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3869 {"bflrl-",   XLO(19,BOF,16,1),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3870 {"bbfrl",    XLO(19,BOF,16,1),          XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
3871 {"bflr+",    XLO(19,BOFP,16,0),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3872 {"bflrl+",   XLO(19,BOFP,16,1),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3873 {"bflr-",    XLO(19,BOFM4,16,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
3874 {"bflrl-",   XLO(19,BOFM4,16,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
3875 {"bflr+",    XLO(19,BOFP4,16,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
3876 {"bflrl+",   XLO(19,BOFP4,16,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
3877 {"bdnztlr",  XLO(19,BODNZT,16,0),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3878 {"bdnztlr-", XLO(19,BODNZT,16,0),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3879 {"bdnztlrl", XLO(19,BODNZT,16,1),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3880 {"bdnztlrl-",XLO(19,BODNZT,16,1),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3881 {"bdnztlr+", XLO(19,BODNZTP,16,0),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3882 {"bdnztlrl+",XLO(19,BODNZTP,16,1),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3883 {"bdztlr",   XLO(19,BODZT,16,0),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3884 {"bdztlr-",  XLO(19,BODZT,16,0),        XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3885 {"bdztlrl",  XLO(19,BODZT,16,1),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3886 {"bdztlrl-", XLO(19,BODZT,16,1),        XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3887 {"bdztlr+",  XLO(19,BODZTP,16,0),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3888 {"bdztlrl+", XLO(19,BODZTP,16,1),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3889 {"btlr",     XLO(19,BOT,16,0),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3890 {"btlr-",    XLO(19,BOT,16,0),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3891 {"bbtr",     XLO(19,BOT,16,0),          XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
3892 {"btlrl",    XLO(19,BOT,16,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3893 {"btlrl-",   XLO(19,BOT,16,1),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3894 {"bbtrl",    XLO(19,BOT,16,1),          XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
3895 {"btlr+",    XLO(19,BOTP,16,0),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3896 {"btlrl+",   XLO(19,BOTP,16,1),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3897 {"btlr-",    XLO(19,BOTM4,16,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
3898 {"btlrl-",   XLO(19,BOTM4,16,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
3899 {"btlr+",    XLO(19,BOTP4,16,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
3900 {"btlrl+",   XLO(19,BOTP4,16,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
3901
3902 {"bclr-",    XLYLK(19,16,0,0),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3903 {"bclrl-",   XLYLK(19,16,0,1),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3904 {"bclr+",    XLYLK(19,16,1,0),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3905 {"bclrl+",   XLYLK(19,16,1,1),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3906 {"bclr",     XLLK(19,16,0),             XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
3907 {"bcr",      XLLK(19,16,0),             XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
3908 {"bclrl",    XLLK(19,16,1),             XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
3909 {"bcrl",     XLLK(19,16,1),             XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
3910
3911 {"rfid",        XL(19,18),      0xffffffff,  PPC64,     PPCNONE,        {0}},
3912
3913 {"crnot",       XL(19,33),      XL_MASK,     PPCCOM,    PPCNONE,        {BT, BA, BBA}},
3914 {"crnor",       XL(19,33),      XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3915 {"rfmci",       X(19,38),   0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCNONE, {0}},
3916
3917 {"rfdi",        XL(19,39),      0xffffffff,  E500MC,    PPCNONE,        {0}},
3918 {"rfi",         XL(19,50),      0xffffffff,  COM,       PPCNONE,        {0}},
3919 {"rfci",        XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCNONE, {0}},
3920
3921 {"rfsvc",       XL(19,82),      0xffffffff,  POWER,     PPCNONE,        {0}},
3922
3923 {"rfgi",        XL(19,102),   0xffffffff, E500MC|PPCA2, PPCNONE,        {0}},
3924
3925 {"crandc",      XL(19,129),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3926
3927 {"isync",       XL(19,150),     0xffffffff,  PPCCOM,    PPCNONE,        {0}},
3928 {"ics",         XL(19,150),     0xffffffff,  PWRCOM,    PPCNONE,        {0}},
3929
3930 {"crclr",       XL(19,193),     XL_MASK,     PPCCOM,    PPCNONE,        {BT, BAT, BBA}},
3931 {"crxor",       XL(19,193),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3932
3933 {"dnh",         X(19,198),      X_MASK,      E500MC,    PPCNONE,        {DUI, DUIS}},
3934
3935 {"crnand",      XL(19,225),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3936
3937 {"crand",       XL(19,257),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3938
3939 {"hrfid",       XL(19,274),     0xffffffff, POWER5|CELL, PPC476,        {0}},
3940
3941 {"crset",       XL(19,289),     XL_MASK,     PPCCOM,    PPCNONE,        {BT, BAT, BBA}},
3942 {"creqv",       XL(19,289),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3943
3944 {"doze",        XL(19,402),     0xffffffff,  POWER6,    PPCNONE,        {0}},
3945
3946 {"crorc",       XL(19,417),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3947
3948 {"nap",         XL(19,434),     0xffffffff,  POWER6,    PPCNONE,        {0}},
3949
3950 {"crmove",      XL(19,449),     XL_MASK,     PPCCOM,    PPCNONE,        {BT, BA, BBA}},
3951 {"cror",        XL(19,449),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3952
3953 {"sleep",       XL(19,466),     0xffffffff,  POWER6,    PPCNONE,        {0}},
3954 {"rvwinkle",    XL(19,498),     0xffffffff,  POWER6,    PPCNONE,        {0}},
3955
3956 {"bctr",    XLO(19,BOU,528,0),          XLBOBIBB_MASK, COM,      PPCNONE,       {0}},
3957 {"bctrl",   XLO(19,BOU,528,1),          XLBOBIBB_MASK, COM,      PPCNONE,       {0}},
3958
3959 {"bgectr",  XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3960 {"bgectr-", XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3961 {"bnlctr",  XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3962 {"bnlctr-", XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3963 {"bgectrl", XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3964 {"bgectrl-",XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3965 {"bnlctrl", XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3966 {"bnlctrl-",XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3967 {"blectr",  XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3968 {"blectr-", XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3969 {"bngctr",  XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3970 {"bngctr-", XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3971 {"blectrl", XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3972 {"blectrl-",XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3973 {"bngctrl", XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3974 {"bngctrl-",XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3975 {"bnectr",  XLOCB(19,BOF,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3976 {"bnectr-", XLOCB(19,BOF,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3977 {"bnectrl", XLOCB(19,BOF,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3978 {"bnectrl-",XLOCB(19,BOF,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3979 {"bnsctr",  XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3980 {"bnsctr-", XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3981 {"bnuctr",  XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3982 {"bnuctr-", XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3983 {"bnsctrl", XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3984 {"bnsctrl-",XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3985 {"bnuctrl", XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3986 {"bnuctrl-",XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3987 {"bgectr+", XLOCB(19,BOFP,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3988 {"bnlctr+", XLOCB(19,BOFP,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3989 {"bgectrl+",XLOCB(19,BOFP,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3990 {"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3991 {"blectr+", XLOCB(19,BOFP,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3992 {"bngctr+", XLOCB(19,BOFP,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3993 {"blectrl+",XLOCB(19,BOFP,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3994 {"bngctrl+",XLOCB(19,BOFP,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3995 {"bnectr+", XLOCB(19,BOFP,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3996 {"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3997 {"bnsctr+", XLOCB(19,BOFP,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3998 {"bnuctr+", XLOCB(19,BOFP,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3999 {"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4000 {"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4001 {"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4002 {"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4003 {"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4004 {"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4005 {"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4006 {"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4007 {"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4008 {"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4009 {"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4010 {"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4011 {"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4012 {"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4013 {"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4014 {"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4015 {"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4016 {"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4017 {"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4018 {"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4019 {"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4020 {"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4021 {"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4022 {"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4023 {"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4024 {"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4025 {"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4026 {"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4027 {"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4028 {"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4029 {"bltctr",  XLOCB(19,BOT,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4030 {"bltctr-", XLOCB(19,BOT,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4031 {"bltctrl", XLOCB(19,BOT,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4032 {"bltctrl-",XLOCB(19,BOT,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4033 {"bgtctr",  XLOCB(19,BOT,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4034 {"bgtctr-", XLOCB(19,BOT,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4035 {"bgtctrl", XLOCB(19,BOT,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4036 {"bgtctrl-",XLOCB(19,BOT,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4037 {"beqctr",  XLOCB(19,BOT,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4038 {"beqctr-", XLOCB(19,BOT,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4039 {"beqctrl", XLOCB(19,BOT,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4040 {"beqctrl-",XLOCB(19,BOT,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4041 {"bsoctr",  XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4042 {"bsoctr-", XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4043 {"bunctr",  XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4044 {"bunctr-", XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4045 {"bsoctrl", XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4046 {"bsoctrl-",XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4047 {"bunctrl", XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4048 {"bunctrl-",XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4049 {"bltctr+", XLOCB(19,BOTP,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4050 {"bltctrl+",XLOCB(19,BOTP,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4051 {"bgtctr+", XLOCB(19,BOTP,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4052 {"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4053 {"beqctr+", XLOCB(19,BOTP,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4054 {"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4055 {"bsoctr+", XLOCB(19,BOTP,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4056 {"bunctr+", XLOCB(19,BOTP,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4057 {"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4058 {"bunctrl+",XLOCB(19,BOTP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4059 {"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4060 {"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4061 {"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4062 {"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4063 {"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4064 {"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4065 {"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4066 {"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4067 {"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4068 {"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4069 {"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4070 {"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4071 {"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4072 {"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4073 {"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4074 {"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4075 {"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4076 {"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4077 {"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4078 {"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4079
4080 {"bfctr",   XLO(19,BOF,528,0),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4081 {"bfctr-",  XLO(19,BOF,528,0),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4082 {"bfctrl",  XLO(19,BOF,528,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4083 {"bfctrl-", XLO(19,BOF,528,1),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4084 {"bfctr+",  XLO(19,BOFP,528,0),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4085 {"bfctrl+", XLO(19,BOFP,528,1),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4086 {"bfctr-",  XLO(19,BOFM4,528,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4087 {"bfctrl-", XLO(19,BOFM4,528,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4088 {"bfctr+",  XLO(19,BOFP4,528,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4089 {"bfctrl+", XLO(19,BOFP4,528,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4090 {"btctr",   XLO(19,BOT,528,0),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4091 {"btctr-",  XLO(19,BOT,528,0),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4092 {"btctrl",  XLO(19,BOT,528,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4093 {"btctrl-", XLO(19,BOT,528,1),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4094 {"btctr+",  XLO(19,BOTP,528,0),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4095 {"btctrl+", XLO(19,BOTP,528,1),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4096 {"btctr-",  XLO(19,BOTM4,528,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4097 {"btctrl-", XLO(19,BOTM4,528,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4098 {"btctr+",  XLO(19,BOTP4,528,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4099 {"btctrl+", XLO(19,BOTP4,528,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4100
4101 {"bcctr-",  XLYLK(19,528,0,0),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
4102 {"bcctrl-", XLYLK(19,528,0,1),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
4103 {"bcctr+",  XLYLK(19,528,1,0),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
4104 {"bcctrl+", XLYLK(19,528,1,1),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
4105 {"bcctr",   XLLK(19,528,0),             XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
4106 {"bcc",     XLLK(19,528,0),             XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
4107 {"bcctrl",  XLLK(19,528,1),             XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
4108 {"bccl",    XLLK(19,528,1),             XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
4109
4110 {"rlwimi",      M(20,0),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4111 {"rlimi",       M(20,0),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4112
4113 {"rlwimi.",     M(20,1),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4114 {"rlimi.",      M(20,1),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4115
4116 {"rotlwi",      MME(21,31,0),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, SH}},
4117 {"clrlwi",      MME(21,31,0),   MSHME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, MB}},
4118 {"rlwinm",      M(21,0),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4119 {"rlinm",       M(21,0),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4120 {"rotlwi.",     MME(21,31,1),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, SH}},
4121 {"clrlwi.",     MME(21,31,1),   MSHME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, MB}},
4122 {"rlwinm.",     M(21,1),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4123 {"rlinm.",      M(21,1),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4124
4125 {"rlmi",        M(22,0),        M_MASK,      M601,      PPCNONE,        {RA, RS, RB, MBE, ME}},
4126 {"rlmi.",       M(22,1),        M_MASK,      M601,      PPCNONE,        {RA, RS, RB, MBE, ME}},
4127
4128 {"rotlw",       MME(23,31,0),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, RB}},
4129 {"rlwnm",       M(23,0),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
4130 {"rlnm",        M(23,0),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
4131 {"rotlw.",      MME(23,31,1),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, RB}},
4132 {"rlwnm.",      M(23,1),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
4133 {"rlnm.",       M(23,1),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
4134
4135 {"nop",         OP(24),         0xffffffff,  PPCCOM,    PPCNONE,        {0}},
4136 {"ori",         OP(24),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
4137 {"oril",        OP(24),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
4138
4139 {"oris",        OP(25),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
4140 {"oriu",        OP(25),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
4141
4142 {"xori",        OP(26),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
4143 {"xoril",       OP(26),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
4144
4145 {"xoris",       OP(27),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
4146 {"xoriu",       OP(27),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
4147
4148 {"andi.",       OP(28),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
4149 {"andil.",      OP(28),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
4150
4151 {"andis.",      OP(29),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
4152 {"andiu.",      OP(29),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
4153
4154 {"rotldi",      MD(30,0,0),     MDMB_MASK,   PPC64,     PPCNONE,        {RA, RS, SH6}},
4155 {"clrldi",      MD(30,0,0),     MDSH_MASK,   PPC64,     PPCNONE,        {RA, RS, MB6}},
4156 {"rldicl",      MD(30,0,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
4157 {"rotldi.",     MD(30,0,1),     MDMB_MASK,   PPC64,     PPCNONE,        {RA, RS, SH6}},
4158 {"clrldi.",     MD(30,0,1),     MDSH_MASK,   PPC64,     PPCNONE,        {RA, RS, MB6}},
4159 {"rldicl.",     MD(30,0,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
4160
4161 {"rldicr",      MD(30,1,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, ME6}},
4162 {"rldicr.",     MD(30,1,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, ME6}},
4163
4164 {"rldic",       MD(30,2,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
4165 {"rldic.",      MD(30,2,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
4166
4167 {"rldimi",      MD(30,3,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
4168 {"rldimi.",     MD(30,3,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
4169
4170 {"rotld",       MDS(30,8,0),    MDSMB_MASK,  PPC64,     PPCNONE,        {RA, RS, RB}},
4171 {"rldcl",       MDS(30,8,0),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, MB6}},
4172 {"rotld.",      MDS(30,8,1),    MDSMB_MASK,  PPC64,     PPCNONE,        {RA, RS, RB}},
4173 {"rldcl.",      MDS(30,8,1),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, MB6}},
4174
4175 {"rldcr",       MDS(30,9,0),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, ME6}},
4176 {"rldcr.",      MDS(30,9,1),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, ME6}},
4177
4178 {"cmpw",        XOPL(31,0,0),   XCMPL_MASK,  PPCCOM,    PPCNONE,        {OBF, RA, RB}},
4179 {"cmpd",        XOPL(31,0,1),   XCMPL_MASK,  PPC64,     PPCNONE,        {OBF, RA, RB}},
4180 {"cmp",         X(31,0),        XCMP_MASK,   PPC|PPCVLE, PPCNONE,       {BF, L, RA, RB}},
4181 {"cmp",         X(31,0),        XCMPL_MASK,  PWRCOM,    PPC,            {BF, RA, RB}},
4182
4183 {"twlgt",       XTO(31,4,TOLGT), XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4184 {"tlgt",        XTO(31,4,TOLGT), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4185 {"twllt",       XTO(31,4,TOLLT), XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4186 {"tllt",        XTO(31,4,TOLLT), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4187 {"tweq",        XTO(31,4,TOEQ),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4188 {"teq",         XTO(31,4,TOEQ),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4189 {"twlge",       XTO(31,4,TOLGE), XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4190 {"tlge",        XTO(31,4,TOLGE), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4191 {"twlnl",       XTO(31,4,TOLNL), XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4192 {"tlnl",        XTO(31,4,TOLNL), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4193 {"twlle",       XTO(31,4,TOLLE), XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4194 {"tlle",        XTO(31,4,TOLLE), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4195 {"twlng",       XTO(31,4,TOLNG), XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4196 {"tlng",        XTO(31,4,TOLNG), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4197 {"twgt",        XTO(31,4,TOGT),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4198 {"tgt",         XTO(31,4,TOGT),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4199 {"twge",        XTO(31,4,TOGE),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4200 {"tge",         XTO(31,4,TOGE),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4201 {"twnl",        XTO(31,4,TONL),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4202 {"tnl",         XTO(31,4,TONL),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4203 {"twlt",        XTO(31,4,TOLT),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4204 {"tlt",         XTO(31,4,TOLT),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4205 {"twle",        XTO(31,4,TOLE),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4206 {"tle",         XTO(31,4,TOLE),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4207 {"twng",        XTO(31,4,TONG),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4208 {"tng",         XTO(31,4,TONG),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4209 {"twne",        XTO(31,4,TONE),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4210 {"tne",         XTO(31,4,TONE),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4211 {"trap",        XTO(31,4,TOU),   0xffffffff, PPCCOM|PPCVLE, PPCNONE,    {0}},
4212 {"tw",          X(31,4),         X_MASK, PPCCOM|PPCVLE, PPCNONE,        {TO, RA, RB}},
4213 {"t",           X(31,4),         X_MASK,     PWRCOM,    PPCNONE,        {TO, RA, RB}},
4214
4215 {"lvsl",        X(31,6),        X_MASK,      PPCVEC,    PPCNONE,        {VD, RA0, RB}},
4216 {"lvebx",       X(31,7),        X_MASK,      PPCVEC,    PPCNONE,        {VD, RA0, RB}},
4217 {"lbfcmx",      APU(31,7,0),    APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4218
4219 {"subfc",       XO(31,8,0,0),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4220 {"sf",          XO(31,8,0,0),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4221 {"subc",        XO(31,8,0,0),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RB, RA}},
4222 {"subfc.",      XO(31,8,0,1),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4223 {"sf.",         XO(31,8,0,1),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4224 {"subc.",       XO(31,8,0,1),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RB, RA}},
4225
4226 {"mulhdu",      XO(31,9,0,0),   XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
4227 {"mulhdu.",     XO(31,9,0,1),   XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
4228
4229 {"addc",        XO(31,10,0,0),  XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4230 {"a",           XO(31,10,0,0),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4231 {"addc.",       XO(31,10,0,1),  XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4232 {"a.",          XO(31,10,0,1),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4233
4234 {"mulhwu",      XO(31,11,0,0),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
4235 {"mulhwu.",     XO(31,11,0,1),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
4236
4237 {"isellt",      X(31,15),       X_MASK,      PPCISEL,   PPCNONE,        {RT, RA0, RB}},
4238
4239 {"tlbilxlpid",  XTO(31,18,0),   XTO_MASK, E500MC|PPCA2, PPCNONE,        {0}},
4240 {"tlbilxpid",   XTO(31,18,1),   XTO_MASK, E500MC|PPCA2, PPCNONE,        {0}},
4241 {"tlbilxva",    XTO(31,18,3),   XTO_MASK, E500MC|PPCA2, PPCNONE,        {RA0, RB}},
4242 {"tlbilx",      X(31,18),       X_MASK,   E500MC|PPCA2, PPCNONE,        {T, RA0, RB}},
4243
4244 {"mfcr",        XFXM(31,19,0,0), XFXFXM_MASK, POWER4,   PPCNONE,        {RT, FXM4}},
4245 {"mfcr",        XFXM(31,19,0,0), XRARB_MASK, COM|PPCVLE, POWER4,        {RT}},
4246 {"mfocrf",      XFXM(31,19,0,1), XFXFXM_MASK, COM,      PPCNONE,        {RT, FXM}},
4247
4248 {"lwarx",       X(31,20),       XEH_MASK,    PPC|PPCVLE, PPCNONE,       {RT, RA0, RB, EH}},
4249
4250 {"ldx",         X(31,21),       X_MASK,      PPC64|PPCVLE, PPCNONE,     {RT, RA0, RB}},
4251
4252 {"icbt",        X(31,22),       X_MASK,      BOOKE|PPCE300|PPCA2|PPC476|PPCVLE, PPCNONE, {CT, RA0, RB}},
4253
4254 {"lwzx",        X(31,23),       X_MASK,      PPCCOM|PPCVLE, PPCNONE,    {RT, RA0, RB}},
4255 {"lx",          X(31,23),       X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
4256
4257 {"slw",         XRC(31,24,0),   X_MASK,      PPCCOM|PPCVLE, PPCNONE,    {RA, RS, RB}},
4258 {"sl",          XRC(31,24,0),   X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
4259 {"slw.",        XRC(31,24,1),   X_MASK,      PPCCOM|PPCVLE, PPCNONE,    {RA, RS, RB}},
4260 {"sl.",         XRC(31,24,1),   X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
4261
4262 {"cntlzw",      XRC(31,26,0),   XRB_MASK,    PPCCOM|PPCVLE, PPCNONE,    {RA, RS}},
4263 {"cntlz",       XRC(31,26,0),   XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
4264 {"cntlzw.",     XRC(31,26,1),   XRB_MASK,    PPCCOM|PPCVLE, PPCNONE,    {RA, RS}},
4265 {"cntlz.",      XRC(31,26,1),   XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
4266
4267 {"sld",         XRC(31,27,0),   X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
4268 {"sld.",        XRC(31,27,1),   X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
4269
4270 {"and",         XRC(31,28,0),   X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4271 {"and.",        XRC(31,28,1),   X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4272
4273 {"maskg",       XRC(31,29,0),   X_MASK,      M601,      PPCA2,          {RA, RS, RB}},
4274 {"maskg.",      XRC(31,29,1),   X_MASK,      M601,      PPCA2,          {RA, RS, RB}},
4275
4276 {"ldepx",       X(31,29),       X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
4277 {"lwepx",       X(31,31),       X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
4278
4279 {"cmplw",       XOPL(31,32,0),  XCMPL_MASK,  PPCCOM|PPCVLE, PPCNONE,    {OBF, RA, RB}},
4280 {"cmpld",       XOPL(31,32,1),  XCMPL_MASK,  PPC64,     PPCNONE,        {OBF, RA, RB}},
4281 {"cmpl",        X(31,32),       XCMP_MASK,   PPC|PPCVLE, PPCNONE,       {BF, L, RA, RB}},
4282 {"cmpl",        X(31,32),       XCMPL_MASK,  PWRCOM,    PPC,            {BF, RA, RB}},
4283
4284 {"lvsr",        X(31,38),       X_MASK,      PPCVEC,    PPCNONE,        {VD, RA0, RB}},
4285 {"lvehx",       X(31,39),       X_MASK,      PPCVEC,    PPCNONE,        {VD, RA0, RB}},
4286 {"lhfcmx",      APU(31,39,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4287
4288 {"iselgt",      X(31,47),       X_MASK,      PPCISEL,   PPCNONE,        {RT, RA0, RB}},
4289
4290 {"lvewx",       X(31,71),       X_MASK,      PPCVEC,    PPCNONE,        {VD, RA0, RB}},
4291
4292 {"addg6s",      XO(31,74,0,0),  XO_MASK,     POWER6,    PPCNONE,        {RT, RA, RB}},
4293
4294 {"iseleq",      X(31,79),       X_MASK,      PPCISEL,   PPCNONE,        {RT, RA0, RB}},
4295
4296 {"isel",        XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, PPCNONE,       {RT, RA0, RB, CRB}},
4297
4298 {"subf",        XO(31,40,0,0),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
4299 {"sub",         XO(31,40,0,0),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RB, RA}},
4300 {"subf.",       XO(31,40,0,1),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
4301 {"sub.",        XO(31,40,0,1),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RB, RA}},
4302
4303 {"eratilx",     X(31,51),       X_MASK,      PPCA2,     PPCNONE,        {ERAT_T, RA, RB}},
4304
4305 {"lbarx",       X(31,52),       XEH_MASK,    POWER7,    PPCNONE,        {RT, RA0, RB, EH}},
4306
4307 {"ldux",        X(31,53),       X_MASK,      PPC64|PPCVLE, PPCNONE,     {RT, RAL, RB}},
4308
4309 {"dcbst",       X(31,54),       XRT_MASK,    PPC|PPCVLE, PPCNONE,       {RA0, RB}},
4310
4311 {"lwzux",       X(31,55),       X_MASK,      PPCCOM|PPCVLE, PPCNONE,    {RT, RAL, RB}},
4312 {"lux",         X(31,55),       X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
4313
4314 {"cntlzd",      XRC(31,58,0),   XRB_MASK,    PPC64|PPCVLE, PPCNONE,     {RA, RS}},
4315 {"cntlzd.",     XRC(31,58,1),   XRB_MASK,    PPC64|PPCVLE, PPCNONE,     {RA, RS}},
4316
4317 {"andc",        XRC(31,60,0),   X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4318 {"andc.",       XRC(31,60,1),   X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4319
4320 {"waitrsv",     X(31,62)|(1<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
4321 {"waitimpl",    X(31,62)|(2<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
4322 {"wait",        X(31,62),       XWC_MASK,    POWER7|E500MC|PPCA2|PPCVLE, PPCNONE, {WC}},
4323
4324 {"dcbstep",     XRT(31,63,0),   XRT_MASK,    E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
4325
4326 {"tdlgt",       XTO(31,68,TOLGT), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4327 {"tdllt",       XTO(31,68,TOLLT), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4328 {"tdeq",        XTO(31,68,TOEQ),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4329 {"tdlge",       XTO(31,68,TOLGE), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4330 {"tdlnl",       XTO(31,68,TOLNL), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4331 {"tdlle",       XTO(31,68,TOLLE), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4332 {"tdlng",       XTO(31,68,TOLNG), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4333 {"tdgt",        XTO(31,68,TOGT),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4334 {"tdge",        XTO(31,68,TOGE),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4335 {"tdnl",        XTO(31,68,TONL),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4336 {"tdlt",        XTO(31,68,TOLT),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4337 {"tdle",        XTO(31,68,TOLE),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4338 {"tdng",        XTO(31,68,TONG),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4339 {"tdne",        XTO(31,68,TONE),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4340 {"td",          X(31,68),       X_MASK,      PPC64|PPCVLE, PPCNONE,     {TO, RA, RB}},
4341
4342 {"lwfcmx",      APU(31,71,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4343 {"mulhd",       XO(31,73,0,0),  XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
4344 {"mulhd.",      XO(31,73,0,1),  XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
4345
4346 {"mulhw",       XO(31,75,0,0),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
4347 {"mulhw.",      XO(31,75,0,1),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
4348
4349 {"dlmzb",       XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, PPCNONE,     {RA, RS, RB}},
4350 {"dlmzb.",      XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, PPCNONE,     {RA, RS, RB}},
4351
4352 {"mtsrd",       X(31,82),  XRB_MASK|(1<<20), PPC64,     PPCNONE,        {SR, RS}},
4353
4354 {"mfmsr",       X(31,83),       XRARB_MASK,  COM|PPCVLE, PPCNONE,       {RT}},
4355
4356 {"ldarx",       X(31,84),       XEH_MASK,    PPC64|PPCVLE, PPCNONE,     {RT, RA0, RB, EH}},
4357
4358 {"dcbfl",       XOPL(31,86,1),  XRT_MASK,    POWER5,    PPC476,         {RA0, RB}},
4359 {"dcbf",        X(31,86),       XLRT_MASK,   PPC|PPCVLE, PPCNONE,       {RA0, RB, L}},
4360
4361 {"lbzx",        X(31,87),       X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RA0, RB}},
4362
4363 {"lbepx",       X(31,95),       X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
4364
4365 {"dni",         XRC(31,97,1),   XRB_MASK,    E6500,     PPCNONE,        {DUI, DCTL}},
4366
4367 {"lvx",         X(31,103),      X_MASK,      PPCVEC,    PPCNONE,        {VD, RA0, RB}},
4368 {"lqfcmx",      APU(31,103,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4369
4370 {"neg",         XO(31,104,0,0), XORB_MASK,   COM|PPCVLE, PPCNONE,       {RT, RA}},
4371 {"neg.",        XO(31,104,0,1), XORB_MASK,   COM|PPCVLE, PPCNONE,       {RT, RA}},
4372
4373 {"mul",         XO(31,107,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4374 {"mul.",        XO(31,107,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4375
4376 {"mvidsplt",    X(31,110),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA, RB}},
4377
4378 {"mtsrdin",     X(31,114),      XRA_MASK,    PPC64,     PPCNONE,        {RS, RB}},
4379
4380 {"lharx",       X(31,116),      XEH_MASK,    POWER7,    PPCNONE,        {RT, RA0, RB, EH}},
4381
4382 {"clf",         X(31,118),      XTO_MASK,    POWER,     PPCNONE,        {RA, RB}},
4383
4384 {"lbzux",       X(31,119),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RAL, RB}},
4385
4386 {"popcntb",     X(31,122),      XRB_MASK,    POWER5|PPCVLE, PPCNONE,    {RA, RS}},
4387
4388 {"not",         XRC(31,124,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RBS}},
4389 {"nor",         XRC(31,124,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4390 {"not.",        XRC(31,124,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RBS}},
4391 {"nor.",        XRC(31,124,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4392
4393 {"dcbfep",      XRT(31,127,0),  XRT_MASK,    E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
4394
4395 {"wrtee",       X(31,131),      XRARB_MASK,  PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RS}},
4396
4397 {"dcbtstls",    X(31,134),      X_MASK,      PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
4398
4399 {"stvebx",      X(31,135),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA0, RB}},
4400 {"stbfcmx",     APU(31,135,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4401
4402 {"subfe",       XO(31,136,0,0), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4403 {"sfe",         XO(31,136,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4404 {"subfe.",      XO(31,136,0,1), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4405 {"sfe.",        XO(31,136,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4406
4407 {"adde",        XO(31,138,0,0), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4408 {"ae",          XO(31,138,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4409 {"adde.",       XO(31,138,0,1), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4410 {"ae.",         XO(31,138,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4411
4412 {"mviwsplt",    X(31,142),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA, RB}},
4413
4414 {"dcbtstlse",   X(31,142),      X_MASK,      PPCCHLK,   E500MC,         {CT, RA0, RB}},
4415
4416 {"mtcr",        XFXM(31,144,0xff,0), XRARB_MASK, COM,   PPCNONE,        {RS}},
4417 {"mtcrf",       XFXM(31,144,0,0), XFXFXM_MASK, COM,     PPCNONE,        {FXM, RS}},
4418 {"mtocrf",      XFXM(31,144,0,1), XFXFXM_MASK, COM,     PPCNONE,        {FXM, RS}},
4419
4420 {"mtmsr",       X(31,146),      XRLARB_MASK, COM|PPCVLE, PPCNONE,       {RS, A_L}},
4421
4422 {"eratsx",      XRC(31,147,0),  X_MASK,      PPCA2,     PPCNONE,        {RT, RA0, RB}},
4423 {"eratsx.",     XRC(31,147,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, RA0, RB}},
4424
4425 {"stdx",        X(31,149),      X_MASK,      PPC64|PPCVLE, PPCNONE,     {RS, RA0, RB}},
4426
4427 {"stwcx.",      XRC(31,150,1),  X_MASK,      PPC|PPCVLE, PPCNONE,       {RS, RA0, RB}},
4428
4429 {"stwx",        X(31,151),      X_MASK,      PPCCOM|PPCVLE, PPCNONE,    {RS, RA0, RB}},
4430 {"stx",         X(31,151),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA, RB}},
4431
4432 {"slq",         XRC(31,152,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4433 {"slq.",        XRC(31,152,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4434
4435 {"sle",         XRC(31,153,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4436 {"sle.",        XRC(31,153,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4437
4438 {"prtyw",       X(31,154),      XRB_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS}},
4439
4440 {"stdepx",      X(31,157),      X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
4441
4442 {"stwepx",      X(31,159),      X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
4443
4444 {"wrteei",      X(31,163),      XE_MASK,     PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {E}},
4445
4446 {"dcbtls",      X(31,166),      X_MASK,      PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
4447
4448 {"stvehx",      X(31,167),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA0, RB}},
4449 {"sthfcmx",     APU(31,167,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4450
4451 {"dcbtlse",     X(31,174),      X_MASK,      PPCCHLK,   E500MC,         {CT, RA0, RB}},
4452
4453 {"mtmsrd",      X(31,178),      XRLARB_MASK, PPC64,     PPCNONE,        {RS, A_L}},
4454
4455 {"eratre",      X(31,179),      X_MASK,      PPCA2,     PPCNONE,        {RT, RA, WS}},
4456
4457 {"stdux",       X(31,181),      X_MASK,      PPC64|PPCVLE, PPCNONE,     {RS, RAS, RB}},
4458
4459 {"wchkall",     X(31,182),      X_MASK,      PPCA2,     PPCNONE,        {OBF}},
4460
4461 {"stwux",       X(31,183),      X_MASK,      PPCCOM|PPCVLE, PPCNONE,    {RS, RAS, RB}},
4462 {"stux",        X(31,183),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, RB}},
4463
4464 {"sliq",        XRC(31,184,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4465 {"sliq.",       XRC(31,184,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4466
4467 {"prtyd",       X(31,186),      XRB_MASK, POWER6|PPCA2, PPCNONE,        {RA, RS}},
4468
4469 {"icblq.",      XRC(31,198,1),  X_MASK,      E6500,     PPCNONE,        {CT, RA0, RB}},
4470
4471 {"stvewx",      X(31,199),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA0, RB}},
4472 {"stwfcmx",     APU(31,199,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4473
4474 {"subfze",      XO(31,200,0,0), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
4475 {"sfze",        XO(31,200,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4476 {"subfze.",     XO(31,200,0,1), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
4477 {"sfze.",       XO(31,200,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4478
4479 {"addze",       XO(31,202,0,0), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
4480 {"aze",         XO(31,202,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4481 {"addze.",      XO(31,202,0,1), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
4482 {"aze.",        XO(31,202,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4483
4484 {"msgsnd",      XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RB}},
4485
4486 {"mtsr",        X(31,210), XRB_MASK|(1<<20), COM,       NON32,          {SR, RS}},
4487
4488 {"eratwe",      X(31,211),      X_MASK,      PPCA2,     PPCNONE,        {RS, RA, WS}},
4489
4490 {"ldawx.",      XRC(31,212,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, RA0, RB}},
4491
4492 {"stdcx.",      XRC(31,214,1),  X_MASK,      PPC64|PPCVLE, PPCNONE,     {RS, RA0, RB}},
4493
4494 {"stbx",        X(31,215),      X_MASK,      COM|PPCVLE, PPCNONE,       {RS, RA0, RB}},
4495
4496 {"sllq",        XRC(31,216,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4497 {"sllq.",       XRC(31,216,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4498
4499 {"sleq",        XRC(31,217,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4500 {"sleq.",       XRC(31,217,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4501
4502 {"stbepx",      X(31,223),      X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
4503
4504 {"icblc",       X(31,230),      X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
4505
4506 {"stvx",        X(31,231),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA0, RB}},
4507 {"stqfcmx",     APU(31,231,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4508
4509 {"subfme",      XO(31,232,0,0), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
4510 {"sfme",        XO(31,232,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4511 {"subfme.",     XO(31,232,0,1), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
4512 {"sfme.",       XO(31,232,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4513
4514 {"mulld",       XO(31,233,0,0), XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
4515 {"mulld.",      XO(31,233,0,1), XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
4516
4517 {"addme",       XO(31,234,0,0), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
4518 {"ame",         XO(31,234,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4519 {"addme.",      XO(31,234,0,1), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
4520 {"ame.",        XO(31,234,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4521
4522 {"mullw",       XO(31,235,0,0), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4523 {"muls",        XO(31,235,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4524 {"mullw.",      XO(31,235,0,1), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4525 {"muls.",       XO(31,235,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4526
4527 {"icblce",      X(31,238),      X_MASK,      PPCCHLK,   E500MC|PPCA2,   {CT, RA, RB}},
4528 {"msgclr",      XRTRA(31,238,0,0),XRTRA_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RB}},
4529 {"mtsrin",      X(31,242),      XRA_MASK,    PPC,       NON32,          {RS, RB}},
4530 {"mtsri",       X(31,242),      XRA_MASK,    POWER,     NON32,          {RS, RB}},
4531
4532 {"dcbtstt",     XRT(31,246,0x10), XRT_MASK,  POWER7,    PPCNONE,        {RA0, RB}},
4533 {"dcbtst",      X(31,246),      X_MASK,      POWER4,    PPCNONE,        {RA0, RB, CT}},
4534 {"dcbtst",      X(31,246),      X_MASK,      PPC|PPCVLE, POWER4,        {CT, RA0, RB}},
4535
4536 {"stbux",       X(31,247),      X_MASK,      COM|PPCVLE, PPCNONE,       {RS, RAS, RB}},
4537
4538 {"slliq",       XRC(31,248,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4539 {"slliq.",      XRC(31,248,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4540
4541 {"bpermd",      X(31,252),      X_MASK,   POWER7|PPCA2, PPCNONE,        {RA, RS, RB}},
4542
4543 {"dcbtstep",    XRT(31,255,0),  X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA0, RB}},
4544
4545 {"mfdcrx",      X(31,259),      X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {RS, RA}},
4546 {"mfdcrx.",     XRC(31,259,1),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA}},
4547
4548 {"lvexbx",      X(31,261),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
4549
4550 {"icbt",        X(31,262),      XRT_MASK,    PPC403,    PPCNONE,        {RA, RB}},
4551
4552 {"lvepxl",      X(31,263),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
4553
4554 {"ldfcmx",      APU(31,263,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4555 {"doz",         XO(31,264,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4556 {"doz.",        XO(31,264,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4557
4558 {"add",         XO(31,266,0,0), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4559 {"cax",         XO(31,266,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4560 {"add.",        XO(31,266,0,1), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4561 {"cax.",        XO(31,266,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4562
4563 {"ehpriv",      X(31,270),      0xffffffff, E500MC|PPCA2, PPCNONE,      {0}},
4564
4565 {"tlbiel",      X(31,274),      XRTLRA_MASK, POWER4,    PPC476,         {RB, L}},
4566
4567 {"mfapidi",     X(31,275),      X_MASK,      BOOKE,     TITAN,          {RT, RA}},
4568
4569 {"lscbx",       XRC(31,277,0),  X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
4570 {"lscbx.",      XRC(31,277,1),  X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
4571
4572 {"dcbtt",       XRT(31,278,0x10), XRT_MASK,  POWER7,    PPCNONE,        {RA0, RB}},
4573 {"dcbt",        X(31,278),      X_MASK,      POWER4,    PPCNONE,        {RA0, RB, CT}},
4574 {"dcbt",        X(31,278),      X_MASK,      PPC|PPCVLE, POWER4,        {CT, RA0, RB}},
4575
4576 {"lhzx",        X(31,279),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RA0, RB}},
4577
4578 {"cdtbcd",      X(31,282),      XRB_MASK,    POWER6,    PPCNONE,        {RA, RS}},
4579
4580 {"eqv",         XRC(31,284,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4581 {"eqv.",        XRC(31,284,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4582
4583 {"lhepx",       X(31,287),      X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA0, RB}},
4584
4585 {"mfdcrux",     X(31,291),      X_MASK,      PPC464|PPCVLE, PPCNONE,    {RS, RA}},
4586
4587 {"lvexhx",      X(31,293),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
4588 {"lvepx",       X(31,295),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
4589
4590 {"tlbie",       X(31,306),      XRTLRA_MASK, PPC,       TITAN,          {RB, L}},
4591 {"tlbi",        X(31,306),      XRT_MASK,    POWER,     PPCNONE,        {RA0, RB}},
4592
4593 {"eciwx",       X(31,310),      X_MASK,      PPC,       TITAN,          {RT, RA0, RB}},
4594
4595 {"lhzux",       X(31,311),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RAL, RB}},
4596
4597 {"cbcdtd",      X(31,314),      XRB_MASK,    POWER6,    PPCNONE,        {RA, RS}},
4598
4599 {"xor",         XRC(31,316,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4600 {"xor.",        XRC(31,316,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4601
4602 {"dcbtep",      XRT(31,319,0),  X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA0, RB}},
4603
4604 {"mfexisr",     XSPR(31,323, 64), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4605 {"mfexier",     XSPR(31,323, 66), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4606 {"mfbr0",       XSPR(31,323,128), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4607 {"mfbr1",       XSPR(31,323,129), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4608 {"mfbr2",       XSPR(31,323,130), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4609 {"mfbr3",       XSPR(31,323,131), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4610 {"mfbr4",       XSPR(31,323,132), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4611 {"mfbr5",       XSPR(31,323,133), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4612 {"mfbr6",       XSPR(31,323,134), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4613 {"mfbr7",       XSPR(31,323,135), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4614 {"mfbear",      XSPR(31,323,144), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4615 {"mfbesr",      XSPR(31,323,145), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4616 {"mfiocr",      XSPR(31,323,160), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4617 {"mfdmacr0",    XSPR(31,323,192), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4618 {"mfdmact0",    XSPR(31,323,193), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4619 {"mfdmada0",    XSPR(31,323,194), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4620 {"mfdmasa0",    XSPR(31,323,195), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4621 {"mfdmacc0",    XSPR(31,323,196), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4622 {"mfdmacr1",    XSPR(31,323,200), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4623 {"mfdmact1",    XSPR(31,323,201), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4624 {"mfdmada1",    XSPR(31,323,202), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4625 {"mfdmasa1",    XSPR(31,323,203), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4626 {"mfdmacc1",    XSPR(31,323,204), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4627 {"mfdmacr2",    XSPR(31,323,208), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4628 {"mfdmact2",    XSPR(31,323,209), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4629 {"mfdmada2",    XSPR(31,323,210), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4630 {"mfdmasa2",    XSPR(31,323,211), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4631 {"mfdmacc2",    XSPR(31,323,212), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4632 {"mfdmacr3",    XSPR(31,323,216), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4633 {"mfdmact3",    XSPR(31,323,217), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4634 {"mfdmada3",    XSPR(31,323,218), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4635 {"mfdmasa3",    XSPR(31,323,219), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4636 {"mfdmacc3",    XSPR(31,323,220), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4637 {"mfdmasr",     XSPR(31,323,224), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4638 {"mfdcr",       X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {RT, SPR}},
4639 {"mfdcr.",      XRC(31,323,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, SPR}},
4640
4641 {"lvexwx",      X(31,325),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
4642
4643 {"dcread",      X(31,326),      X_MASK,  PPC476|TITAN,  PPCNONE,        {RT, RA0, RB}},
4644
4645 {"div",         XO(31,331,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4646 {"div.",        XO(31,331,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4647
4648 {"lxvdsx",      X(31,332),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA0, RB}},
4649
4650 {"mfpmr",       X(31,334),      X_MASK, PPCPMR|PPCE300|PPCVLE, PPCNONE, {RT, PMR}},
4651 {"mftmr",       X(31,366),      X_MASK, PPCTMR|E6500,   PPCNONE,        {RT, TMR}},
4652
4653 {"mfmq",        XSPR(31,339,  0), XSPR_MASK, M601,      PPCNONE,        {RT}},
4654 {"mfxer",       XSPR(31,339,  1), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RT}},
4655 {"mfrtcu",      XSPR(31,339,  4), XSPR_MASK, COM,       TITAN,          {RT}},
4656 {"mfrtcl",      XSPR(31,339,  5), XSPR_MASK, COM,       TITAN,          {RT}},
4657 {"mfdec",       XSPR(31,339,  6), XSPR_MASK, MFDEC1,    PPCNONE,        {RT}},
4658 {"mflr",        XSPR(31,339,  8), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RT}},
4659 {"mfctr",       XSPR(31,339,  9), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RT}},
4660 {"mftid",       XSPR(31,339, 17), XSPR_MASK, POWER,     PPCNONE,        {RT}},
4661 {"mfdsisr",     XSPR(31,339, 18), XSPR_MASK, COM,       TITAN,          {RT}},
4662 {"mfdar",       XSPR(31,339, 19), XSPR_MASK, COM,       TITAN,          {RT}},
4663 {"mfdec",       XSPR(31,339, 22), XSPR_MASK, MFDEC2,    MFDEC1,         {RT}},
4664 {"mfsdr0",      XSPR(31,339, 24), XSPR_MASK, POWER,     PPCNONE,        {RT}},
4665 {"mfsdr1",      XSPR(31,339, 25), XSPR_MASK, COM,       TITAN,          {RT}},
4666 {"mfsrr0",      XSPR(31,339, 26), XSPR_MASK, COM,       PPCNONE,        {RT}},
4667 {"mfsrr1",      XSPR(31,339, 27), XSPR_MASK, COM,       PPCNONE,        {RT}},
4668 {"mfcfar",      XSPR(31,339, 28), XSPR_MASK, POWER6,    PPCNONE,        {RT}},
4669 {"mfpid",       XSPR(31,339, 48), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4670 {"mfcsrr0",     XSPR(31,339, 58), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4671 {"mfcsrr1",     XSPR(31,339, 59), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4672 {"mfdear",      XSPR(31,339, 61), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4673 {"mfesr",       XSPR(31,339, 62), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4674 {"mfivpr",      XSPR(31,339, 63), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4675 {"mfcmpa",      XSPR(31,339,144), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4676 {"mfcmpb",      XSPR(31,339,145), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4677 {"mfcmpc",      XSPR(31,339,146), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4678 {"mfcmpd",      XSPR(31,339,147), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4679 {"mficr",       XSPR(31,339,148), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4680 {"mfder",       XSPR(31,339,149), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4681 {"mfcounta",    XSPR(31,339,150), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4682 {"mfcountb",    XSPR(31,339,151), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4683 {"mfcmpe",      XSPR(31,339,152), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4684 {"mfcmpf",      XSPR(31,339,153), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4685 {"mfcmpg",      XSPR(31,339,154), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4686 {"mfcmph",      XSPR(31,339,155), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4687 {"mflctrl1",    XSPR(31,339,156), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4688 {"mflctrl2",    XSPR(31,339,157), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4689 {"mfictrl",     XSPR(31,339,158), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4690 {"mfbar",       XSPR(31,339,159), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4691 {"mfvrsave",    XSPR(31,339,256), XSPR_MASK, PPCVEC,    PPCNONE,        {RT}},
4692 {"mfusprg0",    XSPR(31,339,256), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4693 {"mfsprg",      XSPR(31,339,256), XSPRG_MASK, PPC|PPCVLE, PPCNONE,      {RT, SPRG}},
4694 {"mfsprg4",     XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
4695 {"mfsprg5",     XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
4696 {"mfsprg6",     XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
4697 {"mfsprg7",     XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
4698 {"mftb",        XSPR(31,339,268), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4699 {"mftbl",       XSPR(31,339,268), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4700 {"mftbu",       XSPR(31,339,269), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4701 {"mfsprg0",     XSPR(31,339,272), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RT}},
4702 {"mfsprg1",     XSPR(31,339,273), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RT}},
4703 {"mfsprg2",     XSPR(31,339,274), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RT}},
4704 {"mfsprg3",     XSPR(31,339,275), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RT}},
4705 {"mfasr",       XSPR(31,339,280), XSPR_MASK, PPC64,     PPCNONE,        {RT}},
4706 {"mfear",       XSPR(31,339,282), XSPR_MASK, PPC,       TITAN,          {RT}},
4707 {"mfpir",       XSPR(31,339,286), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4708 {"mfpvr",       XSPR(31,339,287), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RT}},
4709 {"mfdbsr",      XSPR(31,339,304), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4710 {"mfdbcr0",     XSPR(31,339,308), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4711 {"mfdbcr1",     XSPR(31,339,309), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4712 {"mfdbcr2",     XSPR(31,339,310), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4713 {"mfiac1",      XSPR(31,339,312), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4714 {"mfiac2",      XSPR(31,339,313), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4715 {"mfiac3",      XSPR(31,339,314), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4716 {"mfiac4",      XSPR(31,339,315), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4717 {"mfdac1",      XSPR(31,339,316), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4718 {"mfdac2",      XSPR(31,339,317), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4719 {"mfdvc1",      XSPR(31,339,318), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4720 {"mfdvc2",      XSPR(31,339,319), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4721 {"mftsr",       XSPR(31,339,336), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4722 {"mftcr",       XSPR(31,339,340), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4723 {"mfivor0",     XSPR(31,339,400), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4724 {"mfivor1",     XSPR(31,339,401), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4725 {"mfivor2",     XSPR(31,339,402), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4726 {"mfivor3",     XSPR(31,339,403), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4727 {"mfivor4",     XSPR(31,339,404), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4728 {"mfivor5",     XSPR(31,339,405), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4729 {"mfivor6",     XSPR(31,339,406), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4730 {"mfivor7",     XSPR(31,339,407), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4731 {"mfivor8",     XSPR(31,339,408), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4732 {"mfivor9",     XSPR(31,339,409), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4733 {"mfivor10",    XSPR(31,339,410), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4734 {"mfivor11",    XSPR(31,339,411), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4735 {"mfivor12",    XSPR(31,339,412), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4736 {"mfivor13",    XSPR(31,339,413), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4737 {"mfivor14",    XSPR(31,339,414), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4738 {"mfivor15",    XSPR(31,339,415), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4739 {"mfspefscr",   XSPR(31,339,512), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
4740 {"mfbbear",     XSPR(31,339,513), XSPR_MASK, PPCBRLK,   PPCNONE,        {RT}},
4741 {"mfbbtar",     XSPR(31,339,514), XSPR_MASK, PPCBRLK,   PPCNONE,        {RT}},
4742 {"mfivor32",    XSPR(31,339,528), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
4743 {"mfibatu",     XSPR(31,339,528), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
4744 {"mfivor33",    XSPR(31,339,529), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
4745 {"mfibatl",     XSPR(31,339,529), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
4746 {"mfivor34",    XSPR(31,339,530), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
4747 {"mfivor35",    XSPR(31,339,531), XSPR_MASK, PPCPMR,    PPCNONE,        {RT}},
4748 {"mfdbatu",     XSPR(31,339,536), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
4749 {"mfdbatl",     XSPR(31,339,537), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
4750 {"mfic_cst",    XSPR(31,339,560), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4751 {"mfic_adr",    XSPR(31,339,561), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4752 {"mfic_dat",    XSPR(31,339,562), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4753 {"mfdc_cst",    XSPR(31,339,568), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4754 {"mfdc_adr",    XSPR(31,339,569), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4755 {"mfdc_dat",    XSPR(31,339,570), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4756 {"mfmcsrr0",    XSPR(31,339,570), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RT}},
4757 {"mfmcsrr1",    XSPR(31,339,571), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RT}},
4758 {"mfmcsr",      XSPR(31,339,572), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RT}},
4759 {"mfmcar",      XSPR(31,339,573), XSPR_MASK, PPCRFMCI,  TITAN,          {RT}},
4760 {"mfdpdr",      XSPR(31,339,630), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4761 {"mfdpir",      XSPR(31,339,631), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4762 {"mfimmr",      XSPR(31,339,638), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4763 {"mfmi_ctr",    XSPR(31,339,784), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4764 {"mfmi_ap",     XSPR(31,339,786), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4765 {"mfmi_epn",    XSPR(31,339,787), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4766 {"mfmi_twc",    XSPR(31,339,789), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4767 {"mfmi_rpn",    XSPR(31,339,790), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4768 {"mfmd_ctr",    XSPR(31,339,792), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4769 {"mfm_casid",   XSPR(31,339,793), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4770 {"mfmd_ap",     XSPR(31,339,794), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4771 {"mfmd_epn",    XSPR(31,339,795), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4772 {"mfmd_twb",    XSPR(31,339,796), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4773 {"mfmd_twc",    XSPR(31,339,797), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4774 {"mfmd_rpn",    XSPR(31,339,798), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4775 {"mfm_tw",      XSPR(31,339,799), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4776 {"mfmi_dbcam",  XSPR(31,339,816), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4777 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4778 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4779 {"mfmd_dbcam",  XSPR(31,339,824), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4780 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4781 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4782 {"mfivndx",     XSPR(31,339,880), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4783 {"mfdvndx",     XSPR(31,339,881), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4784 {"mfivlim",     XSPR(31,339,882), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4785 {"mfdvlim",     XSPR(31,339,883), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4786 {"mfclcsr",     XSPR(31,339,884), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4787 {"mfccr1",      XSPR(31,339,888), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4788 {"mfrstcfg",    XSPR(31,339,923), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4789 {"mfdcdbtrl",   XSPR(31,339,924), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4790 {"mfdcdbtrh",   XSPR(31,339,925), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4791 {"mficdbtr",    XSPR(31,339,927), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4792 {"mfummcr0",    XSPR(31,339,936), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4793 {"mfupmc1",     XSPR(31,339,937), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4794 {"mfupmc2",     XSPR(31,339,938), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4795 {"mfusia",      XSPR(31,339,939), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4796 {"mfummcr1",    XSPR(31,339,940), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4797 {"mfupmc3",     XSPR(31,339,941), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4798 {"mfupmc4",     XSPR(31,339,942), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4799 {"mfzpr",       XSPR(31,339,944), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4800 {"mfpid",       XSPR(31,339,945), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4801 {"mfmmucr",     XSPR(31,339,946), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4802 {"mfccr0",      XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, PPCNONE,     {RT}},
4803 {"mfiac3",      XSPR(31,339,948), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4804 {"mfiac4",      XSPR(31,339,949), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4805 {"mfdvc1",      XSPR(31,339,950), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4806 {"mfdvc2",      XSPR(31,339,951), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4807 {"mfmmcr0",     XSPR(31,339,952), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4808 {"mfpmc1",      XSPR(31,339,953), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4809 {"mfsgr",       XSPR(31,339,953), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4810 {"mfdcwr",      XSPR(31,339,954), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4811 {"mfpmc2",      XSPR(31,339,954), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4812 {"mfsia",       XSPR(31,339,955), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4813 {"mfsler",      XSPR(31,339,955), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4814 {"mfmmcr1",     XSPR(31,339,956), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4815 {"mfsu0r",      XSPR(31,339,956), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4816 {"mfdbcr1",     XSPR(31,339,957), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4817 {"mfpmc3",      XSPR(31,339,957), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4818 {"mfpmc4",      XSPR(31,339,958), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4819 {"mficdbdr",    XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, PPCNONE,     {RT}},
4820 {"mfesr",       XSPR(31,339,980), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4821 {"mfdear",      XSPR(31,339,981), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4822 {"mfevpr",      XSPR(31,339,982), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4823 {"mfcdbcr",     XSPR(31,339,983), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4824 {"mftsr",       XSPR(31,339,984), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4825 {"mftcr",       XSPR(31,339,986), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4826 {"mfpit",       XSPR(31,339,987), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4827 {"mftbhi",      XSPR(31,339,988), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4828 {"mftblo",      XSPR(31,339,989), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4829 {"mfsrr2",      XSPR(31,339,990), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4830 {"mfsrr3",      XSPR(31,339,991), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4831 {"mfdbsr",      XSPR(31,339,1008), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4832 {"mfdbcr0",     XSPR(31,339,1010), XSPR_MASK, PPC405,   PPCNONE,        {RT}},
4833 {"mfdbdr",      XSPR(31,339,1011), XSPR_MASK, TITAN,    PPCNONE,        {RS}},
4834 {"mfiac1",      XSPR(31,339,1012), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4835 {"mfiac2",      XSPR(31,339,1013), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4836 {"mfdac1",      XSPR(31,339,1014), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4837 {"mfdac2",      XSPR(31,339,1015), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4838 {"mfl2cr",      XSPR(31,339,1017), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
4839 {"mfdccr",      XSPR(31,339,1018), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4840 {"mficcr",      XSPR(31,339,1019), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4841 {"mfictc",      XSPR(31,339,1019), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
4842 {"mfpbl1",      XSPR(31,339,1020), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4843 {"mfthrm1",     XSPR(31,339,1020), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
4844 {"mfpbu1",      XSPR(31,339,1021), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4845 {"mfthrm2",     XSPR(31,339,1021), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
4846 {"mfpbl2",      XSPR(31,339,1022), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4847 {"mfthrm3",     XSPR(31,339,1022), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
4848 {"mfpbu2",      XSPR(31,339,1023), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4849 {"mfspr",       X(31,339),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, SPR}},
4850
4851 {"lwax",        X(31,341),      X_MASK,      PPC64|PPCVLE, PPCNONE,     {RT, RA0, RB}},
4852
4853 {"dst",         XDSS(31,342,0), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
4854
4855 {"lhax",        X(31,343),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RA0, RB}},
4856
4857 {"lvxl",        X(31,359),      X_MASK,      PPCVEC,    PPCNONE,        {VD, RA0, RB}},
4858
4859 {"abs",         XO(31,360,0,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4860 {"abs.",        XO(31,360,0,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4861
4862 {"divs",        XO(31,363,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4863 {"divs.",       XO(31,363,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4864
4865 {"tlbia",       X(31,370),      0xffffffff,  PPC,       TITAN,          {0}},
4866
4867 {"mftbl",       XSPR(31,371,268), XSPR_MASK, PPC,       NO371,          {RT}},
4868 {"mftbu",       XSPR(31,371,269), XSPR_MASK, PPC,       NO371,          {RT}},
4869 {"mftb",        X(31,371),      X_MASK,      PPC|PPCA2, NO371|POWER7,   {RT, TBR}},
4870
4871 {"lwaux",       X(31,373),      X_MASK,      PPC64|PPCVLE, PPCNONE,     {RT, RAL, RB}},
4872
4873 {"dstst",       XDSS(31,374,0), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
4874
4875 {"lhaux",       X(31,375),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RAL, RB}},
4876
4877 {"popcntw",     X(31,378),      XRB_MASK, POWER7|PPCA2, PPCNONE,        {RA, RS}},
4878
4879 {"mtdcrx",      X(31,387),      X_MASK, BOOKE|PPCA2|PPC476, TITAN,      {RA, RS}},
4880 {"mtdcrx.",     XRC(31,387,1),  X_MASK,      PPCA2|PPCVLE, PPCNONE,     {RA, RS}},
4881
4882 {"stvexbx",     X(31,389),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
4883
4884 {"dcblc",       X(31,390),      X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
4885 {"stdfcmx",     APU(31,391,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4886
4887 {"divdeu",      XO(31,393,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4888 {"divdeu.",     XO(31,393,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4889 {"divweu",      XO(31,395,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4890 {"divweu.",     XO(31,395,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4891
4892 {"dcblce",      X(31,398),      X_MASK,      PPCCHLK,   E500MC,         {CT, RA, RB}},
4893
4894 {"slbmte",      X(31,402),      XRA_MASK,    PPC64,     PPCNONE,        {RS, RB}},
4895
4896 {"icswx",       XRC(31,406,0),  X_MASK,   POWER7|PPCA2, PPCNONE,        {RS, RA, RB}},
4897 {"icswx.",      XRC(31,406,1),  X_MASK,   POWER7|PPCA2, PPCNONE,        {RS, RA, RB}},
4898
4899 {"sthx",        X(31,407),      X_MASK,      COM|PPCVLE, PPCNONE,       {RS, RA0, RB}},
4900
4901 {"orc",         XRC(31,412,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4902 {"orc.",        XRC(31,412,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4903
4904 {"sthepx",      X(31,415),      X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
4905
4906 {"mtdcrux",     X(31,419),      X_MASK,      PPC464|PPCVLE, PPCNONE,    {RA, RS}},
4907
4908 {"stvexhx",     X(31,421),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
4909
4910 {"dcblq.",      XRC(31,422,1),  X_MASK,      E6500,     PPCNONE,        {CT, RA0, RB}},
4911
4912 {"divde",       XO(31,425,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4913 {"divde.",      XO(31,425,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4914 {"divwe",       XO(31,427,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4915 {"divwe.",      XO(31,427,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4916
4917 {"slbie",       X(31,434),      XRTRA_MASK,  PPC64,     PPCNONE,        {RB}},
4918
4919 {"ecowx",       X(31,438),      X_MASK,      PPC,       TITAN,          {RT, RA0, RB}},
4920
4921 {"sthux",       X(31,439),      X_MASK,      COM|PPCVLE, PPCNONE,       {RS, RAS, RB}},
4922
4923 {"mdors",       0x7f9ce378,     0xffffffff,  E500MC,    PPCNONE,        {0}},
4924
4925 {"miso",        0x7f5ad378,     0xffffffff,  E6500,     PPCNONE,        {0}},
4926
4927 {"mr",          XRC(31,444,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RBS}},
4928 {"or",          XRC(31,444,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4929 {"mr.",         XRC(31,444,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RBS}},
4930 {"or.",         XRC(31,444,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4931
4932 {"mtexisr",     XSPR(31,451, 64), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4933 {"mtexier",     XSPR(31,451, 66), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4934 {"mtbr0",       XSPR(31,451,128), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4935 {"mtbr1",       XSPR(31,451,129), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4936 {"mtbr2",       XSPR(31,451,130), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4937 {"mtbr3",       XSPR(31,451,131), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4938 {"mtbr4",       XSPR(31,451,132), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4939 {"mtbr5",       XSPR(31,451,133), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4940 {"mtbr6",       XSPR(31,451,134), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4941 {"mtbr7",       XSPR(31,451,135), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4942 {"mtbear",      XSPR(31,451,144), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4943 {"mtbesr",      XSPR(31,451,145), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4944 {"mtiocr",      XSPR(31,451,160), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4945 {"mtdmacr0",    XSPR(31,451,192), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4946 {"mtdmact0",    XSPR(31,451,193), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4947 {"mtdmada0",    XSPR(31,451,194), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4948 {"mtdmasa0",    XSPR(31,451,195), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4949 {"mtdmacc0",    XSPR(31,451,196), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4950 {"mtdmacr1",    XSPR(31,451,200), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4951 {"mtdmact1",    XSPR(31,451,201), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4952 {"mtdmada1",    XSPR(31,451,202), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4953 {"mtdmasa1",    XSPR(31,451,203), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4954 {"mtdmacc1",    XSPR(31,451,204), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4955 {"mtdmacr2",    XSPR(31,451,208), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4956 {"mtdmact2",    XSPR(31,451,209), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4957 {"mtdmada2",    XSPR(31,451,210), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4958 {"mtdmasa2",    XSPR(31,451,211), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4959 {"mtdmacc2",    XSPR(31,451,212), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4960 {"mtdmacr3",    XSPR(31,451,216), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4961 {"mtdmact3",    XSPR(31,451,217), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4962 {"mtdmada3",    XSPR(31,451,218), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4963 {"mtdmasa3",    XSPR(31,451,219), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4964 {"mtdmacc3",    XSPR(31,451,220), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4965 {"mtdmasr",     XSPR(31,451,224), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4966 {"mtdcr",       X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {SPR, RS}},
4967 {"mtdcr.",      XRC(31,451,1), X_MASK,       PPCA2,     PPCNONE,        {SPR, RS}},
4968
4969 {"stvexwx",     X(31,453),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
4970
4971 {"dccci",       X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
4972 {"dci",         X(31,454),      XRARB_MASK, PPCA2|PPC476|PPCVLE, PPCNONE, {CT}},
4973
4974 {"divdu",       XO(31,457,0,0), XO_MASK,  PPC64|PPCVLE, PPCNONE,        {RT, RA, RB}},
4975 {"divdu.",      XO(31,457,0,1), XO_MASK,  PPC64|PPCVLE, PPCNONE,        {RT, RA, RB}},
4976
4977 {"divwu",       XO(31,459,0,0), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4978 {"divwu.",      XO(31,459,0,1), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4979
4980 {"mtpmr",       X(31,462),      X_MASK, PPCPMR|PPCE300, PPCNONE,        {PMR, RS}},
4981 {"mttmr",       X(31,494),      X_MASK, PPCTMR|E6500,   PPCNONE,        {TMR, RS}},
4982
4983 {"mtmq",        XSPR(31,467,  0), XSPR_MASK, M601,      PPCNONE,        {RS}},
4984 {"mtxer",       XSPR(31,467,  1), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RS}},
4985 {"mtlr",        XSPR(31,467,  8), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RS}},
4986 {"mtctr",       XSPR(31,467,  9), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RS}},
4987 {"mttid",       XSPR(31,467, 17), XSPR_MASK, POWER,     PPCNONE,        {RS}},
4988 {"mtdsisr",     XSPR(31,467, 18), XSPR_MASK, COM,       TITAN,          {RS}},
4989 {"mtdar",       XSPR(31,467, 19), XSPR_MASK, COM,       TITAN,          {RS}},
4990 {"mtrtcu",      XSPR(31,467, 20), XSPR_MASK, COM,       TITAN,          {RS}},
4991 {"mtrtcl",      XSPR(31,467, 21), XSPR_MASK, COM,       TITAN,          {RS}},
4992 {"mtdec",       XSPR(31,467, 22), XSPR_MASK, COM,       PPCNONE,        {RS}},
4993 {"mtsdr0",      XSPR(31,467, 24), XSPR_MASK, POWER,     PPCNONE,        {RS}},
4994 {"mtsdr1",      XSPR(31,467, 25), XSPR_MASK, COM,       TITAN,          {RS}},
4995 {"mtsrr0",      XSPR(31,467, 26), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RS}},
4996 {"mtsrr1",      XSPR(31,467, 27), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RS}},
4997 {"mtcfar",      XSPR(31,467, 28), XSPR_MASK, POWER6,    PPCNONE,        {RS}},
4998 {"mtpid",       XSPR(31,467, 48), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
4999 {"mtdecar",     XSPR(31,467, 54), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5000 {"mtcsrr0",     XSPR(31,467, 58), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5001 {"mtcsrr1",     XSPR(31,467, 59), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5002 {"mtdear",      XSPR(31,467, 61), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5003 {"mtesr",       XSPR(31,467, 62), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5004 {"mtivpr",      XSPR(31,467, 63), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5005 {"mtcmpa",      XSPR(31,467,144), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5006 {"mtcmpb",      XSPR(31,467,145), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5007 {"mtcmpc",      XSPR(31,467,146), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5008 {"mtcmpd",      XSPR(31,467,147), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5009 {"mticr",       XSPR(31,467,148), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5010 {"mtder",       XSPR(31,467,149), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5011 {"mtcounta",    XSPR(31,467,150), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5012 {"mtcountb",    XSPR(31,467,151), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5013 {"mtcmpe",      XSPR(31,467,152), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5014 {"mtcmpf",      XSPR(31,467,153), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5015 {"mtcmpg",      XSPR(31,467,154), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5016 {"mtcmph",      XSPR(31,467,155), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5017 {"mtlctrl1",    XSPR(31,467,156), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5018 {"mtlctrl2",    XSPR(31,467,157), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5019 {"mtictrl",     XSPR(31,467,158), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5020 {"mtbar",       XSPR(31,467,159), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5021 {"mtvrsave",    XSPR(31,467,256), XSPR_MASK, PPCVEC,    PPCNONE,        {RS}},
5022 {"mtusprg0",    XSPR(31,467,256), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5023 {"mtsprg",      XSPR(31,467,256), XSPRG_MASK, PPC|PPCVLE, PPCNONE,      {SPRG, RS}},
5024 {"mtsprg0",     XSPR(31,467,272), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RS}},
5025 {"mtsprg1",     XSPR(31,467,273), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RS}},
5026 {"mtsprg2",     XSPR(31,467,274), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RS}},
5027 {"mtsprg3",     XSPR(31,467,275), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RS}},
5028 {"mtsprg4",     XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
5029 {"mtsprg5",     XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
5030 {"mtsprg6",     XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
5031 {"mtsprg7",     XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
5032 {"mtasr",       XSPR(31,467,280), XSPR_MASK, PPC64,     PPCNONE,        {RS}},
5033 {"mtear",       XSPR(31,467,282), XSPR_MASK, PPC,       TITAN,          {RS}},
5034 {"mttbl",       XSPR(31,467,284), XSPR_MASK, PPC,       PPCNONE,        {RS}},
5035 {"mttbu",       XSPR(31,467,285), XSPR_MASK, PPC,       PPCNONE,        {RS}},
5036 {"mtdbsr",      XSPR(31,467,304), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5037 {"mtdbcr0",     XSPR(31,467,308), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5038 {"mtdbcr1",     XSPR(31,467,309), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5039 {"mtdbcr2",     XSPR(31,467,310), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5040 {"mtiac1",      XSPR(31,467,312), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5041 {"mtiac2",      XSPR(31,467,313), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5042 {"mtiac3",      XSPR(31,467,314), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5043 {"mtiac4",      XSPR(31,467,315), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5044 {"mtdac1",      XSPR(31,467,316), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5045 {"mtdac2",      XSPR(31,467,317), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5046 {"mtdvc1",      XSPR(31,467,318), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5047 {"mtdvc2",      XSPR(31,467,319), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5048 {"mttsr",       XSPR(31,467,336), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5049 {"mttcr",       XSPR(31,467,340), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5050 {"mtivor0",     XSPR(31,467,400), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5051 {"mtivor1",     XSPR(31,467,401), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5052 {"mtivor2",     XSPR(31,467,402), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5053 {"mtivor3",     XSPR(31,467,403), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5054 {"mtivor4",     XSPR(31,467,404), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5055 {"mtivor5",     XSPR(31,467,405), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5056 {"mtivor6",     XSPR(31,467,406), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5057 {"mtivor7",     XSPR(31,467,407), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5058 {"mtivor8",     XSPR(31,467,408), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5059 {"mtivor9",     XSPR(31,467,409), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5060 {"mtivor10",    XSPR(31,467,410), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5061 {"mtivor11",    XSPR(31,467,411), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5062 {"mtivor12",    XSPR(31,467,412), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5063 {"mtivor13",    XSPR(31,467,413), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5064 {"mtivor14",    XSPR(31,467,414), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5065 {"mtivor15",    XSPR(31,467,415), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5066 {"mtspefscr",   XSPR(31,467,512), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
5067 {"mtbbear",     XSPR(31,467,513), XSPR_MASK, PPCBRLK,   PPCNONE,        {RS}},
5068 {"mtbbtar",     XSPR(31,467,514), XSPR_MASK, PPCBRLK,   PPCNONE,        {RS}},
5069 {"mtivor32",    XSPR(31,467,528), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
5070 {"mtibatu",     XSPR(31,467,528), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
5071 {"mtivor33",    XSPR(31,467,529), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
5072 {"mtibatl",     XSPR(31,467,529), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
5073 {"mtivor34",    XSPR(31,467,530), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
5074 {"mtivor35",    XSPR(31,467,531), XSPR_MASK, PPCPMR,    PPCNONE,        {RS}},
5075 {"mtdbatu",     XSPR(31,467,536), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
5076 {"mtdbatl",     XSPR(31,467,537), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
5077 {"mtmcsrr0",    XSPR(31,467,570), XSPR_MASK, PPCRFMCI|PPCVLE, PPCNONE,  {RS}},
5078 {"mtmcsrr1",    XSPR(31,467,571), XSPR_MASK, PPCRFMCI|PPCVLE, PPCNONE,  {RS}},
5079 {"mtmcsr",      XSPR(31,467,572), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RS}},
5080 {"mtivndx",     XSPR(31,467,880), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
5081 {"mtdvndx",     XSPR(31,467,881), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
5082 {"mtivlim",     XSPR(31,467,882), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
5083 {"mtdvlim",     XSPR(31,467,883), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
5084 {"mtclcsr",     XSPR(31,467,884), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
5085 {"mtccr1",      XSPR(31,467,888), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
5086 {"mtummcr0",    XSPR(31,467,936), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5087 {"mtupmc1",     XSPR(31,467,937), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5088 {"mtupmc2",     XSPR(31,467,938), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5089 {"mtusia",      XSPR(31,467,939), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5090 {"mtummcr1",    XSPR(31,467,940), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5091 {"mtupmc3",     XSPR(31,467,941), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5092 {"mtupmc4",     XSPR(31,467,942), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5093 {"mtzpr",       XSPR(31,467,944), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5094 {"mtpid",       XSPR(31,467,945), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5095 {"mtrmmucr",    XSPR(31,467,946), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
5096 {"mtccr0",      XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, PPCNONE,     {RS}},
5097 {"mtiac3",      XSPR(31,467,948), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
5098 {"mtiac4",      XSPR(31,467,949), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
5099 {"mtdvc1",      XSPR(31,467,950), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
5100 {"mtdvc2",      XSPR(31,467,951), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
5101 {"mtmmcr0",     XSPR(31,467,952), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5102 {"mtpmc1",      XSPR(31,467,953), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5103 {"mtsgr",       XSPR(31,467,953), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5104 {"mtdcwr",      XSPR(31,467,954), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5105 {"mtpmc2",      XSPR(31,467,954), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5106 {"mtsia",       XSPR(31,467,955), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5107 {"mtsler",      XSPR(31,467,955), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
5108 {"mtmmcr1",     XSPR(31,467,956), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5109 {"mtsu0r",      XSPR(31,467,956), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
5110 {"mtdbcr1",     XSPR(31,467,957), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
5111 {"mtpmc3",      XSPR(31,467,957), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5112 {"mtpmc4",      XSPR(31,467,958), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5113 {"mticdbdr",    XSPR(31,467,979), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5114 {"mtesr",       XSPR(31,467,980), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5115 {"mtdear",      XSPR(31,467,981), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5116 {"mtevpr",      XSPR(31,467,982), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5117 {"mtcdbcr",     XSPR(31,467,983), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5118 {"mttsr",       XSPR(31,467,984), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5119 {"mttcr",       XSPR(31,467,986), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5120 {"mtpit",       XSPR(31,467,987), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5121 {"mttbhi",      XSPR(31,467,988), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5122 {"mttblo",      XSPR(31,467,989), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5123 {"mtsrr2",      XSPR(31,467,990), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5124 {"mtsrr3",      XSPR(31,467,991), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5125 {"mtdbsr",      XSPR(31,467,1008), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5126 {"mtdbdr",      XSPR(31,467,1011), XSPR_MASK, TITAN,    PPCNONE,        {RS}},
5127 {"mtdbcr0",     XSPR(31,467,1010), XSPR_MASK, PPC405,   PPCNONE,        {RS}},
5128 {"mtiac1",      XSPR(31,467,1012), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5129 {"mtiac2",      XSPR(31,467,1013), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5130 {"mtdac1",      XSPR(31,467,1014), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5131 {"mtdac2",      XSPR(31,467,1015), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5132 {"mtl2cr",      XSPR(31,467,1017), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
5133 {"mtdccr",      XSPR(31,467,1018), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5134 {"mticcr",      XSPR(31,467,1019), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5135 {"mtictc",      XSPR(31,467,1019), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
5136 {"mtpbl1",      XSPR(31,467,1020), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5137 {"mtthrm1",     XSPR(31,467,1020), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
5138 {"mtpbu1",      XSPR(31,467,1021), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5139 {"mtthrm2",     XSPR(31,467,1021), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
5140 {"mtpbl2",      XSPR(31,467,1022), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5141 {"mtthrm3",     XSPR(31,467,1022), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
5142 {"mtpbu2",      XSPR(31,467,1023), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5143 {"mtspr",       X(31,467),      X_MASK,      COM|PPCVLE, PPCNONE,       {SPR, RS}},
5144
5145 {"dcbi",        X(31,470),      XRT_MASK,    PPC|PPCVLE, PPCNONE,       {RA0, RB}},
5146
5147 {"nand",        XRC(31,476,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
5148 {"nand.",       XRC(31,476,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
5149
5150 {"dsn",         X(31,483),      XRT_MASK,    E500MC,    PPCNONE,        {RA, RB}},
5151
5152 {"dcread",      X(31,486),      X_MASK,  PPC403|PPC440, PPCA2|PPC476,   {RT, RA0, RB}},
5153
5154 {"icbtls",      X(31,486),      X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
5155
5156 {"stvxl",       X(31,487),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA0, RB}},
5157
5158 {"nabs",        XO(31,488,0,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
5159 {"nabs.",       XO(31,488,0,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
5160
5161 {"divd",        XO(31,489,0,0), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
5162 {"divd.",       XO(31,489,0,1), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
5163
5164 {"divw",        XO(31,491,0,0), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
5165 {"divw.",       XO(31,491,0,1), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
5166
5167 {"icbtlse",     X(31,494),      X_MASK,      PPCCHLK,   E500MC,         {CT, RA, RB}},
5168
5169 {"slbia",       X(31,498),      0xffffffff,  PPC64,     PPCNONE,        {0}},
5170
5171 {"cli",         X(31,502),      XRB_MASK,    POWER,     PPCNONE,        {RT, RA}},
5172
5173 {"popcntd",     X(31,506),      XRB_MASK, POWER7|PPCA2, PPCNONE,        {RA, RS}},
5174
5175 {"cmpb",        X(31,508),      X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {RA, RS, RB}},
5176
5177 {"mcrxr",       X(31,512), XRARB_MASK|(3<<21), COM,     POWER7,         {BF}},
5178
5179 {"lbdx",        X(31,515),      X_MASK,      E500MC,    PPCNONE,        {RT, RA, RB}},
5180
5181 {"bblels",      X(31,518),      X_MASK,      PPCBRLK,   PPCNONE,        {0}},
5182
5183 {"lvlx",        X(31,519),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
5184 {"lbfcmux",     APU(31,519,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5185
5186 {"subfco",      XO(31,8,1,0),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
5187 {"sfo",         XO(31,8,1,0),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5188 {"subco",       XO(31,8,1,0),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RB, RA}},
5189 {"subfco.",     XO(31,8,1,1),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
5190 {"sfo.",        XO(31,8,1,1),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5191 {"subco.",      XO(31,8,1,1),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RB, RA}},
5192
5193 {"addco",       XO(31,10,1,0),  XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
5194 {"ao",          XO(31,10,1,0),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5195 {"addco.",      XO(31,10,1,1),  XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
5196 {"ao.",         XO(31,10,1,1),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5197
5198 {"clcs",        X(31,531),      XRB_MASK,    M601,      PPCNONE,        {RT, RA}},
5199
5200 {"ldbrx",       X(31,532),      X_MASK, CELL|POWER7|PPCA2, PPCNONE,     {RT, RA0, RB}},
5201
5202 {"lswx",        X(31,533),      X_MASK,  PPCCOM|PPCVLE, E500|E500MC,    {RT, RA0, RB}},
5203 {"lsx",         X(31,533),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
5204
5205 {"lwbrx",       X(31,534),      X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RT, RA0, RB}},
5206 {"lbrx",        X(31,534),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
5207
5208 {"lfsx",        X(31,535),      X_MASK,      COM,       PPCEFS,         {FRT, RA0, RB}},
5209
5210 {"srw",         XRC(31,536,0),  X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RA, RS, RB}},
5211 {"sr",          XRC(31,536,0),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
5212 {"srw.",        XRC(31,536,1),  X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RA, RS, RB}},
5213 {"sr.",         XRC(31,536,1),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
5214
5215 {"rrib",        XRC(31,537,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5216 {"rrib.",       XRC(31,537,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5217
5218 {"srd",         XRC(31,539,0),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
5219 {"srd.",        XRC(31,539,1),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
5220
5221 {"maskir",      XRC(31,541,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5222 {"maskir.",     XRC(31,541,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5223
5224 {"lhdx",        X(31,547),      X_MASK,      E500MC,    PPCNONE,        {RT, RA, RB}},
5225
5226 {"lvtrx",       X(31,549),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
5227
5228 {"bbelr",       X(31,550),      X_MASK,      PPCBRLK,   PPCNONE,        {0}},
5229
5230 {"lvrx",        X(31,551),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
5231 {"lhfcmux",     APU(31,551,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5232
5233 {"subfo",       XO(31,40,1,0),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
5234 {"subo",        XO(31,40,1,0),  XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
5235 {"subfo.",      XO(31,40,1,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
5236 {"subo.",       XO(31,40,1,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
5237
5238 {"tlbsync",     X(31,566),      0xffffffff, PPC|PPCVLE, PPCNONE,        {0}},
5239
5240 {"lfsux",       X(31,567),      X_MASK,      COM,       PPCEFS,         {FRT, RAS, RB}},
5241
5242 {"lwdx",        X(31,579),      X_MASK,      E500MC,    PPCNONE,        {RT, RA, RB}},
5243
5244 {"lvtlx",       X(31,581),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
5245
5246 {"lwfcmux",     APU(31,583,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5247
5248 {"lxsdx",       X(31,588),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA0, RB}},
5249
5250 {"mfsr",        X(31,595), XRB_MASK|(1<<20), COM,       NON32,          {RT, SR}},
5251
5252 {"lswi",        X(31,597),      X_MASK,  PPCCOM|PPCVLE, E500|E500MC,    {RT, RA0, NB}},
5253 {"lsi",         X(31,597),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA0, NB}},
5254
5255 {"lwsync",      XSYNC(31,598,1), 0xffffffff, PPC,       E500,           {0}},
5256 {"ptesync",     XSYNC(31,598,2), 0xffffffff, PPC64,     PPCNONE,        {0}},
5257 {"sync",        X(31,598),      XSYNCLE_MASK,E6500,     PPCNONE,        {LS, ESYNC}},
5258 {"sync",        X(31,598),      XSYNC_MASK, PPCCOM|PPCVLE, BOOKE|PPC476, {LS}},
5259 {"msync",       X(31,598),      0xffffffff, BOOKE|PPCA2|PPC476, PPCNONE, {0}},
5260 {"sync",        X(31,598),      0xffffffff, BOOKE|PPC476, E6500,        {0}},
5261 {"lwsync",      X(31,598),      0xffffffff, E500,       PPCNONE,        {0}},
5262 {"dcs",         X(31,598),      0xffffffff,  PWRCOM,    PPCNONE,        {0}},
5263
5264 {"lfdx",        X(31,599),      X_MASK,      COM,       PPCEFS,         {FRT, RA0, RB}},
5265
5266 {"mffgpr",      XRC(31,607,0),  XRA_MASK,    POWER6,    POWER7,         {FRT, RB}},
5267 {"lfdepx",      X(31,607),      X_MASK,   E500MC|PPCA2|PPCVLE, PPCNONE, {FRT, RA0, RB}},
5268
5269 {"lddx",        X(31,611),      X_MASK,      E500MC,    PPCNONE,        {RT, RA, RB}},
5270
5271 {"lvswx",       X(31,613),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
5272
5273 {"lqfcmux",     APU(31,615,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5274
5275 {"nego",        XO(31,104,1,0), XORB_MASK,   COM,       PPCNONE,        {RT, RA}},
5276 {"nego.",       XO(31,104,1,1), XORB_MASK,   COM,       PPCNONE,        {RT, RA}},
5277
5278 {"mulo",        XO(31,107,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5279 {"mulo.",       XO(31,107,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5280
5281 {"mfsri",       X(31,627),      X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
5282
5283 {"dclst",       X(31,630),      XRB_MASK,    M601,      PPCNONE,        {RS, RA}},
5284
5285 {"lfdux",       X(31,631),      X_MASK,      COM,       PPCEFS,         {FRT, RAS, RB}},
5286
5287 {"stbdx",       X(31,643),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
5288
5289 {"stvlx",       X(31,647),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
5290 {"stbfcmux",    APU(31,647,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5291
5292 {"subfeo",      XO(31,136,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE,        {RT, RA, RB}},
5293 {"sfeo",        XO(31,136,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5294 {"subfeo.",     XO(31,136,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE,        {RT, RA, RB}},
5295 {"sfeo.",       XO(31,136,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5296
5297 {"addeo",       XO(31,138,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE,        {RT, RA, RB}},
5298 {"aeo",         XO(31,138,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5299 {"addeo.",      XO(31,138,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE,        {RT, RA, RB}},
5300 {"aeo.",        XO(31,138,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5301
5302 {"mfsrin",      X(31,659),      XRA_MASK,    PPC,       NON32,          {RT, RB}},
5303
5304 {"stdbrx",      X(31,660),      X_MASK, CELL|POWER7|PPCA2, PPCNONE,     {RS, RA0, RB}},
5305
5306 {"stswx",       X(31,661),      X_MASK, PPCCOM|PPCVLE,  E500|E500MC,    {RS, RA0, RB}},
5307 {"stsx",        X(31,661),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, RB}},
5308
5309 {"stwbrx",      X(31,662),      X_MASK, PPCCOM|PPCVLE,  PPCNONE,        {RS, RA0, RB}},
5310 {"stbrx",       X(31,662),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, RB}},
5311
5312 {"stfsx",       X(31,663),      X_MASK,      COM,       PPCEFS,         {FRS, RA0, RB}},
5313
5314 {"srq",         XRC(31,664,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5315 {"srq.",        XRC(31,664,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5316
5317 {"sre",         XRC(31,665,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5318 {"sre.",        XRC(31,665,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5319
5320 {"sthdx",       X(31,675),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
5321
5322 {"stvfrx",      X(31,677),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5323
5324 {"stvrx",       X(31,679),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
5325 {"sthfcmux",    APU(31,679,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5326
5327 {"stbcx.",      XRC(31,694,1),  X_MASK,      POWER7,    PPCNONE,        {RS, RA0, RB}},
5328
5329 {"stfsux",      X(31,695),      X_MASK,      COM,       PPCEFS,         {FRS, RAS, RB}},
5330
5331 {"sriq",        XRC(31,696,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
5332 {"sriq.",       XRC(31,696,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
5333
5334 {"stwdx",       X(31,707),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
5335
5336 {"stvflx",      X(31,709),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5337
5338 {"stwfcmux",    APU(31,711,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5339
5340 {"stxsdx",      X(31,716),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA0, RB}},
5341
5342 {"subfzeo",     XO(31,200,1,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE,      {RT, RA}},
5343 {"sfzeo",       XO(31,200,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5344 {"subfzeo.",    XO(31,200,1,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE,      {RT, RA}},
5345 {"sfzeo.",      XO(31,200,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5346
5347 {"addzeo",      XO(31,202,1,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE,      {RT, RA}},
5348 {"azeo",        XO(31,202,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5349 {"addzeo.",     XO(31,202,1,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE,      {RT, RA}},
5350 {"azeo.",       XO(31,202,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5351
5352 {"stswi",       X(31,725),      X_MASK, PPCCOM|PPCVLE,  E500|E500MC,    {RS, RA0, NB}},
5353 {"stsi",        X(31,725),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, NB}},
5354
5355 {"sthcx.",      XRC(31,726,1),  X_MASK,      POWER7,    PPCNONE,        {RS, RA0, RB}},
5356
5357 {"stfdx",       X(31,727),      X_MASK,      COM,       PPCEFS,         {FRS, RA0, RB}},
5358
5359 {"srlq",        XRC(31,728,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5360 {"srlq.",       XRC(31,728,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5361
5362 {"sreq",        XRC(31,729,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5363 {"sreq.",       XRC(31,729,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5364
5365 {"mftgpr",      XRC(31,735,0),  XRA_MASK,    POWER6,    POWER7,         {RT, FRB}},
5366 {"stfdepx",     X(31,735),      X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE,   {FRS, RA0, RB}},
5367
5368 {"stddx",       X(31,739),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
5369
5370 {"stvswx",      X(31,741),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5371
5372 {"stqfcmux",    APU(31,743,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5373
5374 {"subfmeo",     XO(31,232,1,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
5375 {"sfmeo",       XO(31,232,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5376 {"subfmeo.",    XO(31,232,1,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
5377 {"sfmeo.",      XO(31,232,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5378
5379 {"mulldo",      XO(31,233,1,0), XO_MASK,  PPC64|PPCVLE, PPCNONE,        {RT, RA, RB}},
5380 {"mulldo.",     XO(31,233,1,1), XO_MASK,  PPC64|PPCVLE, PPCNONE,        {RT, RA, RB}},
5381
5382 {"addmeo",      XO(31,234,1,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
5383 {"ameo",        XO(31,234,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5384 {"addmeo.",     XO(31,234,1,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
5385 {"ameo.",       XO(31,234,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5386
5387 {"mullwo",      XO(31,235,1,0), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
5388 {"mulso",       XO(31,235,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5389 {"mullwo.",     XO(31,235,1,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
5390 {"mulso.",      XO(31,235,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5391
5392 {"dcba",        X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, PPCNONE, {RA0, RB}},
5393 {"dcbal",       XOPL(31,758,1), XRT_MASK,    E500MC,    PPCNONE,        {RA0, RB}},
5394
5395 {"stfdux",      X(31,759),      X_MASK,      COM,       PPCEFS,         {FRS, RAS, RB}},
5396
5397 {"srliq",       XRC(31,760,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
5398 {"srliq.",      XRC(31,760,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
5399
5400 {"lvsm",        X(31,773),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
5401 {"stvepxl",     X(31,775),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5402 {"lvlxl",       X(31,775),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
5403 {"ldfcmux",     APU(31,775,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5404
5405 {"dozo",        XO(31,264,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5406 {"dozo.",       XO(31,264,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5407
5408 {"addo",        XO(31,266,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE,        {RT, RA, RB}},
5409 {"caxo",        XO(31,266,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5410 {"addo.",       XO(31,266,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE,        {RT, RA, RB}},
5411 {"caxo.",       XO(31,266,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5412
5413 {"lxvw4x",      X(31,780),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA0, RB}},
5414
5415 {"tlbivax",     X(31,786),      XRT_MASK, BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RA0, RB}},
5416
5417 {"lwzcix",      X(31,789),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
5418
5419 {"lhbrx",       X(31,790),      X_MASK,      COM,       PPCNONE,        {RT, RA0, RB}},
5420
5421 {"lfdpx",       X(31,791),      X_MASK,      POWER6,    POWER7,         {FRTp, RA0, RB}},
5422 {"lfqx",        X(31,791),      X_MASK,      POWER2,    PPCNONE,        {FRT, RA, RB}},
5423
5424 {"sraw",        XRC(31,792,0),  X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RA, RS, RB}},
5425 {"sra",         XRC(31,792,0),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
5426 {"sraw.",       XRC(31,792,1),  X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RA, RS, RB}},
5427 {"sra.",        XRC(31,792,1),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
5428
5429 {"srad",        XRC(31,794,0),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
5430 {"srad.",       XRC(31,794,1),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
5431
5432 {"lfddx",       X(31,803),      X_MASK,      E500MC,    PPCNONE,        {FRT, RA, RB}},
5433
5434 {"lvtrxl",      X(31,805),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
5435 {"stvepx",      X(31,807),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5436 {"lvrxl",       X(31,807),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
5437
5438 {"rac",         X(31,818),      X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
5439
5440 {"erativax",    X(31,819),      X_MASK,      PPCA2,     PPCNONE,        {RS, RA0, RB}},
5441
5442 {"lhzcix",      X(31,821),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
5443
5444 {"dss",         XDSS(31,822,0), XDSS_MASK,   PPCVEC,    PPCNONE,        {STRM}},
5445
5446 {"lfqux",       X(31,823),      X_MASK,      POWER2,    PPCNONE,        {FRT, RA, RB}},
5447
5448 {"srawi",       XRC(31,824,0),  X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RA, RS, SH}},
5449 {"srai",        XRC(31,824,0),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH}},
5450 {"srawi.",      XRC(31,824,1),  X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RA, RS, SH}},
5451 {"srai.",       XRC(31,824,1),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH}},
5452
5453 {"sradi",       XS(31,413,0),   XS_MASK,     PPC64|PPCVLE, PPCNONE,     {RA, RS, SH6}},
5454 {"sradi.",      XS(31,413,1),   XS_MASK,     PPC64|PPCVLE, PPCNONE,     {RA, RS, SH6}},
5455
5456 {"lvtlxl",      X(31,837),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
5457
5458 {"divo",        XO(31,331,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5459 {"divo.",       XO(31,331,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5460
5461 {"lxvd2x",      X(31,844),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA0, RB}},
5462
5463 {"tlbsrx.",     XRC(31,850,1),  XRT_MASK,    PPCA2,     PPCNONE,        {RA0, RB}},
5464
5465 {"slbmfev",     X(31,851),      XRA_MASK,    PPC64,     PPCNONE,        {RT, RB}},
5466
5467 {"lbzcix",      X(31,853),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
5468
5469 {"eieio",       X(31,854),      0xffffffff,  PPC,   BOOKE|PPCA2|PPC476, {0}},
5470 {"mbar",        X(31,854),      X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {MO}},
5471 {"eieio",       XMBAR(31,854,1),0xffffffff,  E500,      PPCNONE,        {0}},
5472 {"eieio",       X(31,854),      0xffffffff, PPCA2|PPC476, PPCNONE,      {0}},
5473
5474 {"lfiwax",      X(31,855),      X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, RA0, RB}},
5475
5476 {"lvswxl",      X(31,869),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
5477
5478 {"abso",        XO(31,360,1,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
5479 {"abso.",       XO(31,360,1,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
5480
5481 {"divso",       XO(31,363,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5482 {"divso.",      XO(31,363,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5483
5484 {"ldcix",       X(31,885),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
5485
5486 {"lfiwzx",      X(31,887),      X_MASK,   POWER7|PPCA2, PPCNONE,        {FRT, RA0, RB}},
5487
5488 {"stvlxl",      X(31,903),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
5489 {"stdfcmux",    APU(31,903,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5490
5491 {"divdeuo",     XO(31,393,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5492 {"divdeuo.",    XO(31,393,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5493 {"divweuo",     XO(31,395,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5494 {"divweuo.",    XO(31,395,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5495
5496 {"stxvw4x",     X(31,908),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA0, RB}},
5497
5498 {"tlbsx",       XRC(31,914,0),  X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA0, RB}},
5499 {"tlbsx.",      XRC(31,914,1),  X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA0, RB}},
5500
5501 {"slbmfee",     X(31,915),      XRA_MASK,    PPC64,     PPCNONE,        {RT, RB}},
5502
5503 {"stwcix",      X(31,917),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
5504
5505 {"sthbrx",      X(31,918),      X_MASK,      COM,       PPCNONE,        {RS, RA0, RB}},
5506
5507 {"stfdpx",      X(31,919),      X_MASK,      POWER6,    POWER7,         {FRSp, RA0, RB}},
5508 {"stfqx",       X(31,919),      X_MASK,      POWER2,    PPCNONE,        {FRS, RA0, RB}},
5509
5510 {"sraq",        XRC(31,920,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5511 {"sraq.",       XRC(31,920,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5512
5513 {"srea",        XRC(31,921,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5514 {"srea.",       XRC(31,921,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5515
5516 {"extsh",       XRC(31,922,0),  XRB_MASK,    PPCCOM|PPCVLE, PPCNONE,    {RA, RS}},
5517 {"exts",        XRC(31,922,0),  XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
5518 {"extsh.",      XRC(31,922,1),  XRB_MASK,    PPCCOM|PPCVLE, PPCNONE,    {RA, RS}},
5519 {"exts.",       XRC(31,922,1),  XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
5520
5521 {"stfddx",      X(31,931),      X_MASK,      E500MC,    PPCNONE,        {FRS, RA, RB}},
5522
5523 {"stvfrxl",     X(31,933),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5524
5525 {"wclrone",     XOPL2(31,934,2),XRT_MASK,    PPCA2,     PPCNONE,        {RA0, RB}},
5526 {"wclrall",     X(31,934),      XRARB_MASK,  PPCA2,     PPCNONE,        {L}},
5527 {"wclr",        X(31,934),      X_MASK,      PPCA2,     PPCNONE,        {L, RA0, RB}},
5528
5529 {"stvrxl",      X(31,935),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
5530
5531 {"divdeo",      XO(31,425,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5532 {"divdeo.",     XO(31,425,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5533 {"divweo",      XO(31,427,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5534 {"divweo.",     XO(31,427,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5535
5536 {"tlbrehi",     XTLB(31,946,0), XTLB_MASK,   PPC403,    PPCA2,          {RT, RA}},
5537 {"tlbrelo",     XTLB(31,946,1), XTLB_MASK,   PPC403,    PPCA2,          {RT, RA}},
5538 {"tlbre",       X(31,946),      X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
5539
5540 {"sthcix",      X(31,949),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
5541
5542 {"icswepx",     XRC(31,950,0),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA, RB}},
5543 {"icswepx.",    XRC(31,950,1),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA, RB}},
5544
5545 {"stfqux",      X(31,951),      X_MASK,      POWER2,    PPCNONE,        {FRS, RA, RB}},
5546
5547 {"sraiq",       XRC(31,952,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
5548 {"sraiq.",      XRC(31,952,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
5549
5550 {"extsb",       XRC(31,954,0),  XRB_MASK, PPC|PPCVLE,   PPCNONE,        {RA, RS}},
5551 {"extsb.",      XRC(31,954,1),  XRB_MASK, PPC|PPCVLE,   PPCNONE,        {RA, RS}},
5552
5553 {"stvflxl",     X(31,965),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5554
5555 {"iccci",       X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
5556 {"ici",         X(31,966),      XRARB_MASK,  PPCA2|PPC476|PPCVLE, PPCNONE, {CT}},
5557
5558 {"divduo",      XO(31,457,1,0), XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
5559 {"divduo.",     XO(31,457,1,1), XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
5560
5561 {"divwuo",      XO(31,459,1,0), XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
5562 {"divwuo.",     XO(31,459,1,1), XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
5563
5564 {"stxvd2x",     X(31,972),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA0, RB}},
5565
5566 {"tlbld",       X(31,978),      XRTRA_MASK,  PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
5567 {"tlbwehi",     XTLB(31,978,0), XTLB_MASK,   PPC403,    PPCNONE,        {RT, RA}},
5568 {"tlbwelo",     XTLB(31,978,1), XTLB_MASK,   PPC403,    PPCNONE,        {RT, RA}},
5569 {"tlbwe",       X(31,978),      X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
5570
5571 {"stbcix",      X(31,981),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
5572
5573 {"icbi",        X(31,982),      XRT_MASK,    PPC,       PPCNONE,        {RA0, RB}},
5574
5575 {"stfiwx",      X(31,983),      X_MASK,      PPC,       PPCEFS,         {FRS, RA0, RB}},
5576
5577 {"extsw",       XRC(31,986,0),  XRB_MASK, PPC64|PPCVLE, PPCNONE,        {RA, RS}},
5578 {"extsw.",      XRC(31,986,1),  XRB_MASK, PPC64|PPCVLE, PPCNONE,        {RA, RS}},
5579
5580 {"icbiep",      XRT(31,991,0),  XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
5581
5582 {"stvswxl",     X(31,997),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5583
5584 {"icread",      X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCVLE, PPCNONE, {RA0, RB}},
5585
5586 {"nabso",       XO(31,488,1,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
5587 {"nabso.",      XO(31,488,1,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
5588
5589 {"divdo",       XO(31,489,1,0), XO_MASK,  PPC64|PPCVLE, PPCNONE,        {RT, RA, RB}},
5590 {"divdo.",      XO(31,489,1,1), XO_MASK,  PPC64|PPCVLE, PPCNONE,        {RT, RA, RB}},
5591
5592 {"divwo",       XO(31,491,1,0), XO_MASK,   PPC|PPCVLE,  PPCNONE,        {RT, RA, RB}},
5593 {"divwo.",      XO(31,491,1,1), XO_MASK,   PPC|PPCVLE,  PPCNONE,        {RT, RA, RB}},
5594
5595
5596 {"tlbli",       X(31,1010),     XRTRA_MASK,  PPC,       TITAN,          {RB}},
5597
5598 {"stdcix",      X(31,1013),     X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
5599
5600 {"dcbz",        X(31,1014),     XRT_MASK,    PPC,       PPCNONE,        {RA0, RB}},
5601 {"dclz",        X(31,1014),     XRT_MASK,    PPC,       PPCNONE,        {RA0, RB}},
5602
5603 {"dcbzep",      XRT(31,1023,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
5604
5605 {"dcbzl",       XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476,       {RA0, RB}},
5606
5607 {"cctpl",       0x7c210b78,     0xffffffff,  CELL,      PPCNONE,        {0}},
5608 {"cctpm",       0x7c421378,     0xffffffff,  CELL,      PPCNONE,        {0}},
5609 {"cctph",       0x7c631b78,     0xffffffff,  CELL,      PPCNONE,        {0}},
5610
5611 {"dstt",        XDSS(31,342,1), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
5612 {"dststt",      XDSS(31,374,1), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
5613 {"dssall",      XDSS(31,822,1), XDSS_MASK,   PPCVEC,    PPCNONE,        {0}},
5614
5615 {"db8cyc",      0x7f9ce378,     0xffffffff,  CELL,      PPCNONE,        {0}},
5616 {"db10cyc",     0x7fbdeb78,     0xffffffff,  CELL,      PPCNONE,        {0}},
5617 {"db12cyc",     0x7fdef378,     0xffffffff,  CELL,      PPCNONE,        {0}},
5618 {"db16cyc",     0x7ffffb78,     0xffffffff,  CELL,      PPCNONE,        {0}},
5619
5620 {"lwz",         OP(32),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RA0}},
5621 {"l",           OP(32),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
5622
5623 {"lwzu",        OP(33),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RAL}},
5624 {"lu",          OP(33),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
5625
5626 {"lbz",         OP(34),         OP_MASK,     COM,       PPCNONE,        {RT, D, RA0}},
5627
5628 {"lbzu",        OP(35),         OP_MASK,     COM,       PPCNONE,        {RT, D, RAL}},
5629
5630 {"stw",         OP(36),         OP_MASK,     PPCCOM,    PPCNONE,        {RS, D, RA0}},
5631 {"st",          OP(36),         OP_MASK,     PWRCOM,    PPCNONE,        {RS, D, RA0}},
5632
5633 {"stwu",        OP(37),         OP_MASK,     PPCCOM,    PPCNONE,        {RS, D, RAS}},
5634 {"stu",         OP(37),         OP_MASK,     PWRCOM,    PPCNONE,        {RS, D, RA0}},
5635
5636 {"stb",         OP(38),         OP_MASK,     COM,       PPCNONE,        {RS, D, RA0}},
5637
5638 {"stbu",        OP(39),         OP_MASK,     COM,       PPCNONE,        {RS, D, RAS}},
5639
5640 {"lhz",         OP(40),         OP_MASK,     COM,       PPCNONE,        {RT, D, RA0}},
5641
5642 {"lhzu",        OP(41),         OP_MASK,     COM,       PPCNONE,        {RT, D, RAL}},
5643
5644 {"lha",         OP(42),         OP_MASK,     COM,       PPCNONE,        {RT, D, RA0}},
5645
5646 {"lhau",        OP(43),         OP_MASK,     COM,       PPCNONE,        {RT, D, RAL}},
5647
5648 {"sth",         OP(44),         OP_MASK,     COM,       PPCNONE,        {RS, D, RA0}},
5649
5650 {"sthu",        OP(45),         OP_MASK,     COM,       PPCNONE,        {RS, D, RAS}},
5651
5652 {"lmw",         OP(46),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RAM}},
5653 {"lm",          OP(46),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
5654
5655 {"stmw",        OP(47),         OP_MASK,     PPCCOM,    PPCNONE,        {RS, D, RA0}},
5656 {"stm",         OP(47),         OP_MASK,     PWRCOM,    PPCNONE,        {RS, D, RA0}},
5657
5658 {"lfs",         OP(48),         OP_MASK,     COM,       PPCEFS,         {FRT, D, RA0}},
5659
5660 {"lfsu",        OP(49),         OP_MASK,     COM,       PPCEFS,         {FRT, D, RAS}},
5661
5662 {"lfd",         OP(50),         OP_MASK,     COM,       PPCEFS,         {FRT, D, RA0}},
5663
5664 {"lfdu",        OP(51),         OP_MASK,     COM,       PPCEFS,         {FRT, D, RAS}},
5665
5666 {"stfs",        OP(52),         OP_MASK,     COM,       PPCEFS,         {FRS, D, RA0}},
5667
5668 {"stfsu",       OP(53),         OP_MASK,     COM,       PPCEFS,         {FRS, D, RAS}},
5669
5670 {"stfd",        OP(54),         OP_MASK,     COM,       PPCEFS,         {FRS, D, RA0}},
5671
5672 {"stfdu",       OP(55),         OP_MASK,     COM,       PPCEFS,         {FRS, D, RAS}},
5673
5674 {"lq",          OP(56),         OP_MASK,     POWER4,    PPC476,         {RTQ, DQ, RAQ}},
5675 {"psq_l",       OP(56),         OP_MASK,     PPCPS,     PPCNONE,        {FRT,PSD,RA,PSW,PSQ}},
5676 {"lfq",         OP(56),         OP_MASK,     POWER2,    PPCNONE,        {FRT, D, RA0}},
5677
5678 {"lfdp",        OP(57),         OP_MASK,     POWER6,    POWER7,         {FRTp, D, RA0}},
5679 {"psq_lu",      OP(57),         OP_MASK,     PPCPS,     PPCNONE,        {FRT,PSD,RA,PSW,PSQ}},
5680 {"lfqu",        OP(57),         OP_MASK,     POWER2,    PPCNONE,        {FRT, D, RA0}},
5681
5682 {"ld",          DSO(58,0),      DS_MASK,     PPC64,     PPCNONE,        {RT, DS, RA0}},
5683 {"ldu",         DSO(58,1),      DS_MASK,     PPC64,     PPCNONE,        {RT, DS, RAL}},
5684 {"lwa",         DSO(58,2),      DS_MASK,     PPC64,     PPCNONE,        {RT, DS, RA0}},
5685
5686 {"dadd",        XRC(59,2,0),    X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5687 {"dadd.",       XRC(59,2,1),    X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5688
5689 {"dqua",        ZRC(59,3,0),    Z2_MASK,     POWER6,    PPCNONE,        {FRT,FRA,FRB,RMC}},
5690 {"dqua.",       ZRC(59,3,1),    Z2_MASK,     POWER6,    PPCNONE,        {FRT,FRA,FRB,RMC}},
5691
5692 {"fdivs",       A(59,18,0),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
5693 {"fdivs.",      A(59,18,1),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
5694
5695 {"fsubs",       A(59,20,0),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
5696 {"fsubs.",      A(59,20,1),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
5697
5698 {"fadds",       A(59,21,0),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
5699 {"fadds.",      A(59,21,1),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
5700
5701 {"fsqrts",      A(59,22,0),    AFRAFRC_MASK, PPC,       TITAN,          {FRT, FRB}},
5702 {"fsqrts.",     A(59,22,1),    AFRAFRC_MASK, PPC,       TITAN,          {FRT, FRB}},
5703
5704 {"fres",        A(59,24,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
5705 {"fres",        A(59,24,0),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
5706 {"fres.",       A(59,24,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
5707 {"fres.",       A(59,24,1),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
5708
5709 {"fmuls",       A(59,25,0),     AFRB_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRC}},
5710 {"fmuls.",      A(59,25,1),     AFRB_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRC}},
5711
5712 {"frsqrtes",    A(59,26,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
5713 {"frsqrtes",    A(59,26,0),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
5714 {"frsqrtes.",   A(59,26,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
5715 {"frsqrtes.",   A(59,26,1),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
5716
5717 {"fmsubs",      A(59,28,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
5718 {"fmsubs.",     A(59,28,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
5719
5720 {"fmadds",      A(59,29,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
5721 {"fmadds.",     A(59,29,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
5722
5723 {"fnmsubs",     A(59,30,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
5724 {"fnmsubs.",    A(59,30,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
5725
5726 {"fnmadds",     A(59,31,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
5727 {"fnmadds.",    A(59,31,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
5728
5729 {"dmul",        XRC(59,34,0),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5730 {"dmul.",       XRC(59,34,1),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5731
5732 {"drrnd",       ZRC(59,35,0),   Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
5733 {"drrnd.",      ZRC(59,35,1),   Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
5734
5735 {"dscli",       ZRC(59,66,0),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
5736 {"dscli.",      ZRC(59,66,1),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
5737
5738 {"dquai",       ZRC(59,67,0),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRT,FRB,RMC}},
5739 {"dquai.",      ZRC(59,67,1),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRT,FRB,RMC}},
5740
5741 {"dscri",       ZRC(59,98,0),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
5742 {"dscri.",      ZRC(59,98,1),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
5743
5744 {"drintx",      ZRC(59,99,0),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
5745 {"drintx.",     ZRC(59,99,1),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
5746
5747 {"dcmpo",       X(59,130),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
5748
5749 {"dtstex",      X(59,162),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
5750 {"dtstdc",      Z(59,194),      Z_MASK,      POWER6,    PPCNONE,        {BF,  FRA, DCM}},
5751 {"dtstdg",      Z(59,226),      Z_MASK,      POWER6,    PPCNONE,        {BF,  FRA, DGM}},
5752
5753 {"drintn",      ZRC(59,227,0),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
5754 {"drintn.",     ZRC(59,227,1),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
5755
5756 {"dctdp",       XRC(59,258,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5757 {"dctdp.",      XRC(59,258,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5758
5759 {"dctfix",      XRC(59,290,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5760 {"dctfix.",     XRC(59,290,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5761
5762 {"ddedpd",      XRC(59,322,0),  X_MASK,      POWER6,    PPCNONE,        {SP, FRT, FRB}},
5763 {"ddedpd.",     XRC(59,322,1),  X_MASK,      POWER6,    PPCNONE,        {SP, FRT, FRB}},
5764
5765 {"dxex",        XRC(59,354,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5766 {"dxex.",       XRC(59,354,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5767
5768 {"dsub",        XRC(59,514,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5769 {"dsub.",       XRC(59,514,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5770
5771 {"ddiv",        XRC(59,546,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5772 {"ddiv.",       XRC(59,546,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5773
5774 {"dcmpu",       X(59,642),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
5775
5776 {"dtstsf",      X(59,674),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
5777
5778 {"drsp",        XRC(59,770,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5779 {"drsp.",       XRC(59,770,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5780
5781 {"dcffix",      XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCNONE,        {FRT, FRB}},
5782 {"dcffix.",     XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCNONE,        {FRT, FRB}},
5783
5784 {"denbcd",      XRC(59,834,0),  X_MASK,      POWER6,    PPCNONE,        {S, FRT, FRB}},
5785 {"denbcd.",     XRC(59,834,1),  X_MASK,      POWER6,    PPCNONE,        {S, FRT, FRB}},
5786
5787 {"fcfids",      XRC(59,846,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5788 {"fcfids.",     XRC(59,846,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5789
5790 {"diex",        XRC(59,866,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5791 {"diex.",       XRC(59,866,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5792
5793 {"fcfidus",     XRC(59,974,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5794 {"fcfidus.",    XRC(59,974,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5795
5796 {"xxsldwi",     XX3(60,2),      XX3SHW_MASK, PPCVSX,    PPCNONE,        {XT6, XA6, XB6, SHW}},
5797 {"xxsel",       XX4(60,3),      XX4_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6, XC6}},
5798 {"xxspltd",     XX3(60,10),     XX3DM_MASK,  PPCVSX,    PPCNONE,        {XT6, XA6, XB6S, DMEX}},
5799 {"xxmrghd",     XX3(60,10),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5800 {"xxswapd",     XX3(60,10)|(2<<8), XX3_MASK, PPCVSX,    PPCNONE,        {XT6, XA6, XB6S}},
5801 {"xxmrgld",     XX3(60,10)|(3<<8), XX3_MASK, PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5802 {"xxpermdi",    XX3(60,10),     XX3DM_MASK,  PPCVSX,    PPCNONE,        {XT6, XA6, XB6, DM}},
5803 {"xxmrghw",     XX3(60,18),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5804 {"xsadddp",     XX3(60,32),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5805 {"xsmaddadp",   XX3(60,33),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5806 {"xscmpudp",    XX3(60,35),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
5807 {"xssubdp",     XX3(60,40),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5808 {"xsmaddmdp",   XX3(60,41),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5809 {"xscmpodp",    XX3(60,43),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
5810 {"xsmuldp",     XX3(60,48),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5811 {"xsmsubadp",   XX3(60,49),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5812 {"xxmrglw",     XX3(60,50),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5813 {"xsdivdp",     XX3(60,56),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5814 {"xsmsubmdp",   XX3(60,57),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5815 {"xstdivdp",    XX3(60,61),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
5816 {"xvaddsp",     XX3(60,64),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5817 {"xvmaddasp",   XX3(60,65),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5818 {"xvcmpeqsp",   XX3RC(60,67,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5819 {"xvcmpeqsp.",  XX3RC(60,67,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5820 {"xvsubsp",     XX3(60,72),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5821 {"xscvdpuxws",  XX2(60,72),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5822 {"xvmaddmsp",   XX3(60,73),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5823 {"xsrdpi",      XX2(60,73),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5824 {"xsrsqrtedp",  XX2(60,74),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5825 {"xssqrtdp",    XX2(60,75),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5826 {"xvcmpgtsp",   XX3RC(60,75,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5827 {"xvcmpgtsp.",  XX3RC(60,75,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5828 {"xvmulsp",     XX3(60,80),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5829 {"xvmsubasp",   XX3(60,81),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5830 {"xvcmpgesp",   XX3RC(60,83,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5831 {"xvcmpgesp.",  XX3RC(60,83,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5832 {"xvdivsp",     XX3(60,88),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5833 {"xscvdpsxws",  XX2(60,88),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5834 {"xvmsubmsp",   XX3(60,89),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5835 {"xsrdpiz",     XX2(60,89),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5836 {"xsredp",      XX2(60,90),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5837 {"xvtdivsp",    XX3(60,93),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
5838 {"xvadddp",     XX3(60,96),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5839 {"xvmaddadp",   XX3(60,97),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5840 {"xvcmpeqdp",   XX3RC(60,99,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5841 {"xvcmpeqdp.",  XX3RC(60,99,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5842 {"xvsubdp",     XX3(60,104),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5843 {"xvmaddmdp",   XX3(60,105),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5844 {"xsrdpip",     XX2(60,105),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5845 {"xstsqrtdp",   XX2(60,106),    XX2BF_MASK,  PPCVSX,    PPCNONE,        {BF, XB6}},
5846 {"xsrdpic",     XX2(60,107),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5847 {"xvcmpgtdp",   XX3RC(60,107,0), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5848 {"xvcmpgtdp.",  XX3RC(60,107,1), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5849 {"xvmuldp",     XX3(60,112),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5850 {"xvmsubadp",   XX3(60,113),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5851 {"xvcmpgedp",   XX3RC(60,115,0), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5852 {"xvcmpgedp.",  XX3RC(60,115,1), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5853 {"xvdivdp",     XX3(60,120),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5854 {"xvmsubmdp",   XX3(60,121),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5855 {"xsrdpim",     XX2(60,121),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5856 {"xvtdivdp",    XX3(60,125),    XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
5857 {"xxland",      XX3(60,130),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5858 {"xvcvspuxws",  XX2(60,136),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5859 {"xvrspi",      XX2(60,137),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5860 {"xxlandc",     XX3(60,138),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5861 {"xvrsqrtesp",  XX2(60,138),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5862 {"xvsqrtsp",    XX2(60,139),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5863 {"xxlor",       XX3(60,146),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5864 {"xvcvspsxws",  XX2(60,152),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5865 {"xvrspiz",     XX2(60,153),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5866 {"xxlxor",      XX3(60,154),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5867 {"xvresp",      XX2(60,154),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5868 {"xsmaxdp",     XX3(60,160),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5869 {"xsnmaddadp",  XX3(60,161),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5870 {"xxlnor",      XX3(60,162),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5871 {"xxspltw",     XX2(60,164),    XX2UIM_MASK, PPCVSX,    PPCNONE,        {XT6, XB6, UIM}},
5872 {"xsmindp",     XX3(60,168),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5873 {"xvcvuxwsp",   XX2(60,168),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5874 {"xsnmaddmdp",  XX3(60,169),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5875 {"xvrspip",     XX2(60,169),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5876 {"xvtsqrtsp",   XX2(60,170),    XX2BF_MASK,  PPCVSX,    PPCNONE,        {BF, XB6}},
5877 {"xvrspic",     XX2(60,171),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5878 {"xscpsgndp",   XX3(60,176),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5879 {"xsnmsubadp",  XX3(60,177),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5880 {"xvcvsxwsp",   XX2(60,184),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5881 {"xsnmsubmdp",  XX3(60,185),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5882 {"xvrspim",     XX2(60,185),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5883 {"xvmaxsp",     XX3(60,192),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5884 {"xvnmaddasp",  XX3(60,193),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5885 {"xvminsp",     XX3(60,200),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5886 {"xvcvdpuxws",  XX2(60,200),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5887 {"xvnmaddmsp",  XX3(60,201),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5888 {"xvrdpi",      XX2(60,201),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5889 {"xvrsqrtedp",  XX2(60,202),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5890 {"xvsqrtdp",    XX2(60,203),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5891 {"xvmovsp",     XX3(60,208),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6S}},
5892 {"xvcpsgnsp",   XX3(60,208),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5893 {"xvnmsubasp",  XX3(60,209),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5894 {"xvcvdpsxws",  XX2(60,216),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5895 {"xvnmsubmsp",  XX3(60,217),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5896 {"xvrdpiz",     XX2(60,217),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5897 {"xvredp",      XX2(60,218),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5898 {"xvmaxdp",     XX3(60,224),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5899 {"xvnmaddadp",  XX3(60,225),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5900 {"xvmindp",     XX3(60,232),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5901 {"xvnmaddmdp",  XX3(60,233),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5902 {"xvcvuxwdp",   XX2(60,232),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5903 {"xvrdpip",     XX2(60,233),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5904 {"xvtsqrtdp",   XX2(60,234),    XX2BF_MASK,  PPCVSX,    PPCNONE,        {BF, XB6}},
5905 {"xvrdpic",     XX2(60,235),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5906 {"xvmovdp",     XX3(60,240),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6S}},
5907 {"xvcpsgndp",   XX3(60,240),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5908 {"xvnmsubadp",  XX3(60,241),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5909 {"xvcvsxwdp",   XX2(60,248),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5910 {"xvnmsubmdp",  XX3(60,249),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5911 {"xvrdpim",     XX2(60,249),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5912 {"xscvdpsp",    XX2(60,265),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5913 {"xscvdpuxds",  XX2(60,328),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5914 {"xscvspdp",    XX2(60,329),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5915 {"xscvdpsxds",  XX2(60,344),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5916 {"xsabsdp",     XX2(60,345),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5917 {"xscvuxddp",   XX2(60,360),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5918 {"xsnabsdp",    XX2(60,361),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5919 {"xscvsxddp",   XX2(60,376),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5920 {"xsnegdp",     XX2(60,377),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5921 {"xvcvspuxds",  XX2(60,392),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5922 {"xvcvdpsp",    XX2(60,393),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5923 {"xvcvspsxds",  XX2(60,408),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5924 {"xvabssp",     XX2(60,409),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5925 {"xvcvuxdsp",   XX2(60,424),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5926 {"xvnabssp",    XX2(60,425),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5927 {"xvcvsxdsp",   XX2(60,440),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5928 {"xvnegsp",     XX2(60,441),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5929 {"xvcvdpuxds",  XX2(60,456),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5930 {"xvcvspdp",    XX2(60,457),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5931 {"xvcvdpsxds",  XX2(60,472),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5932 {"xvabsdp",     XX2(60,473),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5933 {"xvcvuxddp",   XX2(60,488),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5934 {"xvnabsdp",    XX2(60,489),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5935 {"xvcvsxddp",   XX2(60,504),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5936 {"xvnegdp",     XX2(60,505),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5937
5938 {"psq_st",      OP(60),         OP_MASK,     PPCPS,     PPCNONE,        {FRS,PSD,RA,PSW,PSQ}},
5939 {"stfq",        OP(60),         OP_MASK,     POWER2,    PPCNONE,        {FRS, D, RA}},
5940
5941 {"stfdp",       OP(61),         OP_MASK,     POWER6,    POWER7,         {FRSp, D, RA0}},
5942 {"psq_stu",     OP(61),         OP_MASK,     PPCPS,     PPCNONE,        {FRS,PSD,RA,PSW,PSQ}},
5943 {"stfqu",       OP(61),         OP_MASK,     POWER2,    PPCNONE,        {FRS, D, RA}},
5944
5945 {"std",         DSO(62,0),      DS_MASK,     PPC64,     PPCNONE,        {RS, DS, RA0}},
5946 {"stdu",        DSO(62,1),      DS_MASK,     PPC64,     PPCNONE,        {RS, DS, RAS}},
5947 {"stq",         DSO(62,2),      DS_MASK,     POWER4,    PPC476,         {RSQ, DS, RA0}},
5948
5949 {"fcmpu",       X(63,0),     X_MASK|(3<<21), COM,       PPCEFS,         {BF, FRA, FRB}},
5950
5951 {"daddq",       XRC(63,2,0),    X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
5952 {"daddq.",      XRC(63,2,1),    X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
5953
5954 {"dquaq",       ZRC(63,3,0),    Z2_MASK,     POWER6,    PPCNONE,        {FRTp, FRAp, FRBp, RMC}},
5955 {"dquaq.",      ZRC(63,3,1),    Z2_MASK,     POWER6,    PPCNONE,        {FRTp, FRAp, FRBp, RMC}},
5956
5957 {"fcpsgn",      XRC(63,8,0),    X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, FRA, FRB}},
5958 {"fcpsgn.",     XRC(63,8,1),    X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, FRA, FRB}},
5959
5960 {"frsp",        XRC(63,12,0),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
5961 {"frsp.",       XRC(63,12,1),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
5962
5963 {"fctiw",       XRC(63,14,0),   XRA_MASK,    PPCCOM,    PPCEFS,         {FRT, FRB}},
5964 {"fcir",        XRC(63,14,0),   XRA_MASK,    PWR2COM,   PPCNONE,        {FRT, FRB}},
5965 {"fctiw.",      XRC(63,14,1),   XRA_MASK,    PPCCOM,    PPCEFS,         {FRT, FRB}},
5966 {"fcir.",       XRC(63,14,1),   XRA_MASK,    PWR2COM,   PPCNONE,        {FRT, FRB}},
5967
5968 {"fctiwz",      XRC(63,15,0),   XRA_MASK,    PPCCOM,    PPCEFS,         {FRT, FRB}},
5969 {"fcirz",       XRC(63,15,0),   XRA_MASK,    PWR2COM,   PPCNONE,        {FRT, FRB}},
5970 {"fctiwz.",     XRC(63,15,1),   XRA_MASK,    PPCCOM,    PPCEFS,         {FRT, FRB}},
5971 {"fcirz.",      XRC(63,15,1),   XRA_MASK,    PWR2COM,   PPCNONE,        {FRT, FRB}},
5972
5973 {"fdiv",        A(63,18,0),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
5974 {"fd",          A(63,18,0),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
5975 {"fdiv.",       A(63,18,1),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
5976 {"fd.",         A(63,18,1),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
5977
5978 {"fsub",        A(63,20,0),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
5979 {"fs",          A(63,20,0),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
5980 {"fsub.",       A(63,20,1),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
5981 {"fs.",         A(63,20,1),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
5982
5983 {"fadd",        A(63,21,0),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
5984 {"fa",          A(63,21,0),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
5985 {"fadd.",       A(63,21,1),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
5986 {"fa.",         A(63,21,1),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
5987
5988 {"fsqrt",       A(63,22,0),    AFRAFRC_MASK, PPCPWR2,   TITAN,          {FRT, FRB}},
5989 {"fsqrt.",      A(63,22,1),    AFRAFRC_MASK, PPCPWR2,   TITAN,          {FRT, FRB}},
5990
5991 {"fsel",        A(63,23,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
5992 {"fsel.",       A(63,23,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
5993
5994 {"fre",         A(63,24,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
5995 {"fre",         A(63,24,0),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
5996 {"fre.",        A(63,24,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
5997 {"fre.",        A(63,24,1),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
5998
5999 {"fmul",        A(63,25,0),     AFRB_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRC}},
6000 {"fm",          A(63,25,0),     AFRB_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRC}},
6001 {"fmul.",       A(63,25,1),     AFRB_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRC}},
6002 {"fm.",         A(63,25,1),     AFRB_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRC}},
6003
6004 {"frsqrte",     A(63,26,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
6005 {"frsqrte",     A(63,26,0),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
6006 {"frsqrte.",    A(63,26,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
6007 {"frsqrte.",    A(63,26,1),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
6008
6009 {"fmsub",       A(63,28,0),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6010 {"fms",         A(63,28,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6011 {"fmsub.",      A(63,28,1),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6012 {"fms.",        A(63,28,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6013
6014 {"fmadd",       A(63,29,0),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6015 {"fma",         A(63,29,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6016 {"fmadd.",      A(63,29,1),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6017 {"fma.",        A(63,29,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6018
6019 {"fnmsub",      A(63,30,0),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6020 {"fnms",        A(63,30,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6021 {"fnmsub.",     A(63,30,1),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6022 {"fnms.",       A(63,30,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6023
6024 {"fnmadd",      A(63,31,0),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6025 {"fnma",        A(63,31,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6026 {"fnmadd.",     A(63,31,1),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6027 {"fnma.",       A(63,31,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6028
6029 {"fcmpo",       X(63,32),    X_MASK|(3<<21), COM,       PPCEFS,         {BF, FRA, FRB}},
6030
6031 {"dmulq",       XRC(63,34,0),   X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
6032 {"dmulq.",      XRC(63,34,1),   X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
6033
6034 {"drrndq",      ZRC(63,35,0),   Z2_MASK,     POWER6,    PPCNONE,        {FRTp, FRA, FRBp, RMC}},
6035 {"drrndq.",     ZRC(63,35,1),   Z2_MASK,     POWER6,    PPCNONE,        {FRTp, FRA, FRBp, RMC}},
6036
6037 {"mtfsb1",      XRC(63,38,0),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
6038 {"mtfsb1.",     XRC(63,38,1),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
6039
6040 {"fneg",        XRC(63,40,0),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6041 {"fneg.",       XRC(63,40,1),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6042
6043 {"mcrfs",      X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCNONE,        {BF, BFA}},
6044
6045 {"dscliq",      ZRC(63,66,0),   Z_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, SH16}},
6046 {"dscliq.",     ZRC(63,66,1),   Z_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, SH16}},
6047
6048 {"dquaiq",      ZRC(63,67,0),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRTp, FRBp, RMC}},
6049 {"dquaiq.",     ZRC(63,67,1),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRTp, FRBp, RMC}},
6050
6051 {"mtfsb0",      XRC(63,70,0),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
6052 {"mtfsb0.",     XRC(63,70,1),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
6053
6054 {"fmr",         XRC(63,72,0),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6055 {"fmr.",        XRC(63,72,1),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6056
6057 {"dscriq",      ZRC(63,98,0),   Z_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, SH16}},
6058 {"dscriq.",     ZRC(63,98,1),   Z_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, SH16}},
6059
6060 {"drintxq",     ZRC(63,99,0),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRTp, FRBp, RMC}},
6061 {"drintxq.",    ZRC(63,99,1),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRTp, FRBp, RMC}},
6062
6063 {"ftdiv",       X(63,128),   X_MASK|(3<<21), POWER7,    PPCNONE,        {BF, FRA, FRB}},
6064
6065 {"dcmpoq",      X(63,130),      X_MASK,      POWER6,    PPCNONE,        {BF, FRAp, FRBp}},
6066
6067 {"mtfsfi",  XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
6068 {"mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
6069 {"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
6070 {"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
6071
6072 {"fnabs",       XRC(63,136,0),  XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6073 {"fnabs.",      XRC(63,136,1),  XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6074
6075 {"fctiwu",      XRC(63,142,0),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
6076 {"fctiwu.",     XRC(63,142,1),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
6077 {"fctiwuz",     XRC(63,143,0),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
6078 {"fctiwuz.",    XRC(63,143,1),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
6079
6080 {"ftsqrt",      X(63,160), X_MASK|(3<<21|FRA_MASK), POWER7, PPCNONE,    {BF, FRB}},
6081
6082 {"dtstexq",     X(63,162),      X_MASK,      POWER6,    PPCNONE,        {BF, FRAp, FRBp}},
6083 {"dtstdcq",     Z(63,194),      Z_MASK,      POWER6,    PPCNONE,        {BF, FRAp, DCM}},
6084 {"dtstdgq",     Z(63,226),      Z_MASK,      POWER6,    PPCNONE,        {BF, FRAp, DGM}},
6085
6086 {"drintnq",     ZRC(63,227,0),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRTp, FRBp, RMC}},
6087 {"drintnq.",    ZRC(63,227,1),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRTp, FRBp, RMC}},
6088
6089 {"dctqpq",      XRC(63,258,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRB}},
6090 {"dctqpq.",     XRC(63,258,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRB}},
6091
6092 {"fabs",        XRC(63,264,0),  XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6093 {"fabs.",       XRC(63,264,1),  XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6094
6095 {"dctfixq",     XRC(63,290,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRBp}},
6096 {"dctfixq.",    XRC(63,290,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRBp}},
6097
6098 {"ddedpdq",     XRC(63,322,0),  X_MASK,      POWER6,    PPCNONE,        {SP, FRTp, FRBp}},
6099 {"ddedpdq.",    XRC(63,322,1),  X_MASK,      POWER6,    PPCNONE,        {SP, FRTp, FRBp}},
6100
6101 {"dxexq",       XRC(63,354,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRBp}},
6102 {"dxexq.",      XRC(63,354,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRBp}},
6103
6104 {"frin",        XRC(63,392,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6105 {"frin.",       XRC(63,392,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6106 {"friz",        XRC(63,424,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6107 {"friz.",       XRC(63,424,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6108 {"frip",        XRC(63,456,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6109 {"frip.",       XRC(63,456,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6110 {"frim",        XRC(63,488,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6111 {"frim.",       XRC(63,488,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6112
6113 {"dsubq",       XRC(63,514,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
6114 {"dsubq.",      XRC(63,514,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
6115
6116 {"ddivq",       XRC(63,546,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
6117 {"ddivq.",      XRC(63,546,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
6118
6119 {"mffs",        XRC(63,583,0),  XRARB_MASK,  COM,       PPCEFS,         {FRT}},
6120 {"mffs.",       XRC(63,583,1),  XRARB_MASK,  COM,       PPCEFS,         {FRT}},
6121
6122 {"dcmpuq",      X(63,642),      X_MASK,      POWER6,    PPCNONE,        {BF, FRAp, FRBp}},
6123
6124 {"dtstsfq",     X(63,674),      X_MASK,      POWER6,    PPCNONE,        {BF, FRA, FRBp}},
6125
6126 {"mtfsf",       XFL(63,711,0),  XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
6127 {"mtfsf",       XFL(63,711,0),  XFL_MASK,    COM, POWER6|PPCA2|PPC476|PPCEFS,   {FLM, FRB}},
6128 {"mtfsf.",      XFL(63,711,1),  XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
6129 {"mtfsf.",      XFL(63,711,1),  XFL_MASK,    COM, POWER6|PPCA2|PPC476|PPCEFS,   {FLM, FRB}},
6130
6131 {"drdpq",       XRC(63,770,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRBp}},
6132 {"drdpq.",      XRC(63,770,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRBp}},
6133
6134 {"dcffixq",     XRC(63,802,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRB}},
6135 {"dcffixq.",    XRC(63,802,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRB}},
6136
6137 {"fctid",       XRC(63,814,0),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
6138 {"fctid",       XRC(63,814,0),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
6139 {"fctid.",      XRC(63,814,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
6140 {"fctid.",      XRC(63,814,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
6141
6142 {"fctidz",      XRC(63,815,0),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
6143 {"fctidz",      XRC(63,815,0),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
6144 {"fctidz.",     XRC(63,815,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
6145 {"fctidz.",     XRC(63,815,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
6146
6147 {"denbcdq",     XRC(63,834,0),  X_MASK,      POWER6,    PPCNONE,        {S, FRTp, FRBp}},
6148 {"denbcdq.",    XRC(63,834,1),  X_MASK,      POWER6,    PPCNONE,        {S, FRTp, FRBp}},
6149
6150 {"fcfid",       XRC(63,846,0),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
6151 {"fcfid",       XRC(63,846,0),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
6152 {"fcfid.",      XRC(63,846,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
6153 {"fcfid.",      XRC(63,846,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
6154
6155 {"diexq",       XRC(63,866,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRA, FRBp}},
6156 {"diexq.",      XRC(63,866,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRA, FRBp}},
6157
6158 {"fctidu",      XRC(63,942,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6159 {"fctidu.",     XRC(63,942,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6160
6161 {"fctiduz",     XRC(63,943,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6162 {"fctiduz.",    XRC(63,943,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6163
6164 {"fcfidu",      XRC(63,974,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6165 {"fcfidu.",     XRC(63,974,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6166 };
6167
6168 const int powerpc_num_opcodes =
6169   sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
6170 \f
6171 /* The VLE opcode table.
6172
6173    The format of this opcode table is the same as the main opcode table.  */
6174
6175 const struct powerpc_opcode vle_opcodes[] = {
6176
6177 {"se_illegal",  C(0),           C_MASK,         PPCVLE, PPCNONE,        {}},
6178 {"se_isync",    C(1),           C_MASK,         PPCVLE, PPCNONE,        {}},
6179 {"se_sc",       C(2),           C_MASK,         PPCVLE, PPCNONE,        {}},
6180 {"se_blr",      C_LK(2,0),      C_LK_MASK,      PPCVLE, PPCNONE,        {}},
6181 {"se_blrl",     C_LK(2,1),      C_LK_MASK,      PPCVLE, PPCNONE,        {}},
6182 {"se_bctr",     C_LK(3,0),      C_LK_MASK,      PPCVLE, PPCNONE,        {}},
6183 {"se_bctrl",    C_LK(3,1),      C_LK_MASK,      PPCVLE, PPCNONE,        {}},
6184 {"se_rfi",      C(8),           C_MASK,         PPCVLE, PPCNONE,        {}},
6185 {"se_rfci",     C(9),           C_MASK,         PPCVLE, PPCNONE,        {}},
6186 {"se_rfdi",     C(10),          C_MASK,         PPCVLE, PPCNONE,        {}},
6187 {"se_rfmci",    C(11),          C_MASK,         PPCVLE, PPCNONE,        {}},
6188 {"se_not",      SE_R(0,2),      SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
6189 {"se_neg",      SE_R(0,3),      SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
6190 {"se_mflr",     SE_R(0,8),      SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
6191 {"se_mtlr",     SE_R(0,9),      SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
6192 {"se_mfctr",    SE_R(0,10),     SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
6193 {"se_mtctr",    SE_R(0,11),     SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
6194 {"se_extzb",    SE_R(0,12),     SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
6195 {"se_extsb",    SE_R(0,13),     SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
6196 {"se_extzh",    SE_R(0,14),     SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
6197 {"se_extsh",    SE_R(0,15),     SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
6198 {"se_mr",       SE_RR(0,1),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6199 {"se_mtar",     SE_RR(0,2),     SE_RR_MASK,     PPCVLE, PPCNONE,        {ARX, RY}},
6200 {"se_mfar",     SE_RR(0,3),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, ARY}},
6201 {"se_add",      SE_RR(1,0),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6202 {"se_mullw",    SE_RR(1,1),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6203 {"se_sub",      SE_RR(1,2),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6204 {"se_subf",     SE_RR(1,3),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6205 {"se_cmp",      SE_RR(3,0),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6206 {"se_cmpl",     SE_RR(3,1),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6207 {"se_cmph",     SE_RR(3,2),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6208 {"se_cmphl",    SE_RR(3,3),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6209
6210 {"e_cmpi",      SCI8BF(6,0,21), SCI8BF_MASK,    PPCVLE, PPCNONE,        {CRD32, RA, SCLSCI8}},
6211 {"e_cmpli",     SCI8BF(6,1,21), SCI8BF_MASK,    PPCVLE, PPCNONE,        {CRD32, RA, SCLSCI8}},
6212 {"e_addi",      SCI8(6,16),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
6213 {"e_subi",      SCI8(6,16),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8N}},
6214 {"e_addi.",     SCI8(6,17),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
6215 {"e_addic",     SCI8(6,18),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
6216 {"e_subic",     SCI8(6,18),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8N}},
6217 {"e_addic.",    SCI8(6,19),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
6218 {"e_subic.",    SCI8(6,19),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8N}},
6219 {"e_mulli",     SCI8(6,20),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
6220 {"e_subfic",    SCI8(6,22),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
6221 {"e_subfic.",   SCI8(6,23),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
6222 {"e_andi",      SCI8(6,24),     SCI8_MASK,      PPCVLE, PPCNONE,        {RA, RS, SCLSCI8}},
6223 {"e_andi.",     SCI8(6,25),     SCI8_MASK,      PPCVLE, PPCNONE,        {RA, RS, SCLSCI8}},
6224 {"e_nop",       SCI8(6,26),     0xffffffff,     PPCVLE, PPCNONE,        {0}},
6225 {"e_ori",       SCI8(6,26),     SCI8_MASK,      PPCVLE, PPCNONE,        {RA, RS, SCLSCI8}},
6226 {"e_ori.",      SCI8(6,27),     SCI8_MASK,      PPCVLE, PPCNONE,        {RA, RS, SCLSCI8}},
6227 {"e_xori",      SCI8(6,28),     SCI8_MASK,      PPCVLE, PPCNONE,        {RA, RS, SCLSCI8}},
6228 {"e_xori.",     SCI8(6,29),     SCI8_MASK,      PPCVLE, PPCNONE,        {RA, RS, SCLSCI8}},
6229 {"e_lbzu",      OPVUP(6,0),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
6230 {"e_lhau",      OPVUP(6,3),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
6231 {"e_lhzu",      OPVUP(6,1),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
6232 {"e_lmw",       OPVUP(6,8),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
6233 {"e_lwzu",      OPVUP(6,2),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
6234 {"e_stbu",      OPVUP(6,4),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
6235 {"e_sthu",      OPVUP(6,5),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
6236 {"e_stwu",      OPVUP(6,6),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
6237 {"e_stmw",      OPVUP(6,9),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
6238 {"e_add16i",    OP(7),          OP_MASK,        PPCVLE, PPCNONE,        {RT, RA, SI}},
6239 {"e_la",        OP(7),          OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
6240 {"e_sub16i",    OP(7),          OP_MASK,        PPCVLE, PPCNONE,        {RT, RA, NSI}},
6241
6242 {"se_addi",     SE_IM5(8,0),    SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, OIMM5}},
6243 {"se_cmpli",    SE_IM5(8,1),    SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, OIMM5}},
6244 {"se_subi",     SE_IM5(9,0),    SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, OIMM5}},
6245 {"se_subi.",    SE_IM5(9,1),    SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, OIMM5}},
6246 {"se_cmpi",     SE_IM5(10,1),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
6247 {"se_bmaski",   SE_IM5(11,0),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
6248 {"se_andi",     SE_IM5(11,1),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
6249
6250 {"e_lbz",       OP(12),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
6251 {"e_stb",       OP(13),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
6252 {"e_lha",       OP(14),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
6253
6254 {"se_srw",      SE_RR(16,0),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6255 {"se_sraw",     SE_RR(16,1),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6256 {"se_slw",      SE_RR(16,2),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6257 {"se_nop",      SE_RR(17,0),    0xffff,         PPCVLE, PPCNONE,        {0}},
6258 {"se_or",       SE_RR(17,0),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6259 {"se_andc",     SE_RR(17,1),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6260 {"se_and",      SE_RR(17,2),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6261 {"se_and.",     SE_RR(17,3),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6262 {"se_li",       IM7(9),         IM7_MASK,       PPCVLE, PPCNONE,        {RX, UI7}},
6263
6264 {"e_lwz",       OP(20),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
6265 {"e_stw",       OP(21),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
6266 {"e_lhz",       OP(22),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
6267 {"e_sth",       OP(23),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
6268
6269 {"se_bclri",    SE_IM5(24,0),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
6270 {"se_bgeni",    SE_IM5(24,1),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
6271 {"se_bseti",    SE_IM5(25,0),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
6272 {"se_btsti",    SE_IM5(25,1),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
6273 {"se_srwi",     SE_IM5(26,0),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
6274 {"se_srawi",    SE_IM5(26,1),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
6275 {"se_slwi",     SE_IM5(27,0),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
6276
6277 {"e_lis",       I16L(28,28),    I16L_MASK,      PPCVLE, PPCNONE,        {RD, VLEUIMML}},
6278 {"e_and2is.",   I16L(28,29),    I16L_MASK,      PPCVLE, PPCNONE,        {RD, VLEUIMML}},
6279 {"e_or2is",     I16L(28,26),    I16L_MASK,      PPCVLE, PPCNONE,        {RD, VLEUIMML}},
6280 {"e_and2i.",    I16L(28,25),    I16L_MASK,      PPCVLE, PPCNONE,        {RD, VLEUIMML}},
6281 {"e_or2i",      I16L(28,24),    I16L_MASK,      PPCVLE, PPCNONE,        {RD, VLEUIMML}},
6282 {"e_cmphl16i",  IA16(28,23),    IA16_MASK,      PPCVLE, PPCNONE,        {RA, VLEUIMM}},
6283 {"e_cmph16i",   IA16(28,22),    IA16_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
6284 {"e_cmpl16i",   I16A(28,21),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLEUIMM}},
6285 {"e_cmplwi",    I16A(28,21),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
6286 {"e_mull2i",    I16A(28,20),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
6287 {"e_cmp16i",    IA16(28,19),    IA16_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
6288 {"e_cmpwi",     IA16(28,19),    IA16_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
6289 {"e_sub2is",    I16A(28,18),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLENSIMM}},
6290 {"e_add2is",    I16A(28,18),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
6291 {"e_sub2i.",    I16A(28,17),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLENSIMM}},
6292 {"e_add2i.",    I16A(28,17),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
6293 {"e_li",        LI20(28,0),     LI20_MASK,      PPCVLE, PPCNONE,        {RT, IMM20}},
6294 {"e_rlwimi",    M(29,0),        M_MASK,         PPCVLE, PPCNONE,        {RA, RS, SH, MB, ME}},
6295 {"e_rlwinm",    M(29,1),        M_MASK,         PPCVLE, PPCNONE,        {RA, RT, SH, MBE, ME}},
6296 {"e_b",         BD24(30,0,0),   BD24_MASK,      PPCVLE, PPCNONE,        {B24}},
6297 {"e_bl",        BD24(30,0,1),   BD24_MASK,      PPCVLE, PPCNONE,        {B24}},
6298 {"e_bdnz",      EBD15(30,8,BO32DNZ,0),  EBD15_MASK, PPCVLE, PPCNONE,    {B15}},
6299 {"e_bdnzl",     EBD15(30,8,BO32DNZ,1),  EBD15_MASK, PPCVLE, PPCNONE,    {B15}},
6300 {"e_bdz",       EBD15(30,8,BO32DZ,0),   EBD15_MASK, PPCVLE, PPCNONE,    {B15}},
6301 {"e_bdzl",      EBD15(30,8,BO32DZ,1),   EBD15_MASK, PPCVLE, PPCNONE,    {B15}},
6302 {"e_bge",       EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6303 {"e_bgel",      EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6304 {"e_bnl",       EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6305 {"e_bnll",      EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6306 {"e_blt",       EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6307 {"e_bltl",      EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6308 {"e_bgt",       EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6309 {"e_bgtl",      EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6310 {"e_ble",       EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6311 {"e_blel",      EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6312 {"e_bng",       EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6313 {"e_bngl",      EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6314 {"e_bne",       EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6315 {"e_bnel",      EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6316 {"e_beq",       EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6317 {"e_beql",      EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6318 {"e_bso",       EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6319 {"e_bsol",      EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6320 {"e_bun",       EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6321 {"e_bunl",      EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6322 {"e_bns",       EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6323 {"e_bnsl",      EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6324 {"e_bnu",       EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6325 {"e_bnul",      EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6326 {"e_bc",        BD15(30,8,0),   BD15_MASK,      PPCVLE, PPCNONE,        {BO32, BI32, B15}},
6327 {"e_bcl",       BD15(30,8,1),   BD15_MASK,      PPCVLE, PPCNONE,        {BO32, BI32, B15}},
6328
6329 {"e_bf",        EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, PPCNONE,       {BI32,B15}},
6330 {"e_bfl",       EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, PPCNONE,       {BI32,B15}},
6331 {"e_bt",        EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, PPCNONE,       {BI32,B15}},
6332 {"e_btl",       EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, PPCNONE,       {BI32,B15}},
6333
6334 {"e_cmph",      X(31,14),       X_MASK,         PPCVLE, PPCNONE,        {CRD, RA, RB}},
6335 {"e_cmphl",     X(31,46),       X_MASK,         PPCVLE, PPCNONE,        {CRD, RA, RB}},
6336 {"e_crandc",    XL(31,129),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
6337 {"e_crnand",    XL(31,225),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
6338 {"e_crnot",     XL(31,33),      XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BBA}},
6339 {"e_crnor",     XL(31,33),      XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
6340 {"e_crclr",     XL(31,193),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BAT, BBA}},
6341 {"e_crxor",     XL(31,193),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
6342 {"e_mcrf",      XL(31,16),      XL_MASK,        PPCVLE, PPCNONE,        {CRD, CR}},
6343 {"e_slwi",      EX(31,112),     EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, SH}},
6344 {"e_slwi.",     EX(31,113),     EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, SH}},
6345
6346 {"e_crand",     XL(31,257),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
6347
6348 {"e_rlw",       EX(31,560),     EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, RB}},
6349 {"e_rlw.",      EX(31,561),     EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, RB}},
6350
6351 {"e_crset",     XL(31,289),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BAT, BBA}},
6352 {"e_creqv",     XL(31,289),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
6353
6354 {"e_rlwi",      EX(31,624),     EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, SH}},
6355 {"e_rlwi.",     EX(31,625),     EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, SH}},
6356
6357 {"e_crorc",     XL(31,417),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
6358
6359 {"e_crmove",    XL(31,449),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BBA}},
6360 {"e_cror",      XL(31,449),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
6361
6362 {"mtmas1",      XSPR(31,467,625), XSPR_MASK,    PPCVLE, PPCNONE,        {RS}},
6363
6364 {"e_srwi",      EX(31,1136),    EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, SH}},
6365 {"e_srwi.",     EX(31,1137),    EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, SH}},
6366
6367 {"se_lbz",      SD4(8),         SD4_MASK,       PPCVLE, PPCNONE,        {RZ, SE_SD, RX}},
6368
6369 {"se_stb",      SD4(9),         SD4_MASK,       PPCVLE, PPCNONE,        {RZ, SE_SD, RX}},
6370
6371 {"se_lhz",      SD4(10),        SD4_MASK,       PPCVLE, PPCNONE,        {RZ, SE_SDH, RX}},
6372
6373 {"se_sth",      SD4(11),        SD4_MASK,       PPCVLE, PPCNONE,        {RZ, SE_SDH, RX}},
6374
6375 {"se_lwz",      SD4(12),        SD4_MASK,       PPCVLE, PPCNONE,        {RZ, SE_SDW, RX}},
6376
6377 {"se_stw",      SD4(13),        SD4_MASK,       PPCVLE, PPCNONE,        {RZ, SE_SDW, RX}},
6378
6379 {"se_bge",      EBD8IO(28,0,0), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6380 {"se_bnl",      EBD8IO(28,0,0), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6381 {"se_ble",      EBD8IO(28,0,1), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6382 {"se_bng",      EBD8IO(28,0,1), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6383 {"se_bne",      EBD8IO(28,0,2), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6384 {"se_bns",      EBD8IO(28,0,3), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6385 {"se_bnu",      EBD8IO(28,0,3), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6386 {"se_bf",       EBD8IO(28,0,0), EBD8IO2_MASK,   PPCVLE, PPCNONE,        {BI16, B8}},
6387 {"se_blt",      EBD8IO(28,1,0), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6388 {"se_bgt",      EBD8IO(28,1,1), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6389 {"se_beq",      EBD8IO(28,1,2), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6390 {"se_bso",      EBD8IO(28,1,3), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6391 {"se_bun",      EBD8IO(28,1,3), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6392 {"se_bt",       EBD8IO(28,1,0), EBD8IO2_MASK,   PPCVLE, PPCNONE,        {BI16, B8}},
6393 {"se_bc",       BD8IO(28),      BD8IO_MASK,     PPCVLE, PPCNONE,        {BO16, BI16, B8}},
6394 {"se_b",        BD8(58,0,0),    BD8_MASK,       PPCVLE, PPCNONE,        {B8}},
6395 {"se_bl",       BD8(58,0,1),    BD8_MASK,       PPCVLE, PPCNONE,        {B8}},
6396 };
6397
6398 const int vle_num_opcodes =
6399   sizeof (vle_opcodes) / sizeof (vle_opcodes[0]);
6400 \f
6401 /* The macro table.  This is only used by the assembler.  */
6402
6403 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
6404    when x=0; 32-x when x is between 1 and 31; are negative if x is
6405    negative; and are 32 or more otherwise.  This is what you want
6406    when, for instance, you are emulating a right shift by a
6407    rotate-left-and-mask, because the underlying instructions support
6408    shifts of size 0 but not shifts of size 32.  By comparison, when
6409    extracting x bits from some word you want to use just 32-x, because
6410    the underlying instructions don't support extracting 0 bits but do
6411    support extracting the whole word (32 bits in this case).  */
6412
6413 const struct powerpc_macro powerpc_macros[] = {
6414 {"extldi",   4, PPC64,  "rldicr %0,%1,%3,(%2)-1"},
6415 {"extldi.",  4, PPC64,  "rldicr. %0,%1,%3,(%2)-1"},
6416 {"extrdi",   4, PPC64,  "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
6417 {"extrdi.",  4, PPC64,  "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
6418 {"insrdi",   4, PPC64,  "rldimi %0,%1,64-((%2)+(%3)),%3"},
6419 {"insrdi.",  4, PPC64,  "rldimi. %0,%1,64-((%2)+(%3)),%3"},
6420 {"rotrdi",   3, PPC64,  "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
6421 {"rotrdi.",  3, PPC64,  "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
6422 {"sldi",     3, PPC64,  "rldicr %0,%1,%2,63-(%2)"},
6423 {"sldi.",    3, PPC64,  "rldicr. %0,%1,%2,63-(%2)"},
6424 {"srdi",     3, PPC64,  "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
6425 {"srdi.",    3, PPC64,  "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
6426 {"clrrdi",   3, PPC64,  "rldicr %0,%1,0,63-(%2)"},
6427 {"clrrdi.",  3, PPC64,  "rldicr. %0,%1,0,63-(%2)"},
6428 {"clrlsldi", 4, PPC64,  "rldic %0,%1,%3,(%2)-(%3)"},
6429 {"clrlsldi.",4, PPC64,  "rldic. %0,%1,%3,(%2)-(%3)"},
6430
6431 {"extlwi",   4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
6432 {"extlwi.",  4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
6433 {"extrwi",   4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
6434 {"extrwi.",  4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
6435 {"inslwi",   4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
6436 {"inslwi.",  4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
6437 {"insrwi",   4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
6438 {"insrwi.",  4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
6439 {"rotrwi",   3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
6440 {"rotrwi.",  3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
6441 {"slwi",     3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"},
6442 {"sli",      3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
6443 {"slwi.",    3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"},
6444 {"sli.",     3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"},
6445 {"srwi",     3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6446 {"sri",      3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6447 {"srwi.",    3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6448 {"sri.",     3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6449 {"clrrwi",   3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"},
6450 {"clrrwi.",  3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
6451 {"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
6452 {"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
6453
6454 {"e_extlwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"},
6455 {"e_extrwi", 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
6456 {"e_inslwi", 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
6457 {"e_insrwi", 4, PPCVLE, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
6458 {"e_rotlwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31"},
6459 {"e_rotrwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
6460 {"e_slwi",   3, PPCVLE, "e_rlwinm %0,%1,%2,0,31-(%2)"},
6461 {"e_srwi",   3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6462 {"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"},
6463 {"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"},
6464 {"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
6465 };
6466
6467 const int powerpc_num_macros =
6468   sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);