2 Copyright (C) 2011-2021 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of the GNU opcodes library.
9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
24 #include "disassemble.h"
25 #include "libiberty.h"
26 #include "opcode/riscv.h"
29 #include "elf/riscv.h"
30 #include "cpu-riscv.h"
32 #include "bfd_stdint.h"
35 static enum riscv_spec_class default_priv_spec
= PRIV_SPEC_CLASS_NONE
;
37 struct riscv_private_data
41 bfd_vma hi_addr
[OP_MASK_RD
+ 1];
44 static const char * const *riscv_gpr_names
;
45 static const char * const *riscv_fpr_names
;
47 /* If set, disassemble as most general instruction. */
48 static int no_aliases
;
51 set_default_riscv_dis_options (void)
53 riscv_gpr_names
= riscv_gpr_names_abi
;
54 riscv_fpr_names
= riscv_fpr_names_abi
;
59 parse_riscv_dis_option_without_args (const char *option
)
61 if (strcmp (option
, "no-aliases") == 0)
63 else if (strcmp (option
, "numeric") == 0)
65 riscv_gpr_names
= riscv_gpr_names_numeric
;
66 riscv_fpr_names
= riscv_fpr_names_numeric
;
74 parse_riscv_dis_option (const char *option
)
78 if (parse_riscv_dis_option_without_args (option
))
81 equal
= strchr (option
, '=');
84 /* The option without '=' should be defined above. */
85 opcodes_error_handler (_("unrecognized disassembler option: %s"), option
);
89 || *(equal
+ 1) == '\0')
91 /* Invalid options with '=', no option name before '=',
92 and no value after '='. */
93 opcodes_error_handler (_("unrecognized disassembler option with '=': %s"),
100 if (strcmp (option
, "priv-spec") == 0)
102 enum riscv_spec_class priv_spec
= PRIV_SPEC_CLASS_NONE
;
103 const char *name
= NULL
;
105 RISCV_GET_PRIV_SPEC_CLASS (value
, priv_spec
);
106 if (priv_spec
== PRIV_SPEC_CLASS_NONE
)
107 opcodes_error_handler (_("unknown privileged spec set by %s=%s"),
109 else if (default_priv_spec
== PRIV_SPEC_CLASS_NONE
)
110 default_priv_spec
= priv_spec
;
111 else if (default_priv_spec
!= priv_spec
)
113 RISCV_GET_PRIV_SPEC_NAME (name
, default_priv_spec
);
114 opcodes_error_handler (_("mis-matched privilege spec set by %s=%s, "
115 "the elf privilege attribute is %s"),
116 option
, value
, name
);
121 /* xgettext:c-format */
122 opcodes_error_handler (_("unrecognized disassembler option: %s"), option
);
127 parse_riscv_dis_options (const char *opts_in
)
129 char *opts
= xstrdup (opts_in
), *opt
= opts
, *opt_end
= opts
;
131 set_default_riscv_dis_options ();
133 for ( ; opt_end
!= NULL
; opt
= opt_end
+ 1)
135 if ((opt_end
= strchr (opt
, ',')) != NULL
)
137 parse_riscv_dis_option (opt
);
143 /* Print one argument from an array. */
146 arg_print (struct disassemble_info
*info
, unsigned long val
,
147 const char* const* array
, size_t size
)
149 const char *s
= val
>= size
|| array
[val
] == NULL
? "unknown" : array
[val
];
150 (*info
->fprintf_func
) (info
->stream
, "%s", s
);
154 maybe_print_address (struct riscv_private_data
*pd
, int base_reg
, int offset
)
156 if (pd
->hi_addr
[base_reg
] != (bfd_vma
)-1)
158 pd
->print_addr
= (base_reg
!= 0 ? pd
->hi_addr
[base_reg
] : 0) + offset
;
159 pd
->hi_addr
[base_reg
] = -1;
161 else if (base_reg
== X_GP
&& pd
->gp
!= (bfd_vma
)-1)
162 pd
->print_addr
= pd
->gp
+ offset
;
163 else if (base_reg
== X_TP
|| base_reg
== 0)
164 pd
->print_addr
= offset
;
167 /* Print insn arguments for 32/64-bit code. */
170 print_insn_args (const char *d
, insn_t l
, bfd_vma pc
, disassemble_info
*info
)
172 struct riscv_private_data
*pd
= info
->private_data
;
173 int rs1
= (l
>> OP_SH_RS1
) & OP_MASK_RS1
;
174 int rd
= (l
>> OP_SH_RD
) & OP_MASK_RD
;
175 fprintf_ftype print
= info
->fprintf_func
;
178 print (info
->stream
, "\t");
180 for (; *d
!= '\0'; d
++)
187 case 's': /* RS1 x8-x15. */
188 case 'w': /* RS1 x8-x15. */
189 print (info
->stream
, "%s",
190 riscv_gpr_names
[EXTRACT_OPERAND (CRS1S
, l
) + 8]);
192 case 't': /* RS2 x8-x15. */
193 case 'x': /* RS2 x8-x15. */
194 print (info
->stream
, "%s",
195 riscv_gpr_names
[EXTRACT_OPERAND (CRS2S
, l
) + 8]);
197 case 'U': /* RS1, constrained to equal RD. */
198 print (info
->stream
, "%s", riscv_gpr_names
[rd
]);
200 case 'c': /* RS1, constrained to equal sp. */
201 print (info
->stream
, "%s", riscv_gpr_names
[X_SP
]);
204 print (info
->stream
, "%s",
205 riscv_gpr_names
[EXTRACT_OPERAND (CRS2
, l
)]);
208 print (info
->stream
, "%d", (int)EXTRACT_RVC_SIMM3 (l
));
212 print (info
->stream
, "%d", (int)EXTRACT_RVC_IMM (l
));
215 print (info
->stream
, "%d", (int)EXTRACT_RVC_LW_IMM (l
));
218 print (info
->stream
, "%d", (int)EXTRACT_RVC_LD_IMM (l
));
221 print (info
->stream
, "%d", (int)EXTRACT_RVC_LWSP_IMM (l
));
224 print (info
->stream
, "%d", (int)EXTRACT_RVC_LDSP_IMM (l
));
227 print (info
->stream
, "%d", (int)EXTRACT_RVC_ADDI4SPN_IMM (l
));
230 print (info
->stream
, "%d", (int)EXTRACT_RVC_ADDI16SP_IMM (l
));
233 print (info
->stream
, "%d", (int)EXTRACT_RVC_SWSP_IMM (l
));
236 print (info
->stream
, "%d", (int)EXTRACT_RVC_SDSP_IMM (l
));
239 info
->target
= EXTRACT_RVC_B_IMM (l
) + pc
;
240 (*info
->print_address_func
) (info
->target
, info
);
243 info
->target
= EXTRACT_RVC_J_IMM (l
) + pc
;
244 (*info
->print_address_func
) (info
->target
, info
);
247 print (info
->stream
, "0x%x",
248 (int)(EXTRACT_RVC_IMM (l
) & (RISCV_BIGIMM_REACH
-1)));
251 print (info
->stream
, "0x%x", (int)EXTRACT_RVC_IMM (l
) & 0x3f);
254 print (info
->stream
, "0x%x", (int)EXTRACT_RVC_IMM (l
) & 0x1f);
256 case 'T': /* Floating-point RS2. */
257 print (info
->stream
, "%s",
258 riscv_fpr_names
[EXTRACT_OPERAND (CRS2
, l
)]);
260 case 'D': /* Floating-point RS2 x8-x15. */
261 print (info
->stream
, "%s",
262 riscv_fpr_names
[EXTRACT_OPERAND (CRS2S
, l
) + 8]);
272 print (info
->stream
, "%c", *d
);
276 /* Only print constant 0 if it is the last argument. */
278 print (info
->stream
, "0");
283 if ((l
& MASK_JALR
) == MATCH_JALR
)
284 maybe_print_address (pd
, rs1
, 0);
285 print (info
->stream
, "%s", riscv_gpr_names
[rs1
]);
289 print (info
->stream
, "%s",
290 riscv_gpr_names
[EXTRACT_OPERAND (RS2
, l
)]);
294 print (info
->stream
, "0x%x",
295 (unsigned)EXTRACT_UTYPE_IMM (l
) >> RISCV_IMM_BITS
);
299 arg_print (info
, EXTRACT_OPERAND (RM
, l
),
300 riscv_rm
, ARRAY_SIZE (riscv_rm
));
304 arg_print (info
, EXTRACT_OPERAND (PRED
, l
),
305 riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
));
309 arg_print (info
, EXTRACT_OPERAND (SUCC
, l
),
310 riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
));
314 maybe_print_address (pd
, rs1
, EXTRACT_ITYPE_IMM (l
));
317 if (((l
& MASK_ADDI
) == MATCH_ADDI
&& rs1
!= 0)
318 || (l
& MASK_JALR
) == MATCH_JALR
)
319 maybe_print_address (pd
, rs1
, EXTRACT_ITYPE_IMM (l
));
320 print (info
->stream
, "%d", (int)EXTRACT_ITYPE_IMM (l
));
324 maybe_print_address (pd
, rs1
, EXTRACT_STYPE_IMM (l
));
325 print (info
->stream
, "%d", (int)EXTRACT_STYPE_IMM (l
));
329 info
->target
= EXTRACT_UJTYPE_IMM (l
) + pc
;
330 (*info
->print_address_func
) (info
->target
, info
);
334 info
->target
= EXTRACT_SBTYPE_IMM (l
) + pc
;
335 (*info
->print_address_func
) (info
->target
, info
);
339 if ((l
& MASK_AUIPC
) == MATCH_AUIPC
)
340 pd
->hi_addr
[rd
] = pc
+ EXTRACT_UTYPE_IMM (l
);
341 else if ((l
& MASK_LUI
) == MATCH_LUI
)
342 pd
->hi_addr
[rd
] = EXTRACT_UTYPE_IMM (l
);
343 else if ((l
& MASK_C_LUI
) == MATCH_C_LUI
)
344 pd
->hi_addr
[rd
] = EXTRACT_RVC_LUI_IMM (l
);
345 print (info
->stream
, "%s", riscv_gpr_names
[rd
]);
349 print (info
->stream
, "%s", riscv_gpr_names
[0]);
353 print (info
->stream
, "0x%x", (int)EXTRACT_OPERAND (SHAMT
, l
));
357 print (info
->stream
, "0x%x", (int)EXTRACT_OPERAND (SHAMTW
, l
));
362 print (info
->stream
, "%s", riscv_fpr_names
[rs1
]);
366 print (info
->stream
, "%s", riscv_fpr_names
[EXTRACT_OPERAND (RS2
, l
)]);
370 print (info
->stream
, "%s", riscv_fpr_names
[rd
]);
374 print (info
->stream
, "%s", riscv_fpr_names
[EXTRACT_OPERAND (RS3
, l
)]);
379 static const char *riscv_csr_hash
[4096]; /* Total 2^12 CSRs. */
380 static bfd_boolean init_csr
= FALSE
;
381 unsigned int csr
= EXTRACT_OPERAND (CSR
, l
);
386 for (i
= 0; i
< 4096; i
++)
387 riscv_csr_hash
[i
] = NULL
;
389 /* Set to the newest privileged version. */
390 if (default_priv_spec
== PRIV_SPEC_CLASS_NONE
)
391 default_priv_spec
= PRIV_SPEC_CLASS_DRAFT
- 1;
393 #define DECLARE_CSR(name, num, class, define_version, abort_version) \
394 if (riscv_csr_hash[num] == NULL \
395 && ((define_version == PRIV_SPEC_CLASS_NONE \
396 && abort_version == PRIV_SPEC_CLASS_NONE) \
397 || (default_priv_spec >= define_version \
398 && default_priv_spec < abort_version))) \
399 riscv_csr_hash[num] = #name;
400 #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
401 DECLARE_CSR (name, num, class, define_version, abort_version)
402 #include "opcode/riscv-opc.h"
406 if (riscv_csr_hash
[csr
] != NULL
)
407 print (info
->stream
, "%s", riscv_csr_hash
[csr
]);
409 print (info
->stream
, "0x%x", csr
);
414 print (info
->stream
, "%d", rs1
);
418 /* xgettext:c-format */
419 print (info
->stream
, _("# internal error, undefined modifier (%c)"),
426 /* Print the RISC-V instruction at address MEMADDR in debugged memory,
427 on using INFO. Returns length of the instruction, in bytes.
428 BIGENDIAN must be 1 if this is big-endian code, 0 if
429 this is little-endian code. */
432 riscv_disassemble_insn (bfd_vma memaddr
, insn_t word
, disassemble_info
*info
)
434 const struct riscv_opcode
*op
;
435 static bfd_boolean init
= 0;
436 static const struct riscv_opcode
*riscv_hash
[OP_MASK_OP
+ 1];
437 struct riscv_private_data
*pd
;
440 #define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : OP_MASK_OP))
442 /* Build a hash table to shorten the search time. */
445 for (op
= riscv_opcodes
; op
->name
; op
++)
446 if (!riscv_hash
[OP_HASH_IDX (op
->match
)])
447 riscv_hash
[OP_HASH_IDX (op
->match
)] = op
;
452 if (info
->private_data
== NULL
)
456 pd
= info
->private_data
= xcalloc (1, sizeof (struct riscv_private_data
));
459 for (i
= 0; i
< (int)ARRAY_SIZE (pd
->hi_addr
); i
++)
462 for (i
= 0; i
< info
->symtab_size
; i
++)
463 if (strcmp (bfd_asymbol_name (info
->symtab
[i
]), RISCV_GP_SYMBOL
) == 0)
464 pd
->gp
= bfd_asymbol_value (info
->symtab
[i
]);
467 pd
= info
->private_data
;
469 insnlen
= riscv_insn_length (word
);
471 /* RISC-V instructions are always little-endian. */
472 info
->endian_code
= BFD_ENDIAN_LITTLE
;
474 info
->bytes_per_chunk
= insnlen
% 4 == 0 ? 4 : 2;
475 info
->bytes_per_line
= 8;
476 /* We don't support constant pools, so this must be code. */
477 info
->display_endian
= info
->endian_code
;
478 info
->insn_info_valid
= 1;
479 info
->branch_delay_insns
= 0;
481 info
->insn_type
= dis_nonbranch
;
485 op
= riscv_hash
[OP_HASH_IDX (word
)];
490 /* If XLEN is not known, get its value from the ELF class. */
491 if (info
->mach
== bfd_mach_riscv64
)
493 else if (info
->mach
== bfd_mach_riscv32
)
495 else if (info
->section
!= NULL
)
497 Elf_Internal_Ehdr
*ehdr
= elf_elfheader (info
->section
->owner
);
498 xlen
= ehdr
->e_ident
[EI_CLASS
] == ELFCLASS64
? 64 : 32;
501 for (; op
->name
; op
++)
503 /* Does the opcode match? */
504 if (! (op
->match_func
) (op
, word
))
506 /* Is this a pseudo-instruction and may we print it as such? */
507 if (no_aliases
&& (op
->pinfo
& INSN_ALIAS
))
509 /* Is this instruction restricted to a certain value of XLEN? */
510 if ((op
->xlen_requirement
!= 0) && (op
->xlen_requirement
!= xlen
))
514 (*info
->fprintf_func
) (info
->stream
, "%s", op
->name
);
515 print_insn_args (op
->args
, word
, memaddr
, info
);
517 /* Try to disassemble multi-instruction addressing sequences. */
518 if (pd
->print_addr
!= (bfd_vma
)-1)
520 info
->target
= pd
->print_addr
;
521 (*info
->fprintf_func
) (info
->stream
, " # ");
522 (*info
->print_address_func
) (info
->target
, info
);
526 /* Finish filling out insn_info fields. */
527 switch (op
->pinfo
& INSN_TYPE
)
530 info
->insn_type
= dis_branch
;
532 case INSN_CONDBRANCH
:
533 info
->insn_type
= dis_condbranch
;
536 info
->insn_type
= dis_jsr
;
539 info
->insn_type
= dis_dref
;
545 if (op
->pinfo
& INSN_DATA_SIZE
)
547 int size
= ((op
->pinfo
& INSN_DATA_SIZE
)
548 >> INSN_DATA_SIZE_SHIFT
);
549 info
->data_size
= 1 << (size
- 1);
556 /* We did not find a match, so just print the instruction bits. */
557 info
->insn_type
= dis_noninsn
;
558 (*info
->fprintf_func
) (info
->stream
, "0x%llx", (unsigned long long)word
);
563 print_insn_riscv (bfd_vma memaddr
, struct disassemble_info
*info
)
570 if (info
->disassembler_options
!= NULL
)
572 parse_riscv_dis_options (info
->disassembler_options
);
573 /* Avoid repeatedly parsing the options. */
574 info
->disassembler_options
= NULL
;
576 else if (riscv_gpr_names
== NULL
)
577 set_default_riscv_dis_options ();
579 /* Instructions are a sequence of 2-byte packets in little-endian order. */
580 for (n
= 0; n
< sizeof (insn
) && n
< riscv_insn_length (insn
); n
+= 2)
582 status
= (*info
->read_memory_func
) (memaddr
+ n
, packet
, 2, info
);
585 /* Don't fail just because we fell off the end. */
588 (*info
->memory_error_func
) (status
, memaddr
, info
);
592 insn
|= ((insn_t
) bfd_getl16 (packet
)) << (8 * n
);
595 return riscv_disassemble_insn (memaddr
, insn
, info
);
599 riscv_get_disassembler (bfd
*abfd
)
603 const char *sec_name
= get_elf_backend_data (abfd
)->obj_attrs_section
;
604 if (bfd_get_section_by_name (abfd
, sec_name
) != NULL
)
606 obj_attribute
*attr
= elf_known_obj_attributes_proc (abfd
);
607 unsigned int Tag_a
= Tag_RISCV_priv_spec
;
608 unsigned int Tag_b
= Tag_RISCV_priv_spec_minor
;
609 unsigned int Tag_c
= Tag_RISCV_priv_spec_revision
;
610 riscv_get_priv_spec_class_from_numbers (attr
[Tag_a
].i
,
616 return print_insn_riscv
;
619 /* Prevent use of the fake labels that are generated as part of the DWARF
620 and for relaxable relocations in the assembler. */
623 riscv_symbol_is_valid (asymbol
* sym
,
624 struct disassemble_info
* info ATTRIBUTE_UNUSED
)
631 name
= bfd_asymbol_name (sym
);
633 return (strcmp (name
, RISCV_FAKE_LABEL_NAME
) != 0);
637 print_riscv_disassembler_options (FILE *stream
)
639 fprintf (stream
, _("\n\
640 The following RISC-V-specific disassembler options are supported for use\n\
641 with the -M switch (multiple options should be separated by commas):\n"));
643 fprintf (stream
, _("\n\
644 numeric Print numeric register names, rather than ABI names.\n"));
646 fprintf (stream
, _("\n\
647 no-aliases Disassemble only into canonical instructions, rather\n\
648 than into pseudoinstructions.\n"));
650 fprintf (stream
, _("\n\
651 priv-spec=PRIV Print the CSR according to the chosen privilege spec\n\
652 (1.9, 1.9.1, 1.10, 1.11).\n"));
654 fprintf (stream
, _("\n"));