opcodes/rx-decode.opc

   1 /* -*- c -*- */
   2 /* Copyright (C) 2012-2018 Free Software Foundation, Inc.
   3    Contributed by Red Hat.
   4    Written by DJ Delorie.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23 #include "sysdep.h"
  24 #include <stdio.h>
  25 #include <stdlib.h>
  26 #include <string.h>
  27 #include "ansidecl.h"
  28 #include "opcode/rx.h"
  29 #include "libiberty.h"
  30
  31 #define RX_OPCODE_BIG_ENDIAN 0
  32
  33 typedef struct
  34 {
  35   RX_Opcode_Decoded * rx;
  36   int (* getbyte)(void *);
  37   void * ptr;
  38   unsigned char * op;
  39 } LocalData;
  40
  41 static int trace = 0;
  42
  43 #define BSIZE 0
  44 #define WSIZE 1
  45 #define LSIZE 2
  46
  47 /* These are for when the upper bits are "don't care" or "undefined".  */
  48 static int bwl[4] =
  49 {
  50   RX_Byte,
  51   RX_Word,
  52   RX_Long,
  53   RX_Bad_Size /* Bogus instructions can have a size field set to 3.  */
  54 };
  55
  56 static int sbwl[4] =
  57 {
  58   RX_SByte,
  59   RX_SWord,
  60   RX_Long,
  61   RX_Bad_Size /* Bogus instructions can have a size field set to 3.  */
  62 };
  63
  64 static int ubw[4] =
  65 {
  66   RX_UByte,
  67   RX_UWord,
  68   RX_Bad_Size,/* Bogus instructions can have a size field set to 2.  */
  69   RX_Bad_Size /* Bogus instructions can have a size field set to 3.  */
  70 };
  71
  72 static int memex[4] =
  73 {
  74   RX_SByte,
  75   RX_SWord,
  76   RX_Long,
  77   RX_UWord
  78 };
  79
  80 #define ID(x) rx->id = RXO_##x
  81 #define OP(n,t,r,a) (rx->op[n].type = t, \
  82                      rx->op[n].reg = r,      \
  83                      rx->op[n].addend = a )
  84 #define OPs(n,t,r,a,s) (OP (n,t,r,a), \
  85                         rx->op[n].size = s )
  86
  87 /* This is for the BWL and BW bitfields.  */
  88 static int SCALE[] = { 1, 2, 4, 0 };
  89 /* This is for the prefix size enum.  */
  90 static int PSCALE[] = { 4, 1, 1, 1, 2, 2, 2, 3, 4 };
  91
  92 #define GET_SCALE(_indx)  ((unsigned)(_indx) < ARRAY_SIZE (SCALE) ? SCALE[(_indx)] : 0)
  93 #define GET_PSCALE(_indx) ((unsigned)(_indx) < ARRAY_SIZE (PSCALE) ? PSCALE[(_indx)] : 0)
  94
  95 static int flagmap[] = {0, 1, 2, 3, 0, 0, 0, 0,
  96                        16, 17, 0, 0, 0, 0, 0, 0 };
  97
  98 static int dsp3map[] = { 8, 9, 10, 3, 4, 5, 6, 7 };
  99
 100 /*
 101  *C     a constant (immediate) c
 102  *R     A register
 103  *I     Register indirect, no offset
 104  *Is    Register indirect, with offset
 105  *D     standard displacement: type (r,[r],dsp8,dsp16 code), register, BWL code
 106  *P     standard displacement: type (r,[r]), reg, assumes UByte
 107  *Pm    memex displacement: type (r,[r]), reg, memex code
 108  *cc    condition code.  */
 109
 110 #define DC(c)       OP (0, RX_Operand_Immediate, 0, c)
 111 #define DR(r)       OP (0, RX_Operand_Register,  r, 0)
 112 #define DI(r,a)     OP (0, RX_Operand_Indirect,  r, a)
 113 #define DIs(r,a,s)  OP (0, RX_Operand_Indirect,  r, (a) * GET_SCALE (s))
 114 #define DD(t,r,s)   rx_disp (0, t, r, bwl[s], ld);
 115 #define DF(r)       OP (0, RX_Operand_Flag,  flagmap[r], 0)
 116
 117 #define SC(i)       OP (1, RX_Operand_Immediate, 0, i)
 118 #define SR(r)       OP (1, RX_Operand_Register,  r, 0)
 119 #define SRR(r)      OP (1, RX_Operand_TwoReg,  r, 0)
 120 #define SI(r,a)     OP (1, RX_Operand_Indirect,  r, a)
 121 #define SIs(r,a,s)  OP (1, RX_Operand_Indirect,  r, (a) * GET_SCALE (s))
 122 #define SD(t,r,s)   rx_disp (1, t, r, bwl[s], ld);
 123 #define SP(t,r)     rx_disp (1, t, r, (t!=3) ? RX_UByte : RX_Long, ld); P(t, 1);
 124 #define SPm(t,r,m)  rx_disp (1, t, r, memex[m], ld); rx->op[1].size = memex[m];
 125 #define Scc(cc)     OP (1, RX_Operand_Condition,  cc, 0)
 126
 127 #define S2C(i)      OP (2, RX_Operand_Immediate, 0, i)
 128 #define S2R(r)      OP (2, RX_Operand_Register,  r, 0)
 129 #define S2I(r,a)    OP (2, RX_Operand_Indirect,  r, a)
 130 #define S2Is(r,a,s) OP (2, RX_Operand_Indirect,  r, (a) * GET_SCALE (s))
 131 #define S2D(t,r,s)  rx_disp (2, t, r, bwl[s], ld);
 132 #define S2P(t,r)    rx_disp (2, t, r, (t!=3) ? RX_UByte : RX_Long, ld); P(t, 2);
 133 #define S2Pm(t,r,m) rx_disp (2, t, r, memex[m], ld); rx->op[2].size = memex[m];
 134 #define S2cc(cc)    OP (2, RX_Operand_Condition,  cc, 0)
 135
 136 #define BWL(sz)     rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = bwl[sz]
 137 #define sBWL(sz)    rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = sbwl[sz]
 138 #define uBW(sz)     rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = ubw[sz]
 139 #define P(t, n)     rx->op[n].size = (t!=3) ? RX_UByte : RX_Long;
 140
 141 #define F(f) store_flags(rx, f)
 142
 143 #define AU ATTRIBUTE_UNUSED
 144 #define GETBYTE() (ld->op [ld->rx->n_bytes++] = ld->getbyte (ld->ptr))
 145
 146 #define SYNTAX(x) rx->syntax = x
 147
 148 #define UNSUPPORTED() \
 149   rx->syntax = "*unknown*"
 150
 151 #define IMM(sf)   immediate (sf, 0, ld)
 152 #define IMMex(sf) immediate (sf, 1, ld)
 153
 154 static int
 155 immediate (int sfield, int ex, LocalData * ld)
 156 {
 157   unsigned long i = 0, j;
 158
 159   switch (sfield)
 160     {
 161 #define B ((unsigned long) GETBYTE())
 162     case 0:
 163 #if RX_OPCODE_BIG_ENDIAN
 164       i  = B;
 165       if (ex && (i & 0x80))
 166         i -= 0x100;
 167       i <<= 24;
 168       i |= B << 16;
 169       i |= B << 8;
 170       i |= B;
 171 #else
 172       i = B;
 173       i |= B << 8;
 174       i |= B << 16;
 175       j = B;
 176       if (ex && (j & 0x80))
 177         j -= 0x100;
 178       i |= j << 24;
 179 #endif
 180       break;
 181     case 3:
 182 #if RX_OPCODE_BIG_ENDIAN
 183       i  = B << 16;
 184       i |= B << 8;
 185       i |= B;
 186 #else
 187       i  = B;
 188       i |= B << 8;
 189       i |= B << 16;
 190 #endif
 191       if (ex && (i & 0x800000))
 192         i -= 0x1000000;
 193       break;
 194     case 2:
 195 #if RX_OPCODE_BIG_ENDIAN
 196       i |= B << 8;
 197       i |= B;
 198 #else
 199       i |= B;
 200       i |= B << 8;
 201 #endif
 202       if (ex && (i & 0x8000))
 203         i -= 0x10000;
 204       break;
 205     case 1:
 206       i |= B;
 207       if (ex && (i & 0x80))
 208         i -= 0x100;
 209       break;
 210     default:
 211       abort();
 212     }
 213   return i;
 214 }
 215
 216 static void
 217 rx_disp (int n, int type, int reg, unsigned int size, LocalData * ld)
 218 {
 219   int disp;
 220
 221   ld->rx->op[n].reg = reg;
 222   switch (type)
 223     {
 224     case 3:
 225       ld->rx->op[n].type = RX_Operand_Register;
 226       break;
 227     case 0:
 228       ld->rx->op[n].type = RX_Operand_Zero_Indirect;
 229       ld->rx->op[n].addend = 0;
 230       break;
 231     case 1:
 232       ld->rx->op[n].type = RX_Operand_Indirect;
 233       disp = GETBYTE ();
 234       ld->rx->op[n].addend = disp * GET_PSCALE (size);
 235       break;
 236     case 2:
 237       ld->rx->op[n].type = RX_Operand_Indirect;
 238       disp = GETBYTE ();
 239 #if RX_OPCODE_BIG_ENDIAN
 240       disp = disp * 256 + GETBYTE ();
 241 #else
 242       disp = disp + GETBYTE () * 256;
 243 #endif
 244       ld->rx->op[n].addend = disp * GET_PSCALE (size);
 245       break;
 246     default:
 247       abort ();
 248     }
 249 }
 250
 251 #define xO 8
 252 #define xS 4
 253 #define xZ 2
 254 #define xC 1
 255
 256 #define F_____
 257 #define F___ZC rx->flags_0 = rx->flags_s = xZ|xC;
 258 #define F__SZ_ rx->flags_0 = rx->flags_s = xS|xZ;
 259 #define F__SZC rx->flags_0 = rx->flags_s = xS|xZ|xC;
 260 #define F_0SZC rx->flags_0 = xO|xS|xZ|xC; rx->flags_s = xS|xZ|xC;
 261 #define F_O___ rx->flags_0 = rx->flags_s = xO;
 262 #define F_OS__ rx->flags_0 = rx->flags_s = xO|xS;
 263 #define F_OSZ_ rx->flags_0 = rx->flags_s = xO|xS|xZ;
 264 #define F_OSZC rx->flags_0 = rx->flags_s = xO|xS|xZ|xC;
 265
 266 int
 267 rx_decode_opcode (unsigned long pc AU,
 268                   RX_Opcode_Decoded * rx,
 269                   int (* getbyte)(void *),
 270                   void * ptr)
 271 {
 272   LocalData lds, * ld = &lds;
 273   unsigned char op[20] = {0};
 274
 275   lds.rx = rx;
 276   lds.getbyte = getbyte;
 277   lds.ptr = ptr;
 278   lds.op = op;
 279
 280   memset (rx, 0, sizeof (*rx));
 281   BWL(LSIZE);
 282
 283 /** VARY sz 00 01 10 */
 284
 285 /*----------------------------------------------------------------------*/
 286 /* MOV                                                                  */
 287
 288 /** 0111 0101 0100 rdst         mov%s   #%1, %0 */
 289   ID(mov); DR(rdst); SC(IMM (1)); F_____;
 290
 291 /** 1111 10sd rdst im sz        mov%s   #%1, %0 */
 292   ID(mov); DD(sd, rdst, sz);
 293   if ((im == 1 && sz == 0)
 294       || (im == 2 && sz == 1)
 295       || (im == 0 && sz == 2))
 296     {
 297       BWL (sz);
 298       SC(IMM(im));
 299     }
 300   else
 301     {
 302       sBWL (sz);
 303       SC(IMMex(im));
 304     }
 305    F_____;
 306
 307 /** 0110 0110 immm rdst         mov%s   #%1, %0 */
 308   ID(mov); DR(rdst); SC(immm); F_____;
 309
 310 /** 0011 11sz d dst sppp                mov%s   #%1, %0 */
 311   ID(mov); sBWL (sz); DIs(dst, d*16+sppp, sz); SC(IMM(1)); F_____;
 312
 313 /** 11sz sd ss rsrc rdst        mov%s   %1, %0 */
 314   if (sd == 3 && ss == 3 && sz == 2 && rsrc == 0 && rdst == 0)
 315     {
 316       ID(nop2);
 317       SYNTAX ("nop\t; mov.l\tr0, r0");
 318     }
 319   else
 320     {
 321       ID(mov); sBWL(sz); F_____;
 322       if ((ss == 3) && (sd != 3))
 323         {
 324           SD(ss, rdst, sz); DD(sd, rsrc, sz);
 325         }
 326       else
 327         {
 328           SD(ss, rsrc, sz); DD(sd, rdst, sz);
 329         }
 330     }
 331
 332 /** 10sz 1dsp a src b dst       mov%s   %1, %0 */
 333   ID(mov); sBWL(sz); DR(dst); SIs(src, dsp*4+a*2+b, sz); F_____;
 334
 335 /** 10sz 0dsp a dst b src       mov%s   %1, %0 */
 336   ID(mov); sBWL(sz); DIs(dst, dsp*4+a*2+b, sz); SR(src); F_____;
 337
 338 /** 1111 1110 01sz isrc bsrc rdst       mov%s   [%1, %2], %0 */
 339   ID(movbi); sBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____;
 340
 341 /** 1111 1110 00sz isrc bsrc rdst       mov%s   %0, [%1, %2] */
 342   ID(movbir); sBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____;
 343
 344 /** 1111 1110 11sz isrc bsrc rdst       movu%s  [%1, %2], %0 */
 345   ID(movbi); uBW(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____;
 346
 347 /** 1111 1101 0010 0p sz rdst rsrc      mov%s   %1, %0 */
 348   ID(mov); sBWL (sz); SR(rsrc); F_____;
 349   OP(0, p ? RX_Operand_Predec : RX_Operand_Postinc, rdst, 0);
 350
 351 /** 1111 1101 0010 1p sz rsrc rdst      mov%s   %1, %0 */
 352   ID(mov); sBWL (sz); DR(rdst); F_____;
 353   OP(1, p ? RX_Operand_Predec : RX_Operand_Postinc, rsrc, 0);
 354
 355 /** 1011 w dsp a src b dst      movu%s  %1, %0 */
 356   ID(mov); uBW(w); DR(dst); SIs(src, dsp*4+a*2+b, w); F_____;
 357
 358 /** 0101 1 s ss rsrc rdst       movu%s  %1, %0 */
 359   ID(mov); uBW(s); SD(ss, rsrc, s); DR(rdst); F_____;
 360
 361 /** 1111 1101 0011 1p sz rsrc rdst      movu%s  %1, %0 */
 362   ID(mov); uBW (sz); DR(rdst); F_____;
 363    OP(1, p ? RX_Operand_Predec : RX_Operand_Postinc, rsrc, 0);
 364
 365 /*----------------------------------------------------------------------*/
 366 /* PUSH/POP                                                             */
 367
 368 /** 0110 1111 dsta dstb         popm    %1-%2 */
 369   ID(popm); SR(dsta); S2R(dstb); F_____;
 370
 371 /** 0110 1110 dsta dstb         pushm   %1-%2 */
 372   ID(pushm); SR(dsta); S2R(dstb); F_____;
 373
 374 /** 0111 1110 1011 rdst         pop     %0 */
 375   ID(mov); OP(1, RX_Operand_Postinc, 0, 0); DR(rdst); F_____;
 376
 377 /** 0111 1110 10sz rsrc         push%s  %1 */
 378   ID(mov); BWL(sz); OP(0, RX_Operand_Predec, 0, 0); SR(rsrc); F_____;
 379
 380 /** 1111 01ss rsrc 10sz         push%s  %1 */
 381   ID(mov); BWL(sz); OP(0, RX_Operand_Predec, 0, 0); SD(ss, rsrc, sz); F_____;
 382
 383 /*----------------------------------------------------------------------*/
 384 /* XCHG                                                                 */
 385
 386 /** 1111 1100 0100 00ss rsrc rdst       xchg    %1%S1, %0 */
 387   ID(xchg); DR(rdst); SP(ss, rsrc);
 388
 389 /** 0000 0110 mx10 00ss 0001 0000 rsrc rdst     xchg    %1%S1, %0 */
 390   ID(xchg); DR(rdst); SPm(ss, rsrc, mx);
 391
 392 /*----------------------------------------------------------------------*/
 393 /* STZ/STNZ                                                             */
 394
 395 /** 1111 1101 0111 im00 1110rdst        stz     #%1, %0 */
 396   ID(stcc); SC(IMMex(im)); DR(rdst); S2cc(RXC_z);
 397
 398 /** 1111 1101 0111 im00 1111rdst        stnz    #%1, %0 */
 399   ID(stcc); SC(IMMex(im)); DR(rdst); S2cc(RXC_nz);
 400
 401 /*----------------------------------------------------------------------*/
 402 /* RTSD                                                                 */
 403
 404 /** 0110 0111                   rtsd    #%1 */
 405   ID(rtsd); SC(IMM(1) * 4);
 406
 407 /** 0011 1111 rega regb         rtsd    #%1, %2-%0 */
 408   ID(rtsd); SC(IMM(1) * 4); S2R(rega); DR(regb);
 409
 410 /*----------------------------------------------------------------------*/
 411 /* AND                                                                  */
 412
 413 /** 0110 0100 immm rdst                 and     #%1, %0 */
 414   ID(and); SC(immm); DR(rdst); F__SZ_;
 415
 416 /** 0111 01im 0010 rdst                 and     #%1, %0 */
 417   ID(and); SC(IMMex(im)); DR(rdst); F__SZ_;
 418
 419 /** 0101 00ss rsrc rdst                 and     %1%S1, %0 */
 420   ID(and); SP(ss, rsrc); DR(rdst); F__SZ_;
 421
 422 /** 0000 0110 mx01 00ss rsrc rdst       and     %1%S1, %0 */
 423   ID(and); SPm(ss, rsrc, mx); DR(rdst); F__SZ_;
 424
 425 /** 1111 1111 0100 rdst srca srcb       and     %2, %1, %0 */
 426   ID(and); DR(rdst); SR(srcb); S2R(srca); F__SZ_;
 427
 428 /*----------------------------------------------------------------------*/
 429 /* OR                                                                   */
 430
 431 /** 0110 0101 immm rdst                 or      #%1, %0 */
 432   ID(or); SC(immm); DR(rdst); F__SZ_;
 433
 434 /** 0111 01im 0011 rdst                 or      #%1, %0 */
 435   ID(or); SC(IMMex(im)); DR(rdst); F__SZ_;
 436
 437 /** 0101 01ss rsrc rdst                 or      %1%S1, %0 */
 438   ID(or); SP(ss, rsrc); DR(rdst); F__SZ_;
 439
 440 /** 0000 0110 mx01 01ss rsrc rdst                       or      %1%S1, %0 */
 441   ID(or); SPm(ss, rsrc, mx); DR(rdst); F__SZ_;
 442
 443 /** 1111 1111 0101 rdst srca srcb       or      %2, %1, %0 */
 444   ID(or); DR(rdst); SR(srcb); S2R(srca); F__SZ_;
 445
 446 /*----------------------------------------------------------------------*/
 447 /* XOR                                                                  */
 448
 449 /** 1111 1101 0111 im00 1101rdst        xor     #%1, %0 */
 450   ID(xor); SC(IMMex(im)); DR(rdst); F__SZ_;
 451
 452 /** 1111 1100 0011 01ss rsrc rdst       xor     %1%S1, %0 */
 453   ID(xor); SP(ss, rsrc); DR(rdst); F__SZ_;
 454
 455 /** 0000 0110 mx10 00ss 0000 1101 rsrc rdst     xor     %1%S1, %0 */
 456   ID(xor); SPm(ss, rsrc, mx); DR(rdst); F__SZ_;
 457
 458 /*----------------------------------------------------------------------*/
 459 /* NOT                                                                  */
 460
 461 /** 0111 1110 0000 rdst                 not     %0 */
 462   ID(xor); DR(rdst); SR(rdst); S2C(~0); F__SZ_;
 463
 464 /** 1111 1100 0011 1011 rsrc rdst       not     %1, %0 */
 465   ID(xor); DR(rdst); SR(rsrc); S2C(~0); F__SZ_;
 466
 467 /*----------------------------------------------------------------------*/
 468 /* TST                                                                  */
 469
 470 /** 1111 1101 0111 im00 1100rdst        tst     #%1, %2 */
 471   ID(and); SC(IMMex(im)); S2R(rdst); F__SZ_;
 472
 473 /** 1111 1100 0011 00ss rsrc rdst       tst     %1%S1, %2 */
 474   ID(and); SP(ss, rsrc); S2R(rdst); F__SZ_;
 475
 476 /** 0000 0110 mx10 00ss 0000 1100 rsrc rdst     tst     %1%S1, %2 */
 477   ID(and); SPm(ss, rsrc, mx); S2R(rdst); F__SZ_;
 478
 479 /*----------------------------------------------------------------------*/
 480 /* NEG                                                                  */
 481
 482 /** 0111 1110 0001 rdst                 neg     %0 */
 483   ID(sub); DR(rdst); SC(0); S2R(rdst); F_OSZC;
 484
 485 /** 1111 1100 0000 0111 rsrc rdst       neg     %2, %0 */
 486   ID(sub); DR(rdst); SC(0); S2R(rsrc); F_OSZC;
 487
 488 /*----------------------------------------------------------------------*/
 489 /* ADC                                                                  */
 490
 491 /** 1111 1101 0111 im00 0010rdst        adc     #%1, %0 */
 492   ID(adc); SC(IMMex(im)); DR(rdst); F_OSZC;
 493
 494 /** 1111 1100 0000 1011 rsrc rdst       adc     %1, %0 */
 495   ID(adc); SR(rsrc); DR(rdst); F_OSZC;
 496
 497 /** 0000 0110 1010 00ss 0000 0010 rsrc rdst     adc     %1%S1, %0 */
 498   ID(adc); SPm(ss, rsrc, 2); DR(rdst); F_OSZC;
 499
 500 /*----------------------------------------------------------------------*/
 501 /* ADD                                                                  */
 502
 503 /** 0110 0010 immm rdst                 add     #%1, %0 */
 504   ID(add); SC(immm); DR(rdst); F_OSZC;
 505
 506 /** 0100 10ss rsrc rdst                 add     %1%S1, %0 */
 507   ID(add); SP(ss, rsrc); DR(rdst); F_OSZC;
 508
 509 /** 0000 0110 mx00 10ss rsrc rdst       add     %1%S1, %0 */
 510   ID(add); SPm(ss, rsrc, mx); DR(rdst); F_OSZC;
 511
 512 /** 0111 00im rsrc rdst                 add     #%1, %2, %0 */
 513   ID(add); SC(IMMex(im)); S2R(rsrc); DR(rdst); F_OSZC;
 514
 515 /** 1111 1111 0010 rdst srca srcb       add     %2, %1, %0 */
 516   ID(add); DR(rdst); SR(srcb); S2R(srca); F_OSZC;
 517
 518 /*----------------------------------------------------------------------*/
 519 /* CMP                                                                  */
 520
 521 /** 0110 0001 immm rdst                 cmp     #%2, %1 */
 522   ID(sub); S2C(immm); SR(rdst); F_OSZC;
 523
 524 /** 0111 01im 0000 rsrc         cmp     #%2, %1%S1 */
 525   ID(sub); SR(rsrc); S2C(IMMex(im)); F_OSZC;
 526
 527 /** 0111 0101 0101 rsrc                 cmp     #%2, %1 */
 528   ID(sub); SR(rsrc); S2C(IMM(1)); F_OSZC;
 529
 530 /** 0100 01ss rsrc rdst         cmp     %2%S2, %1 */
 531   ID(sub); S2P(ss, rsrc); SR(rdst); F_OSZC;
 532
 533 /** 0000 0110 mx00 01ss rsrc rdst               cmp     %2%S2, %1 */
 534   ID(sub); S2Pm(ss, rsrc, mx); SR(rdst); F_OSZC;
 535
 536 /*----------------------------------------------------------------------*/
 537 /* SUB                                                                  */
 538
 539 /** 0110 0000 immm rdst                 sub     #%2, %0 */
 540   ID(sub); S2C(immm); SR(rdst); DR(rdst); F_OSZC;
 541
 542 /** 0100 00ss rsrc rdst                 sub     %2%S2, %1 */
 543   ID(sub); S2P(ss, rsrc); SR(rdst); DR(rdst); F_OSZC;
 544
 545 /** 0000 0110 mx00 00ss rsrc rdst                       sub     %2%S2, %1 */
 546   ID(sub); S2Pm(ss, rsrc, mx); SR(rdst); DR(rdst); F_OSZC;
 547
 548 /** 1111 1111 0000 rdst srca srcb       sub     %2, %1, %0 */
 549   ID(sub); DR(rdst); SR(srcb); S2R(srca); F_OSZC;
 550
 551 /*----------------------------------------------------------------------*/
 552 /* SBB                                                                  */
 553
 554 /** 1111 1100 0000 0011 rsrc rdst       sbb     %1, %0 */
 555   ID(sbb); SR (rsrc); DR(rdst); F_OSZC;
 556
 557   /* FIXME: only supports .L */
 558 /** 0000 0110 mx10 00sp 0000 0000 rsrc rdst     sbb     %1%S1, %0 */
 559   ID(sbb); SPm(sp, rsrc, mx); DR(rdst); F_OSZC;
 560
 561 /*----------------------------------------------------------------------*/
 562 /* ABS                                                                  */
 563
 564 /** 0111 1110 0010 rdst                 abs     %0 */
 565   ID(abs); DR(rdst); SR(rdst); F_OSZ_;
 566
 567 /** 1111 1100 0000 1111 rsrc rdst       abs     %1, %0 */
 568   ID(abs); DR(rdst); SR(rsrc); F_OSZ_;
 569
 570 /*----------------------------------------------------------------------*/
 571 /* MAX                                                                  */
 572
 573 /** 1111 1101 0111 im00 0100rdst        max     #%1, %0 */
 574   int val = IMMex (im);
 575   if (im == 0 && (unsigned) val == 0x80000000 && rdst == 0)
 576     {
 577       ID (nop7);
 578       SYNTAX("nop\t; max\t#0x80000000, r0");
 579     }
 580   else
 581     {
 582       ID(max);
 583     }
 584   DR(rdst); SC(val);
 585
 586 /** 1111 1100 0001 00ss rsrc rdst       max     %1%S1, %0 */
 587   if (ss == 3 && rsrc == 0 && rdst == 0)
 588     {
 589       ID(nop3);
 590       SYNTAX("nop\t; max\tr0, r0");
 591     }
 592   else
 593     {
 594       ID(max); SP(ss, rsrc); DR(rdst);
 595     }
 596
 597 /** 0000 0110 mx10 00ss 0000 0100 rsrc rdst     max     %1%S1, %0 */
 598   ID(max); SPm(ss, rsrc, mx); DR(rdst);
 599
 600 /*----------------------------------------------------------------------*/
 601 /* MIN                                                                  */
 602
 603 /** 1111 1101 0111 im00 0101rdst        min     #%1, %0 */
 604   ID(min); DR(rdst); SC(IMMex(im));
 605
 606 /** 1111 1100 0001 01ss rsrc rdst       min     %1%S1, %0 */
 607   ID(min); SP(ss, rsrc); DR(rdst);
 608
 609 /** 0000 0110 mx10 00ss 0000 0101 rsrc rdst     min     %1%S1, %0 */
 610   ID(min); SPm(ss, rsrc, mx); DR(rdst);
 611
 612 /*----------------------------------------------------------------------*/
 613 /* MUL                                                                  */
 614
 615 /** 0110 0011 immm rdst                 mul     #%1, %0 */
 616   if (immm == 1 && rdst == 0)
 617     {
 618       ID(nop2);
 619       SYNTAX ("nop\t; mul\t#1, r0");
 620     }
 621   else
 622     {
 623       ID(mul);
 624     }
 625   DR(rdst); SC(immm); F_____;
 626
 627 /** 0111 01im 0001rdst                  mul     #%1, %0 */
 628   int val = IMMex(im);
 629   if (val == 1 && rdst == 0)
 630     {
 631       SYNTAX("nop\t; mul\t#1, r0");
 632       switch (im)
 633         {
 634         case 2: ID(nop4); break;
 635         case 3: ID(nop5); break;
 636         case 0: ID(nop6); break;
 637         default:
 638           ID(mul);
 639           SYNTAX("mul   #%1, %0");
 640           break;
 641         }
 642     }
 643   else
 644     {
 645       ID(mul);
 646     }
 647   DR(rdst); SC(val); F_____;
 648
 649 /** 0100 11ss rsrc rdst                 mul     %1%S1, %0 */
 650   ID(mul); SP(ss, rsrc); DR(rdst); F_____;
 651
 652 /** 0000 0110 mx00 11ss rsrc rdst       mul     %1%S1, %0 */
 653   ID(mul); SPm(ss, rsrc, mx); DR(rdst); F_____;
 654
 655 /** 1111 1111 0011 rdst srca srcb       mul     %2, %1, %0 */
 656   ID(mul); DR(rdst); SR(srcb); S2R(srca); F_____;
 657
 658 /*----------------------------------------------------------------------*/
 659 /* EMUL                                                                 */
 660
 661 /** 1111 1101 0111 im00 0110rdst        emul    #%1, %0 */
 662   ID(emul); DR(rdst); SC(IMMex(im));
 663
 664 /** 1111 1100 0001 10ss rsrc rdst       emul    %1%S1, %0 */
 665   ID(emul); SP(ss, rsrc); DR(rdst);
 666
 667 /** 0000 0110 mx10 00ss 0000 0110 rsrc rdst     emul    %1%S1, %0 */
 668   ID(emul); SPm(ss, rsrc, mx); DR(rdst);
 669
 670 /*----------------------------------------------------------------------*/
 671 /* EMULU                                                                        */
 672
 673 /** 1111 1101 0111 im00 0111rdst        emulu   #%1, %0 */
 674   ID(emulu); DR(rdst); SC(IMMex(im));
 675
 676 /** 1111 1100 0001 11ss rsrc rdst       emulu   %1%S1, %0 */
 677   ID(emulu); SP(ss, rsrc); DR(rdst);
 678
 679 /** 0000 0110 mx10 00ss 0000 0111 rsrc rdst     emulu   %1%S1, %0 */
 680   ID(emulu); SPm(ss, rsrc, mx); DR(rdst);
 681
 682 /*----------------------------------------------------------------------*/
 683 /* DIV                                                                  */
 684
 685 /** 1111 1101 0111 im00 1000rdst        div     #%1, %0 */
 686   ID(div); DR(rdst); SC(IMMex(im)); F_O___;
 687
 688 /** 1111 1100 0010 00ss rsrc rdst       div     %1%S1, %0 */
 689   ID(div); SP(ss, rsrc); DR(rdst); F_O___;
 690
 691 /** 0000 0110 mx10 00ss 0000 1000 rsrc rdst     div     %1%S1, %0 */
 692   ID(div); SPm(ss, rsrc, mx); DR(rdst); F_O___;
 693
 694 /*----------------------------------------------------------------------*/
 695 /* DIVU                                                                 */
 696
 697 /** 1111 1101 0111 im00 1001rdst        divu    #%1, %0 */
 698   ID(divu); DR(rdst); SC(IMMex(im)); F_O___;
 699
 700 /** 1111 1100 0010 01ss rsrc rdst       divu    %1%S1, %0 */
 701   ID(divu); SP(ss, rsrc); DR(rdst); F_O___;
 702
 703 /** 0000 0110 mx10 00ss 0000 1001 rsrc rdst     divu    %1%S1, %0 */
 704   ID(divu); SPm(ss, rsrc, mx); DR(rdst); F_O___;
 705
 706 /*----------------------------------------------------------------------*/
 707 /* SHIFT                                                                */
 708
 709 /** 0110 110i mmmm rdst                 shll    #%2, %0 */
 710   ID(shll); S2C(i*16+mmmm); SR(rdst); DR(rdst); F_OSZC;
 711
 712 /** 1111 1101 0110 0010 rsrc rdst       shll    %2, %0 */
 713   ID(shll); S2R(rsrc); SR(rdst); DR(rdst); F_OSZC;
 714
 715 /** 1111 1101 110immmm rsrc rdst        shll    #%2, %1, %0 */
 716   ID(shll); S2C(immmm); SR(rsrc); DR(rdst); F_OSZC;
 717
 718
 719 /** 0110 101i mmmm rdst                 shar    #%2, %0 */
 720   ID(shar); S2C(i*16+mmmm); SR(rdst); DR(rdst); F_0SZC;
 721
 722 /** 1111 1101 0110 0001 rsrc rdst       shar    %2, %0 */
 723   ID(shar); S2R(rsrc); SR(rdst); DR(rdst); F_0SZC;
 724
 725 /** 1111 1101 101immmm rsrc rdst        shar    #%2, %1, %0 */
 726   ID(shar); S2C(immmm); SR(rsrc); DR(rdst); F_0SZC;
 727
 728
 729 /** 0110 100i mmmm rdst                 shlr    #%2, %0 */
 730   ID(shlr); S2C(i*16+mmmm); SR(rdst); DR(rdst); F__SZC;
 731
 732 /** 1111 1101 0110 0000 rsrc rdst       shlr    %2, %0 */
 733   ID(shlr); S2R(rsrc); SR(rdst); DR(rdst); F__SZC;
 734
 735 /** 1111 1101 100immmm rsrc rdst        shlr    #%2, %1, %0 */
 736   ID(shlr); S2C(immmm); SR(rsrc); DR(rdst); F__SZC;
 737
 738 /*----------------------------------------------------------------------*/
 739 /* ROTATE                                                               */
 740
 741 /** 0111 1110 0101 rdst                 rolc    %0 */
 742   ID(rolc); DR(rdst); F__SZC;
 743
 744 /** 0111 1110 0100 rdst                 rorc    %0 */
 745   ID(rorc); DR(rdst); F__SZC;
 746
 747 /** 1111 1101 0110 111i mmmm rdst       rotl    #%1, %0 */
 748   ID(rotl); SC(i*16+mmmm); DR(rdst); F__SZC;
 749
 750 /** 1111 1101 0110 0110 rsrc rdst       rotl    %1, %0 */
 751   ID(rotl); SR(rsrc); DR(rdst); F__SZC;
 752
 753 /** 1111 1101 0110 110i mmmm rdst       rotr    #%1, %0 */
 754   ID(rotr); SC(i*16+mmmm); DR(rdst); F__SZC;
 755
 756 /** 1111 1101 0110 0100 rsrc rdst       rotr    %1, %0 */
 757   ID(rotr); SR(rsrc); DR(rdst); F__SZC;
 758
 759 /** 1111 1101 0110 0101 rsrc rdst       revw    %1, %0 */
 760   ID(revw); SR(rsrc); DR(rdst);
 761
 762 /** 1111 1101 0110 0111 rsrc rdst       revl    %1, %0 */
 763   ID(revl); SR(rsrc); DR(rdst);
 764
 765 /*----------------------------------------------------------------------*/
 766 /* BRANCH                                                               */
 767
 768 /** 0001 n dsp                  b%1.s   %a0 */
 769   ID(branch); Scc(n); DC(pc + dsp3map[dsp]);
 770
 771 /** 0010 cond                   b%1.b   %a0 */
 772   ID(branch); Scc(cond); DC(pc + IMMex (1));
 773
 774 /** 0011 101c                   b%1.w   %a0 */
 775   ID(branch); Scc(c); DC(pc + IMMex (2));
 776
 777
 778 /** 0000 1dsp                   bra.s   %a0 */
 779   ID(branch); DC(pc + dsp3map[dsp]);
 780
 781 /** 0010 1110                   bra.b   %a0 */
 782   ID(branch); DC(pc + IMMex(1));
 783
 784 /** 0011 1000                   bra.w   %a0 */
 785   ID(branch); DC(pc + IMMex(2));
 786
 787 /** 0000 0100                   bra.a   %a0 */
 788   ID(branch); DC(pc + IMMex(3));
 789
 790 /** 0111 1111 0100 rsrc         bra.l   %0 */
 791   ID(branchrel); DR(rsrc);
 792
 793
 794 /** 0111 1111 0000 rsrc         jmp     %0 */
 795   ID(branch); DR(rsrc);
 796
 797 /** 0111 1111 0001 rsrc         jsr     %0 */
 798   ID(jsr); DR(rsrc);
 799
 800 /** 0011 1001                   bsr.w   %a0 */
 801   ID(jsr); DC(pc + IMMex(2));
 802
 803 /** 0000 0101                   bsr.a   %a0 */
 804   ID(jsr); DC(pc + IMMex(3));
 805
 806 /** 0111 1111 0101 rsrc         bsr.l   %0 */
 807   ID(jsrrel); DR(rsrc);
 808
 809 /** 0000 0010                   rts */
 810   ID(rts);
 811
 812 /*----------------------------------------------------------------------*/
 813 /* NOP                                                          */
 814
 815 /** 0000 0011                   nop */
 816   ID(nop);
 817
 818 /*----------------------------------------------------------------------*/
 819 /* STRING FUNCTIONS                                                     */
 820
 821 /** 0111 1111 1000 0011         scmpu */
 822   ID(scmpu); F___ZC;
 823
 824 /** 0111 1111 1000 0111         smovu */
 825   ID(smovu);
 826
 827 /** 0111 1111 1000 1011         smovb */
 828   ID(smovb);
 829
 830 /** 0111 1111 1000 00sz         suntil%s */
 831   ID(suntil); BWL(sz); F___ZC;
 832
 833 /** 0111 1111 1000 01sz         swhile%s */
 834   ID(swhile); BWL(sz); F___ZC;
 835
 836 /** 0111 1111 1000 1111         smovf */
 837   ID(smovf);
 838
 839 /** 0111 1111 1000 10sz         sstr%s */
 840   ID(sstr); BWL(sz);
 841
 842 /*----------------------------------------------------------------------*/
 843 /* RMPA                                                                 */
 844
 845 /** 0111 1111 1000 11sz         rmpa%s */
 846   ID(rmpa); BWL(sz); F_OS__;
 847
 848 /*----------------------------------------------------------------------*/
 849 /* HI/LO stuff                                                          */
 850
 851 /** 1111 1101 0000 a000 srca srcb       mulhi   %1, %2, %0 */
 852   ID(mulhi); DR(a+32); SR(srca); S2R(srcb); F_____;
 853
 854 /** 1111 1101 0000 a001 srca srcb       mullo   %1, %2, %0 */
 855   ID(mullo); DR(a+32); SR(srca); S2R(srcb); F_____;
 856
 857 /** 1111 1101 0000 a100 srca srcb       machi   %1, %2, %0 */
 858   ID(machi); DR(a+32); SR(srca); S2R(srcb); F_____;
 859
 860 /** 1111 1101 0000 a101 srca srcb       maclo   %1, %2, %0 */
 861   ID(maclo); DR(a+32); SR(srca); S2R(srcb); F_____;
 862
 863 /** 1111 1101 0001 0111 a000 rsrc       mvtachi %1, %0 */
 864   ID(mvtachi); DR(a+32); SR(rsrc); F_____;
 865
 866 /** 1111 1101 0001 0111 a001 rsrc       mvtaclo %1, %0 */
 867   ID(mvtaclo); DR(a+32); SR(rsrc); F_____;
 868
 869 /** 1111 1101 0001 111i a m00 rdst      mvfachi #%2, %1, %0 */
 870   ID(mvfachi); S2C(((i^1)<<1)|m); SR(a+32); DR(rdst); F_____;
 871
 872 /** 1111 1101 0001 111i a m10 rdst      mvfacmi #%2, %1, %0 */
 873   ID(mvfacmi); S2C(((i^1)<<1)|m); SR(a+32); DR(rdst); F_____;
 874
 875 /** 1111 1101 0001 111i a m01 rdst      mvfaclo #%2, %1, %0 */
 876   ID(mvfaclo); S2C(((i^1)<<1)|m); SR(a+32); DR(rdst); F_____;
 877
 878 /** 1111 1101 0001 1000 a00i 0000       racw    #%1, %0 */
 879   ID(racw); SC(i+1); DR(a+32); F_____;
 880
 881 /*----------------------------------------------------------------------*/
 882 /* SAT                                                                  */
 883
 884 /** 0111 1110 0011 rdst         sat     %0 */
 885   ID(sat); DR (rdst);
 886
 887 /** 0111 1111 1001 0011         satr */
 888   ID(satr);
 889
 890 /*----------------------------------------------------------------------*/
 891 /* FLOAT                                                                */
 892
 893 /** 1111 1101 0111 0010 0010 rdst       fadd    #%1, %0 */
 894   ID(fadd); DR(rdst); SC(IMM(0)); F__SZ_;
 895
 896 /** 1111 1100 1000 10sd rsrc rdst       fadd    %1%S1, %0 */
 897   ID(fadd); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
 898
 899 /** 1111 1101 0111 0010 0001 rdst       fcmp    #%1, %0 */
 900   ID(fcmp); DR(rdst); SC(IMM(0)); F_OSZ_;
 901
 902 /** 1111 1100 1000 01sd rsrc rdst       fcmp    %1%S1, %0 */
 903   ID(fcmp); DR(rdst); SD(sd, rsrc, LSIZE); F_OSZ_;
 904
 905 /** 1111 1101 0111 0010 0000 rdst       fsub    #%1, %0 */
 906   ID(fsub); DR(rdst); SC(IMM(0)); F__SZ_;
 907
 908 /** 1111 1100 1000 00sd rsrc rdst       fsub    %1%S1, %0 */
 909   ID(fsub); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
 910
 911 /** 1111 1100 1001 01sd rsrc rdst       ftoi    %1%S1, %0 */
 912   ID(ftoi); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
 913
 914 /** 1111 1101 0111 0010 0011 rdst       fmul    #%1, %0 */
 915   ID(fmul); DR(rdst); SC(IMM(0)); F__SZ_;
 916
 917 /** 1111 1100 1000 11sd rsrc rdst       fmul    %1%S1, %0 */
 918   ID(fmul); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
 919
 920 /** 1111 1101 0111 0010 0100 rdst       fdiv    #%1, %0 */
 921   ID(fdiv); DR(rdst); SC(IMM(0)); F__SZ_;
 922
 923 /** 1111 1100 1001 00sd rsrc rdst       fdiv    %1%S1, %0 */
 924   ID(fdiv); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
 925
 926 /** 1111 1100 1001 10sd rsrc rdst       round   %1%S1, %0 */
 927   ID(round); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
 928
 929 /** 1111 1100 0100 01sd rsrc rdst       itof    %1%S1, %0 */
 930   ID(itof); DR (rdst); SP(sd, rsrc); F__SZ_;
 931
 932 /** 0000 0110 mx10 00sd 0001 0001 rsrc rdst     itof    %1%S1, %0 */
 933   ID(itof); DR (rdst); SPm(sd, rsrc, mx); F__SZ_;
 934
 935 /*----------------------------------------------------------------------*/
 936 /* BIT OPS                                                              */
 937
 938 /** 1111 00sd rdst 0bit                 bset    #%1, %0%S0 */
 939   ID(bset); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE); F_____;
 940
 941 /** 1111 1100 0110 00sd rdst rsrc       bset    %1, %0%S0 */
 942   ID(bset); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE); F_____;
 943   if (sd == 3) /* bset reg,reg */
 944     BWL(LSIZE);
 945
 946 /** 0111 100b ittt rdst                 bset    #%1, %0 */
 947   ID(bset); BWL(LSIZE); SC(b*16+ittt); DR(rdst); F_____;
 948
 949
 950 /** 1111 00sd rdst 1bit                 bclr    #%1, %0%S0 */
 951   ID(bclr); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE); F_____;
 952
 953 /** 1111 1100 0110 01sd rdst rsrc       bclr    %1, %0%S0 */
 954   ID(bclr); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE); F_____;
 955   if (sd == 3) /* bset reg,reg */
 956     BWL(LSIZE);
 957
 958 /** 0111 101b ittt rdst                 bclr    #%1, %0 */
 959   ID(bclr); BWL(LSIZE); SC(b*16+ittt); DR(rdst); F_____;
 960
 961
 962 /** 1111 01sd rdst 0bit                 btst    #%2, %1%S1 */
 963   ID(btst); BWL(BSIZE); S2C(bit); SD(sd, rdst, BSIZE); F___ZC;
 964
 965 /** 1111 1100 0110 10sd rdst rsrc       btst    %2, %1%S1 */
 966   ID(btst); BWL(BSIZE); S2R(rsrc); SD(sd, rdst, BSIZE); F___ZC;
 967   if (sd == 3) /* bset reg,reg */
 968     BWL(LSIZE);
 969
 970 /** 0111 110b ittt rdst                 btst    #%2, %1 */
 971   ID(btst); BWL(LSIZE); S2C(b*16+ittt); SR(rdst); F___ZC;
 972
 973
 974 /** 1111 1100 111bit sd rdst 1111       bnot    #%1, %0%S0 */
 975   ID(bnot); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE);
 976
 977 /** 1111 1100 0110 11sd rdst rsrc       bnot    %1, %0%S0 */
 978   ID(bnot); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE);
 979   if (sd == 3) /* bset reg,reg */
 980     BWL(LSIZE);
 981
 982 /** 1111 1101 111bittt 1111 rdst        bnot    #%1, %0 */
 983   ID(bnot); BWL(LSIZE); SC(bittt); DR(rdst);
 984
 985
 986 /** 1111 1100 111bit sd rdst cond       bm%2    #%1, %0%S0 */
 987   ID(bmcc); BWL(BSIZE); S2cc(cond); SC(bit); DD(sd, rdst, BSIZE);
 988
 989 /** 1111 1101 111 bittt cond rdst       bm%2    #%1, %0%S0 */
 990   ID(bmcc); BWL(LSIZE); S2cc(cond); SC(bittt); DR(rdst);
 991
 992 /*----------------------------------------------------------------------*/
 993 /* CONTROL REGISTERS                                                    */
 994
 995 /** 0111 1111 1011 rdst                 clrpsw  %0 */
 996   ID(clrpsw); DF(rdst);
 997
 998 /** 0111 1111 1010 rdst                 setpsw  %0 */
 999   ID(setpsw); DF(rdst);
1000
1001 /** 0111 0101 0111 0000 0000 immm       mvtipl  #%1 */
1002   ID(mvtipl); SC(immm);
1003
1004 /** 0111 1110 111 crdst                 popc    %0 */
1005   ID(mov); OP(1, RX_Operand_Postinc, 0, 0); DR(crdst + 16);
1006
1007 /** 0111 1110 110 crsrc                 pushc   %1 */
1008   ID(mov); OP(0, RX_Operand_Predec, 0, 0); SR(crsrc + 16);
1009
1010 /** 1111 1101 0111 im11 000crdst        mvtc    #%1, %0 */
1011   ID(mov); SC(IMMex(im)); DR(crdst + 16);
1012
1013 /** 1111 1101 0110 100c rsrc rdst       mvtc    %1, %0 */
1014   ID(mov); SR(rsrc); DR(c*16+rdst + 16);
1015
1016 /** 1111 1101 0110 101s rsrc rdst       mvfc    %1, %0 */
1017   ID(mov); SR((s*16+rsrc) + 16); DR(rdst);
1018
1019 /*----------------------------------------------------------------------*/
1020 /* INTERRUPTS                                                           */
1021
1022 /** 0111 1111 1001 0100         rtfi */
1023   ID(rtfi);
1024
1025 /** 0111 1111 1001 0101         rte */
1026   ID(rte);
1027
1028 /** 0000 0000                   brk */
1029   ID(brk);
1030
1031 /** 0000 0001                   dbt */
1032   ID(dbt);
1033
1034 /** 0111 0101 0110 0000         int #%1 */
1035   ID(int); SC(IMM(1));
1036
1037 /** 0111 1111 1001 0110         wait */
1038   ID(wait);
1039
1040 /*----------------------------------------------------------------------*/
1041 /* SCcnd                                                                */
1042
1043 /** 1111 1100 1101 sz sd rdst cond      sc%1%s  %0 */
1044   ID(sccnd); BWL(sz); DD (sd, rdst, sz); Scc(cond);
1045
1046 /*----------------------------------------------------------------------*/
1047 /* RXv2 enhanced                                                                */
1048
1049 /** 1111 1101 0010 0111 rdst rsrc       movco   %1, [%0] */
1050    ID(movco); SR(rsrc); DR(rdst); F_____;
1051
1052 /** 1111 1101 0010 1111 rsrc rdst       movli   [%1], %0 */
1053    ID(movli); SR(rsrc); DR(rdst); F_____;
1054
1055 /** 1111 1100 0100 1011 rsrc rdst       stz     %1, %0 */
1056   ID(stcc); SR(rsrc); DR(rdst); S2cc(RXC_z);
1057
1058 /** 1111 1100 0100 1111 rsrc rdst       stnz    %1, %0 */
1059   ID(stcc); SR(rsrc); DR(rdst); S2cc(RXC_nz);
1060
1061 /** 1111 1101 0000 a111 srca srcb       emaca   %1, %2, %0 */
1062   ID(emaca); DR(a+32); SR(srca); S2R(srcb); F_____;
1063
1064 /** 1111 1101 0100 a111 srca srcb       emsba   %1, %2, %0 */
1065   ID(emsba); DR(a+32); SR(srca); S2R(srcb); F_____;
1066
1067 /** 1111 1101 0000 a011 srca srcb       emula   %1, %2, %0 */
1068   ID(emula); DR(a+32); SR(srca); S2R(srcb); F_____;
1069
1070 /** 1111 1101 0000 a110 srca srcb       maclh   %1, %2, %0 */
1071   ID(maclh); DR(a+32); SR(srca); S2R(srcb); F_____;
1072
1073 /** 1111 1101 0100 a100 srca srcb       msbhi   %1, %2, %0 */
1074   ID(msbhi); DR(a+32); SR(srca); S2R(srcb); F_____;
1075
1076 /** 1111 1101 0100 a110 srca srcb       msblh   %1, %2, %0 */
1077   ID(msblh); DR(a+32); SR(srca); S2R(srcb); F_____;
1078
1079 /** 1111 1101 0100 a101 srca srcb       msblo   %1, %2, %0 */
1080   ID(msblo); DR(a+32); SR(srca); S2R(srcb); F_____;
1081
1082 /** 1111 1101 0000 a010 srca srcb       mullh   %1, %2, %0 */
1083   ID(mullh); DR(a+32); SR(srca); S2R(srcb); F_____;
1084
1085 /** 1111 1101 0001 111i a m11 rdst      mvfacgu #%2, %1, %0 */
1086   ID(mvfacgu); S2C(((i^1)<<1)|m); SR(a+32); DR(rdst); F_____;
1087
1088 /** 1111 1101 0001 0111 a011 rdst       mvtacgu %0, %1 */
1089   ID(mvtacgu); DR(a+32); SR(rdst); F_____;
1090
1091 /** 1111 1101 0001 1001 a00i 0000       racl    #%1, %0 */
1092   ID(racl); SC(i+1); DR(a+32); F_____;
1093
1094 /** 1111 1101 0001 1001 a10i 0000       rdacl   #%1, %0 */
1095   ID(rdacl); SC(i+1); DR(a+32); F_____;
1096
1097 /** 1111 1101 0001 1000 a10i 0000       rdacw   #%1, %0 */
1098   ID(rdacw); SC(i+1); DR(a+32); F_____;
1099
1100 /** 1111 1111 1010 rdst srca srcb       fadd    %2, %1, %0 */
1101   ID(fadd); DR(rdst); SR(srcb); S2R(srca); F__SZ_;
1102
1103 /** 1111 1111 1000 rdst srca srcb       fsub    %2, %1, %0 */
1104   ID(fsub); DR(rdst); SR(srcb); S2R(srca); F__SZ_;
1105
1106 /** 1111 1111 1011 rdst srca srcb       fmul    %2, %1, %0 */
1107   ID(fmul); DR(rdst); SR(srcb); S2R(srca); F__SZ_;
1108
1109 /** 1111 1100 1010 00sd rsrc rdst       fsqrt   %1%S1, %0 */
1110   ID(fsqrt); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
1111
1112 /** 1111 1100 1010 01sd rsrc rdst       ftou    %1%S1, %0 */
1113   ID(ftou); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
1114
1115 /** 1111 1100 0101 01sd rsrc rdst       utof    %1%S1, %0 */
1116   ID(utof); DR (rdst); SP(sd, rsrc); F__SZ_;
1117
1118 /** 0000 0110 mx10 00sd 0001 0101 rsrc rdst     utof    %1%S1, %0 */
1119   ID(utof); DR (rdst); SPm(sd, rsrc, mx); F__SZ_;
1120
1121 /** */
1122
1123   return rx->n_bytes;
1124 }