opcodes/s390-opc.c

   1 /* s390-opc.c -- S390 opcode list
   2    Copyright 2000, 2001 Free Software Foundation, Inc.
   3    Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
   4
   5    This file is part of GDB, GAS, and the GNU binutils.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; if not, write to the Free Software
  19    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
  20    02111-1307, USA.  */
  21
  22 #include <stdio.h>
  23 #include "ansidecl.h"
  24 #include "opcode/s390.h"
  25
  26 /* This file holds the S390 opcode table.  The opcode table
  27    includes almost all of the extended instruction mnemonics.  This
  28    permits the disassembler to use them, and simplifies the assembler
  29    logic, at the cost of increasing the table size.  The table is
  30    strictly constant data, so the compiler should be able to put it in
  31    the .text section.
  32
  33    This file also holds the operand table.  All knowledge about
  34    inserting operands into instructions and vice-versa is kept in this
  35    file.  */
  36
  37 /* The operands table.
  38    The fields are bits, shift, insert, extract, flags.  */
  39
  40 const struct s390_operand s390_operands[] =
  41 {
  42 #define UNUSED 0
  43   { 0, 0, 0 },                    /* Indicates the end of the operand list */
  44
  45 #define R_8    1                  /* GPR starting at position 8 */
  46   { 4, 8, S390_OPERAND_GPR },
  47 #define R_12   2                  /* GPR starting at position 12 */
  48   { 4, 12, S390_OPERAND_GPR },
  49 #define R_16   3                  /* GPR starting at position 16 */
  50   { 4, 16, S390_OPERAND_GPR },
  51 #define R_20   4                  /* GPR starting at position 20 */
  52   { 4, 20, S390_OPERAND_GPR },
  53 #define R_24   5                  /* GPR starting at position 24 */
  54   { 4, 24, S390_OPERAND_GPR },
  55 #define R_28   6                  /* GPR starting at position 28 */
  56   { 4, 28, S390_OPERAND_GPR },
  57 #define R_32   7                  /* GPR starting at position 32 */
  58   { 4, 32, S390_OPERAND_GPR },
  59
  60 #define F_8    8                  /* FPR starting at position 8 */
  61   { 4, 8, S390_OPERAND_FPR },
  62 #define F_12   9                  /* FPR starting at position 12 */
  63   { 4, 12, S390_OPERAND_FPR },
  64 #define F_16   10                 /* FPR starting at position 16 */
  65   { 4, 16, S390_OPERAND_FPR },
  66 #define F_20   11                 /* FPR starting at position 16 */
  67   { 4, 16, S390_OPERAND_FPR },
  68 #define F_24   12                 /* FPR starting at position 24 */
  69   { 4, 24, S390_OPERAND_FPR },
  70 #define F_28   13                 /* FPR starting at position 28 */
  71   { 4, 28, S390_OPERAND_FPR },
  72 #define F_32   14                 /* FPR starting at position 32 */
  73   { 4, 32, S390_OPERAND_FPR },
  74
  75 #define A_8    15                 /* Access reg. starting at position 8 */
  76   { 4, 8, S390_OPERAND_AR },
  77 #define A_12   16                 /* Access reg. starting at position 12 */
  78   { 4, 12, S390_OPERAND_AR },
  79 #define A_24   17                 /* Access reg. starting at position 24 */
  80   { 4, 24, S390_OPERAND_AR },
  81 #define A_28   18                 /* Access reg. starting at position 28 */
  82   { 4, 28, S390_OPERAND_AR },
  83
  84 #define C_8    19                 /* Control reg. starting at position 8 */
  85   { 4, 8, S390_OPERAND_CR },
  86 #define C_12   20                 /* Control reg. starting at position 12 */
  87   { 4, 12, S390_OPERAND_CR },
  88
  89 #define B_16   21                 /* Base register starting at position 16 */
  90   { 4, 16, S390_OPERAND_BASE|S390_OPERAND_GPR },
  91 #define B_32   22                 /* Base register starting at position 32 */
  92   { 4, 32, S390_OPERAND_BASE|S390_OPERAND_GPR },
  93
  94 #define X_12   23                 /* Index register starting at position 12 */
  95   { 4, 12, S390_OPERAND_INDEX|S390_OPERAND_GPR },
  96
  97 #define D_20   24                 /* Displacement starting at position 20 */
  98   { 12, 20, S390_OPERAND_DISP },
  99 #define D_36   25                 /* Displacement starting at position 36 */
 100   { 12, 36, S390_OPERAND_DISP },
 101 #define D20_20 26                 /* 20 bit displacement starting at 20 */
 102   { 20, 20, S390_OPERAND_DISP|S390_OPERAND_SIGNED },
 103
 104 #define L4_8   27                 /* 4 bit length starting at position 8 */
 105   { 4, 8, S390_OPERAND_LENGTH },
 106 #define L4_12  28                 /* 4 bit length starting at position 12 */
 107   { 4, 12, S390_OPERAND_LENGTH },
 108 #define L8_8   29                 /* 8 bit length starting at position 8 */
 109   { 8, 8, S390_OPERAND_LENGTH },
 110
 111 #define U4_8   30                 /* 4 bit unsigned value starting at 8 */
 112   { 4, 8, 0 },
 113 #define U4_12  31                 /* 4 bit unsigned value starting at 12 */
 114   { 4, 12, 0 },
 115 #define U4_16  32                 /* 4 bit unsigned value starting at 16 */
 116   { 4, 16, 0 },
 117 #define U4_20  33                 /* 4 bit unsigned value starting at 20 */
 118   { 4, 20, 0 },
 119 #define U8_8   34                 /* 8 bit unsigned value starting at 8 */
 120   { 8, 8, 0 },
 121 #define U8_16  35                 /* 8 bit unsigned value starting at 16 */
 122   { 8, 16, 0 },
 123 #define I16_16 36                 /* 16 bit signed value starting at 16 */
 124   { 16, 16, S390_OPERAND_SIGNED },
 125 #define U16_16 37                 /* 16 bit unsigned value starting at 16 */
 126   { 16, 16, 0 },
 127 #define J16_16 38                 /* PC relative jump offset at 16 */
 128   { 16, 16, S390_OPERAND_PCREL },
 129 #define J32_16 39                 /* PC relative long offset at 16 */
 130   { 32, 16, S390_OPERAND_PCREL }
 131 };
 132
 133
 134 /* Macros used to form opcodes.  */
 135
 136 /* 8/16/48 bit opcodes.  */
 137 #define OP8(x) { x, 0x00, 0x00, 0x00, 0x00, 0x00 }
 138 #define OP16(x) { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 }
 139 #define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \
 140                   (x >> 16) & 255, (x >> 8) & 255, x & 255}
 141
 142 /* The new format of the INSTR_x_y and MASK_x_y defines is based
 143    on the following rules:
 144    1) the middle part of the definition (x in INSTR_x_y) is the official
 145       names of the instruction format that you can find in the principals
 146       of operation.
 147    2) the last part of the definition (y in INSTR_x_y) gives you an idea
 148       which operands the binary represenation of the instruction has.
 149       The meanings of the letters in y are:
 150       a - access register
 151       c - control register
 152       d - displacement, 12 bit
 153       f - floating pointer register
 154       i - signed integer, 4 or 8 bit
 155       l - length, 4 or 8 bit
 156       p - pc relative
 157       r - general purpose register
 158       u - unsigned integer, 4 or 8 bit
 159       0 - operand skipped.
 160       The order of the letters reflects the layout of the format in
 161       storage and not the order of the paramaters of the instructions.
 162       The use of the letters is not a 100% match with the PoP but it is
 163       quite close.
 164
 165       For example the instruction "mvo" is defined in the PoP as follows:
 166
 167       MVO  D1(L1,B1),D2(L2,B2)   [SS]
 168
 169       --------------------------------------
 170       | 'F1' | L1 | L2 | B1 | D1 | B2 | D2 |
 171       --------------------------------------
 172        0      8    12   16   20   32   36
 173
 174       The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD.  */
 175
 176 #define INSTR_E          2, { 0,0,0,0,0,0 }                    /* e.g. pr    */
 177 #define INSTR_RIE_RRP    6, { R_8,R_12,J16_16,0,0,0 }          /* e.g. brxhg */
 178 #define INSTR_RIL_0P     6, { J32_16,0,0,0,0 }                 /* e.g. jg    */
 179 #define INSTR_RIL_RP     6, { R_8,J32_16,0,0,0,0 }             /* e.g. brasl */
 180 #define INSTR_RIL_UP     6, { U4_8,J32_16,0,0,0,0 }            /* e.g. brcl  */
 181 #define INSTR_RI_0P      4, { J16_16,0,0,0,0,0 }               /* e.g. j     */
 182 #define INSTR_RI_RI      4, { R_8,I16_16,0,0,0,0 }             /* e.g. ahi   */
 183 #define INSTR_RI_RP      4, { R_8,J16_16,0,0,0,0 }             /* e.g. brct  */
 184 #define INSTR_RI_RU      4, { R_8,U16_16,0,0,0,0 }             /* e.g. tml   */
 185 #define INSTR_RI_UP      4, { U4_8,J16_16,0,0,0,0 }            /* e.g. brc   */
 186 #define INSTR_RRE_00     4, { 0,0,0,0,0,0 }                    /* e.g. palb  */
 187 #define INSTR_RRE_0R     4, { R_28,0,0,0,0,0 }                 /* e.g. tb    */
 188 #define INSTR_RRE_AA     4, { A_24,A_28,0,0,0,0 }              /* e.g. cpya  */
 189 #define INSTR_RRE_AR     4, { A_24,R_28,0,0,0,0 }              /* e.g. sar   */
 190 #define INSTR_RRE_F0     4, { F_24,0,0,0,0,0 }                 /* e.g. sqer  */
 191 #define INSTR_RRE_FF     4, { F_24,F_28,0,0,0,0 }              /* e.g. debr  */
 192 #define INSTR_RRE_R0     4, { R_24,0,0,0,0,0 }                 /* e.g. ipm   */
 193 #define INSTR_RRE_RA     4, { R_24,A_28,0,0,0,0 }              /* e.g. ear   */
 194 #define INSTR_RRE_RF     4, { R_24,F_28,0,0,0,0 }              /* e.g. cefbr */
 195 #define INSTR_RRE_RR     4, { R_24,R_28,0,0,0,0 }              /* e.g. lura  */
 196 #define INSTR_RRF_F0FF   4, { F_16,F_24,F_28,0,0,0 }           /* e.g. madbr */
 197 #define INSTR_RRF_FUFF   4, { F_24,F_16,F_28,U4_20,0,0 }       /* e.g. didbr */
 198 #define INSTR_RRF_RURR   4, { R_24,R_28,R_16,U4_20,0,0 }       /* e.g. .insn */
 199 #define INSTR_RRF_R0RR   4, { R_24,R_28,R_16,0,0,0 }           /* e.g. idte  */
 200 #define INSTR_RRF_U0FF   4, { F_24,U4_16,F_28,0,0,0 }          /* e.g. cfxbr */
 201 #define INSTR_RRF_U0FR   4, { F_24,U4_16,R_28,0,0,0 }          /* e.g. cfebr */
 202 #define INSTR_RRF_U0FR   4, { F_24,U4_16,R_28,0,0,0 }          /* e.g. cfxbr */
 203 #define INSTR_RR_0R      2, { R_12, 0,0,0,0,0 }                /* e.g. br    */
 204 #define INSTR_RR_FF      2, { F_8,F_12,0,0,0,0 }               /* e.g. adr   */
 205 #define INSTR_RR_R0      2, { R_8, 0,0,0,0,0 }                 /* e.g. spm   */
 206 #define INSTR_RR_RR      2, { R_8,R_12,0,0,0,0 }               /* e.g. lr    */
 207 #define INSTR_RR_U0      2, { U8_8, 0,0,0,0,0 }                /* e.g. svc   */
 208 #define INSTR_RR_UR      2, { U4_8,R_12,0,0,0,0 }              /* e.g. bcr   */
 209 #define INSTR_RSE_RRRD   6, { R_8,R_12,D_20,B_16,0,0 }         /* e.g. lmh   */
 210 #define INSTR_RSE_RURD   6, { R_8,U4_12,D_20,B_16,0,0 }        /* e.g. icmh  */
 211 #define INSTR_RSL_R0RD   6, { R_8,D_20,B_16,0,0,0 }            /* e.g. tp    */
 212 #define INSTR_RSI_RRP    4, { R_8,R_12,J16_16,0,0,0 }          /* e.g. brxh  */
 213 #define INSTR_RSY_RRRD   6, { R_8,R_12,D20_20,B_16,0,0 }       /* e.g. stmy  */
 214 #define INSTR_RSY_RURD   6, { R_8,U4_12,D20_20,B_16,0,0 }      /* e.g. icmh  */
 215 #define INSTR_RSY_AARD   6, { A_8,A_12,D20_20,B_16,0,0 }       /* e.g. lamy  */
 216 #define INSTR_RS_AARD    4, { A_8,A_12,D_20,B_16,0,0 }         /* e.g. lam   */
 217 #define INSTR_RS_CCRD    4, { C_8,C_12,D_20,B_16,0,0 }         /* e.g. lctl  */
 218 #define INSTR_RS_R0RD    4, { R_8,D_20,B_16,0,0,0 }            /* e.g. sll   */
 219 #define INSTR_RS_RRRD    4, { R_8,R_12,D_20,B_16,0,0 }         /* e.g. cs    */
 220 #define INSTR_RS_RURD    4, { R_8,U4_12,D_20,B_16,0,0 }        /* e.g. icm   */
 221 #define INSTR_RXE_FRRD   6, { F_8,D_20,X_12,B_16,0,0 }         /* e.g. axbr  */
 222 #define INSTR_RXE_RRRD   6, { R_8,D_20,X_12,B_16,0,0 }         /* e.g. lg    */
 223 #define INSTR_RXF_FRRDF  6, { F_32,F_8,D_20,X_12,B_16,0 }      /* e.g. madb  */
 224 #define INSTR_RXF_RRRDR  6, { R_32,R_8,D_20,X_12,B_16,0 }      /* e.g. .insn */
 225 #define INSTR_RXY_RRRD   6, { R_8,D20_20,X_12,B_16,0,0 }       /* e.g. ly    */
 226 #define INSTR_RXY_FRRD   6, { F_8,D20_20,X_12,B_16,0,0 }       /* e.g. ley   */
 227 #define INSTR_RX_0RRD    4, { D_20,X_12,B_16,0,0,0 }           /* e.g. be    */
 228 #define INSTR_RX_FRRD    4, { F_8,D_20,X_12,B_16,0,0 }         /* e.g. ae    */
 229 #define INSTR_RX_RRRD    4, { R_8,D_20,X_12,B_16,0,0 }         /* e.g. l     */
 230 #define INSTR_RX_URRD    4, { U4_8,D_20,X_12,B_16,0,0 }        /* e.g. bc    */
 231 #define INSTR_SI_URD     4, { D_20,B_16,U8_8,0,0,0 }           /* e.g. cli   */
 232 #define INSTR_SIY_URD    6, { D20_20,B_16,U8_8,0,0,0 }         /* e.g. tmy   */
 233 #define INSTR_SSE_RDRD   6, { D_20,B_16,D_36,B_32,0,0 }        /* e.g. mvsdk */
 234 #define INSTR_SS_L0RDRD  6, { D_20,L8_8,B_16,D_36,B_32,0     } /* e.g. mvc   */
 235 #define INSTR_SS_LIRDRD  6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp   */
 236 #define INSTR_SS_LLRDRD  6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack  */
 237 #define INSTR_SS_RRRDRD  6, { D_20,R_8,B_16,D_36,B_32,R_12 }   /* e.g. mvck  */
 238 #define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 }   /* e.g. plo   */
 239 #define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 }   /* e.g. lmd   */
 240 #define INSTR_S_00       4, { 0,0,0,0,0,0 }                    /* e.g. hsch  */
 241 #define INSTR_S_RD       4, { D_20,B_16,0,0,0,0 }              /* e.g. lpsw  */
 242
 243 #define MASK_E           { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 244 #define MASK_RIE_RRP     { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 245 #define MASK_RIL_0P      { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 246 #define MASK_RIL_RP      { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
 247 #define MASK_RIL_UP      { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
 248 #define MASK_RI_0P       { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 249 #define MASK_RI_RI       { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
 250 #define MASK_RI_RP       { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
 251 #define MASK_RI_RU       { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
 252 #define MASK_RI_UP       { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
 253 #define MASK_RRE_00      { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
 254 #define MASK_RRE_0R      { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 }
 255 #define MASK_RRE_AA      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
 256 #define MASK_RRE_AR      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
 257 #define MASK_RRE_F0      { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
 258 #define MASK_RRE_FF      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
 259 #define MASK_RRE_R0      { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
 260 #define MASK_RRE_RA      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
 261 #define MASK_RRE_RF      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
 262 #define MASK_RRE_RR      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
 263 #define MASK_RRF_F0FF    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 264 #define MASK_RRF_FUFF    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 265 #define MASK_RRF_RURR    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 266 #define MASK_RRF_R0RR    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 267 #define MASK_RRF_U0FF    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 268 #define MASK_RRF_U0FR    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 269 #define MASK_RRF_U0FR    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 270 #define MASK_RR_0R       { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
 271 #define MASK_RR_FF       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 272 #define MASK_RR_R0       { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
 273 #define MASK_RR_RR       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 274 #define MASK_RR_U0       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 275 #define MASK_RR_UR       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 276 #define MASK_RSE_RRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 277 #define MASK_RSE_RURD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 278 #define MASK_RSL_R0RD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 279 #define MASK_RSI_RRP     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 280 #define MASK_RS_AARD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 281 #define MASK_RS_CCRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 282 #define MASK_RS_R0RD     { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
 283 #define MASK_RS_RRRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 284 #define MASK_RS_RURD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 285 #define MASK_RSY_RRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 286 #define MASK_RSY_RURD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 287 #define MASK_RSY_AARD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 288 #define MASK_RXE_FRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 289 #define MASK_RXE_RRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 290 #define MASK_RXF_FRRDF   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 291 #define MASK_RXF_RRRDR   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 292 #define MASK_RXY_RRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 293 #define MASK_RXY_FRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 294 #define MASK_RX_0RRD     { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
 295 #define MASK_RX_FRRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 296 #define MASK_RX_RRRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 297 #define MASK_RX_URRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 298 #define MASK_SI_URD      { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 299 #define MASK_SIY_URD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 300 #define MASK_SSE_RDRD    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 301 #define MASK_SS_L0RDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 302 #define MASK_SS_LIRDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 303 #define MASK_SS_LLRDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 304 #define MASK_SS_RRRDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 305 #define MASK_SS_RRRDRD2  { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 306 #define MASK_SS_RRRDRD3  { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 307 #define MASK_S_00        { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
 308 #define MASK_S_RD        { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 309
 310 /* The opcode formats table (blueprints for .insn pseudo mnemonic).  */
 311
 312 const struct s390_opcode s390_opformats[] =
 313   {
 314   { "e",        OP8(0x00LL),    MASK_E,         INSTR_E,        3, 0 },
 315   { "ri",       OP8(0x00LL),    MASK_RI_RI,     INSTR_RI_RI,    3, 0 },
 316   { "rie",      OP8(0x00LL),    MASK_RIE_RRP,   INSTR_RIE_RRP,  3, 0 },
 317   { "ril",      OP8(0x00LL),    MASK_RIL_RP,    INSTR_RIL_RP,   3, 0 },
 318   { "rr",       OP8(0x00LL),    MASK_RR_RR,     INSTR_RR_RR,    3, 0 },
 319   { "rre",      OP8(0x00LL),    MASK_RRE_RR,    INSTR_RRE_RR,   3, 0 },
 320   { "rrf",      OP8(0x00LL),    MASK_RRF_RURR,  INSTR_RRF_RURR, 3, 0 },
 321   { "rs",       OP8(0x00LL),    MASK_RS_RRRD,   INSTR_RS_RRRD,  3, 0 },
 322   { "rse",      OP8(0x00LL),    MASK_RSE_RRRD,  INSTR_RSE_RRRD, 3, 0 },
 323   { "rsi",      OP8(0x00LL),    MASK_RSI_RRP,   INSTR_RSI_RRP,  3, 0 },
 324   { "rsy",      OP8(0x00LL),    MASK_RSY_RRRD,  INSTR_RSY_RRRD, 3, 3 },
 325   { "rx",       OP8(0x00LL),    MASK_RX_RRRD,   INSTR_RX_RRRD,  3, 0 },
 326   { "rxe",      OP8(0x00LL),    MASK_RXE_RRRD,  INSTR_RXE_RRRD, 3, 0 },
 327   { "rxf",      OP8(0x00LL),    MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3, 0 },
 328   { "rxy",      OP8(0x00LL),    MASK_RXY_RRRD,  INSTR_RXY_RRRD, 3, 3 },
 329   { "s",        OP8(0x00LL),    MASK_S_RD,      INSTR_S_RD,     3, 0 },
 330   { "si",       OP8(0x00LL),    MASK_SI_URD,    INSTR_SI_URD,   3, 0 },
 331   { "siy",      OP8(0x00LL),    MASK_SIY_URD,   INSTR_SIY_URD,  3, 3 },
 332   { "ss",       OP8(0x00LL),    MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 },
 333   { "sse",      OP8(0x00LL),    MASK_SSE_RDRD,  INSTR_SSE_RDRD, 3, 0 },
 334 };
 335
 336 const int s390_num_opformats =
 337   sizeof (s390_opformats) / sizeof (s390_opformats[0]);
 338
 339 #include "s390-opc.tab"