1 /* Print SPARC instructions.
2 Copyright 1989, 1991, 1992, 1993, 1995 Free Software Foundation, Inc.
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
19 #include "opcode/sparc.h"
21 #include "libiberty.h"
24 /* For faster lookup, after insns are sorted they are hashed. */
25 /* ??? I think there is room for even more improvement. */
28 /* It is important that we only look at insn code bits as that is how the
29 opcode table is hashed. OPCODE_BITS is a table of valid bits for each
30 of the main types (0,1,2,3). */
31 static int opcode_bits
[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
32 #define HASH_INSN(INSN) \
33 ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
35 struct opcode_hash
*next
;
36 struct sparc_opcode
*opcode
;
38 static struct opcode_hash
*opcode_hash_table
[HASH_SIZE
];
39 static void build_hash_table ();
41 /* Sign-extend a value which is N bits long. */
42 #define SEX(value, bits) \
43 ((((int)(value)) << ((8 * sizeof (int)) - bits)) \
44 >> ((8 * sizeof (int)) - bits) )
46 static char *reg_names
[] =
47 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
48 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
49 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
50 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
51 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
52 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
53 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
54 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
56 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
57 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
58 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
59 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
60 /* psr, wim, tbr, fpsr, cpsr are v8 only. */
62 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
65 #define freg_names (®_names[4 * 8])
68 /* These are ordered according to there register number in
69 rdpr and wrpr insns. */
70 static char *v9_priv_reg_names
[] =
72 "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
73 "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
75 /* "ver" - special cased */
79 /* Macros used to extract instruction fields. Not all fields have
80 macros defined here, only those which are actually used. */
82 #define X_RD(i) (((i) >> 25) & 0x1f)
83 #define X_RS1(i) (((i) >> 14) & 0x1f)
84 #define X_LDST_I(i) (((i) >> 13) & 1)
85 #define X_ASI(i) (((i) >> 5) & 0xff)
86 #define X_RS2(i) (((i) >> 0) & 0x1f)
87 #define X_IMM13(i) (((i) >> 0) & 0x1fff)
88 #define X_DISP22(i) (((i) >> 0) & 0x3fffff)
89 #define X_IMM22(i) X_DISP22 (i)
90 #define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
93 #define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
96 /* Here is the union which was used to extract instruction fields
97 before the shift and mask macros were written.
101 unsigned long int code;
109 unsigned int anrs1:5;
110 #define rs1 ldst.anrs1
112 unsigned int anasi:8;
113 #define asi ldst.anasi
114 unsigned int anrs2:5;
115 #define rs2 ldst.anrs2
120 unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
121 unsigned int IMM13:13;
122 #define imm13 IMM13.IMM13
130 unsigned int DISP22:22;
131 #define disp22 branch.DISP22
140 unsigned int rcond:3;
142 unsigned int DISP16HI:2;
145 unsigned int DISP16LO:14;
151 unsigned int adisp30:30;
152 #define disp30 call.adisp30
158 /* Nonzero if INSN is the opcode for a delayed branch. */
160 is_delayed_branch (insn
)
163 struct opcode_hash
*op
;
165 for (op
= opcode_hash_table
[HASH_INSN (insn
)]; op
; op
= op
->next
)
167 CONST
struct sparc_opcode
*opcode
= op
->opcode
;
168 if ((opcode
->match
& insn
) == opcode
->match
169 && (opcode
->lose
& insn
) == 0)
170 return (opcode
->flags
& F_DELAYED
);
175 /* Nonzero of opcode table has been initialized. */
176 static int opcodes_initialized
= 0;
178 /* Nonzero of the current architecture is sparc64.
179 This is kept in a global because compare_opcodes uses it. */
180 static int sparc64_p
;
182 /* extern void qsort (); */
183 static int compare_opcodes ();
185 /* Print one instruction from MEMADDR on INFO->STREAM.
187 We suffix the instruction with a comment that gives the absolute
188 address involved, as well as its symbolic form, if the instruction
189 is preceded by a findable `sethi' and it either adds an immediate
190 displacement to that register, or it is an `add' or `or' instruction
194 print_insn (memaddr
, info
)
196 disassemble_info
*info
;
198 FILE *stream
= info
->stream
;
201 register unsigned int i
;
202 register struct opcode_hash
*op
;
204 if (!opcodes_initialized
)
206 qsort ((char *) sparc_opcodes
, NUMOPCODES
,
207 sizeof (sparc_opcodes
[0]), compare_opcodes
);
208 build_hash_table (sparc_opcodes
, opcode_hash_table
, NUMOPCODES
);
209 opcodes_initialized
= 1;
214 (*info
->read_memory_func
) (memaddr
, buffer
, sizeof (buffer
), info
);
217 (*info
->memory_error_func
) (status
, memaddr
, info
);
222 insn
= bfd_getb32 (buffer
);
224 info
->insn_info_valid
= 1; /* We do return this info */
225 info
->insn_type
= dis_nonbranch
; /* Assume non branch insn */
226 info
->branch_delay_insns
= 0; /* Assume no delay */
227 info
->target
= 0; /* Assume no target known */
229 for (op
= opcode_hash_table
[HASH_INSN (insn
)]; op
; op
= op
->next
)
231 CONST
struct sparc_opcode
*opcode
= op
->opcode
;
233 if ((opcode
->match
& insn
) == opcode
->match
234 && (opcode
->lose
& insn
) == 0)
236 /* Nonzero means that we have found an instruction which has
237 the effect of adding or or'ing the imm13 field to rs1. */
238 int imm_added_to_rs1
= 0;
240 /* Nonzero means that we have found a plus sign in the args
241 field of the opcode table. */
244 /* Nonzero means we have an annulled branch. */
247 /* Do we have an `add' or `or' instruction where rs1 is the same
248 as rsd, and which has the i bit set? */
249 if ((opcode
->match
== 0x80102000 || opcode
->match
== 0x80002000)
251 && X_RS1 (insn
) == X_RD (insn
))
252 imm_added_to_rs1
= 1;
254 if (X_RS1 (insn
) != X_RD (insn
)
255 && strchr (opcode
->args
, 'r') != 0)
256 /* Can't do simple format if source and dest are different. */
259 (*info
->fprintf_func
) (stream
, opcode
->name
);
262 register CONST
char *s
;
264 if (opcode
->args
[0] != ',')
265 (*info
->fprintf_func
) (stream
, " ");
266 for (s
= opcode
->args
; *s
!= '\0'; ++s
)
270 (*info
->fprintf_func
) (stream
, ",");
274 (*info
->fprintf_func
) (stream
, "a");
280 (*info
->fprintf_func
) (stream
, "pn");
285 (*info
->fprintf_func
) (stream
, "pt");
292 } /* switch on arg */
293 } /* while there are comma started args */
295 (*info
->fprintf_func
) (stream
, " ");
302 /* note fall-through */
304 (*info
->fprintf_func
) (stream
, "%c", *s
);
308 (*info
->fprintf_func
) (stream
, "0");
311 #define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n])
326 #define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n])
327 #define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)])
331 case 'v': /* double/even */
332 case 'V': /* quad/multiple of 4 */
333 fregx (X_RS1 (insn
));
339 case 'B': /* double/even */
340 case 'R': /* quad/multiple of 4 */
341 fregx (X_RS2 (insn
));
347 case 'H': /* double/even */
348 case 'J': /* quad/multiple of 4 */
354 #define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n))
369 (*info
->fprintf_func
) (stream
, "%%hi(%#x)",
371 & ((int) X_IMM22 (insn
) << 10)));
376 int imm
= SEX (X_IMM13 (insn
), 13);
378 /* Check to see whether we have a 1+i, and take
381 Note: because of the way we sort the table,
382 we will be matching 1+i rather than i+1,
383 so it is OK to assume that i is after +,
386 imm_added_to_rs1
= 1;
389 (*info
->fprintf_func
) (stream
, "%d", imm
);
391 (*info
->fprintf_func
) (stream
, "%#x", imm
);
396 case 'I': /* 11 bit immediate. */
397 case 'j': /* 10 bit immediate. */
402 imm
= SEX (X_IMM13 (insn
), 11);
404 imm
= SEX (X_IMM13 (insn
), 10);
406 /* Check to see whether we have a 1+i, and take
409 Note: because of the way we sort the table,
410 we will be matching 1+i rather than i+1,
411 so it is OK to assume that i is after +,
414 imm_added_to_rs1
= 1;
417 (info
->fprintf_func
) (stream
, "%d", imm
);
419 (info
->fprintf_func
) (stream
, "%#x", (unsigned) imm
);
424 info
->target
= memaddr
+ (SEX (X_DISP16 (insn
), 16)) * 4;
425 (*info
->print_address_func
) (info
->target
, info
);
429 info
->target
= memaddr
+ (SEX (X_DISP22 (insn
), 19)) * 4;
430 (*info
->print_address_func
) (info
->target
, info
);
437 (*info
->fprintf_func
) (stream
, "%%fcc%c", *s
- '6' + '0');
441 (*info
->fprintf_func
) (stream
, "%%icc");
445 (*info
->fprintf_func
) (stream
, "%%xcc");
449 (*info
->fprintf_func
) (stream
, "%%ccr");
453 (*info
->fprintf_func
) (stream
, "%%fprs");
457 (*info
->fprintf_func
) (stream
, "%%asi");
461 (*info
->fprintf_func
) (stream
, "%%tick");
465 (*info
->fprintf_func
) (stream
, "%%pc");
469 if (X_RS1 (insn
) == 31)
470 (*info
->fprintf_func
) (stream
, "%%ver");
471 else if ((unsigned) X_RS1 (insn
) < 16)
472 (*info
->fprintf_func
) (stream
, "%%%s",
473 v9_priv_reg_names
[X_RS1 (insn
)]);
475 (*info
->fprintf_func
) (stream
, "%%reserved");
479 if ((unsigned) X_RD (insn
) < 15)
480 (*info
->fprintf_func
) (stream
, "%%%s",
481 v9_priv_reg_names
[X_RD (insn
)]);
483 (*info
->fprintf_func
) (stream
, "%%reserved");
489 (*info
->fprintf_func
) (stream
, "%%asr%d", X_RS1 (insn
));
493 (*info
->fprintf_func
) (stream
, "%%asr%d", X_RD (insn
));
497 info
->target
= memaddr
+ X_DISP30 (insn
) * 4;
498 (*info
->print_address_func
) (info
->target
, info
);
502 (*info
->fprintf_func
)
503 (stream
, "%#x", (SEX (X_DISP22 (insn
), 22)));
507 info
->target
= memaddr
+ (SEX (X_DISP22 (insn
), 22)) * 4;
508 (*info
->print_address_func
) (info
->target
, info
);
512 (*info
->fprintf_func
) (stream
, "(%d)", X_ASI (insn
));
516 (*info
->fprintf_func
) (stream
, "%%csr");
520 (*info
->fprintf_func
) (stream
, "%%fsr");
524 (*info
->fprintf_func
) (stream
, "%%psr");
528 (*info
->fprintf_func
) (stream
, "%%fq");
532 (*info
->fprintf_func
) (stream
, "%%cq");
536 (*info
->fprintf_func
) (stream
, "%%tbr");
540 (*info
->fprintf_func
) (stream
, "%%wim");
544 (*info
->fprintf_func
) (stream
, "%d",
545 ((X_LDST_I (insn
) << 8)
550 (*info
->fprintf_func
) (stream
, "%%y");
556 /* If we are adding or or'ing something to rs1, then
557 check to see whether the previous instruction was
558 a sethi to the same register as in the sethi.
559 If so, attempt to print the result of the add or
560 or (in this context add and or do the same thing)
561 and its symbolic value. */
562 if (imm_added_to_rs1
)
564 unsigned long prev_insn
;
568 (*info
->read_memory_func
)
569 (memaddr
- 4, buffer
, sizeof (buffer
), info
);
570 prev_insn
= bfd_getb32 (buffer
);
574 /* If it is a delayed branch, we need to look at the
575 instruction before the delayed branch. This handles
578 sethi %o1, %hi(_foo), %o1
580 or %o1, %lo(_foo), %o1
583 if (is_delayed_branch (prev_insn
))
585 errcode
= (*info
->read_memory_func
)
586 (memaddr
- 8, buffer
, sizeof (buffer
), info
);
587 prev_insn
= bfd_getb32 (buffer
);
591 /* If there was a problem reading memory, then assume
592 the previous instruction was not sethi. */
595 /* Is it sethi to the same register? */
596 if ((prev_insn
& 0xc1c00000) == 0x01000000
597 && X_RD (prev_insn
) == X_RS1 (insn
))
599 (*info
->fprintf_func
) (stream
, "\t! ");
601 (0xFFFFFFFF & (int) X_IMM22 (prev_insn
) << 10)
602 | SEX (X_IMM13 (insn
), 13);
603 (*info
->print_address_func
) (info
->target
, info
);
604 info
->insn_type
= dis_dref
;
605 info
->data_size
= 4; /* FIXME!!! */
610 if (opcode
->flags
& (F_UNBR
|F_CONDBR
|F_JSR
))
612 /* FIXME -- check is_annulled flag */
613 if (opcode
->flags
& F_UNBR
)
614 info
->insn_type
= dis_branch
;
615 if (opcode
->flags
& F_CONDBR
)
616 info
->insn_type
= dis_condbranch
;
617 if (opcode
->flags
& F_JSR
)
618 info
->insn_type
= dis_jsr
;
619 if (opcode
->flags
& F_DELAYED
)
620 info
->branch_delay_insns
= 1;
623 return sizeof (buffer
);
627 info
->insn_type
= dis_noninsn
; /* Mark as non-valid instruction */
628 (*info
->fprintf_func
) (stream
, "%#8x", insn
);
629 return sizeof (buffer
);
632 /* Compare opcodes A and B. */
635 compare_opcodes (a
, b
)
638 struct sparc_opcode
*op0
= (struct sparc_opcode
*) a
;
639 struct sparc_opcode
*op1
= (struct sparc_opcode
*) b
;
640 unsigned long int match0
= op0
->match
, match1
= op1
->match
;
641 unsigned long int lose0
= op0
->lose
, lose1
= op1
->lose
;
642 register unsigned int i
;
644 /* If a bit is set in both match and lose, there is something
645 wrong with the opcode table. */
648 fprintf (stderr
, "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n",
649 op0
->name
, match0
, lose0
);
650 op0
->lose
&= ~op0
->match
;
656 fprintf (stderr
, "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n",
657 op1
->name
, match1
, lose1
);
658 op1
->lose
&= ~op1
->match
;
662 /* If the current architecture isn't sparc64, move v9 insns to the end.
663 Only do this when one isn't v9 and one is. If both are v9 we still
664 need to properly sort them.
665 This must be done before checking match and lose. */
667 && (op0
->architecture
== v9
) != (op1
->architecture
== v9
))
668 return (op0
->architecture
== v9
) - (op1
->architecture
== v9
);
670 /* If the current architecture is sparc64, move non-v9 insns to the end.
671 This must be done before checking match and lose. */
673 && (op0
->flags
& F_NOTV9
) != (op1
->flags
& F_NOTV9
))
674 return (op0
->flags
& F_NOTV9
) - (op1
->flags
& F_NOTV9
);
676 /* Because the bits that are variable in one opcode are constant in
677 another, it is important to order the opcodes in the right order. */
678 for (i
= 0; i
< 32; ++i
)
680 unsigned long int x
= 1 << i
;
681 int x0
= (match0
& x
) != 0;
682 int x1
= (match1
& x
) != 0;
688 for (i
= 0; i
< 32; ++i
)
690 unsigned long int x
= 1 << i
;
691 int x0
= (lose0
& x
) != 0;
692 int x1
= (lose1
& x
) != 0;
698 /* They are functionally equal. So as long as the opcode table is
699 valid, we can put whichever one first we want, on aesthetic grounds. */
701 /* Our first aesthetic ground is that aliases defer to real insns. */
703 int alias_diff
= (op0
->flags
& F_ALIAS
) - (op1
->flags
& F_ALIAS
);
705 /* Put the one that isn't an alias first. */
709 /* Except for aliases, two "identical" instructions had
710 better have the same opcode. This is a sanity check on the table. */
711 i
= strcmp (op0
->name
, op1
->name
);
713 if (op0
->flags
& F_ALIAS
) /* If they're both aliases, be arbitrary. */
717 "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n",
718 op0
->name
, op1
->name
);
720 /* Fewer arguments are preferred. */
722 int length_diff
= strlen (op0
->args
) - strlen (op1
->args
);
723 if (length_diff
!= 0)
724 /* Put the one with fewer arguments first. */
728 /* Put 1+i before i+1. */
730 char *p0
= (char *) strchr(op0
->args
, '+');
731 char *p1
= (char *) strchr(op1
->args
, '+');
735 /* There is a plus in both operands. Note that a plus
736 sign cannot be the first character in args,
737 so the following [-1]'s are valid. */
738 if (p0
[-1] == 'i' && p1
[1] == 'i')
739 /* op0 is i+1 and op1 is 1+i, so op1 goes first. */
741 if (p0
[1] == 'i' && p1
[-1] == 'i')
742 /* op0 is 1+i and op1 is i+1, so op0 goes first. */
747 /* They are, as far as we can tell, identical.
748 Since qsort may have rearranged the table partially, there is
749 no way to tell which one was first in the opcode table as
750 written, so just say there are equal. */
754 /* Build a hash table from the opcode table. */
757 build_hash_table (table
, hash_table
, num_opcodes
)
758 struct sparc_opcode
*table
;
759 struct opcode_hash
**hash_table
;
763 int hash_count
[HASH_SIZE
];
764 struct opcode_hash
*hash_buf
;
766 /* Start at the end of the table and work backwards so that each
768 /* ??? Do we really need to sort them now? */
770 memset (hash_table
, 0, HASH_SIZE
* sizeof (hash_table
[0]));
771 memset (hash_count
, 0, HASH_SIZE
* sizeof (hash_count
[0]));
772 hash_buf
= (struct opcode_hash
*) xmalloc (sizeof (struct opcode_hash
) * num_opcodes
);
773 for (i
= num_opcodes
- 1; i
>= 0; --i
)
775 register int hash
= HASH_INSN (sparc_opcodes
[i
].match
);
776 register struct opcode_hash
*h
= &hash_buf
[i
];
777 h
->next
= hash_table
[hash
];
778 h
->opcode
= &sparc_opcodes
[i
];
779 hash_table
[hash
] = h
;
783 #if 0 /* for debugging */
785 int min_count
= num_opcodes
, max_count
= 0;
788 for (i
= 0; i
< HASH_SIZE
; ++i
)
790 if (hash_count
[i
] < min_count
)
791 min_count
= hash_count
[i
];
792 if (hash_count
[i
] > max_count
)
793 max_count
= hash_count
[i
];
794 total
+= hash_count
[i
];
797 printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
798 min_count
, max_count
, (double) total
/ HASH_SIZE
);
804 print_insn_sparc (memaddr
, info
)
806 disassemble_info
*info
;
808 /* It's not clear that we'll ever switch cpus in a running program.
809 It could theoretically happen in gdb so we handle it.
810 ??? There is currently a memory leak but it's not worth the trouble. */
812 opcodes_initialized
= 0;
814 return print_insn (memaddr
, info
);
818 print_insn_sparc64 (memaddr
, info
)
820 disassemble_info
*info
;
822 /* It's not clear that we'll ever switch cpus in a running program.
823 It could theoretically happen in gdb so we handle it.
824 ??? There is currently a memory leak but it's not worth the trouble. */
826 opcodes_initialized
= 0;
828 return print_insn (memaddr
, info
);
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