1 /* Table of opcodes for the sparc.
2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this file; see the file COPYING. If not, write to the
18 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* FIXME-someday: perhaps the ,a's and such should be embedded in the
23 instruction's name rather than the args. This would make gas faster, pinsn
24 slower, but would mess up some macros a bit. xoxorich. */
28 #include "opcode/sparc.h"
30 /* Some defines to make life easy. */
31 #define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6)
32 #define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7)
33 #define MASK_V8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)
34 #define MASK_LEON SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_LEON)
35 #define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET)
36 #define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
37 #define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9)
38 #define MASK_V9A SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)
39 #define MASK_V9B SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B)
40 #define MASK_V9C SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9C)
41 #define MASK_V9D SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9D)
42 #define MASK_V9E SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9E)
43 #define MASK_V9V SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9V)
44 #define MASK_V9M SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9M)
46 /* Bit masks of architectures supporting the insn. */
48 #define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \
49 | MASK_SPARCLET | MASK_SPARCLITE \
50 | MASK_V9 | MASK_V9A | MASK_V9B \
51 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
52 /* v6 insns not supported on the sparclet. */
53 #define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \
54 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B \
55 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
56 #define v7 (MASK_V7 | MASK_V8 | MASK_LEON | MASK_SPARCLET \
57 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B \
58 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
59 /* Although not all insns are implemented in hardware, sparclite is defined
60 to be a superset of v8. Unimplemented insns trap and are then theoretically
61 implemented in software.
62 It's not clear that the same is true for sparclet, although the docs
63 suggest it is. Rather than complicating things, the sparclet assembler
64 recognizes all v8 insns. */
65 #define v8 (MASK_V8 | MASK_LEON | MASK_SPARCLET | MASK_SPARCLITE \
66 | MASK_V9 | MASK_V9A | MASK_V9B \
67 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
68 #define sparclet (MASK_SPARCLET)
69 /* sparclet insns supported by leon. */
70 #define letandleon (MASK_SPARCLET | MASK_LEON)
71 #define sparclite (MASK_SPARCLITE)
72 #define v9 (MASK_V9 | MASK_V9A | MASK_V9B \
73 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
74 /* v9 insns supported by leon. */
75 #define v9andleon (MASK_V9 | MASK_V9A | MASK_V9B \
76 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \
78 #define v9a (MASK_V9A | MASK_V9B \
79 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
80 #define v9b (MASK_V9B \
81 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
82 #define v9c (MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
83 #define v9d (MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
84 #define v9e (MASK_V9E | MASK_V9V | MASK_V9M)
85 #define v9v (MASK_V9V | MASK_V9M)
86 #define v9m (MASK_V9M)
88 /* v6 insns not supported by v9. */
89 #define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \
90 | MASK_SPARCLET | MASK_SPARCLITE)
91 /* v9a instructions which would appear to be aliases to v9's impdep's
93 #define v9notv9a (MASK_V9)
95 /* Table of opcode architectures.
96 The order is defined in opcode/sparc.h. */
98 const struct sparc_opcode_arch sparc_opcode_archs
[] =
101 { "v7", MASK_V6
| MASK_V7
},
102 { "v8", MASK_V6
| MASK_V7
| MASK_V8
},
103 { "leon", MASK_V6
| MASK_V7
| MASK_V8
| MASK_LEON
},
104 { "sparclet", MASK_V6
| MASK_V7
| MASK_V8
| MASK_SPARCLET
},
105 { "sparclite", MASK_V6
| MASK_V7
| MASK_V8
| MASK_SPARCLITE
},
106 /* ??? Don't some v8 priviledged insns conflict with v9? */
107 { "v9", MASK_V6
| MASK_V7
| MASK_V8
| MASK_V9
},
108 /* v9 with ultrasparc additions */
109 { "v9a", MASK_V6
| MASK_V7
| MASK_V8
| MASK_V9
| MASK_V9A
},
110 /* v9 with cheetah additions */
111 { "v9b", MASK_V6
| MASK_V7
| MASK_V8
| MASK_V9
| MASK_V9A
| MASK_V9B
},
112 /* v9 with UA2005 and T1 additions. */
113 { "v9c", (MASK_V6
| MASK_V7
| MASK_V8
| MASK_V9
| MASK_V9A
| MASK_V9B
115 /* v9 with UA2007 and T3 additions. */
116 { "v9d", (MASK_V6
| MASK_V7
| MASK_V8
| MASK_V9
| MASK_V9A
| MASK_V9B
117 | MASK_V9C
| MASK_V9D
) },
118 /* v9 with OSA2011 and T4 additions modulus integer multiply-add. */
119 { "v9e", (MASK_V6
| MASK_V7
| MASK_V8
| MASK_V9
| MASK_V9A
| MASK_V9B
120 | MASK_V9C
| MASK_V9D
| MASK_V9E
) },
121 /* V9 with OSA2011 and T4 additions, integer multiply and Fujitsu fp
123 { "v9v", (MASK_V6
| MASK_V7
| MASK_V8
| MASK_V9
| MASK_V9A
| MASK_V9B
124 | MASK_V9C
| MASK_V9D
| MASK_V9E
| MASK_V9V
) },
125 /* v9 with OSA2015 and M7 additions. */
126 { "v9m", (MASK_V6
| MASK_V7
| MASK_V8
| MASK_V9
| MASK_V9A
| MASK_V9B
127 | MASK_V9C
| MASK_V9D
| MASK_V9E
| MASK_V9V
| MASK_V9M
) },
131 /* Given NAME, return it's architecture entry. */
133 enum sparc_opcode_arch_val
134 sparc_opcode_lookup_arch (const char *name
)
136 const struct sparc_opcode_arch
*p
;
138 for (p
= &sparc_opcode_archs
[0]; p
->name
; ++p
)
139 if (strcmp (name
, p
->name
) == 0)
140 return (enum sparc_opcode_arch_val
) (p
- &sparc_opcode_archs
[0]);
142 return SPARC_OPCODE_ARCH_BAD
;
145 /* Branch condition field. */
146 #define COND(x) (((x) & 0xf) << 25)
148 /* Compare And Branch condition field. */
149 #define CBCOND(x) (((x) & 0x1f) << 25)
151 /* v9: Move (MOVcc and FMOVcc) condition field. */
152 #define MCOND(x,i_or_f) ((((i_or_f) & 1) << 18) | (((x) >> 11) & (0xf << 14))) /* v9 */
154 /* v9: Move register (MOVRcc and FMOVRcc) condition field. */
155 #define RCOND(x) (((x) & 0x7) << 10) /* v9 */
157 #define CONDA (COND (0x8))
158 #define CONDCC (COND (0xd))
159 #define CONDCS (COND (0x5))
160 #define CONDE (COND (0x1))
161 #define CONDG (COND (0xa))
162 #define CONDGE (COND (0xb))
163 #define CONDGU (COND (0xc))
164 #define CONDL (COND (0x3))
165 #define CONDLE (COND (0x2))
166 #define CONDLEU (COND (0x4))
167 #define CONDN (COND (0x0))
168 #define CONDNE (COND (0x9))
169 #define CONDNEG (COND (0x6))
170 #define CONDPOS (COND (0xe))
171 #define CONDVC (COND (0xf))
172 #define CONDVS (COND (0x7))
174 #define CONDNZ CONDNE
176 #define CONDGEU CONDCC
177 #define CONDLU CONDCS
179 #define FCONDA (COND (0x8))
180 #define FCONDE (COND (0x9))
181 #define FCONDG (COND (0x6))
182 #define FCONDGE (COND (0xb))
183 #define FCONDL (COND (0x4))
184 #define FCONDLE (COND (0xd))
185 #define FCONDLG (COND (0x2))
186 #define FCONDN (COND (0x0))
187 #define FCONDNE (COND (0x1))
188 #define FCONDO (COND (0xf))
189 #define FCONDU (COND (0x7))
190 #define FCONDUE (COND (0xa))
191 #define FCONDUG (COND (0x5))
192 #define FCONDUGE (COND (0xc))
193 #define FCONDUL (COND (0x3))
194 #define FCONDULE (COND (0xe))
196 #define FCONDNZ FCONDNE
197 #define FCONDZ FCONDE
199 #define ICC (0) /* v9 */
200 #define XCC (1 << 12) /* v9 */
201 #define CBCOND_XCC (1 << 21)
202 #define FCC(x) (((x) & 0x3) << 11) /* v9 */
203 #define FBFCC(x) (((x) & 0x3) << 20) /* v9 */
205 /* The order of the opcodes in the table is significant:
207 * The assembler requires that all instances of the same mnemonic must
208 be consecutive. If they aren't, the assembler will bomb at runtime.
210 * The disassembler should not care about the order of the opcodes. */
212 /* Entries for commutative arithmetic operations. */
213 /* ??? More entries can make use of this. */
214 #define COMMUTEOP(opcode, op3, arch_mask) \
215 { opcode, F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0), "1,2,d", 0, 0, 0, arch_mask }, \
216 { opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "1,i,d", 0, 0, 0, arch_mask }, \
217 { opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "i,1,d", 0, 0, 0, arch_mask }
219 const struct sparc_opcode sparc_opcodes
[] = {
221 { "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", 0, 0, 0, v6
},
222 { "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0
, "[1],d", 0, 0, 0, v6
}, /* ld [rs1+%g0],d */
223 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", 0, 0, 0, v6
},
224 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", 0, 0, 0, v6
},
225 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0
, "[i],d", 0, 0, 0, v6
},
226 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6
}, /* ld [rs1+0],d */
227 { "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0), "[1+2],g", 0, 0, 0, v6
},
228 { "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0
, "[1],g", 0, 0, 0, v6
}, /* ld [rs1+%g0],d */
229 { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[1+i],g", 0, 0, 0, v6
},
230 { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[i+1],g", 0, 0, 0, v6
},
231 { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0
, "[i],g", 0, 0, 0, v6
},
232 { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0), "[1],g", 0, 0, 0, v6
}, /* ld [rs1+0],d */
234 { "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0), "[1+2],F", 0, 0, 0, v6
},
235 { "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0
|RD(~0),"[1],F", 0, 0, 0, v6
}, /* ld [rs1+%g0],d */
236 { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[1+i],F", 0, 0, 0, v6
},
237 { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[i+1],F", 0, 0, 0, v6
},
238 { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0
|RD(~0),"[i],F", 0, 0, 0, v6
},
239 { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, 0, 0, v6
}, /* ld [rs1+0],d */
241 { "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2],D", 0, 0, 0, v6notv9
},
242 { "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0
, "[1],D", 0, 0, 0, v6notv9
}, /* ld [rs1+%g0],d */
243 { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i],D", 0, 0, 0, v6notv9
},
244 { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1],D", 0, 0, 0, v6notv9
},
245 { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0
, "[i],D", 0, 0, 0, v6notv9
},
246 { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1],D", 0, 0, 0, v6notv9
}, /* ld [rs1+0],d */
247 { "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0), "[1+2],C", 0, 0, 0, v6notv9
},
248 { "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0
, "[1],C", 0, 0, 0, v6notv9
}, /* ld [rs1+%g0],d */
249 { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[1+i],C", 0, 0, 0, v6notv9
},
250 { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[i+1],C", 0, 0, 0, v6notv9
},
251 { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0
, "[i],C", 0, 0, 0, v6notv9
},
252 { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0), "[1],C", 0, 0, 0, v6notv9
}, /* ld [rs1+0],d */
254 /* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the
255 'ld' pseudo-op in v9. */
256 { "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", F_ALIAS
, 0, 0, v9
},
257 { "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0
, "[1],d", F_ALIAS
, 0, 0, v9
}, /* ld [rs1+%g0],d */
258 { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", F_ALIAS
, 0, 0, v9
},
259 { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", F_ALIAS
, 0, 0, v9
},
260 { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0
, "[i],d", F_ALIAS
, 0, 0, v9
},
261 { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", F_ALIAS
, 0, 0, v9
}, /* ld [rs1+0],d */
263 { "ldtw", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v9
},
264 { "ldtw", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v9
}, /* ldd [rs1+%g0],d */
265 { "ldtw", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", 0, 0, 0, v9
},
266 { "ldtw", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", 0, 0, 0, v9
},
267 { "ldtw", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0
, "[i],d", 0, 0, 0, v9
},
268 { "ldtw", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v9
}, /* ldd [rs1+0],d */
270 { "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", F_ALIAS
, 0, 0, v6
},
271 { "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", F_ALIAS
, 0, 0, v6
}, /* ldd [rs1+%g0],d */
272 { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", F_ALIAS
, 0, 0, v6
},
273 { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", F_ALIAS
, 0, 0, v6
},
274 { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0
, "[i],d", F_ALIAS
, 0, 0, v6
},
275 { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", F_ALIAS
, 0, 0, v6
}, /* ldd [rs1+0],d */
276 { "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0), "[1+2],H", F_ALIAS
, 0, 0, v6
},
277 { "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0), "[1],H", F_ALIAS
, 0, 0, v6
}, /* ldd [rs1+%g0],d */
278 { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[1+i],H", F_ALIAS
, 0, 0, v6
},
279 { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[i+1],H", F_ALIAS
, 0, 0, v6
},
280 { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0
, "[i],H", F_ALIAS
, 0, 0, v6
},
281 { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0), "[1],H", F_ALIAS
, 0, 0, v6
}, /* ldd [rs1+0],d */
283 { "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0), "[1+2],D", 0, 0, 0, v6notv9
},
284 { "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0), "[1],D", 0, 0, 0, v6notv9
}, /* ldd [rs1+%g0],d */
285 { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i],D", 0, 0, 0, v6notv9
},
286 { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1],D", 0, 0, 0, v6notv9
},
287 { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0
, "[i],D", 0, 0, 0, v6notv9
},
288 { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1],D", 0, 0, 0, v6notv9
}, /* ldd [rs1+0],d */
290 { "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0), "[1+2],J", 0, 0, 0, v9
},
291 { "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0), "[1],J", 0, 0, 0, v9
}, /* ldd [rs1+%g0],d */
292 { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[1+i],J", 0, 0, 0, v9
},
293 { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[i+1],J", 0, 0, 0, v9
},
294 { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0
, "[i],J", 0, 0, 0, v9
},
295 { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0), "[1],J", 0, 0, 0, v9
}, /* ldd [rs1+0],d */
297 { "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v6
},
298 { "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v6
}, /* ldsb [rs1+%g0],d */
299 { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[1+i],d", 0, 0, 0, v6
},
300 { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[i+1],d", 0, 0, 0, v6
},
301 { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0
, "[i],d", 0, 0, 0, v6
},
302 { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6
}, /* ldsb [rs1+0],d */
304 { "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v6
}, /* ldsh [rs1+%g0],d */
305 { "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v6
},
306 { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[1+i],d", 0, 0, 0, v6
},
307 { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[i+1],d", 0, 0, 0, v6
},
308 { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0
, "[i],d", 0, 0, 0, v6
},
309 { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6
}, /* ldsh [rs1+0],d */
311 { "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v6
},
312 { "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v6
}, /* ldstub [rs1+%g0],d */
313 { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[1+i],d", 0, 0, 0, v6
},
314 { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[i+1],d", 0, 0, 0, v6
},
315 { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0
, "[i],d", 0, 0, 0, v6
},
316 { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6
}, /* ldstub [rs1+0],d */
318 { "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v9
},
319 { "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v9
}, /* ldsw [rs1+%g0],d */
320 { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[1+i],d", 0, 0, 0, v9
},
321 { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[i+1],d", 0, 0, 0, v9
},
322 { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0
, "[i],d", 0, 0, 0, v9
},
323 { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v9
}, /* ldsw [rs1+0],d */
325 { "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v6
},
326 { "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v6
}, /* ldub [rs1+%g0],d */
327 { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[1+i],d", 0, 0, 0, v6
},
328 { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[i+1],d", 0, 0, 0, v6
},
329 { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0
, "[i],d", 0, 0, 0, v6
},
330 { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6
}, /* ldub [rs1+0],d */
332 { "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v6
},
333 { "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v6
}, /* lduh [rs1+%g0],d */
334 { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[1+i],d", 0, 0, 0, v6
},
335 { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[i+1],d", 0, 0, 0, v6
},
336 { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0
, "[i],d", 0, 0, 0, v6
},
337 { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6
}, /* lduh [rs1+0],d */
339 { "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v9
},
340 { "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v9
}, /* ldx [rs1+%g0],d */
341 { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[1+i],d", 0, 0, 0, v9
},
342 { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[i+1],d", 0, 0, 0, v9
},
343 { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0
, "[i],d", 0, 0, 0, v9
},
344 { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v9
}, /* ldx [rs1+0],d */
346 { "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F", 0, 0, 0, v9
},
347 { "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0
|RD(~1), "[1],F", 0, 0, 0, v9
}, /* ld [rs1+%g0],d */
348 { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F", 0, 0, 0, v9
},
349 { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F", 0, 0, 0, v9
},
350 { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0
|RD(~1), "[i],F", 0, 0, 0, v9
},
351 { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, 0, 0, v9
}, /* ld [rs1+0],d */
353 { "ldx", F3(3, 0x21, 0)|RD(3), F3(~3, ~0x21, ~0)|RD(~3), "[1+2],(", 0, 0, HWCAP2_VIS3B
, v9b
},
354 { "ldx", F3(3, 0x21, 0)|RD(3), F3(~3, ~0x21, ~0)|RS2_G0
|RD(~3),"[1],(", 0, 0, HWCAP2_VIS3B
, v9b
},
355 { "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RD(~3), "[1+i],(", 0, 0, HWCAP2_VIS3B
, v9b
},
356 { "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RD(~3), "[i+1],(", 0, 0, HWCAP2_VIS3B
, v9b
},
357 { "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RS1_G0
|RD(~3),"[i],(", 0, 0, HWCAP2_VIS3B
, v9b
},
358 { "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~3),"[1],(", 0, 0, HWCAP2_VIS3B
, v9b
},
360 { "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", 0, 0, 0, v6
},
361 { "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0
, "[1]A,d", 0, 0, 0, v6
}, /* lda [rs1+%g0],d */
362 { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", 0, 0, 0, v9
},
363 { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", 0, 0, 0, v9
},
364 { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0
, "[i]o,d", 0, 0, 0, v9
},
365 { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9
}, /* ld [rs1+0],d */
366 { "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2]A,g", 0, 0, 0, v9
},
367 { "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0
, "[1]A,g", 0, 0, 0, v9
}, /* lda [rs1+%g0],d */
368 { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i]o,g", 0, 0, 0, v9
},
369 { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1]o,g", 0, 0, 0, v9
},
370 { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0
, "[i]o,g", 0, 0, 0, v9
},
371 { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1]o,g", 0, 0, 0, v9
}, /* ld [rs1+0],d */
373 { "ldtwa", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", 0, 0, 0, v9
},
374 { "ldtwa", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0
, "[1]A,d", 0, 0, 0, v9
}, /* ldda [rs1+%g0],d */
375 { "ldtwa", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", 0, 0, 0, v9
},
376 { "ldtwa", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d", 0, 0, 0, v9
},
377 { "ldtwa", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0
, "[i]o,d", 0, 0, 0, v9
},
378 { "ldtwa", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9
}, /* ld [rs1+0],d */
380 { "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", F_ALIAS
, 0, 0, v6
},
381 { "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0
, "[1]A,d", F_ALIAS
, 0, 0, v6
}, /* ldda [rs1+%g0],d */
382 { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", F_ALIAS
, 0, 0, v9
},
383 { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d", F_ALIAS
, 0, 0, v9
},
384 { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0
, "[i]o,d", F_ALIAS
, 0, 0, v9
},
385 { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS
, 0, 0, v9
}, /* ld [rs1+0],d */
387 { "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0), "[1+2]A,H", 0, 0, 0, v9
},
388 { "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0
, "[1]A,H", 0, 0, 0, v9
}, /* ldda [rs1+%g0],d */
389 { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i]o,H", 0, 0, 0, v9
},
390 { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1]o,H", 0, 0, 0, v9
},
391 { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0
, "[i]o,H", 0, 0, 0, v9
},
392 { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1]o,H", 0, 0, 0, v9
}, /* ld [rs1+0],d */
394 { "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0), "[1+2]A,J", 0, 0, 0, v9
},
395 { "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0
, "[1]A,J", 0, 0, 0, v9
}, /* ldd [rs1+%g0],d */
396 { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[1+i]o,J", 0, 0, 0, v9
},
397 { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[i+1]o,J", 0, 0, 0, v9
},
398 { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0
, "[i]o,J", 0, 0, 0, v9
},
399 { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0), "[1]o,J", 0, 0, 0, v9
}, /* ldd [rs1+0],d */
401 { "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0), "[1+2]A,d", 0, 0, 0, v6
},
402 { "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0
, "[1]A,d", 0, 0, 0, v6
}, /* ldsba [rs1+%g0],d */
403 { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[1+i]o,d", 0, 0, 0, v9
},
404 { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[i+1]o,d", 0, 0, 0, v9
},
405 { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0
, "[i]o,d", 0, 0, 0, v9
},
406 { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9
}, /* ld [rs1+0],d */
408 { "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0), "[1+2]A,d", 0, 0, 0, v6
},
409 { "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0
, "[1]A,d", 0, 0, 0, v6
}, /* ldsha [rs1+%g0],d */
410 { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[1+i]o,d", 0, 0, 0, v9
},
411 { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[i+1]o,d", 0, 0, 0, v9
},
412 { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0
, "[i]o,d", 0, 0, 0, v9
},
413 { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9
}, /* ld [rs1+0],d */
415 { "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0), "[1+2]A,d", 0, 0, 0, v6
},
416 { "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0
, "[1]A,d", 0, 0, 0, v6
}, /* ldstuba [rs1+%g0],d */
417 { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[1+i]o,d", 0, 0, 0, v9
},
418 { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[i+1]o,d", 0, 0, 0, v9
},
419 { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0
, "[i]o,d", 0, 0, 0, v9
},
420 { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9
}, /* ld [rs1+0],d */
422 { "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0), "[1+2]A,d", 0, 0, 0, v9
},
423 { "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0
, "[1]A,d", 0, 0, 0, v9
}, /* lda [rs1+%g0],d */
424 { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[1+i]o,d", 0, 0, 0, v9
},
425 { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[i+1]o,d", 0, 0, 0, v9
},
426 { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0
, "[i]o,d", 0, 0, 0, v9
},
427 { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9
}, /* ld [rs1+0],d */
429 { "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0), "[1+2]A,d", 0, 0, 0, v6
},
430 { "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0
, "[1]A,d", 0, 0, 0, v6
}, /* lduba [rs1+%g0],d */
431 { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[1+i]o,d", 0, 0, 0, v9
},
432 { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[i+1]o,d", 0, 0, 0, v9
},
433 { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0
, "[i]o,d", 0, 0, 0, v9
},
434 { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9
}, /* ld [rs1+0],d */
436 { "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0), "[1+2]A,d", 0, 0, 0, v6
},
437 { "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0
, "[1]A,d", 0, 0, 0, v6
}, /* lduha [rs1+%g0],d */
438 { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[1+i]o,d", 0, 0, 0, v9
},
439 { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[i+1]o,d", 0, 0, 0, v9
},
440 { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0
, "[i]o,d", 0, 0, 0, v9
},
441 { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9
}, /* ld [rs1+0],d */
443 { "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", F_ALIAS
, 0, 0, v9
}, /* lduwa === lda */
444 { "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0
, "[1]A,d", F_ALIAS
, 0, 0, v9
}, /* lda [rs1+%g0],d */
445 { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", F_ALIAS
, 0, 0, v9
},
446 { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", F_ALIAS
, 0, 0, v9
},
447 { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0
, "[i]o,d", F_ALIAS
, 0, 0, v9
},
448 { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS
, 0, 0, v9
}, /* ld [rs1+0],d */
450 { "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0), "[1+2]A,d", 0, 0, 0, v9
},
451 { "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0
, "[1]A,d", 0, 0, 0, v9
}, /* lda [rs1+%g0],d */
452 { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[1+i]o,d", 0, 0, 0, v9
},
453 { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[i+1]o,d", 0, 0, 0, v9
},
454 { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0
, "[i]o,d", 0, 0, 0, v9
},
455 { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9
}, /* ld [rs1+0],d */
457 { "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", 0, 0, 0, v6
},
458 { "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, 0, v6
}, /* st d,[rs1+%g0] */
459 { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", 0, 0, 0, v6
},
460 { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", 0, 0, 0, v6
},
461 { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0
, "d,[i]", 0, 0, 0, v6
},
462 { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", 0, 0, 0, v6
}, /* st d,[rs1+0] */
463 { "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0), "g,[1+2]", 0, 0, 0, v6
},
464 { "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0), "g,[1]", 0, 0, 0, v6
}, /* st d[rs1+%g0] */
465 { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[1+i]", 0, 0, 0, v6
},
466 { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[i+1]", 0, 0, 0, v6
},
467 { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0
, "g,[i]", 0, 0, 0, v6
},
468 { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0), "g,[1]", 0, 0, 0, v6
}, /* st d,[rs1+0] */
470 { "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0), "D,[1+2]", 0, 0, 0, v6notv9
},
471 { "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0), "D,[1]", 0, 0, 0, v6notv9
}, /* st d,[rs1+%g0] */
472 { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[1+i]", 0, 0, 0, v6notv9
},
473 { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[i+1]", 0, 0, 0, v6notv9
},
474 { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0
, "D,[i]", 0, 0, 0, v6notv9
},
475 { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "D,[1]", 0, 0, 0, v6notv9
}, /* st d,[rs1+0] */
476 { "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0), "C,[1+2]", 0, 0, 0, v6notv9
},
477 { "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0), "C,[1]", 0, 0, 0, v6notv9
}, /* st d,[rs1+%g0] */
478 { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[1+i]", 0, 0, 0, v6notv9
},
479 { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[i+1]", 0, 0, 0, v6notv9
},
480 { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0
, "C,[i]", 0, 0, 0, v6notv9
},
481 { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0), "C,[1]", 0, 0, 0, v6notv9
}, /* st d,[rs1+0] */
483 { "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0
|ASI(~0), "F,[1+2]", 0, 0, 0, v6
},
484 { "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0
|ASI_RS2(~0), "F,[1]", 0, 0, 0, v6
}, /* st d,[rs1+%g0] */
485 { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0
, "F,[1+i]", 0, 0, 0, v6
},
486 { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0
, "F,[i+1]", 0, 0, 0, v6
},
487 { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0
|RS1_G0
, "F,[i]", 0, 0, 0, v6
},
488 { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0
|SIMM13(~0), "F,[1]", 0, 0, 0, v6
}, /* st d,[rs1+0] */
490 { "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS
, 0, 0, v9
},
491 { "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS
, 0, 0, v9
}, /* st d,[rs1+%g0] */
492 { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS
, 0, 0, v9
},
493 { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS
, 0, 0, v9
},
494 { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0
, "d,[i]", F_ALIAS
, 0, 0, v9
},
495 { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS
, 0, 0, v9
}, /* st d,[rs1+0] */
496 { "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS
, 0, 0, v9
},
497 { "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS
, 0, 0, v9
}, /* st d,[rs1+%g0] */
498 { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS
, 0, 0, v9
},
499 { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS
, 0, 0, v9
},
500 { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0
, "d,[i]", F_ALIAS
, 0, 0, v9
},
501 { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS
, 0, 0, v9
}, /* st d,[rs1+0] */
502 { "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS
, 0, 0, v9
},
503 { "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS
, 0, 0, v9
}, /* st d,[rs1+%g0] */
504 { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS
, 0, 0, v9
},
505 { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS
, 0, 0, v9
},
506 { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0
, "d,[i]", F_ALIAS
, 0, 0, v9
},
507 { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS
, 0, 0, v9
}, /* st d,[rs1+0] */
509 { "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS
, 0, 0, v6
},
510 { "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS
, 0, 0, v6
}, /* st d,[rs1+%g0] */
511 { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS
, 0, 0, v6
},
512 { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS
, 0, 0, v6
},
513 { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0
, "d,[i]", F_ALIAS
, 0, 0, v6
},
514 { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS
, 0, 0, v6
}, /* st d,[rs1+0] */
516 { "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", 0, 0, 0, v6
},
517 { "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", 0, 0, 0, v6
}, /* sta d,[rs1+%g0] */
518 { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", 0, 0, 0, v9
},
519 { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", 0, 0, 0, v9
},
520 { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0
, "d,[i]o", 0, 0, 0, v9
},
521 { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", 0, 0, 0, v9
}, /* st d,[rs1+0] */
523 { "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0), "g,[1+2]A", 0, 0, 0, v9
},
524 { "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0), "g,[1]A", 0, 0, 0, v9
}, /* sta d,[rs1+%g0] */
525 { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[1+i]o", 0, 0, 0, v9
},
526 { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[i+1]o", 0, 0, 0, v9
},
527 { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0
, "g,[i]o", 0, 0, 0, v9
},
528 { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "g,[1]o", 0, 0, 0, v9
}, /* st d,[rs1+0] */
530 { "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS
, 0, 0, v9
},
531 { "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS
, 0, 0, v9
}, /* sta d,[rs1+%g0] */
532 { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS
, 0, 0, v9
},
533 { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS
, 0, 0, v9
},
534 { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0
, "d,[i]o", F_ALIAS
, 0, 0, v9
},
535 { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS
, 0, 0, v9
}, /* st d,[rs1+0] */
536 { "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS
, 0, 0, v9
},
537 { "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS
, 0, 0, v9
}, /* sta d,[rs1+%g0] */
538 { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS
, 0, 0, v9
},
539 { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS
, 0, 0, v9
},
540 { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0
, "d,[i]o", F_ALIAS
, 0, 0, v9
},
541 { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS
, 0, 0, v9
}, /* st d,[rs1+0] */
542 { "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS
, 0, 0, v9
},
543 { "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS
, 0, 0, v9
}, /* sta d,[rs1+%g0] */
544 { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS
, 0, 0, v9
},
545 { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS
, 0, 0, v9
},
546 { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0
, "d,[i]o", F_ALIAS
, 0, 0, v9
},
547 { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS
, 0, 0, v9
}, /* st d,[rs1+0] */
549 { "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", 0, 0, 0, v6
},
550 { "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, 0, v6
}, /* stb d,[rs1+%g0] */
551 { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", 0, 0, 0, v6
},
552 { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", 0, 0, 0, v6
},
553 { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0
, "d,[i]", 0, 0, 0, v6
},
554 { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", 0, 0, 0, v6
}, /* stb d,[rs1+0] */
556 { "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS
, 0, 0, v6
},
557 { "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS
, 0, 0, v6
}, /* stb d,[rs1+%g0] */
558 { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS
, 0, 0, v6
},
559 { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS
, 0, 0, v6
},
560 { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0
, "d,[i]", F_ALIAS
, 0, 0, v6
},
561 { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS
, 0, 0, v6
}, /* stb d,[rs1+0] */
562 { "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS
, 0, 0, v6
},
563 { "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS
, 0, 0, v6
}, /* stb d,[rs1+%g0] */
564 { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS
, 0, 0, v6
},
565 { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS
, 0, 0, v6
},
566 { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0
, "d,[i]", F_ALIAS
, 0, 0, v6
},
567 { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS
, 0, 0, v6
}, /* stb d,[rs1+0] */
569 { "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", 0, 0, 0, v6
},
570 { "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", 0, 0, 0, v6
}, /* stba d,[rs1+%g0] */
571 { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", 0, 0, 0, v9
},
572 { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", 0, 0, 0, v9
},
573 { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0
, "d,[i]o", 0, 0, 0, v9
},
574 { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", 0, 0, 0, v9
}, /* stb d,[rs1+0] */
576 { "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS
, 0, 0, v6
},
577 { "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS
, 0, 0, v6
}, /* stba d,[rs1+%g0] */
578 { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS
, 0, 0, v9
},
579 { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS
, 0, 0, v9
},
580 { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0
, "d,[i]o", F_ALIAS
, 0, 0, v9
},
581 { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS
, 0, 0, v9
}, /* stb d,[rs1+0] */
582 { "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS
, 0, 0, v6
},
583 { "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS
, 0, 0, v6
}, /* stba d,[rs1+%g0] */
584 { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS
, 0, 0, v9
},
585 { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS
, 0, 0, v9
},
586 { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0
, "d,[i]o", F_ALIAS
, 0, 0, v9
},
587 { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS
, 0, 0, v9
}, /* stb d,[rs1+0] */
589 { "sttw", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", 0, 0, 0, v9
},
590 { "sttw", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, 0, v9
}, /* std d,[rs1+%g0] */
591 { "sttw", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", 0, 0, 0, v9
},
592 { "sttw", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", 0, 0, 0, v9
},
593 { "sttw", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0
, "d,[i]", 0, 0, 0, v9
},
594 { "sttw", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", 0, 0, 0, v9
}, /* std d,[rs1+0] */
596 { "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", F_PREF_ALIAS
, 0, 0, v6
},
597 { "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", F_PREF_ALIAS
, 0, 0, v6
}, /* std d,[rs1+%g0] */
598 { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", F_PREF_ALIAS
, 0, 0, v6
},
599 { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", F_PREF_ALIAS
, 0, 0, v6
},
600 { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0
, "d,[i]", F_PREF_ALIAS
, 0, 0, v6
},
601 { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", F_PREF_ALIAS
, 0, 0, v6
}, /* std d,[rs1+0] */
603 { "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "q,[1+2]", 0, 0, 0, v6notv9
},
604 { "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "q,[1]", 0, 0, 0, v6notv9
}, /* std d,[rs1+%g0] */
605 { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[1+i]", 0, 0, 0, v6notv9
},
606 { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[i+1]", 0, 0, 0, v6notv9
},
607 { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0
, "q,[i]", 0, 0, 0, v6notv9
},
608 { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "q,[1]", 0, 0, 0, v6notv9
}, /* std d,[rs1+0] */
609 { "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0), "H,[1+2]", 0, 0, 0, v6
},
610 { "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0), "H,[1]", 0, 0, 0, v6
}, /* std d,[rs1+%g0] */
611 { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[1+i]", 0, 0, 0, v6
},
612 { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[i+1]", 0, 0, 0, v6
},
613 { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0
, "H,[i]", 0, 0, 0, v6
},
614 { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0), "H,[1]", 0, 0, 0, v6
}, /* std d,[rs1+0] */
616 { "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "Q,[1+2]", 0, 0, 0, v6notv9
},
617 { "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "Q,[1]", 0, 0, 0, v6notv9
}, /* std d,[rs1+%g0] */
618 { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[1+i]", 0, 0, 0, v6notv9
},
619 { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[i+1]", 0, 0, 0, v6notv9
},
620 { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0
, "Q,[i]", 0, 0, 0, v6notv9
},
621 { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "Q,[1]", 0, 0, 0, v6notv9
}, /* std d,[rs1+0] */
622 { "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0), "D,[1+2]", 0, 0, 0, v6notv9
},
623 { "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0), "D,[1]", 0, 0, 0, v6notv9
}, /* std d,[rs1+%g0] */
624 { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[1+i]", 0, 0, 0, v6notv9
},
625 { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[i+1]", 0, 0, 0, v6notv9
},
626 { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0
, "D,[i]", 0, 0, 0, v6notv9
},
627 { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "D,[1]", 0, 0, 0, v6notv9
}, /* std d,[rs1+0] */
629 { "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", F_ALIAS
, 0, 0, v6
},
630 { "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS
, 0, 0, v6
}, /* std d,[rs1+%g0] */
631 { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", F_ALIAS
, 0, 0, v6
},
632 { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", F_ALIAS
, 0, 0, v6
},
633 { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0
, "d,[i]", F_ALIAS
, 0, 0, v6
},
634 { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", F_ALIAS
, 0, 0, v6
}, /* std d,[rs1+0] */
636 { "sttwa", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", 0, 0, 0, v9
},
637 { "sttwa", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", 0, 0, 0, v9
}, /* stda d,[rs1+%g0] */
638 { "sttwa", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o", 0, 0, 0, v9
},
639 { "sttwa", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o", 0, 0, 0, v9
},
640 { "sttwa", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0
, "d,[i]o", 0, 0, 0, v9
},
641 { "sttwa", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", 0, 0, 0, v9
}, /* std d,[rs1+0] */
643 { "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", F_ALIAS
, 0, 0, v6
},
644 { "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", F_ALIAS
, 0, 0, v6
}, /* stda d,[rs1+%g0] */
645 { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o", F_ALIAS
, 0, 0, v9
},
646 { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o", F_ALIAS
, 0, 0, v9
},
647 { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0
, "d,[i]o", F_ALIAS
, 0, 0, v9
},
648 { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS
, 0, 0, v9
}, /* std d,[rs1+0] */
649 { "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0), "H,[1+2]A", 0, 0, 0, v9
},
650 { "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0), "H,[1]A", 0, 0, 0, v9
}, /* stda d,[rs1+%g0] */
651 { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[1+i]o", 0, 0, 0, v9
},
652 { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[i+1]o", 0, 0, 0, v9
},
653 { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0
, "H,[i]o", 0, 0, 0, v9
},
654 { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "H,[1]o", 0, 0, 0, v9
}, /* std d,[rs1+0] */
656 { "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", 0, 0, 0, v6
},
657 { "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, 0, v6
}, /* sth d,[rs1+%g0] */
658 { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", 0, 0, 0, v6
},
659 { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", 0, 0, 0, v6
},
660 { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0
, "d,[i]", 0, 0, 0, v6
},
661 { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", 0, 0, 0, v6
}, /* sth d,[rs1+0] */
663 { "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS
, 0, 0, v6
},
664 { "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS
, 0, 0, v6
}, /* sth d,[rs1+%g0] */
665 { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS
, 0, 0, v6
},
666 { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS
, 0, 0, v6
},
667 { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0
, "d,[i]", F_ALIAS
, 0, 0, v6
},
668 { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS
, 0, 0, v6
}, /* sth d,[rs1+0] */
669 { "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS
, 0, 0, v6
},
670 { "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS
, 0, 0, v6
}, /* sth d,[rs1+%g0] */
671 { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS
, 0, 0, v6
},
672 { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS
, 0, 0, v6
},
673 { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0
, "d,[i]", F_ALIAS
, 0, 0, v6
},
674 { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS
, 0, 0, v6
}, /* sth d,[rs1+0] */
676 { "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", 0, 0, 0, v6
},
677 { "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", 0, 0, 0, v6
}, /* stha ,[rs1+%g0] */
678 { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", 0, 0, 0, v9
},
679 { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", 0, 0, 0, v9
},
680 { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0
, "d,[i]o", 0, 0, 0, v9
},
681 { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", 0, 0, 0, v9
}, /* sth d,[rs1+0] */
683 { "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS
, 0, 0, v6
},
684 { "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS
, 0, 0, v6
}, /* stha ,[rs1+%g0] */
685 { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS
, 0, 0, v9
},
686 { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS
, 0, 0, v9
},
687 { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0
, "d,[i]o", F_ALIAS
, 0, 0, v9
},
688 { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS
, 0, 0, v9
}, /* sth d,[rs1+0] */
689 { "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS
, 0, 0, v6
},
690 { "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS
, 0, 0, v6
}, /* stha ,[rs1+%g0] */
691 { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS
, 0, 0, v9
},
692 { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS
, 0, 0, v9
},
693 { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0
, "d,[i]o", F_ALIAS
, 0, 0, v9
},
694 { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS
, 0, 0, v9
}, /* sth d,[rs1+0] */
696 { "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0), "d,[1+2]", 0, 0, 0, v9
},
697 { "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, 0, v9
}, /* stx d,[rs1+%g0] */
698 { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[1+i]", 0, 0, 0, v9
},
699 { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[i+1]", 0, 0, 0, v9
},
700 { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0
, "d,[i]", 0, 0, 0, v9
},
701 { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0), "d,[1]", 0, 0, 0, v9
}, /* stx d,[rs1+0] */
703 { "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1), "F,[1+2]", 0, 0, 0, v9
},
704 { "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, 0, 0, v9
}, /* stx d,[rs1+%g0] */
705 { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[1+i]", 0, 0, 0, v9
},
706 { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[i+1]", 0, 0, 0, v9
},
707 { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0
|RD(~1), "F,[i]", 0, 0, 0, v9
},
708 { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, 0, 0, v9
}, /* stx d,[rs1+0] */
710 { "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0), "d,[1+2]A", 0, 0, 0, v9
},
711 { "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0), "d,[1]A", 0, 0, 0, v9
}, /* stxa d,[rs1+%g0] */
712 { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[1+i]o", 0, 0, 0, v9
},
713 { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[i+1]o", 0, 0, 0, v9
},
714 { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0
, "d,[i]o", 0, 0, 0, v9
},
715 { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0), "d,[1]o", 0, 0, 0, v9
}, /* stx d,[rs1+0] */
717 { "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "J,[1+2]", 0, 0, 0, v9
},
718 { "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "J,[1]", 0, 0, 0, v9
}, /* stq [rs1+%g0] */
719 { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[1+i]", 0, 0, 0, v9
},
720 { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[i+1]", 0, 0, 0, v9
},
721 { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0
, "J,[i]", 0, 0, 0, v9
},
722 { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "J,[1]", 0, 0, 0, v9
}, /* stq [rs1+0] */
724 { "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "J,[1+2]A", 0, 0, 0, v9
},
725 { "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "J,[1]A", 0, 0, 0, v9
}, /* stqa [rs1+%g0] */
726 { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[1+i]o", 0, 0, 0, v9
},
727 { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[i+1]o", 0, 0, 0, v9
},
728 { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0
, "J,[i]o", 0, 0, 0, v9
},
729 { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "J,[1]o", 0, 0, 0, v9
}, /* stqa [rs1+0] */
731 { "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v7
},
732 { "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v7
}, /* swap [rs1+%g0],d */
733 { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[1+i],d", 0, 0, 0, v7
},
734 { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[i+1],d", 0, 0, 0, v7
},
735 { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0
, "[i],d", 0, 0, 0, v7
},
736 { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v7
}, /* swap [rs1+0],d */
738 { "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0), "[1+2]A,d", 0, 0, 0, v7
},
739 { "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0), "[1]A,d", 0, 0, 0, v7
}, /* swapa [rs1+%g0],d */
740 { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[1+i]o,d", 0, 0, 0, v9
},
741 { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[i+1]o,d", 0, 0, 0, v9
},
742 { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0
, "[i]o,d", 0, 0, 0, v9
},
743 { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9
}, /* swap [rs1+0],d */
745 { "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
746 { "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0
|RS1_G0
|ASI_RS2(~0), "", 0, 0, 0, v6
}, /* restore %g0,%g0,%g0 */
747 { "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1), "1,i,d", 0, 0, 0, v6
},
748 { "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0
|RS1_G0
|SIMM13(~0), "", 0, 0, 0, v6
}, /* restore %g0,0,%g0 */
750 { "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0
|ASI(~0), "1+2", F_UNBR
|F_DELAYED
, 0, 0, v6
}, /* rett rs1+rs2 */
751 { "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0
|ASI_RS2(~0), "1", F_UNBR
|F_DELAYED
, 0, 0, v6
}, /* rett rs1,%g0 */
752 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0
, "1+i", F_UNBR
|F_DELAYED
, 0, 0, v6
}, /* rett rs1+X */
753 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0
, "i+1", F_UNBR
|F_DELAYED
, 0, 0, v6
}, /* rett X+rs1 */
754 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0
|RS1_G0
, "i", F_UNBR
|F_DELAYED
, 0, 0, v6
}, /* rett X+rs1 */
755 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0
|RS1_G0
, "i", F_UNBR
|F_DELAYED
, 0, 0, v6
}, /* rett X */
756 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0
|SIMM13(~0), "1", F_UNBR
|F_DELAYED
, 0, 0, v6
}, /* rett rs1+0 */
758 { "save", F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
759 { "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "1,i,d", 0, 0, 0, v6
},
760 { "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "i,1,d", 0, 0, 0, v6
}, /* Sun assembler compatibility */
761 { "save", 0x81e00000, ~0x81e00000, "", F_ALIAS
, 0, 0, v6
},
763 { "ret", F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8), "", F_UNBR
|F_DELAYED
, 0, 0, v6
}, /* jmpl %i7+8,%g0 */
764 { "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR
|F_DELAYED
, 0, 0, v6
}, /* jmpl %o7+8,%g0 */
766 { "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0), "1+2,d", F_JSR
|F_DELAYED
, 0, 0, v6
},
767 { "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0), "1,d", F_JSR
|F_DELAYED
, 0, 0, v6
}, /* jmpl rs1+%g0,d */
768 { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0), "1,d", F_JSR
|F_DELAYED
, 0, 0, v6
}, /* jmpl rs1+0,d */
769 { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0
, "i,d", F_JSR
|F_DELAYED
, 0, 0, v6
}, /* jmpl %g0+i,d */
770 { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "1+i,d", F_JSR
|F_DELAYED
, 0, 0, v6
},
771 { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "i+1,d", F_JSR
|F_DELAYED
, 0, 0, v6
},
773 { "done", F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0
|SIMM13(~0), "", 0, 0, 0, v9
},
774 { "retry", F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0
|SIMM13(~0), "", 0, 0, 0, v9
},
775 { "saved", F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0
|SIMM13(~0), "", 0, 0, 0, v9
},
776 { "restored", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0
|SIMM13(~0), "", 0, 0, 0, v9
},
777 { "allclean", F3(2, 0x31, 0)|RD(2), F3(~2, ~0x31, ~0)|RD(~2)|RS1_G0
|SIMM13(~0), "", 0, 0, 0, v9
},
778 { "otherw", F3(2, 0x31, 0)|RD(3), F3(~2, ~0x31, ~0)|RD(~3)|RS1_G0
|SIMM13(~0), "", 0, 0, 0, v9
},
779 { "normalw", F3(2, 0x31, 0)|RD(4), F3(~2, ~0x31, ~0)|RD(~4)|RS1_G0
|SIMM13(~0), "", 0, 0, 0, v9
},
780 { "invalw", F3(2, 0x31, 0)|RD(5), F3(~2, ~0x31, ~0)|RD(~5)|RS1_G0
|SIMM13(~0), "", 0, 0, 0, v9
},
781 { "sir", F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0
, "i", 0, 0, 0, v9
},
783 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "[1+2]", 0, 0, 0, v9
},
784 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "[1]", 0, 0, 0, v9
}, /* flush rs1+%g0 */
785 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "[1]", 0, 0, 0, v9
}, /* flush rs1+0 */
786 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0
, "[i]", 0, 0, 0, v9
}, /* flush %g0+i */
787 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "[1+i]", 0, 0, 0, v9
},
788 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "[i+1]", 0, 0, 0, v9
},
790 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS
, 0, 0, v8
},
791 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS
, 0, 0, v8
}, /* flush rs1+%g0 */
792 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS
, 0, 0, v8
}, /* flush rs1+0 */
793 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0
, "i", F_ALIAS
, 0, 0, v8
}, /* flush %g0+i */
794 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS
, 0, 0, v8
},
795 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS
, 0, 0, v8
},
797 /* IFLUSH was renamed to FLUSH in v8. */
798 { "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS
, 0, 0, v6
},
799 { "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS
, 0, 0, v6
}, /* flush rs1+%g0 */
800 { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS
, 0, 0, v6
}, /* flush rs1+0 */
801 { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0
, "i", F_ALIAS
, 0, 0, v6
},
802 { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS
, 0, 0, v6
},
803 { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS
, 0, 0, v6
},
805 { "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0), "1+2", 0, 0, 0, v9
},
806 { "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0), "1", 0, 0, 0, v9
}, /* return rs1+%g0 */
807 { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0), "1", 0, 0, 0, v9
}, /* return rs1+0 */
808 { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0
, "i", 0, 0, 0, v9
}, /* return %g0+i */
809 { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "1+i", 0, 0, 0, v9
},
810 { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "i+1", 0, 0, 0, v9
},
812 { "flushw", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0
|RS1_G0
|ASI_RS2(~0), "", 0, 0, 0, v9
},
814 { "membar", F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0
|RS1(~0xf)|SIMM13(~127), "K", 0, 0, 0, v9
},
815 { "stbar", F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0
|RS1(~0xf)|SIMM13(~0), "", 0, 0, 0, v8
},
817 { "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0), "[1+2],*", 0, 0, 0, v9
},
818 { "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0
, "[1],*", 0, 0, 0, v9
}, /* prefetch [rs1+%g0],prefetch_fcn */
819 { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[1+i],*", 0, 0, 0, v9
},
820 { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[i+1],*", 0, 0, 0, v9
},
821 { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0
, "[i],*", 0, 0, 0, v9
},
822 { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0), "[1],*", 0, 0, 0, v9
}, /* prefetch [rs1+0],prefetch_fcn */
823 { "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0), "[1+2]A,*", 0, 0, 0, v9
},
824 { "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0
, "[1]A,*", 0, 0, 0, v9
}, /* prefetcha [rs1+%g0],prefetch_fcn */
825 { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[1+i]o,*", 0, 0, 0, v9
},
826 { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[i+1]o,*", 0, 0, 0, v9
},
827 { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0
, "[i]o,*", 0, 0, 0, v9
},
828 { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0), "[1]o,*", 0, 0, 0, v9
}, /* prefetcha [rs1+0],d */
830 { "sll", F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, 0, 0, v6
},
831 { "sll", F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, 0, 0, v6
},
832 { "sra", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, 0, 0, v6
},
833 { "sra", F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, 0, 0, v6
},
834 { "srl", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, 0, 0, v6
},
835 { "srl", F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, 0, 0, v6
},
837 { "sllx", F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5), "1,2,d", 0, 0, 0, v9
},
838 { "sllx", F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6), "1,Y,d", 0, 0, 0, v9
},
839 { "srax", F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5), "1,2,d", 0, 0, 0, v9
},
840 { "srax", F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6), "1,Y,d", 0, 0, 0, v9
},
841 { "srlx", F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5), "1,2,d", 0, 0, 0, v9
},
842 { "srlx", F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6), "1,Y,d", 0, 0, 0, v9
},
844 { "mulscc", F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
845 { "mulscc", F3(2, 0x24, 1), F3(~2, ~0x24, ~1), "1,i,d", 0, 0, 0, v6
},
847 { "divscc", F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0), "1,2,d", 0, 0, 0, sparclite
},
848 { "divscc", F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1), "1,i,d", 0, 0, 0, sparclite
},
850 { "scan", F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, sparclet
|sparclite
},
851 { "scan", F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1), "1,i,d", 0, 0, 0, sparclet
|sparclite
},
853 { "popc", F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0
|ASI(~0),"2,d", 0, HWCAP_POPC
, 0, v9
},
854 { "popc", F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS1_G0
, "i,d", 0, HWCAP_POPC
, 0, v9
},
856 { "clr", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0
|RS1_G0
|ASI_RS2(~0), "d", F_ALIAS
, 0, 0, v6
}, /* or %g0,%g0,d */
857 { "clr", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0
|SIMM13(~0), "d", F_ALIAS
, 0, 0, v6
}, /* or %g0,0,d */
858 { "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0
|ASI(~0), "[1+2]", F_ALIAS
, 0, 0, v6
},
859 { "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0
|ASI_RS2(~0), "[1]", F_ALIAS
, 0, 0, v6
}, /* st %g0,[rs1+%g0] */
860 { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0
, "[1+i]", F_ALIAS
, 0, 0, v6
},
861 { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0
, "[i+1]", F_ALIAS
, 0, 0, v6
},
862 { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0
|RS1_G0
, "[i]", F_ALIAS
, 0, 0, v6
},
863 { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0
|SIMM13(~0), "[1]", F_ALIAS
, 0, 0, v6
}, /* st %g0,[rs1+0] */
865 { "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0
|ASI(~0), "[1+2]", F_ALIAS
, 0, 0, v6
},
866 { "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0
|ASI_RS2(~0), "[1]", F_ALIAS
, 0, 0, v6
}, /* stb %g0,[rs1+%g0] */
867 { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0
, "[1+i]", F_ALIAS
, 0, 0, v6
},
868 { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0
, "[i+1]", F_ALIAS
, 0, 0, v6
},
869 { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0
|RS1_G0
, "[i]", F_ALIAS
, 0, 0, v6
},
870 { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0
|SIMM13(~0), "[1]", F_ALIAS
, 0, 0, v6
}, /* stb %g0,[rs1+0] */
872 { "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0
|ASI(~0), "[1+2]", F_ALIAS
, 0, 0, v6
},
873 { "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0
|ASI_RS2(~0), "[1]", F_ALIAS
, 0, 0, v6
}, /* sth %g0,[rs1+%g0] */
874 { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0
, "[1+i]", F_ALIAS
, 0, 0, v6
},
875 { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0
, "[i+1]", F_ALIAS
, 0, 0, v6
},
876 { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0
|RS1_G0
, "[i]", F_ALIAS
, 0, 0, v6
},
877 { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0
|SIMM13(~0), "[1]", F_ALIAS
, 0, 0, v6
}, /* sth %g0,[rs1+0] */
879 { "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0
|ASI(~0), "[1+2]", F_ALIAS
, 0, 0, v9
},
880 { "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0
|ASI_RS2(~0), "[1]", F_ALIAS
, 0, 0, v9
}, /* stx %g0,[rs1+%g0] */
881 { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0
, "[1+i]", F_ALIAS
, 0, 0, v9
},
882 { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0
, "[i+1]", F_ALIAS
, 0, 0, v9
},
883 { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0
|RS1_G0
, "[i]", F_ALIAS
, 0, 0, v9
},
884 { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0
|SIMM13(~0), "[1]", F_ALIAS
, 0, 0, v9
}, /* stx %g0,[rs1+0] */
886 { "orcc", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
887 { "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "1,i,d", 0, 0, 0, v6
},
888 { "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "i,1,d", 0, 0, 0, v6
},
890 /* This is not a commutative instruction. */
891 { "orncc", F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
892 { "orncc", F3(2, 0x16, 1), F3(~2, ~0x16, ~1), "1,i,d", 0, 0, 0, v6
},
894 /* This is not a commutative instruction. */
895 { "orn", F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
896 { "orn", F3(2, 0x06, 1), F3(~2, ~0x06, ~1), "1,i,d", 0, 0, 0, v6
},
898 { "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0
|ASI_RS2(~0), "1", 0, 0, 0, v6
}, /* orcc rs1, %g0, %g0 */
899 { "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0
|RS1_G0
|ASI(~0), "2", 0, 0, 0, v6
}, /* orcc %g0, rs2, %g0 */
900 { "tst", F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0
|SIMM13(~0), "1", 0, 0, 0, v6
}, /* orcc rs1, 0, %g0 */
903 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", 0, 0, 0, v8
}, /* wr r,r,%asrX */
904 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", 0, 0, 0, v8
}, /* wr r,i,%asrX */
905 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RS1_G0
|ASI(~0), "2,m", F_PREF_ALIAS
, 0, 0, v8
}, /* wr %g0,rs2,%asrX */
906 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RS1_G0
, "i,m", F_PREF_ALIAS
, 0, 0, v8
}, /* wr %g0,i,%asrX */
907 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0), "1,m", F_PREF_ALIAS
, 0, 0, v8
}, /* wr rs1,%asrX */
908 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_PREF_ALIAS
, 0, 0, v8
}, /* wr rs1,%g0,%asrX */
909 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0
|ASI(~0), "1,2,y", 0, 0, 0, v6
}, /* wr r,r,%y */
910 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0
, "1,i,y", 0, 0, 0, v6
}, /* wr r,i,%y */
911 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0
|RS1_G0
|ASI(~0), "2,y", F_PREF_ALIAS
, 0, 0, v6
}, /* wr %g0,rs2,%y */
912 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0
|RS1_G0
, "i,y", F_PREF_ALIAS
, 0, 0, v6
}, /* wr %g0,i,%y */
913 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0
|SIMM13(~0), "1,y", F_PREF_ALIAS
, 0, 0, v6
}, /* wr rs1,0,%y */
914 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0
|ASI_RS2(~0), "1,y", F_PREF_ALIAS
, 0, 0, v6
}, /* wr rs1,%g0,%y */
915 { "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0
|ASI(~0), "1,2,p", 0, 0, 0, v6notv9
}, /* wr r,r,%psr */
916 { "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0
, "1,i,p", 0, 0, 0, v6notv9
}, /* wr r,i,%psr */
917 { "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0
|RS1_G0
|ASI(~0), "2,p", F_PREF_ALIAS
, 0, 0, v6notv9
}, /* wr %g0,rs2,%psr */
918 { "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0
|RS1_G0
, "i,p", F_PREF_ALIAS
, 0, 0, v6notv9
}, /* wr %g0,i,%psr */
919 { "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0
|SIMM13(~0), "1,p", F_PREF_ALIAS
, 0, 0, v6notv9
}, /* wr rs1,0,%psr */
920 { "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0
|ASI_RS2(~0), "1,p", F_PREF_ALIAS
, 0, 0, v6notv9
}, /* wr rs1,%g0,%psr */
921 { "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0
|ASI(~0), "1,2,w", 0, 0, 0, v6notv9
}, /* wr r,r,%wim */
922 { "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0
, "1,i,w", 0, 0, 0, v6notv9
}, /* wr r,i,%wim */
923 { "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0
|RS1_G0
|ASI(~0), "2,w", F_PREF_ALIAS
, 0, 0, v6notv9
}, /* wr %g0,rs2,%wim */
924 { "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0
|RS1_G0
, "i,w", F_PREF_ALIAS
, 0, 0, v6notv9
}, /* wr %g0,i,%wim */
925 { "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0
|SIMM13(~0), "1,w", F_PREF_ALIAS
, 0, 0, v6notv9
}, /* wr rs1,0,%wim */
926 { "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0
|ASI_RS2(~0), "1,w", F_PREF_ALIAS
, 0, 0, v6notv9
}, /* wr rs1,%g0,%wim */
927 { "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0
|ASI(~0), "1,2,t", 0, 0, 0, v6notv9
}, /* wr r,r,%tbr */
928 { "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0
, "1,i,t", 0, 0, 0, v6notv9
}, /* wr r,i,%tbr */
929 { "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0
|RS1_G0
|ASI(~0), "2,t", F_PREF_ALIAS
, 0, 0, v6notv9
}, /* wr %g0,rs2,%tbr */
930 { "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0
|RS1_G0
, "i,t", F_PREF_ALIAS
, 0, 0, v6notv9
}, /* wr %g0,i,%tbr */
931 { "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0
|SIMM13(~0), "1,t", F_PREF_ALIAS
, 0, 0, v6notv9
}, /* wr rs1,0,%tbr */
932 { "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0
|ASI_RS2(~0), "1,t", F_PREF_ALIAS
, 0, 0, v6notv9
}, /* wr rs1,%g0,%tbr */
934 { "wr", F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E", 0, 0, 0, v9
}, /* wr r,r,%ccr */
935 { "wr", F3(2, 0x30, 1)|RD(2), F3(~2, ~0x30, ~1)|RD(~2), "1,i,E", 0, 0, 0, v9
}, /* wr r,i,%ccr */
936 { "wr", F3(2, 0x30, 0)|RD(3), F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0), "1,2,o", 0, 0, 0, v9
}, /* wr r,r,%asi */
937 { "wr", F3(2, 0x30, 1)|RD(3), F3(~2, ~0x30, ~1)|RD(~3), "1,i,o", 0, 0, 0, v9
}, /* wr r,i,%asi */
938 { "wr", F3(2, 0x30, 0)|RD(6), F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0), "1,2,s", 0, 0, 0, v9
}, /* wr r,r,%fprs */
939 { "wr", F3(2, 0x30, 1)|RD(6), F3(~2, ~0x30, ~1)|RD(~6), "1,i,s", 0, 0, 0, v9
}, /* wr r,i,%fprs */
940 { "wr", F3(2, 0x30, 0)|RD(14), F3(~2, ~0x30, ~0)|RD(~14), "1,2,{", 0, 0, HWCAP2_SPARC5
, v9b
}, /* wr r,r,%mcdper */
941 { "wr", F3(2, 0x30, 1)|RD(14), F3(~2, ~0x30, ~1)|RD(~14), "1,i,{", 0, 0, HWCAP2_SPARC5
, v9b
}, /* wr r,i,%mcdper */
943 { "wr", F3(2, 0x30, 0)|RD(16), F3(~2, ~0x30, ~0)|RD(~16)|ASI(~0), "1,2,_", 0, HWCAP_VIS
, 0, v9a
}, /* wr r,r,%pcr */
944 { "wr", F3(2, 0x30, 1)|RD(16), F3(~2, ~0x30, ~1)|RD(~16), "1,i,_", 0, HWCAP_VIS
, 0, v9a
}, /* wr r,i,%pcr */
945 { "wr", F3(2, 0x30, 0)|RD(17), F3(~2, ~0x30, ~0)|RD(~17)|ASI(~0), "1,2,_", 0, HWCAP_VIS
, 0, v9a
}, /* wr r,r,%pic */
946 { "wr", F3(2, 0x30, 1)|RD(17), F3(~2, ~0x30, ~1)|RD(~17), "1,i,_", 0, HWCAP_VIS
, 0, v9a
}, /* wr r,i,%pic */
947 { "wr", F3(2, 0x30, 0)|RD(18), F3(~2, ~0x30, ~0)|RD(~18)|ASI(~0), "1,2,_", 0, HWCAP_VIS
, 0, v9a
}, /* wr r,r,%dcr */
948 { "wr", F3(2, 0x30, 1)|RD(18), F3(~2, ~0x30, ~1)|RD(~18), "1,i,_", 0, HWCAP_VIS
, 0, v9a
}, /* wr r,i,%dcr */
949 { "wr", F3(2, 0x30, 0)|RD(19), F3(~2, ~0x30, ~0)|RD(~19)|ASI(~0), "1,2,_", 0, HWCAP_VIS
, 0, v9a
}, /* wr r,r,%gsr */
950 { "wr", F3(2, 0x30, 1)|RD(19), F3(~2, ~0x30, ~1)|RD(~19), "1,i,_", 0, HWCAP_VIS
, 0, v9a
}, /* wr r,i,%gsr */
951 { "wr", F3(2, 0x30, 0)|RD(20), F3(~2, ~0x30, ~0)|RD(~20)|ASI(~0), "1,2,_", 0, HWCAP_VIS
, 0, v9a
}, /* wr r,r,%set_softint */
952 { "wr", F3(2, 0x30, 1)|RD(20), F3(~2, ~0x30, ~1)|RD(~20), "1,i,_", 0, HWCAP_VIS
, 0, v9a
}, /* wr r,i,%set_softint */
953 { "wr", F3(2, 0x30, 0)|RD(21), F3(~2, ~0x30, ~0)|RD(~21)|ASI(~0), "1,2,_", 0, HWCAP_VIS
, 0, v9a
}, /* wr r,r,%clear_softint */
954 { "wr", F3(2, 0x30, 1)|RD(21), F3(~2, ~0x30, ~1)|RD(~21), "1,i,_", 0, HWCAP_VIS
, 0, v9a
}, /* wr r,i,%clear_softint */
955 { "wr", F3(2, 0x30, 0)|RD(22), F3(~2, ~0x30, ~0)|RD(~22)|ASI(~0), "1,2,_", 0, HWCAP_VIS
, 0, v9a
}, /* wr r,r,%softint */
956 { "wr", F3(2, 0x30, 1)|RD(22), F3(~2, ~0x30, ~1)|RD(~22), "1,i,_", 0, HWCAP_VIS
, 0, v9a
}, /* wr r,i,%softint */
957 { "wr", F3(2, 0x30, 0)|RD(23), F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0), "1,2,_", 0, HWCAP_VIS
, 0, v9a
}, /* wr r,r,%tick_cmpr */
958 { "wr", F3(2, 0x30, 1)|RD(23), F3(~2, ~0x30, ~1)|RD(~23), "1,i,_", 0, HWCAP_VIS
, 0, v9a
}, /* wr r,i,%tick_cmpr */
959 { "wr", F3(2, 0x30, 0)|RD(24), F3(~2, ~0x30, ~0)|RD(~24)|ASI(~0), "1,2,_", 0, HWCAP_VIS2
, 0, v9b
}, /* wr r,r,%sys_tick */
960 { "wr", F3(2, 0x30, 1)|RD(24), F3(~2, ~0x30, ~1)|RD(~24), "1,i,_", 0, HWCAP_VIS2
, 0, v9b
}, /* wr r,i,%sys_tick */
961 { "wr", F3(2, 0x30, 0)|RD(25), F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0), "1,2,_", 0, HWCAP_VIS2
, 0, v9b
}, /* wr r,r,%sys_tick_cmpr */
962 { "wr", F3(2, 0x30, 1)|RD(25), F3(~2, ~0x30, ~1)|RD(~25), "1,i,_", 0, HWCAP_VIS2
, 0, v9b
}, /* wr r,i,%sys_tick_cmpr */
963 { "wr", F3(2, 0x30, 0)|RD(26), F3(~2, ~0x30, ~0)|RD(~26)|ASI(~0), "1,2,_", 0, HWCAP_CBCOND
, 0, v9b
}, /* wr r,r,%cfr */
964 { "wr", F3(2, 0x30, 1)|RD(26), F3(~2, ~0x30, ~1)|RD(~26), "1,i,_", 0, HWCAP_CBCOND
, 0, v9b
}, /* wr r,i,%cfr */
965 { "wr", F3(2, 0x30, 0)|RD(27), F3(~2, ~0x30, ~0)|RD(~27)|ASI(~0), "1,2,_", 0, HWCAP_PAUSE
, 0, v9b
}, /* wr r,r,%pause */
966 { "wr", F3(2, 0x30, 1)|RD(27), F3(~2, ~0x30, ~1)|RD(~27), "1,i,_", 0, HWCAP_PAUSE
, 0, v9b
}, /* wr r,i,%pause */
967 { "wr", F3(2, 0x30, 0)|RD(28), F3(~2, ~0x30, ~0)|RD(~28)|ASI(~0), "1,2,_", 0, 0, HWCAP2_MWAIT
, v9b
}, /* wr r,r,%mwait */
968 { "wr", F3(2, 0x30, 1)|RD(28), F3(~2, ~0x30, ~1)|RD(~28), "1,i,_", 0, 0, HWCAP2_MWAIT
, v9b
}, /* wr r,i,%mwait */
970 { "pause", F3(2, 0x30, 1)|RD(27)|RS1(0), F3(~2, ~0x30, ~1)|RD(~27)|RS1(~0), "i", 0, HWCAP_PAUSE
, 0, v9b
}, /* wr %g0,i,%pause */
972 { "rd", F3(2, 0x28, 0)|RS1(2), F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0), "E,d", 0, 0, 0, v9
}, /* rd %ccr,r */
973 { "rd", F3(2, 0x28, 0)|RS1(3), F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0), "o,d", 0, 0, 0, v9
}, /* rd %asi,r */
974 { "rd", F3(2, 0x28, 0)|RS1(4), F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0), "W,d", 0, 0, 0, v9
}, /* rd %tick,r */
975 { "rd", F3(2, 0x28, 0)|RS1(5), F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0), "P,d", 0, 0, 0, v9
}, /* rd %pc,r */
976 { "rd", F3(2, 0x28, 0)|RS1(6), F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0), "s,d", 0, 0, 0, v9
}, /* rd %fprs,r */
977 { "rd", F3(2, 0x28, 0)|RS1(14), F3(~2, ~0x28, ~0)|RS1(~14)|SIMM13(~0), "{,d", 0, 0, HWCAP2_SPARC5
, v9b
}, /* rd %mcdper,r */
979 { "rd", F3(2, 0x28, 0)|RS1(16), F3(~2, ~0x28, ~0)|RS1(~16)|SIMM13(~0), "/,d", 0, HWCAP_VIS
, 0, v9a
}, /* rd %pcr,r */
980 { "rd", F3(2, 0x28, 0)|RS1(17), F3(~2, ~0x28, ~0)|RS1(~17)|SIMM13(~0), "/,d", 0, HWCAP_VIS
, 0, v9a
}, /* rd %pic,r */
981 { "rd", F3(2, 0x28, 0)|RS1(18), F3(~2, ~0x28, ~0)|RS1(~18)|SIMM13(~0), "/,d", 0, HWCAP_VIS
, 0, v9a
}, /* rd %dcr,r */
982 { "rd", F3(2, 0x28, 0)|RS1(19), F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0), "/,d", 0, HWCAP_VIS
, 0, v9a
}, /* rd %gsr,r */
983 { "rd", F3(2, 0x28, 0)|RS1(22), F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0), "/,d", 0, HWCAP_VIS
, 0, v9a
}, /* rd %softint,r */
984 { "rd", F3(2, 0x28, 0)|RS1(23), F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0), "/,d", 0, HWCAP_VIS
, 0, v9a
}, /* rd %tick_cmpr,r */
985 { "rd", F3(2, 0x28, 0)|RS1(24), F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0), "/,d", 0, HWCAP_VIS2
, 0, v9b
}, /* rd %sys_tick,r */
986 { "rd", F3(2, 0x28, 0)|RS1(25), F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0), "/,d", 0, HWCAP_VIS2
, 0, v9b
}, /* rd %sys_tick_cmpr,r */
987 { "rd", F3(2, 0x28, 0)|RS1(26), F3(~2, ~0x28, ~0)|RS1(~26)|SIMM13(~0), "/,d", 0, HWCAP_CBCOND
, 0, v9b
}, /* rd %cfr,r */
988 { "rd", F3(2, 0x28, 0)|RS1(28), F3(~2, ~0x28, ~0)|RS1(~28)|SIMM13(~0), "/,d", 0, 0, HWCAP2_MWAIT
, v9b
}, /* rd %mwait,r */
990 { "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", 0, 0, 0, v8
}, /* rd %asrX,r */
991 { "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0
|SIMM13(~0), "y,d", 0, 0, 0, v6
}, /* rd %y,r */
992 { "rd", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0
|SIMM13(~0), "p,d", 0, 0, 0, v6notv9
}, /* rd %psr,r */
993 { "rd", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0
|SIMM13(~0), "w,d", 0, 0, 0, v6notv9
}, /* rd %wim,r */
994 { "rd", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0
|SIMM13(~0), "t,d", 0, 0, 0, v6notv9
}, /* rd %tbr,r */
996 { "rdpr", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|SIMM13(~0), "?,d", 0, 0, 0, v9
}, /* rdpr %priv,r */
997 { "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0), "1,2,!", 0, 0, 0, v9
}, /* wrpr r1,r2,%priv */
998 { "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|SIMM13(~0), "1,!", 0, 0, 0, v9
}, /* wrpr r1,%priv */
999 { "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "1,i,!", 0, 0, 0, v9
}, /* wrpr r1,i,%priv */
1000 { "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "i,1,!", F_ALIAS
, 0, 0, v9
}, /* wrpr i,r1,%priv */
1001 { "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RS1(~0), "i,!", 0, 0, 0, v9
}, /* wrpr i,%priv */
1003 { "rdhpr", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|SIMM13(~0), "$,d", 0, 0, 0, v9
}, /* rdhpr %hpriv,r */
1004 { "wrhpr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0), "1,2,%", 0, 0, 0, v9
}, /* wrhpr r1,r2,%hpriv */
1005 { "wrhpr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|SIMM13(~0), "1,%", 0, 0, 0, v9
}, /* wrhpr r1,%hpriv */
1006 { "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1), "1,i,%", 0, 0, 0, v9
}, /* wrhpr r1,i,%hpriv */
1007 { "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1), "i,1,%", F_ALIAS
, 0, 0, v9
}, /* wrhpr i,r1,%hpriv */
1008 { "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RS1(~0), "i,%", 0, 0, 0, v9
}, /* wrhpr i,%hpriv */
1010 { "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", F_ALIAS
, 0, 0, v8
}, /* rd %asr1,r */
1011 { "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0
|SIMM13(~0), "y,d", F_ALIAS
, 0, 0, v6
}, /* rd %y,r */
1012 { "mov", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0
|SIMM13(~0), "p,d", F_ALIAS
, 0, 0, v6notv9
}, /* rd %psr,r */
1013 { "mov", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0
|SIMM13(~0), "w,d", F_ALIAS
, 0, 0, v6notv9
}, /* rd %wim,r */
1014 { "mov", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0
|SIMM13(~0), "t,d", F_ALIAS
, 0, 0, v6notv9
}, /* rd %tbr,r */
1016 { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RS1_G0
|ASI(~0), "2,m", F_ALIAS
, 0, 0, v8
}, /* wr %g0,rs2,%asrX */
1017 { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RS1_G0
, "i,m", F_ALIAS
, 0, 0, v8
}, /* wr %g0,i,%asrX */
1018 { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0
|RS1_G0
|ASI(~0), "2,y", F_ALIAS
, 0, 0, v6
}, /* wr %g0,rs2,%y */
1019 { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0
|RS1_G0
, "i,y", F_ALIAS
, 0, 0, v6
}, /* wr %g0,i,%y */
1020 { "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0
|RS1_G0
|ASI(~0), "2,p", F_ALIAS
, 0, 0, v6notv9
}, /* wr %g0,rs2,%psr */
1021 { "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0
|RS1_G0
, "i,p", F_ALIAS
, 0, 0, v6notv9
}, /* wr %g0,i,%psr */
1022 { "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0
|RS1_G0
|ASI(~0), "2,w", F_ALIAS
, 0, 0, v6notv9
}, /* wr %g0,rs2,%wim */
1023 { "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0
|RS1_G0
, "i,w", F_ALIAS
, 0, 0, v6notv9
}, /* wr %g0,i,%wim */
1024 { "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0
|RS1_G0
|ASI(~0), "2,t", F_ALIAS
, 0, 0, v6notv9
}, /* wr %g0,rs2,%tbr */
1025 { "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0
|RS1_G0
, "i,t", F_ALIAS
, 0, 0, v6notv9
}, /* wr %g0,i,%tbr */
1027 { "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0
|ASI(~0), "2,d", 0, 0, 0, v6
}, /* or %g0,rs2,d */
1028 { "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0
, "i,d", 0, 0, 0, v6
}, /* or %g0,i,d */
1029 { "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0), "1,d", 0, 0, 0, v6
}, /* or rs1,%g0,d */
1030 { "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0), "1,d", 0, 0, 0, v6
}, /* or rs1,0,d */
1032 { "or", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1033 { "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "1,i,d", 0, 0, 0, v6
},
1034 { "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,1,d", 0, 0, 0, v6
},
1036 { "bset", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "2,r", F_ALIAS
, 0, 0, v6
}, /* or rd,rs2,rd */
1037 { "bset", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,r", F_ALIAS
, 0, 0, v6
}, /* or rd,i,rd */
1039 /* This is not a commutative instruction. */
1040 { "andn", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1041 { "andn", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "1,i,d", 0, 0, 0, v6
},
1043 /* This is not a commutative instruction. */
1044 { "andncc", F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1045 { "andncc", F3(2, 0x15, 1), F3(~2, ~0x15, ~1), "1,i,d", 0, 0, 0, v6
},
1047 { "bclr", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "2,r", F_ALIAS
, 0, 0, v6
}, /* andn rd,rs2,rd */
1048 { "bclr", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "i,r", F_ALIAS
, 0, 0, v6
}, /* andn rd,i,rd */
1050 { "cmp", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0
|ASI(~0), "1,2", 0, 0, 0, v6
}, /* subcc rs1,rs2,%g0 */
1051 { "cmp", F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0
, "1,i", 0, 0, 0, v6
}, /* subcc rs1,i,%g0 */
1053 { "sub", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1054 { "sub", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "1,i,d", 0, 0, 0, v6
},
1056 { "subcc", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1057 { "subcc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "1,i,d", 0, 0, 0, v6
},
1059 { "subx", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6notv9
},
1060 { "subx", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, 0, 0, v6notv9
},
1061 { "subc", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9
},
1062 { "subc", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, 0, 0, v9
},
1064 { "subxcc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6notv9
},
1065 { "subxcc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, 0, 0, v6notv9
},
1066 { "subccc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9
},
1067 { "subccc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, 0, 0, v9
},
1069 { "and", F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1070 { "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "1,i,d", 0, 0, 0, v6
},
1071 { "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "i,1,d", 0, 0, 0, v6
},
1073 { "andcc", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1074 { "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "1,i,d", 0, 0, 0, v6
},
1075 { "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "i,1,d", 0, 0, 0, v6
},
1077 { "dec", F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS
, 0, 0, v6
}, /* sub rd,1,rd */
1078 { "dec", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "i,r", F_ALIAS
, 0, 0, v8
}, /* sub rd,imm,rd */
1079 { "deccc", F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS
, 0, 0, v6
}, /* subcc rd,1,rd */
1080 { "deccc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "i,r", F_ALIAS
, 0, 0, v8
}, /* subcc rd,imm,rd */
1081 { "inc", F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS
, 0, 0, v6
}, /* add rd,1,rd */
1082 { "inc", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,r", F_ALIAS
, 0, 0, v8
}, /* add rd,imm,rd */
1083 { "inccc", F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS
, 0, 0, v6
}, /* addcc rd,1,rd */
1084 { "inccc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,r", F_ALIAS
, 0, 0, v8
}, /* addcc rd,imm,rd */
1086 { "btst", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0
|ASI(~0), "1,2", F_ALIAS
, 0, 0, v6
}, /* andcc rs1,rs2,%g0 */
1087 { "btst", F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0
, "i,1", F_ALIAS
, 0, 0, v6
}, /* andcc rs1,i,%g0 */
1089 { "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0
|ASI(~0), "2,d", F_ALIAS
, 0, 0, v6
}, /* sub %g0,rs2,rd */
1090 { "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0
|ASI(~0), "O", F_ALIAS
, 0, 0, v6
}, /* sub %g0,rd,rd */
1092 { "add", F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1093 { "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "1,i,d", 0, 0, 0, v6
},
1094 { "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,1,d", 0, 0, 0, v6
},
1095 { "addcc", F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1096 { "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "1,i,d", 0, 0, 0, v6
},
1097 { "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,1,d", 0, 0, 0, v6
},
1099 { "addx", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6notv9
},
1100 { "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, 0, 0, v6notv9
},
1101 { "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, 0, 0, v6notv9
},
1102 { "addc", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9
},
1103 { "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, 0, 0, v9
},
1104 { "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, 0, 0, v9
},
1106 { "addxcc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6notv9
},
1107 { "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, 0, 0, v6notv9
},
1108 { "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, 0, 0, v6notv9
},
1109 { "addccc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9
},
1110 { "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, 0, 0, v9
},
1111 { "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, 0, 0, v9
},
1113 { "smul", F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0), "1,2,d", 0, HWCAP_MUL32
, 0, v8
},
1114 { "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "1,i,d", 0, HWCAP_MUL32
, 0, v8
},
1115 { "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "i,1,d", 0, HWCAP_MUL32
, 0, v8
},
1116 { "smulcc", F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0), "1,2,d", 0, HWCAP_MUL32
, 0, v8
},
1117 { "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "1,i,d", 0, HWCAP_MUL32
, 0, v8
},
1118 { "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "i,1,d", 0, HWCAP_MUL32
, 0, v8
},
1119 { "umul", F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0), "1,2,d", 0, HWCAP_MUL32
, 0, v8
},
1120 { "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "1,i,d", 0, HWCAP_MUL32
, 0, v8
},
1121 { "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "i,1,d", 0, HWCAP_MUL32
, 0, v8
},
1122 { "umulcc", F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0), "1,2,d", 0, HWCAP_MUL32
, 0, v8
},
1123 { "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "1,i,d", 0, HWCAP_MUL32
, 0, v8
},
1124 { "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "i,1,d", 0, HWCAP_MUL32
, 0, v8
},
1125 { "sdiv", F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0), "1,2,d", 0, HWCAP_DIV32
, 0, v8
},
1126 { "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "1,i,d", 0, HWCAP_DIV32
, 0, v8
},
1127 { "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "i,1,d", 0, HWCAP_DIV32
, 0, v8
},
1128 { "sdivcc", F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0), "1,2,d", 0, HWCAP_DIV32
, 0, v8
},
1129 { "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "1,i,d", 0, HWCAP_DIV32
, 0, v8
},
1130 { "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "i,1,d", 0, HWCAP_DIV32
, 0, v8
},
1131 { "udiv", F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0), "1,2,d", 0, HWCAP_DIV32
, 0, v8
},
1132 { "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "1,i,d", 0, HWCAP_DIV32
, 0, v8
},
1133 { "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "i,1,d", 0, HWCAP_DIV32
, 0, v8
},
1134 { "udivcc", F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0), "1,2,d", 0, HWCAP_DIV32
, 0, v8
},
1135 { "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "1,i,d", 0, HWCAP_DIV32
, 0, v8
},
1136 { "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "i,1,d", 0, HWCAP_DIV32
, 0, v8
},
1138 { "mulx", F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9
},
1139 { "mulx", F3(2, 0x09, 1), F3(~2, ~0x09, ~1), "1,i,d", 0, 0, 0, v9
},
1140 { "sdivx", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9
},
1141 { "sdivx", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, 0, 0, v9
},
1142 { "udivx", F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9
},
1143 { "udivx", F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1), "1,i,d", 0, 0, 0, v9
},
1145 { "call", F1(0x1), F1(~0x1), "L", F_JSR
|F_DELAYED
, 0, 0, v6
},
1146 { "call", F1(0x1), F1(~0x1), "L,#", F_JSR
|F_DELAYED
, 0, 0, v6
},
1148 { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2", F_JSR
|F_DELAYED
, 0, 0, v6
}, /* jmpl rs1+rs2,%o7 */
1149 { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2,#", F_JSR
|F_DELAYED
, 0, 0, v6
},
1150 { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1", F_JSR
|F_DELAYED
, 0, 0, v6
}, /* jmpl rs1+%g0,%o7 */
1151 { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1,#", F_JSR
|F_DELAYED
, 0, 0, v6
},
1152 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i", F_JSR
|F_DELAYED
, 0, 0, v6
}, /* jmpl rs1+i,%o7 */
1153 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i,#", F_JSR
|F_DELAYED
, 0, 0, v6
},
1154 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1", F_JSR
|F_DELAYED
, 0, 0, v6
}, /* jmpl i+rs1,%o7 */
1155 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1,#", F_JSR
|F_DELAYED
, 0, 0, v6
},
1156 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0
, "i", F_JSR
|F_DELAYED
, 0, 0, v6
}, /* jmpl %g0+i,%o7 */
1157 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0
, "i,#", F_JSR
|F_DELAYED
, 0, 0, v6
},
1158 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1", F_JSR
|F_DELAYED
, 0, 0, v6
}, /* jmpl rs1+0,%o7 */
1159 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1,#", F_JSR
|F_DELAYED
, 0, 0, v6
},
1161 /* Conditional instructions.
1163 Because this part of the table was such a mess earlier, I have
1164 macrofied it so that all the branches and traps are generated from
1165 a single-line description of each condition value. John Gilmore. */
1167 /* Define branches -- one annulled, one without, etc. */
1168 #define br(opcode, mask, lose, flags) \
1169 { opcode, (mask)|ANNUL, (lose), ",a l", (flags), 0, 0, v6 }, \
1170 { opcode, (mask) , (lose)|ANNUL, "l", (flags), 0, 0, v6 }
1172 #define brx(opcode, mask, lose, flags) /* v9 */ \
1173 { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), "Z,G", (flags), 0, 0, v9 }, \
1174 { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), ",T Z,G", (flags), 0, 0, v9 }, \
1175 { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a Z,G", (flags), 0, 0, v9 }, \
1176 { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a,T Z,G", (flags), 0, 0, v9 }, \
1177 { opcode, (mask)|(2<<20), ANNUL|BPRED|(lose), ",N Z,G", (flags), 0, 0, v9 }, \
1178 { opcode, (mask)|(2<<20)|ANNUL, BPRED|(lose), ",a,N Z,G", (flags), 0, 0, v9 }, \
1179 { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), "z,G", (flags), 0, 0, v9 }, \
1180 { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), ",T z,G", (flags), 0, 0, v9 }, \
1181 { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a z,G", (flags), 0, 0, v9 }, \
1182 { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a,T z,G", (flags), 0, 0, v9 }, \
1183 { opcode, (mask), ANNUL|BPRED|(lose)|(2<<20), ",N z,G", (flags), 0, 0, v9 }, \
1184 { opcode, (mask)|ANNUL, BPRED|(lose)|(2<<20), ",a,N z,G", (flags), 0, 0, v9 }
1186 /* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */
1187 #define tr(opcode, mask, lose, flags) \
1188 { opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0, "Z,i", (flags), 0, 0, v9 }, /* %g0 + imm */ \
1189 { opcode, (mask)|(2<<11)|IMMED, (lose), "Z,1+i", (flags), 0, 0, v9 }, /* rs1 + imm */ \
1190 { opcode, (mask)|(2<<11), IMMED|(lose), "Z,1+2", (flags), 0, 0, v9 }, /* rs1 + rs2 */ \
1191 { opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0, "Z,1", (flags), 0, 0, v9 }, /* rs1 + %g0 */ \
1192 { opcode, (mask)|IMMED, (lose)|RS1_G0, "z,i", (flags)|F_ALIAS, 0, 0, v9 }, /* %g0 + imm */ \
1193 { opcode, (mask)|IMMED, (lose), "z,1+i", (flags)|F_ALIAS, 0, 0, v9 }, /* rs1 + imm */ \
1194 { opcode, (mask), IMMED|(lose), "z,1+2", (flags)|F_ALIAS, 0, 0, v9 }, /* rs1 + rs2 */ \
1195 { opcode, (mask), IMMED|(lose)|RS2_G0, "z,1", (flags)|F_ALIAS, 0, 0, v9 }, /* rs1 + %g0 */ \
1196 { opcode, (mask)|IMMED, (lose)|RS1_G0, "i", (flags), 0, 0, v6 }, /* %g0 + imm */ \
1197 { opcode, (mask)|IMMED, (lose), "1+i", (flags), 0, 0, v6 }, /* rs1 + imm */ \
1198 { opcode, (mask)|IMMED, (lose), "i+1", (flags), 0, 0, v6 }, /* imm + rs1 */ \
1199 { opcode, (mask), IMMED|(lose), "1+2", (flags), 0, 0, v6 }, /* rs1 + rs2 */ \
1200 { opcode, (mask), IMMED|(lose)|RS2_G0, "1", (flags), 0, 0, v6 } /* rs1 + %g0 */
1202 /* v9: We must put `brx' before `br', to ensure that we never match something
1203 v9: against an expression unless it is an expression. Otherwise, we end
1204 v9: up with undefined symbol tables entries, because they get added, but
1205 v9: are not deleted if the pattern fails to match. */
1207 /* Define both branches and traps based on condition mask */
1208 #define cond(bop, top, mask, flags) \
1209 brx(bop, F2(0, 1)|(mask), F2(~0, ~1)|((~mask)&COND(~0)), F_DELAYED|(flags)), /* v9 */ \
1210 br(bop, F2(0, 2)|(mask), F2(~0, ~2)|((~mask)&COND(~0)), F_DELAYED|(flags)), \
1211 tr(top, F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)), ((flags) & ~(F_UNBR|F_CONDBR)))
1213 /* Define all the conditions, all the branches, all the traps. */
1215 /* Standard branch, trap mnemonics */
1216 cond ("b", "ta", CONDA
, F_UNBR
),
1217 /* Alternative form (just for assembly, not for disassembly) */
1218 cond ("ba", "t", CONDA
, F_UNBR
|F_ALIAS
),
1220 cond ("bcc", "tcc", CONDCC
, F_CONDBR
),
1221 cond ("bcs", "tcs", CONDCS
, F_CONDBR
),
1222 cond ("be", "te", CONDE
, F_CONDBR
),
1223 cond ("beq", "teq", CONDE
, F_CONDBR
|F_ALIAS
),
1224 cond ("bg", "tg", CONDG
, F_CONDBR
),
1225 cond ("bgt", "tgt", CONDG
, F_CONDBR
|F_ALIAS
),
1226 cond ("bge", "tge", CONDGE
, F_CONDBR
),
1227 cond ("bgeu", "tgeu", CONDGEU
, F_CONDBR
|F_ALIAS
), /* for cc */
1228 cond ("bgu", "tgu", CONDGU
, F_CONDBR
),
1229 cond ("bl", "tl", CONDL
, F_CONDBR
),
1230 cond ("blt", "tlt", CONDL
, F_CONDBR
|F_ALIAS
),
1231 cond ("ble", "tle", CONDLE
, F_CONDBR
),
1232 cond ("bleu", "tleu", CONDLEU
, F_CONDBR
),
1233 cond ("blu", "tlu", CONDLU
, F_CONDBR
|F_ALIAS
), /* for cs */
1234 cond ("bn", "tn", CONDN
, F_CONDBR
),
1235 cond ("bne", "tne", CONDNE
, F_CONDBR
),
1236 cond ("bneg", "tneg", CONDNEG
, F_CONDBR
),
1237 cond ("bnz", "tnz", CONDNZ
, F_CONDBR
|F_ALIAS
), /* for ne */
1238 cond ("bpos", "tpos", CONDPOS
, F_CONDBR
),
1239 cond ("bvc", "tvc", CONDVC
, F_CONDBR
),
1240 cond ("bvs", "tvs", CONDVS
, F_CONDBR
),
1241 cond ("bz", "tz", CONDZ
, F_CONDBR
|F_ALIAS
), /* for e */
1248 #define brr(opcode, mask, lose, flags) /* v9 */ \
1249 { opcode, (mask)|BPRED, ANNUL|(lose), "1,k", F_DELAYED|(flags), 0, 0, v9 }, \
1250 { opcode, (mask)|BPRED, ANNUL|(lose), ",T 1,k", F_DELAYED|(flags), 0, 0, v9 }, \
1251 { opcode, (mask)|BPRED|ANNUL, (lose), ",a 1,k", F_DELAYED|(flags), 0, 0, v9 }, \
1252 { opcode, (mask)|BPRED|ANNUL, (lose), ",a,T 1,k", F_DELAYED|(flags), 0, 0, v9 }, \
1253 { opcode, (mask), ANNUL|BPRED|(lose), ",N 1,k", F_DELAYED|(flags), 0, 0, v9 }, \
1254 { opcode, (mask)|ANNUL, BPRED|(lose), ",a,N 1,k", F_DELAYED|(flags), 0, 0, v9 }
1256 #define condr(bop, mask, flags) /* v9 */ \
1257 brr(bop, F2(0, 3)|COND(mask), F2(~0, ~3)|COND(~(mask)), (flags)) /* v9 */
1259 /* v9 */ condr("brnz", 0x5, F_CONDBR
),
1260 /* v9 */ condr("brz", 0x1, F_CONDBR
),
1261 /* v9 */ condr("brgez", 0x7, F_CONDBR
),
1262 /* v9 */ condr("brlz", 0x3, F_CONDBR
),
1263 /* v9 */ condr("brlez", 0x2, F_CONDBR
),
1264 /* v9 */ condr("brgz", 0x6, F_CONDBR
),
1266 #define cbcond(cop, cmask, flgs) \
1267 { "cw" cop, F2(0, 3)|CBCOND(cmask)|F3I(0),F2(~0,~3)|CBCOND(~(cmask))|F3I(~0)|CBCOND_XCC, \
1268 "1,2,=", flgs, HWCAP_CBCOND, 0, v9}, \
1269 { "cw" cop, F2(0, 3)|CBCOND(cmask)|F3I(1),F2(~0,~3)|CBCOND(~(cmask))|F3I(~1)|CBCOND_XCC, \
1270 "1,X,=", flgs, HWCAP_CBCOND, 0, v9}, \
1271 { "cx" cop, F2(0, 3)|CBCOND(cmask)|F3I(0)|CBCOND_XCC,F2(~0,~3)|CBCOND(~(cmask))|F3I(~0), \
1272 "1,2,=", flgs, HWCAP_CBCOND, 0, v9}, \
1273 { "cx" cop, F2(0, 3)|CBCOND(cmask)|F3I(1)|CBCOND_XCC,F2(~0,~3)|CBCOND(~(cmask))|F3I(~1), \
1274 "1,X,=", flgs, HWCAP_CBCOND, 0, v9},
1276 cbcond("be", 0x09, F_CONDBR
)
1277 cbcond("bz", 0x09, F_CONDBR
|F_ALIAS
)
1278 cbcond("ble", 0x0a, F_CONDBR
)
1279 cbcond("bl", 0x0b, F_CONDBR
)
1280 cbcond("bleu", 0x0c, F_CONDBR
)
1281 cbcond("bcs", 0x0d, F_CONDBR
)
1282 cbcond("blu", 0x0d, F_CONDBR
|F_ALIAS
)
1283 cbcond("bneg", 0x0e, F_CONDBR
)
1284 cbcond("bvs", 0x0f, F_CONDBR
)
1285 cbcond("bne", 0x19, F_CONDBR
)
1286 cbcond("bnz", 0x19, F_CONDBR
|F_ALIAS
)
1287 cbcond("bg", 0x1a, F_CONDBR
)
1288 cbcond("bge", 0x1b, F_CONDBR
)
1289 cbcond("bgu", 0x1c, F_CONDBR
)
1290 cbcond("bcc", 0x1d, F_CONDBR
)
1291 cbcond("bgeu", 0x1d, F_CONDBR
|F_ALIAS
)
1292 cbcond("bpos", 0x1e, F_CONDBR
)
1293 cbcond("bvc", 0x1f, F_CONDBR
)
1296 #undef condr /* v9 */
1299 #define movr(opcode, mask, flags) /* v9 */ \
1300 { opcode, F3(2, 0x2f, 0)|RCOND(mask), F3(~2, ~0x2f, ~0)|RCOND(~(mask)), "1,2,d", (flags), 0, 0, v9 }, \
1301 { opcode, F3(2, 0x2f, 1)|RCOND(mask), F3(~2, ~0x2f, ~1)|RCOND(~(mask)), "1,j,d", (flags), 0, 0, v9 }
1303 #define fmrrs(opcode, mask, lose, flags) /* v9 */ \
1304 { opcode, (mask), (lose), "1,f,g", (flags) | F_FLOAT, 0, 0, v9 }
1305 #define fmrrd(opcode, mask, lose, flags) /* v9 */ \
1306 { opcode, (mask), (lose), "1,B,H", (flags) | F_FLOAT, 0, 0, v9 }
1307 #define fmrrq(opcode, mask, lose, flags) /* v9 */ \
1308 { opcode, (mask), (lose), "1,R,J", (flags) | F_FLOAT, 0, 0, v9 }
1310 #define fmovrs(mop, mask, flags) /* v9 */ \
1311 fmrrs(mop, F3(2, 0x35, 0)|OPF_LOW5(5)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~5)|RCOND(~(mask)), (flags)) /* v9 */
1312 #define fmovrd(mop, mask, flags) /* v9 */ \
1313 fmrrd(mop, F3(2, 0x35, 0)|OPF_LOW5(6)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~6)|RCOND(~(mask)), (flags)) /* v9 */
1314 #define fmovrq(mop, mask, flags) /* v9 */ \
1315 fmrrq(mop, F3(2, 0x35, 0)|OPF_LOW5(7)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~7)|RCOND(~(mask)), (flags)) /* v9 */
1317 /* v9 */ movr("movrne", 0x5, 0),
1318 /* v9 */ movr("movre", 0x1, 0),
1319 /* v9 */ movr("movrgez", 0x7, 0),
1320 /* v9 */ movr("movrlz", 0x3, 0),
1321 /* v9 */ movr("movrlez", 0x2, 0),
1322 /* v9 */ movr("movrgz", 0x6, 0),
1323 /* v9 */ movr("movrnz", 0x5, F_ALIAS
),
1324 /* v9 */ movr("movrz", 0x1, F_ALIAS
),
1326 /* v9 */ fmovrs("fmovrsne", 0x5, 0),
1327 /* v9 */ fmovrs("fmovrse", 0x1, 0),
1328 /* v9 */ fmovrs("fmovrsgez", 0x7, 0),
1329 /* v9 */ fmovrs("fmovrslz", 0x3, 0),
1330 /* v9 */ fmovrs("fmovrslez", 0x2, 0),
1331 /* v9 */ fmovrs("fmovrsgz", 0x6, 0),
1332 /* v9 */ fmovrs("fmovrsnz", 0x5, F_ALIAS
),
1333 /* v9 */ fmovrs("fmovrsz", 0x1, F_ALIAS
),
1335 /* v9 */ fmovrd("fmovrdne", 0x5, 0),
1336 /* v9 */ fmovrd("fmovrde", 0x1, 0),
1337 /* v9 */ fmovrd("fmovrdgez", 0x7, 0),
1338 /* v9 */ fmovrd("fmovrdlz", 0x3, 0),
1339 /* v9 */ fmovrd("fmovrdlez", 0x2, 0),
1340 /* v9 */ fmovrd("fmovrdgz", 0x6, 0),
1341 /* v9 */ fmovrd("fmovrdnz", 0x5, F_ALIAS
),
1342 /* v9 */ fmovrd("fmovrdz", 0x1, F_ALIAS
),
1344 /* v9 */ fmovrq("fmovrqne", 0x5, 0),
1345 /* v9 */ fmovrq("fmovrqe", 0x1, 0),
1346 /* v9 */ fmovrq("fmovrqgez", 0x7, 0),
1347 /* v9 */ fmovrq("fmovrqlz", 0x3, 0),
1348 /* v9 */ fmovrq("fmovrqlez", 0x2, 0),
1349 /* v9 */ fmovrq("fmovrqgz", 0x6, 0),
1350 /* v9 */ fmovrq("fmovrqnz", 0x5, F_ALIAS
),
1351 /* v9 */ fmovrq("fmovrqz", 0x1, F_ALIAS
),
1353 #undef movr /* v9 */
1354 #undef fmovr /* v9 */
1355 #undef fmrr /* v9 */
1357 #define movicc(opcode, cond, flags) /* v9 */ \
1358 { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|XCC|(1<<11), "z,2,d", flags, 0, 0, v9 }, \
1359 { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|XCC|(1<<11), "z,I,d", flags, 0, 0, v9 }, \
1360 { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|(1<<11), "Z,2,d", flags, 0, 0, v9 }, \
1361 { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|(1<<11), "Z,I,d", flags, 0, 0, v9 }
1363 #define movfcc(opcode, fcond, flags) /* v9 */ \
1364 { opcode, F3(2, 0x2c, 0)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~0), "6,2,d", flags, 0, 0, v9 }, \
1365 { opcode, F3(2, 0x2c, 1)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~1), "6,I,d", flags, 0, 0, v9 }, \
1366 { opcode, F3(2, 0x2c, 0)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~0), "7,2,d", flags, 0, 0, v9 }, \
1367 { opcode, F3(2, 0x2c, 1)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~1), "7,I,d", flags, 0, 0, v9 }, \
1368 { opcode, F3(2, 0x2c, 0)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~0), "8,2,d", flags, 0, 0, v9 }, \
1369 { opcode, F3(2, 0x2c, 1)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~1), "8,I,d", flags, 0, 0, v9 }, \
1370 { opcode, F3(2, 0x2c, 0)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~0), "9,2,d", flags, 0, 0, v9 }, \
1371 { opcode, F3(2, 0x2c, 1)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~1), "9,I,d", flags, 0, 0, v9 }
1373 #define movcc(opcode, cond, fcond, flags) /* v9 */ \
1374 movfcc (opcode, fcond, flags), /* v9 */ \
1375 movicc (opcode, cond, flags) /* v9 */
1377 /* v9 */ movcc ("mova", CONDA
, FCONDA
, 0),
1378 /* v9 */ movicc ("movcc", CONDCC
, 0),
1379 /* v9 */ movicc ("movgeu", CONDGEU
, F_ALIAS
),
1380 /* v9 */ movicc ("movcs", CONDCS
, 0),
1381 /* v9 */ movicc ("movlu", CONDLU
, F_ALIAS
),
1382 /* v9 */ movcc ("move", CONDE
, FCONDE
, 0),
1383 /* v9 */ movcc ("movg", CONDG
, FCONDG
, 0),
1384 /* v9 */ movcc ("movge", CONDGE
, FCONDGE
, 0),
1385 /* v9 */ movicc ("movgu", CONDGU
, 0),
1386 /* v9 */ movcc ("movl", CONDL
, FCONDL
, 0),
1387 /* v9 */ movcc ("movle", CONDLE
, FCONDLE
, 0),
1388 /* v9 */ movicc ("movleu", CONDLEU
, 0),
1389 /* v9 */ movfcc ("movlg", FCONDLG
, 0),
1390 /* v9 */ movcc ("movn", CONDN
, FCONDN
, 0),
1391 /* v9 */ movcc ("movne", CONDNE
, FCONDNE
, 0),
1392 /* v9 */ movicc ("movneg", CONDNEG
, 0),
1393 /* v9 */ movcc ("movnz", CONDNZ
, FCONDNZ
, F_ALIAS
),
1394 /* v9 */ movfcc ("movo", FCONDO
, 0),
1395 /* v9 */ movicc ("movpos", CONDPOS
, 0),
1396 /* v9 */ movfcc ("movu", FCONDU
, 0),
1397 /* v9 */ movfcc ("movue", FCONDUE
, 0),
1398 /* v9 */ movfcc ("movug", FCONDUG
, 0),
1399 /* v9 */ movfcc ("movuge", FCONDUGE
, 0),
1400 /* v9 */ movfcc ("movul", FCONDUL
, 0),
1401 /* v9 */ movfcc ("movule", FCONDULE
, 0),
1402 /* v9 */ movicc ("movvc", CONDVC
, 0),
1403 /* v9 */ movicc ("movvs", CONDVS
, 0),
1404 /* v9 */ movcc ("movz", CONDZ
, FCONDZ
, F_ALIAS
),
1406 #undef movicc /* v9 */
1407 #undef movfcc /* v9 */
1408 #undef movcc /* v9 */
1410 #define FM_SF 1 /* v9 - values for fpsize */
1411 #define FM_DF 2 /* v9 */
1412 #define FM_QF 3 /* v9 */
1414 #define fmoviccx(opcode, fpsize, args, cond, flags) /* v9 */ \
1415 { opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags, 0, 0, v9 }, \
1416 { opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags, 0, 0, v9 }
1418 #define fmovfccx(opcode, fpsize, args, fcond, flags) /* v9 */ \
1419 { opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags, 0, 0, v9 }, \
1420 { opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags, 0, 0, v9 }, \
1421 { opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags, 0, 0, v9 }, \
1422 { opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags, 0, 0, v9 }
1424 /* FIXME: use fmovicc/fmovfcc? */ /* v9 */
1425 #define fmovccx(opcode, fpsize, args, cond, fcond, flags) /* v9 */ \
1426 { opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags | F_FLOAT, 0, 0, v9 }, \
1427 { opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags | F_FLOAT, 0, 0, v9 }, \
1428 { opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags | F_FLOAT, 0, 0, v9 }, \
1429 { opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags | F_FLOAT, 0, 0, v9 }, \
1430 { opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags | F_FLOAT, 0, 0, v9 }, \
1431 { opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags | F_FLOAT, 0, 0, v9 }
1433 #define fmovicc(suffix, cond, flags) /* v9 */ \
1434 fmoviccx("fmovd" suffix, FM_DF, "B,H", cond, flags), \
1435 fmoviccx("fmovq" suffix, FM_QF, "R,J", cond, flags), \
1436 fmoviccx("fmovs" suffix, FM_SF, "f,g", cond, flags)
1438 #define fmovfcc(suffix, fcond, flags) /* v9 */ \
1439 fmovfccx("fmovd" suffix, FM_DF, "B,H", fcond, flags), \
1440 fmovfccx("fmovq" suffix, FM_QF, "R,J", fcond, flags), \
1441 fmovfccx("fmovs" suffix, FM_SF, "f,g", fcond, flags)
1443 #define fmovcc(suffix, cond, fcond, flags) /* v9 */ \
1444 fmovccx("fmovd" suffix, FM_DF, "B,H", cond, fcond, flags), \
1445 fmovccx("fmovq" suffix, FM_QF, "R,J", cond, fcond, flags), \
1446 fmovccx("fmovs" suffix, FM_SF, "f,g", cond, fcond, flags)
1448 /* v9 */ fmovcc ("a", CONDA
, FCONDA
, 0),
1449 /* v9 */ fmovicc ("cc", CONDCC
, 0),
1450 /* v9 */ fmovicc ("cs", CONDCS
, 0),
1451 /* v9 */ fmovcc ("e", CONDE
, FCONDE
, 0),
1452 /* v9 */ fmovcc ("g", CONDG
, FCONDG
, 0),
1453 /* v9 */ fmovcc ("ge", CONDGE
, FCONDGE
, 0),
1454 /* v9 */ fmovicc ("geu", CONDGEU
, F_ALIAS
),
1455 /* v9 */ fmovicc ("gu", CONDGU
, 0),
1456 /* v9 */ fmovcc ("l", CONDL
, FCONDL
, 0),
1457 /* v9 */ fmovcc ("le", CONDLE
, FCONDLE
, 0),
1458 /* v9 */ fmovicc ("leu", CONDLEU
, 0),
1459 /* v9 */ fmovfcc ("lg", FCONDLG
, 0),
1460 /* v9 */ fmovicc ("lu", CONDLU
, F_ALIAS
),
1461 /* v9 */ fmovcc ("n", CONDN
, FCONDN
, 0),
1462 /* v9 */ fmovcc ("ne", CONDNE
, FCONDNE
, 0),
1463 /* v9 */ fmovicc ("neg", CONDNEG
, 0),
1464 /* v9 */ fmovcc ("nz", CONDNZ
, FCONDNZ
, F_ALIAS
),
1465 /* v9 */ fmovfcc ("o", FCONDO
, 0),
1466 /* v9 */ fmovicc ("pos", CONDPOS
, 0),
1467 /* v9 */ fmovfcc ("u", FCONDU
, 0),
1468 /* v9 */ fmovfcc ("ue", FCONDUE
, 0),
1469 /* v9 */ fmovfcc ("ug", FCONDUG
, 0),
1470 /* v9 */ fmovfcc ("uge", FCONDUGE
, 0),
1471 /* v9 */ fmovfcc ("ul", FCONDUL
, 0),
1472 /* v9 */ fmovfcc ("ule", FCONDULE
, 0),
1473 /* v9 */ fmovicc ("vc", CONDVC
, 0),
1474 /* v9 */ fmovicc ("vs", CONDVS
, 0),
1475 /* v9 */ fmovcc ("z", CONDZ
, FCONDZ
, F_ALIAS
),
1477 #undef fmoviccx /* v9 */
1478 #undef fmovfccx /* v9 */
1479 #undef fmovccx /* v9 */
1480 #undef fmovicc /* v9 */
1481 #undef fmovfcc /* v9 */
1482 #undef fmovcc /* v9 */
1483 #undef FM_DF /* v9 */
1484 #undef FM_QF /* v9 */
1485 #undef FM_SF /* v9 */
1487 /* Coprocessor branches. */
1488 #define CBR(opcode, mask, lose, flags, arch) \
1489 { opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED, 0, 0, arch }, \
1490 { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED, 0, 0, arch }
1492 /* Floating point branches. */
1493 #define FBR(opcode, mask, lose, flags) \
1494 { opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED | F_FBR, 0, 0, v6 }, \
1495 { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED | F_FBR, 0, 0, v6 }
1497 /* V9 extended floating point branches. */
1498 #define FBRX(opcode, mask, lose, flags) /* v9 */ \
1499 { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), "6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1500 { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1501 { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a 6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1502 { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a,T 6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1503 { opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), ",N 6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1504 { opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a,N 6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1505 { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), "7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1506 { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), ",T 7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1507 { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a 7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1508 { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a,T 7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1509 { opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), ",N 7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1510 { opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a,N 7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1511 { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), "8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1512 { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), ",T 8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1513 { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a 8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1514 { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a,T 8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1515 { opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), ",N 8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1516 { opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a,N 8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1517 { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), "9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1518 { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), ",T 9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1519 { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a 9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1520 { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a,T 9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1521 { opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N 9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1522 { opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }
1524 /* v9: We must put `FBRX' before `FBR', to ensure that we never match
1525 v9: something against an expression unless it is an expression. Otherwise,
1526 v9: we end up with undefined symbol tables entries, because they get added,
1527 v9: but are not deleted if the pattern fails to match. */
1529 #define CONDFC(fop, cop, mask, flags) \
1530 FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
1531 FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
1532 CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6notlet)
1534 #define CONDFCL(fop, cop, mask, flags) \
1535 FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
1536 FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
1537 CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6)
1539 #define CONDF(fop, mask, flags) \
1540 FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
1541 FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags)
1543 CONDFC ("fb", "cb", 0x8, F_UNBR
),
1544 CONDFCL ("fba", "cba", 0x8, F_UNBR
|F_ALIAS
),
1545 CONDFC ("fbe", "cb0", 0x9, F_CONDBR
),
1546 CONDF ("fbz", 0x9, F_CONDBR
|F_ALIAS
),
1547 CONDFC ("fbg", "cb2", 0x6, F_CONDBR
),
1548 CONDFC ("fbge", "cb02", 0xb, F_CONDBR
),
1549 CONDFC ("fbl", "cb1", 0x4, F_CONDBR
),
1550 CONDFC ("fble", "cb01", 0xd, F_CONDBR
),
1551 CONDFC ("fblg", "cb12", 0x2, F_CONDBR
),
1552 CONDFCL ("fbn", "cbn", 0x0, F_UNBR
),
1553 CONDFC ("fbne", "cb123", 0x1, F_CONDBR
),
1554 CONDF ("fbnz", 0x1, F_CONDBR
|F_ALIAS
),
1555 CONDFC ("fbo", "cb012", 0xf, F_CONDBR
),
1556 CONDFC ("fbu", "cb3", 0x7, F_CONDBR
),
1557 CONDFC ("fbue", "cb03", 0xa, F_CONDBR
),
1558 CONDFC ("fbug", "cb23", 0x5, F_CONDBR
),
1559 CONDFC ("fbuge", "cb023", 0xc, F_CONDBR
),
1560 CONDFC ("fbul", "cb13", 0x3, F_CONDBR
),
1561 CONDFC ("fbule", "cb013", 0xe, F_CONDBR
),
1568 #undef FBRX /* v9 */
1570 { "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0
|ASI(~0), "1+2", F_UNBR
|F_DELAYED
, 0, 0, v6
}, /* jmpl rs1+rs2,%g0 */
1571 { "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0
|ASI_RS2(~0), "1", F_UNBR
|F_DELAYED
, 0, 0, v6
}, /* jmpl rs1+%g0,%g0 */
1572 { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0
, "1+i", F_UNBR
|F_DELAYED
, 0, 0, v6
}, /* jmpl rs1+i,%g0 */
1573 { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0
, "i+1", F_UNBR
|F_DELAYED
, 0, 0, v6
}, /* jmpl i+rs1,%g0 */
1574 { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0
|RS1_G0
, "i", F_UNBR
|F_DELAYED
, 0, 0, v6
}, /* jmpl %g0+i,%g0 */
1575 { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0
|SIMM13(~0), "1", F_UNBR
|F_DELAYED
, 0, 0, v6
}, /* jmpl rs1+0,%g0 */
1577 { "nop", F2(0, 4), 0xfeffffff, "", 0, 0, 0, v6
}, /* sethi 0, %g0 */
1579 { "set", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS
, 0, 0, v6
},
1580 { "setuw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS
, 0, 0, v9
},
1581 { "setsw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS
, 0, 0, v9
},
1582 { "setx", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS
, 0, 0, v9
},
1584 { "sethi", F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, 0, 0, v6
},
1586 { "taddcc", F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1587 { "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "1,i,d", 0, 0, 0, v6
},
1588 { "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "i,1,d", 0, 0, 0, v6
},
1589 { "taddcctv", F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1590 { "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "1,i,d", 0, 0, 0, v6
},
1591 { "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "i,1,d", 0, 0, 0, v6
},
1593 { "tsubcc", F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1594 { "tsubcc", F3(2, 0x21, 1), F3(~2, ~0x21, ~1), "1,i,d", 0, 0, 0, v6
},
1595 { "tsubcctv", F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1596 { "tsubcctv", F3(2, 0x23, 1), F3(~2, ~0x23, ~1), "1,i,d", 0, 0, 0, v6
},
1598 { "unimp", F2(0x0, 0x0), 0xffc00000, "n", 0, 0, 0, v6notv9
},
1599 { "illtrap", F2(0, 0), F2(~0, ~0)|RD_G0
, "n", 0, 0, 0, v9
},
1601 /* This *is* a commutative instruction. */
1602 { "xnor", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1603 { "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "1,i,d", 0, 0, 0, v6
},
1604 { "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "i,1,d", 0, 0, 0, v6
},
1605 /* This *is* a commutative instruction. */
1606 { "xnorcc", F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1607 { "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "1,i,d", 0, 0, 0, v6
},
1608 { "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "i,1,d", 0, 0, 0, v6
},
1609 { "xor", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1610 { "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "1,i,d", 0, 0, 0, v6
},
1611 { "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,1,d", 0, 0, 0, v6
},
1612 { "xorcc", F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1613 { "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "1,i,d", 0, 0, 0, v6
},
1614 { "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "i,1,d", 0, 0, 0, v6
},
1616 { "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS
, 0, 0, v6
}, /* xnor rs1,%0,rd */
1617 { "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS
, 0, 0, v6
}, /* xnor rd,%0,rd */
1619 { "btog", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "2,r", F_ALIAS
, 0, 0, v6
}, /* xor rd,rs2,rd */
1620 { "btog", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,r", F_ALIAS
, 0, 0, v6
}, /* xor rd,i,rd */
1622 /* FPop1 and FPop2 are not instructions. Don't accept them. */
1624 { "fdtoi", F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0
, "B,g", F_FLOAT
, 0, 0, v6
},
1625 { "fstoi", F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0
, "f,g", F_FLOAT
, 0, 0, v6
},
1626 { "fqtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0
, "R,g", F_FLOAT
, 0, 0, v8
},
1628 { "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0
, "B,H", F_FLOAT
, 0, 0, v9
},
1629 { "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0
, "f,H", F_FLOAT
, 0, 0, v9
},
1630 { "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0
, "R,H", F_FLOAT
, 0, 0, v9
},
1632 { "fitod", F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0
, "f,H", F_FLOAT
, 0, 0, v6
},
1633 { "fitos", F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0
, "f,g", F_FLOAT
, 0, 0, v6
},
1634 { "fitoq", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0
, "f,J", F_FLOAT
, 0, 0, v8
},
1636 { "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0
, "B,H", F_FLOAT
, 0, 0, v9
},
1637 { "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0
, "B,g", F_FLOAT
, 0, 0, v9
},
1638 { "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0
, "B,J", F_FLOAT
, 0, 0, v9
},
1640 { "fdtoq", F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0
, "B,J", F_FLOAT
, 0, 0, v8
},
1641 { "fdtos", F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0
, "B,g", F_FLOAT
, 0, 0, v6
},
1642 { "fqtod", F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0
, "R,H", F_FLOAT
, 0, 0, v8
},
1643 { "fqtos", F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0
, "R,g", F_FLOAT
, 0, 0, v8
},
1644 { "fstod", F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0
, "f,H", F_FLOAT
, 0, 0, v6
},
1645 { "fstoq", F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0
, "f,J", F_FLOAT
, 0, 0, v8
},
1647 { "fdivd", F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", F_FLOAT
, 0, 0, v6
},
1648 { "fdivq", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT
, 0, 0, v8
},
1649 { "fdivx", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT
|F_ALIAS
, 0, 0, v8
},
1650 { "fdivs", F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", F_FLOAT
, 0, 0, v6
},
1651 { "fmuld", F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", F_FLOAT
, 0, 0, v6
},
1652 { "fmulq", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT
, 0, 0, v8
},
1653 { "fmulx", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT
|F_ALIAS
, 0, 0, v8
},
1654 { "fmuls", F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", F_FLOAT
, 0, 0, v6
},
1656 { "fdmulq", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT
, 0, 0, v8
},
1657 { "fdmulx", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT
|F_ALIAS
, 0, 0, v8
},
1658 { "fsmuld", F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", F_FLOAT
, HWCAP_FSMULD
, 0, v8
},
1660 { "fsqrtd", F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0
, "B,H", F_FLOAT
, 0, 0, v7
},
1661 { "fsqrtq", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0
, "R,J", F_FLOAT
, 0, 0, v8
},
1662 { "fsqrtx", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0
, "R,J", F_FLOAT
|F_ALIAS
, 0, 0, v8
},
1663 { "fsqrts", F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0
, "f,g", F_FLOAT
, 0, 0, v7
},
1665 { "fabsd", F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0
, "B,H", F_FLOAT
, 0, 0, v9
},
1666 { "fabsq", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0
, "R,J", F_FLOAT
, 0, 0, v9
},
1667 { "fabsx", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0
, "R,J", F_FLOAT
|F_ALIAS
, 0, 0, v9
},
1668 { "fabss", F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0
, "f,g", F_FLOAT
, 0, 0, v6
},
1669 { "fmovd", F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0
, "B,H", F_FLOAT
, 0, 0, v9
},
1670 { "fmovq", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0
, "R,J", F_FLOAT
, 0, 0, v9
},
1671 { "fmovx", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0
, "R,J", F_FLOAT
|F_ALIAS
, 0, 0, v9
},
1672 { "fmovs", F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0
, "f,g", F_FLOAT
, 0, 0, v6
},
1673 { "fnegd", F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0
, "B,H", F_FLOAT
, 0, 0, v9
},
1674 { "fnegq", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0
, "R,J", F_FLOAT
, 0, 0, v9
},
1675 { "fnegx", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0
, "R,J", F_FLOAT
|F_ALIAS
, 0, 0, v9
},
1676 { "fnegs", F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0
, "f,g", F_FLOAT
, 0, 0, v6
},
1678 { "faddd", F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", F_FLOAT
, 0, 0, v6
},
1679 { "faddq", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT
, 0, 0, v8
},
1680 { "faddx", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT
|F_ALIAS
, 0, 0, v8
},
1681 { "fadds", F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", F_FLOAT
, 0, 0, v6
},
1682 { "fsubd", F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", F_FLOAT
, 0, 0, v6
},
1683 { "fsubq", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT
, 0, 0, v8
},
1684 { "fsubx", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT
|F_ALIAS
, 0, 0, v8
},
1685 { "fsubs", F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", F_FLOAT
, 0, 0, v6
},
1687 #define CMPFCC(x) (((x)&0x3)<<25)
1689 { "fcmpd", F3F(2, 0x35, 0x052), F3F(~2, ~0x35, ~0x052)|RD_G0
, "v,B", F_FLOAT
, 0, 0, v6
},
1690 { "fcmpd", CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052), "6,v,B", F_FLOAT
, 0, 0, v9
},
1691 { "fcmpd", CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052), "7,v,B", F_FLOAT
, 0, 0, v9
},
1692 { "fcmpd", CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052), "8,v,B", F_FLOAT
, 0, 0, v9
},
1693 { "fcmpd", CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052), "9,v,B", F_FLOAT
, 0, 0, v9
},
1694 { "fcmped", F3F(2, 0x35, 0x056), F3F(~2, ~0x35, ~0x056)|RD_G0
, "v,B", F_FLOAT
, 0, 0, v6
},
1695 { "fcmped", CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056), "6,v,B", F_FLOAT
, 0, 0, v9
},
1696 { "fcmped", CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056), "7,v,B", F_FLOAT
, 0, 0, v9
},
1697 { "fcmped", CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056), "8,v,B", F_FLOAT
, 0, 0, v9
},
1698 { "fcmped", CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056), "9,v,B", F_FLOAT
, 0, 0, v9
},
1699 { "fcmpq", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0
, "V,R", F_FLOAT
, 0, 0, v8
},
1700 { "fcmpq", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT
, 0, 0, v9
},
1701 { "fcmpq", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT
, 0, 0, v9
},
1702 { "fcmpq", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT
, 0, 0, v9
},
1703 { "fcmpq", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT
, 0, 0, v9
},
1704 { "fcmpeq", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0
, "V,R", F_FLOAT
, 0, 0, v8
},
1705 { "fcmpeq", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT
, 0, 0, v9
},
1706 { "fcmpeq", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT
, 0, 0, v9
},
1707 { "fcmpeq", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT
, 0, 0, v9
},
1708 { "fcmpeq", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT
, 0, 0, v9
},
1709 { "fcmpx", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0
, "V,R", F_FLOAT
|F_ALIAS
, 0, 0, v8
},
1710 { "fcmpx", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT
|F_ALIAS
, 0, 0, v9
},
1711 { "fcmpx", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT
|F_ALIAS
, 0, 0, v9
},
1712 { "fcmpx", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT
|F_ALIAS
, 0, 0, v9
},
1713 { "fcmpx", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT
|F_ALIAS
, 0, 0, v9
},
1714 { "fcmpex", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0
, "V,R", F_FLOAT
|F_ALIAS
, 0, 0, v8
},
1715 { "fcmpex", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT
|F_ALIAS
, 0, 0, v9
},
1716 { "fcmpex", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT
|F_ALIAS
, 0, 0, v9
},
1717 { "fcmpex", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT
|F_ALIAS
, 0, 0, v9
},
1718 { "fcmpex", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT
|F_ALIAS
, 0, 0, v9
},
1719 { "fcmps", F3F(2, 0x35, 0x051), F3F(~2, ~0x35, ~0x051)|RD_G0
, "e,f", F_FLOAT
, 0, 0, v6
},
1720 { "fcmps", CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051), "6,e,f", F_FLOAT
, 0, 0, v9
},
1721 { "fcmps", CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051), "7,e,f", F_FLOAT
, 0, 0, v9
},
1722 { "fcmps", CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051), "8,e,f", F_FLOAT
, 0, 0, v9
},
1723 { "fcmps", CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051), "9,e,f", F_FLOAT
, 0, 0, v9
},
1724 { "fcmpes", F3F(2, 0x35, 0x055), F3F(~2, ~0x35, ~0x055)|RD_G0
, "e,f", F_FLOAT
, 0, 0, v6
},
1725 { "fcmpes", CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055), "6,e,f", F_FLOAT
, 0, 0, v9
},
1726 { "fcmpes", CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055), "7,e,f", F_FLOAT
, 0, 0, v9
},
1727 { "fcmpes", CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055), "8,e,f", F_FLOAT
, 0, 0, v9
},
1728 { "fcmpes", CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055), "9,e,f", F_FLOAT
, 0, 0, v9
},
1730 /* These Extended FPop (FIFO) instructions are new in the Fujitsu
1731 MB86934, replacing the CPop instructions from v6 and later
1734 #define EFPOP1_2(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op)|RS1_G0, args, 0, 0, 0, sparclite }
1735 #define EFPOP1_3(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op), args, 0, 0, 0, sparclite }
1736 #define EFPOP2_2(name, op, args) { name, F3F(2, 0x37, op), F3F(~2, ~0x37, ~op)|RD_G0, args, 0, 0, 0, sparclite }
1738 EFPOP1_2 ("efitod", 0x0c8, "f,H"),
1739 EFPOP1_2 ("efitos", 0x0c4, "f,g"),
1740 EFPOP1_2 ("efdtoi", 0x0d2, "B,g"),
1741 EFPOP1_2 ("efstoi", 0x0d1, "f,g"),
1742 EFPOP1_2 ("efstod", 0x0c9, "f,H"),
1743 EFPOP1_2 ("efdtos", 0x0c6, "B,g"),
1744 EFPOP1_2 ("efmovs", 0x001, "f,g"),
1745 EFPOP1_2 ("efnegs", 0x005, "f,g"),
1746 EFPOP1_2 ("efabss", 0x009, "f,g"),
1747 EFPOP1_2 ("efsqrtd", 0x02a, "B,H"),
1748 EFPOP1_2 ("efsqrts", 0x029, "f,g"),
1749 EFPOP1_3 ("efaddd", 0x042, "v,B,H"),
1750 EFPOP1_3 ("efadds", 0x041, "e,f,g"),
1751 EFPOP1_3 ("efsubd", 0x046, "v,B,H"),
1752 EFPOP1_3 ("efsubs", 0x045, "e,f,g"),
1753 EFPOP1_3 ("efdivd", 0x04e, "v,B,H"),
1754 EFPOP1_3 ("efdivs", 0x04d, "e,f,g"),
1755 EFPOP1_3 ("efmuld", 0x04a, "v,B,H"),
1756 EFPOP1_3 ("efmuls", 0x049, "e,f,g"),
1757 EFPOP1_3 ("efsmuld", 0x069, "e,f,H"),
1758 EFPOP2_2 ("efcmpd", 0x052, "v,B"),
1759 EFPOP2_2 ("efcmped", 0x056, "v,B"),
1760 EFPOP2_2 ("efcmps", 0x051, "e,f"),
1761 EFPOP2_2 ("efcmpes", 0x055, "e,f"),
1767 /* These are marked F_ALIAS, so that they won't conflict with sparclite insns
1768 present. Otherwise, the F_ALIAS flag is ignored. */
1769 { "cpop1", F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS
, 0, 0, v6notv9
},
1770 { "cpop2", F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS
, 0, 0, v6notv9
},
1772 /* sparclet specific insns */
1774 COMMUTEOP ("umac", 0x3e, letandleon
),
1775 COMMUTEOP ("smac", 0x3f, letandleon
),
1777 COMMUTEOP ("umacd", 0x2e, sparclet
),
1778 COMMUTEOP ("smacd", 0x2f, sparclet
),
1779 COMMUTEOP ("umuld", 0x09, sparclet
),
1780 COMMUTEOP ("smuld", 0x0d, sparclet
),
1782 { "shuffle", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, 0, 0, sparclet
},
1783 { "shuffle", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, 0, 0, sparclet
},
1785 /* The manual isn't completely accurate on these insns. The `rs2' field is
1786 treated as being 6 bits to account for 6 bit immediates to cpush. It is
1787 assumed that it is intended that bit 5 is 0 when rs2 contains a reg. */
1789 { "crdcxt", F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5
|RS2(~0), "U,d", 0, 0, 0, sparclet
},
1790 { "cwrcxt", F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5
|RS2(~0), "1,u", 0, 0, 0, sparclet
},
1791 { "cpush", F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5
|RD(~0), "1,2", 0, 0, 0, sparclet
},
1792 { "cpush", F3(2, 0x36, 1)|SLCPOP(0), F3(~2, ~0x36, ~1)|SLCPOP(~0)|RD(~0), "1,Y", 0, 0, 0, sparclet
},
1793 { "cpusha", F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5
|RD(~0), "1,2", 0, 0, 0, sparclet
},
1794 { "cpusha", F3(2, 0x36, 1)|SLCPOP(1), F3(~2, ~0x36, ~1)|SLCPOP(~1)|RD(~0), "1,Y", 0, 0, 0, sparclet
},
1795 { "cpull", F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5
|RS1(~0)|RS2(~0), "d", 0, 0, 0, sparclet
},
1798 /* sparclet coprocessor branch insns */
1799 #define SLCBCC2(opcode, mask, lose) \
1800 { opcode, (mask), ANNUL|(lose), "l", F_DELAYED|F_CONDBR, 0, 0, sparclet }, \
1801 { opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR, 0, 0, sparclet }
1802 #define SLCBCC(opcode, mask) \
1803 SLCBCC2(opcode, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)))
1805 /* cbn,cba can't be defined here because they're defined elsewhere and GAS
1806 requires all mnemonics of the same name to be consecutive. */
1807 /*SLCBCC("cbn", 0), - already defined */
1815 /*SLCBCC("cba", 8), - already defined */
1818 SLCBCC("cbnef", 11),
1820 SLCBCC("cbner", 13),
1821 SLCBCC("cbnfr", 14),
1822 SLCBCC("cbnefr", 15),
1827 { "casa", F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, 0, 0, v9andleon
},
1828 { "casa", F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, 0, 0, v9andleon
},
1829 { "casxa", F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, 0, 0, v9
},
1830 { "casxa", F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, 0, 0, v9
},
1832 /* v9 synthetic insns */
1833 { "iprefetch", F2(0, 1)|(2<<20)|BPRED
, F2(~0, ~1)|(1<<20)|ANNUL
|COND(~0), "G", 0, 0, 0, v9
}, /* bn,a,pt %xcc,label */
1834 { "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0
, "1,d", F_ALIAS
, 0, 0, v9
}, /* sra rs1,%g0,rd */
1835 { "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0
, "r", F_ALIAS
, 0, 0, v9
}, /* sra rd,%g0,rd */
1836 { "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0
, "1,d", F_ALIAS
, 0, 0, v9
}, /* srl rs1,%g0,rd */
1837 { "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0
, "r", F_ALIAS
, 0, 0, v9
}, /* srl rd,%g0,rd */
1838 { "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS
, 0, 0, v9
}, /* casa [rs1]ASI_P,rs2,rd */
1839 { "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS
, 0, 0, v9
}, /* casa [rs1]ASI_P_L,rs2,rd */
1840 { "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS
, 0, 0, v9
}, /* casxa [rs1]ASI_P,rs2,rd */
1841 { "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS
, 0, 0, v9
}, /* casxa [rs1]ASI_P_L,rs2,rd */
1843 /* Ultrasparc extensions */
1844 { "shutdown", F3F(2, 0x36, 0x080), F3F(~2, ~0x36, ~0x080)|RD_G0
|RS1_G0
|RS2_G0
, "", 0, HWCAP_VIS
, 0, v9a
},
1846 /* FIXME: Do we want to mark these as F_FLOAT, or something similar? */
1847 { "fpadd16", F3F(2, 0x36, 0x050), F3F(~2, ~0x36, ~0x050), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
1848 { "fpadd16s", F3F(2, 0x36, 0x051), F3F(~2, ~0x36, ~0x051), "e,f,g", 0, HWCAP_VIS
, 0, v9a
},
1849 { "fpadd32", F3F(2, 0x36, 0x052), F3F(~2, ~0x36, ~0x052), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
1850 { "fpadd32s", F3F(2, 0x36, 0x053), F3F(~2, ~0x36, ~0x053), "e,f,g", 0, HWCAP_VIS
, 0, v9a
},
1851 { "fpsub16", F3F(2, 0x36, 0x054), F3F(~2, ~0x36, ~0x054), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
1852 { "fpsub16s", F3F(2, 0x36, 0x055), F3F(~2, ~0x36, ~0x055), "e,f,g", 0, HWCAP_VIS
, 0, v9a
},
1853 { "fpsub32", F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
1854 { "fpsub32s", F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g", 0, HWCAP_VIS
, 0, v9a
},
1856 { "fpack32", F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
1857 { "fpack16", F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0
, "B,g", 0, HWCAP_VIS
, 0, v9a
},
1858 { "fpackfix", F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0
, "B,g", 0, HWCAP_VIS
, 0, v9a
},
1859 { "fexpand", F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0
, "f,H", 0, HWCAP_VIS
, 0, v9a
},
1860 { "fpmerge", F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H", 0, HWCAP_VIS
, 0, v9a
},
1862 /* Note that the mixing of 32/64 bit regs is intentional. */
1863 { "fmul8x16", F3F(2, 0x36, 0x031), F3F(~2, ~0x36, ~0x031), "e,B,H", 0, HWCAP_VIS
, 0, v9a
},
1864 { "fmul8x16au", F3F(2, 0x36, 0x033), F3F(~2, ~0x36, ~0x033), "e,f,H", 0, HWCAP_VIS
, 0, v9a
},
1865 { "fmul8x16al", F3F(2, 0x36, 0x035), F3F(~2, ~0x36, ~0x035), "e,f,H", 0, HWCAP_VIS
, 0, v9a
},
1866 { "fmul8sux16", F3F(2, 0x36, 0x036), F3F(~2, ~0x36, ~0x036), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
1867 { "fmul8ulx16", F3F(2, 0x36, 0x037), F3F(~2, ~0x36, ~0x037), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
1868 { "fmuld8sux16", F3F(2, 0x36, 0x038), F3F(~2, ~0x36, ~0x038), "e,f,H", 0, HWCAP_VIS
, 0, v9a
},
1869 { "fmuld8ulx16", F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039), "e,f,H", 0, HWCAP_VIS
, 0, v9a
},
1871 { "alignaddr", F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, HWCAP_VIS
, 0, v9a
},
1872 { "alignaddrl", F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, HWCAP_VIS
, 0, v9a
},
1873 { "faligndata", F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, HWCAP_VIS
, 0, v9a
}, /* faligndatag */
1874 { "faligndata", F3F(2, 0x36, 0x049), F3F(~2, ~0x36, ~0x049), "v,B,5,}", 0, 0, HWCAP2_SPARC5
, v9b
}, /* faligndatai */
1876 { "fzerod", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, HWCAP_VIS
, 0, v9a
},
1877 { "fzero", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1878 { "fzeros", F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g", 0, HWCAP_VIS
, 0, v9a
},
1879 { "foned", F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, HWCAP_VIS
, 0, v9a
},
1880 { "fone", F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1881 { "fones", F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g", 0, HWCAP_VIS
, 0, v9a
},
1882 { "fsrc1d", F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, HWCAP_VIS
, 0, v9a
},
1883 { "fsrc1", F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1884 { "fsrc1s", F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g", 0, HWCAP_VIS
, 0, v9a
},
1885 { "fsrc2d", F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, HWCAP_VIS
, 0, v9a
},
1886 { "fsrc2", F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1887 { "fsrc2s", F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g", 0, HWCAP_VIS
, 0, v9a
},
1888 { "fnot1d", F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, HWCAP_VIS
, 0, v9a
},
1889 { "fnot1", F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1890 { "fnot1s", F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g", 0, HWCAP_VIS
, 0, v9a
},
1891 { "fnot2d", F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, HWCAP_VIS
, 0, v9a
},
1892 { "fnot2", F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1893 { "fnot2s", F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g", 0, HWCAP_VIS
, 0, v9a
},
1894 { "ford", F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
1895 { "for", F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1896 { "fors", F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g", 0, HWCAP_VIS
, 0, v9a
},
1897 { "fnord", F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
1898 { "fnor", F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1899 { "fnors", F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g", 0, HWCAP_VIS
, 0, v9a
},
1900 { "fandd", F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
1901 { "fand", F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1902 { "fands", F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g", 0, HWCAP_VIS
, 0, v9a
},
1903 { "fnandd", F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
1904 { "fnand", F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1905 { "fnands", F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g", 0, HWCAP_VIS
, 0, v9a
},
1906 { "fxord", F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
1907 { "fxor", F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1908 { "fxors", F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g", 0, HWCAP_VIS
, 0, v9a
},
1909 { "fxnord", F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
1910 { "fxnor", F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1911 { "fxnors", F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g", 0, HWCAP_VIS
, 0, v9a
},
1912 { "fornot1d", F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
1913 { "fornot1", F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1914 { "fornot1s", F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g", 0, HWCAP_VIS
, 0, v9a
},
1915 { "fornot2d", F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
1916 { "fornot2", F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1917 { "fornot2s", F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g", 0, HWCAP_VIS
, 0, v9a
},
1918 { "fandnot1d", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
1919 { "fandnot1", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1920 { "fandnot1s", F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g", 0, HWCAP_VIS
, 0, v9a
},
1921 { "fandnot2d", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
1922 { "fandnot2", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1923 { "fandnot2s", F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g", 0, HWCAP_VIS
, 0, v9a
},
1925 { "fpcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, HWCAP_VIS
, 0, v9a
},
1926 { "fcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1927 { "fpcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, HWCAP_VIS
, 0, v9a
},
1928 { "fcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1929 { "fpcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, HWCAP_VIS
, 0, v9a
},
1930 { "fcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1931 { "fpcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, HWCAP_VIS
, 0, v9a
},
1932 { "fcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1933 { "fpcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, HWCAP_VIS
, 0, v9a
},
1934 { "fpcmpune16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1935 { "fcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1936 { "fpcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, HWCAP_VIS
, 0, v9a
},
1937 { "fpcmpune32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1938 { "fcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1939 { "fpcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, HWCAP_VIS
, 0, v9a
},
1940 { "fpcmpueq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1941 { "fcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1942 { "fpcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, HWCAP_VIS
, 0, v9a
},
1943 { "fpcmpueq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1944 { "fcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1946 { "edge8cc", F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, HWCAP_VIS
, 0, v9a
},
1947 { "edge8lcc", F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, HWCAP_VIS
, 0, v9a
},
1948 { "edge16cc", F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, HWCAP_VIS
, 0, v9a
},
1949 { "edge16lcc", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, HWCAP_VIS
, 0, v9a
},
1950 { "edge32cc", F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, HWCAP_VIS
, 0, v9a
},
1951 { "edge32lcc", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, HWCAP_VIS
, 0, v9a
},
1953 { "edge8", F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1954 { "edge8l", F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1955 { "edge16", F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1956 { "edge16l", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1957 { "edge32", F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1958 { "edge32l", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
1960 { "pdist", F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
1962 { "array8", F3F(2, 0x36, 0x010), F3F(~2, ~0x36, ~0x010), "1,2,d", 0, HWCAP_VIS
, 0, v9a
},
1963 { "array16", F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, HWCAP_VIS
, 0, v9a
},
1964 { "array32", F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, HWCAP_VIS
, 0, v9a
},
1966 /* Cheetah instructions */
1967 { "edge8n", F3F(2, 0x36, 0x001), F3F(~2, ~0x36, ~0x001), "1,2,d", 0, HWCAP_VIS2
, 0, v9b
},
1968 { "edge8ln", F3F(2, 0x36, 0x003), F3F(~2, ~0x36, ~0x003), "1,2,d", 0, HWCAP_VIS2
, 0, v9b
},
1969 { "edge16n", F3F(2, 0x36, 0x005), F3F(~2, ~0x36, ~0x005), "1,2,d", 0, HWCAP_VIS2
, 0, v9b
},
1970 { "edge16ln", F3F(2, 0x36, 0x007), F3F(~2, ~0x36, ~0x007), "1,2,d", 0, HWCAP_VIS2
, 0, v9b
},
1971 { "edge32n", F3F(2, 0x36, 0x009), F3F(~2, ~0x36, ~0x009), "1,2,d", 0, HWCAP_VIS2
, 0, v9b
},
1972 { "edge32ln", F3F(2, 0x36, 0x00b), F3F(~2, ~0x36, ~0x00b), "1,2,d", 0, HWCAP_VIS2
, 0, v9b
},
1974 { "bmask", F3F(2, 0x36, 0x019), F3F(~2, ~0x36, ~0x019), "1,2,d", 0, HWCAP_VIS2
, 0, v9b
},
1975 { "bshuffle", F3F(2, 0x36, 0x04c), F3F(~2, ~0x36, ~0x04c), "v,B,H", 0, HWCAP_VIS2
, 0, v9b
},
1977 { "siam", F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0
|RS1_G0
|RS2(~7), "3", 0, HWCAP_VIS2
, 0, v9b
},
1979 { "fnadds", F3F(2, 0x34, 0x051), F3F(~2, ~0x34, ~0x051), "e,f,g", F_FLOAT
, HWCAP_HPC
, 0, v9b
},
1980 { "fnaddd", F3F(2, 0x34, 0x052), F3F(~2, ~0x34, ~0x052), "v,B,H", F_FLOAT
, HWCAP_HPC
, 0, v9b
},
1981 { "fnmuls", F3F(2, 0x34, 0x059), F3F(~2, ~0x34, ~0x059), "e,f,g", F_FLOAT
, HWCAP_HPC
, 0, v9b
},
1982 { "fnmuld", F3F(2, 0x34, 0x05a), F3F(~2, ~0x34, ~0x05a), "v,B,H", F_FLOAT
, HWCAP_HPC
, 0, v9b
},
1983 { "fhadds", F3F(2, 0x34, 0x061), F3F(~2, ~0x34, ~0x061), "e,f,g", F_FLOAT
, HWCAP_HPC
, 0, v9b
},
1984 { "fhaddd", F3F(2, 0x34, 0x062), F3F(~2, ~0x34, ~0x062), "v,B,H", F_FLOAT
, HWCAP_HPC
, 0, v9b
},
1985 { "fhsubs", F3F(2, 0x34, 0x065), F3F(~2, ~0x34, ~0x065), "e,f,g", F_FLOAT
, HWCAP_HPC
, 0, v9b
},
1986 { "fhsubd", F3F(2, 0x34, 0x066), F3F(~2, ~0x34, ~0x066), "v,B,H", F_FLOAT
, HWCAP_HPC
, 0, v9b
},
1987 { "fnhadds", F3F(2, 0x34, 0x071), F3F(~2, ~0x34, ~0x071), "e,f,g", F_FLOAT
, HWCAP_HPC
, 0, v9b
},
1988 { "fnhaddd", F3F(2, 0x34, 0x072), F3F(~2, ~0x34, ~0x072), "v,B,H", F_FLOAT
, HWCAP_HPC
, 0, v9b
},
1989 { "fnsmuld", F3F(2, 0x34, 0x079), F3F(~2, ~0x34, ~0x079), "e,f,H", F_FLOAT
, HWCAP_HPC
, 0, v9b
},
1990 { "fpmaddx", F3(2, 0x37, 0)|OPF_LOW4(0), F3(~2, ~0x37, 0)|OPF_LOW4(~0), "v,B,5,H", F_FLOAT
, HWCAP_IMA
, 0, v9b
},
1991 { "fmadds", F3(2, 0x37, 0)|OPF_LOW4(1), F3(~2, ~0x37, 0)|OPF_LOW4(~1), "e,f,4,g", F_FLOAT
, HWCAP_FMAF
, 0, v9b
},
1992 { "fmaddd", F3(2, 0x37, 0)|OPF_LOW4(2), F3(~2, ~0x37, 0)|OPF_LOW4(~2), "v,B,5,H", F_FLOAT
, HWCAP_FMAF
, 0, v9b
},
1993 { "fpmaddxhi", F3(2, 0x37, 0)|OPF_LOW4(4), F3(~2, ~0x37, 0)|OPF_LOW4(~4), "v,B,5,H", F_FLOAT
, HWCAP_IMA
, 0, v9b
},
1994 { "fmsubs", F3(2, 0x37, 0)|OPF_LOW4(5), F3(~2, ~0x37, 0)|OPF_LOW4(~5), "e,f,4,g", F_FLOAT
, HWCAP_FMAF
, 0, v9b
},
1995 { "fmsubd", F3(2, 0x37, 0)|OPF_LOW4(6), F3(~2, ~0x37, 0)|OPF_LOW4(~6), "v,B,5,H", F_FLOAT
, HWCAP_FMAF
, 0, v9b
},
1996 { "fnmsubs", F3(2, 0x37, 0)|OPF_LOW4(9), F3(~2, ~0x37, 0)|OPF_LOW4(~9), "e,f,4,g", F_FLOAT
, HWCAP_FMAF
, 0, v9b
},
1997 { "fnmsubd", F3(2, 0x37, 0)|OPF_LOW4(10), F3(~2, ~0x37, 0)|OPF_LOW4(~10), "v,B,5,H", F_FLOAT
, HWCAP_FMAF
, 0, v9b
},
1998 { "fnmadds", F3(2, 0x37, 0)|OPF_LOW4(13), F3(~2, ~0x37, 0)|OPF_LOW4(~13), "e,f,4,g", F_FLOAT
, HWCAP_FMAF
, 0, v9b
},
1999 { "fnmaddd", F3(2, 0x37, 0)|OPF_LOW4(14), F3(~2, ~0x37, 0)|OPF_LOW4(~14), "v,B,5,H", F_FLOAT
, HWCAP_FMAF
, 0, v9b
},
2000 { "fumadds", F3(2, 0x3f, 0)|OPF_LOW4(1), F3(~2, ~0x3f, 0)|OPF_LOW4(~1), "e,f,4,g", F_FLOAT
, HWCAP_FJFMAU
, 0, v9b
},
2001 { "fumaddd", F3(2, 0x3f, 0)|OPF_LOW4(2), F3(~2, ~0x3f, 0)|OPF_LOW4(~2), "v,B,5,H", F_FLOAT
, HWCAP_FJFMAU
, 0, v9b
},
2002 { "fumsubs", F3(2, 0x3f, 0)|OPF_LOW4(5), F3(~2, ~0x3f, 0)|OPF_LOW4(~5), "e,f,4,g", F_FLOAT
, HWCAP_FJFMAU
, 0, v9b
},
2003 { "fumsubd", F3(2, 0x3f, 0)|OPF_LOW4(6), F3(~2, ~0x3f, 0)|OPF_LOW4(~6), "v,B,5,H", F_FLOAT
, HWCAP_FJFMAU
, 0, v9b
},
2004 { "fnumsubs", F3(2, 0x3f, 0)|OPF_LOW4(9), F3(~2, ~0x3f, 0)|OPF_LOW4(~9), "e,f,4,g", F_FLOAT
, HWCAP_FJFMAU
, 0, v9b
},
2005 { "fnumsubd", F3(2, 0x3f, 0)|OPF_LOW4(10), F3(~2, ~0x3f, 0)|OPF_LOW4(~10), "v,B,5,H", F_FLOAT
, HWCAP_FJFMAU
, 0, v9b
},
2006 { "fnumadds", F3(2, 0x3f, 0)|OPF_LOW4(13), F3(~2, ~0x3f, 0)|OPF_LOW4(~13), "e,f,4,g", F_FLOAT
, HWCAP_FJFMAU
, 0, v9b
},
2007 { "fnumaddd", F3(2, 0x3f, 0)|OPF_LOW4(14), F3(~2, ~0x3f, 0)|OPF_LOW4(~14), "v,B,5,H", F_FLOAT
, HWCAP_FJFMAU
, 0, v9b
},
2008 { "addxc", F3F(2, 0x36, 0x011), F3F(~2, ~0x36, ~0x011), "1,2,d", 0, HWCAP_VIS3
, 0, v9b
},
2009 { "addxccc", F3F(2, 0x36, 0x013), F3F(~2, ~0x36, ~0x013), "1,2,d", 0, HWCAP_VIS3
, 0, v9b
},
2010 { "umulxhi", F3F(2, 0x36, 0x016), F3F(~2, ~0x36, ~0x016), "1,2,d", 0, HWCAP_VIS3
, 0, v9b
},
2011 { "lzcnt", F3F(2, 0x36, 0x017), F3F(~2, ~0x36, ~0x017), "2,d", 0, HWCAP_VIS3
, 0, v9b
},
2012 { "lzd", F3F(2, 0x36, 0x017), F3F(~2, ~0x36, ~0x017), "2,d", F_ALIAS
, HWCAP_VIS3
, 0, v9b
},
2013 { "cmask8", F3F(2, 0x36, 0x01b), F3F(~2, ~0x36, ~0x01b), "2", 0, HWCAP_VIS3
, 0, v9b
},
2014 { "cmask16", F3F(2, 0x36, 0x01d), F3F(~2, ~0x36, ~0x01d), "2", 0, HWCAP_VIS3
, 0, v9b
},
2015 { "cmask32", F3F(2, 0x36, 0x01f), F3F(~2, ~0x36, ~0x01f), "2", 0, HWCAP_VIS3
, 0, v9b
},
2016 { "fsll16", F3F(2, 0x36, 0x021), F3F(~2, ~0x36, ~0x021), "v,B,H", 0, HWCAP_VIS3
, 0, v9b
},
2017 { "fsrl16", F3F(2, 0x36, 0x023), F3F(~2, ~0x36, ~0x023), "v,B,H", 0, HWCAP_VIS3
, 0, v9b
},
2018 { "fsll32", F3F(2, 0x36, 0x025), F3F(~2, ~0x36, ~0x025), "v,B,H", 0, HWCAP_VIS3
, 0, v9b
},
2019 { "fsrl32", F3F(2, 0x36, 0x027), F3F(~2, ~0x36, ~0x027), "v,B,H", 0, HWCAP_VIS3
, 0, v9b
},
2020 { "fslas16", F3F(2, 0x36, 0x029), F3F(~2, ~0x36, ~0x029), "v,B,H", 0, HWCAP_VIS3
, 0, v9b
},
2021 { "fsra16", F3F(2, 0x36, 0x02b), F3F(~2, ~0x36, ~0x02b), "v,B,H", 0, HWCAP_VIS3
, 0, v9b
},
2022 { "fslas32", F3F(2, 0x36, 0x02d), F3F(~2, ~0x36, ~0x02d), "v,B,H", 0, HWCAP_VIS3
, 0, v9b
},
2023 { "fsra32", F3F(2, 0x36, 0x02f), F3F(~2, ~0x36, ~0x02f), "v,B,H", 0, HWCAP_VIS3
, 0, v9b
},
2024 { "pdistn", F3F(2, 0x36, 0x03f), F3F(~2, ~0x36, ~0x03f), "v,B,d", 0, HWCAP_VIS3
, 0, v9b
},
2025 { "fmean16", F3F(2, 0x36, 0x040), F3F(~2, ~0x36, ~0x040), "v,B,H", 0, HWCAP_VIS3
, 0, v9b
},
2026 { "fpadd64", F3F(2, 0x36, 0x042), F3F(~2, ~0x36, ~0x042), "v,B,H", 0, HWCAP_VIS3
, HWCAP2_VIS3B
, v9b
},
2027 { "fchksm16", F3F(2, 0x36, 0x044), F3F(~2, ~0x36, ~0x044), "v,B,H", 0, HWCAP_VIS3
, 0, v9b
},
2028 { "fpsub64", F3F(2, 0x36, 0x046), F3F(~2, ~0x36, ~0x046), "v,B,H", 0, HWCAP_VIS3
, HWCAP2_VIS3B
, v9b
},
2029 { "fpadds16", F3F(2, 0x36, 0x058), F3F(~2, ~0x36, ~0x058), "v,B,H", 0, HWCAP_VIS3
, 0, v9b
},
2030 { "fpadds16s", F3F(2, 0x36, 0x059), F3F(~2, ~0x36, ~0x059), "e,f,g", 0, HWCAP_VIS3
, 0, v9b
},
2031 { "fpadds32", F3F(2, 0x36, 0x05a), F3F(~2, ~0x36, ~0x05a), "v,B,H", 0, HWCAP_VIS3
, 0, v9b
},
2032 { "fpadds32s", F3F(2, 0x36, 0x05b), F3F(~2, ~0x36, ~0x05b), "e,f,g", 0, HWCAP_VIS3
, 0, v9b
},
2033 { "fpsubs16", F3F(2, 0x36, 0x05c), F3F(~2, ~0x36, ~0x05c), "v,B,H", 0, HWCAP_VIS3
, 0, v9b
},
2034 { "fpsubs16s", F3F(2, 0x36, 0x05d), F3F(~2, ~0x36, ~0x05d), "e,f,g", 0, HWCAP_VIS3
, 0, v9b
},
2035 { "fpsubs32", F3F(2, 0x36, 0x05e), F3F(~2, ~0x36, ~0x05e), "v,B,H", 0, HWCAP_VIS3
, 0, v9b
},
2036 { "fpsubs32s", F3F(2, 0x36, 0x05f), F3F(~2, ~0x36, ~0x05f), "e,f,g", 0, HWCAP_VIS3
, 0, v9b
},
2037 { "movdtox", F3F(2, 0x36, 0x110), F3F(~2, ~0x36, ~0x110), "B,d", F_FLOAT
, HWCAP_VIS3
, 0, v9b
},
2038 { "movstouw", F3F(2, 0x36, 0x111), F3F(~2, ~0x36, ~0x111), "f,d", F_FLOAT
, HWCAP_VIS3
, 0, v9b
},
2039 { "movstosw", F3F(2, 0x36, 0x113), F3F(~2, ~0x36, ~0x113), "f,d", F_FLOAT
, HWCAP_VIS3
, 0, v9b
},
2040 { "movxtod", F3F(2, 0x36, 0x118), F3F(~2, ~0x36, ~0x118), "2,H", F_FLOAT
, HWCAP_VIS3
, 0, v9b
},
2041 { "movwtos", F3F(2, 0x36, 0x119), F3F(~2, ~0x36, ~0x119), "2,g", F_FLOAT
, HWCAP_VIS3
, 0, v9b
},
2042 { "xmulx", F3F(2, 0x36, 0x115), F3F(~2, ~0x36, ~0x115), "1,2,d", 0, HWCAP_VIS3
, 0, v9b
},
2043 { "xmulxhi", F3F(2, 0x36, 0x116), F3F(~2, ~0x36, ~0x116), "1,2,d", 0, HWCAP_VIS3
, 0, v9b
},
2044 { "fpcmpule8", F3F(2, 0x36, 0x120), F3F(~2, ~0x36, ~0x120), "v,B,d", 0, HWCAP_VIS3
, HWCAP2_VIS3B
, v9b
},
2045 { "fucmple8", F3F(2, 0x36, 0x120), F3F(~2, ~0x36, ~0x120), "v,B,d", F_ALIAS
, HWCAP_VIS3
, 0, v9b
},
2046 { "fpcmpune8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", 0, HWCAP_VIS3
, HWCAP2_VIS3B
, v9b
},
2047 { "fpcmpne8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", F_PREF_ALIAS
, HWCAP_VIS3
, 0, v9b
},
2048 { "fucmpne8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", F_ALIAS
, HWCAP_VIS3
, 0, v9b
},
2049 { "fpcmpugt8", F3F(2, 0x36, 0x128), F3F(~2, ~0x36, ~0x128), "v,B,d", 0, HWCAP_VIS3
, HWCAP2_VIS3B
, v9b
},
2050 { "fucmpgt8", F3F(2, 0x36, 0x128), F3F(~2, ~0x36, ~0x128), "v,B,d", F_ALIAS
, HWCAP_VIS3
, 0, v9b
},
2051 { "fpcmpueq8", F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", 0, HWCAP_VIS3
, HWCAP2_VIS3B
, v9b
},
2052 { "fpcmpeq8", F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", F_PREF_ALIAS
, HWCAP_VIS3
, 0, v9b
},
2053 { "fucmpeq8", F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", F_ALIAS
, HWCAP_VIS3
, 0, v9b
},
2054 {"aes_kexpand0",F3F(2, 0x36, 0x130), F3F(~2, ~0x36, ~0x130), "v,B,H", F_FLOAT
, HWCAP_AES
, 0, v9b
},
2055 {"aes_kexpand2",F3F(2, 0x36, 0x131), F3F(~2, ~0x36, ~0x131), "v,B,H", F_FLOAT
, HWCAP_AES
, 0, v9b
},
2056 { "des_ip", F3F(2, 0x36, 0x134), F3F(~2, ~0x36, ~0x134), "v,H", F_FLOAT
, HWCAP_DES
, 0, v9b
},
2057 { "des_iip", F3F(2, 0x36, 0x135), F3F(~2, ~0x36, ~0x135), "v,H", F_FLOAT
, HWCAP_DES
, 0, v9b
},
2058 { "des_kexpand",F3F(2, 0x36, 0x136), F3F(~2, ~0x36, ~0x136), "v,X,H", F_FLOAT
, HWCAP_DES
, 0, v9b
},
2059 {"kasumi_fi_fi",F3F(2, 0x36, 0x138), F3F(~2, ~0x36, ~0x138), "v,B,H", F_FLOAT
, HWCAP_KASUMI
, 0, v9b
},
2060 { "camellia_fi",F3F(2, 0x36, 0x13c), F3F(~2, ~0x36, ~0x13c), "v,B,H", F_FLOAT
, HWCAP_CAMELLIA
, 0, v9b
},
2061 {"camellia_fli",F3F(2, 0x36, 0x13d), F3F(~2, ~0x36, ~0x13d), "v,B,H", F_FLOAT
, HWCAP_CAMELLIA
, 0, v9b
},
2062 { "md5", F3F(2, 0x36, 0x140), F3F(~2, ~0x36, ~0x140), "", F_FLOAT
, HWCAP_MD5
, 0, v9b
},
2063 { "sha1", F3F(2, 0x36, 0x141), F3F(~2, ~0x36, ~0x141), "", F_FLOAT
, HWCAP_SHA1
, 0, v9b
},
2064 { "sha256", F3F(2, 0x36, 0x142), F3F(~2, ~0x36, ~0x142), "", F_FLOAT
, HWCAP_SHA256
, 0, v9b
},
2065 { "sha512", F3F(2, 0x36, 0x143), F3F(~2, ~0x36, ~0x143), "", F_FLOAT
, HWCAP_SHA512
, 0, v9b
},
2066 { "crc32c", F3F(2, 0x36, 0x147), F3F(~2, ~0x36, ~0x147), "v,B,H", F_FLOAT
, HWCAP_CRC32C
, 0, v9b
},
2067 { "xmpmul", F3F(2, 0x36, 0x148)|RD(1), F3F(~2, ~0x36, ~0x148)|RD(~1), "X", F_FLOAT
, 0, HWCAP2_XMPMUL
, v9b
},
2068 { "mpmul", F3F(2, 0x36, 0x148), F3F(~2, ~0x36, ~0x148), "X", F_FLOAT
, HWCAP_MPMUL
, 0, v9b
},
2069 { "xmontmul", F3F(2, 0x36, 0x149)|RD(1), F3F(~2, ~0x36, ~0x149)|RD(~1), "X", F_FLOAT
, 0, HWCAP2_XMONT
, v9b
},
2070 { "montmul", F3F(2, 0x36, 0x149), F3F(~2, ~0x36, ~0x149), "X", F_FLOAT
, HWCAP_MONT
, 0, v9b
},
2071 { "xmontsqr", F3F(2, 0x36, 0x14a)|RD(1), F3F(~2, ~0x36, ~0x14a)|RD(~1), "X", F_FLOAT
, 0, HWCAP2_XMONT
, v9b
},
2072 { "montsqr", F3F(2, 0x36, 0x14a), F3F(~2, ~0x36, ~0x14a), "X", F_FLOAT
, HWCAP_MONT
, 0, v9b
},
2073 {"aes_eround01", F3F4(2, 0x19, 0), F3F4(~2, ~0x19, ~0), "v,B,5,H", F_FLOAT
, HWCAP_AES
, 0, v9b
},
2074 {"aes_eround23", F3F4(2, 0x19, 1), F3F4(~2, ~0x19, ~1), "v,B,5,H", F_FLOAT
, HWCAP_AES
, 0, v9b
},
2075 {"aes_dround01", F3F4(2, 0x19, 2), F3F4(~2, ~0x19, ~2), "v,B,5,H", F_FLOAT
, HWCAP_AES
, 0, v9b
},
2076 {"aes_dround23", F3F4(2, 0x19, 3), F3F4(~2, ~0x19, ~3), "v,B,5,H", F_FLOAT
, HWCAP_AES
, 0, v9b
},
2077 {"aes_eround01_l",F3F4(2, 0x19, 4), F3F4(~2, ~0x19, ~4), "v,B,5,H", F_FLOAT
, HWCAP_AES
, 0, v9b
},
2078 {"aes_eround23_l",F3F4(2, 0x19, 5), F3F4(~2, ~0x19, ~5), "v,B,5,H", F_FLOAT
, HWCAP_AES
, 0, v9b
},
2079 {"aes_dround01_l",F3F4(2, 0x19, 6), F3F4(~2, ~0x19, ~6), "v,B,5,H", F_FLOAT
, HWCAP_AES
, 0, v9b
},
2080 {"aes_dround23_l",F3F4(2, 0x19, 7), F3F4(~2, ~0x19, ~7), "v,B,5,H", F_FLOAT
, HWCAP_AES
, 0, v9b
},
2081 {"aes_kexpand1", F3F4(2, 0x19, 8), F3F4(~2, ~0x19, ~8), "v,B,),H", F_FLOAT
, HWCAP_AES
, 0, v9b
},
2082 {"des_round", F3F4(2, 0x19, 9), F3F4(~2, ~0x19, ~9), "v,B,5,H", F_FLOAT
, HWCAP_DES
, 0, v9b
},
2083 {"kasumi_fl_xor", F3F4(2, 0x19, 10), F3F4(~2, ~0x19, ~10), "v,B,5,H", F_FLOAT
, HWCAP_KASUMI
, 0, v9b
},
2084 {"kasumi_fi_xor", F3F4(2, 0x19, 11), F3F4(~2, ~0x19, ~11), "v,B,5,H", F_FLOAT
, HWCAP_KASUMI
, 0, v9b
},
2085 {"camellia_f", F3F4(2, 0x19, 12), F3F4(~2, ~0x19, ~12), "v,B,5,H", F_FLOAT
, HWCAP_CAMELLIA
, 0, v9b
},
2086 { "flcmps", CMPFCC(0)|F3F(2, 0x36, 0x151), CMPFCC(~0)|F3F(~2, ~0x36, ~0x151), "6,e,f", F_FLOAT
, HWCAP_HPC
, 0, v9b
},
2087 { "flcmps", CMPFCC(1)|F3F(2, 0x36, 0x151), CMPFCC(~1)|F3F(~2, ~0x36, ~0x151), "7,e,f", F_FLOAT
, HWCAP_HPC
, 0, v9b
},
2088 { "flcmps", CMPFCC(2)|F3F(2, 0x36, 0x151), CMPFCC(~2)|F3F(~2, ~0x36, ~0x151), "8,e,f", F_FLOAT
, HWCAP_HPC
, 0, v9b
},
2089 { "flcmps", CMPFCC(3)|F3F(2, 0x36, 0x151), CMPFCC(~3)|F3F(~2, ~0x36, ~0x151), "9,e,f", F_FLOAT
, HWCAP_HPC
, 0, v9b
},
2090 { "flcmpd", CMPFCC(0)|F3F(2, 0x36, 0x152), CMPFCC(~0)|F3F(~2, ~0x36, ~0x152), "6,v,B", F_FLOAT
, HWCAP_HPC
, 0, v9b
},
2091 { "flcmpd", CMPFCC(1)|F3F(2, 0x36, 0x152), CMPFCC(~1)|F3F(~2, ~0x36, ~0x152), "7,v,B", F_FLOAT
, HWCAP_HPC
, 0, v9b
},
2092 { "flcmpd", CMPFCC(2)|F3F(2, 0x36, 0x152), CMPFCC(~2)|F3F(~2, ~0x36, ~0x152), "8,v,B", F_FLOAT
, HWCAP_HPC
, 0, v9b
},
2093 { "flcmpd", CMPFCC(3)|F3F(2, 0x36, 0x152), CMPFCC(~3)|F3F(~2, ~0x36, ~0x152), "9,v,B", F_FLOAT
, HWCAP_HPC
, 0, v9b
},
2095 { "mwait", F3(2, 0x30, 0)|RD(28), F3(~2, ~0x30, ~0)|RD(~28)|RS1_G0
|ASI(~0), "2", 0, 0, HWCAP2_MWAIT
, v9b
}, /* mwait r */
2096 { "mwait", F3(2, 0x30, 1)|RD(28), F3(~2, ~0x30, ~1)|RD(~28)|RS1_G0
, "i", 0, 0, HWCAP2_MWAIT
, v9b
}, /* mwait imm */
2098 /* Other SPARC5 and VIS4.0 instructions. */
2100 { "subxc", F3(2, 0x36, 0)|OPF(0x41), F3(~2, ~0x36, ~0)|OPF(~0x41), "1,2,d", 0, 0, HWCAP2_SPARC5
, v9b
},
2101 { "subxccc", F3(2, 0x36, 0)|OPF(0x43), F3(~2, ~0x36, ~0)|OPF(~0x43), "1,2,d", 0, 0, HWCAP2_SPARC5
, v9b
},
2103 { "fpadd8", F3F(2, 0x36, 0x124), F3F(~2, ~0x36, ~0x124), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9b
},
2104 { "fpadds8", F3F(2, 0x36, 0x126), F3F(~2, ~0x36, ~0x126), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9b
},
2105 { "fpaddus8", F3F(2, 0x36, 0x127), F3F(~2, ~0x36, ~0x127), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9b
},
2106 { "fpaddus16", F3F(2, 0x36, 0x123), F3F(~2, ~0x36, ~0x123), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9b
},
2107 { "fpcmple8", F3F(2, 0x36, 0x034), F3F(~2, ~0x36, ~0x034), "v,B,d", 0, 0, HWCAP2_SPARC5
, v9b
},
2108 { "fpcmpgt8", F3F(2, 0x36, 0x03c), F3F(~2, ~0x36, ~0x03c), "v,B,d", 0, 0, HWCAP2_SPARC5
, v9b
},
2109 { "fpcmpule16", F3F(2, 0x36, 0x12e), F3F(~2, ~0x36, ~0x12e), "v,B,d", 0, 0, HWCAP2_SPARC5
, v9b
},
2110 { "fpcmpugt16", F3F(2, 0x36, 0x12b), F3F(~2, ~0x36, ~0x12b), "v,B,d", 0, 0, HWCAP2_SPARC5
, v9b
},
2111 { "fpcmpule32", F3F(2, 0x36, 0x12f), F3F(~2, ~0x36, ~0x12f), "v,B,d", 0, 0, HWCAP2_SPARC5
, v9b
},
2112 { "fpcmpugt32", F3F(2, 0x36, 0x12c), F3F(~2, ~0x36, ~0x12c), "v,B,d", 0, 0, HWCAP2_SPARC5
, v9b
},
2113 { "fpmax8", F3F(2, 0x36, 0x11d), F3F(~2, ~0x36, ~0x11d), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9b
},
2114 { "fpmax16", F3F(2, 0x36, 0x11e), F3F(~2, ~0x36, ~0x11e), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9b
},
2115 { "fpmax32", F3F(2, 0x36, 0x11f), F3F(~2, ~0x36, ~0x11f), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9b
},
2116 { "fpmaxu8", F3F(2, 0x36, 0x15d), F3F(~2, ~0x36, ~0x15d), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9b
},
2117 { "fpmaxu16", F3F(2, 0x36, 0x15e), F3F(~2, ~0x36, ~0x15e), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9b
},
2118 { "fpmaxu32", F3F(2, 0x36, 0x15f), F3F(~2, ~0x36, ~0x15f), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9b
},
2119 { "fpmin8", F3F(2, 0x36, 0x11a), F3F(~2, ~0x36, ~0x11a), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9b
},
2120 { "fpmin16", F3F(2, 0x36, 0x11b), F3F(~2, ~0x36, ~0x11b), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9b
},
2121 { "fpmin32", F3F(2, 0x36, 0x11c), F3F(~2, ~0x36, ~0x11c), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9b
},
2122 { "fpminu8", F3F(2, 0x36, 0x15a), F3F(~2, ~0x36, ~0x15a), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9b
},
2123 { "fpminu16", F3F(2, 0x36, 0x15b), F3F(~2, ~0x36, ~0x15b), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9b
},
2124 { "fpminu32", F3F(2, 0x36, 0x15c), F3F(~2, ~0x36, ~0x15c), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9b
},
2125 { "fpsub8", F3F(2, 0x36, 0x154), F3F(~2, ~0x36, ~0x154), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9b
},
2126 { "fpsubs8", F3F(2, 0x36, 0x156), F3F(~2, ~0x36, ~0x156), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9b
},
2127 { "fpsubus8", F3F(2, 0x36, 0x157), F3F(~2, ~0x36, ~0x157), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9b
},
2128 { "fpsubus16", F3F(2, 0x36, 0x153), F3F(~2, ~0x36, ~0x153), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9b
},
2130 /* More v9 specific insns, these need to come last so they do not clash
2131 with v9a instructions such as "edge8" which looks like impdep1. */
2133 #define IMPDEP(name, code) \
2134 { name, F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9notv9a }, \
2135 { name, F3(2, code, 1), F3(~2, ~code, ~1), "1,i,d", 0, 0, 0, v9notv9a }, \
2136 { name, F3(2, code, 0), F3(~2, ~code, ~0), "x,1,2,d", 0, 0, 0, v9notv9a }, \
2137 { name, F3(2, code, 0), F3(~2, ~code, ~0), "x,e,f,g", 0, 0, 0, v9notv9a }
2139 IMPDEP ("impdep1", 0x36),
2140 IMPDEP ("impdep2", 0x37),
2146 const int sparc_num_opcodes
= ((sizeof sparc_opcodes
)/(sizeof sparc_opcodes
[0]));
2148 /* Utilities for argument parsing. */
2156 /* Look up NAME in TABLE. */
2159 lookup_name (const arg
*table
, const char *name
)
2163 for (p
= table
; p
->name
; ++p
)
2164 if (strcmp (name
, p
->name
) == 0)
2170 /* Look up VALUE in TABLE. */
2173 lookup_value (const arg
*table
, int value
)
2177 for (p
= table
; p
->name
; ++p
)
2178 if (value
== p
->value
)
2186 static arg asi_table
[] =
2188 /* These are in the v9 architecture manual. */
2189 /* The shorter versions appear first, they're here because Sun's as has them.
2190 Sun's as uses #ASI_P_L instead of #ASI_PL (which appears in the
2191 UltraSPARC architecture manual). */
2193 { 0x0c, "#ASI_N_L" },
2194 { 0x10, "#ASI_AIUP" },
2195 { 0x11, "#ASI_AIUS" },
2196 { 0x18, "#ASI_AIUP_L" },
2197 { 0x19, "#ASI_AIUS_L" },
2200 { 0x82, "#ASI_PNF" },
2201 { 0x83, "#ASI_SNF" },
2202 { 0x88, "#ASI_P_L" },
2203 { 0x89, "#ASI_S_L" },
2204 { 0x8a, "#ASI_PNF_L" },
2205 { 0x8b, "#ASI_SNF_L" },
2206 { 0x04, "#ASI_NUCLEUS" },
2207 { 0x0c, "#ASI_NUCLEUS_LITTLE" },
2208 { 0x10, "#ASI_AS_IF_USER_PRIMARY" },
2209 { 0x11, "#ASI_AS_IF_USER_SECONDARY" },
2210 { 0x18, "#ASI_AS_IF_USER_PRIMARY_LITTLE" },
2211 { 0x19, "#ASI_AS_IF_USER_SECONDARY_LITTLE" },
2212 { 0x80, "#ASI_PRIMARY" },
2213 { 0x81, "#ASI_SECONDARY" },
2214 { 0x82, "#ASI_PRIMARY_NOFAULT" },
2215 { 0x83, "#ASI_SECONDARY_NOFAULT" },
2216 { 0x88, "#ASI_PRIMARY_LITTLE" },
2217 { 0x89, "#ASI_SECONDARY_LITTLE" },
2218 { 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE" },
2219 { 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE" },
2220 /* These are UltraSPARC and Niagara extensions. */
2221 { 0x14, "#ASI_PHYS_USE_EC" },
2222 { 0x15, "#ASI_PHYS_BYPASS_EC_E" },
2223 { 0x16, "#ASI_BLK_AIUP_4V" },
2224 { 0x17, "#ASI_BLK_AIUS_4V" },
2225 { 0x1c, "#ASI_PHYS_USE_EC_L" },
2226 { 0x1d, "#ASI_PHYS_BYPASS_EC_E_L" },
2227 { 0x1e, "#ASI_BLK_AIUP_L_4V" },
2228 { 0x1f, "#ASI_BLK_AIUS_L_4V" },
2229 { 0x20, "#ASI_SCRATCHPAD" },
2230 { 0x21, "#ASI_MMU" },
2231 { 0x23, "#ASI_BLK_INIT_QUAD_LDD_AIUS" },
2232 { 0x24, "#ASI_NUCLEUS_QUAD_LDD" },
2233 { 0x25, "#ASI_QUEUE" },
2234 { 0x26, "#ASI_QUAD_LDD_PHYS_4V" },
2235 { 0x2c, "#ASI_NUCLEUS_QUAD_LDD_L" },
2236 { 0x30, "#ASI_PCACHE_DATA_STATUS" },
2237 { 0x31, "#ASI_PCACHE_DATA" },
2238 { 0x32, "#ASI_PCACHE_TAG" },
2239 { 0x33, "#ASI_PCACHE_SNOOP_TAG" },
2240 { 0x34, "#ASI_QUAD_LDD_PHYS" },
2241 { 0x38, "#ASI_WCACHE_VALID_BITS" },
2242 { 0x39, "#ASI_WCACHE_DATA" },
2243 { 0x3a, "#ASI_WCACHE_TAG" },
2244 { 0x3b, "#ASI_WCACHE_SNOOP_TAG" },
2245 { 0x3c, "#ASI_QUAD_LDD_PHYS_L" },
2246 { 0x40, "#ASI_SRAM_FAST_INIT" },
2247 { 0x41, "#ASI_CORE_AVAILABLE" },
2248 { 0x41, "#ASI_CORE_ENABLE_STAT" },
2249 { 0x41, "#ASI_CORE_ENABLE" },
2250 { 0x41, "#ASI_XIR_STEERING" },
2251 { 0x41, "#ASI_CORE_RUNNING_RW" },
2252 { 0x41, "#ASI_CORE_RUNNING_W1S" },
2253 { 0x41, "#ASI_CORE_RUNNING_W1C" },
2254 { 0x41, "#ASI_CORE_RUNNING_STAT" },
2255 { 0x41, "#ASI_CMT_ERROR_STEERING" },
2256 { 0x41, "#ASI_DCACHE_INVALIDATE" },
2257 { 0x41, "#ASI_DCACHE_UTAG" },
2258 { 0x41, "#ASI_DCACHE_SNOOP_TAG" },
2259 { 0x42, "#ASI_DCACHE_INVALIDATE" },
2260 { 0x43, "#ASI_DCACHE_UTAG" },
2261 { 0x44, "#ASI_DCACHE_SNOOP_TAG" },
2262 { 0x45, "#ASI_LSU_CONTROL_REG" },
2263 { 0x45, "#ASI_DCU_CONTROL_REG" },
2264 { 0x46, "#ASI_DCACHE_DATA" },
2265 { 0x47, "#ASI_DCACHE_TAG" },
2266 { 0x48, "#ASI_INTR_DISPATCH_STAT" },
2267 { 0x49, "#ASI_INTR_RECEIVE" },
2268 { 0x4a, "#ASI_UPA_CONFIG" },
2269 { 0x4a, "#ASI_JBUS_CONFIG" },
2270 { 0x4a, "#ASI_SAFARI_CONFIG" },
2271 { 0x4a, "#ASI_SAFARI_ADDRESS" },
2272 { 0x4b, "#ASI_ESTATE_ERROR_EN" },
2273 { 0x4c, "#ASI_AFSR" },
2274 { 0x4d, "#ASI_AFAR" },
2275 { 0x4e, "#ASI_EC_TAG_DATA" },
2276 { 0x50, "#ASI_IMMU" },
2277 { 0x51, "#ASI_IMMU_TSB_8KB_PTR" },
2278 { 0x52, "#ASI_IMMU_TSB_16KB_PTR" },
2279 { 0x54, "#ASI_ITLB_DATA_IN" },
2280 { 0x55, "#ASI_ITLB_DATA_ACCESS" },
2281 { 0x56, "#ASI_ITLB_TAG_READ" },
2282 { 0x57, "#ASI_IMMU_DEMAP" },
2283 { 0x58, "#ASI_DMMU" },
2284 { 0x59, "#ASI_DMMU_TSB_8KB_PTR" },
2285 { 0x5a, "#ASI_DMMU_TSB_64KB_PTR" },
2286 { 0x5b, "#ASI_DMMU_TSB_DIRECT_PTR" },
2287 { 0x5c, "#ASI_DTLB_DATA_IN" },
2288 { 0x5d, "#ASI_DTLB_DATA_ACCESS" },
2289 { 0x5e, "#ASI_DTLB_TAG_READ" },
2290 { 0x5f, "#ASI_DMMU_DEMAP" },
2291 { 0x60, "#ASI_IIU_INST_TRAP" },
2292 { 0x63, "#ASI_INTR_ID" },
2293 { 0x63, "#ASI_CORE_ID" },
2294 { 0x63, "#ASI_CESR_ID" },
2295 { 0x66, "#ASI_IC_INSTR" },
2296 { 0x67, "#ASI_IC_TAG" },
2297 { 0x68, "#ASI_IC_STAG" },
2298 { 0x6e, "#ASI_IC_PRE_DECODE" },
2299 { 0x6f, "#ASI_IC_NEXT_FIELD" },
2300 { 0x6f, "#ASI_BRPRED_ARRAY" },
2301 { 0x70, "#ASI_BLK_AIUP" },
2302 { 0x71, "#ASI_BLK_AIUS" },
2303 { 0x72, "#ASI_MCU_CTRL_REG" },
2304 { 0x74, "#ASI_EC_DATA" },
2305 { 0x75, "#ASI_EC_CTRL" },
2306 { 0x76, "#ASI_EC_W" },
2307 { 0x77, "#ASI_UDB_ERROR_W" },
2308 { 0x77, "#ASI_UDB_CONTROL_W" },
2309 { 0x77, "#ASI_INTR_W" },
2310 { 0x77, "#ASI_INTR_DATAN_W" },
2311 { 0x77, "#ASI_INTR_DISPATCH_W" },
2312 { 0x78, "#ASI_BLK_AIUPL" },
2313 { 0x79, "#ASI_BLK_AIUSL" },
2314 { 0x7e, "#ASI_EC_R" },
2315 { 0x7f, "#ASI_UDBH_ERROR_R" },
2316 { 0x7f, "#ASI_UDBL_ERROR_R" },
2317 { 0x7f, "#ASI_UDBH_CONTROL_R" },
2318 { 0x7f, "#ASI_UDBL_CONTROL_R" },
2319 { 0x7f, "#ASI_INTR_R" },
2320 { 0x7f, "#ASI_INTR_DATAN_R" },
2321 { 0xc0, "#ASI_PST8_P" },
2322 { 0xc1, "#ASI_PST8_S" },
2323 { 0xc2, "#ASI_PST16_P" },
2324 { 0xc3, "#ASI_PST16_S" },
2325 { 0xc4, "#ASI_PST32_P" },
2326 { 0xc5, "#ASI_PST32_S" },
2327 { 0xc8, "#ASI_PST8_PL" },
2328 { 0xc9, "#ASI_PST8_SL" },
2329 { 0xca, "#ASI_PST16_PL" },
2330 { 0xcb, "#ASI_PST16_SL" },
2331 { 0xcc, "#ASI_PST32_PL" },
2332 { 0xcd, "#ASI_PST32_SL" },
2333 { 0xd0, "#ASI_FL8_P" },
2334 { 0xd1, "#ASI_FL8_S" },
2335 { 0xd2, "#ASI_FL16_P" },
2336 { 0xd3, "#ASI_FL16_S" },
2337 { 0xd8, "#ASI_FL8_PL" },
2338 { 0xd9, "#ASI_FL8_SL" },
2339 { 0xda, "#ASI_FL16_PL" },
2340 { 0xdb, "#ASI_FL16_SL" },
2341 { 0xe0, "#ASI_BLK_COMMIT_P", },
2342 { 0xe1, "#ASI_BLK_COMMIT_S", },
2343 { 0xe2, "#ASI_BLK_INIT_QUAD_LDD_P" },
2344 { 0xf0, "#ASI_BLK_P", },
2345 { 0xf1, "#ASI_BLK_S", },
2346 { 0xf8, "#ASI_BLK_PL", },
2347 { 0xf9, "#ASI_BLK_SL", },
2351 /* Return the value for ASI NAME, or -1 if not found. */
2354 sparc_encode_asi (const char *name
)
2356 return lookup_name (asi_table
, name
);
2359 /* Return the name for ASI value VALUE or NULL if not found. */
2362 sparc_decode_asi (int value
)
2364 return lookup_value (asi_table
, value
);
2367 /* Handle membar masks. */
2369 static arg membar_table
[] =
2372 { 0x20, "#MemIssue" },
2373 { 0x10, "#Lookaside" },
2374 { 0x08, "#StoreStore" },
2375 { 0x04, "#LoadStore" },
2376 { 0x02, "#StoreLoad" },
2377 { 0x01, "#LoadLoad" },
2381 /* Return the value for membar arg NAME, or -1 if not found. */
2384 sparc_encode_membar (const char *name
)
2386 return lookup_name (membar_table
, name
);
2389 /* Return the name for membar value VALUE or NULL if not found. */
2392 sparc_decode_membar (int value
)
2394 return lookup_value (membar_table
, value
);
2397 /* Handle prefetch args. */
2399 static arg prefetch_table
[] =
2404 { 3, "#one_write" },
2406 { 16, "#invalidate" },
2407 { 17, "#unified", },
2408 { 20, "#n_reads_strong", },
2409 { 21, "#one_read_strong", },
2410 { 22, "#n_writes_strong", },
2411 { 23, "#one_write_strong", },
2415 /* Return the value for prefetch arg NAME, or -1 if not found. */
2418 sparc_encode_prefetch (const char *name
)
2420 return lookup_name (prefetch_table
, name
);
2423 /* Return the name for prefetch value VALUE or NULL if not found. */
2426 sparc_decode_prefetch (int value
)
2428 return lookup_value (prefetch_table
, value
);
2431 /* Handle sparclet coprocessor registers. */
2433 static arg sparclet_cpreg_table
[] =
2445 /* Return the value for sparclet cpreg arg NAME, or -1 if not found. */
2448 sparc_encode_sparclet_cpreg (const char *name
)
2450 return lookup_name (sparclet_cpreg_table
, name
);
2453 /* Return the name for sparclet cpreg value VALUE or NULL if not found. */
2456 sparc_decode_sparclet_cpreg (int value
)
2458 return lookup_value (sparclet_cpreg_table
, value
);
projects / deliverable / binutils-gdb.git / blob