1 /* Table of opcodes for the sparc.
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this file; see the file COPYING. If not, write to the
18 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* FIXME-someday: perhaps the ,a's and such should be embedded in the
23 instruction's name rather than the args. This would make gas faster, pinsn
24 slower, but would mess up some macros a bit. xoxorich. */
28 #include "opcode/sparc.h"
30 /* Some defines to make life easy. */
31 #define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6)
32 #define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7)
33 #define MASK_V8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)
34 #define MASK_LEON SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_LEON)
35 #define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET)
36 #define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
37 #define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9)
38 #define MASK_V9A SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)
39 #define MASK_V9B SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B)
40 #define MASK_V9C SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9C)
41 #define MASK_V9D SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9D)
42 #define MASK_V9E SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9E)
43 #define MASK_V9V SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9V)
44 #define MASK_V9M SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9M)
45 #define MASK_M8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_M8)
47 /* Bit masks of architectures supporting the insn. */
49 #define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \
50 | MASK_SPARCLET | MASK_SPARCLITE \
51 | MASK_V9 | MASK_V9A | MASK_V9B \
52 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \
54 /* v6 insns not supported on the sparclet. */
55 #define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \
56 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B \
57 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \
59 #define v7 (MASK_V7 | MASK_V8 | MASK_LEON | MASK_SPARCLET \
60 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B \
61 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \
63 /* Although not all insns are implemented in hardware, sparclite is defined
64 to be a superset of v8. Unimplemented insns trap and are then theoretically
65 implemented in software.
66 It's not clear that the same is true for sparclet, although the docs
67 suggest it is. Rather than complicating things, the sparclet assembler
68 recognizes all v8 insns. */
69 #define v8 (MASK_V8 | MASK_LEON | MASK_SPARCLET | MASK_SPARCLITE \
70 | MASK_V9 | MASK_V9A | MASK_V9B \
71 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \
73 #define sparclet (MASK_SPARCLET)
74 /* sparclet insns supported by leon. */
75 #define letandleon (MASK_SPARCLET | MASK_LEON)
76 #define sparclite (MASK_SPARCLITE)
77 #define v9 (MASK_V9 | MASK_V9A | MASK_V9B \
78 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \
80 /* v9 insns supported by leon. */
81 #define v9andleon (MASK_V9 | MASK_V9A | MASK_V9B \
82 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \
83 | MASK_M8 | MASK_LEON)
84 #define v9a (MASK_V9A | MASK_V9B \
85 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \
87 #define v9b (MASK_V9B \
88 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \
90 #define v9c (MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \
92 #define v9d (MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M | MASK_M8)
93 #define v9e (MASK_V9E | MASK_V9V | MASK_V9M | MASK_M8)
94 #define v9v (MASK_V9V | MASK_V9M | MASK_M8)
95 #define v9m (MASK_V9M | MASK_M8)
98 /* v6 insns not supported by v9. */
99 #define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \
100 | MASK_SPARCLET | MASK_SPARCLITE)
101 /* v9a instructions which would appear to be aliases to v9's impdep's
103 #define v9notv9a (MASK_V9)
105 /* Hardware capability sets, used to keep sparc_opcode_archs easy to
107 #define HWS_V8 HWCAP_MUL32 | HWCAP_DIV32 | HWCAP_FSMULD
108 #define HWS_V9 HWS_V8 | HWCAP_POPC
109 #define HWS_VA HWS_V9 | HWCAP_VIS
110 #define HWS_VB HWS_VA | HWCAP_VIS2
111 #define HWS_VC HWS_VB | HWCAP_ASI_BLK_INIT
112 #define HWS_VD HWS_VC | HWCAP_FMAF | HWCAP_VIS3 | HWCAP_HPC
113 #define HWS_VE HWS_VD \
114 | HWCAP_AES | HWCAP_DES | HWCAP_KASUMI | HWCAP_CAMELLIA \
115 | HWCAP_MD5 | HWCAP_SHA1 | HWCAP_SHA256 |HWCAP_SHA512 | HWCAP_MPMUL \
116 | HWCAP_MONT | HWCAP_CRC32C | HWCAP_CBCOND | HWCAP_PAUSE
117 #define HWS_VV HWS_VE | HWCAP_FJFMAU | HWCAP_IMA
118 #define HWS_VM HWS_VV
119 #define HWS_VM8 HWS_VM
122 HWCAP2_VIS3B | HWCAP2_ADP | HWCAP2_SPARC5 | HWCAP2_MWAIT \
123 | HWCAP2_XMPMUL | HWCAP2_XMONT
124 #define HWS2_VM8 HWS2_VM \
125 | HWCAP2_SPARC6 | HWCAP2_ONADDSUB | HWCAP2_ONMUL | HWCAP2_ONDIV \
126 | HWCAP2_DICTUNP | HWCAP2_FPCMPSHL | HWCAP2_RLE | HWCAP2_SHA3
129 /* Table of opcode architectures.
130 The order is defined in opcode/sparc.h. */
132 const struct sparc_opcode_arch sparc_opcode_archs
[] =
134 { "v6", MASK_V6
, 0, 0 },
135 { "v7", MASK_V6
| MASK_V7
, 0, 0 },
136 { "v8", MASK_V6
| MASK_V7
| MASK_V8
, HWS_V8
, 0 },
137 { "leon", MASK_V6
| MASK_V7
| MASK_V8
| MASK_LEON
, HWS_V8
, 0 },
138 { "sparclet", MASK_V6
| MASK_V7
| MASK_V8
| MASK_SPARCLET
, HWS_V8
, 0 },
139 { "sparclite", MASK_V6
| MASK_V7
| MASK_V8
| MASK_SPARCLITE
, HWS_V8
, 0 },
140 /* ??? Don't some v8 priviledged insns conflict with v9? */
141 { "v9", MASK_V6
| MASK_V7
| MASK_V8
| MASK_V9
, HWS_V9
, 0 },
142 /* v9 with ultrasparc additions */
143 { "v9a", MASK_V6
| MASK_V7
| MASK_V8
| MASK_V9
| MASK_V9A
, HWS_VA
, 0 },
144 /* v9 with cheetah additions */
145 { "v9b", MASK_V6
| MASK_V7
| MASK_V8
| MASK_V9
| MASK_V9A
| MASK_V9B
, HWS_VB
, 0 },
146 /* v9 with UA2005 and T1 additions. */
147 { "v9c", (MASK_V6
| MASK_V7
| MASK_V8
| MASK_V9
| MASK_V9A
| MASK_V9B
148 | MASK_V9C
), HWS_VC
, 0 },
149 /* v9 with UA2007 and T3 additions. */
150 { "v9d", (MASK_V6
| MASK_V7
| MASK_V8
| MASK_V9
| MASK_V9A
| MASK_V9B
151 | MASK_V9C
| MASK_V9D
), HWS_VD
, 0 },
152 /* v9 with OSA2011 and T4 additions modulus integer multiply-add. */
153 { "v9e", (MASK_V6
| MASK_V7
| MASK_V8
| MASK_V9
| MASK_V9A
| MASK_V9B
154 | MASK_V9C
| MASK_V9D
| MASK_V9E
), HWS_VE
, 0 },
155 /* V9 with OSA2011 and T4 additions, integer multiply and Fujitsu fp
157 { "v9v", (MASK_V6
| MASK_V7
| MASK_V8
| MASK_V9
| MASK_V9A
| MASK_V9B
158 | MASK_V9C
| MASK_V9D
| MASK_V9E
| MASK_V9V
), HWS_VV
, 0 },
159 /* v9 with OSA2015 and M7 additions. */
160 { "v9m", (MASK_V6
| MASK_V7
| MASK_V8
| MASK_V9
| MASK_V9A
| MASK_V9B
161 | MASK_V9C
| MASK_V9D
| MASK_V9E
| MASK_V9V
| MASK_V9M
), HWS_VM
, HWS2_VM
},
162 /* v9 with OSA2017 and M8 additions. */
163 { "m8", (MASK_V6
| MASK_V7
| MASK_V8
| MASK_V9
| MASK_V9A
| MASK_V9B
164 | MASK_V9C
| MASK_V9D
| MASK_V9E
| MASK_V9V
| MASK_V9M
| MASK_M8
),
169 /* Given NAME, return it's architecture entry. */
171 enum sparc_opcode_arch_val
172 sparc_opcode_lookup_arch (const char *name
)
174 const struct sparc_opcode_arch
*p
;
176 for (p
= &sparc_opcode_archs
[0]; p
->name
; ++p
)
177 if (strcmp (name
, p
->name
) == 0)
178 return (enum sparc_opcode_arch_val
) (p
- &sparc_opcode_archs
[0]);
180 return SPARC_OPCODE_ARCH_BAD
;
183 /* Branch condition field. */
184 #define COND(x) (((x) & 0xf) << 25)
186 /* Compare And Branch condition field. */
187 #define CBCOND(x) (((x) & 0x1f) << 25)
189 /* v9: Move (MOVcc and FMOVcc) condition field. */
190 #define MCOND(x,i_or_f) ((((i_or_f) & 1) << 18) | (((x) >> 11) & (0xf << 14))) /* v9 */
192 /* v9: Move register (MOVRcc and FMOVRcc) condition field. */
193 #define RCOND(x) (((x) & 0x7) << 10) /* v9 */
195 #define CONDA (COND (0x8))
196 #define CONDCC (COND (0xd))
197 #define CONDCS (COND (0x5))
198 #define CONDE (COND (0x1))
199 #define CONDG (COND (0xa))
200 #define CONDGE (COND (0xb))
201 #define CONDGU (COND (0xc))
202 #define CONDL (COND (0x3))
203 #define CONDLE (COND (0x2))
204 #define CONDLEU (COND (0x4))
205 #define CONDN (COND (0x0))
206 #define CONDNE (COND (0x9))
207 #define CONDNEG (COND (0x6))
208 #define CONDPOS (COND (0xe))
209 #define CONDVC (COND (0xf))
210 #define CONDVS (COND (0x7))
212 #define CONDNZ CONDNE
214 #define CONDGEU CONDCC
215 #define CONDLU CONDCS
217 #define FCONDA (COND (0x8))
218 #define FCONDE (COND (0x9))
219 #define FCONDG (COND (0x6))
220 #define FCONDGE (COND (0xb))
221 #define FCONDL (COND (0x4))
222 #define FCONDLE (COND (0xd))
223 #define FCONDLG (COND (0x2))
224 #define FCONDN (COND (0x0))
225 #define FCONDNE (COND (0x1))
226 #define FCONDO (COND (0xf))
227 #define FCONDU (COND (0x7))
228 #define FCONDUE (COND (0xa))
229 #define FCONDUG (COND (0x5))
230 #define FCONDUGE (COND (0xc))
231 #define FCONDUL (COND (0x3))
232 #define FCONDULE (COND (0xe))
234 #define FCONDNZ FCONDNE
235 #define FCONDZ FCONDE
237 #define ICC (0) /* v9 */
238 #define XCC (1 << 12) /* v9 */
239 #define CBCOND_XCC (1 << 21)
240 #define FCC(x) (((x) & 0x3) << 11) /* v9 */
241 #define FBFCC(x) (((x) & 0x3) << 20) /* v9 */
243 /* The order of the opcodes in the table is significant:
245 * The assembler requires that all instances of the same mnemonic must
246 be consecutive. If they aren't, the assembler will bomb at runtime.
248 * The disassembler should not care about the order of the opcodes. */
250 /* Entries for commutative arithmetic operations. */
251 /* ??? More entries can make use of this. */
252 #define COMMUTEOP(opcode, op3, arch_mask) \
253 { opcode, F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0), "1,2,d", 0, 0, 0, arch_mask }, \
254 { opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "1,i,d", 0, 0, 0, arch_mask }, \
255 { opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "i,1,d", 0, 0, 0, arch_mask }
257 const struct sparc_opcode sparc_opcodes
[] = {
259 { "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", 0, 0, 0, v6
},
260 { "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0
, "[1],d", 0, 0, 0, v6
}, /* ld [rs1+%g0],d */
261 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", 0, 0, 0, v6
},
262 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", 0, 0, 0, v6
},
263 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0
, "[i],d", 0, 0, 0, v6
},
264 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6
}, /* ld [rs1+0],d */
265 { "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0), "[1+2],g", 0, 0, 0, v6
},
266 { "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0
, "[1],g", 0, 0, 0, v6
}, /* ld [rs1+%g0],d */
267 { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[1+i],g", 0, 0, 0, v6
},
268 { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[i+1],g", 0, 0, 0, v6
},
269 { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0
, "[i],g", 0, 0, 0, v6
},
270 { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0), "[1],g", 0, 0, 0, v6
}, /* ld [rs1+0],d */
272 { "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0), "[1+2],F", 0, 0, 0, v6
},
273 { "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0
|RD(~0),"[1],F", 0, 0, 0, v6
}, /* ld [rs1+%g0],d */
274 { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[1+i],F", 0, 0, 0, v6
},
275 { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[i+1],F", 0, 0, 0, v6
},
276 { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0
|RD(~0),"[i],F", 0, 0, 0, v6
},
277 { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, 0, 0, v6
}, /* ld [rs1+0],d */
279 { "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2],D", 0, 0, 0, v6notv9
},
280 { "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0
, "[1],D", 0, 0, 0, v6notv9
}, /* ld [rs1+%g0],d */
281 { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i],D", 0, 0, 0, v6notv9
},
282 { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1],D", 0, 0, 0, v6notv9
},
283 { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0
, "[i],D", 0, 0, 0, v6notv9
},
284 { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1],D", 0, 0, 0, v6notv9
}, /* ld [rs1+0],d */
285 { "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0), "[1+2],C", 0, 0, 0, v6notv9
},
286 { "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0
, "[1],C", 0, 0, 0, v6notv9
}, /* ld [rs1+%g0],d */
287 { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[1+i],C", 0, 0, 0, v6notv9
},
288 { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[i+1],C", 0, 0, 0, v6notv9
},
289 { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0
, "[i],C", 0, 0, 0, v6notv9
},
290 { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0), "[1],C", 0, 0, 0, v6notv9
}, /* ld [rs1+0],d */
292 /* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the
293 'ld' pseudo-op in v9. */
294 { "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", F_ALIAS
, 0, 0, v9
},
295 { "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0
, "[1],d", F_ALIAS
, 0, 0, v9
}, /* ld [rs1+%g0],d */
296 { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", F_ALIAS
, 0, 0, v9
},
297 { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", F_ALIAS
, 0, 0, v9
},
298 { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0
, "[i],d", F_ALIAS
, 0, 0, v9
},
299 { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", F_ALIAS
, 0, 0, v9
}, /* ld [rs1+0],d */
301 { "ldtw", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v9
},
302 { "ldtw", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v9
}, /* ldd [rs1+%g0],d */
303 { "ldtw", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", 0, 0, 0, v9
},
304 { "ldtw", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", 0, 0, 0, v9
},
305 { "ldtw", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0
, "[i],d", 0, 0, 0, v9
},
306 { "ldtw", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v9
}, /* ldd [rs1+0],d */
308 { "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", F_ALIAS
, 0, 0, v6
},
309 { "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", F_ALIAS
, 0, 0, v6
}, /* ldd [rs1+%g0],d */
310 { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", F_ALIAS
, 0, 0, v6
},
311 { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", F_ALIAS
, 0, 0, v6
},
312 { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0
, "[i],d", F_ALIAS
, 0, 0, v6
},
313 { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", F_ALIAS
, 0, 0, v6
}, /* ldd [rs1+0],d */
314 { "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0), "[1+2],H", F_ALIAS
, 0, 0, v6
},
315 { "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0), "[1],H", F_ALIAS
, 0, 0, v6
}, /* ldd [rs1+%g0],d */
316 { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[1+i],H", F_ALIAS
, 0, 0, v6
},
317 { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[i+1],H", F_ALIAS
, 0, 0, v6
},
318 { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0
, "[i],H", F_ALIAS
, 0, 0, v6
},
319 { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0), "[1],H", F_ALIAS
, 0, 0, v6
}, /* ldd [rs1+0],d */
321 { "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0), "[1+2],D", 0, 0, 0, v6notv9
},
322 { "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0), "[1],D", 0, 0, 0, v6notv9
}, /* ldd [rs1+%g0],d */
323 { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i],D", 0, 0, 0, v6notv9
},
324 { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1],D", 0, 0, 0, v6notv9
},
325 { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0
, "[i],D", 0, 0, 0, v6notv9
},
326 { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1],D", 0, 0, 0, v6notv9
}, /* ldd [rs1+0],d */
328 { "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0), "[1+2],J", 0, 0, 0, v9
},
329 { "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0), "[1],J", 0, 0, 0, v9
}, /* ldd [rs1+%g0],d */
330 { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[1+i],J", 0, 0, 0, v9
},
331 { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[i+1],J", 0, 0, 0, v9
},
332 { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0
, "[i],J", 0, 0, 0, v9
},
333 { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0), "[1],J", 0, 0, 0, v9
}, /* ldd [rs1+0],d */
335 { "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v6
},
336 { "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v6
}, /* ldsb [rs1+%g0],d */
337 { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[1+i],d", 0, 0, 0, v6
},
338 { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[i+1],d", 0, 0, 0, v6
},
339 { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0
, "[i],d", 0, 0, 0, v6
},
340 { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6
}, /* ldsb [rs1+0],d */
342 { "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v6
}, /* ldsh [rs1+%g0],d */
343 { "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v6
},
344 { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[1+i],d", 0, 0, 0, v6
},
345 { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[i+1],d", 0, 0, 0, v6
},
346 { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0
, "[i],d", 0, 0, 0, v6
},
347 { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6
}, /* ldsh [rs1+0],d */
349 { "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v6
},
350 { "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v6
}, /* ldstub [rs1+%g0],d */
351 { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[1+i],d", 0, 0, 0, v6
},
352 { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[i+1],d", 0, 0, 0, v6
},
353 { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0
, "[i],d", 0, 0, 0, v6
},
354 { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6
}, /* ldstub [rs1+0],d */
356 { "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v9
},
357 { "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v9
}, /* ldsw [rs1+%g0],d */
358 { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[1+i],d", 0, 0, 0, v9
},
359 { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[i+1],d", 0, 0, 0, v9
},
360 { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0
, "[i],d", 0, 0, 0, v9
},
361 { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v9
}, /* ldsw [rs1+0],d */
363 { "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v6
},
364 { "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v6
}, /* ldub [rs1+%g0],d */
365 { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[1+i],d", 0, 0, 0, v6
},
366 { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[i+1],d", 0, 0, 0, v6
},
367 { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0
, "[i],d", 0, 0, 0, v6
},
368 { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6
}, /* ldub [rs1+0],d */
370 { "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v6
},
371 { "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v6
}, /* lduh [rs1+%g0],d */
372 { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[1+i],d", 0, 0, 0, v6
},
373 { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[i+1],d", 0, 0, 0, v6
},
374 { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0
, "[i],d", 0, 0, 0, v6
},
375 { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6
}, /* lduh [rs1+0],d */
377 { "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v9
},
378 { "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v9
}, /* ldx [rs1+%g0],d */
379 { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[1+i],d", 0, 0, 0, v9
},
380 { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[i+1],d", 0, 0, 0, v9
},
381 { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0
, "[i],d", 0, 0, 0, v9
},
382 { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v9
}, /* ldx [rs1+0],d */
384 { "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F", 0, 0, 0, v9
},
385 { "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0
|RD(~1), "[1],F", 0, 0, 0, v9
}, /* ld [rs1+%g0],d */
386 { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F", 0, 0, 0, v9
},
387 { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F", 0, 0, 0, v9
},
388 { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0
|RD(~1), "[i],F", 0, 0, 0, v9
},
389 { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, 0, 0, v9
}, /* ld [rs1+0],d */
391 { "ldx", F3(3, 0x21, 0)|RD(3), F3(~3, ~0x21, ~0)|RD(~3), "[1+2],(", 0, HWCAP_VIS3
, HWCAP2_VIS3B
, v9d
}, /* ldx [rs1+rs2],%efsr */
392 { "ldx", F3(3, 0x21, 0)|RD(3), F3(~3, ~0x21, ~0)|RS2_G0
|RD(~3),"[1],(", 0, HWCAP_VIS3
, HWCAP2_VIS3B
, v9d
}, /* ldx [rs1],%efsr */
393 { "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RD(~3), "[1+i],(", 0, HWCAP_VIS3
, HWCAP2_VIS3B
, v9d
}, /* ldx [%rs1+0],%efsr */
394 { "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RD(~3), "[i+1],(", 0, HWCAP_VIS3
, HWCAP2_VIS3B
, v9d
}, /* ldx [0+%rs1],%efsr */
395 { "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RS1_G0
|RD(~3),"[i],(", 0, HWCAP_VIS3
, HWCAP2_VIS3B
, v9d
}, /* ldx [0],%efsr */
396 { "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~3),"[1],(", 0, HWCAP_VIS3
, HWCAP2_VIS3B
, v9d
}, /* ldx [%rs1], %efsr */
398 { "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", 0, 0, 0, v6
},
399 { "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0
, "[1]A,d", 0, 0, 0, v6
}, /* lda [rs1+%g0],d */
400 { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", 0, 0, 0, v9
},
401 { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", 0, 0, 0, v9
},
402 { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0
, "[i]o,d", 0, 0, 0, v9
},
403 { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9
}, /* ld [rs1+0],d */
404 { "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2]A,g", 0, 0, 0, v9
},
405 { "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0
, "[1]A,g", 0, 0, 0, v9
}, /* lda [rs1+%g0],d */
406 { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i]o,g", 0, 0, 0, v9
},
407 { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1]o,g", 0, 0, 0, v9
},
408 { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0
, "[i]o,g", 0, 0, 0, v9
},
409 { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1]o,g", 0, 0, 0, v9
}, /* ld [rs1+0],d */
411 /* Note that the LDTXA instructions share an opcode with the
412 (deprecated) LDTWA instructions below. They are differenciated by
413 the combination of the `i' instruction field and the ASI used in
417 { "ldtxa", F3(3, 0x13, 0)|ASI((asi)), F3(~3, ~0x13, ~0)|ASI(~(asi)), "[1+2]A,d", 0, HWCAP_ASI_BLK_INIT, 0, v9c }, \
418 { "ldtxa", F3(3, 0x13, 0)|ASI((asi)), F3(~3, ~0x13, ~0)|ASI(~(asi))|RS2_G0, "[1]A,d", 0, HWCAP_ASI_BLK_INIT, 0, v9c }
420 ldtxa (0x22), /* #ASI_TWINX_AIUP */
421 ldtxa (0x23), /* #ASI_TWINX_AIUS */
422 ldtxa (0x26), /* #ASI_TWINX_REAL */
423 ldtxa (0x27), /* #ASI_TWINX_N */
424 ldtxa (0x2A), /* #ASI_TWINX_AIUP_L */
425 ldtxa (0x2B), /* #ASI_TWINX_AIUS_L */
426 ldtxa (0x2E), /* #ASI_TWINX_REAL_L */
427 ldtxa (0x2F), /* #ASI_TWINX_NL */
428 ldtxa (0xE2), /* #ASI_TWINX_P */
429 ldtxa (0xE3), /* #ASI_TWINX_S */
430 ldtxa (0xEA), /* #ASI_TWINX_PL */
431 ldtxa (0xEB), /* #ASI_TWINX_SL */
433 { "ldtwa", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", 0, 0, 0, v9
},
434 { "ldtwa", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0
, "[1]A,d", 0, 0, 0, v9
}, /* ldda [rs1+%g0],d */
435 { "ldtwa", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", 0, 0, 0, v9
},
436 { "ldtwa", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d", 0, 0, 0, v9
},
437 { "ldtwa", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0
, "[i]o,d", 0, 0, 0, v9
},
438 { "ldtwa", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9
}, /* ld [rs1+0],d */
440 { "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", F_ALIAS
, 0, 0, v6
},
441 { "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0
, "[1]A,d", F_ALIAS
, 0, 0, v6
}, /* ldda [rs1+%g0],d */
442 { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", F_ALIAS
, 0, 0, v9
},
443 { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d", F_ALIAS
, 0, 0, v9
},
444 { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0
, "[i]o,d", F_ALIAS
, 0, 0, v9
},
445 { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS
, 0, 0, v9
}, /* ld [rs1+0],d */
447 { "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0), "[1+2]A,H", 0, 0, 0, v9
},
448 { "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0
, "[1]A,H", 0, 0, 0, v9
}, /* ldda [rs1+%g0],d */
449 { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i]o,H", 0, 0, 0, v9
},
450 { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1]o,H", 0, 0, 0, v9
},
451 { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0
, "[i]o,H", 0, 0, 0, v9
},
452 { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1]o,H", 0, 0, 0, v9
}, /* ld [rs1+0],d */
454 { "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0), "[1+2]A,J", 0, 0, 0, v9
},
455 { "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0
, "[1]A,J", 0, 0, 0, v9
}, /* ldd [rs1+%g0],d */
456 { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[1+i]o,J", 0, 0, 0, v9
},
457 { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[i+1]o,J", 0, 0, 0, v9
},
458 { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0
, "[i]o,J", 0, 0, 0, v9
},
459 { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0), "[1]o,J", 0, 0, 0, v9
}, /* ldd [rs1+0],d */
461 { "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0), "[1+2]A,d", 0, 0, 0, v6
},
462 { "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0
, "[1]A,d", 0, 0, 0, v6
}, /* ldsba [rs1+%g0],d */
463 { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[1+i]o,d", 0, 0, 0, v9
},
464 { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[i+1]o,d", 0, 0, 0, v9
},
465 { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0
, "[i]o,d", 0, 0, 0, v9
},
466 { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9
}, /* ld [rs1+0],d */
468 { "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0), "[1+2]A,d", 0, 0, 0, v6
},
469 { "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0
, "[1]A,d", 0, 0, 0, v6
}, /* ldsha [rs1+%g0],d */
470 { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[1+i]o,d", 0, 0, 0, v9
},
471 { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[i+1]o,d", 0, 0, 0, v9
},
472 { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0
, "[i]o,d", 0, 0, 0, v9
},
473 { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9
}, /* ld [rs1+0],d */
475 { "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0), "[1+2]A,d", 0, 0, 0, v6
},
476 { "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0
, "[1]A,d", 0, 0, 0, v6
}, /* ldstuba [rs1+%g0],d */
477 { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[1+i]o,d", 0, 0, 0, v9
},
478 { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[i+1]o,d", 0, 0, 0, v9
},
479 { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0
, "[i]o,d", 0, 0, 0, v9
},
480 { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9
}, /* ld [rs1+0],d */
482 { "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0), "[1+2]A,d", 0, 0, 0, v9
},
483 { "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0
, "[1]A,d", 0, 0, 0, v9
}, /* lda [rs1+%g0],d */
484 { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[1+i]o,d", 0, 0, 0, v9
},
485 { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[i+1]o,d", 0, 0, 0, v9
},
486 { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0
, "[i]o,d", 0, 0, 0, v9
},
487 { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9
}, /* ld [rs1+0],d */
489 { "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0), "[1+2]A,d", 0, 0, 0, v6
},
490 { "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0
, "[1]A,d", 0, 0, 0, v6
}, /* lduba [rs1+%g0],d */
491 { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[1+i]o,d", 0, 0, 0, v9
},
492 { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[i+1]o,d", 0, 0, 0, v9
},
493 { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0
, "[i]o,d", 0, 0, 0, v9
},
494 { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9
}, /* ld [rs1+0],d */
496 { "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0), "[1+2]A,d", 0, 0, 0, v6
},
497 { "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0
, "[1]A,d", 0, 0, 0, v6
}, /* lduha [rs1+%g0],d */
498 { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[1+i]o,d", 0, 0, 0, v9
},
499 { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[i+1]o,d", 0, 0, 0, v9
},
500 { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0
, "[i]o,d", 0, 0, 0, v9
},
501 { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9
}, /* ld [rs1+0],d */
503 { "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", F_ALIAS
, 0, 0, v9
}, /* lduwa === lda */
504 { "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0
, "[1]A,d", F_ALIAS
, 0, 0, v9
}, /* lda [rs1+%g0],d */
505 { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", F_ALIAS
, 0, 0, v9
},
506 { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", F_ALIAS
, 0, 0, v9
},
507 { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0
, "[i]o,d", F_ALIAS
, 0, 0, v9
},
508 { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS
, 0, 0, v9
}, /* ld [rs1+0],d */
510 { "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0), "[1+2]A,d", 0, 0, 0, v9
},
511 { "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0
, "[1]A,d", 0, 0, 0, v9
}, /* lda [rs1+%g0],d */
512 { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[1+i]o,d", 0, 0, 0, v9
},
513 { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[i+1]o,d", 0, 0, 0, v9
},
514 { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0
, "[i]o,d", 0, 0, 0, v9
},
515 { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9
}, /* ld [rs1+0],d */
517 { "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", 0, 0, 0, v6
},
518 { "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, 0, v6
}, /* st d,[rs1+%g0] */
519 { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", 0, 0, 0, v6
},
520 { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", 0, 0, 0, v6
},
521 { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0
, "d,[i]", 0, 0, 0, v6
},
522 { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", 0, 0, 0, v6
}, /* st d,[rs1+0] */
523 { "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0), "g,[1+2]", 0, 0, 0, v6
},
524 { "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0), "g,[1]", 0, 0, 0, v6
}, /* st d[rs1+%g0] */
525 { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[1+i]", 0, 0, 0, v6
},
526 { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[i+1]", 0, 0, 0, v6
},
527 { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0
, "g,[i]", 0, 0, 0, v6
},
528 { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0), "g,[1]", 0, 0, 0, v6
}, /* st d,[rs1+0] */
530 { "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0), "D,[1+2]", 0, 0, 0, v6notv9
},
531 { "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0), "D,[1]", 0, 0, 0, v6notv9
}, /* st d,[rs1+%g0] */
532 { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[1+i]", 0, 0, 0, v6notv9
},
533 { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[i+1]", 0, 0, 0, v6notv9
},
534 { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0
, "D,[i]", 0, 0, 0, v6notv9
},
535 { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "D,[1]", 0, 0, 0, v6notv9
}, /* st d,[rs1+0] */
536 { "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0), "C,[1+2]", 0, 0, 0, v6notv9
},
537 { "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0), "C,[1]", 0, 0, 0, v6notv9
}, /* st d,[rs1+%g0] */
538 { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[1+i]", 0, 0, 0, v6notv9
},
539 { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[i+1]", 0, 0, 0, v6notv9
},
540 { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0
, "C,[i]", 0, 0, 0, v6notv9
},
541 { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0), "C,[1]", 0, 0, 0, v6notv9
}, /* st d,[rs1+0] */
543 { "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0
|ASI(~0), "F,[1+2]", 0, 0, 0, v6
},
544 { "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0
|ASI_RS2(~0), "F,[1]", 0, 0, 0, v6
}, /* st d,[rs1+%g0] */
545 { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0
, "F,[1+i]", 0, 0, 0, v6
},
546 { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0
, "F,[i+1]", 0, 0, 0, v6
},
547 { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0
|RS1_G0
, "F,[i]", 0, 0, 0, v6
},
548 { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0
|SIMM13(~0), "F,[1]", 0, 0, 0, v6
}, /* st d,[rs1+0] */
550 { "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS
, 0, 0, v9
},
551 { "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS
, 0, 0, v9
}, /* st d,[rs1+%g0] */
552 { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS
, 0, 0, v9
},
553 { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS
, 0, 0, v9
},
554 { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0
, "d,[i]", F_ALIAS
, 0, 0, v9
},
555 { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS
, 0, 0, v9
}, /* st d,[rs1+0] */
556 { "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS
, 0, 0, v9
},
557 { "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS
, 0, 0, v9
}, /* st d,[rs1+%g0] */
558 { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS
, 0, 0, v9
},
559 { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS
, 0, 0, v9
},
560 { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0
, "d,[i]", F_ALIAS
, 0, 0, v9
},
561 { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS
, 0, 0, v9
}, /* st d,[rs1+0] */
562 { "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS
, 0, 0, v9
},
563 { "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS
, 0, 0, v9
}, /* st d,[rs1+%g0] */
564 { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS
, 0, 0, v9
},
565 { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS
, 0, 0, v9
},
566 { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0
, "d,[i]", F_ALIAS
, 0, 0, v9
},
567 { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS
, 0, 0, v9
}, /* st d,[rs1+0] */
569 { "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS
, 0, 0, v6
},
570 { "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS
, 0, 0, v6
}, /* st d,[rs1+%g0] */
571 { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS
, 0, 0, v6
},
572 { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS
, 0, 0, v6
},
573 { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0
, "d,[i]", F_ALIAS
, 0, 0, v6
},
574 { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS
, 0, 0, v6
}, /* st d,[rs1+0] */
576 { "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", 0, 0, 0, v6
},
577 { "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", 0, 0, 0, v6
}, /* sta d,[rs1+%g0] */
578 { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", 0, 0, 0, v9
},
579 { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", 0, 0, 0, v9
},
580 { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0
, "d,[i]o", 0, 0, 0, v9
},
581 { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", 0, 0, 0, v9
}, /* st d,[rs1+0] */
583 { "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0), "g,[1+2]A", 0, 0, 0, v9
},
584 { "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0), "g,[1]A", 0, 0, 0, v9
}, /* sta d,[rs1+%g0] */
585 { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[1+i]o", 0, 0, 0, v9
},
586 { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[i+1]o", 0, 0, 0, v9
},
587 { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0
, "g,[i]o", 0, 0, 0, v9
},
588 { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "g,[1]o", 0, 0, 0, v9
}, /* st d,[rs1+0] */
590 { "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS
, 0, 0, v9
},
591 { "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS
, 0, 0, v9
}, /* sta d,[rs1+%g0] */
592 { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS
, 0, 0, v9
},
593 { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS
, 0, 0, v9
},
594 { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0
, "d,[i]o", F_ALIAS
, 0, 0, v9
},
595 { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS
, 0, 0, v9
}, /* st d,[rs1+0] */
596 { "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS
, 0, 0, v9
},
597 { "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS
, 0, 0, v9
}, /* sta d,[rs1+%g0] */
598 { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS
, 0, 0, v9
},
599 { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS
, 0, 0, v9
},
600 { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0
, "d,[i]o", F_ALIAS
, 0, 0, v9
},
601 { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS
, 0, 0, v9
}, /* st d,[rs1+0] */
602 { "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS
, 0, 0, v9
},
603 { "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS
, 0, 0, v9
}, /* sta d,[rs1+%g0] */
604 { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS
, 0, 0, v9
},
605 { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS
, 0, 0, v9
},
606 { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0
, "d,[i]o", F_ALIAS
, 0, 0, v9
},
607 { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS
, 0, 0, v9
}, /* st d,[rs1+0] */
609 { "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", 0, 0, 0, v6
},
610 { "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, 0, v6
}, /* stb d,[rs1+%g0] */
611 { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", 0, 0, 0, v6
},
612 { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", 0, 0, 0, v6
},
613 { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0
, "d,[i]", 0, 0, 0, v6
},
614 { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", 0, 0, 0, v6
}, /* stb d,[rs1+0] */
616 { "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS
, 0, 0, v6
},
617 { "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS
, 0, 0, v6
}, /* stb d,[rs1+%g0] */
618 { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS
, 0, 0, v6
},
619 { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS
, 0, 0, v6
},
620 { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0
, "d,[i]", F_ALIAS
, 0, 0, v6
},
621 { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS
, 0, 0, v6
}, /* stb d,[rs1+0] */
622 { "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS
, 0, 0, v6
},
623 { "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS
, 0, 0, v6
}, /* stb d,[rs1+%g0] */
624 { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS
, 0, 0, v6
},
625 { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS
, 0, 0, v6
},
626 { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0
, "d,[i]", F_ALIAS
, 0, 0, v6
},
627 { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS
, 0, 0, v6
}, /* stb d,[rs1+0] */
629 { "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", 0, 0, 0, v6
},
630 { "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", 0, 0, 0, v6
}, /* stba d,[rs1+%g0] */
631 { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", 0, 0, 0, v9
},
632 { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", 0, 0, 0, v9
},
633 { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0
, "d,[i]o", 0, 0, 0, v9
},
634 { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", 0, 0, 0, v9
}, /* stb d,[rs1+0] */
636 { "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS
, 0, 0, v6
},
637 { "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS
, 0, 0, v6
}, /* stba d,[rs1+%g0] */
638 { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS
, 0, 0, v9
},
639 { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS
, 0, 0, v9
},
640 { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0
, "d,[i]o", F_ALIAS
, 0, 0, v9
},
641 { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS
, 0, 0, v9
}, /* stb d,[rs1+0] */
642 { "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS
, 0, 0, v6
},
643 { "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS
, 0, 0, v6
}, /* stba d,[rs1+%g0] */
644 { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS
, 0, 0, v9
},
645 { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS
, 0, 0, v9
},
646 { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0
, "d,[i]o", F_ALIAS
, 0, 0, v9
},
647 { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS
, 0, 0, v9
}, /* stb d,[rs1+0] */
649 { "sttw", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", 0, 0, 0, v9
},
650 { "sttw", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, 0, v9
}, /* std d,[rs1+%g0] */
651 { "sttw", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", 0, 0, 0, v9
},
652 { "sttw", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", 0, 0, 0, v9
},
653 { "sttw", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0
, "d,[i]", 0, 0, 0, v9
},
654 { "sttw", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", 0, 0, 0, v9
}, /* std d,[rs1+0] */
656 { "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", F_PREF_ALIAS
, 0, 0, v6
},
657 { "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", F_PREF_ALIAS
, 0, 0, v6
}, /* std d,[rs1+%g0] */
658 { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", F_PREF_ALIAS
, 0, 0, v6
},
659 { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", F_PREF_ALIAS
, 0, 0, v6
},
660 { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0
, "d,[i]", F_PREF_ALIAS
, 0, 0, v6
},
661 { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", F_PREF_ALIAS
, 0, 0, v6
}, /* std d,[rs1+0] */
663 { "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "q,[1+2]", 0, 0, 0, v6notv9
},
664 { "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "q,[1]", 0, 0, 0, v6notv9
}, /* std d,[rs1+%g0] */
665 { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[1+i]", 0, 0, 0, v6notv9
},
666 { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[i+1]", 0, 0, 0, v6notv9
},
667 { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0
, "q,[i]", 0, 0, 0, v6notv9
},
668 { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "q,[1]", 0, 0, 0, v6notv9
}, /* std d,[rs1+0] */
669 { "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0), "H,[1+2]", 0, 0, 0, v6
},
670 { "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0), "H,[1]", 0, 0, 0, v6
}, /* std d,[rs1+%g0] */
671 { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[1+i]", 0, 0, 0, v6
},
672 { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[i+1]", 0, 0, 0, v6
},
673 { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0
, "H,[i]", 0, 0, 0, v6
},
674 { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0), "H,[1]", 0, 0, 0, v6
}, /* std d,[rs1+0] */
676 { "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "Q,[1+2]", 0, 0, 0, v6notv9
},
677 { "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "Q,[1]", 0, 0, 0, v6notv9
}, /* std d,[rs1+%g0] */
678 { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[1+i]", 0, 0, 0, v6notv9
},
679 { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[i+1]", 0, 0, 0, v6notv9
},
680 { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0
, "Q,[i]", 0, 0, 0, v6notv9
},
681 { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "Q,[1]", 0, 0, 0, v6notv9
}, /* std d,[rs1+0] */
682 { "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0), "D,[1+2]", 0, 0, 0, v6notv9
},
683 { "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0), "D,[1]", 0, 0, 0, v6notv9
}, /* std d,[rs1+%g0] */
684 { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[1+i]", 0, 0, 0, v6notv9
},
685 { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[i+1]", 0, 0, 0, v6notv9
},
686 { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0
, "D,[i]", 0, 0, 0, v6notv9
},
687 { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "D,[1]", 0, 0, 0, v6notv9
}, /* std d,[rs1+0] */
689 { "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", F_ALIAS
, 0, 0, v6
},
690 { "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS
, 0, 0, v6
}, /* std d,[rs1+%g0] */
691 { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", F_ALIAS
, 0, 0, v6
},
692 { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", F_ALIAS
, 0, 0, v6
},
693 { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0
, "d,[i]", F_ALIAS
, 0, 0, v6
},
694 { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", F_ALIAS
, 0, 0, v6
}, /* std d,[rs1+0] */
696 { "sttwa", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", 0, 0, 0, v9
},
697 { "sttwa", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", 0, 0, 0, v9
}, /* stda d,[rs1+%g0] */
698 { "sttwa", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o", 0, 0, 0, v9
},
699 { "sttwa", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o", 0, 0, 0, v9
},
700 { "sttwa", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0
, "d,[i]o", 0, 0, 0, v9
},
701 { "sttwa", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", 0, 0, 0, v9
}, /* std d,[rs1+0] */
703 { "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", F_ALIAS
, 0, 0, v6
},
704 { "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", F_ALIAS
, 0, 0, v6
}, /* stda d,[rs1+%g0] */
705 { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o", F_ALIAS
, 0, 0, v9
},
706 { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o", F_ALIAS
, 0, 0, v9
},
707 { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0
, "d,[i]o", F_ALIAS
, 0, 0, v9
},
708 { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS
, 0, 0, v9
}, /* std d,[rs1+0] */
709 { "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0), "H,[1+2]A", 0, 0, 0, v9
},
710 { "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0), "H,[1]A", 0, 0, 0, v9
}, /* stda d,[rs1+%g0] */
711 { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[1+i]o", 0, 0, 0, v9
},
712 { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[i+1]o", 0, 0, 0, v9
},
713 { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0
, "H,[i]o", 0, 0, 0, v9
},
714 { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "H,[1]o", 0, 0, 0, v9
}, /* std d,[rs1+0] */
716 { "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", 0, 0, 0, v6
},
717 { "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, 0, v6
}, /* sth d,[rs1+%g0] */
718 { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", 0, 0, 0, v6
},
719 { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", 0, 0, 0, v6
},
720 { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0
, "d,[i]", 0, 0, 0, v6
},
721 { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", 0, 0, 0, v6
}, /* sth d,[rs1+0] */
723 { "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS
, 0, 0, v6
},
724 { "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS
, 0, 0, v6
}, /* sth d,[rs1+%g0] */
725 { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS
, 0, 0, v6
},
726 { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS
, 0, 0, v6
},
727 { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0
, "d,[i]", F_ALIAS
, 0, 0, v6
},
728 { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS
, 0, 0, v6
}, /* sth d,[rs1+0] */
729 { "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS
, 0, 0, v6
},
730 { "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS
, 0, 0, v6
}, /* sth d,[rs1+%g0] */
731 { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS
, 0, 0, v6
},
732 { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS
, 0, 0, v6
},
733 { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0
, "d,[i]", F_ALIAS
, 0, 0, v6
},
734 { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS
, 0, 0, v6
}, /* sth d,[rs1+0] */
736 { "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", 0, 0, 0, v6
},
737 { "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", 0, 0, 0, v6
}, /* stha ,[rs1+%g0] */
738 { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", 0, 0, 0, v9
},
739 { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", 0, 0, 0, v9
},
740 { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0
, "d,[i]o", 0, 0, 0, v9
},
741 { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", 0, 0, 0, v9
}, /* sth d,[rs1+0] */
743 { "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS
, 0, 0, v6
},
744 { "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS
, 0, 0, v6
}, /* stha ,[rs1+%g0] */
745 { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS
, 0, 0, v9
},
746 { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS
, 0, 0, v9
},
747 { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0
, "d,[i]o", F_ALIAS
, 0, 0, v9
},
748 { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS
, 0, 0, v9
}, /* sth d,[rs1+0] */
749 { "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS
, 0, 0, v6
},
750 { "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS
, 0, 0, v6
}, /* stha ,[rs1+%g0] */
751 { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS
, 0, 0, v9
},
752 { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS
, 0, 0, v9
},
753 { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0
, "d,[i]o", F_ALIAS
, 0, 0, v9
},
754 { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS
, 0, 0, v9
}, /* sth d,[rs1+0] */
756 { "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0), "d,[1+2]", 0, 0, 0, v9
},
757 { "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, 0, v9
}, /* stx d,[rs1+%g0] */
758 { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[1+i]", 0, 0, 0, v9
},
759 { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[i+1]", 0, 0, 0, v9
},
760 { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0
, "d,[i]", 0, 0, 0, v9
},
761 { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0), "d,[1]", 0, 0, 0, v9
}, /* stx d,[rs1+0] */
763 { "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1), "F,[1+2]", 0, 0, 0, v9
},
764 { "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, 0, 0, v9
}, /* stx d,[rs1+%g0] */
765 { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[1+i]", 0, 0, 0, v9
},
766 { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[i+1]", 0, 0, 0, v9
},
767 { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0
|RD(~1), "F,[i]", 0, 0, 0, v9
},
768 { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, 0, 0, v9
}, /* stx d,[rs1+0] */
770 { "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0), "d,[1+2]A", 0, 0, 0, v9
},
771 { "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0), "d,[1]A", 0, 0, 0, v9
}, /* stxa d,[rs1+%g0] */
772 { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[1+i]o", 0, 0, 0, v9
},
773 { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[i+1]o", 0, 0, 0, v9
},
774 { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0
, "d,[i]o", 0, 0, 0, v9
},
775 { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0), "d,[1]o", 0, 0, 0, v9
}, /* stx d,[rs1+0] */
777 { "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "J,[1+2]", 0, 0, 0, v9
},
778 { "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "J,[1]", 0, 0, 0, v9
}, /* stq [rs1+%g0] */
779 { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[1+i]", 0, 0, 0, v9
},
780 { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[i+1]", 0, 0, 0, v9
},
781 { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0
, "J,[i]", 0, 0, 0, v9
},
782 { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "J,[1]", 0, 0, 0, v9
}, /* stq [rs1+0] */
784 { "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "J,[1+2]A", 0, 0, 0, v9
},
785 { "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "J,[1]A", 0, 0, 0, v9
}, /* stqa [rs1+%g0] */
786 { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[1+i]o", 0, 0, 0, v9
},
787 { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[i+1]o", 0, 0, 0, v9
},
788 { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0
, "J,[i]o", 0, 0, 0, v9
},
789 { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "J,[1]o", 0, 0, 0, v9
}, /* stqa [rs1+0] */
791 { "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v7
},
792 { "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v7
}, /* swap [rs1+%g0],d */
793 { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[1+i],d", 0, 0, 0, v7
},
794 { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[i+1],d", 0, 0, 0, v7
},
795 { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0
, "[i],d", 0, 0, 0, v7
},
796 { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v7
}, /* swap [rs1+0],d */
798 { "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0), "[1+2]A,d", 0, 0, 0, v7
},
799 { "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0), "[1]A,d", 0, 0, 0, v7
}, /* swapa [rs1+%g0],d */
800 { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[1+i]o,d", 0, 0, 0, v9
},
801 { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[i+1]o,d", 0, 0, 0, v9
},
802 { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0
, "[i]o,d", 0, 0, 0, v9
},
803 { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9
}, /* swap [rs1+0],d */
805 { "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
806 { "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0
|RS1_G0
|ASI_RS2(~0), "", 0, 0, 0, v6
}, /* restore %g0,%g0,%g0 */
807 { "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1), "1,i,d", 0, 0, 0, v6
},
808 { "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0
|RS1_G0
|SIMM13(~0), "", 0, 0, 0, v6
}, /* restore %g0,0,%g0 */
810 { "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0
|ASI(~0), "1+2", F_UNBR
|F_DELAYED
, 0, 0, v6notv9
}, /* rett rs1+rs2 */
811 { "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0
|ASI_RS2(~0), "1", F_UNBR
|F_DELAYED
, 0, 0, v6notv9
}, /* rett rs1,%g0 */
812 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0
, "1+i", F_UNBR
|F_DELAYED
, 0, 0, v6notv9
}, /* rett rs1+X */
813 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0
, "i+1", F_UNBR
|F_DELAYED
, 0, 0, v6notv9
}, /* rett X+rs1 */
814 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0
|RS1_G0
, "i", F_UNBR
|F_DELAYED
, 0, 0, v6notv9
}, /* rett X+rs1 */
815 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0
|RS1_G0
, "i", F_UNBR
|F_DELAYED
, 0, 0, v6notv9
}, /* rett X */
816 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0
|SIMM13(~0), "1", F_UNBR
|F_DELAYED
, 0, 0, v6notv9
}, /* rett rs1+0 */
818 { "save", F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
819 { "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "1,i,d", 0, 0, 0, v6
},
820 { "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "i,1,d", 0, 0, 0, v6
}, /* Sun assembler compatibility */
821 { "save", 0x81e00000, ~0x81e00000, "", F_ALIAS
, 0, 0, v6
},
823 { "ret", F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8), "", F_UNBR
|F_DELAYED
, 0, 0, v6
}, /* jmpl %i7+8,%g0 */
824 { "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR
|F_DELAYED
, 0, 0, v6
}, /* jmpl %o7+8,%g0 */
826 { "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0), "1+2,d", F_JSR
|F_DELAYED
, 0, 0, v6
},
827 { "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0), "1,d", F_JSR
|F_DELAYED
, 0, 0, v6
}, /* jmpl rs1+%g0,d */
828 { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0), "1,d", F_JSR
|F_DELAYED
, 0, 0, v6
}, /* jmpl rs1+0,d */
829 { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0
, "i,d", F_JSR
|F_DELAYED
, 0, 0, v6
}, /* jmpl %g0+i,d */
830 { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "1+i,d", F_JSR
|F_DELAYED
, 0, 0, v6
},
831 { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "i+1,d", F_JSR
|F_DELAYED
, 0, 0, v6
},
833 { "done", F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0
|SIMM13(~0), "", 0, 0, 0, v9
},
834 { "retry", F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0
|SIMM13(~0), "", 0, 0, 0, v9
},
835 { "saved", F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0
|SIMM13(~0), "", 0, 0, 0, v9
},
836 { "restored", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0
|SIMM13(~0), "", 0, 0, 0, v9
},
837 { "allclean", F3(2, 0x31, 0)|RD(2), F3(~2, ~0x31, ~0)|RD(~2)|RS1_G0
|SIMM13(~0), "", 0, 0, 0, v9
},
838 { "otherw", F3(2, 0x31, 0)|RD(3), F3(~2, ~0x31, ~0)|RD(~3)|RS1_G0
|SIMM13(~0), "", 0, 0, 0, v9
},
839 { "normalw", F3(2, 0x31, 0)|RD(4), F3(~2, ~0x31, ~0)|RD(~4)|RS1_G0
|SIMM13(~0), "", 0, 0, 0, v9
},
840 { "invalw", F3(2, 0x31, 0)|RD(5), F3(~2, ~0x31, ~0)|RD(~5)|RS1_G0
|SIMM13(~0), "", 0, 0, 0, v9
},
841 { "sir", F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0
, "i", 0, 0, 0, v9
},
843 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "[1+2]", 0, 0, 0, v9
},
844 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "[1]", 0, 0, 0, v9
}, /* flush rs1+%g0 */
845 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "[1]", 0, 0, 0, v9
}, /* flush rs1+0 */
846 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0
, "[i]", 0, 0, 0, v9
}, /* flush %g0+i */
847 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "[1+i]", 0, 0, 0, v9
},
848 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "[i+1]", 0, 0, 0, v9
},
850 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS
, 0, 0, v8
},
851 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS
, 0, 0, v8
}, /* flush rs1+%g0 */
852 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS
, 0, 0, v8
}, /* flush rs1+0 */
853 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0
, "i", F_ALIAS
, 0, 0, v8
}, /* flush %g0+i */
854 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS
, 0, 0, v8
},
855 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS
, 0, 0, v8
},
857 /* IFLUSH was renamed to FLUSH in v8. */
858 { "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS
, 0, 0, v6
},
859 { "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS
, 0, 0, v6
}, /* flush rs1+%g0 */
860 { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS
, 0, 0, v6
}, /* flush rs1+0 */
861 { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0
, "i", F_ALIAS
, 0, 0, v6
},
862 { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS
, 0, 0, v6
},
863 { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS
, 0, 0, v6
},
865 { "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0), "1+2", 0, 0, 0, v9
},
866 { "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0), "1", 0, 0, 0, v9
}, /* return rs1+%g0 */
867 { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0), "1", 0, 0, 0, v9
}, /* return rs1+0 */
868 { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0
, "i", 0, 0, 0, v9
}, /* return %g0+i */
869 { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "1+i", 0, 0, 0, v9
},
870 { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "i+1", 0, 0, 0, v9
},
872 { "flushw", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0
|RS1_G0
|ASI_RS2(~0), "", 0, 0, 0, v9
},
874 { "membar", F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0
|RS1(~0xf)|SIMM13(~127), "K", 0, 0, 0, v9
},
875 { "stbar", F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0
|RS1(~0xf)|SIMM13(~0), "", 0, 0, 0, v8
},
877 { "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0), "[1+2],*", 0, 0, 0, v9
},
878 { "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0
, "[1],*", 0, 0, 0, v9
}, /* prefetch [rs1+%g0],prefetch_fcn */
879 { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[1+i],*", 0, 0, 0, v9
},
880 { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[i+1],*", 0, 0, 0, v9
},
881 { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0
, "[i],*", 0, 0, 0, v9
},
882 { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0), "[1],*", 0, 0, 0, v9
}, /* prefetch [rs1+0],prefetch_fcn */
883 { "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0), "[1+2]A,*", 0, 0, 0, v9
},
884 { "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0
, "[1]A,*", 0, 0, 0, v9
}, /* prefetcha [rs1+%g0],prefetch_fcn */
885 { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[1+i]o,*", 0, 0, 0, v9
},
886 { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[i+1]o,*", 0, 0, 0, v9
},
887 { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0
, "[i]o,*", 0, 0, 0, v9
},
888 { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0), "[1]o,*", 0, 0, 0, v9
}, /* prefetcha [rs1+0],d */
890 { "sll", F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, 0, 0, v6
},
891 { "sll", F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, 0, 0, v6
},
892 { "sra", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, 0, 0, v6
},
893 { "sra", F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, 0, 0, v6
},
894 { "srl", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, 0, 0, v6
},
895 { "srl", F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, 0, 0, v6
},
897 { "sllx", F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5), "1,2,d", 0, 0, 0, v9
},
898 { "sllx", F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6), "1,Y,d", 0, 0, 0, v9
},
899 { "srax", F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5), "1,2,d", 0, 0, 0, v9
},
900 { "srax", F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6), "1,Y,d", 0, 0, 0, v9
},
901 { "srlx", F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5), "1,2,d", 0, 0, 0, v9
},
902 { "srlx", F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6), "1,Y,d", 0, 0, 0, v9
},
904 { "mulscc", F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
905 { "mulscc", F3(2, 0x24, 1), F3(~2, ~0x24, ~1), "1,i,d", 0, 0, 0, v6
},
907 { "divscc", F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0), "1,2,d", 0, 0, 0, sparclite
},
908 { "divscc", F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1), "1,i,d", 0, 0, 0, sparclite
},
910 { "scan", F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, sparclet
|sparclite
},
911 { "scan", F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1), "1,i,d", 0, 0, 0, sparclet
|sparclite
},
913 { "popc", F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0
|ASI(~0),"2,d", 0, HWCAP_POPC
, 0, v9
},
914 { "popc", F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS1_G0
, "i,d", 0, HWCAP_POPC
, 0, v9
},
916 { "clr", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0
|RS1_G0
|ASI_RS2(~0), "d", F_ALIAS
, 0, 0, v6
}, /* or %g0,%g0,d */
917 { "clr", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0
|SIMM13(~0), "d", F_ALIAS
, 0, 0, v6
}, /* or %g0,0,d */
918 { "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0
|ASI(~0), "[1+2]", F_ALIAS
, 0, 0, v6
},
919 { "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0
|ASI_RS2(~0), "[1]", F_ALIAS
, 0, 0, v6
}, /* st %g0,[rs1+%g0] */
920 { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0
, "[1+i]", F_ALIAS
, 0, 0, v6
},
921 { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0
, "[i+1]", F_ALIAS
, 0, 0, v6
},
922 { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0
|RS1_G0
, "[i]", F_ALIAS
, 0, 0, v6
},
923 { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0
|SIMM13(~0), "[1]", F_ALIAS
, 0, 0, v6
}, /* st %g0,[rs1+0] */
925 { "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0
|ASI(~0), "[1+2]", F_ALIAS
, 0, 0, v6
},
926 { "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0
|ASI_RS2(~0), "[1]", F_ALIAS
, 0, 0, v6
}, /* stb %g0,[rs1+%g0] */
927 { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0
, "[1+i]", F_ALIAS
, 0, 0, v6
},
928 { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0
, "[i+1]", F_ALIAS
, 0, 0, v6
},
929 { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0
|RS1_G0
, "[i]", F_ALIAS
, 0, 0, v6
},
930 { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0
|SIMM13(~0), "[1]", F_ALIAS
, 0, 0, v6
}, /* stb %g0,[rs1+0] */
932 { "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0
|ASI(~0), "[1+2]", F_ALIAS
, 0, 0, v6
},
933 { "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0
|ASI_RS2(~0), "[1]", F_ALIAS
, 0, 0, v6
}, /* sth %g0,[rs1+%g0] */
934 { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0
, "[1+i]", F_ALIAS
, 0, 0, v6
},
935 { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0
, "[i+1]", F_ALIAS
, 0, 0, v6
},
936 { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0
|RS1_G0
, "[i]", F_ALIAS
, 0, 0, v6
},
937 { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0
|SIMM13(~0), "[1]", F_ALIAS
, 0, 0, v6
}, /* sth %g0,[rs1+0] */
939 { "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0
|ASI(~0), "[1+2]", F_ALIAS
, 0, 0, v9
},
940 { "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0
|ASI_RS2(~0), "[1]", F_ALIAS
, 0, 0, v9
}, /* stx %g0,[rs1+%g0] */
941 { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0
, "[1+i]", F_ALIAS
, 0, 0, v9
},
942 { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0
, "[i+1]", F_ALIAS
, 0, 0, v9
},
943 { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0
|RS1_G0
, "[i]", F_ALIAS
, 0, 0, v9
},
944 { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0
|SIMM13(~0), "[1]", F_ALIAS
, 0, 0, v9
}, /* stx %g0,[rs1+0] */
946 { "orcc", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
947 { "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "1,i,d", 0, 0, 0, v6
},
948 { "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "i,1,d", 0, 0, 0, v6
},
950 /* This is not a commutative instruction. */
951 { "orncc", F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
952 { "orncc", F3(2, 0x16, 1), F3(~2, ~0x16, ~1), "1,i,d", 0, 0, 0, v6
},
954 /* This is not a commutative instruction. */
955 { "orn", F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
956 { "orn", F3(2, 0x06, 1), F3(~2, ~0x06, ~1), "1,i,d", 0, 0, 0, v6
},
958 { "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0
|ASI_RS2(~0), "1", 0, 0, 0, v6
}, /* orcc rs1, %g0, %g0 */
959 { "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0
|RS1_G0
|ASI(~0), "2", 0, 0, 0, v6
}, /* orcc %g0, rs2, %g0 */
960 { "tst", F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0
|SIMM13(~0), "1", 0, 0, 0, v6
}, /* orcc rs1, 0, %g0 */
963 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", 0, 0, 0, v8
}, /* wr r,r,%asrX */
964 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", 0, 0, 0, v8
}, /* wr r,i,%asrX */
965 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RS1_G0
|ASI(~0), "2,m", F_PREF_ALIAS
, 0, 0, v8
}, /* wr %g0,rs2,%asrX */
966 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RS1_G0
, "i,m", F_PREF_ALIAS
, 0, 0, v8
}, /* wr %g0,i,%asrX */
967 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0), "1,m", F_PREF_ALIAS
, 0, 0, v8
}, /* wr rs1,%asrX */
968 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_PREF_ALIAS
, 0, 0, v8
}, /* wr rs1,%g0,%asrX */
969 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0
|ASI(~0), "1,2,y", 0, 0, 0, v6
}, /* wr r,r,%y */
970 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0
, "1,i,y", 0, 0, 0, v6
}, /* wr r,i,%y */
971 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0
|RS1_G0
|ASI(~0), "2,y", F_PREF_ALIAS
, 0, 0, v6
}, /* wr %g0,rs2,%y */
972 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0
|RS1_G0
, "i,y", F_PREF_ALIAS
, 0, 0, v6
}, /* wr %g0,i,%y */
973 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0
|SIMM13(~0), "1,y", F_PREF_ALIAS
, 0, 0, v6
}, /* wr rs1,0,%y */
974 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0
|ASI_RS2(~0), "1,y", F_PREF_ALIAS
, 0, 0, v6
}, /* wr rs1,%g0,%y */
975 { "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0
|ASI(~0), "1,2,p", 0, 0, 0, v6notv9
}, /* wr r,r,%psr */
976 { "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0
, "1,i,p", 0, 0, 0, v6notv9
}, /* wr r,i,%psr */
977 { "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0
|RS1_G0
|ASI(~0), "2,p", F_PREF_ALIAS
, 0, 0, v6notv9
}, /* wr %g0,rs2,%psr */
978 { "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0
|RS1_G0
, "i,p", F_PREF_ALIAS
, 0, 0, v6notv9
}, /* wr %g0,i,%psr */
979 { "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0
|SIMM13(~0), "1,p", F_PREF_ALIAS
, 0, 0, v6notv9
}, /* wr rs1,0,%psr */
980 { "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0
|ASI_RS2(~0), "1,p", F_PREF_ALIAS
, 0, 0, v6notv9
}, /* wr rs1,%g0,%psr */
981 { "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0
|ASI(~0), "1,2,w", 0, 0, 0, v6notv9
}, /* wr r,r,%wim */
982 { "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0
, "1,i,w", 0, 0, 0, v6notv9
}, /* wr r,i,%wim */
983 { "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0
|RS1_G0
|ASI(~0), "2,w", F_PREF_ALIAS
, 0, 0, v6notv9
}, /* wr %g0,rs2,%wim */
984 { "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0
|RS1_G0
, "i,w", F_PREF_ALIAS
, 0, 0, v6notv9
}, /* wr %g0,i,%wim */
985 { "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0
|SIMM13(~0), "1,w", F_PREF_ALIAS
, 0, 0, v6notv9
}, /* wr rs1,0,%wim */
986 { "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0
|ASI_RS2(~0), "1,w", F_PREF_ALIAS
, 0, 0, v6notv9
}, /* wr rs1,%g0,%wim */
987 { "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0
|ASI(~0), "1,2,t", 0, 0, 0, v6notv9
}, /* wr r,r,%tbr */
988 { "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0
, "1,i,t", 0, 0, 0, v6notv9
}, /* wr r,i,%tbr */
989 { "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0
|RS1_G0
|ASI(~0), "2,t", F_PREF_ALIAS
, 0, 0, v6notv9
}, /* wr %g0,rs2,%tbr */
990 { "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0
|RS1_G0
, "i,t", F_PREF_ALIAS
, 0, 0, v6notv9
}, /* wr %g0,i,%tbr */
991 { "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0
|SIMM13(~0), "1,t", F_PREF_ALIAS
, 0, 0, v6notv9
}, /* wr rs1,0,%tbr */
992 { "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0
|ASI_RS2(~0), "1,t", F_PREF_ALIAS
, 0, 0, v6notv9
}, /* wr rs1,%g0,%tbr */
994 { "wr", F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E", 0, 0, 0, v9
}, /* wr r,r,%ccr */
995 { "wr", F3(2, 0x30, 1)|RD(2), F3(~2, ~0x30, ~1)|RD(~2), "1,i,E", 0, 0, 0, v9
}, /* wr r,i,%ccr */
996 { "wr", F3(2, 0x30, 0)|RD(3), F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0), "1,2,o", 0, 0, 0, v9
}, /* wr r,r,%asi */
997 { "wr", F3(2, 0x30, 1)|RD(3), F3(~2, ~0x30, ~1)|RD(~3), "1,i,o", 0, 0, 0, v9
}, /* wr r,i,%asi */
998 { "wr", F3(2, 0x30, 0)|RD(6), F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0), "1,2,s", 0, 0, 0, v9
}, /* wr r,r,%fprs */
999 { "wr", F3(2, 0x30, 1)|RD(6), F3(~2, ~0x30, ~1)|RD(~6), "1,i,s", 0, 0, 0, v9
}, /* wr r,i,%fprs */
1000 { "wr", F3(2, 0x30, 0)|RD(14), F3(~2, ~0x30, ~0)|RD(~14), "1,2,{", 0, 0, HWCAP2_SPARC5
, v9m
}, /* wr r,r,%mcdper */
1001 { "wr", F3(2, 0x30, 1)|RD(14), F3(~2, ~0x30, ~1)|RD(~14), "1,i,{", 0, 0, HWCAP2_SPARC5
, v9m
}, /* wr r,i,%mcdper */
1003 /* Write to ASR registers 16..31, which is the range defined in SPARC
1004 V9 for implementation-dependent uses. Note that the read-only ASR
1005 registers can't be used in a `wr' instruction. */
1007 #define wrasr(asr,hwcap,hwcap2,arch) \
1008 { "wr", F3(2, 0x30, 0)|RD((asr)), F3(~2, ~0x30, ~0)|RD(~(asr))|ASI(~0), "1,2,_", 0, (hwcap), (hwcap2), (arch) }, /* wr r,r,%asr */ \
1009 { "wr", F3(2, 0x30, 1)|RD((asr)), F3(~2, ~0x30, ~1)|RD(~(asr)), "1,i,_", 0, (hwcap), (hwcap2), (arch) }, /* wr r,i,%asr */ \
1010 { "wr", F3(2, 0x30, 1)|RD((asr)), F3(~2, ~0x30, ~1)|RD(~(asr)), "i,1,_", F_ALIAS, (hwcap), (hwcap2), (arch) } /* wr i,r,%asr */
1012 wrasr (16, HWCAP_VIS
, 0, v9a
), /* wr ...,%pcr */
1013 wrasr (17, HWCAP_VIS
, 0, v9a
), /* wr ...,%pic */
1014 wrasr (18, HWCAP_VIS
, 0, v9a
), /* wr ...,%dcr */
1015 wrasr (19, HWCAP_VIS
, 0, v9a
), /* wr ...,%gsr */
1016 wrasr (20, HWCAP_VIS
, 0, v9a
), /* wr ...,%softint_set */
1017 wrasr (21, HWCAP_VIS
, 0, v9a
), /* wr ...,%softint_clear */
1018 wrasr (22, HWCAP_VIS
, 0, v9a
), /* wr ...,%softint */
1019 wrasr (23, HWCAP_VIS
, 0, v9a
), /* wr ...,%tick_cmpr */
1020 wrasr (24, HWCAP_VIS2
, 0, v9b
), /* wr ...,%sys_tick */
1021 wrasr (25, HWCAP_VIS2
, 0, v9b
), /* wr ...,%sys_tick_cmpr */
1022 wrasr (26, HWCAP_CBCOND
, 0, v9e
), /* wr ...,%cfr */
1023 wrasr (27, HWCAP_PAUSE
, 0, v9e
), /* wr ...,%pause */
1024 wrasr (28, 0, HWCAP2_MWAIT
, v9m
), /* wr ...,%mwait */
1026 { "pause", F3(2, 0x30, 1)|RD(27)|RS1(0), F3(~2, ~0x30, ~1)|RD(~27)|RS1(~0), "i", 0, HWCAP_PAUSE
, 0, v9e
}, /* wr %g0,i,%pause */
1028 { "rd", F3(2, 0x28, 0)|RS1(2), F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0), "E,d", 0, 0, 0, v9
}, /* rd %ccr,r */
1029 { "rd", F3(2, 0x28, 0)|RS1(3), F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0), "o,d", 0, 0, 0, v9
}, /* rd %asi,r */
1030 { "rd", F3(2, 0x28, 0)|RS1(4), F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0), "W,d", 0, 0, 0, v9
}, /* rd %tick,r */
1031 { "rd", F3(2, 0x28, 0)|RS1(5), F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0), "P,d", 0, 0, 0, v9
}, /* rd %pc,r */
1032 { "rd", F3(2, 0x28, 0)|RS1(6), F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0), "s,d", 0, 0, 0, v9
}, /* rd %fprs,r */
1033 { "rd", F3(2, 0x28, 0)|RS1(13), F3(~2, ~0x28, ~0)|RS1(~13)|SIMM13(~0), "&,d", 0, 0, HWCAP2_SPARC6
, m8
}, /* rd %entropy,r */
1034 { "rd", F3(2, 0x28, 0)|RS1(14), F3(~2, ~0x28, ~0)|RS1(~14)|SIMM13(~0), "{,d", 0, 0, HWCAP2_SPARC5
, v9m
}, /* rd %mcdper,r */
1036 /* Read from ASR registers 16..31, which is the range defined in SPARC
1037 V9 for implementation-dependent uses. Note that the write-only ASR
1038 registers can't be used in a `rd' instruction. */
1040 #define rdasr(asr,hwcap,hwcap2,arch) \
1041 { "rd", F3(2, 0x28, 0)|RS1((asr)), F3(~2, ~0x28, ~0)|RS1(~(asr))|SIMM13(~0), "/,d", 0, (hwcap), (hwcap2), (arch) }
1043 rdasr (16, HWCAP_VIS
, 0, v9a
), /* rd %pcr,r */
1044 rdasr (17, HWCAP_VIS
, 0, v9a
), /* rd %pic,r */
1045 rdasr (18, HWCAP_VIS
, 0, v9a
), /* rd %dcr,r */
1046 rdasr (19, HWCAP_VIS
, 0, v9a
), /* rd %gsr,r */
1047 rdasr (22, HWCAP_VIS
, 0, v9a
), /* rd %softint,r */
1048 rdasr (23, HWCAP_VIS
, 0, v9a
), /* rd %tick_cmpr,r */
1049 rdasr (24, HWCAP_VIS2
, 0, v9b
), /* rd %sys_tick,r */
1050 rdasr (25, HWCAP_VIS2
, 0, v9b
), /* rd %sys_tick_cmpr,r */
1051 rdasr (26, HWCAP_CBCOND
, 0, v9e
), /* rd %cfr,r */
1053 { "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", 0, 0, 0, v8
}, /* rd %asrX,r */
1054 { "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0
|SIMM13(~0), "y,d", 0, 0, 0, v6
}, /* rd %y,r */
1055 { "rd", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0
|SIMM13(~0), "p,d", 0, 0, 0, v6notv9
}, /* rd %psr,r */
1056 { "rd", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0
|SIMM13(~0), "w,d", 0, 0, 0, v6notv9
}, /* rd %wim,r */
1057 { "rd", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0
|SIMM13(~0), "t,d", 0, 0, 0, v6notv9
}, /* rd %tbr,r */
1059 /* Instructions to read and write from/to privileged registers. */
1061 #define rdpr(reg,hwcap,hwcap2,arch) \
1062 { "rdpr", F3(2, 0x2a, 0)|RS1((reg)), F3(~2, ~0x2a, ~0)|RS1(~(reg))|SIMM13(~0),"?,d", 0, (hwcap), (hwcap2), (arch) } /* rdpr %priv,r */
1064 rdpr (0, 0, 0, v9
), /* rdpr %tpc,r */
1065 rdpr (1, 0, 0, v9
), /* rdpr %tnpc,r */
1066 rdpr (2, 0, 0, v9
), /* rdpr %tstate,r */
1067 rdpr (3, 0, 0, v9
), /* rdpr %tt,r */
1068 rdpr (4, 0, 0, v9
), /* rdpr %tick,r */
1069 rdpr (5, 0, 0, v9
), /* rdpr %tba,r */
1070 rdpr (6, 0, 0, v9
), /* rdpr %pstate,r */
1071 rdpr (7, 0, 0, v9
), /* rdpr %tl,r */
1072 rdpr (8, 0, 0, v9
), /* rdpr %pil,r */
1073 rdpr (9, 0, 0, v9
), /* rdpr %cwp,r */
1074 rdpr (10, 0, 0, v9
), /* rdpr %cansave,r */
1075 rdpr (11, 0, 0, v9
), /* rdpr %canrestore,r */
1076 rdpr (12, 0, 0, v9
), /* rdpr %cleanwin,r */
1077 rdpr (13, 0, 0, v9
), /* rdpr %otherwin,r */
1078 rdpr (14, 0, 0, v9
), /* rdpr %wstate,r */
1079 rdpr (15, 0, 0, v9
), /* rdpr %fq,r */
1080 rdpr (16, 0, 0, v9
), /* rdpr %gl,r */
1081 rdpr (23, 0, HWCAP2_SPARC5
, v9m
), /* rdpr %pmcdper,r */
1082 rdpr (31, 0, 0, v9
), /* rdpr %ver,r */
1084 #define wrpr(reg,hwcap,hwcap2,arch) \
1085 { "wrpr", F3(2, 0x32, 0)|RD((reg)), F3(~2, ~0x32, ~0)|RD(~(reg)), "1,2,!", 0, (hwcap), (hwcap2), (arch) }, /* wrpr r1,r2,%priv */ \
1086 { "wrpr", F3(2, 0x32, 0)|RD((reg)), F3(~2, ~0x32, ~0)|RD(~(reg))|SIMM13(~0), "1,!", 0, (hwcap), (hwcap2), (arch) }, /* wrpr r1,%priv */ \
1087 { "wrpr", F3(2, 0x32, 1)|RD((reg)), F3(~2, ~0x32, ~1)|RD(~(reg)), "1,i,!", 0, (hwcap), (hwcap2), (arch) }, /* wrpr r1,i,%priv */ \
1088 { "wrpr", F3(2, 0x32, 1)|RD((reg)), F3(~2, ~0x32, ~1)|RD(~(reg)), "i,1,!", F_ALIAS, (hwcap), (hwcap2), (arch) }, /* wrpr i,r1,%priv */ \
1089 { "wrpr", F3(2, 0x32, 1)|RD((reg)), F3(~2, ~0x32, ~1)|RD(~(reg))|RS1(~0), "i,!", 0, (hwcap), (hwcap2), (arch) } /* wrpr i,%priv */
1091 wrpr (0, 0, 0, v9
), /* wrpr ...,%tpc */
1092 wrpr (1, 0, 0, v9
), /* wrpr ...,%tnpc */
1093 wrpr (2, 0, 0, v9
), /* wrpr ...,%tstate */
1094 wrpr (3, 0, 0, v9
), /* wrpr ...,%tt */
1095 wrpr (4, 0, 0, v9
), /* wrpr ...,%tick */
1096 wrpr (5, 0, 0, v9
), /* wrpr ...,%tba */
1097 wrpr (6, 0, 0, v9
), /* wrpr ...,%pstate */
1098 wrpr (7, 0, 0, v9
), /* wrpr ...,%tl */
1099 wrpr (8, 0, 0, v9
), /* wrpr ...,%pil */
1100 wrpr (9, 0, 0, v9
), /* wrpr ...,%cwp */
1101 wrpr (10, 0, 0, v9
), /* wrpr ...,%cansave */
1102 wrpr (11, 0, 0, v9
), /* wrpr ...,%canrestore */
1103 wrpr (12, 0, 0, v9
), /* wrpr ...,%cleanwin */
1104 wrpr (13, 0, 0, v9
), /* wrpr ...,%otherwin */
1105 wrpr (14, 0, 0, v9
), /* wrpr ...,%wstate */
1106 wrpr (15, 0, 0, v9
), /* wrpr ...,%fq */
1107 wrpr (16, 0, 0, v9
), /* wrpr ...,%gl */
1108 wrpr (23, 0, HWCAP2_SPARC5
, v9m
), /* wdpr ...,%pmcdper */
1109 wrpr (31, 0, 0, v9
), /* wrpr ...,%ver */
1111 /* Instructions to read and write from/to hyperprivileged
1114 #define rdhpr(reg,hwcap,hwcap2,arch) \
1115 { "rdhpr", F3(2, 0x29, 0)|RS1((reg)), F3(~2, ~0x29, ~0)|RS1(~(reg))|SIMM13(~0), "$,d", 0, (hwcap), (hwcap2), (arch) }
1117 rdhpr (0, HWCAP_VIS
, 0, v9a
), /* rdhpr %hpstate,r */
1118 rdhpr (1, HWCAP_VIS
, 0, v9a
), /* rdhpr %htstate,r */
1119 rdhpr (3, HWCAP_VIS
, 0, v9a
), /* rdhpr %hintp,r */
1120 rdhpr (5, HWCAP_VIS
, 0, v9a
), /* rdhpr %htba,r */
1121 rdhpr (6, HWCAP_VIS
, 0, v9a
), /* rdhpr %hver,r */
1122 rdhpr (23, 0, HWCAP2_SPARC5
, v9m
), /* rdhpr %hmcdper,r */
1123 rdhpr (24, 0, HWCAP2_SPARC5
, v9m
), /* rdhpr %hmcddfr,r */
1124 rdhpr (27, 0, HWCAP2_SPARC5
, v9m
), /* rdhpr %hva_mask_nz,r */
1125 rdhpr (28, HWCAP_VIS
, 0, v9a
), /* rdhpr %hstick_offset,r */
1126 rdhpr (29, HWCAP_VIS
, 0, v9a
), /* rdhpar %hstick_enable,r */
1127 rdhpr (31, HWCAP_VIS
, 0, v9a
), /* rdhpr %hstick_cmpr,r */
1129 #define wrhpr(reg,hwcap,hwcap2,arch) \
1130 { "wrhpr", F3(2, 0x33, 0)|RD((reg)), F3(~2, ~0x33, ~0)|RD(~(reg)),"1,2,%", 0, (hwcap), (hwcap2), (arch) }, /* wrhpr r1,r2,%hpriv */ \
1131 { "wrhpr", F3(2, 0x33, 0)|RD((reg)), F3(~2, ~0x33, ~0)|RD(~(reg))|SIMM13(~0), "1,%", 0, (hwcap), (hwcap2), (arch) }, /* wrhpr r1,%hpriv */ \
1132 { "wrhpr", F3(2, 0x33, 1)|RD((reg)), F3(~2, ~0x33, ~1)|RD(~(reg)), "1,i,%", 0, (hwcap), (hwcap2), (arch) }, /* wrhpr r1,i,%hpriv */ \
1133 { "wrhpr", F3(2, 0x33, 1)|RD((reg)), F3(~2, ~0x33, ~1)|RD(~(reg)), "i,1,%", F_ALIAS, (hwcap), (hwcap2), (arch) }, /* wrhpr i,r1,%hpriv */ \
1134 { "wrhpr", F3(2, 0x33, 1)|RD((reg)), F3(~2, ~0x33, ~1)|RD(~(reg))|RS1(~0), "i,%", 0, (hwcap), (hwcap2), (arch) } /* wrhpr i,%hpriv */
1136 wrhpr (0, HWCAP_VIS
, 0, v9a
), /* wrhpr ...,%hpstate */
1137 wrhpr (1, HWCAP_VIS
, 0, v9a
), /* wrhpr ...,%htstate */
1138 wrhpr (3, HWCAP_VIS
, 0, v9a
), /* wrhpr ...,%hintp */
1139 wrhpr (5, HWCAP_VIS
, 0, v9a
), /* wrhpr ...,%htba */
1140 wrhpr (23, 0, HWCAP2_SPARC5
, v9m
), /* wrhpr ...,%hmcdper */
1141 wrhpr (24, 0, HWCAP2_SPARC5
, v9m
), /* wrhpr ...,%hmcddfr */
1142 wrhpr (27, 0, HWCAP2_SPARC5
, v9m
), /* wrhpr ...,%hva_mask_nz */
1143 wrhpr (28, HWCAP_VIS
, 0, v9a
), /* wrhpr ...,%hstick_offset */
1144 wrhpr (29, HWCAP_VIS
, 0, v9a
), /* wrhpr ...,%hstick_enable */
1145 wrhpr (31, HWCAP_VIS
, 0, v9a
), /* wrhpr ...,%hstick_cmpr */
1147 { "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", F_ALIAS
, 0, 0, v8
}, /* rd %asr1,r */
1148 { "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0
|SIMM13(~0), "y,d", F_ALIAS
, 0, 0, v6
}, /* rd %y,r */
1149 { "mov", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0
|SIMM13(~0), "p,d", F_ALIAS
, 0, 0, v6notv9
}, /* rd %psr,r */
1150 { "mov", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0
|SIMM13(~0), "w,d", F_ALIAS
, 0, 0, v6notv9
}, /* rd %wim,r */
1151 { "mov", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0
|SIMM13(~0), "t,d", F_ALIAS
, 0, 0, v6notv9
}, /* rd %tbr,r */
1153 { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RS1_G0
|ASI(~0), "2,m", F_ALIAS
, 0, 0, v8
}, /* wr %g0,rs2,%asrX */
1154 { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RS1_G0
, "i,m", F_ALIAS
, 0, 0, v8
}, /* wr %g0,i,%asrX */
1155 { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0
|RS1_G0
|ASI(~0), "2,y", F_ALIAS
, 0, 0, v6
}, /* wr %g0,rs2,%y */
1156 { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0
|RS1_G0
, "i,y", F_ALIAS
, 0, 0, v6
}, /* wr %g0,i,%y */
1157 { "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0
|RS1_G0
|ASI(~0), "2,p", F_ALIAS
, 0, 0, v6notv9
}, /* wr %g0,rs2,%psr */
1158 { "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0
|RS1_G0
, "i,p", F_ALIAS
, 0, 0, v6notv9
}, /* wr %g0,i,%psr */
1159 { "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0
|RS1_G0
|ASI(~0), "2,w", F_ALIAS
, 0, 0, v6notv9
}, /* wr %g0,rs2,%wim */
1160 { "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0
|RS1_G0
, "i,w", F_ALIAS
, 0, 0, v6notv9
}, /* wr %g0,i,%wim */
1161 { "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0
|RS1_G0
|ASI(~0), "2,t", F_ALIAS
, 0, 0, v6notv9
}, /* wr %g0,rs2,%tbr */
1162 { "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0
|RS1_G0
, "i,t", F_ALIAS
, 0, 0, v6notv9
}, /* wr %g0,i,%tbr */
1164 { "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0
|ASI(~0), "2,d", 0, 0, 0, v6
}, /* or %g0,rs2,d */
1165 { "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0
, "i,d", 0, 0, 0, v6
}, /* or %g0,i,d */
1166 { "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0), "1,d", 0, 0, 0, v6
}, /* or rs1,%g0,d */
1167 { "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0), "1,d", 0, 0, 0, v6
}, /* or rs1,0,d */
1169 { "or", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1170 { "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "1,i,d", 0, 0, 0, v6
},
1171 { "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,1,d", 0, 0, 0, v6
},
1173 { "bset", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "2,r", F_ALIAS
, 0, 0, v6
}, /* or rd,rs2,rd */
1174 { "bset", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,r", F_ALIAS
, 0, 0, v6
}, /* or rd,i,rd */
1176 /* This is not a commutative instruction. */
1177 { "andn", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1178 { "andn", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "1,i,d", 0, 0, 0, v6
},
1180 /* This is not a commutative instruction. */
1181 { "andncc", F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1182 { "andncc", F3(2, 0x15, 1), F3(~2, ~0x15, ~1), "1,i,d", 0, 0, 0, v6
},
1184 { "bclr", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "2,r", F_ALIAS
, 0, 0, v6
}, /* andn rd,rs2,rd */
1185 { "bclr", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "i,r", F_ALIAS
, 0, 0, v6
}, /* andn rd,i,rd */
1187 { "cmp", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0
|ASI(~0), "1,2", 0, 0, 0, v6
}, /* subcc rs1,rs2,%g0 */
1188 { "cmp", F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0
, "1,i", 0, 0, 0, v6
}, /* subcc rs1,i,%g0 */
1190 { "sub", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1191 { "sub", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "1,i,d", 0, 0, 0, v6
},
1193 { "subcc", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1194 { "subcc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "1,i,d", 0, 0, 0, v6
},
1196 { "subx", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6notv9
},
1197 { "subx", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, 0, 0, v6notv9
},
1198 { "subc", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9
},
1199 { "subc", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, 0, 0, v9
},
1201 { "subxcc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6notv9
},
1202 { "subxcc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, 0, 0, v6notv9
},
1203 { "subccc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9
},
1204 { "subccc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, 0, 0, v9
},
1206 { "and", F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1207 { "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "1,i,d", 0, 0, 0, v6
},
1208 { "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "i,1,d", 0, 0, 0, v6
},
1210 { "andcc", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1211 { "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "1,i,d", 0, 0, 0, v6
},
1212 { "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "i,1,d", 0, 0, 0, v6
},
1214 { "dec", F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS
, 0, 0, v6
}, /* sub rd,1,rd */
1215 { "dec", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "i,r", F_ALIAS
, 0, 0, v8
}, /* sub rd,imm,rd */
1216 { "deccc", F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS
, 0, 0, v6
}, /* subcc rd,1,rd */
1217 { "deccc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "i,r", F_ALIAS
, 0, 0, v8
}, /* subcc rd,imm,rd */
1218 { "inc", F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS
, 0, 0, v6
}, /* add rd,1,rd */
1219 { "inc", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,r", F_ALIAS
, 0, 0, v8
}, /* add rd,imm,rd */
1220 { "inccc", F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS
, 0, 0, v6
}, /* addcc rd,1,rd */
1221 { "inccc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,r", F_ALIAS
, 0, 0, v8
}, /* addcc rd,imm,rd */
1223 { "btst", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0
|ASI(~0), "1,2", F_ALIAS
, 0, 0, v6
}, /* andcc rs1,rs2,%g0 */
1224 { "btst", F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0
, "i,1", F_ALIAS
, 0, 0, v6
}, /* andcc rs1,i,%g0 */
1226 { "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0
|ASI(~0), "2,d", F_ALIAS
, 0, 0, v6
}, /* sub %g0,rs2,rd */
1227 { "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0
|ASI(~0), "O", F_ALIAS
, 0, 0, v6
}, /* sub %g0,rd,rd */
1229 { "add", F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1230 { "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "1,i,d", 0, 0, 0, v6
},
1231 { "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,1,d", 0, 0, 0, v6
},
1232 { "addcc", F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1233 { "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "1,i,d", 0, 0, 0, v6
},
1234 { "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,1,d", 0, 0, 0, v6
},
1236 { "addx", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6notv9
},
1237 { "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, 0, 0, v6notv9
},
1238 { "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, 0, 0, v6notv9
},
1239 { "addc", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9
},
1240 { "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, 0, 0, v9
},
1241 { "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, 0, 0, v9
},
1243 { "addxcc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6notv9
},
1244 { "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, 0, 0, v6notv9
},
1245 { "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, 0, 0, v6notv9
},
1246 { "addccc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9
},
1247 { "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, 0, 0, v9
},
1248 { "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, 0, 0, v9
},
1250 { "smul", F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0), "1,2,d", 0, HWCAP_MUL32
, 0, v8
},
1251 { "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "1,i,d", 0, HWCAP_MUL32
, 0, v8
},
1252 { "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "i,1,d", 0, HWCAP_MUL32
, 0, v8
},
1253 { "smulcc", F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0), "1,2,d", 0, HWCAP_MUL32
, 0, v8
},
1254 { "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "1,i,d", 0, HWCAP_MUL32
, 0, v8
},
1255 { "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "i,1,d", 0, HWCAP_MUL32
, 0, v8
},
1256 { "umul", F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0), "1,2,d", 0, HWCAP_MUL32
, 0, v8
},
1257 { "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "1,i,d", 0, HWCAP_MUL32
, 0, v8
},
1258 { "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "i,1,d", 0, HWCAP_MUL32
, 0, v8
},
1259 { "umulcc", F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0), "1,2,d", 0, HWCAP_MUL32
, 0, v8
},
1260 { "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "1,i,d", 0, HWCAP_MUL32
, 0, v8
},
1261 { "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "i,1,d", 0, HWCAP_MUL32
, 0, v8
},
1262 { "sdiv", F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0), "1,2,d", 0, HWCAP_DIV32
, 0, v8
},
1263 { "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "1,i,d", 0, HWCAP_DIV32
, 0, v8
},
1264 { "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "i,1,d", 0, HWCAP_DIV32
, 0, v8
},
1265 { "sdivcc", F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0), "1,2,d", 0, HWCAP_DIV32
, 0, v8
},
1266 { "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "1,i,d", 0, HWCAP_DIV32
, 0, v8
},
1267 { "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "i,1,d", 0, HWCAP_DIV32
, 0, v8
},
1268 { "udiv", F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0), "1,2,d", 0, HWCAP_DIV32
, 0, v8
},
1269 { "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "1,i,d", 0, HWCAP_DIV32
, 0, v8
},
1270 { "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "i,1,d", 0, HWCAP_DIV32
, 0, v8
},
1271 { "udivcc", F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0), "1,2,d", 0, HWCAP_DIV32
, 0, v8
},
1272 { "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "1,i,d", 0, HWCAP_DIV32
, 0, v8
},
1273 { "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "i,1,d", 0, HWCAP_DIV32
, 0, v8
},
1275 { "mulx", F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9
},
1276 { "mulx", F3(2, 0x09, 1), F3(~2, ~0x09, ~1), "1,i,d", 0, 0, 0, v9
},
1277 { "sdivx", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9
},
1278 { "sdivx", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, 0, 0, v9
},
1279 { "udivx", F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9
},
1280 { "udivx", F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1), "1,i,d", 0, 0, 0, v9
},
1282 { "call", F1(0x1), F1(~0x1), "L", F_JSR
|F_DELAYED
, 0, 0, v6
},
1283 { "call", F1(0x1), F1(~0x1), "L,#", F_JSR
|F_DELAYED
, 0, 0, v6
},
1285 { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2", F_JSR
|F_DELAYED
, 0, 0, v6
}, /* jmpl rs1+rs2,%o7 */
1286 { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2,#", F_JSR
|F_DELAYED
, 0, 0, v6
},
1287 { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1", F_JSR
|F_DELAYED
, 0, 0, v6
}, /* jmpl rs1+%g0,%o7 */
1288 { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1,#", F_JSR
|F_DELAYED
, 0, 0, v6
},
1289 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i", F_JSR
|F_DELAYED
, 0, 0, v6
}, /* jmpl rs1+i,%o7 */
1290 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i,#", F_JSR
|F_DELAYED
, 0, 0, v6
},
1291 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1", F_JSR
|F_DELAYED
, 0, 0, v6
}, /* jmpl i+rs1,%o7 */
1292 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1,#", F_JSR
|F_DELAYED
, 0, 0, v6
},
1293 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0
, "i", F_JSR
|F_DELAYED
, 0, 0, v6
}, /* jmpl %g0+i,%o7 */
1294 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0
, "i,#", F_JSR
|F_DELAYED
, 0, 0, v6
},
1295 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1", F_JSR
|F_DELAYED
, 0, 0, v6
}, /* jmpl rs1+0,%o7 */
1296 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1,#", F_JSR
|F_DELAYED
, 0, 0, v6
},
1298 /* Conditional instructions.
1300 Because this part of the table was such a mess earlier, I have
1301 macrofied it so that all the branches and traps are generated from
1302 a single-line description of each condition value. John Gilmore. */
1304 /* Define branches -- one annulled, one without, etc. */
1305 #define br(opcode, mask, lose, flags) \
1306 { opcode, (mask)|ANNUL, (lose), ",a l", (flags), 0, 0, v6 }, \
1307 { opcode, (mask) , (lose)|ANNUL, "l", (flags), 0, 0, v6 }
1309 #define brx(opcode, mask, lose, flags) /* v9 */ \
1310 { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), "Z,G", (flags), 0, 0, v9 }, \
1311 { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), ",T Z,G", (flags), 0, 0, v9 }, \
1312 { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a Z,G", (flags), 0, 0, v9 }, \
1313 { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a,T Z,G", (flags), 0, 0, v9 }, \
1314 { opcode, (mask)|(2<<20), ANNUL|BPRED|(lose), ",N Z,G", (flags), 0, 0, v9 }, \
1315 { opcode, (mask)|(2<<20)|ANNUL, BPRED|(lose), ",a,N Z,G", (flags), 0, 0, v9 }, \
1316 { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), "z,G", (flags), 0, 0, v9 }, \
1317 { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), ",T z,G", (flags), 0, 0, v9 }, \
1318 { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a z,G", (flags), 0, 0, v9 }, \
1319 { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a,T z,G", (flags), 0, 0, v9 }, \
1320 { opcode, (mask), ANNUL|BPRED|(lose)|(2<<20), ",N z,G", (flags), 0, 0, v9 }, \
1321 { opcode, (mask)|ANNUL, BPRED|(lose)|(2<<20), ",a,N z,G", (flags), 0, 0, v9 }
1323 /* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */
1324 #define tr(opcode, mask, lose, flags) \
1325 { opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0, "Z,i", (flags), 0, 0, v9 }, /* %g0 + imm */ \
1326 { opcode, (mask)|(2<<11)|IMMED, (lose), "Z,1+i", (flags), 0, 0, v9 }, /* rs1 + imm */ \
1327 { opcode, (mask)|(2<<11), IMMED|(lose), "Z,1+2", (flags), 0, 0, v9 }, /* rs1 + rs2 */ \
1328 { opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0, "Z,1", (flags), 0, 0, v9 }, /* rs1 + %g0 */ \
1329 { opcode, (mask)|IMMED, (lose)|RS1_G0, "z,i", (flags)|F_ALIAS, 0, 0, v9 }, /* %g0 + imm */ \
1330 { opcode, (mask)|IMMED, (lose), "z,1+i", (flags)|F_ALIAS, 0, 0, v9 }, /* rs1 + imm */ \
1331 { opcode, (mask), IMMED|(lose), "z,1+2", (flags)|F_ALIAS, 0, 0, v9 }, /* rs1 + rs2 */ \
1332 { opcode, (mask), IMMED|(lose)|RS2_G0, "z,1", (flags)|F_ALIAS, 0, 0, v9 }, /* rs1 + %g0 */ \
1333 { opcode, (mask)|IMMED, (lose)|RS1_G0, "i", (flags), 0, 0, v6 }, /* %g0 + imm */ \
1334 { opcode, (mask)|IMMED, (lose), "1+i", (flags), 0, 0, v6 }, /* rs1 + imm */ \
1335 { opcode, (mask)|IMMED, (lose), "i+1", (flags), 0, 0, v6 }, /* imm + rs1 */ \
1336 { opcode, (mask), IMMED|(lose), "1+2", (flags), 0, 0, v6 }, /* rs1 + rs2 */ \
1337 { opcode, (mask), IMMED|(lose)|RS2_G0, "1", (flags), 0, 0, v6 } /* rs1 + %g0 */
1339 /* v9: We must put `brx' before `br', to ensure that we never match something
1340 v9: against an expression unless it is an expression. Otherwise, we end
1341 v9: up with undefined symbol tables entries, because they get added, but
1342 v9: are not deleted if the pattern fails to match. */
1344 /* Define both branches and traps based on condition mask */
1345 #define cond(bop, top, mask, flags) \
1346 brx(bop, F2(0, 1)|(mask), F2(~0, ~1)|((~mask)&COND(~0)), F_DELAYED|(flags)), /* v9 */ \
1347 br(bop, F2(0, 2)|(mask), F2(~0, ~2)|((~mask)&COND(~0)), F_DELAYED|(flags)), \
1348 tr(top, F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)), ((flags) & ~(F_UNBR|F_CONDBR)))
1350 /* Define all the conditions, all the branches, all the traps. */
1352 /* Standard branch, trap mnemonics */
1353 cond ("b", "ta", CONDA
, F_UNBR
),
1354 /* Alternative form (just for assembly, not for disassembly) */
1355 cond ("ba", "t", CONDA
, F_UNBR
|F_ALIAS
),
1357 cond ("bcc", "tcc", CONDCC
, F_CONDBR
),
1358 cond ("bcs", "tcs", CONDCS
, F_CONDBR
),
1359 cond ("be", "te", CONDE
, F_CONDBR
),
1360 cond ("beq", "teq", CONDE
, F_CONDBR
|F_ALIAS
),
1361 cond ("bg", "tg", CONDG
, F_CONDBR
),
1362 cond ("bgt", "tgt", CONDG
, F_CONDBR
|F_ALIAS
),
1363 cond ("bge", "tge", CONDGE
, F_CONDBR
),
1364 cond ("bgeu", "tgeu", CONDGEU
, F_CONDBR
|F_ALIAS
), /* for cc */
1365 cond ("bgu", "tgu", CONDGU
, F_CONDBR
),
1366 cond ("bl", "tl", CONDL
, F_CONDBR
),
1367 cond ("blt", "tlt", CONDL
, F_CONDBR
|F_ALIAS
),
1368 cond ("ble", "tle", CONDLE
, F_CONDBR
),
1369 cond ("bleu", "tleu", CONDLEU
, F_CONDBR
),
1370 cond ("blu", "tlu", CONDLU
, F_CONDBR
|F_ALIAS
), /* for cs */
1371 cond ("bn", "tn", CONDN
, F_CONDBR
),
1372 cond ("bne", "tne", CONDNE
, F_CONDBR
),
1373 cond ("bneg", "tneg", CONDNEG
, F_CONDBR
),
1374 cond ("bnz", "tnz", CONDNZ
, F_CONDBR
|F_ALIAS
), /* for ne */
1375 cond ("bpos", "tpos", CONDPOS
, F_CONDBR
),
1376 cond ("bvc", "tvc", CONDVC
, F_CONDBR
),
1377 cond ("bvs", "tvs", CONDVS
, F_CONDBR
),
1378 cond ("bz", "tz", CONDZ
, F_CONDBR
|F_ALIAS
), /* for e */
1385 #define brr(opcode, mask, lose, flags) /* v9 */ \
1386 { opcode, (mask)|BPRED, ANNUL|(lose), "1,k", F_DELAYED|(flags), 0, 0, v9 }, \
1387 { opcode, (mask)|BPRED, ANNUL|(lose), ",T 1,k", F_DELAYED|(flags), 0, 0, v9 }, \
1388 { opcode, (mask)|BPRED|ANNUL, (lose), ",a 1,k", F_DELAYED|(flags), 0, 0, v9 }, \
1389 { opcode, (mask)|BPRED|ANNUL, (lose), ",a,T 1,k", F_DELAYED|(flags), 0, 0, v9 }, \
1390 { opcode, (mask), ANNUL|BPRED|(lose), ",N 1,k", F_DELAYED|(flags), 0, 0, v9 }, \
1391 { opcode, (mask)|ANNUL, BPRED|(lose), ",a,N 1,k", F_DELAYED|(flags), 0, 0, v9 }
1393 #define condr(bop, mask, flags) /* v9 */ \
1394 brr(bop, F2(0, 3)|COND(mask), F2(~0, ~3)|COND(~(mask)), (flags)) /* v9 */
1396 /* v9 */ condr("brnz", 0x5, F_CONDBR
),
1397 /* v9 */ condr("brz", 0x1, F_CONDBR
),
1398 /* v9 */ condr("brgez", 0x7, F_CONDBR
),
1399 /* v9 */ condr("brlz", 0x3, F_CONDBR
),
1400 /* v9 */ condr("brlez", 0x2, F_CONDBR
),
1401 /* v9 */ condr("brgz", 0x6, F_CONDBR
),
1403 #define cbcond(cop, cmask, flgs) \
1404 { "cw" cop, F2(0, 3)|CBCOND(cmask)|F3I(0),F2(~0,~3)|CBCOND(~(cmask))|F3I(~0)|CBCOND_XCC, \
1405 "1,2,=", flgs, HWCAP_CBCOND, 0, v9e}, \
1406 { "cw" cop, F2(0, 3)|CBCOND(cmask)|F3I(1),F2(~0,~3)|CBCOND(~(cmask))|F3I(~1)|CBCOND_XCC, \
1407 "1,X,=", flgs, HWCAP_CBCOND, 0, v9e}, \
1408 { "cx" cop, F2(0, 3)|CBCOND(cmask)|F3I(0)|CBCOND_XCC,F2(~0,~3)|CBCOND(~(cmask))|F3I(~0), \
1409 "1,2,=", flgs, HWCAP_CBCOND, 0, v9e}, \
1410 { "cx" cop, F2(0, 3)|CBCOND(cmask)|F3I(1)|CBCOND_XCC,F2(~0,~3)|CBCOND(~(cmask))|F3I(~1), \
1411 "1,X,=", flgs, HWCAP_CBCOND, 0, v9e},
1413 cbcond("be", 0x09, F_CONDBR
)
1414 cbcond("bz", 0x09, F_CONDBR
|F_ALIAS
)
1415 cbcond("ble", 0x0a, F_CONDBR
)
1416 cbcond("bl", 0x0b, F_CONDBR
)
1417 cbcond("bleu", 0x0c, F_CONDBR
)
1418 cbcond("bcs", 0x0d, F_CONDBR
)
1419 cbcond("blu", 0x0d, F_CONDBR
|F_ALIAS
)
1420 cbcond("bneg", 0x0e, F_CONDBR
)
1421 cbcond("bvs", 0x0f, F_CONDBR
)
1422 cbcond("bne", 0x19, F_CONDBR
)
1423 cbcond("bnz", 0x19, F_CONDBR
|F_ALIAS
)
1424 cbcond("bg", 0x1a, F_CONDBR
)
1425 cbcond("bge", 0x1b, F_CONDBR
)
1426 cbcond("bgu", 0x1c, F_CONDBR
)
1427 cbcond("bcc", 0x1d, F_CONDBR
)
1428 cbcond("bgeu", 0x1d, F_CONDBR
|F_ALIAS
)
1429 cbcond("bpos", 0x1e, F_CONDBR
)
1430 cbcond("bvc", 0x1f, F_CONDBR
)
1433 #undef condr /* v9 */
1436 #define movr(opcode, mask, flags) /* v9 */ \
1437 { opcode, F3(2, 0x2f, 0)|RCOND(mask), F3(~2, ~0x2f, ~0)|RCOND(~(mask)), "1,2,d", (flags), 0, 0, v9 }, \
1438 { opcode, F3(2, 0x2f, 1)|RCOND(mask), F3(~2, ~0x2f, ~1)|RCOND(~(mask)), "1,j,d", (flags), 0, 0, v9 }
1440 #define fmrrs(opcode, mask, lose, flags) /* v9 */ \
1441 { opcode, (mask), (lose), "1,f,g", (flags) | F_FLOAT, 0, 0, v9 }
1442 #define fmrrd(opcode, mask, lose, flags) /* v9 */ \
1443 { opcode, (mask), (lose), "1,B,H", (flags) | F_FLOAT, 0, 0, v9 }
1444 #define fmrrq(opcode, mask, lose, flags) /* v9 */ \
1445 { opcode, (mask), (lose), "1,R,J", (flags) | F_FLOAT, 0, 0, v9 }
1447 #define fmovrs(mop, mask, flags) /* v9 */ \
1448 fmrrs(mop, F3(2, 0x35, 0)|OPF_LOW5(5)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~5)|RCOND(~(mask)), (flags)) /* v9 */
1449 #define fmovrd(mop, mask, flags) /* v9 */ \
1450 fmrrd(mop, F3(2, 0x35, 0)|OPF_LOW5(6)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~6)|RCOND(~(mask)), (flags)) /* v9 */
1451 #define fmovrq(mop, mask, flags) /* v9 */ \
1452 fmrrq(mop, F3(2, 0x35, 0)|OPF_LOW5(7)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~7)|RCOND(~(mask)), (flags)) /* v9 */
1454 /* v9 */ movr("movrne", 0x5, 0),
1455 /* v9 */ movr("movre", 0x1, 0),
1456 /* v9 */ movr("movrgez", 0x7, 0),
1457 /* v9 */ movr("movrlz", 0x3, 0),
1458 /* v9 */ movr("movrlez", 0x2, 0),
1459 /* v9 */ movr("movrgz", 0x6, 0),
1460 /* v9 */ movr("movrnz", 0x5, F_ALIAS
),
1461 /* v9 */ movr("movrz", 0x1, F_ALIAS
),
1463 /* v9 */ fmovrs("fmovrsne", 0x5, 0),
1464 /* v9 */ fmovrs("fmovrse", 0x1, 0),
1465 /* v9 */ fmovrs("fmovrsgez", 0x7, 0),
1466 /* v9 */ fmovrs("fmovrslz", 0x3, 0),
1467 /* v9 */ fmovrs("fmovrslez", 0x2, 0),
1468 /* v9 */ fmovrs("fmovrsgz", 0x6, 0),
1469 /* v9 */ fmovrs("fmovrsnz", 0x5, F_ALIAS
),
1470 /* v9 */ fmovrs("fmovrsz", 0x1, F_ALIAS
),
1472 /* v9 */ fmovrd("fmovrdne", 0x5, 0),
1473 /* v9 */ fmovrd("fmovrde", 0x1, 0),
1474 /* v9 */ fmovrd("fmovrdgez", 0x7, 0),
1475 /* v9 */ fmovrd("fmovrdlz", 0x3, 0),
1476 /* v9 */ fmovrd("fmovrdlez", 0x2, 0),
1477 /* v9 */ fmovrd("fmovrdgz", 0x6, 0),
1478 /* v9 */ fmovrd("fmovrdnz", 0x5, F_ALIAS
),
1479 /* v9 */ fmovrd("fmovrdz", 0x1, F_ALIAS
),
1481 /* v9 */ fmovrq("fmovrqne", 0x5, 0),
1482 /* v9 */ fmovrq("fmovrqe", 0x1, 0),
1483 /* v9 */ fmovrq("fmovrqgez", 0x7, 0),
1484 /* v9 */ fmovrq("fmovrqlz", 0x3, 0),
1485 /* v9 */ fmovrq("fmovrqlez", 0x2, 0),
1486 /* v9 */ fmovrq("fmovrqgz", 0x6, 0),
1487 /* v9 */ fmovrq("fmovrqnz", 0x5, F_ALIAS
),
1488 /* v9 */ fmovrq("fmovrqz", 0x1, F_ALIAS
),
1490 #undef movr /* v9 */
1491 #undef fmovr /* v9 */
1492 #undef fmrr /* v9 */
1494 #define movicc(opcode, cond, flags) /* v9 */ \
1495 { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|XCC|(1<<11), "z,2,d", flags, 0, 0, v9 }, \
1496 { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|XCC|(1<<11), "z,I,d", flags, 0, 0, v9 }, \
1497 { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|(1<<11), "Z,2,d", flags, 0, 0, v9 }, \
1498 { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|(1<<11), "Z,I,d", flags, 0, 0, v9 }
1500 #define movfcc(opcode, fcond, flags) /* v9 */ \
1501 { opcode, F3(2, 0x2c, 0)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~0), "6,2,d", flags, 0, 0, v9 }, \
1502 { opcode, F3(2, 0x2c, 1)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~1), "6,I,d", flags, 0, 0, v9 }, \
1503 { opcode, F3(2, 0x2c, 0)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~0), "7,2,d", flags, 0, 0, v9 }, \
1504 { opcode, F3(2, 0x2c, 1)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~1), "7,I,d", flags, 0, 0, v9 }, \
1505 { opcode, F3(2, 0x2c, 0)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~0), "8,2,d", flags, 0, 0, v9 }, \
1506 { opcode, F3(2, 0x2c, 1)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~1), "8,I,d", flags, 0, 0, v9 }, \
1507 { opcode, F3(2, 0x2c, 0)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~0), "9,2,d", flags, 0, 0, v9 }, \
1508 { opcode, F3(2, 0x2c, 1)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~1), "9,I,d", flags, 0, 0, v9 }
1510 #define movcc(opcode, cond, fcond, flags) /* v9 */ \
1511 movfcc (opcode, fcond, flags), /* v9 */ \
1512 movicc (opcode, cond, flags) /* v9 */
1514 /* v9 */ movcc ("mova", CONDA
, FCONDA
, 0),
1515 /* v9 */ movicc ("movcc", CONDCC
, 0),
1516 /* v9 */ movicc ("movgeu", CONDGEU
, F_ALIAS
),
1517 /* v9 */ movicc ("movcs", CONDCS
, 0),
1518 /* v9 */ movicc ("movlu", CONDLU
, F_ALIAS
),
1519 /* v9 */ movcc ("move", CONDE
, FCONDE
, 0),
1520 /* v9 */ movcc ("movg", CONDG
, FCONDG
, 0),
1521 /* v9 */ movcc ("movge", CONDGE
, FCONDGE
, 0),
1522 /* v9 */ movicc ("movgu", CONDGU
, 0),
1523 /* v9 */ movcc ("movl", CONDL
, FCONDL
, 0),
1524 /* v9 */ movcc ("movle", CONDLE
, FCONDLE
, 0),
1525 /* v9 */ movicc ("movleu", CONDLEU
, 0),
1526 /* v9 */ movfcc ("movlg", FCONDLG
, 0),
1527 /* v9 */ movcc ("movn", CONDN
, FCONDN
, 0),
1528 /* v9 */ movcc ("movne", CONDNE
, FCONDNE
, 0),
1529 /* v9 */ movicc ("movneg", CONDNEG
, 0),
1530 /* v9 */ movcc ("movnz", CONDNZ
, FCONDNZ
, F_ALIAS
),
1531 /* v9 */ movfcc ("movo", FCONDO
, 0),
1532 /* v9 */ movicc ("movpos", CONDPOS
, 0),
1533 /* v9 */ movfcc ("movu", FCONDU
, 0),
1534 /* v9 */ movfcc ("movue", FCONDUE
, 0),
1535 /* v9 */ movfcc ("movug", FCONDUG
, 0),
1536 /* v9 */ movfcc ("movuge", FCONDUGE
, 0),
1537 /* v9 */ movfcc ("movul", FCONDUL
, 0),
1538 /* v9 */ movfcc ("movule", FCONDULE
, 0),
1539 /* v9 */ movicc ("movvc", CONDVC
, 0),
1540 /* v9 */ movicc ("movvs", CONDVS
, 0),
1541 /* v9 */ movcc ("movz", CONDZ
, FCONDZ
, F_ALIAS
),
1543 #undef movicc /* v9 */
1544 #undef movfcc /* v9 */
1545 #undef movcc /* v9 */
1547 #define FM_SF 1 /* v9 - values for fpsize */
1548 #define FM_DF 2 /* v9 */
1549 #define FM_QF 3 /* v9 */
1551 #define fmoviccx(opcode, fpsize, args, cond, flags) /* v9 */ \
1552 { opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags, 0, 0, v9 }, \
1553 { opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags, 0, 0, v9 }
1555 #define fmovfccx(opcode, fpsize, args, fcond, flags) /* v9 */ \
1556 { opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags, 0, 0, v9 }, \
1557 { opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags, 0, 0, v9 }, \
1558 { opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags, 0, 0, v9 }, \
1559 { opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags, 0, 0, v9 }
1561 /* FIXME: use fmovicc/fmovfcc? */ /* v9 */
1562 #define fmovccx(opcode, fpsize, args, cond, fcond, flags) /* v9 */ \
1563 { opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags | F_FLOAT, 0, 0, v9 }, \
1564 { opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags | F_FLOAT, 0, 0, v9 }, \
1565 { opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags | F_FLOAT, 0, 0, v9 }, \
1566 { opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags | F_FLOAT, 0, 0, v9 }, \
1567 { opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags | F_FLOAT, 0, 0, v9 }, \
1568 { opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags | F_FLOAT, 0, 0, v9 }
1570 #define fmovicc(suffix, cond, flags) /* v9 */ \
1571 fmoviccx("fmovd" suffix, FM_DF, "B,H", cond, flags), \
1572 fmoviccx("fmovq" suffix, FM_QF, "R,J", cond, flags), \
1573 fmoviccx("fmovs" suffix, FM_SF, "f,g", cond, flags)
1575 #define fmovfcc(suffix, fcond, flags) /* v9 */ \
1576 fmovfccx("fmovd" suffix, FM_DF, "B,H", fcond, flags), \
1577 fmovfccx("fmovq" suffix, FM_QF, "R,J", fcond, flags), \
1578 fmovfccx("fmovs" suffix, FM_SF, "f,g", fcond, flags)
1580 #define fmovcc(suffix, cond, fcond, flags) /* v9 */ \
1581 fmovccx("fmovd" suffix, FM_DF, "B,H", cond, fcond, flags), \
1582 fmovccx("fmovq" suffix, FM_QF, "R,J", cond, fcond, flags), \
1583 fmovccx("fmovs" suffix, FM_SF, "f,g", cond, fcond, flags)
1585 /* v9 */ fmovcc ("a", CONDA
, FCONDA
, 0),
1586 /* v9 */ fmovicc ("cc", CONDCC
, 0),
1587 /* v9 */ fmovicc ("cs", CONDCS
, 0),
1588 /* v9 */ fmovcc ("e", CONDE
, FCONDE
, 0),
1589 /* v9 */ fmovcc ("g", CONDG
, FCONDG
, 0),
1590 /* v9 */ fmovcc ("ge", CONDGE
, FCONDGE
, 0),
1591 /* v9 */ fmovicc ("geu", CONDGEU
, F_ALIAS
),
1592 /* v9 */ fmovicc ("gu", CONDGU
, 0),
1593 /* v9 */ fmovcc ("l", CONDL
, FCONDL
, 0),
1594 /* v9 */ fmovcc ("le", CONDLE
, FCONDLE
, 0),
1595 /* v9 */ fmovicc ("leu", CONDLEU
, 0),
1596 /* v9 */ fmovfcc ("lg", FCONDLG
, 0),
1597 /* v9 */ fmovicc ("lu", CONDLU
, F_ALIAS
),
1598 /* v9 */ fmovcc ("n", CONDN
, FCONDN
, 0),
1599 /* v9 */ fmovcc ("ne", CONDNE
, FCONDNE
, 0),
1600 /* v9 */ fmovicc ("neg", CONDNEG
, 0),
1601 /* v9 */ fmovcc ("nz", CONDNZ
, FCONDNZ
, F_ALIAS
),
1602 /* v9 */ fmovfcc ("o", FCONDO
, 0),
1603 /* v9 */ fmovicc ("pos", CONDPOS
, 0),
1604 /* v9 */ fmovfcc ("u", FCONDU
, 0),
1605 /* v9 */ fmovfcc ("ue", FCONDUE
, 0),
1606 /* v9 */ fmovfcc ("ug", FCONDUG
, 0),
1607 /* v9 */ fmovfcc ("uge", FCONDUGE
, 0),
1608 /* v9 */ fmovfcc ("ul", FCONDUL
, 0),
1609 /* v9 */ fmovfcc ("ule", FCONDULE
, 0),
1610 /* v9 */ fmovicc ("vc", CONDVC
, 0),
1611 /* v9 */ fmovicc ("vs", CONDVS
, 0),
1612 /* v9 */ fmovcc ("z", CONDZ
, FCONDZ
, F_ALIAS
),
1614 #undef fmoviccx /* v9 */
1615 #undef fmovfccx /* v9 */
1616 #undef fmovccx /* v9 */
1617 #undef fmovicc /* v9 */
1618 #undef fmovfcc /* v9 */
1619 #undef fmovcc /* v9 */
1620 #undef FM_DF /* v9 */
1621 #undef FM_QF /* v9 */
1622 #undef FM_SF /* v9 */
1624 /* Coprocessor branches. */
1625 #define CBR(opcode, mask, lose, flags, arch) \
1626 { opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED, 0, 0, arch }, \
1627 { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED, 0, 0, arch }
1629 /* Floating point branches. */
1630 #define FBR(opcode, mask, lose, flags) \
1631 { opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED | F_FBR, 0, 0, v6 }, \
1632 { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED | F_FBR, 0, 0, v6 }
1634 /* V9 extended floating point branches. */
1635 #define FBRX(opcode, mask, lose, flags) /* v9 */ \
1636 { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), "6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1637 { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1638 { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a 6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1639 { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a,T 6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1640 { opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), ",N 6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1641 { opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a,N 6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1642 { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), "7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1643 { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), ",T 7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1644 { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a 7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1645 { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a,T 7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1646 { opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), ",N 7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1647 { opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a,N 7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1648 { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), "8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1649 { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), ",T 8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1650 { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a 8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1651 { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a,T 8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1652 { opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), ",N 8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1653 { opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a,N 8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1654 { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), "9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1655 { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), ",T 9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1656 { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a 9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1657 { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a,T 9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1658 { opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N 9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
1659 { opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }
1661 /* v9: We must put `FBRX' before `FBR', to ensure that we never match
1662 v9: something against an expression unless it is an expression. Otherwise,
1663 v9: we end up with undefined symbol tables entries, because they get added,
1664 v9: but are not deleted if the pattern fails to match. */
1666 #define CONDFC(fop, cop, mask, flags) \
1667 FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
1668 FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
1669 CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6notlet)
1671 #define CONDFCL(fop, cop, mask, flags) \
1672 FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
1673 FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
1674 CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6)
1676 #define CONDF(fop, mask, flags) \
1677 FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
1678 FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags)
1680 CONDFC ("fb", "cb", 0x8, F_UNBR
),
1681 CONDFCL ("fba", "cba", 0x8, F_UNBR
|F_ALIAS
),
1682 CONDFC ("fbe", "cb0", 0x9, F_CONDBR
),
1683 CONDF ("fbz", 0x9, F_CONDBR
|F_ALIAS
),
1684 CONDFC ("fbg", "cb2", 0x6, F_CONDBR
),
1685 CONDFC ("fbge", "cb02", 0xb, F_CONDBR
),
1686 CONDFC ("fbl", "cb1", 0x4, F_CONDBR
),
1687 CONDFC ("fble", "cb01", 0xd, F_CONDBR
),
1688 CONDFC ("fblg", "cb12", 0x2, F_CONDBR
),
1689 CONDFCL ("fbn", "cbn", 0x0, F_UNBR
),
1690 CONDFC ("fbne", "cb123", 0x1, F_CONDBR
),
1691 CONDF ("fbnz", 0x1, F_CONDBR
|F_ALIAS
),
1692 CONDFC ("fbo", "cb012", 0xf, F_CONDBR
),
1693 CONDFC ("fbu", "cb3", 0x7, F_CONDBR
),
1694 CONDFC ("fbue", "cb03", 0xa, F_CONDBR
),
1695 CONDFC ("fbug", "cb23", 0x5, F_CONDBR
),
1696 CONDFC ("fbuge", "cb023", 0xc, F_CONDBR
),
1697 CONDFC ("fbul", "cb13", 0x3, F_CONDBR
),
1698 CONDFC ("fbule", "cb013", 0xe, F_CONDBR
),
1705 #undef FBRX /* v9 */
1707 { "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0
|ASI(~0), "1+2", F_UNBR
|F_DELAYED
, 0, 0, v6
}, /* jmpl rs1+rs2,%g0 */
1708 { "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0
|ASI_RS2(~0), "1", F_UNBR
|F_DELAYED
, 0, 0, v6
}, /* jmpl rs1+%g0,%g0 */
1709 { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0
, "1+i", F_UNBR
|F_DELAYED
, 0, 0, v6
}, /* jmpl rs1+i,%g0 */
1710 { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0
, "i+1", F_UNBR
|F_DELAYED
, 0, 0, v6
}, /* jmpl i+rs1,%g0 */
1711 { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0
|RS1_G0
, "i", F_UNBR
|F_DELAYED
, 0, 0, v6
}, /* jmpl %g0+i,%g0 */
1712 { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0
|SIMM13(~0), "1", F_UNBR
|F_DELAYED
, 0, 0, v6
}, /* jmpl rs1+0,%g0 */
1714 { "nop", F2(0, 4), 0xfeffffff, "", 0, 0, 0, v6
}, /* sethi 0, %g0 */
1716 { "set", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS
, 0, 0, v6
},
1717 { "setuw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS
, 0, 0, v9
},
1718 { "setsw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS
, 0, 0, v9
},
1719 { "setx", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS
, 0, 0, v9
},
1721 { "sethi", F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, 0, 0, v6
},
1723 { "taddcc", F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1724 { "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "1,i,d", 0, 0, 0, v6
},
1725 { "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "i,1,d", 0, 0, 0, v6
},
1726 { "taddcctv", F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1727 { "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "1,i,d", 0, 0, 0, v6
},
1728 { "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "i,1,d", 0, 0, 0, v6
},
1730 { "tsubcc", F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1731 { "tsubcc", F3(2, 0x21, 1), F3(~2, ~0x21, ~1), "1,i,d", 0, 0, 0, v6
},
1732 { "tsubcctv", F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1733 { "tsubcctv", F3(2, 0x23, 1), F3(~2, ~0x23, ~1), "1,i,d", 0, 0, 0, v6
},
1735 { "unimp", F2(0x0, 0x0), 0xffc00000, "n", 0, 0, 0, v6notv9
},
1736 { "illtrap", F2(0, 0), F2(~0, ~0)|RD_G0
, "n", 0, 0, 0, v9
},
1738 /* This *is* a commutative instruction. */
1739 { "xnor", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1740 { "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "1,i,d", 0, 0, 0, v6
},
1741 { "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "i,1,d", 0, 0, 0, v6
},
1742 /* This *is* a commutative instruction. */
1743 { "xnorcc", F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1744 { "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "1,i,d", 0, 0, 0, v6
},
1745 { "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "i,1,d", 0, 0, 0, v6
},
1746 { "xor", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1747 { "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "1,i,d", 0, 0, 0, v6
},
1748 { "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,1,d", 0, 0, 0, v6
},
1749 { "xorcc", F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6
},
1750 { "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "1,i,d", 0, 0, 0, v6
},
1751 { "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "i,1,d", 0, 0, 0, v6
},
1753 { "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS
, 0, 0, v6
}, /* xnor rs1,%0,rd */
1754 { "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS
, 0, 0, v6
}, /* xnor rd,%0,rd */
1756 { "btog", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "2,r", F_ALIAS
, 0, 0, v6
}, /* xor rd,rs2,rd */
1757 { "btog", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,r", F_ALIAS
, 0, 0, v6
}, /* xor rd,i,rd */
1759 /* FPop1 and FPop2 are not instructions. Don't accept them. */
1761 { "fdtoi", F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0
, "B,g", F_FLOAT
, 0, 0, v6
},
1762 { "fstoi", F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0
, "f,g", F_FLOAT
, 0, 0, v6
},
1763 { "fqtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0
, "R,g", F_FLOAT
, 0, 0, v8
},
1765 { "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0
, "B,H", F_FLOAT
, 0, 0, v9
},
1766 { "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0
, "f,H", F_FLOAT
, 0, 0, v9
},
1767 { "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0
, "R,H", F_FLOAT
, 0, 0, v9
},
1769 { "fitod", F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0
, "f,H", F_FLOAT
, 0, 0, v6
},
1770 { "fitos", F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0
, "f,g", F_FLOAT
, 0, 0, v6
},
1771 { "fitoq", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0
, "f,J", F_FLOAT
, 0, 0, v8
},
1773 { "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0
, "B,H", F_FLOAT
, 0, 0, v9
},
1774 { "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0
, "B,g", F_FLOAT
, 0, 0, v9
},
1775 { "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0
, "B,J", F_FLOAT
, 0, 0, v9
},
1777 { "fdtoq", F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0
, "B,J", F_FLOAT
, 0, 0, v8
},
1778 { "fdtos", F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0
, "B,g", F_FLOAT
, 0, 0, v6
},
1779 { "fqtod", F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0
, "R,H", F_FLOAT
, 0, 0, v8
},
1780 { "fqtos", F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0
, "R,g", F_FLOAT
, 0, 0, v8
},
1781 { "fstod", F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0
, "f,H", F_FLOAT
, 0, 0, v6
},
1782 { "fstoq", F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0
, "f,J", F_FLOAT
, 0, 0, v8
},
1784 { "fdivd", F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", F_FLOAT
, 0, 0, v6
},
1785 { "fdivq", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT
, 0, 0, v8
},
1786 { "fdivx", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT
|F_ALIAS
, 0, 0, v8
},
1787 { "fdivs", F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", F_FLOAT
, 0, 0, v6
},
1788 { "fmuld", F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", F_FLOAT
, 0, 0, v6
},
1789 { "fmulq", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT
, 0, 0, v8
},
1790 { "fmulx", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT
|F_ALIAS
, 0, 0, v8
},
1791 { "fmuls", F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", F_FLOAT
, 0, 0, v6
},
1793 { "fdmulq", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT
, 0, 0, v8
},
1794 { "fdmulx", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT
|F_ALIAS
, 0, 0, v8
},
1795 { "fsmuld", F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", F_FLOAT
, HWCAP_FSMULD
, 0, v8
},
1797 { "fsqrtd", F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0
, "B,H", F_FLOAT
, 0, 0, v7
},
1798 { "fsqrtq", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0
, "R,J", F_FLOAT
, 0, 0, v8
},
1799 { "fsqrtx", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0
, "R,J", F_FLOAT
|F_ALIAS
, 0, 0, v8
},
1800 { "fsqrts", F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0
, "f,g", F_FLOAT
, 0, 0, v7
},
1802 { "fabsd", F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0
, "B,H", F_FLOAT
, 0, 0, v9
},
1803 { "fabsq", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0
, "R,J", F_FLOAT
, 0, 0, v9
},
1804 { "fabsx", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0
, "R,J", F_FLOAT
|F_ALIAS
, 0, 0, v9
},
1805 { "fabss", F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0
, "f,g", F_FLOAT
, 0, 0, v6
},
1806 { "fmovd", F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0
, "B,H", F_FLOAT
, 0, 0, v9
},
1807 { "fmovq", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0
, "R,J", F_FLOAT
, 0, 0, v9
},
1808 { "fmovx", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0
, "R,J", F_FLOAT
|F_ALIAS
, 0, 0, v9
},
1809 { "fmovs", F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0
, "f,g", F_FLOAT
, 0, 0, v6
},
1810 { "fnegd", F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0
, "B,H", F_FLOAT
, 0, 0, v9
},
1811 { "fnegq", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0
, "R,J", F_FLOAT
, 0, 0, v9
},
1812 { "fnegx", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0
, "R,J", F_FLOAT
|F_ALIAS
, 0, 0, v9
},
1813 { "fnegs", F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0
, "f,g", F_FLOAT
, 0, 0, v6
},
1815 { "faddd", F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", F_FLOAT
, 0, 0, v6
},
1816 { "faddq", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT
, 0, 0, v8
},
1817 { "faddx", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT
|F_ALIAS
, 0, 0, v8
},
1818 { "fadds", F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", F_FLOAT
, 0, 0, v6
},
1819 { "fsubd", F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", F_FLOAT
, 0, 0, v6
},
1820 { "fsubq", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT
, 0, 0, v8
},
1821 { "fsubx", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT
|F_ALIAS
, 0, 0, v8
},
1822 { "fsubs", F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", F_FLOAT
, 0, 0, v6
},
1824 #define CMPFCC(x) (((x)&0x3)<<25)
1826 { "fcmpd", F3F(2, 0x35, 0x052), F3F(~2, ~0x35, ~0x052)|RD_G0
, "v,B", F_FLOAT
, 0, 0, v6
},
1827 { "fcmpd", CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052), "6,v,B", F_FLOAT
, 0, 0, v9
},
1828 { "fcmpd", CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052), "7,v,B", F_FLOAT
, 0, 0, v9
},
1829 { "fcmpd", CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052), "8,v,B", F_FLOAT
, 0, 0, v9
},
1830 { "fcmpd", CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052), "9,v,B", F_FLOAT
, 0, 0, v9
},
1831 { "fcmped", F3F(2, 0x35, 0x056), F3F(~2, ~0x35, ~0x056)|RD_G0
, "v,B", F_FLOAT
, 0, 0, v6
},
1832 { "fcmped", CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056), "6,v,B", F_FLOAT
, 0, 0, v9
},
1833 { "fcmped", CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056), "7,v,B", F_FLOAT
, 0, 0, v9
},
1834 { "fcmped", CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056), "8,v,B", F_FLOAT
, 0, 0, v9
},
1835 { "fcmped", CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056), "9,v,B", F_FLOAT
, 0, 0, v9
},
1836 { "fcmpq", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0
, "V,R", F_FLOAT
, 0, 0, v8
},
1837 { "fcmpq", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT
, 0, 0, v9
},
1838 { "fcmpq", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT
, 0, 0, v9
},
1839 { "fcmpq", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT
, 0, 0, v9
},
1840 { "fcmpq", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT
, 0, 0, v9
},
1841 { "fcmpeq", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0
, "V,R", F_FLOAT
, 0, 0, v8
},
1842 { "fcmpeq", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT
, 0, 0, v9
},
1843 { "fcmpeq", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT
, 0, 0, v9
},
1844 { "fcmpeq", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT
, 0, 0, v9
},
1845 { "fcmpeq", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT
, 0, 0, v9
},
1846 { "fcmpx", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0
, "V,R", F_FLOAT
|F_ALIAS
, 0, 0, v8
},
1847 { "fcmpx", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT
|F_ALIAS
, 0, 0, v9
},
1848 { "fcmpx", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT
|F_ALIAS
, 0, 0, v9
},
1849 { "fcmpx", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT
|F_ALIAS
, 0, 0, v9
},
1850 { "fcmpx", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT
|F_ALIAS
, 0, 0, v9
},
1851 { "fcmpex", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0
, "V,R", F_FLOAT
|F_ALIAS
, 0, 0, v8
},
1852 { "fcmpex", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT
|F_ALIAS
, 0, 0, v9
},
1853 { "fcmpex", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT
|F_ALIAS
, 0, 0, v9
},
1854 { "fcmpex", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT
|F_ALIAS
, 0, 0, v9
},
1855 { "fcmpex", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT
|F_ALIAS
, 0, 0, v9
},
1856 { "fcmps", F3F(2, 0x35, 0x051), F3F(~2, ~0x35, ~0x051)|RD_G0
, "e,f", F_FLOAT
, 0, 0, v6
},
1857 { "fcmps", CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051), "6,e,f", F_FLOAT
, 0, 0, v9
},
1858 { "fcmps", CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051), "7,e,f", F_FLOAT
, 0, 0, v9
},
1859 { "fcmps", CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051), "8,e,f", F_FLOAT
, 0, 0, v9
},
1860 { "fcmps", CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051), "9,e,f", F_FLOAT
, 0, 0, v9
},
1861 { "fcmpes", F3F(2, 0x35, 0x055), F3F(~2, ~0x35, ~0x055)|RD_G0
, "e,f", F_FLOAT
, 0, 0, v6
},
1862 { "fcmpes", CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055), "6,e,f", F_FLOAT
, 0, 0, v9
},
1863 { "fcmpes", CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055), "7,e,f", F_FLOAT
, 0, 0, v9
},
1864 { "fcmpes", CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055), "8,e,f", F_FLOAT
, 0, 0, v9
},
1865 { "fcmpes", CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055), "9,e,f", F_FLOAT
, 0, 0, v9
},
1867 /* These Extended FPop (FIFO) instructions are new in the Fujitsu
1868 MB86934, replacing the CPop instructions from v6 and later
1871 #define EFPOP1_2(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op)|RS1_G0, args, 0, 0, 0, sparclite }
1872 #define EFPOP1_3(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op), args, 0, 0, 0, sparclite }
1873 #define EFPOP2_2(name, op, args) { name, F3F(2, 0x37, op), F3F(~2, ~0x37, ~op)|RD_G0, args, 0, 0, 0, sparclite }
1875 EFPOP1_2 ("efitod", 0x0c8, "f,H"),
1876 EFPOP1_2 ("efitos", 0x0c4, "f,g"),
1877 EFPOP1_2 ("efdtoi", 0x0d2, "B,g"),
1878 EFPOP1_2 ("efstoi", 0x0d1, "f,g"),
1879 EFPOP1_2 ("efstod", 0x0c9, "f,H"),
1880 EFPOP1_2 ("efdtos", 0x0c6, "B,g"),
1881 EFPOP1_2 ("efmovs", 0x001, "f,g"),
1882 EFPOP1_2 ("efnegs", 0x005, "f,g"),
1883 EFPOP1_2 ("efabss", 0x009, "f,g"),
1884 EFPOP1_2 ("efsqrtd", 0x02a, "B,H"),
1885 EFPOP1_2 ("efsqrts", 0x029, "f,g"),
1886 EFPOP1_3 ("efaddd", 0x042, "v,B,H"),
1887 EFPOP1_3 ("efadds", 0x041, "e,f,g"),
1888 EFPOP1_3 ("efsubd", 0x046, "v,B,H"),
1889 EFPOP1_3 ("efsubs", 0x045, "e,f,g"),
1890 EFPOP1_3 ("efdivd", 0x04e, "v,B,H"),
1891 EFPOP1_3 ("efdivs", 0x04d, "e,f,g"),
1892 EFPOP1_3 ("efmuld", 0x04a, "v,B,H"),
1893 EFPOP1_3 ("efmuls", 0x049, "e,f,g"),
1894 EFPOP1_3 ("efsmuld", 0x069, "e,f,H"),
1895 EFPOP2_2 ("efcmpd", 0x052, "v,B"),
1896 EFPOP2_2 ("efcmped", 0x056, "v,B"),
1897 EFPOP2_2 ("efcmps", 0x051, "e,f"),
1898 EFPOP2_2 ("efcmpes", 0x055, "e,f"),
1904 /* These are marked F_ALIAS, so that they won't conflict with sparclite insns
1905 present. Otherwise, the F_ALIAS flag is ignored. */
1906 { "cpop1", F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS
, 0, 0, v6notv9
},
1907 { "cpop2", F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS
, 0, 0, v6notv9
},
1909 /* sparclet specific insns */
1911 COMMUTEOP ("umac", 0x3e, letandleon
),
1912 COMMUTEOP ("smac", 0x3f, letandleon
),
1914 COMMUTEOP ("umacd", 0x2e, sparclet
),
1915 COMMUTEOP ("smacd", 0x2f, sparclet
),
1916 COMMUTEOP ("umuld", 0x09, sparclet
),
1917 COMMUTEOP ("smuld", 0x0d, sparclet
),
1919 { "shuffle", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, 0, 0, sparclet
},
1920 { "shuffle", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, 0, 0, sparclet
},
1922 /* The manual isn't completely accurate on these insns. The `rs2' field is
1923 treated as being 6 bits to account for 6 bit immediates to cpush. It is
1924 assumed that it is intended that bit 5 is 0 when rs2 contains a reg. */
1926 { "crdcxt", F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5
|RS2(~0), "U,d", 0, 0, 0, sparclet
},
1927 { "cwrcxt", F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5
|RS2(~0), "1,u", 0, 0, 0, sparclet
},
1928 { "cpush", F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5
|RD(~0), "1,2", 0, 0, 0, sparclet
},
1929 { "cpush", F3(2, 0x36, 1)|SLCPOP(0), F3(~2, ~0x36, ~1)|SLCPOP(~0)|RD(~0), "1,Y", 0, 0, 0, sparclet
},
1930 { "cpusha", F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5
|RD(~0), "1,2", 0, 0, 0, sparclet
},
1931 { "cpusha", F3(2, 0x36, 1)|SLCPOP(1), F3(~2, ~0x36, ~1)|SLCPOP(~1)|RD(~0), "1,Y", 0, 0, 0, sparclet
},
1932 { "cpull", F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5
|RS1(~0)|RS2(~0), "d", 0, 0, 0, sparclet
},
1935 /* sparclet coprocessor branch insns */
1936 #define SLCBCC2(opcode, mask, lose) \
1937 { opcode, (mask), ANNUL|(lose), "l", F_DELAYED|F_CONDBR, 0, 0, sparclet }, \
1938 { opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR, 0, 0, sparclet }
1939 #define SLCBCC(opcode, mask) \
1940 SLCBCC2(opcode, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)))
1942 /* cbn,cba can't be defined here because they're defined elsewhere and GAS
1943 requires all mnemonics of the same name to be consecutive. */
1944 /*SLCBCC("cbn", 0), - already defined */
1952 /*SLCBCC("cba", 8), - already defined */
1955 SLCBCC("cbnef", 11),
1957 SLCBCC("cbner", 13),
1958 SLCBCC("cbnfr", 14),
1959 SLCBCC("cbnefr", 15),
1964 { "casa", F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, 0, 0, v9andleon
},
1965 { "casa", F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, 0, 0, v9andleon
},
1966 { "casxa", F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, 0, 0, v9
},
1967 { "casxa", F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, 0, 0, v9
},
1969 /* v9 synthetic insns */
1970 { "iprefetch", F2(0, 1)|(2<<20)|BPRED
, F2(~0, ~1)|(1<<20)|ANNUL
|COND(~0), "G", 0, 0, 0, v9
}, /* bn,a,pt %xcc,label */
1971 { "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0
, "1,d", F_ALIAS
, 0, 0, v9
}, /* sra rs1,%g0,rd */
1972 { "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0
, "r", F_ALIAS
, 0, 0, v9
}, /* sra rd,%g0,rd */
1973 { "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0
, "1,d", F_ALIAS
, 0, 0, v9
}, /* srl rs1,%g0,rd */
1974 { "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0
, "r", F_ALIAS
, 0, 0, v9
}, /* srl rd,%g0,rd */
1975 { "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS
, 0, 0, v9
}, /* casa [rs1]ASI_P,rs2,rd */
1976 { "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS
, 0, 0, v9
}, /* casa [rs1]ASI_P_L,rs2,rd */
1977 { "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS
, 0, 0, v9
}, /* casxa [rs1]ASI_P,rs2,rd */
1978 { "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS
, 0, 0, v9
}, /* casxa [rs1]ASI_P_L,rs2,rd */
1980 /* Ultrasparc extensions */
1981 { "shutdown", F3F(2, 0x36, 0x080), F3F(~2, ~0x36, ~0x080)|RD_G0
|RS1_G0
|RS2_G0
, "", 0, HWCAP_VIS
, 0, v9a
},
1983 /* FIXME: Do we want to mark these as F_FLOAT, or something similar? */
1984 { "fpadd16", F3F(2, 0x36, 0x050), F3F(~2, ~0x36, ~0x050), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
1985 { "fpadd16s", F3F(2, 0x36, 0x051), F3F(~2, ~0x36, ~0x051), "e,f,g", 0, HWCAP_VIS
, 0, v9a
},
1986 { "fpadd32", F3F(2, 0x36, 0x052), F3F(~2, ~0x36, ~0x052), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
1987 { "fpadd32s", F3F(2, 0x36, 0x053), F3F(~2, ~0x36, ~0x053), "e,f,g", 0, HWCAP_VIS
, 0, v9a
},
1988 { "fpsub16", F3F(2, 0x36, 0x054), F3F(~2, ~0x36, ~0x054), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
1989 { "fpsub16s", F3F(2, 0x36, 0x055), F3F(~2, ~0x36, ~0x055), "e,f,g", 0, HWCAP_VIS
, 0, v9a
},
1990 { "fpsub32", F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
1991 { "fpsub32s", F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g", 0, HWCAP_VIS
, 0, v9a
},
1993 { "fpack32", F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
1994 { "fpack16", F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0
, "B,g", 0, HWCAP_VIS
, 0, v9a
},
1995 { "fpackfix", F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0
, "B,g", 0, HWCAP_VIS
, 0, v9a
},
1996 { "fexpand", F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0
, "f,H", 0, HWCAP_VIS
, 0, v9a
},
1997 { "fpmerge", F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H", 0, HWCAP_VIS
, 0, v9a
},
1999 /* Note that the mixing of 32/64 bit regs is intentional. */
2000 { "fmul8x16", F3F(2, 0x36, 0x031), F3F(~2, ~0x36, ~0x031), "e,B,H", 0, HWCAP_VIS
, 0, v9a
},
2001 { "fmul8x16au", F3F(2, 0x36, 0x033), F3F(~2, ~0x36, ~0x033), "e,f,H", 0, HWCAP_VIS
, 0, v9a
},
2002 { "fmul8x16al", F3F(2, 0x36, 0x035), F3F(~2, ~0x36, ~0x035), "e,f,H", 0, HWCAP_VIS
, 0, v9a
},
2003 { "fmul8sux16", F3F(2, 0x36, 0x036), F3F(~2, ~0x36, ~0x036), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
2004 { "fmul8ulx16", F3F(2, 0x36, 0x037), F3F(~2, ~0x36, ~0x037), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
2005 { "fmuld8sux16", F3F(2, 0x36, 0x038), F3F(~2, ~0x36, ~0x038), "e,f,H", 0, HWCAP_VIS
, 0, v9a
},
2006 { "fmuld8ulx16", F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039), "e,f,H", 0, HWCAP_VIS
, 0, v9a
},
2008 { "alignaddr", F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, HWCAP_VIS
, 0, v9a
},
2009 { "alignaddrl", F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, HWCAP_VIS
, 0, v9a
},
2010 { "faligndata", F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, HWCAP_VIS
, 0, v9a
}, /* faligndatag */
2011 { "faligndata", F3F(2, 0x36, 0x049), F3F(~2, ~0x36, ~0x049), "v,B,5,}", 0, 0, HWCAP2_SPARC5
, v9m
}, /* faligndatai */
2013 { "fzerod", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, HWCAP_VIS
, 0, v9a
},
2014 { "fzero", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2015 { "fzeros", F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g", 0, HWCAP_VIS
, 0, v9a
},
2016 { "foned", F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, HWCAP_VIS
, 0, v9a
},
2017 { "fone", F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2018 { "fones", F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g", 0, HWCAP_VIS
, 0, v9a
},
2019 { "fsrc1d", F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, HWCAP_VIS
, 0, v9a
},
2020 { "fsrc1", F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2021 { "fsrc1s", F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g", 0, HWCAP_VIS
, 0, v9a
},
2022 { "fsrc2d", F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, HWCAP_VIS
, 0, v9a
},
2023 { "fsrc2", F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2024 { "fsrc2s", F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g", 0, HWCAP_VIS
, 0, v9a
},
2025 { "fnot1d", F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, HWCAP_VIS
, 0, v9a
},
2026 { "fnot1", F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2027 { "fnot1s", F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g", 0, HWCAP_VIS
, 0, v9a
},
2028 { "fnot2d", F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, HWCAP_VIS
, 0, v9a
},
2029 { "fnot2", F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2030 { "fnot2s", F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g", 0, HWCAP_VIS
, 0, v9a
},
2031 { "ford", F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
2032 { "for", F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2033 { "fors", F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g", 0, HWCAP_VIS
, 0, v9a
},
2034 { "fnord", F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
2035 { "fnor", F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2036 { "fnors", F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g", 0, HWCAP_VIS
, 0, v9a
},
2037 { "fandd", F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
2038 { "fand", F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2039 { "fands", F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g", 0, HWCAP_VIS
, 0, v9a
},
2040 { "fnandd", F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
2041 { "fnand", F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2042 { "fnands", F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g", 0, HWCAP_VIS
, 0, v9a
},
2043 { "fxord", F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
2044 { "fxor", F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2045 { "fxors", F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g", 0, HWCAP_VIS
, 0, v9a
},
2046 { "fxnord", F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
2047 { "fxnor", F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2048 { "fxnors", F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g", 0, HWCAP_VIS
, 0, v9a
},
2049 { "fornot1d", F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
2050 { "fornot1", F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2051 { "fornot1s", F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g", 0, HWCAP_VIS
, 0, v9a
},
2052 { "fornot2d", F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
2053 { "fornot2", F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2054 { "fornot2s", F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g", 0, HWCAP_VIS
, 0, v9a
},
2055 { "fandnot1d", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
2056 { "fandnot1", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2057 { "fandnot1s", F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g", 0, HWCAP_VIS
, 0, v9a
},
2058 { "fandnot2d", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
2059 { "fandnot2", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2060 { "fandnot2s", F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g", 0, HWCAP_VIS
, 0, v9a
},
2062 { "fpcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, HWCAP_VIS
, 0, v9a
},
2063 { "fcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2064 { "fpcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, HWCAP_VIS
, 0, v9a
},
2065 { "fcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2066 { "fpcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, HWCAP_VIS
, 0, v9a
},
2067 { "fcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2068 { "fpcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, HWCAP_VIS
, 0, v9a
},
2069 { "fcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2070 { "fpcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, HWCAP_VIS
, 0, v9a
},
2071 { "fpcmpune16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2072 { "fcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2073 { "fpcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, HWCAP_VIS
, 0, v9a
},
2074 { "fpcmpune32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2075 { "fcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2076 { "fpcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, HWCAP_VIS
, 0, v9a
},
2077 { "fpcmpueq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2078 { "fcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2079 { "fpcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, HWCAP_VIS
, 0, v9a
},
2080 { "fpcmpueq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2081 { "fcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2083 { "edge8cc", F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, HWCAP_VIS
, 0, v9a
},
2084 { "edge8lcc", F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, HWCAP_VIS
, 0, v9a
},
2085 { "edge16cc", F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, HWCAP_VIS
, 0, v9a
},
2086 { "edge16lcc", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, HWCAP_VIS
, 0, v9a
},
2087 { "edge32cc", F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, HWCAP_VIS
, 0, v9a
},
2088 { "edge32lcc", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, HWCAP_VIS
, 0, v9a
},
2090 { "edge8", F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2091 { "edge8l", F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2092 { "edge16", F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2093 { "edge16l", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2094 { "edge32", F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2095 { "edge32l", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", F_ALIAS
, HWCAP_VIS
, 0, v9a
},
2097 { "pdist", F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H", 0, HWCAP_VIS
, 0, v9a
},
2099 { "array8", F3F(2, 0x36, 0x010), F3F(~2, ~0x36, ~0x010), "1,2,d", 0, HWCAP_VIS
, 0, v9a
},
2100 { "array16", F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, HWCAP_VIS
, 0, v9a
},
2101 { "array32", F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, HWCAP_VIS
, 0, v9a
},
2103 /* Cheetah instructions */
2104 { "edge8n", F3F(2, 0x36, 0x001), F3F(~2, ~0x36, ~0x001), "1,2,d", 0, HWCAP_VIS2
, 0, v9b
},
2105 { "edge8ln", F3F(2, 0x36, 0x003), F3F(~2, ~0x36, ~0x003), "1,2,d", 0, HWCAP_VIS2
, 0, v9b
},
2106 { "edge16n", F3F(2, 0x36, 0x005), F3F(~2, ~0x36, ~0x005), "1,2,d", 0, HWCAP_VIS2
, 0, v9b
},
2107 { "edge16ln", F3F(2, 0x36, 0x007), F3F(~2, ~0x36, ~0x007), "1,2,d", 0, HWCAP_VIS2
, 0, v9b
},
2108 { "edge32n", F3F(2, 0x36, 0x009), F3F(~2, ~0x36, ~0x009), "1,2,d", 0, HWCAP_VIS2
, 0, v9b
},
2109 { "edge32ln", F3F(2, 0x36, 0x00b), F3F(~2, ~0x36, ~0x00b), "1,2,d", 0, HWCAP_VIS2
, 0, v9b
},
2111 { "bmask", F3F(2, 0x36, 0x019), F3F(~2, ~0x36, ~0x019), "1,2,d", 0, HWCAP_VIS2
, 0, v9b
},
2112 { "bshuffle", F3F(2, 0x36, 0x04c), F3F(~2, ~0x36, ~0x04c), "v,B,H", 0, HWCAP_VIS2
, 0, v9b
},
2114 { "siam", F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0
|RS1_G0
|RS2(~7), "3", 0, HWCAP_VIS2
, 0, v9b
},
2116 { "fnadds", F3F(2, 0x34, 0x051), F3F(~2, ~0x34, ~0x051), "e,f,g", F_FLOAT
, HWCAP_HPC
, 0, v9d
},
2117 { "fnaddd", F3F(2, 0x34, 0x052), F3F(~2, ~0x34, ~0x052), "v,B,H", F_FLOAT
, HWCAP_HPC
, 0, v9d
},
2118 { "fnmuls", F3F(2, 0x34, 0x059), F3F(~2, ~0x34, ~0x059), "e,f,g", F_FLOAT
, HWCAP_HPC
, 0, v9d
},
2119 { "fnmuld", F3F(2, 0x34, 0x05a), F3F(~2, ~0x34, ~0x05a), "v,B,H", F_FLOAT
, HWCAP_HPC
, 0, v9d
},
2120 { "fhadds", F3F(2, 0x34, 0x061), F3F(~2, ~0x34, ~0x061), "e,f,g", F_FLOAT
, HWCAP_HPC
, 0, v9d
},
2121 { "fhaddd", F3F(2, 0x34, 0x062), F3F(~2, ~0x34, ~0x062), "v,B,H", F_FLOAT
, HWCAP_HPC
, 0, v9d
},
2122 { "fhsubs", F3F(2, 0x34, 0x065), F3F(~2, ~0x34, ~0x065), "e,f,g", F_FLOAT
, HWCAP_HPC
, 0, v9d
},
2123 { "fhsubd", F3F(2, 0x34, 0x066), F3F(~2, ~0x34, ~0x066), "v,B,H", F_FLOAT
, HWCAP_HPC
, 0, v9d
},
2124 { "fnhadds", F3F(2, 0x34, 0x071), F3F(~2, ~0x34, ~0x071), "e,f,g", F_FLOAT
, HWCAP_HPC
, 0, v9d
},
2125 { "fnhaddd", F3F(2, 0x34, 0x072), F3F(~2, ~0x34, ~0x072), "v,B,H", F_FLOAT
, HWCAP_HPC
, 0, v9d
},
2126 { "fnsmuld", F3F(2, 0x34, 0x079), F3F(~2, ~0x34, ~0x079), "e,f,H", F_FLOAT
, HWCAP_HPC
, 0, v9d
},
2127 { "fpmaddx", F3(2, 0x37, 0)|OPF_LOW4(0), F3(~2, ~0x37, 0)|OPF_LOW4(~0), "v,B,5,H", F_FLOAT
, HWCAP_IMA
, 0, v9v
},
2128 { "fmadds", F3(2, 0x37, 0)|OPF_LOW4(1), F3(~2, ~0x37, 0)|OPF_LOW4(~1), "e,f,4,g", F_FLOAT
, HWCAP_FMAF
, 0, v9d
},
2129 { "fmaddd", F3(2, 0x37, 0)|OPF_LOW4(2), F3(~2, ~0x37, 0)|OPF_LOW4(~2), "v,B,5,H", F_FLOAT
, HWCAP_FMAF
, 0, v9d
},
2130 { "fpmaddxhi", F3(2, 0x37, 0)|OPF_LOW4(4), F3(~2, ~0x37, 0)|OPF_LOW4(~4), "v,B,5,H", F_FLOAT
, HWCAP_IMA
, 0, v9v
},
2131 { "fmsubs", F3(2, 0x37, 0)|OPF_LOW4(5), F3(~2, ~0x37, 0)|OPF_LOW4(~5), "e,f,4,g", F_FLOAT
, HWCAP_FMAF
, 0, v9d
},
2132 { "fmsubd", F3(2, 0x37, 0)|OPF_LOW4(6), F3(~2, ~0x37, 0)|OPF_LOW4(~6), "v,B,5,H", F_FLOAT
, HWCAP_FMAF
, 0, v9d
},
2133 { "fnmsubs", F3(2, 0x37, 0)|OPF_LOW4(9), F3(~2, ~0x37, 0)|OPF_LOW4(~9), "e,f,4,g", F_FLOAT
, HWCAP_FMAF
, 0, v9d
},
2134 { "fnmsubd", F3(2, 0x37, 0)|OPF_LOW4(10), F3(~2, ~0x37, 0)|OPF_LOW4(~10), "v,B,5,H", F_FLOAT
, HWCAP_FMAF
, 0, v9d
},
2135 { "fnmadds", F3(2, 0x37, 0)|OPF_LOW4(13), F3(~2, ~0x37, 0)|OPF_LOW4(~13), "e,f,4,g", F_FLOAT
, HWCAP_FMAF
, 0, v9d
},
2136 { "fnmaddd", F3(2, 0x37, 0)|OPF_LOW4(14), F3(~2, ~0x37, 0)|OPF_LOW4(~14), "v,B,5,H", F_FLOAT
, HWCAP_FMAF
, 0, v9d
},
2137 { "fumadds", F3(2, 0x3f, 0)|OPF_LOW4(1), F3(~2, ~0x3f, 0)|OPF_LOW4(~1), "e,f,4,g", F_FLOAT
, HWCAP_FJFMAU
, 0, v9v
},
2138 { "fumaddd", F3(2, 0x3f, 0)|OPF_LOW4(2), F3(~2, ~0x3f, 0)|OPF_LOW4(~2), "v,B,5,H", F_FLOAT
, HWCAP_FJFMAU
, 0, v9v
},
2139 { "fumsubs", F3(2, 0x3f, 0)|OPF_LOW4(5), F3(~2, ~0x3f, 0)|OPF_LOW4(~5), "e,f,4,g", F_FLOAT
, HWCAP_FJFMAU
, 0, v9v
},
2140 { "fumsubd", F3(2, 0x3f, 0)|OPF_LOW4(6), F3(~2, ~0x3f, 0)|OPF_LOW4(~6), "v,B,5,H", F_FLOAT
, HWCAP_FJFMAU
, 0, v9v
},
2141 { "fnumsubs", F3(2, 0x3f, 0)|OPF_LOW4(9), F3(~2, ~0x3f, 0)|OPF_LOW4(~9), "e,f,4,g", F_FLOAT
, HWCAP_FJFMAU
, 0, v9v
},
2142 { "fnumsubd", F3(2, 0x3f, 0)|OPF_LOW4(10), F3(~2, ~0x3f, 0)|OPF_LOW4(~10), "v,B,5,H", F_FLOAT
, HWCAP_FJFMAU
, 0, v9v
},
2143 { "fnumadds", F3(2, 0x3f, 0)|OPF_LOW4(13), F3(~2, ~0x3f, 0)|OPF_LOW4(~13), "e,f,4,g", F_FLOAT
, HWCAP_FJFMAU
, 0, v9v
},
2144 { "fnumaddd", F3(2, 0x3f, 0)|OPF_LOW4(14), F3(~2, ~0x3f, 0)|OPF_LOW4(~14), "v,B,5,H", F_FLOAT
, HWCAP_FJFMAU
, 0, v9v
},
2145 { "addxc", F3F(2, 0x36, 0x011), F3F(~2, ~0x36, ~0x011), "1,2,d", 0, HWCAP_VIS3
, 0, v9d
},
2146 { "addxccc", F3F(2, 0x36, 0x013), F3F(~2, ~0x36, ~0x013), "1,2,d", 0, HWCAP_VIS3
, 0, v9d
},
2147 { "umulxhi", F3F(2, 0x36, 0x016), F3F(~2, ~0x36, ~0x016), "1,2,d", 0, HWCAP_VIS3
, 0, v9d
},
2148 { "lzcnt", F3F(2, 0x36, 0x017), F3F(~2, ~0x36, ~0x017), "2,d", 0, HWCAP_VIS3
, 0, v9d
},
2149 { "lzd", F3F(2, 0x36, 0x017), F3F(~2, ~0x36, ~0x017), "2,d", F_ALIAS
, HWCAP_VIS3
, 0, v9d
},
2150 { "cmask8", F3F(2, 0x36, 0x01b), F3F(~2, ~0x36, ~0x01b), "2", 0, HWCAP_VIS3
, 0, v9d
},
2151 { "cmask16", F3F(2, 0x36, 0x01d), F3F(~2, ~0x36, ~0x01d), "2", 0, HWCAP_VIS3
, 0, v9d
},
2152 { "cmask32", F3F(2, 0x36, 0x01f), F3F(~2, ~0x36, ~0x01f), "2", 0, HWCAP_VIS3
, 0, v9d
},
2153 { "fsll16", F3F(2, 0x36, 0x021), F3F(~2, ~0x36, ~0x021), "v,B,H", 0, HWCAP_VIS3
, 0, v9d
},
2154 { "fsrl16", F3F(2, 0x36, 0x023), F3F(~2, ~0x36, ~0x023), "v,B,H", 0, HWCAP_VIS3
, 0, v9d
},
2155 { "fsll32", F3F(2, 0x36, 0x025), F3F(~2, ~0x36, ~0x025), "v,B,H", 0, HWCAP_VIS3
, 0, v9d
},
2156 { "fsrl32", F3F(2, 0x36, 0x027), F3F(~2, ~0x36, ~0x027), "v,B,H", 0, HWCAP_VIS3
, 0, v9d
},
2157 { "fslas16", F3F(2, 0x36, 0x029), F3F(~2, ~0x36, ~0x029), "v,B,H", 0, HWCAP_VIS3
, 0, v9d
},
2158 { "fsra16", F3F(2, 0x36, 0x02b), F3F(~2, ~0x36, ~0x02b), "v,B,H", 0, HWCAP_VIS3
, 0, v9d
},
2159 { "fslas32", F3F(2, 0x36, 0x02d), F3F(~2, ~0x36, ~0x02d), "v,B,H", 0, HWCAP_VIS3
, 0, v9d
},
2160 { "fsra32", F3F(2, 0x36, 0x02f), F3F(~2, ~0x36, ~0x02f), "v,B,H", 0, HWCAP_VIS3
, 0, v9d
},
2161 { "pdistn", F3F(2, 0x36, 0x03f), F3F(~2, ~0x36, ~0x03f), "v,B,d", 0, HWCAP_VIS3
, 0, v9d
},
2162 { "fmean16", F3F(2, 0x36, 0x040), F3F(~2, ~0x36, ~0x040), "v,B,H", 0, HWCAP_VIS3
, 0, v9d
},
2163 { "fpadd64", F3F(2, 0x36, 0x042), F3F(~2, ~0x36, ~0x042), "v,B,H", 0, HWCAP_VIS3
, HWCAP2_VIS3B
, v9d
},
2164 { "fchksm16", F3F(2, 0x36, 0x044), F3F(~2, ~0x36, ~0x044), "v,B,H", 0, HWCAP_VIS3
, 0, v9d
},
2165 { "fpsub64", F3F(2, 0x36, 0x046), F3F(~2, ~0x36, ~0x046), "v,B,H", 0, HWCAP_VIS3
, HWCAP2_VIS3B
, v9d
},
2166 { "fpadds16", F3F(2, 0x36, 0x058), F3F(~2, ~0x36, ~0x058), "v,B,H", 0, HWCAP_VIS3
, 0, v9d
},
2167 { "fpadds16s", F3F(2, 0x36, 0x059), F3F(~2, ~0x36, ~0x059), "e,f,g", 0, HWCAP_VIS3
, 0, v9d
},
2168 { "fpadds32", F3F(2, 0x36, 0x05a), F3F(~2, ~0x36, ~0x05a), "v,B,H", 0, HWCAP_VIS3
, 0, v9d
},
2169 { "fpadds32s", F3F(2, 0x36, 0x05b), F3F(~2, ~0x36, ~0x05b), "e,f,g", 0, HWCAP_VIS3
, 0, v9d
},
2170 { "fpsubs16", F3F(2, 0x36, 0x05c), F3F(~2, ~0x36, ~0x05c), "v,B,H", 0, HWCAP_VIS3
, 0, v9d
},
2171 { "fpsubs16s", F3F(2, 0x36, 0x05d), F3F(~2, ~0x36, ~0x05d), "e,f,g", 0, HWCAP_VIS3
, 0, v9d
},
2172 { "fpsubs32", F3F(2, 0x36, 0x05e), F3F(~2, ~0x36, ~0x05e), "v,B,H", 0, HWCAP_VIS3
, 0, v9d
},
2173 { "fpsubs32s", F3F(2, 0x36, 0x05f), F3F(~2, ~0x36, ~0x05f), "e,f,g", 0, HWCAP_VIS3
, 0, v9d
},
2174 { "movdtox", F3F(2, 0x36, 0x110), F3F(~2, ~0x36, ~0x110), "B,d", F_FLOAT
, HWCAP_VIS3
, 0, v9d
},
2175 { "movstouw", F3F(2, 0x36, 0x111), F3F(~2, ~0x36, ~0x111), "f,d", F_FLOAT
, HWCAP_VIS3
, 0, v9d
},
2176 { "movstosw", F3F(2, 0x36, 0x113), F3F(~2, ~0x36, ~0x113), "f,d", F_FLOAT
, HWCAP_VIS3
, 0, v9d
},
2177 { "movxtod", F3F(2, 0x36, 0x118), F3F(~2, ~0x36, ~0x118), "2,H", F_FLOAT
, HWCAP_VIS3
, 0, v9d
},
2178 { "movwtos", F3F(2, 0x36, 0x119), F3F(~2, ~0x36, ~0x119), "2,g", F_FLOAT
, HWCAP_VIS3
, 0, v9d
},
2179 { "xmulx", F3F(2, 0x36, 0x115), F3F(~2, ~0x36, ~0x115), "1,2,d", 0, HWCAP_VIS3
, 0, v9d
},
2180 { "xmulxhi", F3F(2, 0x36, 0x116), F3F(~2, ~0x36, ~0x116), "1,2,d", 0, HWCAP_VIS3
, 0, v9d
},
2181 { "fpcmpule8", F3F(2, 0x36, 0x120), F3F(~2, ~0x36, ~0x120), "v,B,d", 0, HWCAP_VIS3
, HWCAP2_VIS3B
, v9d
},
2182 { "fucmple8", F3F(2, 0x36, 0x120), F3F(~2, ~0x36, ~0x120), "v,B,d", F_ALIAS
, HWCAP_VIS3
, 0, v9d
},
2183 { "fpcmpune8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", 0, HWCAP_VIS3
, HWCAP2_VIS3B
, v9d
},
2184 { "fpcmpne8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", F_PREF_ALIAS
, HWCAP_VIS3
, 0, v9d
},
2185 { "fucmpne8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", F_ALIAS
, HWCAP_VIS3
, 0, v9d
},
2186 { "fpcmpugt8", F3F(2, 0x36, 0x128), F3F(~2, ~0x36, ~0x128), "v,B,d", 0, HWCAP_VIS3
, HWCAP2_VIS3B
, v9d
},
2187 { "fucmpgt8", F3F(2, 0x36, 0x128), F3F(~2, ~0x36, ~0x128), "v,B,d", F_ALIAS
, HWCAP_VIS3
, 0, v9d
},
2188 { "fpcmpueq8", F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", 0, HWCAP_VIS3
, HWCAP2_VIS3B
, v9d
},
2189 { "fpcmpeq8", F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", F_PREF_ALIAS
, HWCAP_VIS3
, 0, v9d
},
2190 { "fucmpeq8", F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", F_ALIAS
, HWCAP_VIS3
, 0, v9d
},
2191 {"aes_kexpand0",F3F(2, 0x36, 0x130), F3F(~2, ~0x36, ~0x130), "v,B,H", F_FLOAT
, HWCAP_AES
, 0, v9e
},
2192 {"aes_kexpand2",F3F(2, 0x36, 0x131), F3F(~2, ~0x36, ~0x131), "v,B,H", F_FLOAT
, HWCAP_AES
, 0, v9e
},
2193 { "des_ip", F3F(2, 0x36, 0x134), F3F(~2, ~0x36, ~0x134), "v,H", F_FLOAT
, HWCAP_DES
, 0, v9e
},
2194 { "des_iip", F3F(2, 0x36, 0x135), F3F(~2, ~0x36, ~0x135), "v,H", F_FLOAT
, HWCAP_DES
, 0, v9e
},
2195 { "des_kexpand",F3F(2, 0x36, 0x136), F3F(~2, ~0x36, ~0x136), "v,X,H", F_FLOAT
, HWCAP_DES
, 0, v9e
},
2196 {"kasumi_fi_fi",F3F(2, 0x36, 0x138), F3F(~2, ~0x36, ~0x138), "v,B,H", F_FLOAT
, HWCAP_KASUMI
, 0, v9e
},
2197 { "camellia_fl",F3F(2, 0x36, 0x13c), F3F(~2, ~0x36, ~0x13c), "v,B,H", F_FLOAT
, HWCAP_CAMELLIA
, 0, v9e
},
2198 {"camellia_fli",F3F(2, 0x36, 0x13d), F3F(~2, ~0x36, ~0x13d), "v,B,H", F_FLOAT
, HWCAP_CAMELLIA
, 0, v9e
},
2199 { "md5", F3F(2, 0x36, 0x140), F3F(~2, ~0x36, ~0x140), "", F_FLOAT
, HWCAP_MD5
, 0, v9e
},
2200 { "sha1", F3F(2, 0x36, 0x141), F3F(~2, ~0x36, ~0x141), "", F_FLOAT
, HWCAP_SHA1
, 0, v9e
},
2201 { "sha256", F3F(2, 0x36, 0x142), F3F(~2, ~0x36, ~0x142), "", F_FLOAT
, HWCAP_SHA256
, 0, v9e
},
2202 { "sha512", F3F(2, 0x36, 0x143), F3F(~2, ~0x36, ~0x143), "", F_FLOAT
, HWCAP_SHA512
, 0, v9e
},
2203 { "sha3", F3F(2, 0x36, 0x144), F3F(~2, ~0x36, ~0x144), "", F_FLOAT
, 0, HWCAP2_SHA3
, m8
},
2204 { "crc32c", F3F(2, 0x36, 0x147), F3F(~2, ~0x36, ~0x147), "v,B,H", F_FLOAT
, HWCAP_CRC32C
, 0, v9e
},
2205 { "xmpmul", F3F(2, 0x36, 0x148)|RD(1), F3F(~2, ~0x36, ~0x148)|RD(~1), "X", F_FLOAT
, 0, HWCAP2_XMPMUL
, v9m
},
2206 { "mpmul", F3F(2, 0x36, 0x148), F3F(~2, ~0x36, ~0x148), "X", F_FLOAT
, HWCAP_MPMUL
, 0, v9e
},
2207 { "xmontmul", F3F(2, 0x36, 0x149)|RD(1), F3F(~2, ~0x36, ~0x149)|RD(~1), "X", F_FLOAT
, 0, HWCAP2_XMONT
, v9m
},
2208 { "montmul", F3F(2, 0x36, 0x149), F3F(~2, ~0x36, ~0x149), "X", F_FLOAT
, HWCAP_MONT
, 0, v9e
},
2209 { "xmontsqr", F3F(2, 0x36, 0x14a)|RD(1), F3F(~2, ~0x36, ~0x14a)|RD(~1), "X", F_FLOAT
, 0, HWCAP2_XMONT
, v9m
},
2210 { "montsqr", F3F(2, 0x36, 0x14a), F3F(~2, ~0x36, ~0x14a), "X", F_FLOAT
, HWCAP_MONT
, 0, v9e
},
2211 {"aes_eround01", F3F4(2, 0x19, 0), F3F4(~2, ~0x19, ~0), "v,B,5,H", F_FLOAT
, HWCAP_AES
, 0, v9e
},
2212 {"aes_eround23", F3F4(2, 0x19, 1), F3F4(~2, ~0x19, ~1), "v,B,5,H", F_FLOAT
, HWCAP_AES
, 0, v9e
},
2213 {"aes_dround01", F3F4(2, 0x19, 2), F3F4(~2, ~0x19, ~2), "v,B,5,H", F_FLOAT
, HWCAP_AES
, 0, v9e
},
2214 {"aes_dround23", F3F4(2, 0x19, 3), F3F4(~2, ~0x19, ~3), "v,B,5,H", F_FLOAT
, HWCAP_AES
, 0, v9e
},
2215 {"aes_eround01_l",F3F4(2, 0x19, 4), F3F4(~2, ~0x19, ~4), "v,B,5,H", F_FLOAT
, HWCAP_AES
, 0, v9e
},
2216 {"aes_eround23_l",F3F4(2, 0x19, 5), F3F4(~2, ~0x19, ~5), "v,B,5,H", F_FLOAT
, HWCAP_AES
, 0, v9e
},
2217 {"aes_dround01_l",F3F4(2, 0x19, 6), F3F4(~2, ~0x19, ~6), "v,B,5,H", F_FLOAT
, HWCAP_AES
, 0, v9e
},
2218 {"aes_dround23_l",F3F4(2, 0x19, 7), F3F4(~2, ~0x19, ~7), "v,B,5,H", F_FLOAT
, HWCAP_AES
, 0, v9e
},
2219 {"aes_kexpand1", F3F4(2, 0x19, 8), F3F4(~2, ~0x19, ~8), "v,B,),H", F_FLOAT
, HWCAP_AES
, 0, v9e
},
2220 {"des_round", F3F4(2, 0x19, 9), F3F4(~2, ~0x19, ~9), "v,B,5,H", F_FLOAT
, HWCAP_DES
, 0, v9e
},
2221 {"kasumi_fl_xor", F3F4(2, 0x19, 10), F3F4(~2, ~0x19, ~10), "v,B,5,H", F_FLOAT
, HWCAP_KASUMI
, 0, v9e
},
2222 {"kasumi_fi_xor", F3F4(2, 0x19, 11), F3F4(~2, ~0x19, ~11), "v,B,5,H", F_FLOAT
, HWCAP_KASUMI
, 0, v9e
},
2223 {"camellia_f", F3F4(2, 0x19, 12), F3F4(~2, ~0x19, ~12), "v,B,5,H", F_FLOAT
, HWCAP_CAMELLIA
, 0, v9e
},
2224 { "flcmps", CMPFCC(0)|F3F(2, 0x36, 0x151), CMPFCC(~0)|F3F(~2, ~0x36, ~0x151), "6,e,f", F_FLOAT
, HWCAP_HPC
, 0, v9d
},
2225 { "flcmps", CMPFCC(1)|F3F(2, 0x36, 0x151), CMPFCC(~1)|F3F(~2, ~0x36, ~0x151), "7,e,f", F_FLOAT
, HWCAP_HPC
, 0, v9d
},
2226 { "flcmps", CMPFCC(2)|F3F(2, 0x36, 0x151), CMPFCC(~2)|F3F(~2, ~0x36, ~0x151), "8,e,f", F_FLOAT
, HWCAP_HPC
, 0, v9d
},
2227 { "flcmps", CMPFCC(3)|F3F(2, 0x36, 0x151), CMPFCC(~3)|F3F(~2, ~0x36, ~0x151), "9,e,f", F_FLOAT
, HWCAP_HPC
, 0, v9d
},
2228 { "flcmpd", CMPFCC(0)|F3F(2, 0x36, 0x152), CMPFCC(~0)|F3F(~2, ~0x36, ~0x152), "6,v,B", F_FLOAT
, HWCAP_HPC
, 0, v9d
},
2229 { "flcmpd", CMPFCC(1)|F3F(2, 0x36, 0x152), CMPFCC(~1)|F3F(~2, ~0x36, ~0x152), "7,v,B", F_FLOAT
, HWCAP_HPC
, 0, v9d
},
2230 { "flcmpd", CMPFCC(2)|F3F(2, 0x36, 0x152), CMPFCC(~2)|F3F(~2, ~0x36, ~0x152), "8,v,B", F_FLOAT
, HWCAP_HPC
, 0, v9d
},
2231 { "flcmpd", CMPFCC(3)|F3F(2, 0x36, 0x152), CMPFCC(~3)|F3F(~2, ~0x36, ~0x152), "9,v,B", F_FLOAT
, HWCAP_HPC
, 0, v9d
},
2233 { "mwait", F3(2, 0x30, 0)|RD(28), F3(~2, ~0x30, ~0)|RD(~28)|RS1_G0
|ASI(~0), "2", 0, 0, HWCAP2_MWAIT
, v9m
}, /* mwait r */
2234 { "mwait", F3(2, 0x30, 1)|RD(28), F3(~2, ~0x30, ~1)|RD(~28)|RS1_G0
, "i", 0, 0, HWCAP2_MWAIT
, v9m
}, /* mwait imm */
2236 /* Other SPARC5 and VIS4.0 instructions. */
2238 { "subxc", F3(2, 0x36, 0)|OPF(0x41), F3(~2, ~0x36, ~0)|OPF(~0x41), "1,2,d", 0, 0, HWCAP2_SPARC5
, v9m
},
2239 { "subxccc", F3(2, 0x36, 0)|OPF(0x43), F3(~2, ~0x36, ~0)|OPF(~0x43), "1,2,d", 0, 0, HWCAP2_SPARC5
, v9m
},
2241 { "fpadd8", F3F(2, 0x36, 0x124), F3F(~2, ~0x36, ~0x124), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9m
},
2242 { "fpadds8", F3F(2, 0x36, 0x126), F3F(~2, ~0x36, ~0x126), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9m
},
2243 { "fpaddus8", F3F(2, 0x36, 0x127), F3F(~2, ~0x36, ~0x127), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9m
},
2244 { "fpaddus16", F3F(2, 0x36, 0x123), F3F(~2, ~0x36, ~0x123), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9m
},
2245 { "fpcmple8", F3F(2, 0x36, 0x034), F3F(~2, ~0x36, ~0x034), "v,B,d", 0, 0, HWCAP2_SPARC5
, v9m
},
2246 { "fpcmpgt8", F3F(2, 0x36, 0x03c), F3F(~2, ~0x36, ~0x03c), "v,B,d", 0, 0, HWCAP2_SPARC5
, v9m
},
2247 { "fpcmpule16", F3F(2, 0x36, 0x12e), F3F(~2, ~0x36, ~0x12e), "v,B,d", 0, 0, HWCAP2_SPARC5
, v9m
},
2248 { "fpcmpugt16", F3F(2, 0x36, 0x12b), F3F(~2, ~0x36, ~0x12b), "v,B,d", 0, 0, HWCAP2_SPARC5
, v9m
},
2249 { "fpcmpule32", F3F(2, 0x36, 0x12f), F3F(~2, ~0x36, ~0x12f), "v,B,d", 0, 0, HWCAP2_SPARC5
, v9m
},
2250 { "fpcmpugt32", F3F(2, 0x36, 0x12c), F3F(~2, ~0x36, ~0x12c), "v,B,d", 0, 0, HWCAP2_SPARC5
, v9m
},
2251 { "fpmax8", F3F(2, 0x36, 0x11d), F3F(~2, ~0x36, ~0x11d), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9m
},
2252 { "fpmax16", F3F(2, 0x36, 0x11e), F3F(~2, ~0x36, ~0x11e), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9m
},
2253 { "fpmax32", F3F(2, 0x36, 0x11f), F3F(~2, ~0x36, ~0x11f), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9m
},
2254 { "fpmaxu8", F3F(2, 0x36, 0x15d), F3F(~2, ~0x36, ~0x15d), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9m
},
2255 { "fpmaxu16", F3F(2, 0x36, 0x15e), F3F(~2, ~0x36, ~0x15e), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9m
},
2256 { "fpmaxu32", F3F(2, 0x36, 0x15f), F3F(~2, ~0x36, ~0x15f), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9m
},
2257 { "fpmin8", F3F(2, 0x36, 0x11a), F3F(~2, ~0x36, ~0x11a), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9m
},
2258 { "fpmin16", F3F(2, 0x36, 0x11b), F3F(~2, ~0x36, ~0x11b), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9m
},
2259 { "fpmin32", F3F(2, 0x36, 0x11c), F3F(~2, ~0x36, ~0x11c), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9m
},
2260 { "fpminu8", F3F(2, 0x36, 0x15a), F3F(~2, ~0x36, ~0x15a), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9m
},
2261 { "fpminu16", F3F(2, 0x36, 0x15b), F3F(~2, ~0x36, ~0x15b), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9m
},
2262 { "fpminu32", F3F(2, 0x36, 0x15c), F3F(~2, ~0x36, ~0x15c), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9m
},
2263 { "fpsub8", F3F(2, 0x36, 0x154), F3F(~2, ~0x36, ~0x154), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9m
},
2264 { "fpsubs8", F3F(2, 0x36, 0x156), F3F(~2, ~0x36, ~0x156), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9m
},
2265 { "fpsubus8", F3F(2, 0x36, 0x157), F3F(~2, ~0x36, ~0x157), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9m
},
2266 { "fpsubus16", F3F(2, 0x36, 0x153), F3F(~2, ~0x36, ~0x153), "v,B,H", 0, 0, HWCAP2_SPARC5
, v9m
},
2268 /* Other OSA2017 and M8 instructions. */
2270 { "dictunpack", F3F(2, 0x36, 0x1c), F3F(~2, ~0x36, ~0x1c), "v,X,H", 0, 0, HWCAP2_DICTUNP
, m8
},
2272 #define fpcmpshl(cbits, opf) \
2273 { "fpcmp" cbits "shl", F3F(2, 0x36, (opf)), F3F(~2, ~0x36, ~(opf)), "v,',|,d", 0, 0, HWCAP2_FPCMPSHL, m8 }
2275 fpcmpshl ("ule8", 0x190),
2276 fpcmpshl ("ugt8", 0x191),
2277 fpcmpshl ("eq8", 0x192),
2278 fpcmpshl ("ne8", 0x193),
2280 fpcmpshl ("ule16", 0x194),
2281 fpcmpshl ("ugt16", 0x195),
2282 fpcmpshl ("eq16", 0x196),
2283 fpcmpshl ("ne16", 0x197),
2285 fpcmpshl ("ule32", 0x198),
2286 fpcmpshl ("ugt32", 0x199),
2287 fpcmpshl ("eq32", 0x19a),
2288 fpcmpshl ("ne32", 0x19b),
2290 fpcmpshl ("de8", 0x45),
2291 fpcmpshl ("de16", 0x47),
2292 fpcmpshl ("de32", 0x4a),
2294 fpcmpshl ("ur8", 0x19c),
2295 fpcmpshl ("ur16", 0x19d),
2296 fpcmpshl ("ur32", 0x19e),
2300 #define fps64x(dir, opf) \
2301 { "fps" dir "64x", F3F(2, 0x36, (opf)), F3F(~2, ~0x36, ~(opf)), "v,B,H", 0, 0, HWCAP2_SPARC6, m8 }
2303 fps64x ("ll", 0x106),
2304 fps64x ("ra", 0x10f),
2305 fps64x ("rl", 0x107),
2309 #define ldm(width,opm,flags) \
2310 { "ldm" width, F3(3, 0x31, 0)|OPM((opm))|OPMI(0), F3(~3, ~0x31, ~0)|OPM(~(opm))|OPMI(~0), "[1+2],d", (flags), 0, HWCAP2_SPARC6, m8 }, \
2311 { "ldm" width, F3(3, 0x31, 0)|OPM((opm))|OPMI(0), F3(~3, ~0x31, ~0)|OPM(~(opm))|OPMI(~0)|RS2_G0, "[1],d", (flags), 0, HWCAP2_SPARC6, m8 }, /* ldm [rs1+%g0],d */ \
2312 { "ldm" width, F3(3, 0x31, 1)|OPM((opm)), F3(~3, ~0x31, ~1)|OPM(~(opm)), "[1+j],d", (flags), 0, HWCAP2_SPARC6, m8 }, \
2313 { "ldm" width, F3(3, 0x31, 1)|OPM((opm)), F3(~3, ~0x31, ~1)|OPM(~(opm)), "[j+1],d", (flags), 0, HWCAP2_SPARC6, m8 }, /* ldm [rs1+j],d */ \
2314 { "ldm" width, F3(3, 0x31, 1)|OPM((opm)), F3(~3, ~0x31, ~1)|OPM(~(opm))|RS1_G0, "[j],d", (flags), 0, HWCAP2_SPARC6, m8 }, \
2315 { "ldm" width, F3(3, 0x31, 1)|OPM((opm)), F3(~3, ~0x31, ~1)|OPM(~(opm))|SIMM10(~0), "[1],d", (flags), 0, HWCAP2_SPARC6, m8 } /* ldm [rs1+0],d */
2321 /* Note that opm=0x4 is reserved. */
2323 ldm ("ux", 0x5, F_ALIAS
),
2327 #define ldma(width,opm,flags) \
2328 { "ldm" width "a", F3(3, 0x31, 0)|OPM((opm))|OPMI(1), F3(~3, ~0x31, ~0)|OPM(~(opm))|OPMI(~1), "[1+2]o,d", (flags), 0, HWCAP2_SPARC6, m8 }, \
2329 { "ldm" width "a", F3(3, 0x31, 0)|OPM((opm))|OPMI(1), F3(~3, ~0x31, ~0)|OPM(~(opm))|OPMI(~1)|RS2_G0, "[1]o,d", (flags), 0, HWCAP2_SPARC6, m8 }
2331 ldma ("sh", 0x0, 0),
2332 ldma ("uh", 0x1, 0),
2333 ldma ("sw", 0x2, 0),
2334 ldma ("uw", 0x3, 0),
2335 /* Note that opm=0x4 is reserved. */
2337 ldma ("ux", 0x5, F_ALIAS
),
2341 #define ldmf(width,opm,rd) \
2342 { "ldmf" width, F3(3, 0x31, 0)|OPM((opm))|OPMI(0), F3(~3, ~0x31, ~0)|OPM(~(opm))|OPMI(~0), "[1+2]," rd, 0, 0, HWCAP2_SPARC6, m8 }, \
2343 { "ldmf" width, F3(3, 0x31, 0)|OPM((opm))|OPMI(0), F3(~3, ~0x31, ~0)|OPM(~(opm))|OPMI(~0)|RS2_G0, "[1]," rd, 0, 0, HWCAP2_SPARC6, m8 }, /* ldmf [rs1+%g0],rd */ \
2344 { "ldmf" width, F3(3, 0x31, 1)|OPM((opm)), F3(~3, ~0x31, ~1)|OPM(~(opm)), "[1+j]," rd, 0, 0, HWCAP2_SPARC6, m8 }, \
2345 { "ldmf" width, F3(3, 0x31, 1)|OPM((opm)), F3(~3, ~0x31, ~1)|OPM(~(opm)), "[j+1]," rd, 0, 0, HWCAP2_SPARC6, m8 }, /* ldmf [rs1+j],rd */ \
2346 { "ldmf" width, F3(3, 0x31, 1)|OPM((opm)), F3(~3, ~0x31, ~1)|OPM(~(opm))|RS1_G0, "[j]," rd, 0, 0, HWCAP2_SPARC6, m8 }, \
2347 { "ldmf" width, F3(3, 0x31, 1)|OPM((opm)), F3(~3, ~0x31, ~1)|OPM(~(opm))|SIMM10(~0), "[1]," rd, 0, 0, HWCAP2_SPARC6, m8 } /* ldmf [rs1+0],rd */
2349 ldmf ("s", 0x6, "g"),
2350 ldmf ("d", 0x7, "H"),
2354 #define ldmfa(width,opm,rd) \
2355 { "ldmf" width "a", F3(3, 0x31, 0)|OPM((opm))|OPMI(1), F3(~3, ~0x31, ~0)|OPM(~(opm))|OPMI(~1), "[1+2]o," rd, 0, 0, HWCAP2_SPARC6, m8 }, \
2356 { "ldmf" width "a", F3(3, 0x31, 0)|OPM((opm))|OPMI(1), F3(~3, ~0x31, ~0)|OPM(~(opm))|OPMI(~1)|RS2_G0, "[1]o," rd, 0, 0, HWCAP2_SPARC6, m8}
2358 ldmfa ("s", 0x6, "g"),
2359 ldmfa ("d", 0x7, "H"),
2363 #define stm(width,opm) \
2364 { "stm" width, F3(3, 0x35, 0)|OPM((opm))|OPMI(0), F3(~3, ~0x35, ~0)|OPM(~(opm))|OPMI(~0), "d,[1+2]", 0, 0, HWCAP2_SPARC6, m8 }, \
2365 { "stm" width, F3(3, 0x35, 0)|OPM((opm))|OPMI(0), F3(~3, ~0x35, ~0)|OPM(~(opm))|OPMI(~0)|RS2_G0, "d,[1]", 0, 0, HWCAP2_SPARC6, m8 }, /* stm d,[rs1+%g0] */ \
2366 { "stm" width, F3(3, 0x35, 1)|OPM((opm)), F3(~3, ~0x35, ~1)|OPM(~(opm)), "d,[1+j]", 0, 0, HWCAP2_SPARC6, m8 }, \
2367 { "stm" width, F3(3, 0x35, 1)|OPM((opm)), F3(~3, ~0x35, ~1)|OPM(~(opm)), "d,[j+1]", 0, 0, HWCAP2_SPARC6, m8 }, \
2368 { "stm" width, F3(3, 0x35, 1)|OPM((opm)), F3(~3, ~0x35, ~1)|OPM(~(opm))|RS1_G0, "d,[j]", 0, 0, HWCAP2_SPARC6, m8 }, \
2369 { "stm" width, F3(3, 0x35, 1)|OPM((opm)), F3(~3, ~0x35, ~1)|OPM(~(opm))|SIMM10(~0), "d,[1]", 0, 0, HWCAP2_SPARC6, m8 }
2377 #define stma(width,opm) \
2378 { "stm" width "a", F3(3, 0x35, 0)|OPM((opm))|OPMI(1), F3(~3, ~0x35, ~0)|OPM(~(opm))|OPMI(~1), "d,[1+2]o", 0, 0, HWCAP2_SPARC6, m8 }, \
2379 { "stm" width "a", F3(3, 0x35, 0)|OPM((opm))|OPMI(1), F3(~3, ~0x35, ~0)|OPM(~(opm))|OPMI(~1)|RS2_G0, "d,[1]o", 0, 0, HWCAP2_SPARC6, m8 }
2387 #define stmf(width, opm, rd) \
2388 { "stmf" width, F3(3, 0x35, 0)|OPM((opm))|OPMI(0), F3(~3, ~0x35, ~0)|OPM(~(opm))|OPMI(~0), rd ",[1+2]", 0, 0, HWCAP2_SPARC6, m8 }, \
2389 { "stmf" width, F3(3, 0x35, 0)|OPM((opm))|OPMI(0), F3(~3, ~0x35, ~0)|OPM(~(opm))|OPMI(~0)|RS2_G0, rd ",[1]", 0, 0, HWCAP2_SPARC6, m8 }, /* stmf rd,[rs1+%g0] */ \
2390 { "stmf" width, F3(3, 0x35, 1)|OPM((opm)), F3(~3, ~0x35, ~1)|OPM(~(opm)), rd ",[1+j]", 0, 0, HWCAP2_SPARC6, m8 }, \
2391 { "stmf" width, F3(3, 0x35, 1)|OPM((opm)), F3(~3, ~0x35, ~1)|OPM(~(opm)), rd ",[j+1]", 0, 0, HWCAP2_SPARC6, m8 }, \
2392 { "stmf" width, F3(3, 0x35, 1)|OPM((opm)), F3(~3, ~0x35, ~1)|OPM(~(opm))|RS1_G0, rd ",[j]", 0, 0, HWCAP2_SPARC6, m8 }, \
2393 { "stmf" width, F3(3, 0x35, 1)|OPM((opm)), F3(~3, ~0x35, ~1)|OPM(~(opm))|SIMM10(~0), rd ",[1]", 0, 0, HWCAP2_SPARC6, m8 }
2395 stmf ("s", 0x6, "g"),
2396 stmf ("d", 0x7, "H"),
2398 #define stmfa(width, opm, rd) \
2399 { "stmf" width "a", F3(3, 0x35, 0)|OPM((opm))|OPMI(1), F3(~3, ~0x35, ~0)|OPM(~(opm))|OPMI(~1), rd ",[1+2]o", 0, 0, HWCAP2_SPARC6, m8 }, \
2400 { "stmf" width "a", F3(3, 0x35, 0)|OPM((opm))|OPMI(1), F3(~3, ~0x35, ~0)|OPM(~(opm))|OPMI(~1)|RS2_G0, rd ",[1]o", 0, 0, HWCAP2_SPARC6, m8 }
2402 stmfa ("s", 0x6, "g"),
2403 stmfa ("d", 0x7, "H"),
2407 #define on(op,fcn,hwcaps2) \
2408 { "on" op, F3F(2, 0x36, 0x15)|ONFCN((fcn)), F3F(~2, ~0x36, ~0x15)|ONFCN(~(fcn)), ";,:,^", 0, 0, (hwcaps2), m8 }
2410 on ("add", 0x0, HWCAP2_ONADDSUB
),
2411 on ("sub", 0x1, HWCAP2_ONADDSUB
),
2412 on ("mul", 0x2, HWCAP2_ONMUL
),
2413 on ("div", 0x3, HWCAP2_ONDIV
),
2417 #define rev(what,width,fcn) \
2418 { "rev" what width, F3F(2, 0x36, 0x1e)|REVFCN((fcn)), F3F(~2, ~0x36, ~0x1e)|REVFCN(~(fcn)), "1,d", 0, 0, HWCAP2_SPARC6, m8 }
2420 rev ("bits", "b", 0x0),
2421 rev ("bytes", "h", 0x1),
2422 rev ("bytes", "w", 0x2),
2423 rev ("bytes", "x", 0x3),
2427 { "rle_burst", F3F(2, 0x36, 0x30), F3F(~2, ~0x36, ~0x30), "1,2,d", 0, 0, HWCAP2_RLE
, m8
},
2428 { "rle_length", F3F(2, 0x36, 0x32)|RS1(0), F3F(~2, ~0x36, ~0x32)|RS1(~0), "2,d", 0, 0, HWCAP2_RLE
, m8
},
2430 /* More v9 specific insns, these need to come last so they do not clash
2431 with v9a instructions such as "edge8" which looks like impdep1. */
2433 #define IMPDEP(name, code) \
2434 { name, F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9notv9a }, \
2435 { name, F3(2, code, 1), F3(~2, ~code, ~1), "1,i,d", 0, 0, 0, v9notv9a }, \
2436 { name, F3(2, code, 0), F3(~2, ~code, ~0), "x,1,2,d", 0, 0, 0, v9notv9a }, \
2437 { name, F3(2, code, 0), F3(~2, ~code, ~0), "x,e,f,g", 0, 0, 0, v9notv9a }
2439 IMPDEP ("impdep1", 0x36),
2440 IMPDEP ("impdep2", 0x37),
2446 const int sparc_num_opcodes
= ((sizeof sparc_opcodes
)/(sizeof sparc_opcodes
[0]));
2450 static sparc_asi asi_table
[] =
2452 /* These are in the v9 architecture manual. */
2453 /* The shorter versions appear first, they're here because Sun's as has them.
2454 Sun's as uses #ASI_P_L instead of #ASI_PL (which appears in the
2455 UltraSPARC architecture manual). */
2456 { 0x04, "#ASI_N", v9
},
2457 { 0x0c, "#ASI_N_L", v9
},
2458 { 0x10, "#ASI_AIUP", v9
},
2459 { 0x11, "#ASI_AIUS", v9
},
2460 { 0x18, "#ASI_AIUP_L", v9
},
2461 { 0x19, "#ASI_AIUS_L", v9
},
2462 { 0x80, "#ASI_P", v9
},
2463 { 0x81, "#ASI_S", v9
},
2464 { 0x82, "#ASI_PNF", v9
},
2465 { 0x83, "#ASI_SNF", v9
},
2466 { 0x88, "#ASI_P_L", v9
},
2467 { 0x89, "#ASI_S_L", v9
},
2468 { 0x8a, "#ASI_PNF_L", v9
},
2469 { 0x8b, "#ASI_SNF_L", v9
},
2470 { 0x04, "#ASI_NUCLEUS", v9
},
2471 { 0x0c, "#ASI_NUCLEUS_LITTLE", v9
},
2472 { 0x10, "#ASI_AS_IF_USER_PRIMARY", v9
},
2473 { 0x11, "#ASI_AS_IF_USER_SECONDARY", v9
},
2474 { 0x18, "#ASI_AS_IF_USER_PRIMARY_LITTLE", v9
},
2475 { 0x19, "#ASI_AS_IF_USER_SECONDARY_LITTLE", v9
},
2476 { 0x80, "#ASI_PRIMARY", v9
},
2477 { 0x81, "#ASI_SECONDARY", v9
},
2478 { 0x82, "#ASI_PRIMARY_NOFAULT", v9
},
2479 { 0x83, "#ASI_SECONDARY_NOFAULT", v9
},
2480 { 0x88, "#ASI_PRIMARY_LITTLE", v9
},
2481 { 0x89, "#ASI_SECONDARY_LITTLE", v9
},
2482 { 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE", v9
},
2483 { 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE", v9
},
2484 /* These are UltraSPARC and Niagara extensions. */
2485 { 0x14, "#ASI_PHYS_USE_EC", v9b
},
2486 { 0x15, "#ASI_PHYS_BYPASS_EC_E", v9b
},
2487 { 0x16, "#ASI_BLK_AIUP_4V", v9c
},
2488 { 0x17, "#ASI_BLK_AIUS_4V", v9c
},
2489 { 0x1c, "#ASI_PHYS_USE_EC_L", v9b
},
2490 { 0x1d, "#ASI_PHYS_BYPASS_EC_E_L", v9b
},
2491 { 0x1e, "#ASI_BLK_AIUP_L_4V", v9c
},
2492 { 0x1f, "#ASI_BLK_AIUS_L_4V", v9c
},
2493 { 0x20, "#ASI_SCRATCHPAD", v9c
},
2494 { 0x21, "#ASI_MMU", v9c
},
2495 { 0x23, "#ASI_BLK_INIT_QUAD_LDD_AIUS", v9c
},
2496 { 0x24, "#ASI_NUCLEUS_QUAD_LDD", v9b
},
2497 { 0x24, "#ASI_CORE_COMMIT_COUNT", m8
},
2498 { 0x24, "#ASI_CORE_SELECT_COUNT", m8
},
2499 { 0x25, "#ASI_QUEUE", v9c
},
2500 { 0x26, "#ASI_QUAD_LDD_PHYS_4V", v9c
},
2501 { 0x2c, "#ASI_NUCLEUS_QUAD_LDD_L", v9b
},
2502 { 0x30, "#ASI_PCACHE_DATA_STATUS", v9b
},
2503 { 0x31, "#ASI_PCACHE_DATA", v9b
},
2504 { 0x32, "#ASI_PCACHE_TAG", v9b
},
2505 { 0x33, "#ASI_PCACHE_SNOOP_TAG", v9b
},
2506 { 0x34, "#ASI_QUAD_LDD_PHYS", v9b
},
2507 { 0x38, "#ASI_WCACHE_VALID_BITS", v9b
},
2508 { 0x39, "#ASI_WCACHE_DATA", v9b
},
2509 { 0x3a, "#ASI_WCACHE_TAG", v9b
},
2510 { 0x3b, "#ASI_WCACHE_SNOOP_TAG", v9b
},
2511 { 0x3c, "#ASI_QUAD_LDD_PHYS_L", v9b
},
2512 { 0x40, "#ASI_SRAM_FAST_INIT", v9b
},
2513 { 0x41, "#ASI_CORE_AVAILABLE", v9b
},
2514 { 0x41, "#ASI_CORE_ENABLE_STAT", v9b
},
2515 { 0x41, "#ASI_CORE_ENABLE", v9b
},
2516 { 0x41, "#ASI_XIR_STEERING", v9b
},
2517 { 0x41, "#ASI_CORE_RUNNING_RW", v9b
},
2518 { 0x41, "#ASI_CORE_RUNNING_W1S", v9b
},
2519 { 0x41, "#ASI_CORE_RUNNING_W1C", v9b
},
2520 { 0x41, "#ASI_CORE_RUNNING_STAT", v9b
},
2521 { 0x41, "#ASI_CMT_ERROR_STEERING", v9b
},
2522 { 0x45, "#ASI_LSU_CONTROL_REG", v9b
},
2523 { 0x45, "#ASI_DCU_CONTROL_REG", v9b
},
2524 { 0x46, "#ASI_DCACHE_DATA", v9b
},
2525 { 0x47, "#ASI_DCACHE_TAG", v9b
},
2526 { 0x48, "#ASI_INTR_DISPATCH_STAT", v9b
},
2527 { 0x49, "#ASI_INTR_RECEIVE", v9b
},
2528 { 0x4b, "#ASI_ESTATE_ERROR_EN", v9b
},
2529 { 0x4c, "#ASI_AFSR", v9b
},
2530 { 0x4d, "#ASI_AFAR", v9b
},
2531 { 0x4e, "#ASI_EC_TAG_DATA", v9b
},
2532 { 0x48, "#ASI_ARF_ECC_REG", m8
},
2533 { 0x50, "#ASI_IMMU", v9b
},
2534 { 0x51, "#ASI_IMMU_TSB_8KB_PTR", v9b
},
2535 { 0x52, "#ASI_IMMU_TSB_64KB_PTR", v9b
},
2536 { 0x53, "#ASI_ITLB_PROBE", m8
},
2537 { 0x54, "#ASI_ITLB_DATA_IN", v9b
},
2538 { 0x55, "#ASI_ITLB_DATA_ACCESS", v9b
},
2539 { 0x56, "#ASI_ITLB_TAG_READ", v9b
},
2540 { 0x57, "#ASI_IMMU_DEMAP", v9b
},
2541 { 0x58, "#ASI_DMMU", v9b
},
2542 { 0x58, "#ASI_DSFAR", m8
},
2543 { 0x59, "#ASI_DMMU_TSB_8KB_PTR", v9b
},
2544 { 0x5a, "#ASI_DMMU_TSB_64KB_PTR", v9b
},
2545 { 0x5a, "#ASI_DTLB_PROBE_PRIMARY", m8
},
2546 { 0x5b, "#ASI_DMMU_TSB_DIRECT_PTR", v9b
},
2547 { 0x5b, "#ASI_DTLB_PROBE_REAL", m8
},
2548 { 0x5c, "#ASI_DTLB_DATA_IN", v9b
},
2549 { 0x5d, "#ASI_DTLB_DATA_ACCESS", v9b
},
2550 { 0x5e, "#ASI_DTLB_TAG_READ", v9b
},
2551 { 0x5f, "#ASI_DMMU_DEMAP", v9b
},
2552 { 0x60, "#ASI_IIU_INST_TRAP", v9b
},
2553 { 0x63, "#ASI_INTR_ID", v9b
},
2554 { 0x63, "#ASI_CORE_ID", v9b
},
2555 { 0x63, "#ASI_CESR_ID", v9b
},
2556 { 0x64, "#ASI_CORE_SELECT_COMMIT_NHT", m8
},
2557 { 0x66, "#ASI_IC_INSTR", v9b
},
2558 { 0x67, "#ASI_IC_TAG", v9b
},
2559 { 0x68, "#ASI_IC_STAG", v9b
},
2560 { 0x6f, "#ASI_BRPRED_ARRAY", v9b
},
2561 { 0x70, "#ASI_BLK_AIUP", v9b
},
2562 { 0x71, "#ASI_BLK_AIUS", v9b
},
2563 { 0x72, "#ASI_MCU_CTRL_REG", v9b
},
2564 { 0x74, "#ASI_EC_DATA", v9b
},
2565 { 0x75, "#ASI_EC_CTRL", v9b
},
2566 { 0x76, "#ASI_EC_W", v9b
},
2567 { 0x77, "#ASI_INTR_W", v9b
},
2568 { 0x77, "#ASI_INTR_DATAN_W", v9b
},
2569 { 0x77, "#ASI_INTR_DISPATCH_W", v9b
},
2570 { 0x78, "#ASI_BLK_AIUPL", v9b
},
2571 { 0x79, "#ASI_BLK_AIUSL", v9b
},
2572 { 0x7e, "#ASI_EC_R", v9b
},
2573 { 0x7f, "#ASI_INTR_R", v9b
},
2574 { 0x7f, "#ASI_INTR_DATAN_R", v9b
},
2575 { 0xc0, "#ASI_PST8_P", v9b
},
2576 { 0xc1, "#ASI_PST8_S", v9b
},
2577 { 0xc2, "#ASI_PST16_P", v9b
},
2578 { 0xc3, "#ASI_PST16_S", v9b
},
2579 { 0xc4, "#ASI_PST32_P", v9b
},
2580 { 0xc5, "#ASI_PST32_S", v9b
},
2581 { 0xc8, "#ASI_PST8_PL", v9b
},
2582 { 0xc9, "#ASI_PST8_SL", v9b
},
2583 { 0xca, "#ASI_PST16_PL", v9b
},
2584 { 0xcb, "#ASI_PST16_SL", v9b
},
2585 { 0xcc, "#ASI_PST32_PL", v9b
},
2586 { 0xcd, "#ASI_PST32_SL", v9b
},
2587 { 0xd0, "#ASI_FL8_P", v9b
},
2588 { 0xd1, "#ASI_FL8_S", v9b
},
2589 { 0xd2, "#ASI_FL16_P", v9b
},
2590 { 0xd3, "#ASI_FL16_S", v9b
},
2591 { 0xd8, "#ASI_FL8_PL", v9b
},
2592 { 0xd9, "#ASI_FL8_SL", v9b
},
2593 { 0xda, "#ASI_FL16_PL", v9b
},
2594 { 0xdb, "#ASI_FL16_SL", v9b
},
2595 { 0xe0, "#ASI_BLK_COMMIT_P", v9b
},
2596 { 0xe1, "#ASI_BLK_COMMIT_S", v9b
},
2597 { 0xe2, "#ASI_BLK_INIT_QUAD_LDD_P", v9b
},
2598 { 0xf0, "#ASI_BLK_P", v9b
},
2599 { 0xf1, "#ASI_BLK_S", v9b
},
2600 { 0xf8, "#ASI_BLK_PL", v9b
},
2601 { 0xf9, "#ASI_BLK_SL", v9b
},
2602 { 0x22, "#ASI_TWINX_AIUP", v9c
},
2603 { 0x23, "#ASI_TWINX_AIUS", v9c
},
2604 { 0x26, "#ASI_TWINX_REAL", v9c
},
2605 { 0x27, "#ASI_TWINX_N", v9c
},
2606 { 0x2A, "#ASI_TWINX_AIUP_L", v9c
},
2607 { 0x2B, "#ASI_TWINX_AIUS_L", v9c
},
2608 { 0x2E, "#ASI_TWINX_REAL_L", v9c
},
2609 { 0x2F, "#ASI_TWINX_NL", v9c
},
2610 { 0xE2, "#ASI_TWINX_P", v9c
},
2611 { 0xE3, "#ASI_TWINX_S", v9c
},
2612 { 0xEA, "#ASI_TWINX_PL", v9c
},
2613 { 0xEB, "#ASI_TWINX_SL", v9c
},
2614 /* These are ASIs from UA2005, UA2007, OSA2011, & OSA 2015 */
2615 { 0x12, "#ASI_MAIUP", v9m
},
2616 { 0x13, "#ASI_MAIUS", v9m
},
2617 { 0x14, "#ASI_REAL", v9c
},
2618 { 0x15, "#ASI_REAL_IO", v9c
},
2619 { 0x1c, "#ASI_REAL_L", v9c
},
2620 { 0x1d, "#ASI_REAL_IO_L", v9c
},
2621 { 0x30, "#ASI_AIPP", v9d
},
2622 { 0x31, "#ASI_AIPS", v9d
},
2623 { 0x36, "#ASI_AIPN", v9d
},
2624 { 0x38, "#ASI_AIPP_L", v9d
},
2625 { 0x39, "#ASI_AIPS_L", v9d
},
2626 { 0x3e, "#ASI_AIPN_L", v9d
},
2627 { 0x42, "#ASI_INST_MASK_REG", v9d
},
2628 { 0x42, "#ASI_LSU_DIAG_REG", v9d
},
2629 { 0x43, "#ASI_ERROR_INJECT_REG", v9d
},
2630 { 0x48, "#ASI_IRF_ECC_REG", v9d
},
2631 { 0x49, "#ASI_FRF_ECC_REG", v9d
},
2632 { 0x4e, "#ASI_SPARC_PWR_MGMT", v9d
},
2633 { 0x4f, "#ASI_HYP_SCRATCHPAD", v9c
},
2634 { 0x59, "#ASI_SCRATCHPAD_ACCESS", v9d
},
2635 { 0x5a, "#ASI_TICK_ACCESS", v9d
},
2636 { 0x5b, "#ASI_TSA_ACCESS", v9d
},
2637 { 0xb0, "#ASI_PIC", v9e
},
2638 { 0xf2, "#ASI_STBI_PM", v9e
},
2639 { 0xf3, "#ASI_STBI_SM", v9e
},
2640 { 0xfa, "#ASI_STBI_PLM", v9e
},
2641 { 0xfb, "#ASI_STBI_SLM", v9e
},
2645 /* Return the a pointer to the matching sparc_asi struct, NULL if not found. */
2648 sparc_encode_asi (const char *name
)
2652 for (p
= asi_table
; p
->name
; ++p
)
2653 if (strcmp (name
, p
->name
) == 0)
2659 /* Return the name for ASI value VALUE or NULL if not found. */
2662 sparc_decode_asi (int value
)
2666 for (p
= asi_table
; p
->name
; ++p
)
2667 if (value
== p
->value
)
2673 /* Utilities for argument parsing. */
2681 /* Look up NAME in TABLE. */
2684 lookup_name (const arg
*table
, const char *name
)
2688 for (p
= table
; p
->name
; ++p
)
2689 if (strcmp (name
, p
->name
) == 0)
2695 /* Look up VALUE in TABLE. */
2698 lookup_value (const arg
*table
, int value
)
2702 for (p
= table
; p
->name
; ++p
)
2703 if (value
== p
->value
)
2709 /* Handle membar masks. */
2711 static arg membar_table
[] =
2714 { 0x20, "#MemIssue" },
2715 { 0x10, "#Lookaside" },
2716 { 0x08, "#StoreStore" },
2717 { 0x04, "#LoadStore" },
2718 { 0x02, "#StoreLoad" },
2719 { 0x01, "#LoadLoad" },
2723 /* Return the value for membar arg NAME, or -1 if not found. */
2726 sparc_encode_membar (const char *name
)
2728 return lookup_name (membar_table
, name
);
2731 /* Return the name for membar value VALUE or NULL if not found. */
2734 sparc_decode_membar (int value
)
2736 return lookup_value (membar_table
, value
);
2739 /* Handle prefetch args. */
2741 static arg prefetch_table
[] =
2746 { 3, "#one_write" },
2748 { 16, "#invalidate" },
2749 { 17, "#unified", },
2750 { 20, "#n_reads_strong", },
2751 { 21, "#one_read_strong", },
2752 { 22, "#n_writes_strong", },
2753 { 23, "#one_write_strong", },
2757 /* Return the value for prefetch arg NAME, or -1 if not found. */
2760 sparc_encode_prefetch (const char *name
)
2762 return lookup_name (prefetch_table
, name
);
2765 /* Return the name for prefetch value VALUE or NULL if not found. */
2768 sparc_decode_prefetch (int value
)
2770 return lookup_value (prefetch_table
, value
);
2773 /* Handle sparclet coprocessor registers. */
2775 static arg sparclet_cpreg_table
[] =
2787 /* Return the value for sparclet cpreg arg NAME, or -1 if not found. */
2790 sparc_encode_sparclet_cpreg (const char *name
)
2792 return lookup_name (sparclet_cpreg_table
, name
);
2795 /* Return the name for sparclet cpreg value VALUE or NULL if not found. */
2798 sparc_decode_sparclet_cpreg (int value
)
2800 return lookup_value (sparclet_cpreg_table
, value
);
projects / deliverable / binutils-gdb.git / blob