opcodes/v850-opc.c

   1 #include "ansidecl.h"
   2 #include "opcode/v850.h"
   3
   4 /* Local insertion and extraction functions.  */
   5 static unsigned long insert_d9 PARAMS ((unsigned long, long, const char **));
   6 static long extract_d9 PARAMS ((unsigned long, int *));
   7
   8 /* regular opcode */
   9 #define OP(x)           ((x & 0x3f) << 5)
  10 #define OP_MASK         OP(0x3f)
  11
  12 /* conditional branch opcode */
  13 #define BOP(x)          ((0x0b << 7) | (x & 0x0f))
  14 #define BOP_MASK        ((0x0b << 7) | 0x0f)
  15
  16 /* one-word opcodes */
  17 #define one(x)          ((unsigned int) (x))
  18
  19 /* two-word opcodes */
  20 #define two(x,y)        ((unsigned int) (x) | ((unsigned int) (y) << 16))
  21
  22
  23 \f
  24 const struct v850_operand v850_operands[] = {
  25 #define UNUSED  0
  26   { 0, 0, 0, 0, 0 },
  27
  28 /* The R1 field in a format 1, 6, 7, or 9 insn. */
  29 #define R1      (UNUSED+1)
  30   { 5, 0, 0, 0, V850_OPERAND_REG },
  31
  32 /* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
  33 #define R2      (R1+1)
  34   { 5, 11, 0, 0, V850_OPERAND_REG },
  35
  36 /* The IMM5 field in a format 2 insn. */
  37 #define I5      (R2+1)
  38   { 5, 0, 0, 0, V850_OPERAND_SIGNED },
  39
  40 #define I5U     (I5+1)
  41   { 5, 0, 0, 0, 0 },
  42
  43 /* The IMM16 field in a format 6 insn. */
  44 #define I16     (I5U+1)
  45   { 16, 16, 0, 0, 0 },
  46
  47 /* The signed DISP7 field in a format 4 insn. */
  48 #define D7S     (I16+1)
  49   { 7, 0, 0, 0, V850_OPERAND_SIGNED },
  50
  51 /* The DISP9 field in a format 3 insn. */
  52 #define D9      (D7S+1)
  53   { 0, 0, insert_d9, extract_d9, V850_OPERAND_SIGNED },
  54
  55 /* The DISP16 field in a format 6 insn. */
  56 #define D16     (D9+1)
  57   { 16, 16, 0, 0, V850_OPERAND_SIGNED },
  58
  59 /* The DISP22 field in a format 4 insn. */
  60 #define D22     (D16+1)
  61   { 16, 0, 0, 0, 0 },
  62
  63 #define B3      (D22+1)
  64 /* The 3 bit immediate field in format 8 insn.  */
  65   { 3, 11, 0, 0, 0 },
  66
  67 #define CCCC    (B3+1)
  68 /* The 4 bit condition code in a setf instruction */
  69   { 4, 0, 0, 0, V850_OPERAND_CC },
  70
  71 /* The unsigned DISP8 field in a format 4 insn. */
  72 #define D8      (CCCC+1)
  73   { 8, 0, 0, 0, 0 },
  74
  75 /* System register operands.  */
  76 #define SR1     (D8+1)
  77   { 5, 0, 0, 0, V850_OPERAND_SRG }
  78 } ;
  79
  80 \f
  81 /* reg-reg instruction format (Format I) */
  82 #define IF1     {R1, R2}
  83
  84 /* imm-reg instruction format (Format II) */
  85 #define IF2     {I5, R2}
  86
  87 /* conditional branch instruction format (Format III) */
  88 #define IF3     {D9}
  89
  90 /* 16-bit load/store instruction (Format IV) */
  91 #define IF4A    {D7S, R1, R2}
  92 #define IF4B    {R2, D7S, R1}
  93 #define IF4C    {D8, R1, R2}
  94 #define IF4D    {R2, D8, R1}
  95
  96 /* Jump instruction (Format V) */
  97 #define IF5     {D22}
  98
  99 /* 3 operand instruction (Format VI) */
 100 #define IF6     {I16, R1, R2}
 101
 102 /* 32-bit load/store instruction (Format VII) */
 103 #define IF7A    {D16, R1, R2}
 104 #define IF7B    {R2, D16, R1}
 105
 106 /* Bit manipulation function.  */
 107
 108
 109 \f
 110 /* The opcode table.
 111
 112    The format of the opcode table is:
 113
 114    NAME         OPCODE          MASK            { OPERANDS }
 115
 116    NAME is the name of the instruction.
 117    OPCODE is the instruction opcode.
 118    MASK is the opcode mask; this is used to tell the disassembler
 119      which bits in the actual opcode must match OPCODE.
 120    OPERANDS is the list of operands.
 121
 122    The disassembler reads the table in order and prints the first
 123    instruction which matches, so this table is sorted to put more
 124    specific instructions before more general instructions.  It is also
 125    sorted by major opcode.  */
 126
 127 const struct v850_opcode v850_opcodes[] = {
 128 /* load/store instructions */
 129 { "sld.b",      one(0x0300),            one(0x0780),    IF4A, 2 },
 130 { "sld.h",      one(0x0400),            one(0x0780),    IF4A, 2 },
 131 { "sld.w",      one(0x0500),            one(0x0780),    IF4A, 2 },
 132 { "sst.b",      OP(0x00),               OP_MASK,        IF4B, 2 },
 133 { "sst.h",      OP(0x00),               OP_MASK,        IF4D, 2 },
 134 { "sst.w",      OP(0x00),               OP_MASK,        IF4D, 2 },
 135
 136 { "ld.b",       two(0x0700,0x0000),     two (0x07e0,0x0000),    IF7A, 4 },
 137 { "ld.h",       two(0x0720,0x0000),     two (0x07e0,0x0001),    IF7A, 4 },
 138 { "ld.w",       two(0x0720,0x0001),     two (0x07e0,0x0001),    IF7A, 4 },
 139 { "st.b",       two(0x0740,0x0000),     two (0x07e0,0x0000),    IF7B, 4 },
 140 { "st.h",       two(0x0760,0x0000),     two (0x07e0,0x0001),    IF7B, 4 },
 141 { "st.w",       two(0x0760,0x0001),     two (0x07e0,0x0001),    IF7B, 4 },
 142
 143 /* arithmetic operation instructions */
 144 { "mov",        OP(0x00),               OP_MASK,        IF1, 2 },
 145 { "mov",        OP(0x10),               OP_MASK,        IF2, 2 },
 146 { "movea",      OP(0x31),               OP_MASK,        IF6, 4 },
 147 { "movhi",      OP(0x32),               OP_MASK,        IF6, 4 },
 148 { "add",        OP(0x0e),               OP_MASK,        IF1, 2 },
 149 { "add",        OP(0x12),               OP_MASK,        IF2, 2 },
 150 { "addi",       OP(0x30),               OP_MASK,        IF6, 4 },
 151 { "sub",        OP(0x0d),               OP_MASK,        IF1, 2 },
 152 { "subr",       OP(0x0c),               OP_MASK,        IF1, 2 },
 153 { "mulh",       OP(0x07),               OP_MASK,        IF1, 2 },
 154 { "mulh",       OP(0x17),               OP_MASK,        IF2, 2 },
 155 { "mulhi",      OP(0x37),               OP_MASK,        IF6, 4 },
 156 { "divh",       OP(0x02),               OP_MASK,        IF1, 2 },
 157 { "cmp",        OP(0x0f),               OP_MASK,        IF1, 2 },
 158 { "cmp",        OP(0x13),               OP_MASK,        IF2, 2 },
 159 { "setf",       two(0x07e0,0x0000),     two(0x07f0,0xffff), {CCCC,R2}, 4 },
 160
 161 /* saturated operation instructions */
 162 { "satadd",     OP(0x06),               OP_MASK,        IF1, 2 },
 163 { "satadd",     OP(0x11),               OP_MASK,        IF2, 2 },
 164 { "satsub",     OP(0x05),               OP_MASK,        IF1, 2 },
 165 { "satsubi",    OP(0x33),               OP_MASK,        IF6, 4 },
 166 { "satsubr",    OP(0x04),               OP_MASK,        IF1, 2 },
 167
 168 /* logical operation instructions */
 169 { "tst",        OP(0x0b),               OP_MASK,        IF1, 2 },
 170 { "or",         OP(0x08),               OP_MASK,        IF1, 2 },
 171 { "ori",        OP(0x34),               OP_MASK,        IF6, 4 },
 172 { "and",        OP(0x0a),               OP_MASK,        IF1, 2 },
 173 { "andi",       OP(0x36),               OP_MASK,        IF6, 4 },
 174 { "xor",        OP(0x09),               OP_MASK,        IF1, 2 },
 175 { "xori",       OP(0x35),               OP_MASK,        IF6, 4 },
 176 { "not",        OP(0x01),               OP_MASK,        IF1, 2 },
 177 { "sar",        OP(0x15),               OP_MASK,        {I5U, R2}, 2 },
 178 { "sar",        two(0x07e0,0x00a0),     two(0x07e0,0xffff),     {R1,R2}, 4 },
 179 { "shl",        OP(0x16),               OP_MASK,                {I5U, R2}, 2 },
 180 { "shl",        two(0x07e0,0x00c0),     two(0x07e0,0xffff),     {R1,R2}, 4 },
 181 { "shr",        OP(0x14),               OP_MASK,                {I5U, R2}, 2 },
 182 { "shr",        two(0x07e0,0x0080),     two(0x07e0,0xffff),     {R1,R2}, 4 },
 183
 184 /* branch instructions */
 185         /* signed integer */
 186 { "bgt",        BOP(0xf),               BOP_MASK,       IF3, 2 },
 187 { "bge",        BOP(0xe),               BOP_MASK,       IF3, 2 },
 188 { "blt",        BOP(0x6),               BOP_MASK,       IF3, 2 },
 189 { "ble",        BOP(0x7),               BOP_MASK,       IF3, 2 },
 190         /* unsigned integer */
 191 { "bh",         BOP(0xb),               BOP_MASK,       IF3, 2 },
 192 { "bnh",        BOP(0x3),               BOP_MASK,       IF3, 2 },
 193 { "bl",         BOP(0x1),               BOP_MASK,       IF3, 2 },
 194 { "bnl",        BOP(0x9),               BOP_MASK,       IF3, 2 },
 195         /* common */
 196 { "be",         BOP(0x2),               BOP_MASK,       IF3, 2 },
 197 { "bne",        BOP(0xa),               BOP_MASK,       IF3, 2 },
 198         /* others */
 199 { "bv",         BOP(0x0),               BOP_MASK,       IF3, 2 },
 200 { "bnv",        BOP(0x8),               BOP_MASK,       IF3, 2 },
 201 { "bn",         BOP(0x4),               BOP_MASK,       IF3, 2 },
 202 { "bp",         BOP(0xc),               BOP_MASK,       IF3, 2 },
 203 { "bc",         BOP(0x1),               BOP_MASK,       IF3, 2 },
 204 { "bnc",        BOP(0x9),               BOP_MASK,       IF3, 2 },
 205 { "bz",         BOP(0x2),               BOP_MASK,       IF3, 2 },
 206 { "bnz",        BOP(0xa),               BOP_MASK,       IF3, 2 },
 207 { "br",         BOP(0x5),               BOP_MASK,       IF3, 2 },
 208 { "bsa",        BOP(0xd),               BOP_MASK,       IF3, 2 },
 209
 210 { "jmp",        one(0x0060),            one(0xffe0),    { R1}, 2 },
 211 { "jarl",       one(0x0780),            one(0xf83f),    { D22, R2 }, 4 },
 212 { "jr",         one(0x0780),            one(0xffe0),    { D22 }, 4 },
 213
 214 /* bit manipulation instructions */
 215 { "set1",       two(0x07c0,0x0000),     two(0xc7e0,0x0000),     {B3, D16, R1}, 4 },
 216 { "not1",       two(0x47c0,0x0000),     two(0xc7e0,0x0000),     {B3, D16, R1}, 4 },
 217 { "clr1",       two(0x87c0,0x0000),     two(0xc7e0,0x0000),     {B3, D16, R1}, 4 },
 218 { "tst1",       two(0xc7c0,0x0000),     two(0xc7e0,0x0000),     {B3, D16, R1}, 4 },
 219
 220 /* special instructions */
 221 { "di",         two(0x07e0,0x0160),     two(0xffff,0xffff),     {0}, 4 },
 222 { "ei",         two(0x87e0,0x0160),     two(0xffff,0xffff),     {0}, 4 },
 223 { "halt",       two(0x07e0,0x0120),     two(0xffff,0xffff),     {0}, 4 },
 224 { "reti",       two(0x07e0,0x0140),     two(0xffff,0xffff),     {0}, 4 },
 225 { "trap",       two(0x07e0,0x0100),     two(0xffe0,0xffff),     {I5U}, 4 },
 226 { "ldsr",       two(0x07e0,0x0020),     two(0x07e0,0xffff),     {R2,SR1}, 4 },
 227 { "stsr",       two(0x07e0,0x0040),     two(0x07e0,0xffff),     {SR1,R2}, 4 },
 228 { "nop",        one(0x00),              one(0xff),              {0}, 2 },
 229
 230 } ;
 231
 232 const int v850_num_opcodes =
 233   sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);
 234
 235 \f
 236 /* The functions used to insert and extract complicated operands.  */
 237
 238 static unsigned long
 239 insert_d9 (insn, value, errmsg)
 240      unsigned long insn;
 241      long value;
 242      const char **errmsg;
 243 {
 244   if (value > 511 || value <= -512)
 245     *errmsg = "value out of range";
 246
 247   return (insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3));
 248 }
 249
 250 static long
 251 extract_d9 (insn, invalid)
 252      unsigned long insn;
 253      int *invalid;
 254 {
 255   long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3);
 256
 257   if ((insn & 0x8000) != 0)
 258     ret -= 0x0200;
 259
 260   return ret;
 261 }