1 2016-05-06 Nick Clifton <nickc@redhat.com>
3 * simulator.c (do_FMLA_by_element): New function.
6 2016-04-27 Nick Clifton <nickc@redhat.com>
8 * simulator.c: Add TRACE_DECODE statements to all emulation
11 2016-03-30 Nick Clifton <nickc@redhat.com>
13 * cpustate.c (aarch64_set_reg_s32): New function.
14 (aarch64_set_reg_u32): New function.
15 (aarch64_get_FP_half): Place half precision value into the correct
17 (aarch64_set_FP_half): Likewise.
18 * cpustate.h: Add prototypes for aarch64_set_reg_s32 and
20 * memory.c (FETCH_FUNC): Cast the read value to the access type
21 before converting it to the return type. Rename to FETCH_FUNC64.
22 (FETCH_FUNC32): New macro. Duplicates FETCH_FUNC64 but for 32-bit
23 accesses. Use for 32-bit memory access functions.
24 * simulator.c (ldrsb_wb): Use sign extension not zero extension.
25 (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
26 (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
27 (ldrsh_scale_ext, ldrsw_abs): Likewise.
28 (ldrh32_abs): Store 32 bit value not 64-bits.
29 (ldrh32_wb, ldrh32_scale_ext): Likewise.
30 (do_vec_MOV_immediate): Fix computation of val.
31 (do_vec_MVNI): Likewise.
32 (DO_VEC_WIDENING_MUL): New macro.
33 (do_vec_mull): Use new macro.
34 (do_vec_mul): Use new macro.
35 (do_vec_MLA): Read values before writing.
36 (do_vec_xtl): Likewise.
37 (do_vec_SSHL): Select correct shift value.
38 (do_vec_USHL): Likewise.
39 (do_scalar_UCVTF): New function.
40 (do_scalar_vec): Call new function.
41 (store_pair_u64): Treat reads of SP as reads of XZR.
43 2016-03-29 Nick Clifton <nickc@redhat.com>
45 * cpustate.c: Remove space after asterisk in function parameters.
46 * decode.h (greg): Delete unused function.
47 (vreg, shift, extension, scaling, writeback, condcode): Likewise.
48 * simulator.c: Use INSTR macro in more places.
49 (HALT_NYI): Use sim_io_eprintf in place of fprintf.
50 Remove extraneous whitespace.
52 2016-03-23 Nick Clifton <nickc@redhat.com>
54 * cpustate.c (aarch64_get_FP_half): New function. Read a vector
55 register as a half precision floating point number.
56 (aarch64_set_FP_half): New function. Similar, but for setting
57 a half precision register.
58 (aarch64_get_thread_id): New function. Returns the value of the
60 (aarch64_get_FPCR): New function. Returns the value of the CPU's
61 floating point control register.
62 (aarch64_set_FPCR): New function. Set the value of the CPU's FPCR
64 * cpustate.h: Add prototypes for new functions.
65 * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
66 * memory.c: Use unaligned core access functions for all memory
68 * simulator.c (HALT_NYI): Generate an error message if tracing
69 will not tell the user why the simulator is halting.
70 (HALT_UNREACHABLE): Delete. Delete (unneeded) uses of the macro.
71 (INSTR): New time-saver macro.
72 (fldrb_abs): New function. Loads an 8-bit value using a scaled
74 (fldrh_abs): New function. Likewise for 16-bit values.
75 (do_vec_SSHL): Allow for negative shift values.
76 (do_vec_USHL): Likewise.
77 (do_vec_SHL): Correct computation of shift amount.
78 (do_vec_SSHR_USHR): Correct decision of signed vs unsigned
79 shifts and computation of shift value.
80 (clz): New function. Counts leading zero bits.
81 (do_vec_CLZ): New function. Implements CLZ (vector).
82 (do_vec_MOV_element): Call do_vec_CLZ.
83 (dexSimpleFPCondCompare): Implement.
84 (do_FCVT_half_to_single): New function. Implements one of the
86 (do_FCVT_half_to_double): New function. Likewise.
87 (do_FCVT_single_to_half): New function. Likewise.
88 (do_FCVT_double_to_half): New function. Likewise.
89 (dexSimpleFPDataProc1Source): Call new FCVT functions.
90 (do_scalar_SHL): Handle negative shifts.
91 (do_scalar_shift): Handle SSHR.
92 (do_scalar_USHL): New function.
93 (do_double_add): Simplify to just performing a double precision
94 add operation. Move remaining code into...
95 (do_scalar_vec): ... New function.
96 (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
98 (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
100 (system_set): New function.
101 (do_MSR_immediate): New function. Stub for now.
102 (do_MSR_reg): New function. Likewise. Partially implements MSR
104 (do_SYS): New function. Stub for now,
105 (dexSystem): Call new functions.
107 2016-03-18 Nick Clifton <nickc@redhat.com>
109 * cpustate.c: Remove spurious spaces from TRACE strings.
110 Print hex equivalents of floats and doubles.
111 Check element number against array size when accessing vector
113 (GET_VEC_ELEMENT): Fix off by one error checking for an invalid
115 (SET_VEC_ELEMENT): Likewise.
116 (GET_VEC_ELEMENT): And fix thinko using macro arguments.
118 * memory.c: Trace memory reads when --trace-memory is enabled.
119 Remove float and double load and store functions.
120 * memory.h (aarch64_get_mem_float): Delete prototype.
121 (aarch64_get_mem_double): Likewise.
122 (aarch64_set_mem_float): Likewise.
123 (aarch64_set_mem_double): Likewise.
124 * simulator (IS_SET): Always return either 0 or 1.
125 (IS_CLEAR): Likewise.
126 (fldrs_pcrel): Load and store floats using 32-bit memory accesses
127 and doubles using 64-bit memory accesses.
128 (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
129 (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
130 (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
131 (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
132 (store_pair_double, load_pair_float, load_pair_double): Likewise.
133 (do_vec_MUL_by_element): New function.
134 (do_vec_op2): Call do_vec_MUL_by_element.
135 (do_scalar_NEG): New function.
136 (do_double_add): Call do_scalar_NEG.
138 2016-03-03 Nick Clifton <nickc@redhat.com>
140 * simulator.c (set_flags_for_sub32): Correct type of signbit.
141 (CondCompare): Swap interpretation of bit 30.
142 (DO_ADDP): Delete macro.
143 (do_vec_ADDP): Copy source registers before starting to update
144 destination register.
145 (do_vec_FADDP): Likewise.
146 (do_vec_load_store): Fix computation of sizeof_operation.
147 (rbit64): Fix type of constant.
148 (aarch64_step): When displaying insn value, display all 32 bits.
150 2016-01-10 Mike Frysinger <vapier@gentoo.org>
152 * config.in, configure: Regenerate.
154 2016-01-10 Mike Frysinger <vapier@gentoo.org>
156 * configure: Regenerate.
158 2016-01-10 Mike Frysinger <vapier@gentoo.org>
160 * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
161 * configure: Regenerate.
163 2016-01-10 Mike Frysinger <vapier@gentoo.org>
165 * configure: Regenerate.
167 2016-01-10 Mike Frysinger <vapier@gentoo.org>
169 * configure: Regenerate.
171 2016-01-10 Mike Frysinger <vapier@gentoo.org>
173 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
174 * configure: Regenerate.
176 2016-01-10 Mike Frysinger <vapier@gentoo.org>
178 * configure: Regenerate.
180 2016-01-10 Mike Frysinger <vapier@gentoo.org>
182 * configure: Regenerate.
184 2016-01-09 Mike Frysinger <vapier@gentoo.org>
186 * config.in, configure: Regenerate.
188 2016-01-06 Mike Frysinger <vapier@gentoo.org>
190 * interp.c (sim_create_inferior): Mark argv and env const.
191 (sim_open): Mark argv const.
193 2016-01-05 Mike Frysinger <vapier@gentoo.org>
195 * interp.c: Delete dis-asm.h include.
196 (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
197 (sim_create_inferior): Delete disassemble init logic.
198 (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
199 (sim_open): Delete sim_add_option_table call.
200 * memory.c (mem_error): Delete disas check.
201 * simulator.c: Delete dis-asm.h include.
203 (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
204 (HALT_NYI): Likewise.
205 (handle_halt): Delete disas call.
206 (aarch64_step): Replace disas logic with TRACE_DISASM.
207 * simulator.h: Delete dis-asm.h include.
208 (aarch64_print_insn): Delete.
210 2016-01-04 Mike Frysinger <vapier@gentoo.org>
212 * simulator.c (MAX, MIN): Delete.
213 (do_vec_maxv): Change MAX to max and MIN to min.
214 (do_vec_fminmaxV): Likewise.
216 2016-01-04 Tristan Gingold <gingold@adacore.com>
218 * simulator.c: Remove syscall.h include.
220 2016-01-04 Mike Frysinger <vapier@gentoo.org>
222 * configure: Regenerate.
224 2016-01-03 Mike Frysinger <vapier@gentoo.org>
226 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
227 * configure: Regenerate.
229 2016-01-02 Mike Frysinger <vapier@gentoo.org>
231 * configure: Regenerate.
233 2015-12-27 Mike Frysinger <vapier@gentoo.org>
235 * interp.c (sim_dis_read): Change private_data to application_data.
236 (sim_create_inferior): Likewise.
238 2015-12-27 Mike Frysinger <vapier@gentoo.org>
240 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
242 2015-12-26 Mike Frysinger <vapier@gentoo.org>
244 * config.in, configure: Regenerate.
246 2015-12-26 Mike Frysinger <vapier@gentoo.org>
248 * interp.c (sim_create_inferior): Update comment and argv check.
250 2015-12-14 Nick Clifton <nickc@redhat.com>
252 * simulator.c (system_get): New function. Provides read
253 access to the dczid system register.
254 (do_mrs): New function - implements the MRS instruction.
255 (dexSystem): Call do_mrs for the MRS instruction. Halt on
256 unimplemented system instructions.
258 2015-11-24 Nick Clifton <nickc@redhat.com>
260 * configure.ac: New configure template.
261 * aclocal.m4: Generate.
262 * config.in: Generate.
263 * configure: Generate.
264 * cpustate.c: New file - functions for accessing AArch64 registers.
265 * cpustate.h: New header.
266 * decode.h: New header.
267 * interp.c: New file - interface between GDB and simulator.
268 * Makefile.in: New makefile template.
269 * memory.c: New file - functions for simulating aarch64 memory
271 * memory.h: New header.
272 * sim-main.h: New header.
273 * simulator.c: New file - aarch64 simulator functions.
274 * simulator.h: New header.