sim/aarch64/ChangeLog

   1 2019-03-28  Andrew Burgess  <andrew.burgess@embecosm.com>
   2
   3         * cpustate.c: Add 'libiberty.h' include.
   4         * interp.c: Add 'sim-assert.h' include.
   5
   6 2017-09-06  John Baldwin  <jhb@FreeBSD.org>
   7
   8         * configure: Regenerate.
   9
  10 2017-04-22  Jim Wilson  <jim.wilson@linaro.org>
  11
  12         * simulator.c (vec_load): Add M argument.  Rewrite to iterate over
  13         registers based on structure size.
  14         (LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load.
  15         (LD1_1): Replace with call to vec_load.
  16         (vec_store): Add new M argument.  Rewrite to iterate over registers
  17         based on structure size.
  18         (ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store.
  19         (ST1_1): Replace with call to vec_store.
  20
  21 2017-04-08  Jim Wilson  <jim.wilson@linaro.org>
  22
  23         * simulator.c (do_vec_FCVTL): New.
  24         (do_vec_op1): Call do_vec_FCVTL.
  25
  26         * simulator.c (do_scalar_FCMGE_zero, do_scalar_FCMLE_zero,
  27         do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero, do_scalar_FCMLT_zero): New.
  28         (do_scalar_vec): Add calls to new functions.
  29
  30 2017-03-25  Jim Wilson  <jim.wilson@linaro.org>
  31
  32         * simulator.c (set_flags_for_add32): Cast result to uint32_t in carry
  33         flag check.
  34
  35 2017-03-03  Jim Wilson  <jim.wilson@linaro.org>
  36
  37         * simulator.c (mul64hi): Shift carry left by 32.
  38         (smulh): Change signum to negate.  If negate, invert result, and add
  39         carry bit if low part of multiply result is zero.
  40
  41 2017-02-25  Jim Wilson  <jim.wilson@linaro.org>
  42
  43         * simulator.c (do_vec_SMOV_into_scalar): New.
  44         (do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar.
  45         Rewritten.
  46         (do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted.
  47         (do_vec_op1): Move do_vec_TRN call and do_vec_UZP call.  Add
  48         do_vec_SMOV_into_scalar call.  Delete do_vec_MOV_into_scalar and
  49         do_vec_UMOV calls.  Add do_vec_UMOV_into_scalar call.
  50
  51         * simulator.c (popcount): New.
  52         (do_vec_CNT): New.
  53         (do_vec_op1): Add do_vec_CNT call.
  54
  55 2017-02-19  Jim Wilson  <jim.wilson@linaro.org>
  56
  57         * simulator.c (do_vec_ADDV): Mov val declaration inside each case,
  58         with type set to input type size.
  59         (do_vec_xtl): Change bias from 3 to 4 for byte case.
  60
  61 2017-02-14  Jim Wilson  <jim.wilson@linaro.org>
  62
  63         * simulator.c (do_vec_MLA): Rewrite switch body.
  64
  65         * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
  66         2.  Move test_false if inside loop.  Fix logic for computing result
  67         stored to vd.
  68
  69         * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
  70         (do_vec_LDn_single, do_vec_STn_single): New.
  71         (do_vec_LDnR): Add and set new nregs var.  Replace switch on nregs with
  72         loop over nregs using new var n.  Add n times size to address in loop.
  73         Add n to vd in loop.
  74         (do_vec_load_store): Add comment for instruction bit 24.  New var
  75         single to hold instruction bit 24.  Add new code to use single.  Move
  76         ldnr support inside single if statements.  Fix ldnr register counts
  77         inside post if statement.  Change HALT_NYI calls to HALT_UNALLOC.
  78
  79 2017-01-23  Jim Wilson  <jim.wilson@linaro.org>
  80
  81         * simulator.c (do_vec_compare): Add case 0x23 for CMTST.
  82
  83 2017-01-17  Jim Wilson  <jim.wilson@linaro.org>
  84
  85         * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
  86         aarch64_set_reg_u64.  In case 2, call HALT_UNALLOC if not full.  In
  87         case 3, call HALT_UNALLOC unconditionally.
  88         (do_vec_XTN): Delete shifts.  In case 2, change index from i + 4 to
  89         i + 2.  Delete if on bias, change index to i + bias * X.
  90
  91 2017-01-09  Jim Wilson  <jim.wilson@linaro.org>
  92
  93         * simulator.c (do_vec_UZP): Rewrite.
  94
  95 2017-01-04  Jim Wilson  <jim.wilson@linaro.org>
  96
  97         * cpustate.c: Include math.h.
  98         (aarch64_set_FP_float): Use signbit to check for signed zero.
  99         (aarch64_set_FP_double): Likewise.
 100         * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
 101         (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
 102         args same size as third arg.
 103         (fmaxnm): Use isnan instead of fpclassify.
 104         (fminnm, dmaxnm, dminnm): Likewise.
 105         (do_vec_MLS): Reverse order of subtraction operands.
 106         (dexSimpleFPCondSelect): Call aarch64_get_FP_double or
 107         aarch64_get_FP_float to get source register contents.
 108         (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
 109         DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
 110         DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
 111         (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
 112         raise_exception calls.
 113
 114 2016-12-21  Jim Wilson  <jim.wilson@linaro.org>
 115
 116         * simulator.c (set_flags_for_float_compare): Add code to handle Inf.
 117         Add comment to document NaN issue.
 118         (set_flags_for_double_compare): Likewise.
 119
 120 2016-12-13  Jim Wilson  <jim.wilson@linaro.org>
 121
 122         * simulator.c (NEG, POS): Move before set_flags_for_add64.
 123         (set_flags_for_add64): Replace with a modified copy of
 124         set_flags_for_sub64.
 125
 126 2016-12-03  Jim Wilson  <jim.wilson@linaro.org>
 127
 128         * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
 129         (dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
 130
 131 2016-12-01  Jim Wilson  <jim.wilson@linaro.org>
 132
 133         * simulator.c (fsturs): Switch use of rn and st variables.
 134         (fsturd, fsturq): Likewise
 135
 136 2016-08-15  Mike Frysinger  <vapier@gentoo.org>
 137
 138         * interp.c: Include bfd.h.
 139         (symcount, symtab, aarch64_get_sym_value): Delete.
 140         (remove_useless_symbols): Change count type to long.
 141         (aarch64_get_func): Add SIM_DESC to arg list.  Add symcount
 142         and symtab local variables.
 143         (sim_create_inferior): Delete storage.  Replace symbol code
 144         with a call to trace_load_symbols.
 145         * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h
 146         includes.
 147         (aarch64_get_heap_start): Change aarch64_get_sym_value to
 148         trace_sym_value.
 149         * memory.h: Delete bfd.h include.
 150         (mem_add_blk): Delete unused prototype.
 151         * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func.
 152         * simulator.c (aarch64_get_func): Add SIM_DESC to arg list.
 153         (aarch64_get_sym_value): Delete.
 154
 155 2016-08-12  Nick Clifton  <nickc@redhat.com>
 156
 157         * simulator.c (aarch64_step): Revert pervious delta.
 158         (aarch64_run): Call sim_events_tick after each
 159         instruction is simulated, and if necessary call
 160         sim_events_process.
 161         * simulator.h: Revert previous delta.
 162
 163 2016-08-11  Nick Clifton  <nickc@redhat.com>
 164
 165         * interp.c (sim_create_inferior): Allow for being called with a
 166         NULL abfd parameter.  If a bfd is provided, initialise the sim
 167         with that start address.
 168         * simulator.c (HALT_NYI): Just print out the numeric value of the
 169         instruction when not tracing.
 170         (aarch64_step): Change from static to global.
 171         * simulator.h: Add a prototype for aarch64_step().
 172
 173 2016-07-27  Alan Modra  <amodra@gmail.com>
 174
 175         * memory.c: Don't include libbfd.h.
 176
 177 2016-07-21  Nick Clifton  <nickc@redhat.com>
 178
 179         * simulator.c (fsqrts): Use sqrtf rather than sqrt.
 180
 181 2016-06-30  Jim Wilson  <jim.wilson@linaro.org>
 182
 183         * cpustate.h: Include config.h.
 184         (union GRegisterValue): Add WORDS_BIGENDIAN check.  For big endian code
 185         use anonymous structs to align members.
 186         * simulator.c (aarch64_step): Use sim_core_read_buffer and
 187         endian_le2h_4 to read instruction from pc.
 188
 189 2016-05-06  Nick Clifton  <nickc@redhat.com>
 190
 191         * simulator.c (do_FMLA_by_element): New function.
 192         (do_vec_op2): Call it.
 193
 194 2016-04-27  Nick Clifton  <nickc@redhat.com>
 195
 196         * simulator.c: Add TRACE_DECODE statements to all emulation
 197         functions.
 198
 199 2016-03-30  Nick Clifton  <nickc@redhat.com>
 200
 201         * cpustate.c (aarch64_set_reg_s32): New function.
 202         (aarch64_set_reg_u32): New function.
 203         (aarch64_get_FP_half): Place half precision value into the correct
 204         slot of the union.
 205         (aarch64_set_FP_half): Likewise.
 206         * cpustate.h: Add prototypes for aarch64_set_reg_s32 and
 207         aarch64_set_reg_u32.
 208         * memory.c (FETCH_FUNC): Cast the read value to the access type
 209         before converting it to the return type.  Rename to FETCH_FUNC64.
 210         (FETCH_FUNC32): New macro.  Duplicates FETCH_FUNC64 but for 32-bit
 211         accesses.  Use for 32-bit memory access functions.
 212         * simulator.c (ldrsb_wb): Use sign extension not zero extension.
 213         (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
 214         (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
 215         (ldrsh_scale_ext, ldrsw_abs): Likewise.
 216         (ldrh32_abs): Store 32 bit value not 64-bits.
 217         (ldrh32_wb, ldrh32_scale_ext): Likewise.
 218         (do_vec_MOV_immediate): Fix computation of val.
 219         (do_vec_MVNI): Likewise.
 220         (DO_VEC_WIDENING_MUL): New macro.
 221         (do_vec_mull): Use new macro.
 222         (do_vec_mul): Use new macro.
 223         (do_vec_MLA): Read values before writing.
 224         (do_vec_xtl): Likewise.
 225         (do_vec_SSHL): Select correct shift value.
 226         (do_vec_USHL): Likewise.
 227         (do_scalar_UCVTF): New function.
 228         (do_scalar_vec): Call new function.
 229         (store_pair_u64): Treat reads of SP as reads of XZR.
 230
 231 2016-03-29  Nick Clifton  <nickc@redhat.com>
 232
 233         * cpustate.c: Remove space after asterisk in function parameters.
 234         * decode.h (greg): Delete unused function.
 235         (vreg, shift, extension, scaling, writeback, condcode): Likewise.
 236         * simulator.c: Use INSTR macro in more places.
 237         (HALT_NYI): Use sim_io_eprintf in place of fprintf.
 238         Remove extraneous whitespace.
 239
 240 2016-03-23  Nick Clifton  <nickc@redhat.com>
 241
 242         * cpustate.c (aarch64_get_FP_half): New function.  Read a vector
 243         register as a half precision floating point number.
 244         (aarch64_set_FP_half): New function.  Similar, but for setting
 245         a half precision register.
 246         (aarch64_get_thread_id): New function.  Returns the value of the
 247         CPU's TPIDR register.
 248         (aarch64_get_FPCR): New function.  Returns the value of the CPU's
 249         floating point control register.
 250         (aarch64_set_FPCR): New function.  Set the value of the CPU's FPCR
 251         register.
 252         * cpustate.h: Add prototypes for new functions.
 253         * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
 254         * memory.c: Use unaligned core access functions for all memory
 255         reads and writes.
 256         * simulator.c (HALT_NYI): Generate an error message if tracing
 257         will not tell the user why the simulator is halting.
 258         (HALT_UNREACHABLE): Delete.  Delete (unneeded) uses of the macro.
 259         (INSTR): New time-saver macro.
 260         (fldrb_abs): New function.  Loads an 8-bit value using a scaled
 261         offset.
 262         (fldrh_abs): New function.  Likewise for 16-bit values.
 263         (do_vec_SSHL): Allow for negative shift values.
 264         (do_vec_USHL): Likewise.
 265         (do_vec_SHL): Correct computation of shift amount.
 266         (do_vec_SSHR_USHR): Correct decision of signed vs unsigned
 267         shifts and computation of shift value.
 268         (clz): New function.  Counts leading zero bits.
 269         (do_vec_CLZ): New function.  Implements CLZ (vector).
 270         (do_vec_MOV_element): Call do_vec_CLZ.
 271         (dexSimpleFPCondCompare): Implement.
 272         (do_FCVT_half_to_single): New function.  Implements one of the
 273         FCVT operations.
 274         (do_FCVT_half_to_double): New function.  Likewise.
 275         (do_FCVT_single_to_half): New function.  Likewise.
 276         (do_FCVT_double_to_half): New function.  Likewise.
 277         (dexSimpleFPDataProc1Source): Call new FCVT functions.
 278         (do_scalar_SHL): Handle negative shifts.
 279         (do_scalar_shift): Handle SSHR.
 280         (do_scalar_USHL): New function.
 281         (do_double_add): Simplify to just performing a double precision
 282         add operation.  Move remaining code into...
 283         (do_scalar_vec): ... New function.
 284         (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
 285         functions.
 286         (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
 287         registers.
 288         (system_set): New function.
 289         (do_MSR_immediate): New function.  Stub for now.
 290         (do_MSR_reg): New function.  Likewise. Partially implements MSR
 291         instruction.
 292         (do_SYS): New function.  Stub for now,
 293         (dexSystem): Call new functions.
 294
 295 2016-03-18  Nick Clifton  <nickc@redhat.com>
 296
 297         * cpustate.c: Remove spurious spaces from TRACE strings.
 298         Print hex equivalents of floats and doubles.
 299         Check element number against array size when accessing vector
 300         registers.
 301         (GET_VEC_ELEMENT): Fix off by one error checking for an invalid
 302         element index.
 303         (SET_VEC_ELEMENT): Likewise.
 304         (GET_VEC_ELEMENT): And fix thinko using macro arguments.
 305
 306         * memory.c: Trace memory reads when --trace-memory is enabled.
 307         Remove float and double load and store functions.
 308         * memory.h (aarch64_get_mem_float): Delete prototype.
 309         (aarch64_get_mem_double): Likewise.
 310         (aarch64_set_mem_float): Likewise.
 311         (aarch64_set_mem_double): Likewise.
 312         * simulator (IS_SET): Always return either 0 or 1.
 313         (IS_CLEAR): Likewise.
 314         (fldrs_pcrel): Load and store floats using 32-bit memory accesses
 315         and doubles using 64-bit memory accesses.
 316         (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
 317         (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
 318         (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
 319         (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
 320         (store_pair_double, load_pair_float, load_pair_double): Likewise.
 321         (do_vec_MUL_by_element): New function.
 322         (do_vec_op2): Call do_vec_MUL_by_element.
 323         (do_scalar_NEG): New function.
 324         (do_double_add): Call do_scalar_NEG.
 325
 326 2016-03-03  Nick Clifton  <nickc@redhat.com>
 327
 328         * simulator.c (set_flags_for_sub32): Correct type of signbit.
 329         (CondCompare): Swap interpretation of bit 30.
 330         (DO_ADDP): Delete macro.
 331         (do_vec_ADDP): Copy source registers before starting to update
 332         destination register.
 333         (do_vec_FADDP): Likewise.
 334         (do_vec_load_store): Fix computation of sizeof_operation.
 335         (rbit64): Fix type of constant.
 336         (aarch64_step): When displaying insn value, display all 32 bits.
 337
 338 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 339
 340         * config.in, configure: Regenerate.
 341
 342 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 343
 344         * configure: Regenerate.
 345
 346 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 347
 348         * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
 349         * configure: Regenerate.
 350
 351 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 352
 353         * configure: Regenerate.
 354
 355 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 356
 357         * configure: Regenerate.
 358
 359 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 360
 361         * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
 362         * configure: Regenerate.
 363
 364 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 365
 366         * configure: Regenerate.
 367
 368 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 369
 370         * configure: Regenerate.
 371
 372 2016-01-09  Mike Frysinger  <vapier@gentoo.org>
 373
 374         * config.in, configure: Regenerate.
 375
 376 2016-01-06  Mike Frysinger  <vapier@gentoo.org>
 377
 378         * interp.c (sim_create_inferior): Mark argv and env const.
 379         (sim_open): Mark argv const.
 380
 381 2016-01-05  Mike Frysinger  <vapier@gentoo.org>
 382
 383         * interp.c: Delete dis-asm.h include.
 384         (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
 385         (sim_create_inferior): Delete disassemble init logic.
 386         (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
 387         (sim_open): Delete sim_add_option_table call.
 388         * memory.c (mem_error): Delete disas check.
 389         * simulator.c: Delete dis-asm.h include.
 390         (disas): Delete.
 391         (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
 392         (HALT_NYI): Likewise.
 393         (handle_halt): Delete disas call.
 394         (aarch64_step): Replace disas logic with TRACE_DISASM.
 395         * simulator.h: Delete dis-asm.h include.
 396         (aarch64_print_insn): Delete.
 397
 398 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 399
 400         * simulator.c (MAX, MIN): Delete.
 401         (do_vec_maxv): Change MAX to max and MIN to min.
 402         (do_vec_fminmaxV): Likewise.
 403
 404 2016-01-04  Tristan Gingold  <gingold@adacore.com>
 405
 406         * simulator.c: Remove syscall.h include.
 407
 408 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 409
 410         * configure: Regenerate.
 411
 412 2016-01-03  Mike Frysinger  <vapier@gentoo.org>
 413
 414         * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
 415         * configure: Regenerate.
 416
 417 2016-01-02  Mike Frysinger  <vapier@gentoo.org>
 418
 419         * configure: Regenerate.
 420
 421 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 422
 423         * interp.c (sim_dis_read): Change private_data to application_data.
 424         (sim_create_inferior): Likewise.
 425
 426 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 427
 428         * Makefile.in (SIM_OBJS): Delete sim-hload.o.
 429
 430 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 431
 432         * config.in, configure: Regenerate.
 433
 434 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 435
 436         * interp.c (sim_create_inferior): Update comment and argv check.
 437
 438 2015-12-14  Nick Clifton  <nickc@redhat.com>
 439
 440         * simulator.c (system_get): New function.  Provides read
 441         access to the dczid system register.
 442         (do_mrs): New function - implements the MRS instruction.
 443         (dexSystem): Call do_mrs for the MRS instruction.  Halt on
 444         unimplemented system instructions.
 445
 446 2015-11-24  Nick Clifton  <nickc@redhat.com>
 447
 448         * configure.ac: New configure template.
 449         * aclocal.m4: Generate.
 450         * config.in: Generate.
 451         * configure: Generate.
 452         * cpustate.c: New file - functions for accessing AArch64 registers.
 453         * cpustate.h: New header.
 454         * decode.h: New header.
 455         * interp.c: New file - interface between GDB and simulator.
 456         * Makefile.in: New makefile template.
 457         * memory.c: New file - functions for simulating aarch64 memory
 458         accesses.
 459         * memory.h: New header.
 460         * sim-main.h: New header.
 461         * simulator.c: New file - aarch64 simulator functions.
 462         * simulator.h: New header.