1 /* run front end support for arm
2 Copyright (C) 1995-2019 Free Software Foundation, Inc.
4 This file is part of ARM SIM.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19 /* This file provides the interface between the simulator and
20 run.c and gdb (when the simulator is linked with gdb).
21 All simulator interaction should go through this file. */
29 #include "gdb/callback.h"
30 #include "gdb/remote-sim.h"
32 #include "sim-options.h"
36 #include "gdb/sim-arm.h"
37 #include "gdb/signals.h"
38 #include "libiberty.h"
42 /* TODO: This should get pulled from the SIM_DESC. */
43 host_callback
*sim_callback
;
45 /* TODO: This should get merged into sim_cpu. */
46 struct ARMul_State
*state
;
48 /* Memory size in bytes. */
49 /* TODO: Memory should be converted to the common memory module. */
50 static int mem_size
= (1 << 21);
56 /* TODO: Tracing should be converted to common tracing module. */
61 static struct disassemble_info info
;
62 static char opbuf
[1000];
65 op_printf (char *buf
, char *fmt
, ...)
71 ret
= vsprintf (opbuf
+ strlen (opbuf
), fmt
, ap
);
77 sim_dis_read (bfd_vma memaddr ATTRIBUTE_UNUSED
,
80 struct disassemble_info
* info
)
82 ARMword val
= (ARMword
) *((ARMword
*) info
->application_data
);
86 * ptr
++ = val
& 0xFF;
93 print_insn (ARMword instr
)
96 disassembler_ftype disassemble_fn
;
99 info
.application_data
= & instr
;
100 disassemble_fn
= disassembler (bfd_arch_arm
, 0, 0, NULL
);
101 size
= disassemble_fn (0, & info
);
102 fprintf (stderr
, " %*s\n", size
, opbuf
);
112 ARMul_EmulateInit ();
113 state
= ARMul_NewState ();
114 state
->bigendSig
= (CURRENT_TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? HIGH
: LOW
);
115 ARMul_MemoryInit (state
, mem_size
);
116 ARMul_OSInit (state
);
123 ARMul_ConsolePrint (ARMul_State
* state
,
131 va_start (ap
, format
);
132 vprintf (format
, ap
);
138 sim_write (SIM_DESC sd ATTRIBUTE_UNUSED
,
140 const unsigned char * buffer
,
147 for (i
= 0; i
< size
; i
++)
148 ARMul_SafeWriteByte (state
, addr
+ i
, buffer
[i
]);
154 sim_read (SIM_DESC sd ATTRIBUTE_UNUSED
,
156 unsigned char * buffer
,
163 for (i
= 0; i
< size
; i
++)
164 buffer
[i
] = ARMul_SafeReadByte (state
, addr
+ i
);
170 sim_stop (SIM_DESC sd ATTRIBUTE_UNUSED
)
172 state
->Emulate
= STOP
;
178 sim_resume (SIM_DESC sd ATTRIBUTE_UNUSED
,
180 int siggnal ATTRIBUTE_UNUSED
)
182 state
->EndCondition
= 0;
187 state
->Reg
[15] = ARMul_DoInstr (state
);
188 if (state
->EndCondition
== 0)
189 state
->EndCondition
= RDIError_BreakpointReached
;
193 state
->NextInstr
= RESUME
; /* treat as PC change */
194 state
->Reg
[15] = ARMul_DoProg (state
);
201 sim_create_inferior (SIM_DESC sd ATTRIBUTE_UNUSED
,
214 ARMul_SetPC (state
, bfd_get_start_address (abfd
));
215 mach
= bfd_get_mach (abfd
);
219 ARMul_SetPC (state
, 0); /* ??? */
224 if (abfd
!= NULL
&& (bfd_get_start_address (abfd
) & 1))
231 (*sim_callback
->printf_filtered
)
233 "Unknown machine type '%d'; please update sim_create_inferior.\n",
238 /* We wouldn't set the machine type with earlier toolchains, so we
239 explicitly select a processor capable of supporting all ARMs in
241 ARMul_SelectProcessor (state
, ARM_v5_Prop
| ARM_v5e_Prop
| ARM_v6_Prop
);
244 case bfd_mach_arm_XScale
:
245 ARMul_SelectProcessor (state
, ARM_v5_Prop
| ARM_v5e_Prop
| ARM_XScale_Prop
| ARM_v6_Prop
);
248 case bfd_mach_arm_iWMMXt2
:
249 case bfd_mach_arm_iWMMXt
:
251 extern int SWI_vector_installed
;
254 if (! SWI_vector_installed
)
256 /* Intialise the hardware vectors to zero. */
257 if (! SWI_vector_installed
)
258 for (i
= ARMul_ResetV
; i
<= ARMFIQV
; i
+= 4)
259 ARMul_WriteWord (state
, i
, 0);
261 /* ARM_WriteWord will have detected the write to the SWI vector,
262 but we want SWI_vector_installed to remain at 0 so that thumb
263 mode breakpoints will work. */
264 SWI_vector_installed
= 0;
267 ARMul_SelectProcessor (state
, ARM_v5_Prop
| ARM_v5e_Prop
| ARM_XScale_Prop
| ARM_iWMMXt_Prop
);
270 case bfd_mach_arm_ep9312
:
271 ARMul_SelectProcessor (state
, ARM_v4_Prop
| ARM_ep9312_Prop
);
275 if (bfd_family_coff (abfd
))
277 /* This is a special case in order to support COFF based ARM toolchains.
278 The COFF header does not have enough room to store all the different
279 kinds of ARM cpu, so the XScale, v5T and v5TE architectures all default
280 to v5. (See coff_set_flags() in bdf/coffcode.h). So if we see a v5
281 machine type here, we assume it could be any of the above architectures
282 and so select the most feature-full. */
283 ARMul_SelectProcessor (state
, ARM_v5_Prop
| ARM_v5e_Prop
| ARM_XScale_Prop
);
286 /* Otherwise drop through. */
288 case bfd_mach_arm_5T
:
289 ARMul_SelectProcessor (state
, ARM_v5_Prop
);
292 case bfd_mach_arm_5TE
:
293 ARMul_SelectProcessor (state
, ARM_v5_Prop
| ARM_v5e_Prop
);
297 case bfd_mach_arm_4T
:
298 ARMul_SelectProcessor (state
, ARM_v4_Prop
);
302 case bfd_mach_arm_3M
:
303 ARMul_SelectProcessor (state
, ARM_Lock_Prop
);
307 case bfd_mach_arm_2a
:
308 ARMul_SelectProcessor (state
, ARM_Fix26_Prop
);
312 memset (& info
, 0, sizeof (info
));
313 INIT_DISASSEMBLE_INFO (info
, stdout
, op_printf
);
314 info
.read_memory_func
= sim_dis_read
;
315 info
.arch
= bfd_get_arch (abfd
);
316 info
.mach
= bfd_get_mach (abfd
);
317 info
.endian_code
= BFD_ENDIAN_LITTLE
;
319 info
.arch
= bfd_arch_arm
;
320 disassemble_init_for_target (& info
);
324 /* Set up the command line by laboriously stringing together
325 the environment carefully picked apart by our caller. */
327 /* Free any old stuff. */
328 if (state
->CommandLine
!= NULL
)
330 free (state
->CommandLine
);
331 state
->CommandLine
= NULL
;
334 /* See how much we need. */
335 for (arg
= argv
; *arg
!= NULL
; arg
++)
336 argvlen
+= strlen (*arg
) + 1;
339 state
->CommandLine
= malloc (argvlen
+ 1);
340 if (state
->CommandLine
!= NULL
)
343 state
->CommandLine
[0] = '\0';
345 for (arg
= argv
; *arg
!= NULL
; arg
++)
347 strcat (state
->CommandLine
, *arg
);
348 strcat (state
->CommandLine
, " ");
355 /* Now see if there's a MEMSIZE spec in the environment. */
358 if (strncmp (*env
, "MEMSIZE=", sizeof ("MEMSIZE=") - 1) == 0)
362 /* Set up memory limit. */
364 strtoul (*env
+ sizeof ("MEMSIZE=") - 1, &end_of_num
, 0);
374 frommem (struct ARMul_State
*state
, unsigned char *memory
)
376 if (state
->bigendSig
== HIGH
)
377 return (memory
[0] << 24) | (memory
[1] << 16)
378 | (memory
[2] << 8) | (memory
[3] << 0);
380 return (memory
[3] << 24) | (memory
[2] << 16)
381 | (memory
[1] << 8) | (memory
[0] << 0);
385 tomem (struct ARMul_State
*state
,
386 unsigned char *memory
,
389 if (state
->bigendSig
== HIGH
)
391 memory
[0] = val
>> 24;
392 memory
[1] = val
>> 16;
393 memory
[2] = val
>> 8;
394 memory
[3] = val
>> 0;
398 memory
[3] = val
>> 24;
399 memory
[2] = val
>> 16;
400 memory
[1] = val
>> 8;
401 memory
[0] = val
>> 0;
406 arm_reg_store (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
410 switch ((enum sim_arm_regs
) rn
)
412 case SIM_ARM_R0_REGNUM
:
413 case SIM_ARM_R1_REGNUM
:
414 case SIM_ARM_R2_REGNUM
:
415 case SIM_ARM_R3_REGNUM
:
416 case SIM_ARM_R4_REGNUM
:
417 case SIM_ARM_R5_REGNUM
:
418 case SIM_ARM_R6_REGNUM
:
419 case SIM_ARM_R7_REGNUM
:
420 case SIM_ARM_R8_REGNUM
:
421 case SIM_ARM_R9_REGNUM
:
422 case SIM_ARM_R10_REGNUM
:
423 case SIM_ARM_R11_REGNUM
:
424 case SIM_ARM_R12_REGNUM
:
425 case SIM_ARM_R13_REGNUM
:
426 case SIM_ARM_R14_REGNUM
:
427 case SIM_ARM_R15_REGNUM
: /* PC */
428 case SIM_ARM_FP0_REGNUM
:
429 case SIM_ARM_FP1_REGNUM
:
430 case SIM_ARM_FP2_REGNUM
:
431 case SIM_ARM_FP3_REGNUM
:
432 case SIM_ARM_FP4_REGNUM
:
433 case SIM_ARM_FP5_REGNUM
:
434 case SIM_ARM_FP6_REGNUM
:
435 case SIM_ARM_FP7_REGNUM
:
436 case SIM_ARM_FPS_REGNUM
:
437 ARMul_SetReg (state
, state
->Mode
, rn
, frommem (state
, memory
));
440 case SIM_ARM_PS_REGNUM
:
441 state
->Cpsr
= frommem (state
, memory
);
442 ARMul_CPSRAltered (state
);
445 case SIM_ARM_MAVERIC_COP0R0_REGNUM
:
446 case SIM_ARM_MAVERIC_COP0R1_REGNUM
:
447 case SIM_ARM_MAVERIC_COP0R2_REGNUM
:
448 case SIM_ARM_MAVERIC_COP0R3_REGNUM
:
449 case SIM_ARM_MAVERIC_COP0R4_REGNUM
:
450 case SIM_ARM_MAVERIC_COP0R5_REGNUM
:
451 case SIM_ARM_MAVERIC_COP0R6_REGNUM
:
452 case SIM_ARM_MAVERIC_COP0R7_REGNUM
:
453 case SIM_ARM_MAVERIC_COP0R8_REGNUM
:
454 case SIM_ARM_MAVERIC_COP0R9_REGNUM
:
455 case SIM_ARM_MAVERIC_COP0R10_REGNUM
:
456 case SIM_ARM_MAVERIC_COP0R11_REGNUM
:
457 case SIM_ARM_MAVERIC_COP0R12_REGNUM
:
458 case SIM_ARM_MAVERIC_COP0R13_REGNUM
:
459 case SIM_ARM_MAVERIC_COP0R14_REGNUM
:
460 case SIM_ARM_MAVERIC_COP0R15_REGNUM
:
461 memcpy (& DSPregs
[rn
- SIM_ARM_MAVERIC_COP0R0_REGNUM
],
462 memory
, sizeof (struct maverick_regs
));
463 return sizeof (struct maverick_regs
);
465 case SIM_ARM_MAVERIC_DSPSC_REGNUM
:
466 memcpy (&DSPsc
, memory
, sizeof DSPsc
);
469 case SIM_ARM_IWMMXT_COP0R0_REGNUM
:
470 case SIM_ARM_IWMMXT_COP0R1_REGNUM
:
471 case SIM_ARM_IWMMXT_COP0R2_REGNUM
:
472 case SIM_ARM_IWMMXT_COP0R3_REGNUM
:
473 case SIM_ARM_IWMMXT_COP0R4_REGNUM
:
474 case SIM_ARM_IWMMXT_COP0R5_REGNUM
:
475 case SIM_ARM_IWMMXT_COP0R6_REGNUM
:
476 case SIM_ARM_IWMMXT_COP0R7_REGNUM
:
477 case SIM_ARM_IWMMXT_COP0R8_REGNUM
:
478 case SIM_ARM_IWMMXT_COP0R9_REGNUM
:
479 case SIM_ARM_IWMMXT_COP0R10_REGNUM
:
480 case SIM_ARM_IWMMXT_COP0R11_REGNUM
:
481 case SIM_ARM_IWMMXT_COP0R12_REGNUM
:
482 case SIM_ARM_IWMMXT_COP0R13_REGNUM
:
483 case SIM_ARM_IWMMXT_COP0R14_REGNUM
:
484 case SIM_ARM_IWMMXT_COP0R15_REGNUM
:
485 case SIM_ARM_IWMMXT_COP1R0_REGNUM
:
486 case SIM_ARM_IWMMXT_COP1R1_REGNUM
:
487 case SIM_ARM_IWMMXT_COP1R2_REGNUM
:
488 case SIM_ARM_IWMMXT_COP1R3_REGNUM
:
489 case SIM_ARM_IWMMXT_COP1R4_REGNUM
:
490 case SIM_ARM_IWMMXT_COP1R5_REGNUM
:
491 case SIM_ARM_IWMMXT_COP1R6_REGNUM
:
492 case SIM_ARM_IWMMXT_COP1R7_REGNUM
:
493 case SIM_ARM_IWMMXT_COP1R8_REGNUM
:
494 case SIM_ARM_IWMMXT_COP1R9_REGNUM
:
495 case SIM_ARM_IWMMXT_COP1R10_REGNUM
:
496 case SIM_ARM_IWMMXT_COP1R11_REGNUM
:
497 case SIM_ARM_IWMMXT_COP1R12_REGNUM
:
498 case SIM_ARM_IWMMXT_COP1R13_REGNUM
:
499 case SIM_ARM_IWMMXT_COP1R14_REGNUM
:
500 case SIM_ARM_IWMMXT_COP1R15_REGNUM
:
501 return Store_Iwmmxt_Register (rn
- SIM_ARM_IWMMXT_COP0R0_REGNUM
, memory
);
511 arm_reg_fetch (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
518 switch ((enum sim_arm_regs
) rn
)
520 case SIM_ARM_R0_REGNUM
:
521 case SIM_ARM_R1_REGNUM
:
522 case SIM_ARM_R2_REGNUM
:
523 case SIM_ARM_R3_REGNUM
:
524 case SIM_ARM_R4_REGNUM
:
525 case SIM_ARM_R5_REGNUM
:
526 case SIM_ARM_R6_REGNUM
:
527 case SIM_ARM_R7_REGNUM
:
528 case SIM_ARM_R8_REGNUM
:
529 case SIM_ARM_R9_REGNUM
:
530 case SIM_ARM_R10_REGNUM
:
531 case SIM_ARM_R11_REGNUM
:
532 case SIM_ARM_R12_REGNUM
:
533 case SIM_ARM_R13_REGNUM
:
534 case SIM_ARM_R14_REGNUM
:
535 case SIM_ARM_R15_REGNUM
: /* PC */
536 regval
= ARMul_GetReg (state
, state
->Mode
, rn
);
539 case SIM_ARM_FP0_REGNUM
:
540 case SIM_ARM_FP1_REGNUM
:
541 case SIM_ARM_FP2_REGNUM
:
542 case SIM_ARM_FP3_REGNUM
:
543 case SIM_ARM_FP4_REGNUM
:
544 case SIM_ARM_FP5_REGNUM
:
545 case SIM_ARM_FP6_REGNUM
:
546 case SIM_ARM_FP7_REGNUM
:
547 case SIM_ARM_FPS_REGNUM
:
548 memset (memory
, 0, length
);
551 case SIM_ARM_PS_REGNUM
:
552 regval
= ARMul_GetCPSR (state
);
555 case SIM_ARM_MAVERIC_COP0R0_REGNUM
:
556 case SIM_ARM_MAVERIC_COP0R1_REGNUM
:
557 case SIM_ARM_MAVERIC_COP0R2_REGNUM
:
558 case SIM_ARM_MAVERIC_COP0R3_REGNUM
:
559 case SIM_ARM_MAVERIC_COP0R4_REGNUM
:
560 case SIM_ARM_MAVERIC_COP0R5_REGNUM
:
561 case SIM_ARM_MAVERIC_COP0R6_REGNUM
:
562 case SIM_ARM_MAVERIC_COP0R7_REGNUM
:
563 case SIM_ARM_MAVERIC_COP0R8_REGNUM
:
564 case SIM_ARM_MAVERIC_COP0R9_REGNUM
:
565 case SIM_ARM_MAVERIC_COP0R10_REGNUM
:
566 case SIM_ARM_MAVERIC_COP0R11_REGNUM
:
567 case SIM_ARM_MAVERIC_COP0R12_REGNUM
:
568 case SIM_ARM_MAVERIC_COP0R13_REGNUM
:
569 case SIM_ARM_MAVERIC_COP0R14_REGNUM
:
570 case SIM_ARM_MAVERIC_COP0R15_REGNUM
:
571 memcpy (memory
, & DSPregs
[rn
- SIM_ARM_MAVERIC_COP0R0_REGNUM
],
572 sizeof (struct maverick_regs
));
573 return sizeof (struct maverick_regs
);
575 case SIM_ARM_MAVERIC_DSPSC_REGNUM
:
576 memcpy (memory
, & DSPsc
, sizeof DSPsc
);
579 case SIM_ARM_IWMMXT_COP0R0_REGNUM
:
580 case SIM_ARM_IWMMXT_COP0R1_REGNUM
:
581 case SIM_ARM_IWMMXT_COP0R2_REGNUM
:
582 case SIM_ARM_IWMMXT_COP0R3_REGNUM
:
583 case SIM_ARM_IWMMXT_COP0R4_REGNUM
:
584 case SIM_ARM_IWMMXT_COP0R5_REGNUM
:
585 case SIM_ARM_IWMMXT_COP0R6_REGNUM
:
586 case SIM_ARM_IWMMXT_COP0R7_REGNUM
:
587 case SIM_ARM_IWMMXT_COP0R8_REGNUM
:
588 case SIM_ARM_IWMMXT_COP0R9_REGNUM
:
589 case SIM_ARM_IWMMXT_COP0R10_REGNUM
:
590 case SIM_ARM_IWMMXT_COP0R11_REGNUM
:
591 case SIM_ARM_IWMMXT_COP0R12_REGNUM
:
592 case SIM_ARM_IWMMXT_COP0R13_REGNUM
:
593 case SIM_ARM_IWMMXT_COP0R14_REGNUM
:
594 case SIM_ARM_IWMMXT_COP0R15_REGNUM
:
595 case SIM_ARM_IWMMXT_COP1R0_REGNUM
:
596 case SIM_ARM_IWMMXT_COP1R1_REGNUM
:
597 case SIM_ARM_IWMMXT_COP1R2_REGNUM
:
598 case SIM_ARM_IWMMXT_COP1R3_REGNUM
:
599 case SIM_ARM_IWMMXT_COP1R4_REGNUM
:
600 case SIM_ARM_IWMMXT_COP1R5_REGNUM
:
601 case SIM_ARM_IWMMXT_COP1R6_REGNUM
:
602 case SIM_ARM_IWMMXT_COP1R7_REGNUM
:
603 case SIM_ARM_IWMMXT_COP1R8_REGNUM
:
604 case SIM_ARM_IWMMXT_COP1R9_REGNUM
:
605 case SIM_ARM_IWMMXT_COP1R10_REGNUM
:
606 case SIM_ARM_IWMMXT_COP1R11_REGNUM
:
607 case SIM_ARM_IWMMXT_COP1R12_REGNUM
:
608 case SIM_ARM_IWMMXT_COP1R13_REGNUM
:
609 case SIM_ARM_IWMMXT_COP1R14_REGNUM
:
610 case SIM_ARM_IWMMXT_COP1R15_REGNUM
:
611 return Fetch_Iwmmxt_Register (rn
- SIM_ARM_IWMMXT_COP0R0_REGNUM
, memory
);
619 tomem (state
, memory
, regval
);
632 unsigned int swi_mask
;
635 #define SWI_SWITCH "--swi-support"
637 static swi_options options
[] =
640 { "demon", SWI_MASK_DEMON
},
641 { "angel", SWI_MASK_ANGEL
},
642 { "redboot", SWI_MASK_REDBOOT
},
645 { "DEMON", SWI_MASK_DEMON
},
646 { "ANGEL", SWI_MASK_ANGEL
},
647 { "REDBOOT", SWI_MASK_REDBOOT
},
653 sim_target_parse_command_line (int argc
, char ** argv
)
657 for (i
= 1; i
< argc
; i
++)
659 char * ptr
= argv
[i
];
662 if ((ptr
== NULL
) || (* ptr
!= '-'))
665 if (strcmp (ptr
, "-t") == 0)
671 if (strcmp (ptr
, "-z") == 0)
673 /* Remove this option from the argv array. */
674 for (arg
= i
; arg
< argc
; arg
++)
675 argv
[arg
] = argv
[arg
+ 1];
682 if (strcmp (ptr
, "-d") == 0)
684 /* Remove this option from the argv array. */
685 for (arg
= i
; arg
< argc
; arg
++)
686 argv
[arg
] = argv
[arg
+ 1];
693 if (strncmp (ptr
, SWI_SWITCH
, sizeof SWI_SWITCH
- 1) != 0)
696 if (ptr
[sizeof SWI_SWITCH
- 1] == 0)
698 /* Remove this option from the argv array. */
699 for (arg
= i
; arg
< argc
; arg
++)
700 argv
[arg
] = argv
[arg
+ 1];
706 ptr
+= sizeof SWI_SWITCH
;
714 for (i
= ARRAY_SIZE (options
); i
--;)
715 if (strncmp (ptr
, options
[i
].swi_option
,
716 strlen (options
[i
].swi_option
)) == 0)
718 swi_mask
|= options
[i
].swi_mask
;
719 ptr
+= strlen (options
[i
].swi_option
);
732 fprintf (stderr
, "Ignoring swi options: %s\n", ptr
);
734 /* Remove this option from the argv array. */
735 for (arg
= i
; arg
< argc
; arg
++)
736 argv
[arg
] = argv
[arg
+ 1];
744 sim_target_parse_arg_array (char ** argv
)
746 sim_target_parse_command_line (countargv (argv
), argv
);
750 arm_pc_get (sim_cpu
*cpu
)
756 arm_pc_set (sim_cpu
*cpu
, sim_cia pc
)
758 ARMul_SetPC (state
, pc
);
762 free_state (SIM_DESC sd
)
764 if (STATE_MODULES (sd
) != NULL
)
765 sim_module_uninstall (sd
);
766 sim_cpu_free_all (sd
);
771 sim_open (SIM_OPEN_KIND kind
,
777 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
778 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
780 /* The cpu data is kept in a separately allocated chunk of memory. */
781 if (sim_cpu_alloc_all (sd
, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK
)
787 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
793 /* The parser will print an error message for us, so we silently return. */
794 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
800 /* Check for/establish the a reference program image. */
801 if (sim_analyze_program (sd
,
802 (STATE_PROG_ARGV (sd
) != NULL
803 ? *STATE_PROG_ARGV (sd
)
804 : NULL
), abfd
) != SIM_RC_OK
)
810 /* Configure/verify the target byte order and other runtime
811 configuration options. */
812 if (sim_config (sd
) != SIM_RC_OK
)
814 sim_module_uninstall (sd
);
818 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
820 /* Uninstall the modules to avoid memory leaks,
821 file descriptor leaks, etc. */
822 sim_module_uninstall (sd
);
826 /* CPU specific initialization. */
827 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
829 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
831 CPU_REG_FETCH (cpu
) = arm_reg_fetch
;
832 CPU_REG_STORE (cpu
) = arm_reg_store
;
833 CPU_PC_FETCH (cpu
) = arm_pc_get
;
834 CPU_PC_STORE (cpu
) = arm_pc_set
;
839 sim_target_parse_arg_array (argv
);
845 /* Scan for memory-size switches. */
846 for (i
= 0; (argv
[i
] != NULL
) && (argv
[i
][0] != 0); i
++)
847 if (argv
[i
][0] == '-' && argv
[i
][1] == 'm')
849 if (argv
[i
][2] != '\0')
850 mem_size
= atoi (&argv
[i
][2]);
851 else if (argv
[i
+ 1] != NULL
)
853 mem_size
= atoi (argv
[i
+ 1]);
858 sim_callback
->printf_filtered (sim_callback
,
859 "Missing argument to -m option\n");
869 sim_stop_reason (SIM_DESC sd ATTRIBUTE_UNUSED
,
870 enum sim_stop
*reason
,
875 *reason
= sim_stopped
;
876 *sigrc
= GDB_SIGNAL_INT
;
878 else if (state
->EndCondition
== 0)
880 *reason
= sim_exited
;
881 *sigrc
= state
->Reg
[0] & 255;
885 *reason
= sim_stopped
;
886 if (state
->EndCondition
== RDIError_BreakpointReached
)
887 *sigrc
= GDB_SIGNAL_TRAP
;
888 else if ( state
->EndCondition
== RDIError_DataAbort
889 || state
->EndCondition
== RDIError_AddressException
)
890 *sigrc
= GDB_SIGNAL_BUS
;