sim/avr/interp.c

   1 /* Simulator for Atmel's AVR core.
   2    Copyright (C) 2009-2015 Free Software Foundation, Inc.
   3    Written by Tristan Gingold, AdaCore.
   4
   5    This file is part of GDB, the GNU debugger.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #include "config.h"
  21
  22 #ifdef HAVE_STRING_H
  23 #include <string.h>
  24 #endif
  25 #include "bfd.h"
  26 #include "libiberty.h"
  27 #include "gdb/remote-sim.h"
  28
  29 #include "sim-main.h"
  30 #include "sim-base.h"
  31 #include "sim-options.h"
  32
  33 /* As AVR is a 8/16 bits processor, define handy types.  */
  34 typedef unsigned short int word;
  35 typedef signed short int sword;
  36 typedef unsigned char byte;
  37 typedef signed char sbyte;
  38
  39 /* The only real register.  */
  40 unsigned int pc;
  41
  42 /* We update a cycle counter.  */
  43 static unsigned int cycles = 0;
  44
  45 /* If true, the pc needs more than 2 bytes.  */
  46 static int avr_pc22;
  47
  48 /* Max size of I space (which is always flash on avr).  */
  49 #define MAX_AVR_FLASH (128 * 1024)
  50 #define PC_MASK (MAX_AVR_FLASH - 1)
  51
  52 /* Mac size of D space.  */
  53 #define MAX_AVR_SRAM (64 * 1024)
  54 #define SRAM_MASK (MAX_AVR_SRAM - 1)
  55
  56 /* D space offset in ELF file.  */
  57 #define SRAM_VADDR 0x800000
  58
  59 /* Simulator specific ports.  */
  60 #define STDIO_PORT      0x52
  61 #define EXIT_PORT       0x4F
  62 #define ABORT_PORT      0x49
  63
  64 /* GDB defined register numbers.  */
  65 #define AVR_SREG_REGNUM  32
  66 #define AVR_SP_REGNUM    33
  67 #define AVR_PC_REGNUM    34
  68
  69 /* Memory mapped registers.  */
  70 #define SREG    0x5F
  71 #define REG_SP  0x5D
  72 #define EIND    0x5C
  73 #define RAMPZ   0x5B
  74
  75 #define REGX 0x1a
  76 #define REGY 0x1c
  77 #define REGZ 0x1e
  78 #define REGZ_LO 0x1e
  79 #define REGZ_HI 0x1f
  80
  81 /* Sreg (status) bits.  */
  82 #define SREG_I 0x80
  83 #define SREG_T 0x40
  84 #define SREG_H 0x20
  85 #define SREG_S 0x10
  86 #define SREG_V 0x08
  87 #define SREG_N 0x04
  88 #define SREG_Z 0x02
  89 #define SREG_C 0x01
  90
  91 /* In order to speed up emulation we use a simple approach:
  92    a code is associated with each instruction.  The pre-decoding occurs
  93    usually once when the instruction is first seen.
  94    This works well because I&D spaces are separated.
  95
  96    Missing opcodes: sleep, spm, wdr (as they are mmcu dependent).
  97 */
  98 enum avr_opcode
  99   {
 100     /* Opcode not yet decoded.  */
 101     OP_unknown,
 102     OP_bad,
 103
 104     OP_nop,
 105
 106     OP_rjmp,
 107     OP_rcall,
 108     OP_ret,
 109     OP_reti,
 110
 111     OP_break,
 112
 113     OP_brbs,
 114     OP_brbc,
 115
 116     OP_bset,
 117     OP_bclr,
 118
 119     OP_bld,
 120     OP_bst,
 121
 122     OP_sbrc,
 123     OP_sbrs,
 124
 125     OP_eor,
 126     OP_and,
 127     OP_andi,
 128     OP_or,
 129     OP_ori,
 130     OP_com,
 131     OP_swap,
 132     OP_neg,
 133
 134     OP_out,
 135     OP_in,
 136     OP_cbi,
 137     OP_sbi,
 138
 139     OP_sbic,
 140     OP_sbis,
 141
 142     OP_ldi,
 143     OP_cpse,
 144     OP_cp,
 145     OP_cpi,
 146     OP_cpc,
 147     OP_sub,
 148     OP_sbc,
 149     OP_sbiw,
 150     OP_adiw,
 151     OP_add,
 152     OP_adc,
 153     OP_subi,
 154     OP_sbci,
 155     OP_inc,
 156     OP_dec,
 157     OP_lsr,
 158     OP_ror,
 159     OP_asr,
 160
 161     OP_mul,
 162     OP_muls,
 163     OP_mulsu,
 164     OP_fmul,
 165     OP_fmuls,
 166     OP_fmulsu,
 167
 168     OP_mov,
 169     OP_movw,
 170
 171     OP_push,
 172     OP_pop,
 173
 174     OP_st_X,
 175     OP_st_dec_X,
 176     OP_st_X_inc,
 177     OP_st_Y_inc,
 178     OP_st_dec_Y,
 179     OP_st_Z_inc,
 180     OP_st_dec_Z,
 181     OP_std_Y,
 182     OP_std_Z,
 183     OP_ldd_Y,
 184     OP_ldd_Z,
 185     OP_ld_Z_inc,
 186     OP_ld_dec_Z,
 187     OP_ld_Y_inc,
 188     OP_ld_dec_Y,
 189     OP_ld_X,
 190     OP_ld_X_inc,
 191     OP_ld_dec_X,
 192
 193     OP_lpm,
 194     OP_lpm_Z,
 195     OP_lpm_inc_Z,
 196     OP_elpm,
 197     OP_elpm_Z,
 198     OP_elpm_inc_Z,
 199
 200     OP_ijmp,
 201     OP_icall,
 202
 203     OP_eijmp,
 204     OP_eicall,
 205
 206     /* 2 words opcodes.  */
 207 #define OP_2words OP_jmp
 208     OP_jmp,
 209     OP_call,
 210     OP_sts,
 211     OP_lds
 212   };
 213
 214 struct avr_insn_cell
 215 {
 216   /* The insn (16 bits).  */
 217   word op;
 218
 219   /* Pre-decoding code.  */
 220   enum avr_opcode code : 8;
 221   /* One byte of additional information.  */
 222   byte r;
 223 };
 224
 225 /* I&D memories.  */
 226 /* TODO: Should be moved to SIM_CPU.  */
 227 static struct avr_insn_cell flash[MAX_AVR_FLASH];
 228 static byte sram[MAX_AVR_SRAM];
 229
 230 /* Sign extend a value.  */
 231 static int sign_ext (word val, int nb_bits)
 232 {
 233   if (val & (1 << (nb_bits - 1)))
 234     return val | (-1 << nb_bits);
 235   return val;
 236 }
 237
 238 /* Insn field extractors.  */
 239
 240 /* Extract xxxx_xxxRx_xxxx_RRRR.  */
 241 static inline byte get_r (word op)
 242 {
 243   return (op & 0xf) | ((op >> 5) & 0x10);
 244 }
 245
 246 /* Extract xxxx_xxxxx_xxxx_RRRR.  */
 247 static inline byte get_r16 (word op)
 248 {
 249   return 16 + (op & 0xf);
 250 }
 251
 252 /* Extract xxxx_xxxxx_xxxx_xRRR.  */
 253 static inline byte get_r16_23 (word op)
 254 {
 255   return 16 + (op & 0x7);
 256 }
 257
 258 /* Extract xxxx_xxxD_DDDD_xxxx.  */
 259 static inline byte get_d (word op)
 260 {
 261   return (op >> 4) & 0x1f;
 262 }
 263
 264 /* Extract xxxx_xxxx_DDDD_xxxx.  */
 265 static inline byte get_d16 (word op)
 266 {
 267   return 16 + ((op >> 4) & 0x0f);
 268 }
 269
 270 /* Extract xxxx_xxxx_xDDD_xxxx.  */
 271 static inline byte get_d16_23 (word op)
 272 {
 273   return 16 + ((op >> 4) & 0x07);
 274 }
 275
 276 /* Extract xxxx_xAAx_xxxx_AAAA.  */
 277 static inline byte get_A (word op)
 278 {
 279   return (op & 0x0f) | ((op & 0x600) >> 5);
 280 }
 281
 282 /* Extract xxxx_xxxx_AAAA_Axxx.  */
 283 static inline byte get_biA (word op)
 284 {
 285   return (op >> 3) & 0x1f;
 286 }
 287
 288 /* Extract xxxx_KKKK_xxxx_KKKK.  */
 289 static inline byte get_K (word op)
 290 {
 291   return (op & 0xf) | ((op & 0xf00) >> 4);
 292 }
 293
 294 /* Extract xxxx_xxKK_KKKK_Kxxx.  */
 295 static inline int get_k (word op)
 296 {
 297   return sign_ext ((op & 0x3f8) >> 3, 7);
 298 }
 299
 300 /* Extract xxxx_xxxx_xxDD_xxxx.  */
 301 static inline byte get_d24 (word op)
 302 {
 303   return 24 + ((op >> 3) & 6);
 304 }
 305
 306 /* Extract xxxx_xxxx_KKxx_KKKK.  */
 307 static inline byte get_k6 (word op)
 308 {
 309   return (op & 0xf) | ((op >> 2) & 0x30);
 310 }
 311
 312 /* Extract xxQx_QQxx_xxxx_xQQQ.  */
 313 static inline byte get_q (word op)
 314 {
 315   return (op & 7) | ((op >> 7) & 0x18)| ((op >> 8) & 0x20);
 316 }
 317
 318 /* Extract xxxx_xxxx_xxxx_xBBB.  */
 319 static inline byte get_b (word op)
 320 {
 321   return (op & 7);
 322 }
 323
 324 /* AVR is little endian.  */
 325 static inline word
 326 read_word (unsigned int addr)
 327 {
 328   return sram[addr] | (sram[addr + 1] << 8);
 329 }
 330
 331 static inline void
 332 write_word (unsigned int addr, word w)
 333 {
 334   sram[addr] = w;
 335   sram[addr + 1] = w >> 8;
 336 }
 337
 338 static inline word
 339 read_word_post_inc (unsigned int addr)
 340 {
 341   word v = read_word (addr);
 342   write_word (addr, v + 1);
 343   return v;
 344 }
 345
 346 static inline word
 347 read_word_pre_dec (unsigned int addr)
 348 {
 349   word v = read_word (addr) - 1;
 350   write_word (addr, v);
 351   return v;
 352 }
 353
 354 static void
 355 update_flags_logic (byte res)
 356 {
 357   sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z);
 358   if (res == 0)
 359     sram[SREG] |= SREG_Z;
 360   if (res & 0x80)
 361     sram[SREG] |= SREG_N | SREG_S;
 362 }
 363
 364 static void
 365 update_flags_add (byte r, byte a, byte b)
 366 {
 367   byte carry;
 368
 369   sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
 370   if (r & 0x80)
 371     sram[SREG] |= SREG_N;
 372   carry = (a & b) | (a & ~r) | (b & ~r);
 373   if (carry & 0x08)
 374     sram[SREG] |= SREG_H;
 375   if (carry & 0x80)
 376     sram[SREG] |= SREG_C;
 377   if (((a & b & ~r) | (~a & ~b & r)) & 0x80)
 378     sram[SREG] |= SREG_V;
 379   if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_V))
 380     sram[SREG] |= SREG_S;
 381   if (r == 0)
 382     sram[SREG] |= SREG_Z;
 383 }
 384
 385 static void update_flags_sub (byte r, byte a, byte b)
 386 {
 387   byte carry;
 388
 389   sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
 390   if (r & 0x80)
 391     sram[SREG] |= SREG_N;
 392   carry = (~a & b) | (b & r) | (r & ~a);
 393   if (carry & 0x08)
 394     sram[SREG] |= SREG_H;
 395   if (carry & 0x80)
 396     sram[SREG] |= SREG_C;
 397   if (((a & ~b & ~r) | (~a & b & r)) & 0x80)
 398     sram[SREG] |= SREG_V;
 399   if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_V))
 400     sram[SREG] |= SREG_S;
 401   /* Note: Z is not set.  */
 402 }
 403
 404 static enum avr_opcode
 405 decode (unsigned int pc)
 406 {
 407   word op1 = flash[pc].op;
 408
 409   switch ((op1 >> 12) & 0x0f)
 410     {
 411     case 0x0:
 412       switch ((op1 >> 10) & 0x3)
 413         {
 414         case 0x0:
 415           switch ((op1 >> 8) & 0x3)
 416             {
 417             case 0x0:
 418               if (op1 == 0)
 419                 return OP_nop;
 420               break;
 421             case 0x1:
 422               return OP_movw;
 423             case 0x2:
 424               return OP_muls;
 425             case 0x3:
 426               if (op1 & 0x80)
 427                 {
 428                   if (op1 & 0x08)
 429                     return OP_fmulsu;
 430                   else
 431                     return OP_fmuls;
 432                 }
 433               else
 434                 {
 435                   if (op1 & 0x08)
 436                     return OP_fmul;
 437                   else
 438                     return OP_mulsu;
 439                 }
 440             }
 441           break;
 442         case 0x1:
 443           return OP_cpc;
 444         case 0x2:
 445           flash[pc].r = SREG_C;
 446           return OP_sbc;
 447         case 0x3:
 448           flash[pc].r = 0;
 449           return OP_add;
 450         }
 451       break;
 452     case 0x1:
 453       switch ((op1 >> 10) & 0x3)
 454         {
 455         case 0x0:
 456           return OP_cpse;
 457         case 0x1:
 458           return OP_cp;
 459         case 0x2:
 460           flash[pc].r = 0;
 461           return OP_sub;
 462         case 0x3:
 463           flash[pc].r = SREG_C;
 464           return OP_adc;
 465         }
 466       break;
 467     case 0x2:
 468       switch ((op1 >> 10) & 0x3)
 469         {
 470         case 0x0:
 471           return OP_and;
 472         case 0x1:
 473           return OP_eor;
 474         case 0x2:
 475           return OP_or;
 476         case 0x3:
 477           return OP_mov;
 478         }
 479       break;
 480     case 0x3:
 481       return OP_cpi;
 482     case 0x4:
 483       return OP_sbci;
 484     case 0x5:
 485       return OP_subi;
 486     case 0x6:
 487       return OP_ori;
 488     case 0x7:
 489       return OP_andi;
 490     case 0x8:
 491     case 0xa:
 492       if (op1 & 0x0200)
 493         {
 494           if (op1 & 0x0008)
 495             {
 496               flash[pc].r = get_q (op1);
 497               return OP_std_Y;
 498             }
 499           else
 500             {
 501               flash[pc].r = get_q (op1);
 502               return OP_std_Z;
 503             }
 504         }
 505       else
 506         {
 507           if (op1 & 0x0008)
 508             {
 509               flash[pc].r = get_q (op1);
 510               return OP_ldd_Y;
 511             }
 512           else
 513             {
 514               flash[pc].r = get_q (op1);
 515               return OP_ldd_Z;
 516             }
 517         }
 518       break;
 519     case 0x9: /* 9xxx */
 520       switch ((op1 >> 8) & 0xf)
 521         {
 522         case 0x0:
 523         case 0x1:
 524           switch ((op1 >> 0) & 0xf)
 525             {
 526             case 0x0:
 527               return OP_lds;
 528             case 0x1:
 529               return OP_ld_Z_inc;
 530             case 0x2:
 531               return OP_ld_dec_Z;
 532             case 0x4:
 533               return OP_lpm_Z;
 534             case 0x5:
 535               return OP_lpm_inc_Z;
 536             case 0x6:
 537               return OP_elpm_Z;
 538             case 0x7:
 539               return OP_elpm_inc_Z;
 540             case 0x9:
 541               return OP_ld_Y_inc;
 542             case 0xa:
 543               return OP_ld_dec_Y;
 544             case 0xc:
 545               return OP_ld_X;
 546             case 0xd:
 547               return OP_ld_X_inc;
 548             case 0xe:
 549               return OP_ld_dec_X;
 550             case 0xf:
 551               return OP_pop;
 552             }
 553           break;
 554         case 0x2:
 555         case 0x3:
 556           switch ((op1 >> 0) & 0xf)
 557             {
 558             case 0x0:
 559               return OP_sts;
 560             case 0x1:
 561               return OP_st_Z_inc;
 562             case 0x2:
 563               return OP_st_dec_Z;
 564             case 0x9:
 565               return OP_st_Y_inc;
 566             case 0xa:
 567               return OP_st_dec_Y;
 568             case 0xc:
 569               return OP_st_X;
 570             case 0xd:
 571               return OP_st_X_inc;
 572             case 0xe:
 573               return OP_st_dec_X;
 574             case 0xf:
 575               return OP_push;
 576             }
 577           break;
 578         case 0x4:
 579         case 0x5:
 580           switch (op1 & 0xf)
 581             {
 582             case 0x0:
 583               return OP_com;
 584             case 0x1:
 585               return OP_neg;
 586             case 0x2:
 587               return OP_swap;
 588             case 0x3:
 589               return OP_inc;
 590             case 0x5:
 591               flash[pc].r = 0x80;
 592               return OP_asr;
 593             case 0x6:
 594               flash[pc].r = 0;
 595               return OP_lsr;
 596             case 0x7:
 597               return OP_ror;
 598             case 0x8: /* 9[45]x8 */
 599               switch ((op1 >> 4) & 0x1f)
 600                 {
 601                 case 0x00:
 602                 case 0x01:
 603                 case 0x02:
 604                 case 0x03:
 605                 case 0x04:
 606                 case 0x05:
 607                 case 0x06:
 608                 case 0x07:
 609                   return OP_bset;
 610                 case 0x08:
 611                 case 0x09:
 612                 case 0x0a:
 613                 case 0x0b:
 614                 case 0x0c:
 615                 case 0x0d:
 616                 case 0x0e:
 617                 case 0x0f:
 618                   return OP_bclr;
 619                 case 0x10:
 620                   return OP_ret;
 621                 case 0x11:
 622                   return OP_reti;
 623                 case 0x19:
 624                   return OP_break;
 625                 case 0x1c:
 626                   return OP_lpm;
 627                 case 0x1d:
 628                   return OP_elpm;
 629                 default:
 630                   break;
 631                 }
 632               break;
 633             case 0x9: /* 9[45]x9 */
 634               switch ((op1 >> 4) & 0x1f)
 635                 {
 636                 case 0x00:
 637                   return OP_ijmp;
 638                 case 0x01:
 639                   return OP_eijmp;
 640                 case 0x10:
 641                   return OP_icall;
 642                 case 0x11:
 643                   return OP_eicall;
 644                 default:
 645                   break;
 646                 }
 647               break;
 648             case 0xa:
 649               return OP_dec;
 650             case 0xc:
 651             case 0xd:
 652               flash[pc].r = ((op1 & 0x1f0) >> 3) | (op1 & 1);
 653               return OP_jmp;
 654             case 0xe:
 655             case 0xf:
 656               flash[pc].r = ((op1 & 0x1f0) >> 3) | (op1 & 1);
 657               return OP_call;
 658             }
 659           break;
 660         case 0x6:
 661           return OP_adiw;
 662         case 0x7:
 663           return OP_sbiw;
 664         case 0x8:
 665           return OP_cbi;
 666         case 0x9:
 667           return OP_sbic;
 668         case 0xa:
 669           return OP_sbi;
 670         case 0xb:
 671           return OP_sbis;
 672         case 0xc:
 673         case 0xd:
 674         case 0xe:
 675         case 0xf:
 676           return OP_mul;
 677         }
 678       break;
 679     case 0xb:
 680       flash[pc].r = get_A (op1);
 681       if (((op1 >> 11) & 1) == 0)
 682         return OP_in;
 683       else
 684         return OP_out;
 685     case 0xc:
 686       return OP_rjmp;
 687     case 0xd:
 688       return OP_rcall;
 689     case 0xe:
 690       return OP_ldi;
 691     case 0xf:
 692       switch ((op1 >> 9) & 7)
 693         {
 694         case 0:
 695         case 1:
 696           flash[pc].r = 1 << (op1 & 7);
 697           return OP_brbs;
 698         case 2:
 699         case 3:
 700           flash[pc].r = 1 << (op1 & 7);
 701           return OP_brbc;
 702         case 4:
 703           if ((op1 & 8) == 0)
 704             {
 705               flash[pc].r = 1 << (op1 & 7);
 706               return OP_bld;
 707             }
 708           break;
 709         case 5:
 710           if ((op1 & 8) == 0)
 711             {
 712               flash[pc].r = 1 << (op1 & 7);
 713               return OP_bst;
 714             }
 715           break;
 716         case 6:
 717           if ((op1 & 8) == 0)
 718             {
 719               flash[pc].r = 1 << (op1 & 7);
 720               return OP_sbrc;
 721             }
 722           break;
 723         case 7:
 724           if ((op1 & 8) == 0)
 725             {
 726               flash[pc].r = 1 << (op1 & 7);
 727               return OP_sbrs;
 728             }
 729           break;
 730         }
 731     }
 732
 733   return OP_bad;
 734 }
 735
 736 static void
 737 do_call (unsigned int npc)
 738 {
 739   unsigned int sp = read_word (REG_SP);
 740
 741   /* Big endian!  */
 742   sram[sp--] = pc;
 743   sram[sp--] = pc >> 8;
 744   if (avr_pc22)
 745     {
 746       sram[sp--] = pc >> 16;
 747       cycles++;
 748     }
 749   write_word (REG_SP, sp);
 750   pc = npc & PC_MASK;
 751   cycles += 3;
 752 }
 753
 754 static int
 755 get_insn_length (unsigned int p)
 756 {
 757   if (flash[p].code == OP_unknown)
 758     flash[p].code = decode(p);
 759   if (flash[p].code >= OP_2words)
 760     return 2;
 761   else
 762     return 1;
 763 }
 764
 765 static unsigned int
 766 get_z (void)
 767 {
 768   return (sram[RAMPZ] << 16) | (sram[REGZ_HI] << 8) | sram[REGZ_LO];
 769 }
 770
 771 static unsigned char
 772 get_lpm (unsigned int addr)
 773 {
 774   word w;
 775
 776   w = flash[(addr >> 1) & PC_MASK].op;
 777   if (addr & 1)
 778     w >>= 8;
 779   return w;
 780 }
 781
 782 static void
 783 gen_mul (unsigned int res)
 784 {
 785   write_word (0, res);
 786   sram[SREG] &= ~(SREG_Z | SREG_C);
 787   if (res == 0)
 788     sram[SREG] |= SREG_Z;
 789   if (res & 0x8000)
 790     sram[SREG] |= SREG_C;
 791   cycles++;
 792 }
 793
 794 static void
 795 step_once (SIM_CPU *cpu)
 796 {
 797   unsigned int ipc;
 798
 799   int code;
 800   word op;
 801   byte res;
 802   byte r, d, vd;
 803
 804  again:
 805   code = flash[pc].code;
 806   op = flash[pc].op;
 807
 808 #if 0
 809       if (tracing && code != OP_unknown)
 810         {
 811           if (verbose > 0) {
 812             int flags;
 813             int i;
 814
 815             sim_cb_eprintf (callback, "R00-07:");
 816             for (i = 0; i < 8; i++)
 817               sim_cb_eprintf (callback, " %02x", sram[i]);
 818             sim_cb_eprintf (callback, " -");
 819             for (i = 8; i < 16; i++)
 820               sim_cb_eprintf (callback, " %02x", sram[i]);
 821             sim_cb_eprintf (callback, "  SP: %02x %02x",
 822                             sram[REG_SP + 1], sram[REG_SP]);
 823             sim_cb_eprintf (callback, "\n");
 824             sim_cb_eprintf (callback, "R16-31:");
 825             for (i = 16; i < 24; i++)
 826               sim_cb_eprintf (callback, " %02x", sram[i]);
 827             sim_cb_eprintf (callback, " -");
 828             for (i = 24; i < 32; i++)
 829               sim_cb_eprintf (callback, " %02x", sram[i]);
 830             sim_cb_eprintf (callback, "  ");
 831             flags = sram[SREG];
 832             for (i = 0; i < 8; i++)
 833               sim_cb_eprintf (callback, "%c",
 834                               flags & (0x80 >> i) ? "ITHSVNZC"[i] : '-');
 835             sim_cb_eprintf (callback, "\n");
 836           }
 837
 838           if (!tracing)
 839             sim_cb_eprintf (callback, "%06x: %04x\n", 2 * pc, flash[pc].op);
 840           else
 841             {
 842               sim_cb_eprintf (callback, "pc=0x%06x insn=0x%04x code=%d r=%d\n",
 843                               2 * pc, flash[pc].op, code, flash[pc].r);
 844               disassemble_insn (CPU_STATE (cpu), pc);
 845               sim_cb_eprintf (callback, "\n");
 846             }
 847         }
 848 #endif
 849
 850   ipc = pc;
 851   pc = (pc + 1) & PC_MASK;
 852   cycles++;
 853
 854   switch (code)
 855     {
 856       case OP_unknown:
 857         flash[ipc].code = decode(ipc);
 858         pc = ipc;
 859         cycles--;
 860         goto again;
 861
 862       case OP_nop:
 863         break;
 864
 865       case OP_jmp:
 866         /* 2 words instruction, but we don't care about the pc.  */
 867         pc = ((flash[ipc].r << 16) | flash[ipc + 1].op) & PC_MASK;
 868         cycles += 2;
 869         break;
 870
 871       case OP_eijmp:
 872         pc = ((sram[EIND] << 16) | read_word (REGZ)) & PC_MASK;
 873         cycles += 2;
 874         break;
 875
 876       case OP_ijmp:
 877         pc = read_word (REGZ) & PC_MASK;
 878         cycles += 1;
 879         break;
 880
 881       case OP_call:
 882         /* 2 words instruction.  */
 883         pc++;
 884         do_call ((flash[ipc].r << 16) | flash[ipc + 1].op);
 885         break;
 886
 887       case OP_eicall:
 888         do_call ((sram[EIND] << 16) | read_word (REGZ));
 889         break;
 890
 891       case OP_icall:
 892         do_call (read_word (REGZ));
 893         break;
 894
 895       case OP_rcall:
 896         do_call (pc + sign_ext (op & 0xfff, 12));
 897         break;
 898
 899       case OP_reti:
 900         sram[SREG] |= SREG_I;
 901         /* Fall through */
 902       case OP_ret:
 903         {
 904           unsigned int sp = read_word (REG_SP);
 905           if (avr_pc22)
 906             {
 907               pc = sram[++sp] << 16;
 908               cycles++;
 909             }
 910           else
 911             pc = 0;
 912           pc |= sram[++sp] << 8;
 913           pc |= sram[++sp];
 914           write_word (REG_SP, sp);
 915         }
 916         cycles += 3;
 917         break;
 918
 919       case OP_break:
 920         /* Stop on this address.  */
 921         sim_engine_halt (CPU_STATE (cpu), cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
 922         pc = ipc;
 923         break;
 924
 925       case OP_bld:
 926         d = get_d (op);
 927         r = flash[ipc].r;
 928         if (sram[SREG] & SREG_T)
 929           sram[d] |= r;
 930         else
 931           sram[d] &= ~r;
 932         break;
 933
 934       case OP_bst:
 935         if (sram[get_d (op)] & flash[ipc].r)
 936           sram[SREG] |= SREG_T;
 937         else
 938           sram[SREG] &= ~SREG_T;
 939         break;
 940
 941       case OP_sbrc:
 942       case OP_sbrs:
 943         if (((sram[get_d (op)] & flash[ipc].r) == 0) ^ ((op & 0x0200) != 0))
 944           {
 945             int l = get_insn_length(pc);
 946             pc += l;
 947             cycles += l;
 948           }
 949         break;
 950
 951       case OP_push:
 952         {
 953           unsigned int sp = read_word (REG_SP);
 954           sram[sp--] = sram[get_d (op)];
 955           write_word (REG_SP, sp);
 956         }
 957         cycles++;
 958         break;
 959
 960       case OP_pop:
 961         {
 962           unsigned int sp = read_word (REG_SP);
 963           sram[get_d (op)] = sram[++sp];
 964           write_word (REG_SP, sp);
 965         }
 966         cycles++;
 967         break;
 968
 969       case OP_bclr:
 970         sram[SREG] &= ~(1 << ((op >> 4) & 0x7));
 971         break;
 972
 973       case OP_bset:
 974         sram[SREG] |= 1 << ((op >> 4) & 0x7);
 975         break;
 976
 977       case OP_rjmp:
 978         pc = (pc + sign_ext (op & 0xfff, 12)) & PC_MASK;
 979         cycles++;
 980         break;
 981
 982       case OP_eor:
 983         d = get_d (op);
 984         res = sram[d] ^ sram[get_r (op)];
 985         sram[d] = res;
 986         update_flags_logic (res);
 987         break;
 988
 989       case OP_and:
 990         d = get_d (op);
 991         res = sram[d] & sram[get_r (op)];
 992         sram[d] = res;
 993         update_flags_logic (res);
 994         break;
 995
 996       case OP_andi:
 997         d = get_d16 (op);
 998         res = sram[d] & get_K (op);
 999         sram[d] = res;
1000         update_flags_logic (res);
1001         break;
1002
1003       case OP_or:
1004         d = get_d (op);
1005         res = sram[d] | sram[get_r (op)];
1006         sram[d] = res;
1007         update_flags_logic (res);
1008         break;
1009
1010       case OP_ori:
1011         d = get_d16 (op);
1012         res = sram[d] | get_K (op);
1013         sram[d] = res;
1014         update_flags_logic (res);
1015         break;
1016
1017       case OP_com:
1018         d = get_d (op);
1019         res = ~sram[d];
1020         sram[d] = res;
1021         update_flags_logic (res);
1022         sram[SREG] |= SREG_C;
1023         break;
1024
1025       case OP_swap:
1026         d = get_d (op);
1027         vd = sram[d];
1028         sram[d] = (vd >> 4) | (vd << 4);
1029         break;
1030
1031       case OP_neg:
1032         d = get_d (op);
1033         vd = sram[d];
1034         res = -vd;
1035         sram[d] = res;
1036         sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1037         if (res == 0)
1038           sram[SREG] |= SREG_Z;
1039         else
1040           sram[SREG] |= SREG_C;
1041         if (res == 0x80)
1042           sram[SREG] |= SREG_V | SREG_N;
1043         else if (res & 0x80)
1044           sram[SREG] |= SREG_N | SREG_S;
1045         if ((res | vd) & 0x08)
1046           sram[SREG] |= SREG_H;
1047         break;
1048
1049       case OP_inc:
1050         d = get_d (op);
1051         res = sram[d] + 1;
1052         sram[d] = res;
1053         sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z);
1054         if (res == 0x80)
1055           sram[SREG] |= SREG_V | SREG_N;
1056         else if (res & 0x80)
1057           sram[SREG] |= SREG_N | SREG_S;
1058         else if (res == 0)
1059           sram[SREG] |= SREG_Z;
1060         break;
1061
1062       case OP_dec:
1063         d = get_d (op);
1064         res = sram[d] - 1;
1065         sram[d] = res;
1066         sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z);
1067         if (res == 0x7f)
1068           sram[SREG] |= SREG_V | SREG_S;
1069         else if (res & 0x80)
1070           sram[SREG] |= SREG_N | SREG_S;
1071         else if (res == 0)
1072           sram[SREG] |= SREG_Z;
1073         break;
1074
1075       case OP_lsr:
1076       case OP_asr:
1077         d = get_d (op);
1078         vd = sram[d];
1079         res = (vd >> 1) | (vd & flash[ipc].r);
1080         sram[d] = res;
1081         sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1082         if (vd & 1)
1083           sram[SREG] |= SREG_C | SREG_S;
1084         if (res & 0x80)
1085           sram[SREG] |= SREG_N;
1086         if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_C))
1087           sram[SREG] |= SREG_V;
1088         if (res == 0)
1089           sram[SREG] |= SREG_Z;
1090         break;
1091
1092       case OP_ror:
1093         d = get_d (op);
1094         vd = sram[d];
1095         res = vd >> 1 | (sram[SREG] << 7);
1096         sram[d] = res;
1097         sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1098         if (vd & 1)
1099           sram[SREG] |= SREG_C | SREG_S;
1100         if (res & 0x80)
1101           sram[SREG] |= SREG_N;
1102         if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_C))
1103           sram[SREG] |= SREG_V;
1104         if (res == 0)
1105           sram[SREG] |= SREG_Z;
1106         break;
1107
1108       case OP_mul:
1109         gen_mul ((word)sram[get_r (op)] * (word)sram[get_d (op)]);
1110         break;
1111
1112       case OP_muls:
1113         gen_mul ((sword)(sbyte)sram[get_r16 (op)]
1114                  * (sword)(sbyte)sram[get_d16 (op)]);
1115         break;
1116
1117       case OP_mulsu:
1118         gen_mul ((sword)(word)sram[get_r16_23 (op)]
1119                  * (sword)(sbyte)sram[get_d16_23 (op)]);
1120         break;
1121
1122       case OP_fmul:
1123         gen_mul (((word)sram[get_r16_23 (op)]
1124                   * (word)sram[get_d16_23 (op)]) << 1);
1125         break;
1126
1127       case OP_fmuls:
1128         gen_mul (((sword)(sbyte)sram[get_r16_23 (op)]
1129                   * (sword)(sbyte)sram[get_d16_23 (op)]) << 1);
1130         break;
1131
1132       case OP_fmulsu:
1133         gen_mul (((sword)(word)sram[get_r16_23 (op)]
1134                   * (sword)(sbyte)sram[get_d16_23 (op)]) << 1);
1135         break;
1136
1137       case OP_adc:
1138       case OP_add:
1139         r = sram[get_r (op)];
1140         d = get_d (op);
1141         vd = sram[d];
1142         res = r + vd + (sram[SREG] & flash[ipc].r);
1143         sram[d] = res;
1144         update_flags_add (res, vd, r);
1145         break;
1146
1147       case OP_sub:
1148         d = get_d (op);
1149         vd = sram[d];
1150         r = sram[get_r (op)];
1151         res = vd - r;
1152         sram[d] = res;
1153         update_flags_sub (res, vd, r);
1154         if (res == 0)
1155           sram[SREG] |= SREG_Z;
1156         break;
1157
1158       case OP_sbc:
1159         {
1160           byte old = sram[SREG];
1161           d = get_d (op);
1162           vd = sram[d];
1163           r = sram[get_r (op)];
1164           res = vd - r - (old & SREG_C);
1165           sram[d] = res;
1166           update_flags_sub (res, vd, r);
1167           if (res == 0 && (old & SREG_Z))
1168             sram[SREG] |= SREG_Z;
1169         }
1170         break;
1171
1172       case OP_subi:
1173         d = get_d16 (op);
1174         vd = sram[d];
1175         r = get_K (op);
1176         res = vd - r;
1177         sram[d] = res;
1178         update_flags_sub (res, vd, r);
1179         if (res == 0)
1180           sram[SREG] |= SREG_Z;
1181         break;
1182
1183       case OP_sbci:
1184         {
1185           byte old = sram[SREG];
1186
1187           d = get_d16 (op);
1188           vd = sram[d];
1189           r = get_K (op);
1190           res = vd - r - (old & SREG_C);
1191           sram[d] = res;
1192           update_flags_sub (res, vd, r);
1193           if (res == 0 && (old & SREG_Z))
1194             sram[SREG] |= SREG_Z;
1195         }
1196         break;
1197
1198       case OP_mov:
1199         sram[get_d (op)] = sram[get_r (op)];
1200         break;
1201
1202       case OP_movw:
1203         d = (op & 0xf0) >> 3;
1204         r = (op & 0x0f) << 1;
1205         sram[d] = sram[r];
1206         sram[d + 1] = sram[r + 1];
1207         break;
1208
1209       case OP_out:
1210         d = get_A (op) + 0x20;
1211         res = sram[get_d (op)];
1212         sram[d] = res;
1213         if (d == STDIO_PORT)
1214           putchar (res);
1215         else if (d == EXIT_PORT)
1216           sim_engine_halt (CPU_STATE (cpu), cpu, NULL, pc, sim_exited, 0);
1217         else if (d == ABORT_PORT)
1218           sim_engine_halt (CPU_STATE (cpu), cpu, NULL, pc, sim_exited, 1);
1219         break;
1220
1221       case OP_in:
1222         d = get_A (op) + 0x20;
1223         sram[get_d (op)] = sram[d];
1224         break;
1225
1226       case OP_cbi:
1227         d = get_biA (op) + 0x20;
1228         sram[d] &= ~(1 << get_b(op));
1229         break;
1230
1231       case OP_sbi:
1232         d = get_biA (op) + 0x20;
1233         sram[d] |= 1 << get_b(op);
1234         break;
1235
1236       case OP_sbic:
1237         if (!(sram[get_biA (op) + 0x20] & 1 << get_b(op)))
1238           {
1239             int l = get_insn_length(pc);
1240             pc += l;
1241             cycles += l;
1242           }
1243         break;
1244
1245       case OP_sbis:
1246         if (sram[get_biA (op) + 0x20] & 1 << get_b(op))
1247           {
1248             int l = get_insn_length(pc);
1249             pc += l;
1250             cycles += l;
1251           }
1252         break;
1253
1254       case OP_ldi:
1255         res = get_K (op);
1256         d = get_d16 (op);
1257         sram[d] = res;
1258         break;
1259
1260       case OP_lds:
1261         sram[get_d (op)] = sram[flash[pc].op];
1262         pc++;
1263         cycles++;
1264         break;
1265
1266       case OP_sts:
1267         sram[flash[pc].op] = sram[get_d (op)];
1268         pc++;
1269         cycles++;
1270         break;
1271
1272       case OP_cpse:
1273         if (sram[get_r (op)] == sram[get_d (op)])
1274           {
1275             int l = get_insn_length(pc);
1276             pc += l;
1277             cycles += l;
1278           }
1279         break;
1280
1281       case OP_cp:
1282         r = sram[get_r (op)];
1283         d = sram[get_d (op)];
1284         res = d - r;
1285         update_flags_sub (res, d, r);
1286         if (res == 0)
1287           sram[SREG] |= SREG_Z;
1288         break;
1289
1290       case OP_cpi:
1291         r = get_K (op);
1292         d = sram[get_d16 (op)];
1293         res = d - r;
1294         update_flags_sub (res, d, r);
1295         if (res == 0)
1296           sram[SREG] |= SREG_Z;
1297         break;
1298
1299       case OP_cpc:
1300         {
1301           byte old = sram[SREG];
1302           d = sram[get_d (op)];
1303           r = sram[get_r (op)];
1304           res = d - r - (old & SREG_C);
1305           update_flags_sub (res, d, r);
1306           if (res == 0 && (old & SREG_Z))
1307             sram[SREG] |= SREG_Z;
1308         }
1309         break;
1310
1311       case OP_brbc:
1312         if (!(sram[SREG] & flash[ipc].r))
1313           {
1314             pc = (pc + get_k (op)) & PC_MASK;
1315             cycles++;
1316           }
1317         break;
1318
1319       case OP_brbs:
1320         if (sram[SREG] & flash[ipc].r)
1321           {
1322             pc = (pc + get_k (op)) & PC_MASK;
1323             cycles++;
1324           }
1325         break;
1326
1327       case OP_lpm:
1328         sram[0] = get_lpm (read_word (REGZ));
1329         cycles += 2;
1330         break;
1331
1332       case OP_lpm_Z:
1333         sram[get_d (op)] = get_lpm (read_word (REGZ));
1334         cycles += 2;
1335         break;
1336
1337       case OP_lpm_inc_Z:
1338         sram[get_d (op)] = get_lpm (read_word_post_inc (REGZ));
1339         cycles += 2;
1340         break;
1341
1342       case OP_elpm:
1343         sram[0] = get_lpm (get_z ());
1344         cycles += 2;
1345         break;
1346
1347       case OP_elpm_Z:
1348         sram[get_d (op)] = get_lpm (get_z ());
1349         cycles += 2;
1350         break;
1351
1352       case OP_elpm_inc_Z:
1353         {
1354           unsigned int z = get_z ();
1355
1356           sram[get_d (op)] = get_lpm (z);
1357           z++;
1358           sram[REGZ_LO] = z;
1359           sram[REGZ_HI] = z >> 8;
1360           sram[RAMPZ] = z >> 16;
1361         }
1362         cycles += 2;
1363         break;
1364
1365       case OP_ld_Z_inc:
1366         sram[get_d (op)] = sram[read_word_post_inc (REGZ) & SRAM_MASK];
1367         cycles++;
1368         break;
1369
1370       case OP_ld_dec_Z:
1371         sram[get_d (op)] = sram[read_word_pre_dec (REGZ) & SRAM_MASK];
1372         cycles++;
1373         break;
1374
1375       case OP_ld_X_inc:
1376         sram[get_d (op)] = sram[read_word_post_inc (REGX) & SRAM_MASK];
1377         cycles++;
1378         break;
1379
1380       case OP_ld_dec_X:
1381         sram[get_d (op)] = sram[read_word_pre_dec (REGX) & SRAM_MASK];
1382         cycles++;
1383         break;
1384
1385       case OP_ld_Y_inc:
1386         sram[get_d (op)] = sram[read_word_post_inc (REGY) & SRAM_MASK];
1387         cycles++;
1388         break;
1389
1390       case OP_ld_dec_Y:
1391         sram[get_d (op)] = sram[read_word_pre_dec (REGY) & SRAM_MASK];
1392         cycles++;
1393         break;
1394
1395       case OP_st_X:
1396         sram[read_word (REGX) & SRAM_MASK] = sram[get_d (op)];
1397         cycles++;
1398         break;
1399
1400       case OP_st_X_inc:
1401         sram[read_word_post_inc (REGX) & SRAM_MASK] = sram[get_d (op)];
1402         cycles++;
1403         break;
1404
1405       case OP_st_dec_X:
1406         sram[read_word_pre_dec (REGX) & SRAM_MASK] = sram[get_d (op)];
1407         cycles++;
1408         break;
1409
1410       case OP_st_Z_inc:
1411         sram[read_word_post_inc (REGZ) & SRAM_MASK] = sram[get_d (op)];
1412         cycles++;
1413         break;
1414
1415       case OP_st_dec_Z:
1416         sram[read_word_pre_dec (REGZ) & SRAM_MASK] = sram[get_d (op)];
1417         cycles++;
1418         break;
1419
1420       case OP_st_Y_inc:
1421         sram[read_word_post_inc (REGY) & SRAM_MASK] = sram[get_d (op)];
1422         cycles++;
1423         break;
1424
1425       case OP_st_dec_Y:
1426         sram[read_word_pre_dec (REGY) & SRAM_MASK] = sram[get_d (op)];
1427         cycles++;
1428         break;
1429
1430       case OP_std_Y:
1431         sram[read_word (REGY) + flash[ipc].r] = sram[get_d (op)];
1432         cycles++;
1433         break;
1434
1435       case OP_std_Z:
1436         sram[read_word (REGZ) + flash[ipc].r] = sram[get_d (op)];
1437         cycles++;
1438         break;
1439
1440       case OP_ldd_Z:
1441         sram[get_d (op)] = sram[read_word (REGZ) + flash[ipc].r];
1442         cycles++;
1443         break;
1444
1445       case OP_ldd_Y:
1446         sram[get_d (op)] = sram[read_word (REGY) + flash[ipc].r];
1447         cycles++;
1448         break;
1449
1450       case OP_ld_X:
1451         sram[get_d (op)] = sram[read_word (REGX) & SRAM_MASK];
1452         cycles++;
1453         break;
1454
1455       case OP_sbiw:
1456         {
1457           word wk = get_k6 (op);
1458           word wres;
1459           word wr;
1460
1461           d = get_d24 (op);
1462           wr = read_word (d);
1463           wres = wr - wk;
1464
1465           sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1466           if (wres == 0)
1467             sram[SREG] |= SREG_Z;
1468           if (wres & 0x8000)
1469             sram[SREG] |= SREG_N;
1470           if (wres & ~wr & 0x8000)
1471             sram[SREG] |= SREG_C;
1472           if (~wres & wr & 0x8000)
1473             sram[SREG] |= SREG_V;
1474           if (((~wres & wr) ^ wres) & 0x8000)
1475             sram[SREG] |= SREG_S;
1476           write_word (d, wres);
1477         }
1478         cycles++;
1479         break;
1480
1481       case OP_adiw:
1482         {
1483           word wk = get_k6 (op);
1484           word wres;
1485           word wr;
1486
1487           d = get_d24 (op);
1488           wr = read_word (d);
1489           wres = wr + wk;
1490
1491           sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1492           if (wres == 0)
1493             sram[SREG] |= SREG_Z;
1494           if (wres & 0x8000)
1495             sram[SREG] |= SREG_N;
1496           if (~wres & wr & 0x8000)
1497             sram[SREG] |= SREG_C;
1498           if (wres & ~wr & 0x8000)
1499             sram[SREG] |= SREG_V;
1500           if (((wres & ~wr) ^ wres) & 0x8000)
1501             sram[SREG] |= SREG_S;
1502           write_word (d, wres);
1503         }
1504         cycles++;
1505         break;
1506
1507       case OP_bad:
1508         sim_engine_halt (CPU_STATE (cpu), cpu, NULL, pc, sim_signalled, SIM_SIGILL);
1509
1510       default:
1511         sim_engine_halt (CPU_STATE (cpu), cpu, NULL, pc, sim_signalled, SIM_SIGILL);
1512       }
1513 }
1514
1515 void
1516 sim_engine_run (SIM_DESC sd,
1517                 int next_cpu_nr, /* ignore  */
1518                 int nr_cpus, /* ignore  */
1519                 int siggnal) /* ignore  */
1520 {
1521   SIM_CPU *cpu;
1522
1523   SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
1524
1525   cpu = STATE_CPU (sd, 0);
1526
1527   while (1)
1528     {
1529       step_once (cpu);
1530       if (sim_events_tick (sd))
1531         sim_events_process (sd);
1532     }
1533 }
1534
1535 int
1536 sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size)
1537 {
1538   int osize = size;
1539
1540   if (addr >= 0 && addr < SRAM_VADDR)
1541     {
1542       while (size > 0 && addr < (MAX_AVR_FLASH << 1))
1543         {
1544           word val = flash[addr >> 1].op;
1545
1546           if (addr & 1)
1547             val = (val & 0xff) | (buffer[0] << 8);
1548           else
1549             val = (val & 0xff00) | buffer[0];
1550
1551           flash[addr >> 1].op = val;
1552           flash[addr >> 1].code = OP_unknown;
1553           addr++;
1554           buffer++;
1555           size--;
1556         }
1557       return osize - size;
1558     }
1559   else if (addr >= SRAM_VADDR && addr < SRAM_VADDR + MAX_AVR_SRAM)
1560     {
1561       addr -= SRAM_VADDR;
1562       if (addr + size > MAX_AVR_SRAM)
1563         size = MAX_AVR_SRAM - addr;
1564       memcpy (sram + addr, buffer, size);
1565       return size;
1566     }
1567   else
1568     return 0;
1569 }
1570
1571 int
1572 sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
1573 {
1574   int osize = size;
1575
1576   if (addr >= 0 && addr < SRAM_VADDR)
1577     {
1578       while (size > 0 && addr < (MAX_AVR_FLASH << 1))
1579         {
1580           word val = flash[addr >> 1].op;
1581
1582           if (addr & 1)
1583             val >>= 8;
1584
1585           *buffer++ = val;
1586           addr++;
1587           size--;
1588         }
1589       return osize - size;
1590     }
1591   else if (addr >= SRAM_VADDR && addr < SRAM_VADDR + MAX_AVR_SRAM)
1592     {
1593       addr -= SRAM_VADDR;
1594       if (addr + size > MAX_AVR_SRAM)
1595         size = MAX_AVR_SRAM - addr;
1596       memcpy (buffer, sram + addr, size);
1597       return size;
1598     }
1599   else
1600     {
1601       /* Avoid errors.  */
1602       memset (buffer, 0, size);
1603       return size;
1604     }
1605 }
1606
1607 int
1608 sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
1609 {
1610   if (rn < 32 && length == 1)
1611     {
1612       sram[rn] = *memory;
1613       return 1;
1614     }
1615   if (rn == AVR_SREG_REGNUM && length == 1)
1616     {
1617       sram[SREG] = *memory;
1618       return 1;
1619     }
1620   if (rn == AVR_SP_REGNUM && length == 2)
1621     {
1622       sram[REG_SP] = memory[0];
1623       sram[REG_SP + 1] = memory[1];
1624       return 2;
1625     }
1626   if (rn == AVR_PC_REGNUM && length == 4)
1627     {
1628       pc = (memory[0] >> 1) | (memory[1] << 7)
1629         | (memory[2] << 15) | (memory[3] << 23);
1630       pc &= PC_MASK;
1631       return 4;
1632     }
1633   return 0;
1634 }
1635
1636 int
1637 sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
1638 {
1639   if (rn < 32 && length == 1)
1640     {
1641       *memory = sram[rn];
1642       return 1;
1643     }
1644   if (rn == AVR_SREG_REGNUM && length == 1)
1645     {
1646       *memory = sram[SREG];
1647       return 1;
1648     }
1649   if (rn == AVR_SP_REGNUM && length == 2)
1650     {
1651       memory[0] = sram[REG_SP];
1652       memory[1] = sram[REG_SP + 1];
1653       return 2;
1654     }
1655   if (rn == AVR_PC_REGNUM && length == 4)
1656     {
1657       memory[0] = pc << 1;
1658       memory[1] = pc >> 7;
1659       memory[2] = pc >> 15;
1660       memory[3] = pc >> 23;
1661       return 4;
1662     }
1663   return 0;
1664 }
1665
1666 static sim_cia
1667 avr_pc_get (sim_cpu *cpu)
1668 {
1669   return pc;
1670 }
1671
1672 static void
1673 avr_pc_set (sim_cpu *cpu, sim_cia _pc)
1674 {
1675   pc = _pc;
1676 }
1677
1678 static void
1679 free_state (SIM_DESC sd)
1680 {
1681   if (STATE_MODULES (sd) != NULL)
1682     sim_module_uninstall (sd);
1683   sim_cpu_free_all (sd);
1684   sim_state_free (sd);
1685 }
1686
1687 SIM_DESC
1688 sim_open (SIM_OPEN_KIND kind, host_callback *cb, struct bfd *abfd, char **argv)
1689 {
1690   int i;
1691   SIM_DESC sd = sim_state_alloc (kind, cb);
1692   SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
1693
1694   /* The cpu data is kept in a separately allocated chunk of memory.  */
1695   if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
1696     {
1697       free_state (sd);
1698       return 0;
1699     }
1700
1701   STATE_WATCHPOINTS (sd)->pc = &pc;
1702   STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (pc);
1703
1704   if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
1705     {
1706       free_state (sd);
1707       return 0;
1708     }
1709
1710   /* getopt will print the error message so we just have to exit if this fails.
1711      FIXME: Hmmm...  in the case of gdb we need getopt to call
1712      print_filtered.  */
1713   if (sim_parse_args (sd, argv) != SIM_RC_OK)
1714     {
1715       free_state (sd);
1716       return 0;
1717     }
1718
1719   /* Check for/establish the a reference program image.  */
1720   if (sim_analyze_program (sd,
1721                            (STATE_PROG_ARGV (sd) != NULL
1722                             ? *STATE_PROG_ARGV (sd)
1723                             : NULL), abfd) != SIM_RC_OK)
1724     {
1725       free_state (sd);
1726       return 0;
1727     }
1728
1729   /* Configure/verify the target byte order and other runtime
1730      configuration options.  */
1731   if (sim_config (sd) != SIM_RC_OK)
1732     {
1733       sim_module_uninstall (sd);
1734       return 0;
1735     }
1736
1737   if (sim_post_argv_init (sd) != SIM_RC_OK)
1738     {
1739       /* Uninstall the modules to avoid memory leaks,
1740          file descriptor leaks, etc.  */
1741       sim_module_uninstall (sd);
1742       return 0;
1743     }
1744
1745   /* CPU specific initialization.  */
1746   for (i = 0; i < MAX_NR_PROCESSORS; ++i)
1747     {
1748       SIM_CPU *cpu = STATE_CPU (sd, i);
1749
1750       CPU_PC_FETCH (cpu) = avr_pc_get;
1751       CPU_PC_STORE (cpu) = avr_pc_set;
1752     }
1753
1754   /* Clear all the memory.  */
1755   memset (sram, 0, sizeof (sram));
1756   memset (flash, 0, sizeof (flash));
1757
1758   return sd;
1759 }
1760
1761 SIM_RC
1762 sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char **argv, char **env)
1763 {
1764   /* Set the PC.  */
1765   if (abfd != NULL)
1766     pc = bfd_get_start_address (abfd);
1767   else
1768     pc = 0;
1769
1770   if (abfd != NULL)
1771     avr_pc22 = (bfd_get_mach (abfd) >= bfd_mach_avr6);
1772
1773   return SIM_RC_OK;
1774 }