1 /* Blackfin Core Timer model.
3 Copyright (C) 2010-2011 Free Software Foundation, Inc.
4 Contributed by Analog Devices, Inc.
6 This file is part of simulators.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
25 #include "dv-bfin_cec.h"
26 #include "dv-bfin_ctimer.h"
31 struct hw_event
*handler
;
34 /* Order after here is important -- matches hardware MMR layout. */
35 bu32 tcntl
, tperiod
, tscale
, tcount
;
37 #define mmr_base() offsetof(struct bfin_ctimer, tcntl)
38 #define mmr_offset(mmr) (offsetof(struct bfin_ctimer, mmr) - mmr_base())
40 static const char * const mmr_names
[] = {
41 "TCNTL", "TPERIOD", "TSCALE", "TCOUNT",
43 #define mmr_name(off) mmr_names[(off) / 4]
46 bfin_ctimer_enabled (struct bfin_ctimer
*ctimer
)
48 return (ctimer
->tcntl
& TMPWR
) && (ctimer
->tcntl
& TMREN
);
52 bfin_ctimer_scale (struct bfin_ctimer
*ctimer
)
54 /* Only low 8 bits are actually checked. */
55 return (ctimer
->tscale
& 0xff) + 1;
59 bfin_ctimer_schedule (struct hw
*me
, struct bfin_ctimer
*ctimer
);
62 bfin_ctimer_expire (struct hw
*me
, void *data
)
64 struct bfin_ctimer
*ctimer
= data
;
66 ctimer
->tcntl
|= TINT
;
67 if (ctimer
->tcntl
& TAUTORLD
)
69 ctimer
->tcount
= ctimer
->tperiod
;
70 bfin_ctimer_schedule (me
, ctimer
);
75 ctimer
->handler
= NULL
;
78 hw_port_event (me
, IVG_IVTMR
, 1);
82 bfin_ctimer_update_count (struct hw
*me
, struct bfin_ctimer
*ctimer
)
87 /* If the timer was enabled w/out autoreload and has expired, then
88 there's nothing to calculate here. */
89 if (ctimer
->handler
== NULL
)
92 scale
= bfin_ctimer_scale (ctimer
);
93 timeout
= hw_event_remain_time (me
, ctimer
->handler
);
94 ticks
= ctimer
->timeout
- timeout
;
95 ctimer
->tcount
-= (scale
* ticks
);
96 ctimer
->timeout
= timeout
;
100 bfin_ctimer_deschedule (struct hw
*me
, struct bfin_ctimer
*ctimer
)
104 hw_event_queue_deschedule (me
, ctimer
->handler
);
105 ctimer
->handler
= NULL
;
110 bfin_ctimer_schedule (struct hw
*me
, struct bfin_ctimer
*ctimer
)
112 bu32 scale
= bfin_ctimer_scale (ctimer
);
113 ctimer
->timeout
= (ctimer
->tcount
/ scale
) + !!(ctimer
->tcount
% scale
);
114 ctimer
->handler
= hw_event_queue_schedule (me
, ctimer
->timeout
,
120 bfin_ctimer_io_write_buffer (struct hw
*me
, const void *source
,
121 int space
, address_word addr
, unsigned nr_bytes
)
123 struct bfin_ctimer
*ctimer
= hw_data (me
);
129 value
= dv_load_4 (source
);
130 mmr_off
= addr
- ctimer
->base
;
131 valuep
= (void *)((unsigned long)ctimer
+ mmr_base() + mmr_off
);
135 curr_enabled
= bfin_ctimer_enabled (ctimer
);
138 case mmr_offset(tcntl
):
139 /* HRM describes TINT as sticky, but it isn't W1C. */
142 if (bfin_ctimer_enabled (ctimer
) == curr_enabled
)
146 else if (curr_enabled
)
148 bfin_ctimer_update_count (me
, ctimer
);
149 bfin_ctimer_deschedule (me
, ctimer
);
152 bfin_ctimer_schedule (me
, ctimer
);
155 case mmr_offset(tcount
):
156 /* HRM says writes are discarded when enabled. */
157 /* XXX: But hardware seems to be writeable all the time ? */
158 /* if (!curr_enabled) */
161 case mmr_offset(tperiod
):
162 /* HRM says writes are discarded when enabled. */
163 /* XXX: But hardware seems to be writeable all the time ? */
164 /* if (!curr_enabled) */
166 /* Writes are mirrored into TCOUNT. */
167 ctimer
->tcount
= value
;
171 case mmr_offset(tscale
):
174 bfin_ctimer_update_count (me
, ctimer
);
175 bfin_ctimer_deschedule (me
, ctimer
);
179 bfin_ctimer_schedule (me
, ctimer
);
187 bfin_ctimer_io_read_buffer (struct hw
*me
, void *dest
,
188 int space
, address_word addr
, unsigned nr_bytes
)
190 struct bfin_ctimer
*ctimer
= hw_data (me
);
194 mmr_off
= addr
- ctimer
->base
;
195 valuep
= (void *)((unsigned long)ctimer
+ mmr_base() + mmr_off
);
201 case mmr_offset(tcount
):
202 /* Since we're optimizing events here, we need to calculate
203 the new tcount value. */
204 if (bfin_ctimer_enabled (ctimer
))
205 bfin_ctimer_update_count (me
, ctimer
);
209 dv_store_4 (dest
, *valuep
);
214 static const struct hw_port_descriptor bfin_ctimer_ports
[] = {
215 { "ivtmr", IVG_IVTMR
, 0, output_port
, },
220 attach_bfin_ctimer_regs (struct hw
*me
, struct bfin_ctimer
*ctimer
)
222 address_word attach_address
;
224 unsigned attach_size
;
225 reg_property_spec reg
;
227 if (hw_find_property (me
, "reg") == NULL
)
228 hw_abort (me
, "Missing \"reg\" property");
230 if (!hw_find_reg_array_property (me
, "reg", 0, ®
))
231 hw_abort (me
, "\"reg\" property must contain three addr/size entries");
233 hw_unit_address_to_attach_address (hw_parent (me
),
235 &attach_space
, &attach_address
, me
);
236 hw_unit_size_to_attach_size (hw_parent (me
), ®
.size
, &attach_size
, me
);
238 if (attach_size
!= BFIN_COREMMR_CTIMER_SIZE
)
239 hw_abort (me
, "\"reg\" size must be %#x", BFIN_COREMMR_CTIMER_SIZE
);
241 hw_attach_address (hw_parent (me
),
242 0, attach_space
, attach_address
, attach_size
, me
);
244 ctimer
->base
= attach_address
;
248 bfin_ctimer_finish (struct hw
*me
)
250 struct bfin_ctimer
*ctimer
;
252 ctimer
= HW_ZALLOC (me
, struct bfin_ctimer
);
254 set_hw_data (me
, ctimer
);
255 set_hw_io_read_buffer (me
, bfin_ctimer_io_read_buffer
);
256 set_hw_io_write_buffer (me
, bfin_ctimer_io_write_buffer
);
257 set_hw_ports (me
, bfin_ctimer_ports
);
259 attach_bfin_ctimer_regs (me
, ctimer
);
261 /* Initialize the Core Timer. */
264 const struct hw_descriptor dv_bfin_ctimer_descriptor
[] = {
265 {"bfin_ctimer", bfin_ctimer_finish
,},