sim/bfin/dv-bfin_pll.c

   1 /* Blackfin Phase Lock Loop (PLL) model.
   2
   3    Copyright (C) 2010-2011 Free Software Foundation, Inc.
   4    Contributed by Analog Devices, Inc.
   5
   6    This file is part of simulators.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #include "config.h"
  22
  23 #include "sim-main.h"
  24 #include "machs.h"
  25 #include "devices.h"
  26 #include "dv-bfin_pll.h"
  27
  28 struct bfin_pll
  29 {
  30   bu32 base;
  31
  32   /* Order after here is important -- matches hardware MMR layout.  */
  33   bu16 BFIN_MMR_16(pll_ctl);
  34   bu16 BFIN_MMR_16(pll_div);
  35   bu16 BFIN_MMR_16(vr_ctl);
  36   bu16 BFIN_MMR_16(pll_stat);
  37   bu16 BFIN_MMR_16(pll_lockcnt);
  38
  39   /* XXX: Not really the best place for this ...  */
  40   bu32 chipid;
  41 };
  42 #define mmr_base()      offsetof(struct bfin_pll, pll_ctl)
  43 #define mmr_offset(mmr) (offsetof(struct bfin_pll, mmr) - mmr_base())
  44
  45 static const char * const mmr_names[] = {
  46   "PLL_CTL", "PLL_DIV", "VR_CTL", "PLL_STAT", "PLL_LOCKCNT", "CHIPID",
  47 };
  48 #define mmr_name(off) mmr_names[(off) / 4]
  49
  50 static unsigned
  51 bfin_pll_io_write_buffer (struct hw *me, const void *source,
  52                           int space, address_word addr, unsigned nr_bytes)
  53 {
  54   struct bfin_pll *pll = hw_data (me);
  55   bu32 mmr_off;
  56   bu32 value;
  57   bu16 *value16p;
  58   bu32 *value32p;
  59   void *valuep;
  60
  61   if (nr_bytes == 4)
  62     value = dv_load_4 (source);
  63   else
  64     value = dv_load_2 (source);
  65
  66   mmr_off = addr - pll->base;
  67   valuep = (void *)((unsigned long)pll + mmr_base() + mmr_off);
  68   value16p = valuep;
  69   value32p = valuep;
  70
  71   HW_TRACE_WRITE ();
  72
  73   switch (mmr_off)
  74     {
  75     case mmr_offset(pll_stat):
  76       dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
  77     case mmr_offset(chipid):
  78       /* Discard writes.  */
  79       break;
  80     default:
  81       dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
  82       *value16p = value;
  83       break;
  84     }
  85
  86   return nr_bytes;
  87 }
  88
  89 static unsigned
  90 bfin_pll_io_read_buffer (struct hw *me, void *dest,
  91                          int space, address_word addr, unsigned nr_bytes)
  92 {
  93   struct bfin_pll *pll = hw_data (me);
  94   bu32 mmr_off;
  95   bu32 *value32p;
  96   bu16 *value16p;
  97   void *valuep;
  98
  99   mmr_off = addr - pll->base;
 100   valuep = (void *)((unsigned long)pll + mmr_base() + mmr_off);
 101   value16p = valuep;
 102   value32p = valuep;
 103
 104   HW_TRACE_READ ();
 105
 106   switch (mmr_off)
 107     {
 108     case mmr_offset(chipid):
 109       dv_store_4 (dest, *value32p);
 110       break;
 111     default:
 112       dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
 113       dv_store_2 (dest, *value16p);
 114       break;
 115     }
 116
 117   return nr_bytes;
 118 }
 119
 120 static const struct hw_port_descriptor bfin_pll_ports[] = {
 121   { "pll", 0, 0, output_port, },
 122   { NULL, 0, 0, 0, },
 123 };
 124
 125 static void
 126 attach_bfin_pll_regs (struct hw *me, struct bfin_pll *pll)
 127 {
 128   address_word attach_address;
 129   int attach_space;
 130   unsigned attach_size;
 131   reg_property_spec reg;
 132
 133   if (hw_find_property (me, "reg") == NULL)
 134     hw_abort (me, "Missing \"reg\" property");
 135
 136   if (!hw_find_reg_array_property (me, "reg", 0, &reg))
 137     hw_abort (me, "\"reg\" property must contain three addr/size entries");
 138
 139   hw_unit_address_to_attach_address (hw_parent (me),
 140                                      &reg.address,
 141                                      &attach_space, &attach_address, me);
 142   hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);
 143
 144   if (attach_size != BFIN_MMR_PLL_SIZE)
 145     hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_PLL_SIZE);
 146
 147   hw_attach_address (hw_parent (me),
 148                      0, attach_space, attach_address, attach_size, me);
 149
 150   pll->base = attach_address;
 151 }
 152
 153 static void
 154 bfin_pll_finish (struct hw *me)
 155 {
 156   struct bfin_pll *pll;
 157
 158   pll = HW_ZALLOC (me, struct bfin_pll);
 159
 160   set_hw_data (me, pll);
 161   set_hw_io_read_buffer (me, bfin_pll_io_read_buffer);
 162   set_hw_io_write_buffer (me, bfin_pll_io_write_buffer);
 163   set_hw_ports (me, bfin_pll_ports);
 164
 165   attach_bfin_pll_regs (me, pll);
 166
 167   /* Initialize the PLL.  */
 168   /* XXX: Depends on part ?  */
 169   pll->pll_ctl = 0x1400;
 170   pll->pll_div = 0x0005;
 171   pll->vr_ctl = 0x40DB;
 172   pll->pll_stat = 0x00A2;
 173   pll->pll_lockcnt = 0x0200;
 174   pll->chipid = bfin_model_get_chipid (hw_system (me));
 175
 176   /* XXX: slow it down!  */
 177   pll->pll_ctl = 0xa800;
 178   pll->pll_div = 0x4;
 179   pll->vr_ctl = 0x40fb;
 180   pll->pll_stat = 0xa2;
 181   pll->pll_lockcnt = 0x300;
 182 }
 183
 184 const struct hw_descriptor dv_bfin_pll_descriptor[] = {
 185   {"bfin_pll", bfin_pll_finish,},
 186   {NULL, NULL},
 187 };