sim: bfin: new port
[deliverable/binutils-gdb.git] / sim / bfin / dv-bfin_uart.h
1 /* Blackfin Universal Asynchronous Receiver/Transmitter (UART) model.
2 For "old style" UARTs on BF53x/etc... parts.
3
4 Copyright (C) 2010-2011 Free Software Foundation, Inc.
5 Contributed by Analog Devices, Inc.
6
7 This file is part of simulators.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21
22 #ifndef DV_BFIN_UART_H
23 #define DV_BFIN_UART_H
24
25 /* XXX: This should be pushed into the model data. */
26 #define BFIN_MMR_UART_SIZE 0x30
27
28 struct bfin_uart;
29 bu16 bfin_uart_get_next_byte (struct hw *, bu16, bool *fresh);
30 bu16 bfin_uart_write_byte (struct hw *, bu16);
31 bu16 bfin_uart_get_status (struct hw *);
32 unsigned bfin_uart_write_buffer (struct hw *, const unsigned char *, unsigned);
33 unsigned bfin_uart_read_buffer (struct hw *, unsigned char *, unsigned);
34 void bfin_uart_reschedule (struct hw *);
35
36 /* UART_LCR */
37 #define DLAB (1 << 7)
38
39 /* UART_LSR */
40 #define TEMT (1 << 6)
41 #define THRE (1 << 5)
42 #define DR (1 << 0)
43
44 /* UART_IER */
45 #define ERBFI (1 << 0)
46 #define ETBEI (1 << 1)
47 #define ELSI (1 << 2)
48
49 #endif
This page took 0.032741 seconds and 4 git commands to generate.