sim: trace: add a basic cpu register class
[deliverable/binutils-gdb.git] / sim / bfin / tconfig.h
1 /* Blackfin target configuration file. -*- C -*- */
2
3 /* See sim-hload.c. We properly handle LMA. -- TODO: check this */
4 #define SIM_HANDLES_LMA 1
5
6 /* We use this so that we are passed the requesting CPU for HW acesses.
7 Common sim core by default sets hw_system_cpu to NULL for WITH_HW. */
8 #define WITH_DEVICES 1
9
10 /* ??? Temporary hack until model support unified. */
11 #define SIM_HAVE_MODEL
12
13 /* Allows us to do the memory aliasing that some bfroms have:
14 {0xef000000 - 0xef100000} => {0xef000000 - 0xef000800} */
15 #define WITH_MODULO_MEMORY 1
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