1 /* Engine header for Cpu tools GENerated simulators.
2 Copyright (C) 1998, 1999, 2007, 2008, 2009 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* This file is included by ${cpu}.h.
21 It needs CGEN_INSN_WORD which is defined by ${cpu}.h.
22 ??? A lot of this could be moved to genmloop.sh to be put in eng.h
23 and thus remove some conditional compilation. We'd still need
24 CGEN_INSN_WORD though. */
26 /* Semantic functions come in six versions on two axes:
27 fast/full-featured, and using one of the simple/scache/compilation engines.
28 A full featured simulator is always provided. --enable-sim-fast includes
29 support for fast execution by duplicating the semantic code but leaving
30 out all features like tracing and profiling.
31 Using the scache is selected with --enable-sim-scache. */
32 /* FIXME: --enable-sim-fast not implemented yet. */
33 /* FIXME: undecided how to handle WITH_SCACHE_PBB. */
35 /* There are several styles of engines, all generally supported by the
38 WITH_SCACHE && WITH_SCACHE_PBB - pseudo-basic-block scaching
39 WITH_SCACHE && !WITH_SCACHE_PBB - scaching on an insn by insn basis
40 !WITH_SCACHE - simple engine: fetch an insn, execute an insn
42 The !WITH_SCACHE case can also be broken up into two flavours:
43 extract the fields of the insn into an ARGBUF struct, or defer the
44 extraction to the semantic handler. The former can be viewed as the
45 WITH_SCACHE case with a cache size of 1 (thus there's no need for a
46 WITH_EXTRACTION macro). The WITH_SCACHE case always extracts the fields
47 into an ARGBUF struct. */
52 /* Instruction field support macros. */
54 #define EXTRACT_MSB0_INT(val, total, start, length) \
55 (((INT) (val) << ((sizeof (INT) * 8) - (total) + (start))) \
56 >> ((sizeof (INT) * 8) - (length)))
57 #define EXTRACT_MSB0_UINT(val, total, start, length) \
58 (((UINT) (val) << ((sizeof (UINT) * 8) - (total) + (start))) \
59 >> ((sizeof (UINT) * 8) - (length)))
61 #define EXTRACT_LSB0_INT(val, total, start, length) \
62 (((INT) (val) << ((sizeof (INT) * 8) - (start) - 1)) \
63 >> ((sizeof (INT) * 8) - (length)))
64 #define EXTRACT_LSB0_UINT(val, total, start, length) \
65 (((UINT) (val) << ((sizeof (UINT) * 8) - (start) - 1)) \
66 >> ((sizeof (UINT) * 8) - (length)))
68 #define EXTRACT_MSB0_LGSINT(val, total, start, length) \
69 (((CGEN_INSN_LGSINT) (val) << ((sizeof (CGEN_INSN_LGSINT) * 8) - (total) + (start))) \
70 >> ((sizeof (CGEN_INSN_LGSINT) * 8) - (length)))
71 #define EXTRACT_MSB0_LGUINT(val, total, start, length) \
72 (((CGEN_INSN_UINT) (val) << ((sizeof (CGEN_INSN_LGUINT) * 8) - (total) + (start))) \
73 >> ((sizeof (CGEN_INSN_LGUINT) * 8) - (length)))
75 #define EXTRACT_LSB0_LGSINT(val, total, start, length) \
76 (((CGEN_INSN_LGSINT) (val) << ((sizeof (CGEN_INSN_LGSINT) * 8) - (start) - 1)) \
77 >> ((sizeof (CGEN_INSN_LGSINT) * 8) - (length)))
78 #define EXTRACT_LSB0_LGUINT(val, total, start, length) \
79 (((CGEN_INSN_LGUINT) (val) << ((sizeof (CGEN_INSN_LGUINT) * 8) - (start) - 1)) \
80 >> ((sizeof (CGEN_INSN_LGUINT) * 8) - (length)))
82 /* Semantic routines. */
84 /* Type of the machine generated extraction fns. */
85 /* ??? No longer used. */
86 typedef void (EXTRACT_FN
) (SIM_CPU
*, IADDR
, CGEN_INSN_WORD
, ARGBUF
*);
88 /* Type of the machine generated semantic fns. */
92 /* Instruction fields are extracted into ARGBUF before calling the
94 #if HAVE_PARALLEL_INSNS && ! WITH_PARALLEL_GENWRITE
95 typedef SEM_PC (SEMANTIC_FN
) (SIM_CPU
*, SEM_ARG
, PAREXEC
*);
97 typedef SEM_PC (SEMANTIC_FN
) (SIM_CPU
*, SEM_ARG
);
102 /* Result of semantic routines is a status indicator (wip). */
103 typedef unsigned int SEM_STATUS
;
105 /* Instruction fields are extracted by the semantic routine.
106 ??? TODO: multi word insns. */
107 #if HAVE_PARALLEL_INSNS && ! WITH_PARALLEL_GENWRITE
108 typedef SEM_STATUS (SEMANTIC_FN
) (SIM_CPU
*, SEM_ARG
, PAREXEC
*, CGEN_INSN_WORD
);
110 typedef SEM_STATUS (SEMANTIC_FN
) (SIM_CPU
*, SEM_ARG
, CGEN_INSN_WORD
);
115 /* In the ARGBUF struct, a pointer to the semantic routine for the insn. */
118 #if ! WITH_SEM_SWITCH_FULL
119 SEMANTIC_FN
*sem_full
;
121 #if ! WITH_SEM_SWITCH_FAST
122 SEMANTIC_FN
*sem_fast
;
124 #if WITH_SEM_SWITCH_FULL || WITH_SEM_SWITCH_FAST
133 /* Set the appropriate semantic handler in ABUF. */
135 #if WITH_SEM_SWITCH_FULL
137 #define SEM_SET_FULL_CODE(abuf, idesc) \
138 do { (abuf)->semantic.sem_case = (idesc)->sem_full_lab; } while (0)
140 #define SEM_SET_FULL_CODE(abuf, idesc) \
141 do { (abuf)->semantic.sem_case = (idesc)->num; } while (0)
144 #define SEM_SET_FULL_CODE(abuf, idesc) \
145 do { (abuf)->semantic.sem_full = (idesc)->sem_full; } while (0)
148 #if WITH_SEM_SWITCH_FAST
150 #define SEM_SET_FAST_CODE(abuf, idesc) \
151 do { (abuf)->semantic.sem_case = (idesc)->sem_fast_lab; } while (0)
153 #define SEM_SET_FAST_CODE(abuf, idesc) \
154 do { (abuf)->semantic.sem_case = (idesc)->num; } while (0)
157 #define SEM_SET_FAST_CODE(abuf, idesc) \
158 do { (abuf)->semantic.sem_fast = (idesc)->sem_fast; } while (0)
161 #define SEM_SET_CODE(abuf, idesc, fast_p) \
164 SEM_SET_FAST_CODE ((abuf), (idesc)); \
166 SEM_SET_FULL_CODE ((abuf), (idesc)); \
169 /* Return non-zero if IDESC is a conditional or unconditional CTI. */
171 #define IDESC_CTI_P(idesc) \
172 ((CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->idata)) \
173 & (CGEN_ATTR_MASK (CGEN_INSN_COND_CTI) \
174 | CGEN_ATTR_MASK (CGEN_INSN_UNCOND_CTI))) \
177 /* Return non-zero if IDESC is a skip insn. */
179 #define IDESC_SKIP_P(idesc) \
180 ((CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->idata)) \
181 & CGEN_ATTR_MASK (CGEN_INSN_SKIP_CTI)) \
184 /* Return pointer to ARGBUF given ptr to SCACHE. */
185 #define SEM_ARGBUF(sem_arg) (& (sem_arg) -> argbuf)
187 /* There are several styles of engines, all generally supported by the
190 WITH_SCACHE && WITH_SCACHE_PBB - pseudo-basic-block scaching
191 WITH_SCACHE && !WITH_SCACHE_PBB - scaching on an insn by insn basis
192 !WITH_SCACHE - simple engine: fetch an insn, execute an insn
194 ??? The !WITH_SCACHE case can also be broken up into two flavours:
195 extract the fields of the insn into an ARGBUF struct, or defer the
196 extraction to the semantic handler. The WITH_SCACHE case always
197 extracts the fields into an ARGBUF struct. */
201 #define CIA_ADDR(cia) (cia)
205 /* Return the scache pointer of the current insn. */
206 #define SEM_SEM_ARG(vpc, sc) (vpc)
208 /* Return the virtual pc of the next insn to execute
209 (assuming this isn't a cti or the branch isn't taken). */
210 #define SEM_NEXT_VPC(sem_arg, pc, len) ((sem_arg) + 1)
212 /* Update the instruction counter. */
213 #define PBB_UPDATE_INSN_COUNT(cpu,sc) \
214 (CPU_INSN_COUNT (cpu) += SEM_ARGBUF (sc) -> fields.chain.insn_count)
216 /* Do not append a `;' to invocations of this.
217 npc,br_type are for communication between the cti insn and cti-chain. */
218 #define SEM_BRANCH_INIT \
219 IADDR npc = 0; /* assign a value for -Wall */ \
220 SEM_BRANCH_TYPE br_type = SEM_BRANCH_UNTAKEN;
222 /* SEM_IN_SWITCH is defined at the top of the mainloop.c files
223 generated by genmloop.sh. It exists so generated semantic code needn't
224 care whether it's being put in a switch or in a function. */
226 #define SEM_BRANCH_FINI(pcvar) \
229 pbb_br_type = br_type; \
231 #else /* 1 semantic function per instruction */
232 #define SEM_BRANCH_FINI(pcvar) \
234 CPU_PBB_BR_NPC (current_cpu) = npc; \
235 CPU_PBB_BR_TYPE (current_cpu) = br_type; \
239 #define SEM_BRANCH_VIA_CACHE(cpu, sc, newval, pcvar) \
242 br_type = SEM_BRANCH_CACHEABLE; \
245 #define SEM_BRANCH_VIA_ADDR(cpu, sc, newval, pcvar) \
248 br_type = SEM_BRANCH_UNCACHEABLE; \
251 #define SEM_SKIP_COMPILE(cpu, sc, skip) \
253 SEM_ARGBUF (sc) -> skip_count = (skip); \
256 #define SEM_SKIP_INSN(cpu, sc, vpcvar) \
258 (vpcvar) += SEM_ARGBUF (sc) -> skip_count; \
261 #else /* ! WITH_SCACHE_PBB */
263 #define SEM_SEM_ARG(vpc, sc) (sc)
265 #define SEM_NEXT_VPC(sem_arg, pc, len) ((pc) + (len))
267 /* ??? May wish to move taken_p out of here and make it explicit. */
268 #define SEM_BRANCH_INIT \
271 #ifndef TARGET_SEM_BRANCH_FINI
272 #define TARGET_SEM_BRANCH_FINI(pcvar, taken_p)
274 #define SEM_BRANCH_FINI(pcvar) \
275 do { TARGET_SEM_BRANCH_FINI (pcvar, taken_p); } while (0)
277 #define SEM_BRANCH_VIA_CACHE(cpu, sc, newval, pcvar) \
279 (pcvar) = (newval); \
283 #define SEM_BRANCH_VIA_ADDR(cpu, sc, newval, pcvar) \
285 (pcvar) = (newval); \
289 #endif /* ! WITH_SCACHE_PBB */
291 #else /* ! WITH_SCACHE */
293 /* This is the "simple" engine case. */
295 #define CIA_ADDR(cia) (cia)
297 #define SEM_SEM_ARG(vpc, sc) (sc)
299 #define SEM_NEXT_VPC(sem_arg, pc, len) ((pc) + (len))
301 #define SEM_BRANCH_INIT \
304 #define SEM_BRANCH_VIA_CACHE(cpu, abuf, newval, pcvar) \
306 (pcvar) = (newval); \
310 #define SEM_BRANCH_VIA_ADDR(cpu, abuf, newval, pcvar) \
312 (pcvar) = (newval); \
316 /* Finish off branch insns.
317 The target must define TARGET_SEM_BRANCH_FINI.
318 ??? This can probably go away when define-execute is finished. */
319 #define SEM_BRANCH_FINI(pcvar, bool_attrs) \
320 do { TARGET_SEM_BRANCH_FINI ((pcvar), (bool_attrs), taken_p); } while (0)
322 /* Finish off non-branch insns.
323 The target must define TARGET_SEM_NBRANCH_FINI.
324 ??? This can probably go away when define-execute is finished. */
325 #define SEM_NBRANCH_FINI(pcvar, bool_attrs) \
326 do { TARGET_SEM_NBRANCH_FINI ((pcvar), (bool_attrs)); } while (0)
328 #endif /* ! WITH_SCACHE */
330 /* Instruction information. */
332 /* Sanity check, at most one of these may be true. */
333 #if WITH_PARALLEL_READ + WITH_PARALLEL_WRITE + WITH_PARALLEL_GENWRITE > 1
334 #error "At most one of WITH_PARALLEL_{READ,WRITE,GENWRITE} can be true."
337 /* Compile time computable instruction data. */
340 /* The instruction type (a number that identifies each insn over the
341 entire architecture). */
344 /* Index in IDESC table. */
347 /* Semantic format number. */
350 #if HAVE_PARALLEL_INSNS && ! WITH_PARALLEL_ONLY
351 /* Index in IDESC table of parallel handler. */
355 #if WITH_PARALLEL_READ
356 /* Index in IDESC table of read handler. */
360 #if WITH_PARALLEL_WRITE
361 /* Index in IDESC table of writeback handler. */
366 /* Entry in semantic function table.
367 This information is copied to the insn descriptor table at run-time. */
370 /* Index in IDESC table. */
373 /* Function to perform the semantics of the insn. */
377 /* Run-time computed instruction descriptor. */
380 #if WITH_SEM_SWITCH_FAST
384 /* nothing needed, switch's on `num' member */
387 SEMANTIC_FN
*sem_fast
;
390 #if WITH_SEM_SWITCH_FULL
394 /* nothing needed, switch's on `num' member */
397 SEMANTIC_FN
*sem_full
;
400 /* Parallel support. */
401 #if HAVE_PARALLEL_INSNS && (! WITH_PARALLEL_ONLY || (WITH_PARALLEL_ONLY && ! WITH_PARALLEL_GENWRITE))
402 /* Pointer to parallel handler if serial insn.
403 Pointer to readahead/writeback handler if parallel insn. */
404 struct idesc
*par_idesc
;
407 /* Instruction number (index in IDESC table, profile table).
408 Also used to switch on in non-gcc semantic switches. */
411 /* Semantic format id. */
414 /* instruction data (name, attributes, size, etc.) */
415 const CGEN_INSN
*idata
;
417 /* instruction attributes, copied from `idata' for speed */
418 const CGEN_INSN_ATTR_TYPE
*attrs
;
420 /* instruction length in bytes, copied from `idata' for speed */
423 /* profiling/modelling support */
424 const INSN_TIMING
*timing
;
427 /* Tracing/profiling. */
429 /* Return non-zero if a before/after handler is needed.
430 When tracing/profiling a selected range there's no need to slow
431 down simulation of the other insns (except to get more accurate data!).
433 ??? May wish to profile all insns if doing insn tracing, or to
434 get more accurate cycle data.
436 First test ANY_P so we avoid a potentially expensive HIT_P call
437 [if there are lots of address ranges]. */
439 #define PC_IN_TRACE_RANGE_P(cpu, pc) \
441 && ADDR_RANGE_HIT_P (TRACE_RANGE (CPU_TRACE_DATA (cpu)), (pc)))
442 #define PC_IN_PROFILE_RANGE_P(cpu, pc) \
443 (PROFILE_ANY_P (cpu) \
444 && ADDR_RANGE_HIT_P (PROFILE_RANGE (CPU_PROFILE_DATA (cpu)), (pc)))
446 #endif /* CGEN_ENGINE_H */
This page took 0.040784 seconds and 4 git commands to generate.