sim/common/cgen-par.c

   1 /* Simulator parallel routines for CGEN simulators (and maybe others).
   2    Copyright (C) 1999 Free Software Foundation, Inc.
   3    Contributed by Cygnus Solutions.
   4
   5 This file is part of the GNU instruction set simulator.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #include "sim-main.h"
  22 #include "cgen-mem.h"
  23 #include "cgen-par.h"
  24
  25 /* Functions required by the cgen interface.  These functions add various
  26    kinds of writes to the write queue.  */
  27 void sim_queue_bi_write (SIM_CPU *cpu, BI *target, BI value)
  28 {
  29   CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
  30   CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
  31   element->kind = CGEN_BI_WRITE;
  32   element->insn_address = CPU_PC_GET (cpu);
  33   element->kinds.bi_write.target = target;
  34   element->kinds.bi_write.value  = value;
  35 }
  36
  37 void sim_queue_qi_write (SIM_CPU *cpu, UQI *target, UQI value)
  38 {
  39   CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
  40   CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
  41   element->kind = CGEN_QI_WRITE;
  42   element->insn_address = CPU_PC_GET (cpu);
  43   element->kinds.qi_write.target = target;
  44   element->kinds.qi_write.value  = value;
  45 }
  46
  47 void sim_queue_si_write (SIM_CPU *cpu, SI *target, SI value)
  48 {
  49   CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
  50   CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
  51   element->kind = CGEN_SI_WRITE;
  52   element->insn_address = CPU_PC_GET (cpu);
  53   element->kinds.si_write.target = target;
  54   element->kinds.si_write.value  = value;
  55 }
  56
  57 void sim_queue_sf_write (SIM_CPU *cpu, SI *target, SF value)
  58 {
  59   CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
  60   CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
  61   element->kind = CGEN_SF_WRITE;
  62   element->insn_address = CPU_PC_GET (cpu);
  63   element->kinds.sf_write.target = target;
  64   element->kinds.sf_write.value  = value;
  65 }
  66
  67 void sim_queue_pc_write (SIM_CPU *cpu, USI value)
  68 {
  69   CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
  70   CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
  71   element->kind = CGEN_PC_WRITE;
  72   element->insn_address = CPU_PC_GET (cpu);
  73   element->kinds.pc_write.value = value;
  74 }
  75
  76 void sim_queue_fn_hi_write (
  77   SIM_CPU *cpu,
  78   void (*write_function)(SIM_CPU *cpu, UINT, UHI),
  79   UINT regno,
  80   UHI value
  81 )
  82 {
  83   CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
  84   CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
  85   element->kind = CGEN_FN_HI_WRITE;
  86   element->insn_address = CPU_PC_GET (cpu);
  87   element->kinds.fn_hi_write.function = write_function;
  88   element->kinds.fn_hi_write.regno = regno;
  89   element->kinds.fn_hi_write.value = value;
  90 }
  91
  92 void sim_queue_fn_si_write (
  93   SIM_CPU *cpu,
  94   void (*write_function)(SIM_CPU *cpu, UINT, USI),
  95   UINT regno,
  96   SI value
  97 )
  98 {
  99   CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
 100   CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
 101   element->kind = CGEN_FN_SI_WRITE;
 102   element->insn_address = CPU_PC_GET (cpu);
 103   element->kinds.fn_si_write.function = write_function;
 104   element->kinds.fn_si_write.regno = regno;
 105   element->kinds.fn_si_write.value = value;
 106 }
 107
 108 void sim_queue_fn_di_write (
 109   SIM_CPU *cpu,
 110   void (*write_function)(SIM_CPU *cpu, UINT, DI),
 111   UINT regno,
 112   DI value
 113 )
 114 {
 115   CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
 116   CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
 117   element->kind = CGEN_FN_DI_WRITE;
 118   element->insn_address = CPU_PC_GET (cpu);
 119   element->kinds.fn_di_write.function = write_function;
 120   element->kinds.fn_di_write.regno = regno;
 121   element->kinds.fn_di_write.value = value;
 122 }
 123
 124 void sim_queue_fn_df_write (
 125   SIM_CPU *cpu,
 126   void (*write_function)(SIM_CPU *cpu, UINT, DI),
 127   UINT regno,
 128   DF value
 129 )
 130 {
 131   CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
 132   CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
 133   element->kind = CGEN_FN_DF_WRITE;
 134   element->insn_address = CPU_PC_GET (cpu);
 135   element->kinds.fn_df_write.function = write_function;
 136   element->kinds.fn_df_write.regno = regno;
 137   element->kinds.fn_df_write.value = value;
 138 }
 139
 140 void sim_queue_fn_pc_write (
 141   SIM_CPU *cpu,
 142   void (*write_function)(SIM_CPU *cpu, USI),
 143   USI value
 144 )
 145 {
 146   CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
 147   CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
 148   element->kind = CGEN_FN_PC_WRITE;
 149   element->insn_address = CPU_PC_GET (cpu);
 150   element->kinds.fn_pc_write.function = write_function;
 151   element->kinds.fn_pc_write.value = value;
 152 }
 153
 154 void sim_queue_mem_qi_write (SIM_CPU *cpu, SI address, QI value)
 155 {
 156   CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
 157   CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
 158   element->kind = CGEN_MEM_QI_WRITE;
 159   element->insn_address = CPU_PC_GET (cpu);
 160   element->kinds.mem_qi_write.address = address;
 161   element->kinds.mem_qi_write.value   = value;
 162 }
 163
 164 void sim_queue_mem_hi_write (SIM_CPU *cpu, SI address, HI value)
 165 {
 166   CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
 167   CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
 168   element->kind = CGEN_MEM_HI_WRITE;
 169   element->insn_address = CPU_PC_GET (cpu);
 170   element->kinds.mem_hi_write.address = address;
 171   element->kinds.mem_hi_write.value   = value;
 172 }
 173
 174 void sim_queue_mem_si_write (SIM_CPU *cpu, SI address, SI value)
 175 {
 176   CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
 177   CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
 178   element->kind = CGEN_MEM_SI_WRITE;
 179   element->insn_address = CPU_PC_GET (cpu);
 180   element->kinds.mem_si_write.address = address;
 181   element->kinds.mem_si_write.value   = value;
 182 }
 183
 184 void sim_queue_mem_di_write (SIM_CPU *cpu, SI address, DI value)
 185 {
 186   CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
 187   CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
 188   element->kind = CGEN_MEM_DI_WRITE;
 189   element->insn_address = CPU_PC_GET (cpu);
 190   element->kinds.mem_di_write.address = address;
 191   element->kinds.mem_di_write.value   = value;
 192 }
 193
 194 void sim_queue_mem_df_write (SIM_CPU *cpu, SI address, DF value)
 195 {
 196   CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
 197   CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
 198   element->kind = CGEN_MEM_DF_WRITE;
 199   element->insn_address = CPU_PC_GET (cpu);
 200   element->kinds.mem_df_write.address = address;
 201   element->kinds.mem_df_write.value   = value;
 202 }
 203
 204 /* Execute a write stored on the write queue.  */
 205 void
 206 cgen_write_queue_element_execute (SIM_CPU *cpu, CGEN_WRITE_QUEUE_ELEMENT *item)
 207 {
 208   IADDR pc;
 209   switch (CGEN_WRITE_QUEUE_ELEMENT_KIND (item))
 210     {
 211     case CGEN_BI_WRITE:
 212       *item->kinds.bi_write.target = item->kinds.bi_write.value;
 213       break;
 214     case CGEN_QI_WRITE:
 215       *item->kinds.qi_write.target = item->kinds.qi_write.value;
 216       break;
 217     case CGEN_SI_WRITE:
 218       *item->kinds.si_write.target = item->kinds.si_write.value;
 219       break;
 220     case CGEN_SF_WRITE:
 221       *item->kinds.sf_write.target = item->kinds.sf_write.value;
 222       break;
 223     case CGEN_PC_WRITE:
 224       CPU_PC_SET (cpu, item->kinds.pc_write.value);
 225       break;
 226     case CGEN_FN_HI_WRITE:
 227       item->kinds.fn_hi_write.function (cpu,
 228                                         item->kinds.fn_hi_write.regno,
 229                                         item->kinds.fn_hi_write.value);
 230       break;
 231     case CGEN_FN_SI_WRITE:
 232       item->kinds.fn_si_write.function (cpu,
 233                                         item->kinds.fn_si_write.regno,
 234                                         item->kinds.fn_si_write.value);
 235       break;
 236     case CGEN_FN_DI_WRITE:
 237       item->kinds.fn_di_write.function (cpu,
 238                                         item->kinds.fn_di_write.regno,
 239                                         item->kinds.fn_di_write.value);
 240       break;
 241     case CGEN_FN_DF_WRITE:
 242       item->kinds.fn_df_write.function (cpu,
 243                                         item->kinds.fn_df_write.regno,
 244                                         item->kinds.fn_df_write.value);
 245       break;
 246     case CGEN_FN_PC_WRITE:
 247       item->kinds.fn_pc_write.function (cpu, item->kinds.fn_pc_write.value);
 248       break;
 249     case CGEN_MEM_QI_WRITE:
 250       pc = item->insn_address;
 251       SETMEMQI (cpu, pc, item->kinds.mem_qi_write.address,
 252                 item->kinds.mem_qi_write.value);
 253       break;
 254     case CGEN_MEM_HI_WRITE:
 255       pc = item->insn_address;
 256       SETMEMHI (cpu, pc, item->kinds.mem_hi_write.address,
 257                 item->kinds.mem_hi_write.value);
 258       break;
 259     case CGEN_MEM_SI_WRITE:
 260       pc = item->insn_address;
 261       SETMEMSI (cpu, pc, item->kinds.mem_si_write.address,
 262                 item->kinds.mem_si_write.value);
 263       break;
 264     case CGEN_MEM_DI_WRITE:
 265       pc = item->insn_address;
 266       SETMEMDI (cpu, pc, item->kinds.mem_di_write.address,
 267                 item->kinds.mem_di_write.value);
 268       break;
 269     case CGEN_MEM_DF_WRITE:
 270       pc = item->insn_address;
 271       SETMEMDF (cpu, pc, item->kinds.mem_df_write.address,
 272                 item->kinds.mem_df_write.value);
 273       break;
 274     default:
 275       break; /* FIXME: for now....print message later.  */
 276     }
 277 }
 278
 279 /* Utilities for the write queue.  */
 280 CGEN_WRITE_QUEUE_ELEMENT *
 281 cgen_write_queue_overflow (CGEN_WRITE_QUEUE *q)
 282 {
 283   abort (); /* FIXME: for now....print message later.  */
 284   return 0;
 285 }