1 /* Tracing support for CGEN-based simulators.
2 Copyright (C) 1996-2015 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
28 #define min(a,b) ((a) < (b) ? (a) : (b))
30 #ifndef SIZE_INSTRUCTION
31 #define SIZE_INSTRUCTION 16
35 #define SIZE_LOCATION 20
42 #ifndef SIZE_LINE_NUMBER
43 #define SIZE_LINE_NUMBER 4
46 #ifndef SIZE_CYCLE_COUNT
47 #define SIZE_CYCLE_COUNT 2
50 #ifndef SIZE_TOTAL_CYCLE_COUNT
51 #define SIZE_TOTAL_CYCLE_COUNT 9
54 #ifndef SIZE_TRACE_BUF
55 #define SIZE_TRACE_BUF 1024
58 /* Text is queued in TRACE_BUF because we want to output the insn's cycle
59 count first but that isn't known until after the insn has executed.
60 This also handles the queueing of trace results, TRACE_RESULT may be
61 called multiple times for one insn. */
62 static char trace_buf
[SIZE_TRACE_BUF
];
63 /* If NULL, output to stdout directly. */
66 /* Non-zero if this is the first insn in a set of parallel insns. */
67 static int first_insn_p
;
69 /* For communication between cgen_trace_insn and cgen_trace_result. */
70 static int printed_result_p
;
72 /* Insn and its extracted fields.
73 Set by cgen_trace_insn, used by cgen_trace_insn_fini.
74 ??? Move to SIM_CPU to support heterogeneous multi-cpu case. */
75 static const struct cgen_insn
*current_insn
;
76 static const struct argbuf
*current_abuf
;
79 cgen_trace_insn_init (SIM_CPU
*cpu
, int first_p
)
83 first_insn_p
= first_p
;
85 /* Set to NULL so cgen_trace_insn_fini can know if cgen_trace_insn was
92 cgen_trace_insn_fini (SIM_CPU
*cpu
, const struct argbuf
*abuf
, int last_p
)
94 SIM_DESC sd
= CPU_STATE (cpu
);
96 /* Was insn traced? It might not be if trace ranges are in effect. */
97 if (current_insn
== NULL
)
100 /* The first thing printed is current and total cycle counts. */
102 if (PROFILE_MODEL_P (cpu
)
103 && ARGBUF_PROFILE_P (current_abuf
))
105 unsigned long total
= PROFILE_MODEL_TOTAL_CYCLES (CPU_PROFILE_DATA (cpu
));
106 unsigned long this_insn
= PROFILE_MODEL_CUR_INSN_CYCLES (CPU_PROFILE_DATA (cpu
));
110 trace_printf (sd
, cpu
, "%-*ld %-*ld ",
111 SIZE_CYCLE_COUNT
, this_insn
,
112 SIZE_TOTAL_CYCLE_COUNT
, total
);
116 trace_printf (sd
, cpu
, "%-*ld %-*s ",
117 SIZE_CYCLE_COUNT
, this_insn
,
118 SIZE_TOTAL_CYCLE_COUNT
, "---");
122 /* Print the disassembled insn. */
124 trace_printf (sd
, cpu
, "%s", TRACE_PREFIX (CPU_TRACE_DATA (cpu
)));
127 /* Print insn results. */
129 const CGEN_OPINST
*opinst
= CGEN_INSN_OPERANDS (current_insn
);
134 int indices
[MAX_OPERAND_INSTANCES
];
136 /* Fetch the operands used by the insn. */
137 /* FIXME: Add fn ptr to CGEN_CPU_DESC. */
138 CGEN_SYM (get_insn_operands
) (CPU_CPU_DESC (cpu
), current_insn
,
139 0, CGEN_FIELDS_BITSIZE (&insn_fields
),
143 CGEN_OPINST_TYPE (opinst
) != CGEN_OPINST_END
;
146 if (CGEN_OPINST_TYPE (opinst
) == CGEN_OPINST_OUTPUT
)
147 cgen_trace_result (cpu
, current_insn
, opinst
, indices
[i
]);
153 /* Print anything else requested. */
156 trace_printf (sd
, cpu
, " %s\n", trace_buf
);
158 trace_printf (sd
, cpu
, "\n");
162 cgen_trace_insn (SIM_CPU
*cpu
, const struct cgen_insn
*opcode
,
163 const struct argbuf
*abuf
, IADDR pc
)
167 printed_result_p
= 0;
168 current_insn
= opcode
;
171 if (CGEN_INSN_VIRTUAL_P (opcode
))
173 trace_prefix (CPU_STATE (cpu
), cpu
, NULL_CIA
, pc
, 0,
174 NULL
, 0, CGEN_INSN_NAME (opcode
));
178 CPU_DISASSEMBLER (cpu
) (cpu
, opcode
, abuf
, pc
, disasm_buf
);
179 trace_prefix (CPU_STATE (cpu
), cpu
, NULL_CIA
, pc
, TRACE_LINENUM_P (cpu
),
182 first_insn_p
? " " : "|",
183 SIZE_INSTRUCTION
, disasm_buf
);
187 cgen_trace_extract (SIM_CPU
*cpu
, IADDR pc
, char *name
, ...)
190 int printed_one_p
= 0;
193 va_start (args
, name
);
195 trace_printf (CPU_STATE (cpu
), cpu
, "Extract: 0x%.*lx: %s ",
196 SIZE_PC
, (unsigned long) pc
, name
);
201 fmt
= va_arg (args
, char *);
206 trace_printf (CPU_STATE (cpu
), cpu
, ", ");
208 type
= va_arg (args
, int);
212 ival
= va_arg (args
, int);
213 trace_printf (CPU_STATE (cpu
), cpu
, fmt
, ival
);
222 trace_printf (CPU_STATE (cpu
), cpu
, "\n");
226 cgen_trace_result (SIM_CPU
*cpu
, char *name
, int type
, ...)
230 va_start (args
, type
);
231 if (printed_result_p
)
232 cgen_trace_printf (cpu
, ", ");
238 cgen_trace_printf (cpu
, "%s <- 0x%x", name
, va_arg (args
, int));
245 /* this is separated from previous line for sunos cc */
246 di
= va_arg (args
, DI
);
247 sim_fpu_64to (&f
, di
);
249 cgen_trace_printf (cpu
, "%s <- ", name
);
250 sim_fpu_printn_fpu (&f
, (sim_fpu_print_func
*) cgen_trace_printf
, 4, cpu
);
256 /* this is separated from previous line for sunos cc */
257 di
= va_arg (args
, DI
);
258 cgen_trace_printf (cpu
, "%s <- 0x%x%08x", name
,
259 GETHIDI(di
), GETLODI (di
));
264 printed_result_p
= 1;
268 /* Print trace output to BUFPTR if active, otherwise print normally.
269 This is only for tracing semantic code. */
272 cgen_trace_printf (SIM_CPU
*cpu
, char *fmt
, ...)
276 va_start (args
, fmt
);
280 if (TRACE_FILE (CPU_TRACE_DATA (cpu
)) == NULL
)
281 (* STATE_CALLBACK (CPU_STATE (cpu
))->evprintf_filtered
)
282 (STATE_CALLBACK (CPU_STATE (cpu
)), fmt
, args
);
284 vfprintf (TRACE_FILE (CPU_TRACE_DATA (cpu
)), fmt
, args
);
288 vsprintf (bufptr
, fmt
, args
);
289 bufptr
+= strlen (bufptr
);
290 /* ??? Need version of SIM_ASSERT that is always enabled. */
291 if (bufptr
- trace_buf
> SIZE_TRACE_BUF
)
298 /* Disassembly support. */
300 /* sprintf to a "stream" */
303 sim_disasm_sprintf (SFILE
*f
, const char *format
, ...)
308 va_start (args
, format
);
309 vsprintf (f
->current
, format
, args
);
310 f
->current
+= n
= strlen (f
->current
);
315 /* Memory read support for an opcodes disassembler. */
318 sim_disasm_read_memory (bfd_vma memaddr
, bfd_byte
*myaddr
, unsigned int length
,
319 struct disassemble_info
*info
)
321 SIM_CPU
*cpu
= (SIM_CPU
*) info
->application_data
;
322 SIM_DESC sd
= CPU_STATE (cpu
);
323 unsigned length_read
;
325 length_read
= sim_core_read_buffer (sd
, cpu
, read_map
, myaddr
, memaddr
,
327 if (length_read
!= length
)
332 /* Memory error support for an opcodes disassembler. */
335 sim_disasm_perror_memory (int status
, bfd_vma memaddr
,
336 struct disassemble_info
*info
)
340 info
->fprintf_func (info
->stream
, "Unknown error %d.", status
);
342 /* Actually, address between memaddr and memaddr + len was
344 info
->fprintf_func (info
->stream
,
345 "Address 0x%x is out of bounds.",
349 /* Disassemble using the CGEN opcode table.
350 ??? While executing an instruction, the insn has been decoded and all its
351 fields have been extracted. It is certainly possible to do the disassembly
352 with that data. This seems simpler, but maybe in the future the already
353 extracted fields will be used. */
356 sim_cgen_disassemble_insn (SIM_CPU
*cpu
, const CGEN_INSN
*insn
,
357 const ARGBUF
*abuf
, IADDR pc
, char *buf
)
360 unsigned int base_length
;
361 unsigned long insn_value
;
362 struct disassemble_info disasm_info
;
365 unsigned8 bytes
[CGEN_MAX_INSN_SIZE
];
366 unsigned16 shorts
[8];
369 SIM_DESC sd
= CPU_STATE (cpu
);
370 CGEN_CPU_DESC cd
= CPU_CPU_DESC (cpu
);
371 CGEN_EXTRACT_INFO ex_info
;
372 CGEN_FIELDS
*fields
= alloca (CGEN_CPU_SIZEOF_FIELDS (cd
));
373 int insn_bit_length
= CGEN_INSN_BITSIZE (insn
);
374 int insn_length
= insn_bit_length
/ 8;
376 sfile
.buffer
= sfile
.current
= buf
;
377 INIT_DISASSEMBLE_INFO (disasm_info
, (FILE *) &sfile
,
378 (fprintf_ftype
) sim_disasm_sprintf
);
380 (bfd_big_endian (STATE_PROG_BFD (sd
)) ? BFD_ENDIAN_BIG
381 : bfd_little_endian (STATE_PROG_BFD (sd
)) ? BFD_ENDIAN_LITTLE
382 : BFD_ENDIAN_UNKNOWN
);
384 length
= sim_core_read_buffer (sd
, cpu
, read_map
, &insn_buf
, pc
,
387 if (length
!= insn_length
)
389 sim_io_error (sd
, "unable to read address %x", pc
);
392 /* If the entire insn will fit into an integer, then do it. Otherwise, just
393 use the bits of the base_insn. */
394 if (insn_bit_length
<= 32)
395 base_length
= insn_bit_length
;
397 base_length
= min (cd
->base_insn_bitsize
, insn_bit_length
);
400 case 0 : return; /* fake insn, typically "compile" (aka "invalid") */
401 case 8 : insn_value
= insn_buf
.bytes
[0]; break;
402 case 16 : insn_value
= T2H_2 (insn_buf
.shorts
[0]); break;
403 case 32 : insn_value
= T2H_4 (insn_buf
.words
[0]); break;
407 disasm_info
.buffer_vma
= pc
;
408 disasm_info
.buffer
= insn_buf
.bytes
;
409 disasm_info
.buffer_length
= length
;
411 ex_info
.dis_info
= (PTR
) &disasm_info
;
412 ex_info
.valid
= (1 << length
) - 1;
413 ex_info
.insn_bytes
= insn_buf
.bytes
;
415 length
= (*CGEN_EXTRACT_FN (cd
, insn
)) (cd
, insn
, &ex_info
, insn_value
, fields
, pc
);
416 /* Result of extract fn is in bits. */
417 /* ??? This assumes that each instruction has a fixed length (and thus
418 for insns with multiple versions of variable lengths they would each
419 have their own table entry). */
420 if (length
== insn_bit_length
)
422 (*CGEN_PRINT_FN (cd
, insn
)) (cd
, &disasm_info
, insn
, fields
, pc
, length
);
426 /* This shouldn't happen, but aborting is too drastic. */
427 strcpy (buf
, "***unknown***");