sim/common/sim-base.h

   1 /* Simulator pseudo baseclass.
   2    Copyright (C) 1997-1998 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21
  22 /* Simulator state pseudo baseclass.
  23
  24    Each simulator is required to have the file ``sim-main.h''.  That
  25    file includes ``sim-basics.h'', defines the base type ``sim_cia''
  26    (the data type that contains complete current instruction address
  27    information), include ``sim-base.h'':
  28
  29      #include "sim-basics.h"
  30      typedef address_word sim_cia;
  31      /-* If `sim_cia' is not an integral value (e.g. a struct), define
  32          CIA_ADDR to return the integral value.  *-/
  33      /-* #define CIA_ADDR(cia) (...) *-/
  34      #include "sim-base.h"
  35
  36    finally, two data types `struct _sim_cpu' and `struct sim_state'
  37    are defined:
  38
  39      struct _sim_cpu {
  40         ... simulator specific members ...
  41         sim_cpu_base base;
  42      };
  43
  44      struct sim_state {
  45        sim_cpu cpu[MAX_NR_PROCESSORS];
  46      #if (WITH_SMP)
  47      #define STATE_CPU(sd,n) (&(sd)->cpu[n])
  48      #else
  49      #define STATE_CPU(sd,n) (&(sd)->cpu[0])
  50      #endif
  51        ... simulator specific members ...
  52        sim_state_base base;
  53      };
  54
  55    Note that `base' appears last.  This makes `base.magic' appear last
  56    in the entire struct and helps catch miscompilation errors. */
  57
  58
  59 #ifndef SIM_BASE_H
  60 #define SIM_BASE_H
  61
  62 /* Pre-declare certain types. */
  63
  64 /* typedef <target-dependant> sim_cia; */
  65 #ifndef NULL_CIA
  66 #define NULL_CIA ((sim_cia) 0)
  67 #endif
  68 /* Return the current instruction address as a number.
  69    Some targets treat the current instruction address as a struct
  70    (e.g. for delay slot handling).  */
  71 #ifndef CIA_ADDR
  72 #define CIA_ADDR(cia) (cia)
  73 #endif
  74 #ifndef INVALID_INSTRUCTION_ADDRESS
  75 #define INVALID_INSTRUCTION_ADDRESS ((address_word)0 - 1)
  76 #endif
  77
  78 typedef struct _sim_cpu sim_cpu;
  79
  80 #include "sim-module.h"
  81
  82 #include "sim-trace.h"
  83 #include "sim-core.h"
  84 #include "sim-events.h"
  85 #include "sim-profile.h"
  86 #ifdef SIM_HAVE_MODEL
  87 #include "sim-model.h"
  88 #endif
  89 #include "sim-io.h"
  90 #include "sim-engine.h"
  91 #include "sim-watch.h"
  92 #include "sim-memopt.h"
  93 #ifdef SIM_HAVE_BREAKPOINTS
  94 #include "sim-break.h"
  95 #endif
  96
  97 /* Global pointer to current state while sim_resume is running.
  98    On a machine with lots of registers, it might be possible to reserve
  99    one of them for current_state.  However on a machine with few registers
 100    current_state can't permanently live in one and indirecting through it
 101    will be slower [in which case one can have sim_resume set globals from
 102    current_state for faster access].
 103    If CURRENT_STATE_REG is defined, it means current_state is living in
 104    a global register.  */
 105
 106
 107 #ifdef CURRENT_STATE_REG
 108 /* FIXME: wip */
 109 #else
 110 extern struct sim_state *current_state;
 111 #endif
 112
 113
 114 /* The simulator may provide different (and faster) definition.  */
 115 #ifndef CURRENT_STATE
 116 #define CURRENT_STATE current_state
 117 #endif
 118
 119
 120 typedef struct {
 121
 122   /* Simulator's argv[0].  */
 123   const char *my_name;
 124 #define STATE_MY_NAME(sd) ((sd)->base.my_name)
 125
 126   /* Who opened the simulator.  */
 127   SIM_OPEN_KIND open_kind;
 128 #define STATE_OPEN_KIND(sd) ((sd)->base.open_kind)
 129
 130   /* The host callbacks.  */
 131   struct host_callback_struct *callback;
 132 #define STATE_CALLBACK(sd) ((sd)->base.callback)
 133
 134   /* The type of simulation environment (user/operating).  */
 135   enum sim_environment environment;
 136 #define STATE_ENVIRONMENT(sd) ((sd)->base.environment)
 137
 138 #if 0 /* FIXME: Not ready yet.  */
 139   /* Stuff defined in sim-config.h.  */
 140   struct sim_config config;
 141 #define STATE_CONFIG(sd) ((sd)->base.config)
 142 #endif
 143
 144   /* List of installed module `init' handlers.  */
 145   struct module_list *modules;
 146 #define STATE_MODULES(sd) ((sd)->base.modules)
 147
 148   /* Supported options.  */
 149   struct option_list *options;
 150 #define STATE_OPTIONS(sd) ((sd)->base.options)
 151
 152   /* Non-zero if -v specified.  */
 153   int verbose_p;
 154 #define STATE_VERBOSE_P(sd) ((sd)->base.verbose_p)
 155
 156   /* Non cpu-specific trace data.  See sim-trace.h.  */
 157   TRACE_DATA trace_data;
 158 #define STATE_TRACE_DATA(sd) (& (sd)->base.trace_data)
 159
 160   /* If non NULL, the BFD architecture specified on the command line */
 161   const struct bfd_arch_info *architecture;
 162 #define STATE_ARCHITECTURE(sd) ((sd)->base.architecture)
 163
 164   /* If non NULL, the bfd target specified on the command line */
 165   const char *target;
 166 #define STATE_TARGET(sd) ((sd)->base.target)
 167
 168   /* In standalone simulator, this is the program's arguments passed
 169      on the command line.  */
 170   char **prog_argv;
 171 #define STATE_PROG_ARGV(sd) ((sd)->base.prog_argv)
 172
 173   /* The program's bfd.  */
 174   struct _bfd *prog_bfd;
 175 #define STATE_PROG_BFD(sd) ((sd)->base.prog_bfd)
 176
 177   /* Symbol table for prog_bfd */
 178   struct symbol_cache_entry **prog_syms;
 179 #define STATE_PROG_SYMS(sd) ((sd)->base.prog_syms)
 180
 181   /* The program's text section.  */
 182   struct sec *text_section;
 183   /* Starting and ending text section addresses from the bfd.  */
 184   SIM_ADDR text_start, text_end;
 185 #define STATE_TEXT_SECTION(sd) ((sd)->base.text_section)
 186 #define STATE_TEXT_START(sd) ((sd)->base.text_start)
 187 #define STATE_TEXT_END(sd) ((sd)->base.text_end)
 188
 189   /* Start address, set when the program is loaded from the bfd.  */
 190   SIM_ADDR start_addr;
 191 #define STATE_START_ADDR(sd) ((sd)->base.start_addr)
 192
 193   /* Size of the simulator's cache, if any.
 194      This is not the target's cache.  It is the cache the simulator uses
 195      to process instructions.  */
 196   unsigned int scache_size;
 197 #define STATE_SCACHE_SIZE(sd) ((sd)->base.scache_size)
 198
 199   /* FIXME: Move to top level sim_state struct (as some struct)?  */
 200 #ifdef SIM_HAVE_FLATMEM
 201   unsigned int mem_size;
 202 #define STATE_MEM_SIZE(sd) ((sd)->base.mem_size)
 203   unsigned int mem_base;
 204 #define STATE_MEM_BASE(sd) ((sd)->base.mem_base)
 205   unsigned char *memory;
 206 #define STATE_MEMORY(sd) ((sd)->base.memory)
 207 #endif
 208
 209   /* core memory bus */
 210 #define STATE_CORE(sd) (&(sd)->base.core)
 211   sim_core core;
 212
 213   /* Record of memory sections added via the memory-options interface.  */
 214 #define STATE_MEMOPT(sd) ((sd)->base.memopt)
 215   sim_memopt *memopt;
 216
 217   /* event handler */
 218 #define STATE_EVENTS(sd) (&(sd)->base.events)
 219   sim_events events;
 220
 221   /* generic halt/resume engine */
 222   sim_engine engine;
 223 #define STATE_ENGINE(sd) (&(sd)->base.engine)
 224
 225   /* generic watchpoint support */
 226   sim_watchpoints watchpoints;
 227 #define STATE_WATCHPOINTS(sd) (&(sd)->base.watchpoints)
 228
 229   /* Pointer to list of breakpoints */
 230   struct sim_breakpoint *breakpoints;
 231 #define STATE_BREAKPOINTS(sd) ((sd)->base.breakpoints)
 232
 233   /* Marker for those wanting to do sanity checks.
 234      This should remain the last member of this struct to help catch
 235      miscompilation errors.  */
 236   int magic;
 237 #define SIM_MAGIC_NUMBER 0x4242
 238 #define STATE_MAGIC(sd) ((sd)->base.magic)
 239 } sim_state_base;
 240
 241
 242 /* Pseudo baseclass for each cpu.  */
 243
 244 typedef struct {
 245
 246   /* Backlink to main state struct.  */
 247   SIM_DESC state;
 248 #define CPU_STATE(cpu) ((cpu)->base.state)
 249
 250   /* Processor index within the SD_DESC */
 251   int index;
 252 #define CPU_INDEX(cpu) ((cpu)->base.index)
 253
 254   /* The name of the cpu.  */
 255   const char *name;
 256 #define CPU_NAME(cpu) ((cpu)->base.name)
 257
 258   /* Options specific to this cpu.  */
 259   struct option_list *options;
 260 #define CPU_OPTIONS(cpu) ((cpu)->base.options)
 261
 262   /* Processor specific core data */
 263   sim_cpu_core core;
 264 #define CPU_CORE(cpu) (& (cpu)->base.core)
 265
 266   /* Trace data.  See sim-trace.h.  */
 267   TRACE_DATA trace_data;
 268 #define CPU_TRACE_DATA(cpu) (& (cpu)->base.trace_data)
 269
 270   /* Maximum number of debuggable entities.
 271      This debugging is not intended for normal use.
 272      It is only enabled when the simulator is configured with --with-debug
 273      which shouldn't normally be specified.  */
 274 #ifndef MAX_DEBUG_VALUES
 275 #define MAX_DEBUG_VALUES 4
 276 #endif
 277
 278   /* Boolean array of specified debugging flags.  */
 279   char debug_flags[MAX_DEBUG_VALUES];
 280 #define CPU_DEBUG_FLAGS(cpu) ((cpu)->base.debug_flags)
 281   /* Standard values.  */
 282 #define DEBUG_INSN_IDX 0
 283 #define DEBUG_NEXT_IDX 2 /* simulator specific debug bits begin here */
 284
 285   /* Debugging output goes to this or stderr if NULL.
 286      We can't store `stderr' here as stderr goes through a callback.  */
 287   FILE *debug_file;
 288 #define CPU_DEBUG_FILE(cpu) ((cpu)->base.debug_file)
 289
 290   /* Profile data.  See sim-profile.h.  */
 291   PROFILE_DATA profile_data;
 292 #define CPU_PROFILE_DATA(cpu) (& (cpu)->base.profile_data)
 293
 294 #ifdef SIM_HAVE_MODEL
 295   /* Machine tables for this cpu.  See sim-model.h.  */
 296   const MACH *mach;
 297 #define CPU_MACH(cpu) ((cpu)->base.mach)
 298   /* The selected model.  */
 299   const MODEL *model;
 300 #define CPU_MODEL(cpu) ((cpu)->base.model)
 301 #endif
 302
 303 } sim_cpu_base;
 304
 305
 306 /* Functions for allocating/freeing a sim_state.  */
 307 SIM_DESC sim_state_alloc PARAMS ((SIM_OPEN_KIND kind, host_callback *callback));
 308 void sim_state_free PARAMS ((SIM_DESC));
 309
 310 /* Return a pointer to the cpu data for CPU_NAME, or NULL if not found.  */
 311 sim_cpu *sim_cpu_lookup (SIM_DESC sd, const char *cpu_name);
 312
 313
 314 #endif /* SIM_BASE_H */