sim/cr16/interp.c

   1 /* Simulation code for the CR16 processor.
   2    Copyright (C) 2008-2015 Free Software Foundation, Inc.
   3    Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com>
   4
   5    This file is part of GDB, the GNU debugger.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program. If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #include "config.h"
  21 #include <inttypes.h>
  22 #include <signal.h>
  23 #include <stdlib.h>
  24 #include <string.h>
  25 #include "bfd.h"
  26 #include "gdb/callback.h"
  27 #include "gdb/remote-sim.h"
  28
  29 #include "sim-main.h"
  30 #include "sim-options.h"
  31
  32 #include "gdb/sim-cr16.h"
  33 #include "gdb/signals.h"
  34 #include "opcode/cr16.h"
  35
  36 int cr16_debug;
  37
  38 host_callback *cr16_callback;
  39
  40 uint32 OP[4];
  41 uint32 sign_flag;
  42
  43 static struct hash_entry *lookup_hash (uint64 ins, int size);
  44 static void get_operands (operand_desc *s, uint64 mcode, int isize, int nops);
  45 static INLINE uint8 *map_memory (unsigned phys_addr);
  46
  47 #define MAX_HASH  16
  48
  49 struct hash_entry
  50 {
  51   struct hash_entry *next;
  52   uint32 opcode;
  53   uint32 mask;
  54   int format;
  55   int size;
  56   struct simops *ops;
  57 };
  58
  59 struct hash_entry hash_table[MAX_HASH+1];
  60
  61 INLINE static long
  62 hash(unsigned long long insn, int format)
  63 {
  64   unsigned int i = 4, tmp;
  65   if (format)
  66     {
  67       while ((insn >> i) != 0) i +=4;
  68
  69       return ((insn >> (i-4)) & 0xf); /* Use last 4 bits as hask key.  */
  70     }
  71   return ((insn & 0xF)); /* Use last 4 bits as hask key.  */
  72 }
  73
  74
  75 INLINE static struct hash_entry *
  76 lookup_hash (uint64 ins, int size)
  77 {
  78   uint32 mask;
  79   struct hash_entry *h;
  80
  81   h = &hash_table[hash(ins,1)];
  82
  83
  84   mask = (((1 << (32 - h->mask)) -1) << h->mask);
  85
  86  /* Adjuest mask for branch with 2 word instructions.  */
  87   if ((h->ops->mnimonic != NULL) &&
  88       ((streq(h->ops->mnimonic,"b") && h->size == 2)))
  89     mask = 0xff0f0000;
  90
  91
  92   while ((ins & mask) != (BIN(h->opcode, h->mask)))
  93     {
  94       if (h->next == NULL)
  95         {
  96           State.exception = SIGILL;
  97           State.pc_changed = 1; /* Don't increment the PC. */
  98           return NULL;
  99         }
 100       h = h->next;
 101
 102       mask = (((1 << (32 - h->mask)) -1) << h->mask);
 103      /* Adjuest mask for branch with 2 word instructions.  */
 104      if ((streq(h->ops->mnimonic,"b")) && h->size == 2)
 105        mask = 0xff0f0000;
 106
 107      }
 108    return (h);
 109 }
 110
 111 INLINE static void
 112 get_operands (operand_desc *s, uint64 ins, int isize, int nops)
 113 {
 114   uint32 i, opn = 0, start_bit = 0, op_type = 0;
 115   int32 op_size = 0, mask = 0;
 116
 117   if (isize == 1) /* Trunkcate the extra 16 bits of INS.  */
 118     ins = ins >> 16;
 119
 120   for (i=0; i < 4; ++i,++opn)
 121     {
 122       if (s[opn].op_type == dummy) break;
 123
 124       op_type = s[opn].op_type;
 125       start_bit = s[opn].shift;
 126       op_size = cr16_optab[op_type].bit_size;
 127
 128       switch (op_type)
 129         {
 130           case imm3: case imm4: case imm5: case imm6:
 131             {
 132              if (isize == 1)
 133                OP[i] = ((ins >> 4) & ((1 << op_size) -1));
 134              else
 135                OP[i] = ((ins >> (32 - start_bit)) & ((1 << op_size) -1));
 136
 137              if (OP[i] & ((long)1 << (op_size -1)))
 138                {
 139                  sign_flag = 1;
 140                  OP[i] = ~(OP[i]) + 1;
 141                }
 142              OP[i] = (unsigned long int)(OP[i] & (((long)1 << op_size) -1));
 143             }
 144             break;
 145
 146           case uimm3: case uimm3_1: case uimm4_1:
 147              switch (isize)
 148                {
 149               case 1:
 150                OP[i] = ((ins >> 4) & ((1 << op_size) -1)); break;
 151               case 2:
 152                OP[i] = ((ins >> (32 - start_bit)) & ((1 << op_size) -1));break;
 153               default: /* for case 3.  */
 154                OP[i] = ((ins >> (16 + start_bit)) & ((1 << op_size) -1)); break;
 155                break;
 156                }
 157             break;
 158
 159           case uimm4:
 160             switch (isize)
 161               {
 162               case 1:
 163                  if (start_bit == 20)
 164                    OP[i] = ((ins >> 4) & ((1 << op_size) -1));
 165                  else
 166                    OP[i] = (ins & ((1 << op_size) -1));
 167                  break;
 168               case 2:
 169                  OP[i] = ((ins >> start_bit) & ((1 << op_size) -1));
 170                  break;
 171               case 3:
 172                  OP[i] = ((ins >> (start_bit + 16)) & ((1 << op_size) -1));
 173                  break;
 174               default:
 175                  OP[i] = ((ins >> start_bit) & ((1 << op_size) -1));
 176                  break;
 177               }
 178             break;
 179
 180           case imm16: case uimm16:
 181             OP[i] = ins & 0xFFFF;
 182             break;
 183
 184           case uimm20: case imm20:
 185             OP[i] = ins & (((long)1 << op_size) - 1);
 186             break;
 187
 188           case imm32: case uimm32:
 189             OP[i] = ins & 0xFFFFFFFF;
 190             break;
 191
 192           case uimm5: break; /*NOT USED.  */
 193             OP[i] = ins & ((1 << op_size) - 1); break;
 194
 195           case disps5:
 196             OP[i] = (ins >> 4) & ((1 << 4) - 1);
 197             OP[i] = (OP[i] * 2) + 2;
 198             if (OP[i] & ((long)1 << 5))
 199               {
 200                 sign_flag = 1;
 201                 OP[i] = ~(OP[i]) + 1;
 202                 OP[i] = (unsigned long int)(OP[i] & 0x1F);
 203               }
 204             break;
 205
 206           case dispe9:
 207             OP[i] = ((((ins >> 8) & 0xf) << 4) | (ins & 0xf));
 208             OP[i] <<= 1;
 209             if (OP[i] & ((long)1 << 8))
 210               {
 211                 sign_flag = 1;
 212                 OP[i] = ~(OP[i]) + 1;
 213                 OP[i] = (unsigned long int)(OP[i] & 0xFF);
 214               }
 215             break;
 216
 217           case disps17:
 218             OP[i] = (ins & 0xFFFF);
 219             if (OP[i] & 1)
 220               {
 221                 OP[i] = (OP[i] & 0xFFFE);
 222                 sign_flag = 1;
 223                 OP[i] = ~(OP[i]) + 1;
 224                 OP[i] = (unsigned long int)(OP[i] & 0xFFFF);
 225               }
 226             break;
 227
 228           case disps25:
 229             if (isize == 2)
 230               OP[i] = (ins & 0xFFFFFF);
 231             else
 232               OP[i] = (ins & 0xFFFF) | (((ins >> 24) & 0xf) << 16) |
 233                       (((ins >> 16) & 0xf) << 20);
 234
 235             if (OP[i] & 1)
 236               {
 237                 OP[i] = (OP[i] & 0xFFFFFE);
 238                 sign_flag = 1;
 239                 OP[i] = ~(OP[i]) + 1;
 240                 OP[i] = (unsigned long int)(OP[i] & 0xFFFFFF);
 241               }
 242             break;
 243
 244           case abs20:
 245             if (isize == 3)
 246               OP[i] = (ins) & 0xFFFFF;
 247             else
 248               OP[i] = (ins >> start_bit) & 0xFFFFF;
 249             break;
 250           case abs24:
 251             if (isize == 3)
 252               OP[i] = ((ins & 0xFFFF) | (((ins >> 16) & 0xf) << 20)
 253                        | (((ins >> 24) & 0xf) << 16));
 254             else
 255               OP[i] = (ins >> 16) & 0xFFFFFF;
 256             break;
 257
 258           case rra:
 259           case rbase: break; /* NOT USED.  */
 260           case rbase_disps20:  case rbase_dispe20:
 261           case rpbase_disps20: case rpindex_disps20:
 262             OP[i] = ((((ins >> 24)&0xf) << 16)|((ins) & 0xFFFF));
 263             OP[++i] = (ins >> 16) & 0xF;     /* get 4 bit for reg.  */
 264             break;
 265           case rpbase_disps0:
 266             OP[i] = 0;                       /* 4 bit disp const.  */
 267             OP[++i] = (ins) & 0xF;           /* get 4 bit for reg.  */
 268             break;
 269           case rpbase_dispe4:
 270             OP[i] = ((ins >> 8) & 0xF) * 2;  /* 4 bit disp const.   */
 271             OP[++i] = (ins) & 0xF;           /* get 4 bit for reg.  */
 272             break;
 273           case rpbase_disps4:
 274             OP[i] = ((ins >> 8) & 0xF);      /* 4 bit disp const.  */
 275             OP[++i] = (ins) & 0xF;           /* get 4 bit for reg.  */
 276             break;
 277           case rpbase_disps16:
 278             OP[i] = (ins) & 0xFFFF;
 279             OP[++i] = (ins >> 16) & 0xF;     /* get 4 bit for reg.  */
 280             break;
 281           case rpindex_disps0:
 282             OP[i] = 0;
 283             OP[++i] = (ins >> 4) & 0xF;      /* get 4 bit for reg.  */
 284             OP[++i] = (ins >> 8) & 0x1;      /* get 1 bit for index-reg.  */
 285             break;
 286           case rpindex_disps14:
 287             OP[i] = (ins) & 0x3FFF;
 288             OP[++i] = (ins >> 14) & 0x1;     /* get 1 bit for index-reg.  */
 289             OP[++i] = (ins >> 16) & 0xF;     /* get 4 bit for reg.  */
 290           case rindex7_abs20:
 291           case rindex8_abs20:
 292             OP[i] = (ins) & 0xFFFFF;
 293             OP[++i] = (ins >> 24) & 0x1;     /* get 1 bit for index-reg.  */
 294             OP[++i] = (ins >> 20) & 0xF;     /* get 4 bit for reg.  */
 295             break;
 296           case regr: case regp: case pregr: case pregrp:
 297               switch(isize)
 298                 {
 299                   case 1:
 300                     if (start_bit == 20) OP[i] = (ins >> 4) & 0xF;
 301                     else if (start_bit == 16) OP[i] = ins & 0xF;
 302                     break;
 303                   case 2: OP[i] = (ins >>  start_bit) & 0xF; break;
 304                   case 3: OP[i] = (ins >> (start_bit + 16)) & 0xF; break;
 305                 }
 306                break;
 307           case cc:
 308             {
 309               if (isize == 1) OP[i] = (ins >> 4) & 0xF;
 310               else if (isize == 2)  OP[i] = (ins >> start_bit)  & 0xF;
 311               else  OP[i] = (ins >> (start_bit + 16)) & 0xF;
 312               break;
 313             }
 314           default: break;
 315         }
 316
 317       /* For ESC on uimm4_1 operand.  */
 318       if (op_type == uimm4_1)
 319         if (OP[i] == 9)
 320            OP[i] = -1;
 321
 322       /* For increment by 1.  */
 323       if ((op_type == pregr) || (op_type == pregrp))
 324           OP[i] += 1;
 325    }
 326   /* FIXME: for tracing, update values that need to be updated each
 327             instruction decode cycle */
 328   State.trace.psw = PSR;
 329 }
 330
 331 static int
 332 do_run (SIM_DESC sd, uint64 mcode)
 333 {
 334   host_callback *cr16_callback = STATE_CALLBACK (sd);
 335   struct simops *s= Simops;
 336   struct hash_entry *h;
 337   char func[12]="\0";
 338   uint8 *iaddr;
 339 #ifdef DEBUG
 340   if ((cr16_debug & DEBUG_INSTRUCTION) != 0)
 341     (*cr16_callback->printf_filtered) (cr16_callback, "do_long 0x%x\n", mcode);
 342 #endif
 343
 344    h =  lookup_hash(mcode, 1);
 345
 346   if ((h == NULL) || (h->opcode == 0))
 347     return 0;
 348
 349    if (h->size == 3)
 350     {
 351       iaddr = imem_addr ((uint32)PC + 2);
 352        mcode = (mcode << 16) | get_longword( iaddr );
 353     }
 354
 355   /* Re-set OP list.  */
 356   OP[0] = OP[1] = OP[2] = OP[3] = sign_flag = 0;
 357
 358   /* for push/pop/pushrtn with RA instructions. */
 359   if ((h->format & REG_LIST) && (mcode & 0x800000))
 360     OP[2] = 1; /* Set 1 for RA operand.  */
 361
 362   /* numops == 0 means, no operands.  */
 363   if (((h->ops) != NULL) && (((h->ops)->numops) != 0))
 364     get_operands ((h->ops)->operands, mcode, h->size, (h->ops)->numops);
 365
 366   //State.ins_type = h->flags;
 367
 368   (h->ops->func)();
 369
 370   return h->size;
 371 }
 372
 373 static void
 374 sim_size (int power)
 375 {
 376   int i;
 377   for (i = 0; i < IMEM_SEGMENTS; i++)
 378     {
 379       if (State.mem.insn[i])
 380         free (State.mem.insn[i]);
 381     }
 382   for (i = 0; i < DMEM_SEGMENTS; i++)
 383     {
 384       if (State.mem.data[i])
 385         free (State.mem.data[i]);
 386     }
 387   for (i = 0; i < UMEM_SEGMENTS; i++)
 388     {
 389       if (State.mem.unif[i])
 390         free (State.mem.unif[i]);
 391     }
 392   /* Always allocate dmem segment 0.  This contains the IMAP and DMAP
 393      registers. */
 394   State.mem.data[0] = calloc (1, SEGMENT_SIZE);
 395 }
 396
 397 /* For tracing - leave info on last access around. */
 398 static char *last_segname = "invalid";
 399 static char *last_from = "invalid";
 400 static char *last_to = "invalid";
 401
 402 enum
 403   {
 404     IMAP0_OFFSET = 0xff00,
 405     DMAP0_OFFSET = 0xff08,
 406     DMAP2_SHADDOW = 0xff04,
 407     DMAP2_OFFSET = 0xff0c
 408   };
 409
 410 static unsigned long
 411 dmap_register (void *regcache, int reg_nr)
 412 {
 413   uint8 *raw = map_memory (SIM_CR16_MEMORY_DATA
 414                            + DMAP0_OFFSET + 2 * reg_nr);
 415   return READ_16 (raw);
 416 }
 417
 418 static unsigned long
 419 imap_register (void *regcache, int reg_nr)
 420 {
 421   uint8 *raw = map_memory (SIM_CR16_MEMORY_DATA
 422                            + IMAP0_OFFSET + 2 * reg_nr);
 423   return READ_16 (raw);
 424 }
 425
 426 /* Given a virtual address in the DMAP address space, translate it
 427    into a physical address. */
 428
 429 static unsigned long
 430 sim_cr16_translate_dmap_addr (unsigned long offset,
 431                               int nr_bytes,
 432                               unsigned long *phys,
 433                               void *regcache,
 434                               unsigned long (*dmap_register) (void *regcache,
 435                                                               int reg_nr))
 436 {
 437   short map;
 438   int regno;
 439   last_from = "logical-data";
 440   if (offset >= DMAP_BLOCK_SIZE * SIM_CR16_NR_DMAP_REGS)
 441     {
 442       /* Logical address out side of data segments, not supported */
 443       return 0;
 444     }
 445   regno = (offset / DMAP_BLOCK_SIZE);
 446   offset = (offset % DMAP_BLOCK_SIZE);
 447
 448 #if 1
 449   if ((offset % DMAP_BLOCK_SIZE) + nr_bytes > DMAP_BLOCK_SIZE)
 450     {
 451       /* Don't cross a BLOCK boundary */
 452       nr_bytes = DMAP_BLOCK_SIZE - (offset % DMAP_BLOCK_SIZE);
 453     }
 454   map = dmap_register (regcache, regno);
 455   if (regno == 3)
 456     {
 457       /* Always maps to data memory */
 458       int iospi = (offset / 0x1000) % 4;
 459       int iosp = (map >> (4 * (3 - iospi))) % 0x10;
 460       last_to = "io-space";
 461       *phys = (SIM_CR16_MEMORY_DATA + (iosp * 0x10000) + 0xc000 + offset);
 462     }
 463   else
 464     {
 465       int sp = ((map & 0x3000) >> 12);
 466       int segno = (map & 0x3ff);
 467       switch (sp)
 468         {
 469         case 0: /* 00: Unified memory */
 470           *phys = SIM_CR16_MEMORY_UNIFIED + (segno * DMAP_BLOCK_SIZE) + offset;
 471           last_to = "unified";
 472           break;
 473         case 1: /* 01: Instruction Memory */
 474           *phys = SIM_CR16_MEMORY_INSN + (segno * DMAP_BLOCK_SIZE) + offset;
 475           last_to = "chip-insn";
 476           break;
 477         case 2: /* 10: Internal data memory */
 478           *phys = SIM_CR16_MEMORY_DATA + (segno << 16) + (regno * DMAP_BLOCK_SIZE) + offset;
 479           last_to = "chip-data";
 480           break;
 481         case 3: /* 11: Reserved */
 482           return 0;
 483         }
 484     }
 485 #endif
 486   return nr_bytes;
 487 }
 488
 489 /* Given a virtual address in the IMAP address space, translate it
 490    into a physical address. */
 491
 492 static unsigned long
 493 sim_cr16_translate_imap_addr (unsigned long offset,
 494                               int nr_bytes,
 495                               unsigned long *phys,
 496                               void *regcache,
 497                               unsigned long (*imap_register) (void *regcache,
 498                                                               int reg_nr))
 499 {
 500   short map;
 501   int regno;
 502   int sp;
 503   int segno;
 504   last_from = "logical-insn";
 505   if (offset >= (IMAP_BLOCK_SIZE * SIM_CR16_NR_IMAP_REGS))
 506     {
 507       /* Logical address outside of IMAP segments, not supported */
 508       return 0;
 509     }
 510   regno = (offset / IMAP_BLOCK_SIZE);
 511   offset = (offset % IMAP_BLOCK_SIZE);
 512   if (offset + nr_bytes > IMAP_BLOCK_SIZE)
 513     {
 514       /* Don't cross a BLOCK boundary */
 515       nr_bytes = IMAP_BLOCK_SIZE - offset;
 516     }
 517   map = imap_register (regcache, regno);
 518   sp = (map & 0x3000) >> 12;
 519   segno = (map & 0x007f);
 520   switch (sp)
 521     {
 522     case 0: /* 00: unified memory */
 523       *phys = SIM_CR16_MEMORY_UNIFIED + (segno << 17) + offset;
 524       last_to = "unified";
 525       break;
 526     case 1: /* 01: instruction memory */
 527       *phys = SIM_CR16_MEMORY_INSN + (IMAP_BLOCK_SIZE * regno) + offset;
 528       last_to = "chip-insn";
 529       break;
 530     case 2: /*10*/
 531       /* Reserved. */
 532       return 0;
 533     case 3: /* 11: for testing  - instruction memory */
 534       offset = (offset % 0x800);
 535       *phys = SIM_CR16_MEMORY_INSN + offset;
 536       if (offset + nr_bytes > 0x800)
 537         /* don't cross VM boundary */
 538         nr_bytes = 0x800 - offset;
 539       last_to = "test-insn";
 540       break;
 541     }
 542   return nr_bytes;
 543 }
 544
 545 static unsigned long
 546 sim_cr16_translate_addr (unsigned long memaddr, int nr_bytes,
 547                          unsigned long *targ_addr, void *regcache,
 548                          unsigned long (*dmap_register) (void *regcache,
 549                                                          int reg_nr),
 550                          unsigned long (*imap_register) (void *regcache,
 551                                                          int reg_nr))
 552 {
 553   unsigned long phys;
 554   unsigned long seg;
 555   unsigned long off;
 556
 557   last_from = "unknown";
 558   last_to = "unknown";
 559
 560   seg = (memaddr >> 24);
 561   off = (memaddr & 0xffffffL);
 562
 563   switch (seg)
 564     {
 565     case 0x00:                        /* Physical unified memory */
 566       last_from = "phys-unified";
 567       last_to = "unified";
 568       phys = SIM_CR16_MEMORY_UNIFIED + off;
 569       if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
 570         nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
 571       break;
 572
 573     case 0x01:                        /* Physical instruction memory */
 574       last_from = "phys-insn";
 575       last_to = "chip-insn";
 576       phys = SIM_CR16_MEMORY_INSN + off;
 577       if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
 578         nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
 579       break;
 580
 581     case 0x02:                        /* Physical data memory segment */
 582       last_from = "phys-data";
 583       last_to = "chip-data";
 584       phys = SIM_CR16_MEMORY_DATA + off;
 585       if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
 586         nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
 587       break;
 588
 589     case 0x10:                        /* in logical data address segment */
 590       nr_bytes = sim_cr16_translate_dmap_addr (off, nr_bytes, &phys, regcache,
 591                                                dmap_register);
 592       break;
 593
 594     case 0x11:                        /* in logical instruction address segment */
 595       nr_bytes = sim_cr16_translate_imap_addr (off, nr_bytes, &phys, regcache,
 596                                                imap_register);
 597       break;
 598
 599     default:
 600       return 0;
 601     }
 602
 603   *targ_addr = phys;
 604   return nr_bytes;
 605 }
 606
 607 /* Return a pointer into the raw buffer designated by phys_addr.  It
 608    is assumed that the client has already ensured that the access
 609    isn't going to cross a segment boundary. */
 610
 611 uint8 *
 612 map_memory (unsigned phys_addr)
 613 {
 614   uint8 **memory;
 615   uint8 *raw;
 616   unsigned offset;
 617   int segment = ((phys_addr >> 24) & 0xff);
 618
 619   switch (segment)
 620     {
 621
 622     case 0x00: /* Unified memory */
 623       {
 624         memory = &State.mem.unif[(phys_addr / SEGMENT_SIZE) % UMEM_SEGMENTS];
 625         last_segname = "umem";
 626         break;
 627       }
 628
 629     case 0x01: /* On-chip insn memory */
 630       {
 631         memory = &State.mem.insn[(phys_addr / SEGMENT_SIZE) % IMEM_SEGMENTS];
 632         last_segname = "imem";
 633         break;
 634       }
 635
 636     case 0x02: /* On-chip data memory */
 637       {
 638         if ((phys_addr & 0xff00) == 0xff00)
 639           {
 640             phys_addr = (phys_addr & 0xffff);
 641             if (phys_addr == DMAP2_SHADDOW)
 642               {
 643                 phys_addr = DMAP2_OFFSET;
 644                 last_segname = "dmap";
 645               }
 646             else
 647               last_segname = "reg";
 648           }
 649         else
 650           last_segname = "dmem";
 651         memory = &State.mem.data[(phys_addr / SEGMENT_SIZE) % DMEM_SEGMENTS];
 652         break;
 653       }
 654
 655     default:
 656       /* OOPS! */
 657       last_segname = "scrap";
 658       return State.mem.fault;
 659     }
 660
 661   if (*memory == NULL)
 662     {
 663       *memory = calloc (1, SEGMENT_SIZE);
 664       if (*memory == NULL)
 665         {
 666           (*cr16_callback->printf_filtered) (cr16_callback, "Malloc failed.\n");
 667           return State.mem.fault;
 668         }
 669     }
 670
 671   offset = (phys_addr % SEGMENT_SIZE);
 672   raw = *memory + offset;
 673   return raw;
 674 }
 675
 676 /* Transfer data to/from simulated memory.  Since a bug in either the
 677    simulated program or in gdb or the simulator itself may cause a
 678    bogus address to be passed in, we need to do some sanity checking
 679    on addresses to make sure they are within bounds.  When an address
 680    fails the bounds check, treat it as a zero length read/write rather
 681    than aborting the entire run. */
 682
 683 static int
 684 xfer_mem (SIM_DESC sd, SIM_ADDR virt,
 685           unsigned char *buffer,
 686           int size,
 687           int write_p)
 688 {
 689   host_callback *cr16_callback = STATE_CALLBACK (sd);
 690   uint8 *memory;
 691   unsigned long phys;
 692   int phys_size;
 693   phys_size = sim_cr16_translate_addr (virt, size, &phys, NULL,
 694                                        dmap_register, imap_register);
 695   if (phys_size == 0)
 696     return 0;
 697
 698   memory = map_memory (phys);
 699
 700 #ifdef DEBUG
 701   if ((cr16_debug & DEBUG_INSTRUCTION) != 0)
 702     {
 703       (*cr16_callback->printf_filtered)
 704         (cr16_callback,
 705          "sim_%s %d bytes: 0x%08lx (%s) -> 0x%08lx (%s) -> 0x%08lx (%s)\n",
 706              (write_p ? "write" : "read"),
 707          phys_size, virt, last_from,
 708          phys, last_to,
 709          (long) memory, last_segname);
 710     }
 711 #endif
 712
 713   if (write_p)
 714     {
 715       memcpy (memory, buffer, phys_size);
 716     }
 717   else
 718     {
 719       memcpy (buffer, memory, phys_size);
 720     }
 721
 722   return phys_size;
 723 }
 724
 725
 726 int
 727 sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size)
 728 {
 729   /* FIXME: this should be performing a virtual transfer */
 730   return xfer_mem (sd, addr, buffer, size, 1);
 731 }
 732
 733 int
 734 sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
 735 {
 736   /* FIXME: this should be performing a virtual transfer */
 737   return xfer_mem (sd, addr, buffer, size, 0);
 738 }
 739
 740 static sim_cia
 741 cr16_pc_get (sim_cpu *cpu)
 742 {
 743   return PC;
 744 }
 745
 746 static void
 747 cr16_pc_set (sim_cpu *cpu, sim_cia pc)
 748 {
 749   SET_PC (pc);
 750 }
 751
 752 static void
 753 free_state (SIM_DESC sd)
 754 {
 755   if (STATE_MODULES (sd) != NULL)
 756     sim_module_uninstall (sd);
 757   sim_cpu_free_all (sd);
 758   sim_state_free (sd);
 759 }
 760
 761 SIM_DESC trace_sd = NULL;
 762
 763 SIM_DESC
 764 sim_open (SIM_OPEN_KIND kind, struct host_callback_struct *cb, struct bfd *abfd, char **argv)
 765 {
 766   struct simops *s;
 767   struct hash_entry *h;
 768   static int init_p = 0;
 769   char **p;
 770   int i;
 771   SIM_DESC sd = sim_state_alloc (kind, cb);
 772   SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
 773
 774   /* The cpu data is kept in a separately allocated chunk of memory.  */
 775   if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
 776     {
 777       free_state (sd);
 778       return 0;
 779     }
 780
 781   if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
 782     {
 783       free_state (sd);
 784       return 0;
 785     }
 786
 787   /* getopt will print the error message so we just have to exit if this fails.
 788      FIXME: Hmmm...  in the case of gdb we need getopt to call
 789      print_filtered.  */
 790   if (sim_parse_args (sd, argv) != SIM_RC_OK)
 791     {
 792       free_state (sd);
 793       return 0;
 794     }
 795
 796   /* Check for/establish the a reference program image.  */
 797   if (sim_analyze_program (sd,
 798                            (STATE_PROG_ARGV (sd) != NULL
 799                             ? *STATE_PROG_ARGV (sd)
 800                             : NULL), abfd) != SIM_RC_OK)
 801     {
 802       free_state (sd);
 803       return 0;
 804     }
 805
 806   /* Configure/verify the target byte order and other runtime
 807      configuration options.  */
 808   if (sim_config (sd) != SIM_RC_OK)
 809     {
 810       sim_module_uninstall (sd);
 811       return 0;
 812     }
 813
 814   if (sim_post_argv_init (sd) != SIM_RC_OK)
 815     {
 816       /* Uninstall the modules to avoid memory leaks,
 817          file descriptor leaks, etc.  */
 818       sim_module_uninstall (sd);
 819       return 0;
 820     }
 821
 822   /* CPU specific initialization.  */
 823   for (i = 0; i < MAX_NR_PROCESSORS; ++i)
 824     {
 825       SIM_CPU *cpu = STATE_CPU (sd, i);
 826
 827       CPU_PC_FETCH (cpu) = cr16_pc_get;
 828       CPU_PC_STORE (cpu) = cr16_pc_set;
 829     }
 830
 831   trace_sd = sd;
 832   cr16_callback = cb;
 833
 834   /* put all the opcodes in the hash table.  */
 835   if (!init_p++)
 836     {
 837       for (s = Simops; s->func; s++)
 838         {
 839           switch(32 - s->mask)
 840             {
 841             case 0x4:
 842                h = &hash_table[hash(s->opcode, 0)];
 843                break;
 844
 845             case 0x7:
 846                if (((s->opcode << 1) >> 4) != 0)
 847                   h = &hash_table[hash((s->opcode << 1) >> 4, 0)];
 848                else
 849                   h = &hash_table[hash((s->opcode << 1), 0)];
 850                break;
 851
 852             case 0x8:
 853                if ((s->opcode >> 4) != 0)
 854                   h = &hash_table[hash(s->opcode >> 4, 0)];
 855                else
 856                   h = &hash_table[hash(s->opcode, 0)];
 857                break;
 858
 859             case 0x9:
 860                if (((s->opcode  >> 1) >> 4) != 0)
 861                  h = &hash_table[hash((s->opcode >>1) >> 4, 0)];
 862                else
 863                  h = &hash_table[hash((s->opcode >> 1), 0)];
 864                break;
 865
 866             case 0xa:
 867                if ((s->opcode >> 8) != 0)
 868                  h = &hash_table[hash(s->opcode >> 8, 0)];
 869                else if ((s->opcode >> 4) != 0)
 870                  h = &hash_table[hash(s->opcode >> 4, 0)];
 871                else
 872                  h = &hash_table[hash(s->opcode, 0)];
 873                break;
 874
 875             case 0xc:
 876                if ((s->opcode >> 8) != 0)
 877                  h = &hash_table[hash(s->opcode >> 8, 0)];
 878                else if ((s->opcode >> 4) != 0)
 879                  h = &hash_table[hash(s->opcode >> 4, 0)];
 880                else
 881                  h = &hash_table[hash(s->opcode, 0)];
 882                break;
 883
 884             case 0xd:
 885                if (((s->opcode >> 1) >> 8) != 0)
 886                  h = &hash_table[hash((s->opcode >>1) >> 8, 0)];
 887                else if (((s->opcode >> 1) >> 4) != 0)
 888                  h = &hash_table[hash((s->opcode >>1) >> 4, 0)];
 889                else
 890                  h = &hash_table[hash((s->opcode >>1), 0)];
 891                break;
 892
 893             case 0x10:
 894                if ((s->opcode >> 0xc) != 0)
 895                  h = &hash_table[hash(s->opcode >> 12, 0)];
 896                else if ((s->opcode >> 8) != 0)
 897                  h = &hash_table[hash(s->opcode >> 8, 0)];
 898                else if ((s->opcode >> 4) != 0)
 899                  h = &hash_table[hash(s->opcode >> 4, 0)];
 900                else
 901                  h = &hash_table[hash(s->opcode, 0)];
 902                break;
 903
 904             case 0x14:
 905                if ((s->opcode >> 16) != 0)
 906                  h = &hash_table[hash(s->opcode >> 16, 0)];
 907                else if ((s->opcode >> 12) != 0)
 908                  h = &hash_table[hash(s->opcode >> 12, 0)];
 909                else if ((s->opcode >> 8) != 0)
 910                  h = &hash_table[hash(s->opcode >> 8, 0)];
 911                else if ((s->opcode >> 4) != 0)
 912                  h = &hash_table[hash(s->opcode >> 4, 0)];
 913                else
 914                  h = &hash_table[hash(s->opcode, 0)];
 915                break;
 916             default:
 917               break;
 918             }
 919
 920           /* go to the last entry in the chain.  */
 921           while (h->next)
 922             h = h->next;
 923
 924           if (h->ops)
 925             {
 926               h->next = (struct hash_entry *) calloc(1,sizeof(struct hash_entry));
 927               if (!h->next)
 928                 perror ("malloc failure");
 929
 930               h = h->next;
 931             }
 932           h->ops = s;
 933           h->mask = s->mask;
 934           h->opcode = s->opcode;
 935           h->format = s->format;
 936           h->size = s->size;
 937         }
 938     }
 939
 940   /* reset the processor state */
 941   if (!State.mem.data[0])
 942     sim_size (1);
 943
 944   return sd;
 945 }
 946
 947 uint8 *
 948 dmem_addr (uint32 offset)
 949 {
 950   unsigned long phys;
 951   uint8 *mem;
 952   int phys_size;
 953
 954   /* Note: DMEM address range is 0..0x10000. Calling code can compute
 955      things like ``0xfffe + 0x0e60 == 0x10e5d''.  Since offset's type
 956      is uint16 this is modulo'ed onto 0x0e5d. */
 957
 958   phys_size = sim_cr16_translate_dmap_addr (offset, 1, &phys, NULL,
 959                                             dmap_register);
 960   if (phys_size == 0)
 961     {
 962       mem = State.mem.fault;
 963     }
 964   else
 965     mem = map_memory (phys);
 966 #ifdef DEBUG
 967   if ((cr16_debug & DEBUG_MEMORY))
 968     {
 969       (*cr16_callback->printf_filtered)
 970         (cr16_callback,
 971          "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
 972          offset, last_from,
 973          phys, phys_size, last_to,
 974          (long) mem, last_segname);
 975     }
 976 #endif
 977   return mem;
 978 }
 979
 980 uint8 *
 981 imem_addr (uint32 offset)
 982 {
 983   unsigned long phys;
 984   uint8 *mem;
 985   int phys_size = sim_cr16_translate_imap_addr (offset, 1, &phys, NULL,
 986                                                 imap_register);
 987   if (phys_size == 0)
 988     {
 989       return State.mem.fault;
 990     }
 991   mem = map_memory (phys);
 992 #ifdef DEBUG
 993   if ((cr16_debug & DEBUG_MEMORY))
 994     {
 995       (*cr16_callback->printf_filtered)
 996         (cr16_callback,
 997          "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
 998          offset, last_from,
 999          phys, phys_size, last_to,
1000          (long) mem, last_segname);
1001     }
1002 #endif
1003   return mem;
1004 }
1005
1006 static int stop_simulator = 0;
1007
1008 int
1009 sim_stop (SIM_DESC sd)
1010 {
1011   stop_simulator = 1;
1012   return 1;
1013 }
1014
1015
1016 /* Run (or resume) the program.  */
1017 void
1018 sim_resume (SIM_DESC sd, int step, int siggnal)
1019 {
1020   uint32 curr_ins_size = 0;
1021   uint64 mcode = 0;
1022   uint8 *iaddr;
1023
1024 #ifdef DEBUG
1025 //  (*cr16_callback->printf_filtered) (cr16_callback, "sim_resume (%d,%d)  PC=0x%x\n",step,siggnal,PC);
1026 #endif
1027
1028   State.exception = 0;
1029   if (step)
1030     sim_stop (sd);
1031
1032   switch (siggnal)
1033     {
1034     case 0:
1035       break;
1036 #ifdef SIGBUS
1037     case SIGBUS:
1038 #endif
1039     case SIGSEGV:
1040       SET_PC (PC);
1041       SET_PSR (PSR);
1042       JMP (AE_VECTOR_START);
1043       SLOT_FLUSH ();
1044       break;
1045     case SIGILL:
1046       SET_PC (PC);
1047       SET_PSR (PSR);
1048       SET_HW_PSR ((PSR & (PSR_C_BIT)));
1049       JMP (RIE_VECTOR_START);
1050       SLOT_FLUSH ();
1051       break;
1052     default:
1053       /* just ignore it */
1054       break;
1055     }
1056
1057   do
1058     {
1059       iaddr = imem_addr ((uint32)PC);
1060       if (iaddr == State.mem.fault)
1061         {
1062 #ifdef SIGBUS
1063           State.exception = SIGBUS;
1064 #else
1065           State.exception = SIGSEGV;
1066 #endif
1067           break;
1068         }
1069
1070       mcode = get_longword( iaddr );
1071
1072       State.pc_changed = 0;
1073
1074       curr_ins_size = do_run(sd, mcode);
1075
1076 #if CR16_DEBUG
1077  (*cr16_callback->printf_filtered) (cr16_callback, "INS: PC=0x%X, mcode=0x%X\n",PC,mcode);
1078 #endif
1079
1080       if (!State.pc_changed)
1081         {
1082           if (curr_ins_size == 0)
1083            {
1084              State.exception = SIG_CR16_EXIT; /* exit trap */
1085              break;
1086            }
1087           else
1088            SET_PC (PC + (curr_ins_size * 2)); /* For word instructions.  */
1089         }
1090
1091 #if 0
1092       /* Check for a breakpoint trap on this instruction.  This
1093          overrides any pending branches or loops */
1094       if (PSR_DB && PC == DBS)
1095         {
1096           SET_BPC (PC);
1097           SET_BPSR (PSR);
1098           SET_PC (SDBT_VECTOR_START);
1099         }
1100 #endif
1101
1102       /* Writeback all the DATA / PC changes */
1103       SLOT_FLUSH ();
1104     }
1105   while ( !State.exception && !stop_simulator);
1106
1107   if (step && !State.exception)
1108     State.exception = SIGTRAP;
1109 }
1110
1111 SIM_RC
1112 sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char **argv, char **env)
1113 {
1114   bfd_vma start_address;
1115
1116   /* reset all state information */
1117   memset (&State.regs, 0, (uintptr_t)&State.mem - (uintptr_t)&State.regs);
1118
1119   /* There was a hack here to copy the values of argc and argv into r0
1120      and r1.  The values were also saved into some high memory that
1121      won't be overwritten by the stack (0x7C00).  The reason for doing
1122      this was to allow the 'run' program to accept arguments.  Without
1123      the hack, this is not possible anymore.  If the simulator is run
1124      from the debugger, arguments cannot be passed in, so this makes
1125      no difference.  */
1126
1127   /* set PC */
1128   if (abfd != NULL)
1129     start_address = bfd_get_start_address (abfd);
1130   else
1131     start_address = 0x0;
1132 #ifdef DEBUG
1133   if (cr16_debug)
1134     (*cr16_callback->printf_filtered) (cr16_callback, "sim_create_inferior:  PC=0x%lx\n", (long) start_address);
1135 #endif
1136   SET_CREG (PC_CR, start_address);
1137
1138   SLOT_FLUSH ();
1139   return SIM_RC_OK;
1140 }
1141
1142 void
1143 sim_stop_reason (SIM_DESC sd, enum sim_stop *reason, int *sigrc)
1144 {
1145 /*   (*cr16_callback->printf_filtered) (cr16_callback, "sim_stop_reason:  PC=0x%x\n",PC<<2); */
1146
1147   switch (State.exception)
1148     {
1149     case SIG_CR16_STOP:                        /* stop instruction */
1150       *reason = sim_stopped;
1151       *sigrc = 0;
1152       break;
1153
1154     case SIG_CR16_EXIT:                        /* exit trap */
1155       *reason = sim_exited;
1156       *sigrc = GPR (2);
1157       break;
1158
1159     case SIG_CR16_BUS:
1160       *reason = sim_stopped;
1161       *sigrc = GDB_SIGNAL_BUS;
1162       break;
1163 //
1164 //    case SIG_CR16_IAD:
1165 //      *reason = sim_stopped;
1166 //      *sigrc = GDB_SIGNAL_IAD;
1167 //      break;
1168
1169     default:                                /* some signal */
1170       *reason = sim_stopped;
1171       if (stop_simulator && !State.exception)
1172         *sigrc = GDB_SIGNAL_INT;
1173       else
1174         *sigrc = State.exception;
1175       break;
1176     }
1177
1178   stop_simulator = 0;
1179 }
1180
1181 int
1182 sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
1183 {
1184   int size;
1185   switch ((enum sim_cr16_regs) rn)
1186     {
1187     case SIM_CR16_R0_REGNUM:
1188     case SIM_CR16_R1_REGNUM:
1189     case SIM_CR16_R2_REGNUM:
1190     case SIM_CR16_R3_REGNUM:
1191     case SIM_CR16_R4_REGNUM:
1192     case SIM_CR16_R5_REGNUM:
1193     case SIM_CR16_R6_REGNUM:
1194     case SIM_CR16_R7_REGNUM:
1195     case SIM_CR16_R8_REGNUM:
1196     case SIM_CR16_R9_REGNUM:
1197     case SIM_CR16_R10_REGNUM:
1198     case SIM_CR16_R11_REGNUM:
1199       WRITE_16 (memory, GPR (rn - SIM_CR16_R0_REGNUM));
1200       size = 2;
1201       break;
1202     case SIM_CR16_R12_REGNUM:
1203     case SIM_CR16_R13_REGNUM:
1204     case SIM_CR16_R14_REGNUM:
1205     case SIM_CR16_R15_REGNUM:
1206       //WRITE_32 (memory, GPR (rn - SIM_CR16_R0_REGNUM));
1207       write_longword (memory, GPR (rn - SIM_CR16_R0_REGNUM));
1208       size = 4;
1209       break;
1210     case SIM_CR16_PC_REGNUM:
1211     case SIM_CR16_ISP_REGNUM:
1212     case SIM_CR16_USP_REGNUM:
1213     case SIM_CR16_INTBASE_REGNUM:
1214     case SIM_CR16_PSR_REGNUM:
1215     case SIM_CR16_CFG_REGNUM:
1216     case SIM_CR16_DBS_REGNUM:
1217     case SIM_CR16_DCR_REGNUM:
1218     case SIM_CR16_DSR_REGNUM:
1219     case SIM_CR16_CAR0_REGNUM:
1220     case SIM_CR16_CAR1_REGNUM:
1221       //WRITE_32 (memory, CREG (rn - SIM_CR16_PC_REGNUM));
1222       write_longword (memory, CREG (rn - SIM_CR16_PC_REGNUM));
1223       size = 4;
1224       break;
1225     default:
1226       size = 0;
1227       break;
1228     }
1229   return size;
1230 }
1231
1232 int
1233 sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
1234 {
1235   int size;
1236   switch ((enum sim_cr16_regs) rn)
1237     {
1238     case SIM_CR16_R0_REGNUM:
1239     case SIM_CR16_R1_REGNUM:
1240     case SIM_CR16_R2_REGNUM:
1241     case SIM_CR16_R3_REGNUM:
1242     case SIM_CR16_R4_REGNUM:
1243     case SIM_CR16_R5_REGNUM:
1244     case SIM_CR16_R6_REGNUM:
1245     case SIM_CR16_R7_REGNUM:
1246     case SIM_CR16_R8_REGNUM:
1247     case SIM_CR16_R9_REGNUM:
1248     case SIM_CR16_R10_REGNUM:
1249     case SIM_CR16_R11_REGNUM:
1250       SET_GPR (rn - SIM_CR16_R0_REGNUM, READ_16 (memory));
1251       size = 2;
1252       break;
1253     case SIM_CR16_R12_REGNUM:
1254     case SIM_CR16_R13_REGNUM:
1255     case SIM_CR16_R14_REGNUM:
1256     case SIM_CR16_R15_REGNUM:
1257       SET_GPR32 (rn - SIM_CR16_R0_REGNUM, get_longword (memory));
1258       size = 4;
1259       break;
1260     case SIM_CR16_PC_REGNUM:
1261     case SIM_CR16_ISP_REGNUM:
1262     case SIM_CR16_USP_REGNUM:
1263     case SIM_CR16_INTBASE_REGNUM:
1264     case SIM_CR16_PSR_REGNUM:
1265     case SIM_CR16_CFG_REGNUM:
1266     case SIM_CR16_DBS_REGNUM:
1267     case SIM_CR16_DCR_REGNUM:
1268     case SIM_CR16_DSR_REGNUM:
1269     case SIM_CR16_CAR0_REGNUM:
1270     case SIM_CR16_CAR1_REGNUM:
1271       SET_CREG (rn - SIM_CR16_PC_REGNUM, get_longword (memory));
1272       size = 4;
1273       break;
1274     default:
1275       size = 0;
1276       break;
1277     }
1278   SLOT_FLUSH ();
1279   return size;
1280 }