sim/cris/semcrisv10f-switch.c

   1 /* Simulator instruction semantics for crisv10f.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996-2005 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #ifdef DEFINE_LABELS
  26
  27   /* The labels have the case they have because the enum of insn types
  28      is all uppercase and in the non-stdc case the insn symbol is built
  29      into the enum name.  */
  30
  31   static struct {
  32     int index;
  33     void *label;
  34   } labels[] = {
  35     { CRISV10F_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
  36     { CRISV10F_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
  37     { CRISV10F_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
  38     { CRISV10F_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
  39     { CRISV10F_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
  40     { CRISV10F_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
  41     { CRISV10F_INSN_NOP, && case_sem_INSN_NOP },
  42     { CRISV10F_INSN_MOVE_B_R, && case_sem_INSN_MOVE_B_R },
  43     { CRISV10F_INSN_MOVE_W_R, && case_sem_INSN_MOVE_W_R },
  44     { CRISV10F_INSN_MOVE_D_R, && case_sem_INSN_MOVE_D_R },
  45     { CRISV10F_INSN_MOVEPCR, && case_sem_INSN_MOVEPCR },
  46     { CRISV10F_INSN_MOVEQ, && case_sem_INSN_MOVEQ },
  47     { CRISV10F_INSN_MOVS_B_R, && case_sem_INSN_MOVS_B_R },
  48     { CRISV10F_INSN_MOVS_W_R, && case_sem_INSN_MOVS_W_R },
  49     { CRISV10F_INSN_MOVU_B_R, && case_sem_INSN_MOVU_B_R },
  50     { CRISV10F_INSN_MOVU_W_R, && case_sem_INSN_MOVU_W_R },
  51     { CRISV10F_INSN_MOVECBR, && case_sem_INSN_MOVECBR },
  52     { CRISV10F_INSN_MOVECWR, && case_sem_INSN_MOVECWR },
  53     { CRISV10F_INSN_MOVECDR, && case_sem_INSN_MOVECDR },
  54     { CRISV10F_INSN_MOVSCBR, && case_sem_INSN_MOVSCBR },
  55     { CRISV10F_INSN_MOVSCWR, && case_sem_INSN_MOVSCWR },
  56     { CRISV10F_INSN_MOVUCBR, && case_sem_INSN_MOVUCBR },
  57     { CRISV10F_INSN_MOVUCWR, && case_sem_INSN_MOVUCWR },
  58     { CRISV10F_INSN_ADDQ, && case_sem_INSN_ADDQ },
  59     { CRISV10F_INSN_SUBQ, && case_sem_INSN_SUBQ },
  60     { CRISV10F_INSN_CMP_R_B_R, && case_sem_INSN_CMP_R_B_R },
  61     { CRISV10F_INSN_CMP_R_W_R, && case_sem_INSN_CMP_R_W_R },
  62     { CRISV10F_INSN_CMP_R_D_R, && case_sem_INSN_CMP_R_D_R },
  63     { CRISV10F_INSN_CMP_M_B_M, && case_sem_INSN_CMP_M_B_M },
  64     { CRISV10F_INSN_CMP_M_W_M, && case_sem_INSN_CMP_M_W_M },
  65     { CRISV10F_INSN_CMP_M_D_M, && case_sem_INSN_CMP_M_D_M },
  66     { CRISV10F_INSN_CMPCBR, && case_sem_INSN_CMPCBR },
  67     { CRISV10F_INSN_CMPCWR, && case_sem_INSN_CMPCWR },
  68     { CRISV10F_INSN_CMPCDR, && case_sem_INSN_CMPCDR },
  69     { CRISV10F_INSN_CMPQ, && case_sem_INSN_CMPQ },
  70     { CRISV10F_INSN_CMPS_M_B_M, && case_sem_INSN_CMPS_M_B_M },
  71     { CRISV10F_INSN_CMPS_M_W_M, && case_sem_INSN_CMPS_M_W_M },
  72     { CRISV10F_INSN_CMPSCBR, && case_sem_INSN_CMPSCBR },
  73     { CRISV10F_INSN_CMPSCWR, && case_sem_INSN_CMPSCWR },
  74     { CRISV10F_INSN_CMPU_M_B_M, && case_sem_INSN_CMPU_M_B_M },
  75     { CRISV10F_INSN_CMPU_M_W_M, && case_sem_INSN_CMPU_M_W_M },
  76     { CRISV10F_INSN_CMPUCBR, && case_sem_INSN_CMPUCBR },
  77     { CRISV10F_INSN_CMPUCWR, && case_sem_INSN_CMPUCWR },
  78     { CRISV10F_INSN_MOVE_M_B_M, && case_sem_INSN_MOVE_M_B_M },
  79     { CRISV10F_INSN_MOVE_M_W_M, && case_sem_INSN_MOVE_M_W_M },
  80     { CRISV10F_INSN_MOVE_M_D_M, && case_sem_INSN_MOVE_M_D_M },
  81     { CRISV10F_INSN_MOVS_M_B_M, && case_sem_INSN_MOVS_M_B_M },
  82     { CRISV10F_INSN_MOVS_M_W_M, && case_sem_INSN_MOVS_M_W_M },
  83     { CRISV10F_INSN_MOVU_M_B_M, && case_sem_INSN_MOVU_M_B_M },
  84     { CRISV10F_INSN_MOVU_M_W_M, && case_sem_INSN_MOVU_M_W_M },
  85     { CRISV10F_INSN_MOVE_R_SPRV10, && case_sem_INSN_MOVE_R_SPRV10 },
  86     { CRISV10F_INSN_MOVE_SPR_RV10, && case_sem_INSN_MOVE_SPR_RV10 },
  87     { CRISV10F_INSN_RET_TYPE, && case_sem_INSN_RET_TYPE },
  88     { CRISV10F_INSN_MOVE_M_SPRV10, && case_sem_INSN_MOVE_M_SPRV10 },
  89     { CRISV10F_INSN_MOVE_C_SPRV10_P0, && case_sem_INSN_MOVE_C_SPRV10_P0 },
  90     { CRISV10F_INSN_MOVE_C_SPRV10_P1, && case_sem_INSN_MOVE_C_SPRV10_P1 },
  91     { CRISV10F_INSN_MOVE_C_SPRV10_P4, && case_sem_INSN_MOVE_C_SPRV10_P4 },
  92     { CRISV10F_INSN_MOVE_C_SPRV10_P5, && case_sem_INSN_MOVE_C_SPRV10_P5 },
  93     { CRISV10F_INSN_MOVE_C_SPRV10_P8, && case_sem_INSN_MOVE_C_SPRV10_P8 },
  94     { CRISV10F_INSN_MOVE_C_SPRV10_P9, && case_sem_INSN_MOVE_C_SPRV10_P9 },
  95     { CRISV10F_INSN_MOVE_C_SPRV10_P10, && case_sem_INSN_MOVE_C_SPRV10_P10 },
  96     { CRISV10F_INSN_MOVE_C_SPRV10_P11, && case_sem_INSN_MOVE_C_SPRV10_P11 },
  97     { CRISV10F_INSN_MOVE_C_SPRV10_P12, && case_sem_INSN_MOVE_C_SPRV10_P12 },
  98     { CRISV10F_INSN_MOVE_C_SPRV10_P13, && case_sem_INSN_MOVE_C_SPRV10_P13 },
  99     { CRISV10F_INSN_MOVE_C_SPRV10_P7, && case_sem_INSN_MOVE_C_SPRV10_P7 },
 100     { CRISV10F_INSN_MOVE_C_SPRV10_P14, && case_sem_INSN_MOVE_C_SPRV10_P14 },
 101     { CRISV10F_INSN_MOVE_C_SPRV10_P15, && case_sem_INSN_MOVE_C_SPRV10_P15 },
 102     { CRISV10F_INSN_MOVE_SPR_MV10, && case_sem_INSN_MOVE_SPR_MV10 },
 103     { CRISV10F_INSN_SBFS, && case_sem_INSN_SBFS },
 104     { CRISV10F_INSN_MOVEM_R_M, && case_sem_INSN_MOVEM_R_M },
 105     { CRISV10F_INSN_MOVEM_M_R, && case_sem_INSN_MOVEM_M_R },
 106     { CRISV10F_INSN_MOVEM_M_PC, && case_sem_INSN_MOVEM_M_PC },
 107     { CRISV10F_INSN_ADD_B_R, && case_sem_INSN_ADD_B_R },
 108     { CRISV10F_INSN_ADD_W_R, && case_sem_INSN_ADD_W_R },
 109     { CRISV10F_INSN_ADD_D_R, && case_sem_INSN_ADD_D_R },
 110     { CRISV10F_INSN_ADD_M_B_M, && case_sem_INSN_ADD_M_B_M },
 111     { CRISV10F_INSN_ADD_M_W_M, && case_sem_INSN_ADD_M_W_M },
 112     { CRISV10F_INSN_ADD_M_D_M, && case_sem_INSN_ADD_M_D_M },
 113     { CRISV10F_INSN_ADDCBR, && case_sem_INSN_ADDCBR },
 114     { CRISV10F_INSN_ADDCWR, && case_sem_INSN_ADDCWR },
 115     { CRISV10F_INSN_ADDCDR, && case_sem_INSN_ADDCDR },
 116     { CRISV10F_INSN_ADDCPC, && case_sem_INSN_ADDCPC },
 117     { CRISV10F_INSN_ADDS_B_R, && case_sem_INSN_ADDS_B_R },
 118     { CRISV10F_INSN_ADDS_W_R, && case_sem_INSN_ADDS_W_R },
 119     { CRISV10F_INSN_ADDS_M_B_M, && case_sem_INSN_ADDS_M_B_M },
 120     { CRISV10F_INSN_ADDS_M_W_M, && case_sem_INSN_ADDS_M_W_M },
 121     { CRISV10F_INSN_ADDSCBR, && case_sem_INSN_ADDSCBR },
 122     { CRISV10F_INSN_ADDSCWR, && case_sem_INSN_ADDSCWR },
 123     { CRISV10F_INSN_ADDSPCPC, && case_sem_INSN_ADDSPCPC },
 124     { CRISV10F_INSN_ADDU_B_R, && case_sem_INSN_ADDU_B_R },
 125     { CRISV10F_INSN_ADDU_W_R, && case_sem_INSN_ADDU_W_R },
 126     { CRISV10F_INSN_ADDU_M_B_M, && case_sem_INSN_ADDU_M_B_M },
 127     { CRISV10F_INSN_ADDU_M_W_M, && case_sem_INSN_ADDU_M_W_M },
 128     { CRISV10F_INSN_ADDUCBR, && case_sem_INSN_ADDUCBR },
 129     { CRISV10F_INSN_ADDUCWR, && case_sem_INSN_ADDUCWR },
 130     { CRISV10F_INSN_SUB_B_R, && case_sem_INSN_SUB_B_R },
 131     { CRISV10F_INSN_SUB_W_R, && case_sem_INSN_SUB_W_R },
 132     { CRISV10F_INSN_SUB_D_R, && case_sem_INSN_SUB_D_R },
 133     { CRISV10F_INSN_SUB_M_B_M, && case_sem_INSN_SUB_M_B_M },
 134     { CRISV10F_INSN_SUB_M_W_M, && case_sem_INSN_SUB_M_W_M },
 135     { CRISV10F_INSN_SUB_M_D_M, && case_sem_INSN_SUB_M_D_M },
 136     { CRISV10F_INSN_SUBCBR, && case_sem_INSN_SUBCBR },
 137     { CRISV10F_INSN_SUBCWR, && case_sem_INSN_SUBCWR },
 138     { CRISV10F_INSN_SUBCDR, && case_sem_INSN_SUBCDR },
 139     { CRISV10F_INSN_SUBS_B_R, && case_sem_INSN_SUBS_B_R },
 140     { CRISV10F_INSN_SUBS_W_R, && case_sem_INSN_SUBS_W_R },
 141     { CRISV10F_INSN_SUBS_M_B_M, && case_sem_INSN_SUBS_M_B_M },
 142     { CRISV10F_INSN_SUBS_M_W_M, && case_sem_INSN_SUBS_M_W_M },
 143     { CRISV10F_INSN_SUBSCBR, && case_sem_INSN_SUBSCBR },
 144     { CRISV10F_INSN_SUBSCWR, && case_sem_INSN_SUBSCWR },
 145     { CRISV10F_INSN_SUBU_B_R, && case_sem_INSN_SUBU_B_R },
 146     { CRISV10F_INSN_SUBU_W_R, && case_sem_INSN_SUBU_W_R },
 147     { CRISV10F_INSN_SUBU_M_B_M, && case_sem_INSN_SUBU_M_B_M },
 148     { CRISV10F_INSN_SUBU_M_W_M, && case_sem_INSN_SUBU_M_W_M },
 149     { CRISV10F_INSN_SUBUCBR, && case_sem_INSN_SUBUCBR },
 150     { CRISV10F_INSN_SUBUCWR, && case_sem_INSN_SUBUCWR },
 151     { CRISV10F_INSN_ADDI_B_R, && case_sem_INSN_ADDI_B_R },
 152     { CRISV10F_INSN_ADDI_W_R, && case_sem_INSN_ADDI_W_R },
 153     { CRISV10F_INSN_ADDI_D_R, && case_sem_INSN_ADDI_D_R },
 154     { CRISV10F_INSN_NEG_B_R, && case_sem_INSN_NEG_B_R },
 155     { CRISV10F_INSN_NEG_W_R, && case_sem_INSN_NEG_W_R },
 156     { CRISV10F_INSN_NEG_D_R, && case_sem_INSN_NEG_D_R },
 157     { CRISV10F_INSN_TEST_M_B_M, && case_sem_INSN_TEST_M_B_M },
 158     { CRISV10F_INSN_TEST_M_W_M, && case_sem_INSN_TEST_M_W_M },
 159     { CRISV10F_INSN_TEST_M_D_M, && case_sem_INSN_TEST_M_D_M },
 160     { CRISV10F_INSN_MOVE_R_M_B_M, && case_sem_INSN_MOVE_R_M_B_M },
 161     { CRISV10F_INSN_MOVE_R_M_W_M, && case_sem_INSN_MOVE_R_M_W_M },
 162     { CRISV10F_INSN_MOVE_R_M_D_M, && case_sem_INSN_MOVE_R_M_D_M },
 163     { CRISV10F_INSN_MULS_B, && case_sem_INSN_MULS_B },
 164     { CRISV10F_INSN_MULS_W, && case_sem_INSN_MULS_W },
 165     { CRISV10F_INSN_MULS_D, && case_sem_INSN_MULS_D },
 166     { CRISV10F_INSN_MULU_B, && case_sem_INSN_MULU_B },
 167     { CRISV10F_INSN_MULU_W, && case_sem_INSN_MULU_W },
 168     { CRISV10F_INSN_MULU_D, && case_sem_INSN_MULU_D },
 169     { CRISV10F_INSN_MSTEP, && case_sem_INSN_MSTEP },
 170     { CRISV10F_INSN_DSTEP, && case_sem_INSN_DSTEP },
 171     { CRISV10F_INSN_ABS, && case_sem_INSN_ABS },
 172     { CRISV10F_INSN_AND_B_R, && case_sem_INSN_AND_B_R },
 173     { CRISV10F_INSN_AND_W_R, && case_sem_INSN_AND_W_R },
 174     { CRISV10F_INSN_AND_D_R, && case_sem_INSN_AND_D_R },
 175     { CRISV10F_INSN_AND_M_B_M, && case_sem_INSN_AND_M_B_M },
 176     { CRISV10F_INSN_AND_M_W_M, && case_sem_INSN_AND_M_W_M },
 177     { CRISV10F_INSN_AND_M_D_M, && case_sem_INSN_AND_M_D_M },
 178     { CRISV10F_INSN_ANDCBR, && case_sem_INSN_ANDCBR },
 179     { CRISV10F_INSN_ANDCWR, && case_sem_INSN_ANDCWR },
 180     { CRISV10F_INSN_ANDCDR, && case_sem_INSN_ANDCDR },
 181     { CRISV10F_INSN_ANDQ, && case_sem_INSN_ANDQ },
 182     { CRISV10F_INSN_ORR_B_R, && case_sem_INSN_ORR_B_R },
 183     { CRISV10F_INSN_ORR_W_R, && case_sem_INSN_ORR_W_R },
 184     { CRISV10F_INSN_ORR_D_R, && case_sem_INSN_ORR_D_R },
 185     { CRISV10F_INSN_OR_M_B_M, && case_sem_INSN_OR_M_B_M },
 186     { CRISV10F_INSN_OR_M_W_M, && case_sem_INSN_OR_M_W_M },
 187     { CRISV10F_INSN_OR_M_D_M, && case_sem_INSN_OR_M_D_M },
 188     { CRISV10F_INSN_ORCBR, && case_sem_INSN_ORCBR },
 189     { CRISV10F_INSN_ORCWR, && case_sem_INSN_ORCWR },
 190     { CRISV10F_INSN_ORCDR, && case_sem_INSN_ORCDR },
 191     { CRISV10F_INSN_ORQ, && case_sem_INSN_ORQ },
 192     { CRISV10F_INSN_XOR, && case_sem_INSN_XOR },
 193     { CRISV10F_INSN_SWAP, && case_sem_INSN_SWAP },
 194     { CRISV10F_INSN_ASRR_B_R, && case_sem_INSN_ASRR_B_R },
 195     { CRISV10F_INSN_ASRR_W_R, && case_sem_INSN_ASRR_W_R },
 196     { CRISV10F_INSN_ASRR_D_R, && case_sem_INSN_ASRR_D_R },
 197     { CRISV10F_INSN_ASRQ, && case_sem_INSN_ASRQ },
 198     { CRISV10F_INSN_LSRR_B_R, && case_sem_INSN_LSRR_B_R },
 199     { CRISV10F_INSN_LSRR_W_R, && case_sem_INSN_LSRR_W_R },
 200     { CRISV10F_INSN_LSRR_D_R, && case_sem_INSN_LSRR_D_R },
 201     { CRISV10F_INSN_LSRQ, && case_sem_INSN_LSRQ },
 202     { CRISV10F_INSN_LSLR_B_R, && case_sem_INSN_LSLR_B_R },
 203     { CRISV10F_INSN_LSLR_W_R, && case_sem_INSN_LSLR_W_R },
 204     { CRISV10F_INSN_LSLR_D_R, && case_sem_INSN_LSLR_D_R },
 205     { CRISV10F_INSN_LSLQ, && case_sem_INSN_LSLQ },
 206     { CRISV10F_INSN_BTST, && case_sem_INSN_BTST },
 207     { CRISV10F_INSN_BTSTQ, && case_sem_INSN_BTSTQ },
 208     { CRISV10F_INSN_SETF, && case_sem_INSN_SETF },
 209     { CRISV10F_INSN_CLEARF, && case_sem_INSN_CLEARF },
 210     { CRISV10F_INSN_BCC_B, && case_sem_INSN_BCC_B },
 211     { CRISV10F_INSN_BA_B, && case_sem_INSN_BA_B },
 212     { CRISV10F_INSN_BCC_W, && case_sem_INSN_BCC_W },
 213     { CRISV10F_INSN_BA_W, && case_sem_INSN_BA_W },
 214     { CRISV10F_INSN_JUMP_R, && case_sem_INSN_JUMP_R },
 215     { CRISV10F_INSN_JUMP_M, && case_sem_INSN_JUMP_M },
 216     { CRISV10F_INSN_JUMP_C, && case_sem_INSN_JUMP_C },
 217     { CRISV10F_INSN_BREAK, && case_sem_INSN_BREAK },
 218     { CRISV10F_INSN_BOUND_R_B_R, && case_sem_INSN_BOUND_R_B_R },
 219     { CRISV10F_INSN_BOUND_R_W_R, && case_sem_INSN_BOUND_R_W_R },
 220     { CRISV10F_INSN_BOUND_R_D_R, && case_sem_INSN_BOUND_R_D_R },
 221     { CRISV10F_INSN_BOUND_M_B_M, && case_sem_INSN_BOUND_M_B_M },
 222     { CRISV10F_INSN_BOUND_M_W_M, && case_sem_INSN_BOUND_M_W_M },
 223     { CRISV10F_INSN_BOUND_M_D_M, && case_sem_INSN_BOUND_M_D_M },
 224     { CRISV10F_INSN_BOUND_CB, && case_sem_INSN_BOUND_CB },
 225     { CRISV10F_INSN_BOUND_CW, && case_sem_INSN_BOUND_CW },
 226     { CRISV10F_INSN_BOUND_CD, && case_sem_INSN_BOUND_CD },
 227     { CRISV10F_INSN_SCC, && case_sem_INSN_SCC },
 228     { CRISV10F_INSN_LZ, && case_sem_INSN_LZ },
 229     { CRISV10F_INSN_ADDOQ, && case_sem_INSN_ADDOQ },
 230     { CRISV10F_INSN_BDAPQPC, && case_sem_INSN_BDAPQPC },
 231     { CRISV10F_INSN_ADDO_M_B_M, && case_sem_INSN_ADDO_M_B_M },
 232     { CRISV10F_INSN_ADDO_M_W_M, && case_sem_INSN_ADDO_M_W_M },
 233     { CRISV10F_INSN_ADDO_M_D_M, && case_sem_INSN_ADDO_M_D_M },
 234     { CRISV10F_INSN_ADDO_CB, && case_sem_INSN_ADDO_CB },
 235     { CRISV10F_INSN_ADDO_CW, && case_sem_INSN_ADDO_CW },
 236     { CRISV10F_INSN_ADDO_CD, && case_sem_INSN_ADDO_CD },
 237     { CRISV10F_INSN_DIP_M, && case_sem_INSN_DIP_M },
 238     { CRISV10F_INSN_DIP_C, && case_sem_INSN_DIP_C },
 239     { CRISV10F_INSN_ADDI_ACR_B_R, && case_sem_INSN_ADDI_ACR_B_R },
 240     { CRISV10F_INSN_ADDI_ACR_W_R, && case_sem_INSN_ADDI_ACR_W_R },
 241     { CRISV10F_INSN_ADDI_ACR_D_R, && case_sem_INSN_ADDI_ACR_D_R },
 242     { CRISV10F_INSN_BIAP_PC_B_R, && case_sem_INSN_BIAP_PC_B_R },
 243     { CRISV10F_INSN_BIAP_PC_W_R, && case_sem_INSN_BIAP_PC_W_R },
 244     { CRISV10F_INSN_BIAP_PC_D_R, && case_sem_INSN_BIAP_PC_D_R },
 245     { 0, 0 }
 246   };
 247   int i;
 248
 249   for (i = 0; labels[i].label != 0; ++i)
 250     {
 251 #if FAST_P
 252       CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
 253 #else
 254       CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
 255 #endif
 256     }
 257
 258 #undef DEFINE_LABELS
 259 #endif /* DEFINE_LABELS */
 260
 261 #ifdef DEFINE_SWITCH
 262
 263 /* If hyper-fast [well not unnecessarily slow] execution is selected, turn
 264    off frills like tracing and profiling.  */
 265 /* FIXME: A better way would be to have TRACE_RESULT check for something
 266    that can cause it to be optimized out.  Another way would be to emit
 267    special handlers into the instruction "stream".  */
 268
 269 #if FAST_P
 270 #undef TRACE_RESULT
 271 #define TRACE_RESULT(cpu, abuf, name, type, val)
 272 #endif
 273
 274 #undef GET_ATTR
 275 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 276 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
 277 #else
 278 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
 279 #endif
 280
 281 {
 282
 283 #if WITH_SCACHE_PBB
 284
 285 /* Branch to next handler without going around main loop.  */
 286 #define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
 287 SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 288
 289 #else /* ! WITH_SCACHE_PBB */
 290
 291 #define NEXT(vpc) BREAK (sem)
 292 #ifdef __GNUC__
 293 #if FAST_P
 294   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
 295 #else
 296   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
 297 #endif
 298 #else
 299   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
 300 #endif
 301
 302 #endif /* ! WITH_SCACHE_PBB */
 303
 304     {
 305
 306   CASE (sem, INSN_X_INVALID) : /* --invalid-- */
 307 {
 308   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 309   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 310 #define FLD(f) abuf->fields.fmt_empty.f
 311   int UNUSED written = 0;
 312   IADDR UNUSED pc = abuf->addr;
 313   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 314
 315   {
 316     /* Update the recorded pc in the cpu state struct.
 317        Only necessary for WITH_SCACHE case, but to avoid the
 318        conditional compilation ....  */
 319     SET_H_PC (pc);
 320     /* Virtual insns have zero size.  Overwrite vpc with address of next insn
 321        using the default-insn-bitsize spec.  When executing insns in parallel
 322        we may want to queue the fault and continue execution.  */
 323     vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 324     vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
 325   }
 326
 327 #undef FLD
 328 }
 329   NEXT (vpc);
 330
 331   CASE (sem, INSN_X_AFTER) : /* --after-- */
 332 {
 333   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 334   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 335 #define FLD(f) abuf->fields.fmt_empty.f
 336   int UNUSED written = 0;
 337   IADDR UNUSED pc = abuf->addr;
 338   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 339
 340   {
 341 #if WITH_SCACHE_PBB_CRISV10F
 342     crisv10f_pbb_after (current_cpu, sem_arg);
 343 #endif
 344   }
 345
 346 #undef FLD
 347 }
 348   NEXT (vpc);
 349
 350   CASE (sem, INSN_X_BEFORE) : /* --before-- */
 351 {
 352   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 353   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 354 #define FLD(f) abuf->fields.fmt_empty.f
 355   int UNUSED written = 0;
 356   IADDR UNUSED pc = abuf->addr;
 357   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 358
 359   {
 360 #if WITH_SCACHE_PBB_CRISV10F
 361     crisv10f_pbb_before (current_cpu, sem_arg);
 362 #endif
 363   }
 364
 365 #undef FLD
 366 }
 367   NEXT (vpc);
 368
 369   CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
 370 {
 371   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 372   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 373 #define FLD(f) abuf->fields.fmt_empty.f
 374   int UNUSED written = 0;
 375   IADDR UNUSED pc = abuf->addr;
 376   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 377
 378   {
 379 #if WITH_SCACHE_PBB_CRISV10F
 380 #ifdef DEFINE_SWITCH
 381     vpc = crisv10f_pbb_cti_chain (current_cpu, sem_arg,
 382                                pbb_br_type, pbb_br_npc);
 383     BREAK (sem);
 384 #else
 385     /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
 386     vpc = crisv10f_pbb_cti_chain (current_cpu, sem_arg,
 387                                CPU_PBB_BR_TYPE (current_cpu),
 388                                CPU_PBB_BR_NPC (current_cpu));
 389 #endif
 390 #endif
 391   }
 392
 393 #undef FLD
 394 }
 395   NEXT (vpc);
 396
 397   CASE (sem, INSN_X_CHAIN) : /* --chain-- */
 398 {
 399   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 400   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 401 #define FLD(f) abuf->fields.fmt_empty.f
 402   int UNUSED written = 0;
 403   IADDR UNUSED pc = abuf->addr;
 404   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 405
 406   {
 407 #if WITH_SCACHE_PBB_CRISV10F
 408     vpc = crisv10f_pbb_chain (current_cpu, sem_arg);
 409 #ifdef DEFINE_SWITCH
 410     BREAK (sem);
 411 #endif
 412 #endif
 413   }
 414
 415 #undef FLD
 416 }
 417   NEXT (vpc);
 418
 419   CASE (sem, INSN_X_BEGIN) : /* --begin-- */
 420 {
 421   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 422   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 423 #define FLD(f) abuf->fields.fmt_empty.f
 424   int UNUSED written = 0;
 425   IADDR UNUSED pc = abuf->addr;
 426   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 427
 428   {
 429 #if WITH_SCACHE_PBB_CRISV10F
 430 #if defined DEFINE_SWITCH || defined FAST_P
 431     /* In the switch case FAST_P is a constant, allowing several optimizations
 432        in any called inline functions.  */
 433     vpc = crisv10f_pbb_begin (current_cpu, FAST_P);
 434 #else
 435 #if 0 /* cgen engine can't handle dynamic fast/full switching yet.  */
 436     vpc = crisv10f_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
 437 #else
 438     vpc = crisv10f_pbb_begin (current_cpu, 0);
 439 #endif
 440 #endif
 441 #endif
 442   }
 443
 444 #undef FLD
 445 }
 446   NEXT (vpc);
 447
 448   CASE (sem, INSN_NOP) : /* nop */
 449 {
 450   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 451   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 452 #define FLD(f) abuf->fields.fmt_empty.f
 453   int UNUSED written = 0;
 454   IADDR UNUSED pc = abuf->addr;
 455   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 456
 457 {
 458   {
 459     BI opval = 0;
 460     CPU (h_xbit) = opval;
 461     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 462   }
 463   {
 464     BI opval = 0;
 465     SET_H_INSN_PREFIXED_P (opval);
 466     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 467   }
 468 }
 469
 470 #undef FLD
 471 }
 472   NEXT (vpc);
 473
 474   CASE (sem, INSN_MOVE_B_R) : /* move.b move.m ${Rs},${Rd} */
 475 {
 476   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 477   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 478 #define FLD(f) abuf->fields.sfmt_add_b_r.f
 479   int UNUSED written = 0;
 480   IADDR UNUSED pc = abuf->addr;
 481   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 482
 483 {
 484   QI tmp_newval;
 485   tmp_newval = GET_H_GR (FLD (f_operand1));
 486 {
 487   SI tmp_oldregval;
 488   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
 489   {
 490     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
 491     SET_H_GR (FLD (f_operand2), opval);
 492     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 493   }
 494 }
 495 {
 496   {
 497     BI opval = LTQI (tmp_newval, 0);
 498     CPU (h_nbit) = opval;
 499     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 500   }
 501   {
 502     BI opval = ANDIF (EQQI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 503     CPU (h_zbit) = opval;
 504     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 505   }
 506 SET_H_CBIT_MOVE (0);
 507 SET_H_VBIT_MOVE (0);
 508 {
 509   {
 510     BI opval = 0;
 511     CPU (h_xbit) = opval;
 512     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 513   }
 514   {
 515     BI opval = 0;
 516     SET_H_INSN_PREFIXED_P (opval);
 517     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 518   }
 519 }
 520 }
 521 }
 522
 523 #undef FLD
 524 }
 525   NEXT (vpc);
 526
 527   CASE (sem, INSN_MOVE_W_R) : /* move.w move.m ${Rs},${Rd} */
 528 {
 529   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 530   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 531 #define FLD(f) abuf->fields.sfmt_add_b_r.f
 532   int UNUSED written = 0;
 533   IADDR UNUSED pc = abuf->addr;
 534   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 535
 536 {
 537   HI tmp_newval;
 538   tmp_newval = GET_H_GR (FLD (f_operand1));
 539 {
 540   SI tmp_oldregval;
 541   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
 542   {
 543     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
 544     SET_H_GR (FLD (f_operand2), opval);
 545     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 546   }
 547 }
 548 {
 549   {
 550     BI opval = LTHI (tmp_newval, 0);
 551     CPU (h_nbit) = opval;
 552     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 553   }
 554   {
 555     BI opval = ANDIF (EQHI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 556     CPU (h_zbit) = opval;
 557     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 558   }
 559 SET_H_CBIT_MOVE (0);
 560 SET_H_VBIT_MOVE (0);
 561 {
 562   {
 563     BI opval = 0;
 564     CPU (h_xbit) = opval;
 565     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 566   }
 567   {
 568     BI opval = 0;
 569     SET_H_INSN_PREFIXED_P (opval);
 570     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 571   }
 572 }
 573 }
 574 }
 575
 576 #undef FLD
 577 }
 578   NEXT (vpc);
 579
 580   CASE (sem, INSN_MOVE_D_R) : /* move.d move.m ${Rs},${Rd} */
 581 {
 582   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 583   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 584 #define FLD(f) abuf->fields.sfmt_add_b_r.f
 585   int UNUSED written = 0;
 586   IADDR UNUSED pc = abuf->addr;
 587   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 588
 589 {
 590   SI tmp_newval;
 591   tmp_newval = GET_H_GR (FLD (f_operand1));
 592   {
 593     SI opval = tmp_newval;
 594     SET_H_GR (FLD (f_operand2), opval);
 595     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 596   }
 597 {
 598   {
 599     BI opval = LTSI (tmp_newval, 0);
 600     CPU (h_nbit) = opval;
 601     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 602   }
 603   {
 604     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 605     CPU (h_zbit) = opval;
 606     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 607   }
 608 SET_H_CBIT_MOVE (0);
 609 SET_H_VBIT_MOVE (0);
 610 {
 611   {
 612     BI opval = 0;
 613     CPU (h_xbit) = opval;
 614     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 615   }
 616   {
 617     BI opval = 0;
 618     SET_H_INSN_PREFIXED_P (opval);
 619     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 620   }
 621 }
 622 }
 623 }
 624
 625 #undef FLD
 626 }
 627   NEXT (vpc);
 628
 629   CASE (sem, INSN_MOVEPCR) : /* move.d PC,${Rd} */
 630 {
 631   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 632   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 633 #define FLD(f) abuf->fields.sfmt_moveq.f
 634   int UNUSED written = 0;
 635   IADDR UNUSED pc = abuf->addr;
 636   SEM_BRANCH_INIT
 637   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 638
 639 {
 640   SI tmp_pcval;
 641   tmp_pcval = ADDSI (pc, 2);
 642   {
 643     SI opval = tmp_pcval;
 644     SET_H_GR (FLD (f_operand2), opval);
 645     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 646   }
 647 {
 648   {
 649     BI opval = LTSI (tmp_pcval, 0);
 650     CPU (h_nbit) = opval;
 651     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 652   }
 653   {
 654     BI opval = ANDIF (EQSI (tmp_pcval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 655     CPU (h_zbit) = opval;
 656     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 657   }
 658 SET_H_CBIT_MOVE (0);
 659 SET_H_VBIT_MOVE (0);
 660 {
 661   {
 662     BI opval = 0;
 663     CPU (h_xbit) = opval;
 664     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 665   }
 666   {
 667     BI opval = 0;
 668     SET_H_INSN_PREFIXED_P (opval);
 669     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 670   }
 671 }
 672 }
 673 }
 674
 675   SEM_BRANCH_FINI (vpc);
 676 #undef FLD
 677 }
 678   NEXT (vpc);
 679
 680   CASE (sem, INSN_MOVEQ) : /* moveq $i,$Rd */
 681 {
 682   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 683   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 684 #define FLD(f) abuf->fields.sfmt_moveq.f
 685   int UNUSED written = 0;
 686   IADDR UNUSED pc = abuf->addr;
 687   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 688
 689 {
 690   SI tmp_newval;
 691   tmp_newval = FLD (f_s6);
 692   {
 693     SI opval = tmp_newval;
 694     SET_H_GR (FLD (f_operand2), opval);
 695     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 696   }
 697 {
 698 SET_H_NBIT_MOVE (LTSI (tmp_newval, 0));
 699 SET_H_ZBIT_MOVE (ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))));
 700 SET_H_CBIT_MOVE (0);
 701 SET_H_VBIT_MOVE (0);
 702 {
 703   {
 704     BI opval = 0;
 705     CPU (h_xbit) = opval;
 706     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 707   }
 708   {
 709     BI opval = 0;
 710     SET_H_INSN_PREFIXED_P (opval);
 711     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 712   }
 713 }
 714 }
 715 }
 716
 717 #undef FLD
 718 }
 719   NEXT (vpc);
 720
 721   CASE (sem, INSN_MOVS_B_R) : /* movs.b movs.m ${Rs},${Rd} */
 722 {
 723   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 724   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 725 #define FLD(f) abuf->fields.sfmt_muls_b.f
 726   int UNUSED written = 0;
 727   IADDR UNUSED pc = abuf->addr;
 728   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 729
 730 {
 731   QI tmp_newval;
 732   tmp_newval = GET_H_GR (FLD (f_operand1));
 733   {
 734     SI opval = EXTQISI (tmp_newval);
 735     SET_H_GR (FLD (f_operand2), opval);
 736     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 737   }
 738 {
 739   {
 740     BI opval = LTSI (tmp_newval, 0);
 741     CPU (h_nbit) = opval;
 742     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 743   }
 744   {
 745     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 746     CPU (h_zbit) = opval;
 747     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 748   }
 749 SET_H_CBIT_MOVE (0);
 750 SET_H_VBIT_MOVE (0);
 751 {
 752   {
 753     BI opval = 0;
 754     CPU (h_xbit) = opval;
 755     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 756   }
 757   {
 758     BI opval = 0;
 759     SET_H_INSN_PREFIXED_P (opval);
 760     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 761   }
 762 }
 763 }
 764 }
 765
 766 #undef FLD
 767 }
 768   NEXT (vpc);
 769
 770   CASE (sem, INSN_MOVS_W_R) : /* movs.w movs.m ${Rs},${Rd} */
 771 {
 772   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 773   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 774 #define FLD(f) abuf->fields.sfmt_muls_b.f
 775   int UNUSED written = 0;
 776   IADDR UNUSED pc = abuf->addr;
 777   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 778
 779 {
 780   HI tmp_newval;
 781   tmp_newval = GET_H_GR (FLD (f_operand1));
 782   {
 783     SI opval = EXTHISI (tmp_newval);
 784     SET_H_GR (FLD (f_operand2), opval);
 785     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 786   }
 787 {
 788   {
 789     BI opval = LTSI (tmp_newval, 0);
 790     CPU (h_nbit) = opval;
 791     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 792   }
 793   {
 794     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 795     CPU (h_zbit) = opval;
 796     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 797   }
 798 SET_H_CBIT_MOVE (0);
 799 SET_H_VBIT_MOVE (0);
 800 {
 801   {
 802     BI opval = 0;
 803     CPU (h_xbit) = opval;
 804     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 805   }
 806   {
 807     BI opval = 0;
 808     SET_H_INSN_PREFIXED_P (opval);
 809     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 810   }
 811 }
 812 }
 813 }
 814
 815 #undef FLD
 816 }
 817   NEXT (vpc);
 818
 819   CASE (sem, INSN_MOVU_B_R) : /* movu.b movu.m ${Rs},${Rd} */
 820 {
 821   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 822   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 823 #define FLD(f) abuf->fields.sfmt_muls_b.f
 824   int UNUSED written = 0;
 825   IADDR UNUSED pc = abuf->addr;
 826   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 827
 828 {
 829   QI tmp_newval;
 830   tmp_newval = GET_H_GR (FLD (f_operand1));
 831   {
 832     SI opval = ZEXTQISI (tmp_newval);
 833     SET_H_GR (FLD (f_operand2), opval);
 834     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 835   }
 836 {
 837   {
 838     BI opval = LTSI (tmp_newval, 0);
 839     CPU (h_nbit) = opval;
 840     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 841   }
 842   {
 843     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 844     CPU (h_zbit) = opval;
 845     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 846   }
 847 SET_H_CBIT_MOVE (0);
 848 SET_H_VBIT_MOVE (0);
 849 {
 850   {
 851     BI opval = 0;
 852     CPU (h_xbit) = opval;
 853     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 854   }
 855   {
 856     BI opval = 0;
 857     SET_H_INSN_PREFIXED_P (opval);
 858     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 859   }
 860 }
 861 }
 862 }
 863
 864 #undef FLD
 865 }
 866   NEXT (vpc);
 867
 868   CASE (sem, INSN_MOVU_W_R) : /* movu.w movu.m ${Rs},${Rd} */
 869 {
 870   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 871   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 872 #define FLD(f) abuf->fields.sfmt_muls_b.f
 873   int UNUSED written = 0;
 874   IADDR UNUSED pc = abuf->addr;
 875   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 876
 877 {
 878   HI tmp_newval;
 879   tmp_newval = GET_H_GR (FLD (f_operand1));
 880   {
 881     SI opval = ZEXTHISI (tmp_newval);
 882     SET_H_GR (FLD (f_operand2), opval);
 883     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 884   }
 885 {
 886   {
 887     BI opval = LTSI (tmp_newval, 0);
 888     CPU (h_nbit) = opval;
 889     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 890   }
 891   {
 892     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 893     CPU (h_zbit) = opval;
 894     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 895   }
 896 SET_H_CBIT_MOVE (0);
 897 SET_H_VBIT_MOVE (0);
 898 {
 899   {
 900     BI opval = 0;
 901     CPU (h_xbit) = opval;
 902     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 903   }
 904   {
 905     BI opval = 0;
 906     SET_H_INSN_PREFIXED_P (opval);
 907     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 908   }
 909 }
 910 }
 911 }
 912
 913 #undef FLD
 914 }
 915   NEXT (vpc);
 916
 917   CASE (sem, INSN_MOVECBR) : /* move.b ${sconst8},${Rd} */
 918 {
 919   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 920   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 921 #define FLD(f) abuf->fields.sfmt_addcbr.f
 922   int UNUSED written = 0;
 923   IADDR UNUSED pc = abuf->addr;
 924   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 925
 926 {
 927   QI tmp_newval;
 928   tmp_newval = FLD (f_indir_pc__byte);
 929 {
 930   SI tmp_oldregval;
 931   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
 932   {
 933     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
 934     SET_H_GR (FLD (f_operand2), opval);
 935     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 936   }
 937 }
 938 {
 939   {
 940     BI opval = LTQI (tmp_newval, 0);
 941     CPU (h_nbit) = opval;
 942     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 943   }
 944   {
 945     BI opval = ANDIF (EQQI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 946     CPU (h_zbit) = opval;
 947     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 948   }
 949 SET_H_CBIT_MOVE (0);
 950 SET_H_VBIT_MOVE (0);
 951 {
 952   {
 953     BI opval = 0;
 954     CPU (h_xbit) = opval;
 955     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 956   }
 957   {
 958     BI opval = 0;
 959     SET_H_INSN_PREFIXED_P (opval);
 960     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 961   }
 962 }
 963 }
 964 }
 965
 966 #undef FLD
 967 }
 968   NEXT (vpc);
 969
 970   CASE (sem, INSN_MOVECWR) : /* move.w ${sconst16},${Rd} */
 971 {
 972   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 973   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 974 #define FLD(f) abuf->fields.sfmt_addcwr.f
 975   int UNUSED written = 0;
 976   IADDR UNUSED pc = abuf->addr;
 977   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 978
 979 {
 980   HI tmp_newval;
 981   tmp_newval = FLD (f_indir_pc__word);
 982 {
 983   SI tmp_oldregval;
 984   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
 985   {
 986     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
 987     SET_H_GR (FLD (f_operand2), opval);
 988     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 989   }
 990 }
 991 {
 992   {
 993     BI opval = LTHI (tmp_newval, 0);
 994     CPU (h_nbit) = opval;
 995     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 996   }
 997   {
 998     BI opval = ANDIF (EQHI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 999     CPU (h_zbit) = opval;
1000     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1001   }
1002 SET_H_CBIT_MOVE (0);
1003 SET_H_VBIT_MOVE (0);
1004 {
1005   {
1006     BI opval = 0;
1007     CPU (h_xbit) = opval;
1008     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1009   }
1010   {
1011     BI opval = 0;
1012     SET_H_INSN_PREFIXED_P (opval);
1013     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1014   }
1015 }
1016 }
1017 }
1018
1019 #undef FLD
1020 }
1021   NEXT (vpc);
1022
1023   CASE (sem, INSN_MOVECDR) : /* move.d ${const32},${Rd} */
1024 {
1025   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1026   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1027 #define FLD(f) abuf->fields.sfmt_bound_cd.f
1028   int UNUSED written = 0;
1029   IADDR UNUSED pc = abuf->addr;
1030   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
1031
1032 {
1033   SI tmp_newval;
1034   tmp_newval = FLD (f_indir_pc__dword);
1035   {
1036     SI opval = tmp_newval;
1037     SET_H_GR (FLD (f_operand2), opval);
1038     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1039   }
1040 {
1041   {
1042     BI opval = LTSI (tmp_newval, 0);
1043     CPU (h_nbit) = opval;
1044     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1045   }
1046   {
1047     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1048     CPU (h_zbit) = opval;
1049     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1050   }
1051 SET_H_CBIT_MOVE (0);
1052 SET_H_VBIT_MOVE (0);
1053 {
1054   {
1055     BI opval = 0;
1056     CPU (h_xbit) = opval;
1057     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1058   }
1059   {
1060     BI opval = 0;
1061     SET_H_INSN_PREFIXED_P (opval);
1062     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1063   }
1064 }
1065 }
1066 }
1067
1068 #undef FLD
1069 }
1070   NEXT (vpc);
1071
1072   CASE (sem, INSN_MOVSCBR) : /* movs.b ${sconst8},${Rd} */
1073 {
1074   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1075   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1076 #define FLD(f) abuf->fields.sfmt_bound_cb.f
1077   int UNUSED written = 0;
1078   IADDR UNUSED pc = abuf->addr;
1079   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1080
1081 {
1082   SI tmp_newval;
1083   tmp_newval = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
1084   {
1085     SI opval = tmp_newval;
1086     SET_H_GR (FLD (f_operand2), opval);
1087     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1088   }
1089 {
1090   {
1091     BI opval = LTSI (tmp_newval, 0);
1092     CPU (h_nbit) = opval;
1093     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1094   }
1095   {
1096     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1097     CPU (h_zbit) = opval;
1098     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1099   }
1100 SET_H_CBIT_MOVE (0);
1101 SET_H_VBIT_MOVE (0);
1102 {
1103   {
1104     BI opval = 0;
1105     CPU (h_xbit) = opval;
1106     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1107   }
1108   {
1109     BI opval = 0;
1110     SET_H_INSN_PREFIXED_P (opval);
1111     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1112   }
1113 }
1114 }
1115 }
1116
1117 #undef FLD
1118 }
1119   NEXT (vpc);
1120
1121   CASE (sem, INSN_MOVSCWR) : /* movs.w ${sconst16},${Rd} */
1122 {
1123   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1124   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1125 #define FLD(f) abuf->fields.sfmt_bound_cw.f
1126   int UNUSED written = 0;
1127   IADDR UNUSED pc = abuf->addr;
1128   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1129
1130 {
1131   SI tmp_newval;
1132   tmp_newval = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
1133   {
1134     SI opval = tmp_newval;
1135     SET_H_GR (FLD (f_operand2), opval);
1136     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1137   }
1138 {
1139   {
1140     BI opval = LTSI (tmp_newval, 0);
1141     CPU (h_nbit) = opval;
1142     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1143   }
1144   {
1145     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1146     CPU (h_zbit) = opval;
1147     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1148   }
1149 SET_H_CBIT_MOVE (0);
1150 SET_H_VBIT_MOVE (0);
1151 {
1152   {
1153     BI opval = 0;
1154     CPU (h_xbit) = opval;
1155     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1156   }
1157   {
1158     BI opval = 0;
1159     SET_H_INSN_PREFIXED_P (opval);
1160     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1161   }
1162 }
1163 }
1164 }
1165
1166 #undef FLD
1167 }
1168   NEXT (vpc);
1169
1170   CASE (sem, INSN_MOVUCBR) : /* movu.b ${uconst8},${Rd} */
1171 {
1172   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1173   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1174 #define FLD(f) abuf->fields.sfmt_bound_cb.f
1175   int UNUSED written = 0;
1176   IADDR UNUSED pc = abuf->addr;
1177   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1178
1179 {
1180   SI tmp_newval;
1181   tmp_newval = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
1182   {
1183     SI opval = tmp_newval;
1184     SET_H_GR (FLD (f_operand2), opval);
1185     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1186   }
1187 {
1188   {
1189     BI opval = LTSI (tmp_newval, 0);
1190     CPU (h_nbit) = opval;
1191     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1192   }
1193   {
1194     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1195     CPU (h_zbit) = opval;
1196     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1197   }
1198 SET_H_CBIT_MOVE (0);
1199 SET_H_VBIT_MOVE (0);
1200 {
1201   {
1202     BI opval = 0;
1203     CPU (h_xbit) = opval;
1204     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1205   }
1206   {
1207     BI opval = 0;
1208     SET_H_INSN_PREFIXED_P (opval);
1209     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1210   }
1211 }
1212 }
1213 }
1214
1215 #undef FLD
1216 }
1217   NEXT (vpc);
1218
1219   CASE (sem, INSN_MOVUCWR) : /* movu.w ${uconst16},${Rd} */
1220 {
1221   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1222   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1223 #define FLD(f) abuf->fields.sfmt_bound_cw.f
1224   int UNUSED written = 0;
1225   IADDR UNUSED pc = abuf->addr;
1226   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1227
1228 {
1229   SI tmp_newval;
1230   tmp_newval = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
1231   {
1232     SI opval = tmp_newval;
1233     SET_H_GR (FLD (f_operand2), opval);
1234     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1235   }
1236 {
1237   {
1238     BI opval = LTSI (tmp_newval, 0);
1239     CPU (h_nbit) = opval;
1240     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1241   }
1242   {
1243     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1244     CPU (h_zbit) = opval;
1245     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1246   }
1247 SET_H_CBIT_MOVE (0);
1248 SET_H_VBIT_MOVE (0);
1249 {
1250   {
1251     BI opval = 0;
1252     CPU (h_xbit) = opval;
1253     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1254   }
1255   {
1256     BI opval = 0;
1257     SET_H_INSN_PREFIXED_P (opval);
1258     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1259   }
1260 }
1261 }
1262 }
1263
1264 #undef FLD
1265 }
1266   NEXT (vpc);
1267
1268   CASE (sem, INSN_ADDQ) : /* addq $j,$Rd */
1269 {
1270   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1271   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1272 #define FLD(f) abuf->fields.sfmt_addq.f
1273   int UNUSED written = 0;
1274   IADDR UNUSED pc = abuf->addr;
1275   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1276
1277 {
1278   SI tmp_tmpopd;
1279   SI tmp_tmpops;
1280   BI tmp_carry;
1281   SI tmp_newval;
1282   tmp_tmpops = FLD (f_u6);
1283   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1284   tmp_carry = CPU (h_cbit);
1285   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1286   {
1287     SI opval = tmp_newval;
1288     SET_H_GR (FLD (f_operand2), opval);
1289     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1290   }
1291 {
1292   {
1293     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
1294     CPU (h_cbit) = opval;
1295     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1296   }
1297   {
1298     BI opval = LTSI (tmp_newval, 0);
1299     CPU (h_nbit) = opval;
1300     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1301   }
1302   {
1303     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1304     CPU (h_zbit) = opval;
1305     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1306   }
1307   {
1308     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1309     CPU (h_vbit) = opval;
1310     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1311   }
1312 {
1313   {
1314     BI opval = 0;
1315     CPU (h_xbit) = opval;
1316     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1317   }
1318   {
1319     BI opval = 0;
1320     SET_H_INSN_PREFIXED_P (opval);
1321     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1322   }
1323 }
1324 }
1325 }
1326
1327 #undef FLD
1328 }
1329   NEXT (vpc);
1330
1331   CASE (sem, INSN_SUBQ) : /* subq $j,$Rd */
1332 {
1333   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1334   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1335 #define FLD(f) abuf->fields.sfmt_addq.f
1336   int UNUSED written = 0;
1337   IADDR UNUSED pc = abuf->addr;
1338   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1339
1340 {
1341   SI tmp_tmpopd;
1342   SI tmp_tmpops;
1343   BI tmp_carry;
1344   SI tmp_newval;
1345   tmp_tmpops = FLD (f_u6);
1346   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1347   tmp_carry = CPU (h_cbit);
1348   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1349   {
1350     SI opval = tmp_newval;
1351     SET_H_GR (FLD (f_operand2), opval);
1352     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1353   }
1354 {
1355   {
1356     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1357     CPU (h_cbit) = opval;
1358     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1359   }
1360   {
1361     BI opval = LTSI (tmp_newval, 0);
1362     CPU (h_nbit) = opval;
1363     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1364   }
1365   {
1366     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1367     CPU (h_zbit) = opval;
1368     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1369   }
1370   {
1371     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1372     CPU (h_vbit) = opval;
1373     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1374   }
1375 {
1376   {
1377     BI opval = 0;
1378     CPU (h_xbit) = opval;
1379     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1380   }
1381   {
1382     BI opval = 0;
1383     SET_H_INSN_PREFIXED_P (opval);
1384     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1385   }
1386 }
1387 }
1388 }
1389
1390 #undef FLD
1391 }
1392   NEXT (vpc);
1393
1394   CASE (sem, INSN_CMP_R_B_R) : /* cmp-r.b $Rs,$Rd */
1395 {
1396   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1397   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1398 #define FLD(f) abuf->fields.sfmt_add_b_r.f
1399   int UNUSED written = 0;
1400   IADDR UNUSED pc = abuf->addr;
1401   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1402
1403 {
1404   QI tmp_tmpopd;
1405   QI tmp_tmpops;
1406   BI tmp_carry;
1407   QI tmp_newval;
1408   tmp_tmpops = GET_H_GR (FLD (f_operand1));
1409   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1410   tmp_carry = CPU (h_cbit);
1411   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1412 ((void) 0); /*nop*/
1413 {
1414   {
1415     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
1416     CPU (h_cbit) = opval;
1417     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1418   }
1419   {
1420     BI opval = LTQI (tmp_newval, 0);
1421     CPU (h_nbit) = opval;
1422     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1423   }
1424   {
1425     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1426     CPU (h_zbit) = opval;
1427     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1428   }
1429   {
1430     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
1431     CPU (h_vbit) = opval;
1432     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1433   }
1434 {
1435   {
1436     BI opval = 0;
1437     CPU (h_xbit) = opval;
1438     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1439   }
1440   {
1441     BI opval = 0;
1442     SET_H_INSN_PREFIXED_P (opval);
1443     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1444   }
1445 }
1446 }
1447 }
1448
1449 #undef FLD
1450 }
1451   NEXT (vpc);
1452
1453   CASE (sem, INSN_CMP_R_W_R) : /* cmp-r.w $Rs,$Rd */
1454 {
1455   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1456   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1457 #define FLD(f) abuf->fields.sfmt_add_b_r.f
1458   int UNUSED written = 0;
1459   IADDR UNUSED pc = abuf->addr;
1460   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1461
1462 {
1463   HI tmp_tmpopd;
1464   HI tmp_tmpops;
1465   BI tmp_carry;
1466   HI tmp_newval;
1467   tmp_tmpops = GET_H_GR (FLD (f_operand1));
1468   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1469   tmp_carry = CPU (h_cbit);
1470   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1471 ((void) 0); /*nop*/
1472 {
1473   {
1474     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
1475     CPU (h_cbit) = opval;
1476     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1477   }
1478   {
1479     BI opval = LTHI (tmp_newval, 0);
1480     CPU (h_nbit) = opval;
1481     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1482   }
1483   {
1484     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1485     CPU (h_zbit) = opval;
1486     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1487   }
1488   {
1489     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
1490     CPU (h_vbit) = opval;
1491     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1492   }
1493 {
1494   {
1495     BI opval = 0;
1496     CPU (h_xbit) = opval;
1497     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1498   }
1499   {
1500     BI opval = 0;
1501     SET_H_INSN_PREFIXED_P (opval);
1502     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1503   }
1504 }
1505 }
1506 }
1507
1508 #undef FLD
1509 }
1510   NEXT (vpc);
1511
1512   CASE (sem, INSN_CMP_R_D_R) : /* cmp-r.d $Rs,$Rd */
1513 {
1514   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1515   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1516 #define FLD(f) abuf->fields.sfmt_add_b_r.f
1517   int UNUSED written = 0;
1518   IADDR UNUSED pc = abuf->addr;
1519   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1520
1521 {
1522   SI tmp_tmpopd;
1523   SI tmp_tmpops;
1524   BI tmp_carry;
1525   SI tmp_newval;
1526   tmp_tmpops = GET_H_GR (FLD (f_operand1));
1527   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1528   tmp_carry = CPU (h_cbit);
1529   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1530 ((void) 0); /*nop*/
1531 {
1532   {
1533     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1534     CPU (h_cbit) = opval;
1535     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1536   }
1537   {
1538     BI opval = LTSI (tmp_newval, 0);
1539     CPU (h_nbit) = opval;
1540     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1541   }
1542   {
1543     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1544     CPU (h_zbit) = opval;
1545     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1546   }
1547   {
1548     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1549     CPU (h_vbit) = opval;
1550     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1551   }
1552 {
1553   {
1554     BI opval = 0;
1555     CPU (h_xbit) = opval;
1556     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1557   }
1558   {
1559     BI opval = 0;
1560     SET_H_INSN_PREFIXED_P (opval);
1561     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1562   }
1563 }
1564 }
1565 }
1566
1567 #undef FLD
1568 }
1569   NEXT (vpc);
1570
1571   CASE (sem, INSN_CMP_M_B_M) : /* cmp-m.b [${Rs}${inc}],${Rd} */
1572 {
1573   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1574   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1575 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
1576   int UNUSED written = 0;
1577   IADDR UNUSED pc = abuf->addr;
1578   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1579
1580 {
1581   QI tmp_tmpopd;
1582   QI tmp_tmpops;
1583   BI tmp_carry;
1584   QI tmp_newval;
1585   tmp_tmpops = ({   SI tmp_addr;
1586   QI tmp_tmp_mem;
1587   BI tmp_postinc;
1588   tmp_postinc = FLD (f_memmode);
1589 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
1590 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
1591 ; if (NEBI (tmp_postinc, 0)) {
1592 {
1593 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
1594   tmp_addr = ADDSI (tmp_addr, 1);
1595 }
1596   {
1597     SI opval = tmp_addr;
1598     SET_H_GR (FLD (f_operand1), opval);
1599     written |= (1 << 9);
1600     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1601   }
1602 }
1603 }
1604 ; tmp_tmp_mem; });
1605   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1606   tmp_carry = CPU (h_cbit);
1607   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1608 ((void) 0); /*nop*/
1609 {
1610   {
1611     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
1612     CPU (h_cbit) = opval;
1613     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1614   }
1615   {
1616     BI opval = LTQI (tmp_newval, 0);
1617     CPU (h_nbit) = opval;
1618     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1619   }
1620   {
1621     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1622     CPU (h_zbit) = opval;
1623     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1624   }
1625   {
1626     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
1627     CPU (h_vbit) = opval;
1628     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1629   }
1630 {
1631   {
1632     BI opval = 0;
1633     CPU (h_xbit) = opval;
1634     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1635   }
1636   {
1637     BI opval = 0;
1638     SET_H_INSN_PREFIXED_P (opval);
1639     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1640   }
1641 }
1642 }
1643 }
1644
1645   abuf->written = written;
1646 #undef FLD
1647 }
1648   NEXT (vpc);
1649
1650   CASE (sem, INSN_CMP_M_W_M) : /* cmp-m.w [${Rs}${inc}],${Rd} */
1651 {
1652   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1653   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1654 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
1655   int UNUSED written = 0;
1656   IADDR UNUSED pc = abuf->addr;
1657   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1658
1659 {
1660   HI tmp_tmpopd;
1661   HI tmp_tmpops;
1662   BI tmp_carry;
1663   HI tmp_newval;
1664   tmp_tmpops = ({   SI tmp_addr;
1665   HI tmp_tmp_mem;
1666   BI tmp_postinc;
1667   tmp_postinc = FLD (f_memmode);
1668 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
1669 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
1670 ; if (NEBI (tmp_postinc, 0)) {
1671 {
1672 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
1673   tmp_addr = ADDSI (tmp_addr, 2);
1674 }
1675   {
1676     SI opval = tmp_addr;
1677     SET_H_GR (FLD (f_operand1), opval);
1678     written |= (1 << 9);
1679     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1680   }
1681 }
1682 }
1683 ; tmp_tmp_mem; });
1684   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1685   tmp_carry = CPU (h_cbit);
1686   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1687 ((void) 0); /*nop*/
1688 {
1689   {
1690     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
1691     CPU (h_cbit) = opval;
1692     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1693   }
1694   {
1695     BI opval = LTHI (tmp_newval, 0);
1696     CPU (h_nbit) = opval;
1697     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1698   }
1699   {
1700     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1701     CPU (h_zbit) = opval;
1702     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1703   }
1704   {
1705     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
1706     CPU (h_vbit) = opval;
1707     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1708   }
1709 {
1710   {
1711     BI opval = 0;
1712     CPU (h_xbit) = opval;
1713     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1714   }
1715   {
1716     BI opval = 0;
1717     SET_H_INSN_PREFIXED_P (opval);
1718     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1719   }
1720 }
1721 }
1722 }
1723
1724   abuf->written = written;
1725 #undef FLD
1726 }
1727   NEXT (vpc);
1728
1729   CASE (sem, INSN_CMP_M_D_M) : /* cmp-m.d [${Rs}${inc}],${Rd} */
1730 {
1731   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1732   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1733 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
1734   int UNUSED written = 0;
1735   IADDR UNUSED pc = abuf->addr;
1736   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1737
1738 {
1739   SI tmp_tmpopd;
1740   SI tmp_tmpops;
1741   BI tmp_carry;
1742   SI tmp_newval;
1743   tmp_tmpops = ({   SI tmp_addr;
1744   SI tmp_tmp_mem;
1745   BI tmp_postinc;
1746   tmp_postinc = FLD (f_memmode);
1747 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
1748 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
1749 ; if (NEBI (tmp_postinc, 0)) {
1750 {
1751 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
1752   tmp_addr = ADDSI (tmp_addr, 4);
1753 }
1754   {
1755     SI opval = tmp_addr;
1756     SET_H_GR (FLD (f_operand1), opval);
1757     written |= (1 << 9);
1758     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1759   }
1760 }
1761 }
1762 ; tmp_tmp_mem; });
1763   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1764   tmp_carry = CPU (h_cbit);
1765   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1766 ((void) 0); /*nop*/
1767 {
1768   {
1769     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1770     CPU (h_cbit) = opval;
1771     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1772   }
1773   {
1774     BI opval = LTSI (tmp_newval, 0);
1775     CPU (h_nbit) = opval;
1776     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1777   }
1778   {
1779     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1780     CPU (h_zbit) = opval;
1781     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1782   }
1783   {
1784     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1785     CPU (h_vbit) = opval;
1786     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1787   }
1788 {
1789   {
1790     BI opval = 0;
1791     CPU (h_xbit) = opval;
1792     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1793   }
1794   {
1795     BI opval = 0;
1796     SET_H_INSN_PREFIXED_P (opval);
1797     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1798   }
1799 }
1800 }
1801 }
1802
1803   abuf->written = written;
1804 #undef FLD
1805 }
1806   NEXT (vpc);
1807
1808   CASE (sem, INSN_CMPCBR) : /* cmp.b $sconst8,$Rd */
1809 {
1810   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1811   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1812 #define FLD(f) abuf->fields.sfmt_bound_cb.f
1813   int UNUSED written = 0;
1814   IADDR UNUSED pc = abuf->addr;
1815   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1816
1817 {
1818   QI tmp_tmpopd;
1819   QI tmp_tmpops;
1820   BI tmp_carry;
1821   QI tmp_newval;
1822   tmp_tmpops = TRUNCSIQI (FLD (f_indir_pc__byte));
1823   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1824   tmp_carry = CPU (h_cbit);
1825   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1826 ((void) 0); /*nop*/
1827 {
1828   {
1829     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
1830     CPU (h_cbit) = opval;
1831     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1832   }
1833   {
1834     BI opval = LTQI (tmp_newval, 0);
1835     CPU (h_nbit) = opval;
1836     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1837   }
1838   {
1839     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1840     CPU (h_zbit) = opval;
1841     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1842   }
1843   {
1844     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
1845     CPU (h_vbit) = opval;
1846     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1847   }
1848 {
1849   {
1850     BI opval = 0;
1851     CPU (h_xbit) = opval;
1852     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1853   }
1854   {
1855     BI opval = 0;
1856     SET_H_INSN_PREFIXED_P (opval);
1857     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1858   }
1859 }
1860 }
1861 }
1862
1863 #undef FLD
1864 }
1865   NEXT (vpc);
1866
1867   CASE (sem, INSN_CMPCWR) : /* cmp.w $sconst16,$Rd */
1868 {
1869   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1870   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1871 #define FLD(f) abuf->fields.sfmt_bound_cw.f
1872   int UNUSED written = 0;
1873   IADDR UNUSED pc = abuf->addr;
1874   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1875
1876 {
1877   HI tmp_tmpopd;
1878   HI tmp_tmpops;
1879   BI tmp_carry;
1880   HI tmp_newval;
1881   tmp_tmpops = TRUNCSIHI (FLD (f_indir_pc__word));
1882   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1883   tmp_carry = CPU (h_cbit);
1884   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1885 ((void) 0); /*nop*/
1886 {
1887   {
1888     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
1889     CPU (h_cbit) = opval;
1890     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1891   }
1892   {
1893     BI opval = LTHI (tmp_newval, 0);
1894     CPU (h_nbit) = opval;
1895     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1896   }
1897   {
1898     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1899     CPU (h_zbit) = opval;
1900     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1901   }
1902   {
1903     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
1904     CPU (h_vbit) = opval;
1905     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1906   }
1907 {
1908   {
1909     BI opval = 0;
1910     CPU (h_xbit) = opval;
1911     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1912   }
1913   {
1914     BI opval = 0;
1915     SET_H_INSN_PREFIXED_P (opval);
1916     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1917   }
1918 }
1919 }
1920 }
1921
1922 #undef FLD
1923 }
1924   NEXT (vpc);
1925
1926   CASE (sem, INSN_CMPCDR) : /* cmp.d $const32,$Rd */
1927 {
1928   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1929   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1930 #define FLD(f) abuf->fields.sfmt_bound_cd.f
1931   int UNUSED written = 0;
1932   IADDR UNUSED pc = abuf->addr;
1933   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
1934
1935 {
1936   SI tmp_tmpopd;
1937   SI tmp_tmpops;
1938   BI tmp_carry;
1939   SI tmp_newval;
1940   tmp_tmpops = FLD (f_indir_pc__dword);
1941   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1942   tmp_carry = CPU (h_cbit);
1943   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1944 ((void) 0); /*nop*/
1945 {
1946   {
1947     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1948     CPU (h_cbit) = opval;
1949     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1950   }
1951   {
1952     BI opval = LTSI (tmp_newval, 0);
1953     CPU (h_nbit) = opval;
1954     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1955   }
1956   {
1957     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1958     CPU (h_zbit) = opval;
1959     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1960   }
1961   {
1962     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1963     CPU (h_vbit) = opval;
1964     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1965   }
1966 {
1967   {
1968     BI opval = 0;
1969     CPU (h_xbit) = opval;
1970     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1971   }
1972   {
1973     BI opval = 0;
1974     SET_H_INSN_PREFIXED_P (opval);
1975     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1976   }
1977 }
1978 }
1979 }
1980
1981 #undef FLD
1982 }
1983   NEXT (vpc);
1984
1985   CASE (sem, INSN_CMPQ) : /* cmpq $i,$Rd */
1986 {
1987   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1988   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1989 #define FLD(f) abuf->fields.sfmt_andq.f
1990   int UNUSED written = 0;
1991   IADDR UNUSED pc = abuf->addr;
1992   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1993
1994 {
1995   SI tmp_tmpopd;
1996   SI tmp_tmpops;
1997   BI tmp_carry;
1998   SI tmp_newval;
1999   tmp_tmpops = FLD (f_s6);
2000   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2001   tmp_carry = CPU (h_cbit);
2002   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2003 ((void) 0); /*nop*/
2004 {
2005   {
2006     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2007     CPU (h_cbit) = opval;
2008     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2009   }
2010   {
2011     BI opval = LTSI (tmp_newval, 0);
2012     CPU (h_nbit) = opval;
2013     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2014   }
2015   {
2016     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2017     CPU (h_zbit) = opval;
2018     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2019   }
2020   {
2021     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2022     CPU (h_vbit) = opval;
2023     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2024   }
2025 {
2026   {
2027     BI opval = 0;
2028     CPU (h_xbit) = opval;
2029     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2030   }
2031   {
2032     BI opval = 0;
2033     SET_H_INSN_PREFIXED_P (opval);
2034     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2035   }
2036 }
2037 }
2038 }
2039
2040 #undef FLD
2041 }
2042   NEXT (vpc);
2043
2044   CASE (sem, INSN_CMPS_M_B_M) : /* cmps-m.b [${Rs}${inc}],$Rd */
2045 {
2046   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2047   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2048 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
2049   int UNUSED written = 0;
2050   IADDR UNUSED pc = abuf->addr;
2051   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2052
2053 {
2054   SI tmp_tmpopd;
2055   SI tmp_tmpops;
2056   BI tmp_carry;
2057   SI tmp_newval;
2058   tmp_tmpops = EXTQISI (({   SI tmp_addr;
2059   QI tmp_tmp_mem;
2060   BI tmp_postinc;
2061   tmp_postinc = FLD (f_memmode);
2062 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2063 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2064 ; if (NEBI (tmp_postinc, 0)) {
2065 {
2066 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2067   tmp_addr = ADDSI (tmp_addr, 1);
2068 }
2069   {
2070     SI opval = tmp_addr;
2071     SET_H_GR (FLD (f_operand1), opval);
2072     written |= (1 << 9);
2073     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2074   }
2075 }
2076 }
2077 ; tmp_tmp_mem; }));
2078   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2079   tmp_carry = CPU (h_cbit);
2080   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2081 ((void) 0); /*nop*/
2082 {
2083   {
2084     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2085     CPU (h_cbit) = opval;
2086     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2087   }
2088   {
2089     BI opval = LTSI (tmp_newval, 0);
2090     CPU (h_nbit) = opval;
2091     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2092   }
2093   {
2094     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2095     CPU (h_zbit) = opval;
2096     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2097   }
2098   {
2099     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2100     CPU (h_vbit) = opval;
2101     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2102   }
2103 {
2104   {
2105     BI opval = 0;
2106     CPU (h_xbit) = opval;
2107     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2108   }
2109   {
2110     BI opval = 0;
2111     SET_H_INSN_PREFIXED_P (opval);
2112     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2113   }
2114 }
2115 }
2116 }
2117
2118   abuf->written = written;
2119 #undef FLD
2120 }
2121   NEXT (vpc);
2122
2123   CASE (sem, INSN_CMPS_M_W_M) : /* cmps-m.w [${Rs}${inc}],$Rd */
2124 {
2125   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2126   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2127 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
2128   int UNUSED written = 0;
2129   IADDR UNUSED pc = abuf->addr;
2130   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2131
2132 {
2133   SI tmp_tmpopd;
2134   SI tmp_tmpops;
2135   BI tmp_carry;
2136   SI tmp_newval;
2137   tmp_tmpops = EXTHISI (({   SI tmp_addr;
2138   HI tmp_tmp_mem;
2139   BI tmp_postinc;
2140   tmp_postinc = FLD (f_memmode);
2141 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2142 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2143 ; if (NEBI (tmp_postinc, 0)) {
2144 {
2145 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2146   tmp_addr = ADDSI (tmp_addr, 2);
2147 }
2148   {
2149     SI opval = tmp_addr;
2150     SET_H_GR (FLD (f_operand1), opval);
2151     written |= (1 << 9);
2152     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2153   }
2154 }
2155 }
2156 ; tmp_tmp_mem; }));
2157   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2158   tmp_carry = CPU (h_cbit);
2159   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2160 ((void) 0); /*nop*/
2161 {
2162   {
2163     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2164     CPU (h_cbit) = opval;
2165     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2166   }
2167   {
2168     BI opval = LTSI (tmp_newval, 0);
2169     CPU (h_nbit) = opval;
2170     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2171   }
2172   {
2173     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2174     CPU (h_zbit) = opval;
2175     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2176   }
2177   {
2178     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2179     CPU (h_vbit) = opval;
2180     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2181   }
2182 {
2183   {
2184     BI opval = 0;
2185     CPU (h_xbit) = opval;
2186     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2187   }
2188   {
2189     BI opval = 0;
2190     SET_H_INSN_PREFIXED_P (opval);
2191     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2192   }
2193 }
2194 }
2195 }
2196
2197   abuf->written = written;
2198 #undef FLD
2199 }
2200   NEXT (vpc);
2201
2202   CASE (sem, INSN_CMPSCBR) : /* [${Rs}${inc}],$Rd */
2203 {
2204   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2205   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2206 #define FLD(f) abuf->fields.sfmt_bound_cb.f
2207   int UNUSED written = 0;
2208   IADDR UNUSED pc = abuf->addr;
2209   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2210
2211 {
2212   SI tmp_tmpopd;
2213   SI tmp_tmpops;
2214   BI tmp_carry;
2215   SI tmp_newval;
2216   tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
2217   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2218   tmp_carry = CPU (h_cbit);
2219   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2220 ((void) 0); /*nop*/
2221 {
2222   {
2223     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2224     CPU (h_cbit) = opval;
2225     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2226   }
2227   {
2228     BI opval = LTSI (tmp_newval, 0);
2229     CPU (h_nbit) = opval;
2230     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2231   }
2232   {
2233     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2234     CPU (h_zbit) = opval;
2235     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2236   }
2237   {
2238     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2239     CPU (h_vbit) = opval;
2240     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2241   }
2242 {
2243   {
2244     BI opval = 0;
2245     CPU (h_xbit) = opval;
2246     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2247   }
2248   {
2249     BI opval = 0;
2250     SET_H_INSN_PREFIXED_P (opval);
2251     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2252   }
2253 }
2254 }
2255 }
2256
2257 #undef FLD
2258 }
2259   NEXT (vpc);
2260
2261   CASE (sem, INSN_CMPSCWR) : /* [${Rs}${inc}],$Rd */
2262 {
2263   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2264   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2265 #define FLD(f) abuf->fields.sfmt_bound_cw.f
2266   int UNUSED written = 0;
2267   IADDR UNUSED pc = abuf->addr;
2268   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2269
2270 {
2271   SI tmp_tmpopd;
2272   SI tmp_tmpops;
2273   BI tmp_carry;
2274   SI tmp_newval;
2275   tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
2276   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2277   tmp_carry = CPU (h_cbit);
2278   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2279 ((void) 0); /*nop*/
2280 {
2281   {
2282     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2283     CPU (h_cbit) = opval;
2284     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2285   }
2286   {
2287     BI opval = LTSI (tmp_newval, 0);
2288     CPU (h_nbit) = opval;
2289     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2290   }
2291   {
2292     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2293     CPU (h_zbit) = opval;
2294     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2295   }
2296   {
2297     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2298     CPU (h_vbit) = opval;
2299     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2300   }
2301 {
2302   {
2303     BI opval = 0;
2304     CPU (h_xbit) = opval;
2305     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2306   }
2307   {
2308     BI opval = 0;
2309     SET_H_INSN_PREFIXED_P (opval);
2310     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2311   }
2312 }
2313 }
2314 }
2315
2316 #undef FLD
2317 }
2318   NEXT (vpc);
2319
2320   CASE (sem, INSN_CMPU_M_B_M) : /* cmpu-m.b [${Rs}${inc}],$Rd */
2321 {
2322   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2323   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2324 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
2325   int UNUSED written = 0;
2326   IADDR UNUSED pc = abuf->addr;
2327   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2328
2329 {
2330   SI tmp_tmpopd;
2331   SI tmp_tmpops;
2332   BI tmp_carry;
2333   SI tmp_newval;
2334   tmp_tmpops = ZEXTQISI (({   SI tmp_addr;
2335   QI tmp_tmp_mem;
2336   BI tmp_postinc;
2337   tmp_postinc = FLD (f_memmode);
2338 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2339 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2340 ; if (NEBI (tmp_postinc, 0)) {
2341 {
2342 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2343   tmp_addr = ADDSI (tmp_addr, 1);
2344 }
2345   {
2346     SI opval = tmp_addr;
2347     SET_H_GR (FLD (f_operand1), opval);
2348     written |= (1 << 9);
2349     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2350   }
2351 }
2352 }
2353 ; tmp_tmp_mem; }));
2354   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2355   tmp_carry = CPU (h_cbit);
2356   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2357 ((void) 0); /*nop*/
2358 {
2359   {
2360     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2361     CPU (h_cbit) = opval;
2362     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2363   }
2364   {
2365     BI opval = LTSI (tmp_newval, 0);
2366     CPU (h_nbit) = opval;
2367     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2368   }
2369   {
2370     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2371     CPU (h_zbit) = opval;
2372     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2373   }
2374   {
2375     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2376     CPU (h_vbit) = opval;
2377     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2378   }
2379 {
2380   {
2381     BI opval = 0;
2382     CPU (h_xbit) = opval;
2383     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2384   }
2385   {
2386     BI opval = 0;
2387     SET_H_INSN_PREFIXED_P (opval);
2388     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2389   }
2390 }
2391 }
2392 }
2393
2394   abuf->written = written;
2395 #undef FLD
2396 }
2397   NEXT (vpc);
2398
2399   CASE (sem, INSN_CMPU_M_W_M) : /* cmpu-m.w [${Rs}${inc}],$Rd */
2400 {
2401   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2402   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2403 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
2404   int UNUSED written = 0;
2405   IADDR UNUSED pc = abuf->addr;
2406   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2407
2408 {
2409   SI tmp_tmpopd;
2410   SI tmp_tmpops;
2411   BI tmp_carry;
2412   SI tmp_newval;
2413   tmp_tmpops = ZEXTHISI (({   SI tmp_addr;
2414   HI tmp_tmp_mem;
2415   BI tmp_postinc;
2416   tmp_postinc = FLD (f_memmode);
2417 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2418 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2419 ; if (NEBI (tmp_postinc, 0)) {
2420 {
2421 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2422   tmp_addr = ADDSI (tmp_addr, 2);
2423 }
2424   {
2425     SI opval = tmp_addr;
2426     SET_H_GR (FLD (f_operand1), opval);
2427     written |= (1 << 9);
2428     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2429   }
2430 }
2431 }
2432 ; tmp_tmp_mem; }));
2433   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2434   tmp_carry = CPU (h_cbit);
2435   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2436 ((void) 0); /*nop*/
2437 {
2438   {
2439     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2440     CPU (h_cbit) = opval;
2441     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2442   }
2443   {
2444     BI opval = LTSI (tmp_newval, 0);
2445     CPU (h_nbit) = opval;
2446     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2447   }
2448   {
2449     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2450     CPU (h_zbit) = opval;
2451     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2452   }
2453   {
2454     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2455     CPU (h_vbit) = opval;
2456     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2457   }
2458 {
2459   {
2460     BI opval = 0;
2461     CPU (h_xbit) = opval;
2462     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2463   }
2464   {
2465     BI opval = 0;
2466     SET_H_INSN_PREFIXED_P (opval);
2467     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2468   }
2469 }
2470 }
2471 }
2472
2473   abuf->written = written;
2474 #undef FLD
2475 }
2476   NEXT (vpc);
2477
2478   CASE (sem, INSN_CMPUCBR) : /* [${Rs}${inc}],$Rd */
2479 {
2480   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2481   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2482 #define FLD(f) abuf->fields.sfmt_bound_cb.f
2483   int UNUSED written = 0;
2484   IADDR UNUSED pc = abuf->addr;
2485   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2486
2487 {
2488   SI tmp_tmpopd;
2489   SI tmp_tmpops;
2490   BI tmp_carry;
2491   SI tmp_newval;
2492   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
2493   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2494   tmp_carry = CPU (h_cbit);
2495   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2496 ((void) 0); /*nop*/
2497 {
2498   {
2499     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2500     CPU (h_cbit) = opval;
2501     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2502   }
2503   {
2504     BI opval = LTSI (tmp_newval, 0);
2505     CPU (h_nbit) = opval;
2506     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2507   }
2508   {
2509     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2510     CPU (h_zbit) = opval;
2511     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2512   }
2513   {
2514     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2515     CPU (h_vbit) = opval;
2516     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2517   }
2518 {
2519   {
2520     BI opval = 0;
2521     CPU (h_xbit) = opval;
2522     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2523   }
2524   {
2525     BI opval = 0;
2526     SET_H_INSN_PREFIXED_P (opval);
2527     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2528   }
2529 }
2530 }
2531 }
2532
2533 #undef FLD
2534 }
2535   NEXT (vpc);
2536
2537   CASE (sem, INSN_CMPUCWR) : /* [${Rs}${inc}],$Rd */
2538 {
2539   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2540   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2541 #define FLD(f) abuf->fields.sfmt_bound_cw.f
2542   int UNUSED written = 0;
2543   IADDR UNUSED pc = abuf->addr;
2544   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2545
2546 {
2547   SI tmp_tmpopd;
2548   SI tmp_tmpops;
2549   BI tmp_carry;
2550   SI tmp_newval;
2551   tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
2552   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2553   tmp_carry = CPU (h_cbit);
2554   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2555 ((void) 0); /*nop*/
2556 {
2557   {
2558     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2559     CPU (h_cbit) = opval;
2560     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2561   }
2562   {
2563     BI opval = LTSI (tmp_newval, 0);
2564     CPU (h_nbit) = opval;
2565     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2566   }
2567   {
2568     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2569     CPU (h_zbit) = opval;
2570     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2571   }
2572   {
2573     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2574     CPU (h_vbit) = opval;
2575     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2576   }
2577 {
2578   {
2579     BI opval = 0;
2580     CPU (h_xbit) = opval;
2581     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2582   }
2583   {
2584     BI opval = 0;
2585     SET_H_INSN_PREFIXED_P (opval);
2586     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2587   }
2588 }
2589 }
2590 }
2591
2592 #undef FLD
2593 }
2594   NEXT (vpc);
2595
2596   CASE (sem, INSN_MOVE_M_B_M) : /* move-m.b [${Rs}${inc}],${Rd} */
2597 {
2598   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2599   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2600 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
2601   int UNUSED written = 0;
2602   IADDR UNUSED pc = abuf->addr;
2603   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2604
2605 {
2606   SI tmp_tmp;
2607   tmp_tmp = ({   SI tmp_addr;
2608   QI tmp_tmp_mem;
2609   BI tmp_postinc;
2610   tmp_postinc = FLD (f_memmode);
2611 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2612 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2613 ; if (NEBI (tmp_postinc, 0)) {
2614 {
2615 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2616   tmp_addr = ADDSI (tmp_addr, 1);
2617 }
2618   {
2619     SI opval = tmp_addr;
2620     SET_H_GR (FLD (f_operand1), opval);
2621     written |= (1 << 10);
2622     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2623   }
2624 }
2625 }
2626 ; tmp_tmp_mem; });
2627 {
2628   SI tmp_oldregval;
2629   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
2630   {
2631     SI opval = ORSI (ANDSI (tmp_tmp, 255), ANDSI (tmp_oldregval, 0xffffff00));
2632     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
2633     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2634   }
2635 }
2636 {
2637   {
2638     BI opval = LTQI (tmp_tmp, 0);
2639     CPU (h_nbit) = opval;
2640     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2641   }
2642   {
2643     BI opval = ANDIF (EQQI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2644     CPU (h_zbit) = opval;
2645     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2646   }
2647 SET_H_CBIT_MOVE (0);
2648 SET_H_VBIT_MOVE (0);
2649 {
2650   {
2651     BI opval = 0;
2652     CPU (h_xbit) = opval;
2653     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2654   }
2655   {
2656     BI opval = 0;
2657     SET_H_INSN_PREFIXED_P (opval);
2658     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2659   }
2660 }
2661 }
2662 }
2663
2664   abuf->written = written;
2665 #undef FLD
2666 }
2667   NEXT (vpc);
2668
2669   CASE (sem, INSN_MOVE_M_W_M) : /* move-m.w [${Rs}${inc}],${Rd} */
2670 {
2671   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2672   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2673 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
2674   int UNUSED written = 0;
2675   IADDR UNUSED pc = abuf->addr;
2676   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2677
2678 {
2679   SI tmp_tmp;
2680   tmp_tmp = ({   SI tmp_addr;
2681   HI tmp_tmp_mem;
2682   BI tmp_postinc;
2683   tmp_postinc = FLD (f_memmode);
2684 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2685 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2686 ; if (NEBI (tmp_postinc, 0)) {
2687 {
2688 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2689   tmp_addr = ADDSI (tmp_addr, 2);
2690 }
2691   {
2692     SI opval = tmp_addr;
2693     SET_H_GR (FLD (f_operand1), opval);
2694     written |= (1 << 10);
2695     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2696   }
2697 }
2698 }
2699 ; tmp_tmp_mem; });
2700 {
2701   SI tmp_oldregval;
2702   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
2703   {
2704     SI opval = ORSI (ANDSI (tmp_tmp, 65535), ANDSI (tmp_oldregval, 0xffff0000));
2705     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
2706     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2707   }
2708 }
2709 {
2710   {
2711     BI opval = LTHI (tmp_tmp, 0);
2712     CPU (h_nbit) = opval;
2713     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2714   }
2715   {
2716     BI opval = ANDIF (EQHI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2717     CPU (h_zbit) = opval;
2718     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2719   }
2720 SET_H_CBIT_MOVE (0);
2721 SET_H_VBIT_MOVE (0);
2722 {
2723   {
2724     BI opval = 0;
2725     CPU (h_xbit) = opval;
2726     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2727   }
2728   {
2729     BI opval = 0;
2730     SET_H_INSN_PREFIXED_P (opval);
2731     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2732   }
2733 }
2734 }
2735 }
2736
2737   abuf->written = written;
2738 #undef FLD
2739 }
2740   NEXT (vpc);
2741
2742   CASE (sem, INSN_MOVE_M_D_M) : /* move-m.d [${Rs}${inc}],${Rd} */
2743 {
2744   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2745   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2746 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
2747   int UNUSED written = 0;
2748   IADDR UNUSED pc = abuf->addr;
2749   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2750
2751 {
2752   SI tmp_tmp;
2753   tmp_tmp = ({   SI tmp_addr;
2754   SI tmp_tmp_mem;
2755   BI tmp_postinc;
2756   tmp_postinc = FLD (f_memmode);
2757 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2758 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
2759 ; if (NEBI (tmp_postinc, 0)) {
2760 {
2761 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2762   tmp_addr = ADDSI (tmp_addr, 4);
2763 }
2764   {
2765     SI opval = tmp_addr;
2766     SET_H_GR (FLD (f_operand1), opval);
2767     written |= (1 << 9);
2768     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2769   }
2770 }
2771 }
2772 ; tmp_tmp_mem; });
2773   {
2774     SI opval = tmp_tmp;
2775     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
2776     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2777   }
2778 {
2779   {
2780     BI opval = LTSI (tmp_tmp, 0);
2781     CPU (h_nbit) = opval;
2782     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2783   }
2784   {
2785     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2786     CPU (h_zbit) = opval;
2787     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2788   }
2789 SET_H_CBIT_MOVE (0);
2790 SET_H_VBIT_MOVE (0);
2791 {
2792   {
2793     BI opval = 0;
2794     CPU (h_xbit) = opval;
2795     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2796   }
2797   {
2798     BI opval = 0;
2799     SET_H_INSN_PREFIXED_P (opval);
2800     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2801   }
2802 }
2803 }
2804 }
2805
2806   abuf->written = written;
2807 #undef FLD
2808 }
2809   NEXT (vpc);
2810
2811   CASE (sem, INSN_MOVS_M_B_M) : /* movs-m.b [${Rs}${inc}],${Rd} */
2812 {
2813   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2814   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2815 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
2816   int UNUSED written = 0;
2817   IADDR UNUSED pc = abuf->addr;
2818   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2819
2820 {
2821   SI tmp_tmp;
2822   tmp_tmp = EXTQISI (({   SI tmp_addr;
2823   QI tmp_tmp_mem;
2824   BI tmp_postinc;
2825   tmp_postinc = FLD (f_memmode);
2826 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2827 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2828 ; if (NEBI (tmp_postinc, 0)) {
2829 {
2830 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2831   tmp_addr = ADDSI (tmp_addr, 1);
2832 }
2833   {
2834     SI opval = tmp_addr;
2835     SET_H_GR (FLD (f_operand1), opval);
2836     written |= (1 << 8);
2837     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2838   }
2839 }
2840 }
2841 ; tmp_tmp_mem; }));
2842 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
2843   {
2844     SI opval = tmp_tmp;
2845     SET_H_GR (FLD (f_operand1), opval);
2846     written |= (1 << 8);
2847     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2848   }
2849 } else {
2850   {
2851     SI opval = tmp_tmp;
2852     SET_H_GR (FLD (f_operand2), opval);
2853     written |= (1 << 7);
2854     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2855   }
2856 }
2857 {
2858   {
2859     BI opval = LTSI (tmp_tmp, 0);
2860     CPU (h_nbit) = opval;
2861     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2862   }
2863   {
2864     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2865     CPU (h_zbit) = opval;
2866     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2867   }
2868 SET_H_CBIT_MOVE (0);
2869 SET_H_VBIT_MOVE (0);
2870 {
2871   {
2872     BI opval = 0;
2873     CPU (h_xbit) = opval;
2874     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2875   }
2876   {
2877     BI opval = 0;
2878     SET_H_INSN_PREFIXED_P (opval);
2879     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2880   }
2881 }
2882 }
2883 }
2884
2885   abuf->written = written;
2886 #undef FLD
2887 }
2888   NEXT (vpc);
2889
2890   CASE (sem, INSN_MOVS_M_W_M) : /* movs-m.w [${Rs}${inc}],${Rd} */
2891 {
2892   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2893   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2894 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
2895   int UNUSED written = 0;
2896   IADDR UNUSED pc = abuf->addr;
2897   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2898
2899 {
2900   SI tmp_tmp;
2901   tmp_tmp = EXTHISI (({   SI tmp_addr;
2902   HI tmp_tmp_mem;
2903   BI tmp_postinc;
2904   tmp_postinc = FLD (f_memmode);
2905 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2906 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2907 ; if (NEBI (tmp_postinc, 0)) {
2908 {
2909 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2910   tmp_addr = ADDSI (tmp_addr, 2);
2911 }
2912   {
2913     SI opval = tmp_addr;
2914     SET_H_GR (FLD (f_operand1), opval);
2915     written |= (1 << 8);
2916     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2917   }
2918 }
2919 }
2920 ; tmp_tmp_mem; }));
2921 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
2922   {
2923     SI opval = tmp_tmp;
2924     SET_H_GR (FLD (f_operand1), opval);
2925     written |= (1 << 8);
2926     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2927   }
2928 } else {
2929   {
2930     SI opval = tmp_tmp;
2931     SET_H_GR (FLD (f_operand2), opval);
2932     written |= (1 << 7);
2933     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2934   }
2935 }
2936 {
2937   {
2938     BI opval = LTSI (tmp_tmp, 0);
2939     CPU (h_nbit) = opval;
2940     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2941   }
2942   {
2943     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2944     CPU (h_zbit) = opval;
2945     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2946   }
2947 SET_H_CBIT_MOVE (0);
2948 SET_H_VBIT_MOVE (0);
2949 {
2950   {
2951     BI opval = 0;
2952     CPU (h_xbit) = opval;
2953     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2954   }
2955   {
2956     BI opval = 0;
2957     SET_H_INSN_PREFIXED_P (opval);
2958     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2959   }
2960 }
2961 }
2962 }
2963
2964   abuf->written = written;
2965 #undef FLD
2966 }
2967   NEXT (vpc);
2968
2969   CASE (sem, INSN_MOVU_M_B_M) : /* movu-m.b [${Rs}${inc}],${Rd} */
2970 {
2971   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2972   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2973 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
2974   int UNUSED written = 0;
2975   IADDR UNUSED pc = abuf->addr;
2976   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2977
2978 {
2979   SI tmp_tmp;
2980   tmp_tmp = ZEXTQISI (({   SI tmp_addr;
2981   QI tmp_tmp_mem;
2982   BI tmp_postinc;
2983   tmp_postinc = FLD (f_memmode);
2984 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2985 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2986 ; if (NEBI (tmp_postinc, 0)) {
2987 {
2988 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2989   tmp_addr = ADDSI (tmp_addr, 1);
2990 }
2991   {
2992     SI opval = tmp_addr;
2993     SET_H_GR (FLD (f_operand1), opval);
2994     written |= (1 << 8);
2995     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2996   }
2997 }
2998 }
2999 ; tmp_tmp_mem; }));
3000 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
3001   {
3002     SI opval = tmp_tmp;
3003     SET_H_GR (FLD (f_operand1), opval);
3004     written |= (1 << 8);
3005     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3006   }
3007 } else {
3008   {
3009     SI opval = tmp_tmp;
3010     SET_H_GR (FLD (f_operand2), opval);
3011     written |= (1 << 7);
3012     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3013   }
3014 }
3015 {
3016   {
3017     BI opval = LTSI (tmp_tmp, 0);
3018     CPU (h_nbit) = opval;
3019     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
3020   }
3021   {
3022     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
3023     CPU (h_zbit) = opval;
3024     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
3025   }
3026 SET_H_CBIT_MOVE (0);
3027 SET_H_VBIT_MOVE (0);
3028 {
3029   {
3030     BI opval = 0;
3031     CPU (h_xbit) = opval;
3032     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3033   }
3034   {
3035     BI opval = 0;
3036     SET_H_INSN_PREFIXED_P (opval);
3037     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3038   }
3039 }
3040 }
3041 }
3042
3043   abuf->written = written;
3044 #undef FLD
3045 }
3046   NEXT (vpc);
3047
3048   CASE (sem, INSN_MOVU_M_W_M) : /* movu-m.w [${Rs}${inc}],${Rd} */
3049 {
3050   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3051   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3052 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
3053   int UNUSED written = 0;
3054   IADDR UNUSED pc = abuf->addr;
3055   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3056
3057 {
3058   SI tmp_tmp;
3059   tmp_tmp = ZEXTHISI (({   SI tmp_addr;
3060   HI tmp_tmp_mem;
3061   BI tmp_postinc;
3062   tmp_postinc = FLD (f_memmode);
3063 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3064 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
3065 ; if (NEBI (tmp_postinc, 0)) {
3066 {
3067 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3068   tmp_addr = ADDSI (tmp_addr, 2);
3069 }
3070   {
3071     SI opval = tmp_addr;
3072     SET_H_GR (FLD (f_operand1), opval);
3073     written |= (1 << 8);
3074     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3075   }
3076 }
3077 }
3078 ; tmp_tmp_mem; }));
3079 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
3080   {
3081     SI opval = tmp_tmp;
3082     SET_H_GR (FLD (f_operand1), opval);
3083     written |= (1 << 8);
3084     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3085   }
3086 } else {
3087   {
3088     SI opval = tmp_tmp;
3089     SET_H_GR (FLD (f_operand2), opval);
3090     written |= (1 << 7);
3091     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3092   }
3093 }
3094 {
3095   {
3096     BI opval = LTSI (tmp_tmp, 0);
3097     CPU (h_nbit) = opval;
3098     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
3099   }
3100   {
3101     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
3102     CPU (h_zbit) = opval;
3103     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
3104   }
3105 SET_H_CBIT_MOVE (0);
3106 SET_H_VBIT_MOVE (0);
3107 {
3108   {
3109     BI opval = 0;
3110     CPU (h_xbit) = opval;
3111     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3112   }
3113   {
3114     BI opval = 0;
3115     SET_H_INSN_PREFIXED_P (opval);
3116     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3117   }
3118 }
3119 }
3120 }
3121
3122   abuf->written = written;
3123 #undef FLD
3124 }
3125   NEXT (vpc);
3126
3127   CASE (sem, INSN_MOVE_R_SPRV10) : /* move ${Rs},${Pd} */
3128 {
3129   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3130   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3131 #define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
3132   int UNUSED written = 0;
3133   IADDR UNUSED pc = abuf->addr;
3134   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3135
3136 {
3137   SI tmp_tmp;
3138   SI tmp_rno;
3139   tmp_tmp = GET_H_GR (FLD (f_operand1));
3140   tmp_rno = FLD (f_operand2);
3141 if (ORIF (ORIF (EQSI (tmp_rno, 0), EQSI (tmp_rno, 1)), ORIF (EQSI (tmp_rno, 4), EQSI (tmp_rno, 8)))) {
3142 cgen_rtx_error (current_cpu, "move-r-spr: trying to set a read-only special register");
3143 }
3144  else {
3145   {
3146     SI opval = tmp_tmp;
3147     SET_H_SR (FLD (f_operand2), opval);
3148     written |= (1 << 2);
3149     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3150   }
3151 }
3152 {
3153   {
3154     BI opval = 0;
3155     CPU (h_xbit) = opval;
3156     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3157   }
3158   {
3159     BI opval = 0;
3160     SET_H_INSN_PREFIXED_P (opval);
3161     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3162   }
3163 }
3164 }
3165
3166   abuf->written = written;
3167 #undef FLD
3168 }
3169   NEXT (vpc);
3170
3171   CASE (sem, INSN_MOVE_SPR_RV10) : /* move ${Ps},${Rd-sfield} */
3172 {
3173   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3174   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3175 #define FLD(f) abuf->fields.sfmt_move_spr_rv10.f
3176   int UNUSED written = 0;
3177   IADDR UNUSED pc = abuf->addr;
3178   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3179
3180 {
3181   SI tmp_grno;
3182   SI tmp_prno;
3183   SI tmp_newval;
3184   tmp_prno = FLD (f_operand2);
3185   tmp_newval = GET_H_SR (FLD (f_operand2));
3186 if (EQSI (tmp_prno, 0)) {
3187 {
3188   SI tmp_oldregval;
3189   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1));
3190   {
3191     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
3192     SET_H_GR (FLD (f_operand1), opval);
3193     written |= (1 << 4);
3194     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3195   }
3196 }
3197 }
3198  else if (EQSI (tmp_prno, 1)) {
3199 {
3200   SI tmp_oldregval;
3201   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1));
3202   {
3203     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
3204     SET_H_GR (FLD (f_operand1), opval);
3205     written |= (1 << 4);
3206     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3207   }
3208 }
3209 }
3210  else if (EQSI (tmp_prno, 4)) {
3211 {
3212   SI tmp_oldregval;
3213   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1));
3214   {
3215     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
3216     SET_H_GR (FLD (f_operand1), opval);
3217     written |= (1 << 4);
3218     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3219   }
3220 }
3221 }
3222  else if (EQSI (tmp_prno, 5)) {
3223 {
3224   SI tmp_oldregval;
3225   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1));
3226   {
3227     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
3228     SET_H_GR (FLD (f_operand1), opval);
3229     written |= (1 << 4);
3230     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3231   }
3232 }
3233 }
3234  else if (EQSI (tmp_prno, 8)) {
3235   {
3236     SI opval = tmp_newval;
3237     SET_H_GR (FLD (f_operand1), opval);
3238     written |= (1 << 4);
3239     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3240   }
3241 }
3242  else if (EQSI (tmp_prno, 9)) {
3243   {
3244     SI opval = tmp_newval;
3245     SET_H_GR (FLD (f_operand1), opval);
3246     written |= (1 << 4);
3247     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3248   }
3249 }
3250  else if (EQSI (tmp_prno, 10)) {
3251   {
3252     SI opval = tmp_newval;
3253     SET_H_GR (FLD (f_operand1), opval);
3254     written |= (1 << 4);
3255     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3256   }
3257 }
3258  else if (EQSI (tmp_prno, 11)) {
3259   {
3260     SI opval = tmp_newval;
3261     SET_H_GR (FLD (f_operand1), opval);
3262     written |= (1 << 4);
3263     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3264   }
3265 }
3266  else if (EQSI (tmp_prno, 12)) {
3267   {
3268     SI opval = tmp_newval;
3269     SET_H_GR (FLD (f_operand1), opval);
3270     written |= (1 << 4);
3271     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3272   }
3273 }
3274  else if (EQSI (tmp_prno, 13)) {
3275   {
3276     SI opval = tmp_newval;
3277     SET_H_GR (FLD (f_operand1), opval);
3278     written |= (1 << 4);
3279     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3280   }
3281 }
3282  else if (EQSI (tmp_prno, 7)) {
3283   {
3284     SI opval = tmp_newval;
3285     SET_H_GR (FLD (f_operand1), opval);
3286     written |= (1 << 4);
3287     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3288   }
3289 }
3290  else if (EQSI (tmp_prno, 14)) {
3291   {
3292     SI opval = tmp_newval;
3293     SET_H_GR (FLD (f_operand1), opval);
3294     written |= (1 << 4);
3295     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3296   }
3297 }
3298  else if (EQSI (tmp_prno, 15)) {
3299   {
3300     SI opval = tmp_newval;
3301     SET_H_GR (FLD (f_operand1), opval);
3302     written |= (1 << 4);
3303     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3304   }
3305 }
3306  else {
3307 cgen_rtx_error (current_cpu, "move-spr-r from unimplemented register");
3308 }
3309 {
3310   {
3311     BI opval = 0;
3312     CPU (h_xbit) = opval;
3313     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3314   }
3315   {
3316     BI opval = 0;
3317     SET_H_INSN_PREFIXED_P (opval);
3318     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3319   }
3320 }
3321 }
3322
3323   abuf->written = written;
3324 #undef FLD
3325 }
3326   NEXT (vpc);
3327
3328   CASE (sem, INSN_RET_TYPE) : /* ret/reti/retb */
3329 {
3330   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3331   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3332 #define FLD(f) abuf->fields.sfmt_move_spr_rv10.f
3333   int UNUSED written = 0;
3334   IADDR UNUSED pc = abuf->addr;
3335   SEM_BRANCH_INIT
3336   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3337
3338 {
3339   SI tmp_retaddr;
3340   tmp_retaddr = GET_H_SR (FLD (f_operand2));
3341 {
3342   {
3343     BI opval = 0;
3344     CPU (h_xbit) = opval;
3345     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3346   }
3347   {
3348     BI opval = 0;
3349     SET_H_INSN_PREFIXED_P (opval);
3350     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3351   }
3352 }
3353 {
3354   {
3355     USI opval = tmp_retaddr;
3356     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
3357     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3358   }
3359 }
3360 }
3361
3362   SEM_BRANCH_FINI (vpc);
3363 #undef FLD
3364 }
3365   NEXT (vpc);
3366
3367   CASE (sem, INSN_MOVE_M_SPRV10) : /* move [${Rs}${inc}],${Pd} */
3368 {
3369   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3370   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3371 #define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
3372   int UNUSED written = 0;
3373   IADDR UNUSED pc = abuf->addr;
3374   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3375
3376 {
3377   SI tmp_rno;
3378   SI tmp_newval;
3379   tmp_rno = FLD (f_operand2);
3380 if (EQSI (tmp_rno, 0)) {
3381   tmp_newval = EXTQISI (({   SI tmp_addr;
3382   QI tmp_tmp_mem;
3383   BI tmp_postinc;
3384   tmp_postinc = FLD (f_memmode);
3385 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3386 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
3387 ; if (NEBI (tmp_postinc, 0)) {
3388 {
3389 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3390   tmp_addr = ADDSI (tmp_addr, 1);
3391 }
3392   {
3393     SI opval = tmp_addr;
3394     SET_H_GR (FLD (f_operand1), opval);
3395     written |= (1 << 9);
3396     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3397   }
3398 }
3399 }
3400 ; tmp_tmp_mem; }));
3401 }
3402  else if (EQSI (tmp_rno, 1)) {
3403   tmp_newval = EXTQISI (({   SI tmp_addr;
3404   QI tmp_tmp_mem;
3405   BI tmp_postinc;
3406   tmp_postinc = FLD (f_memmode);
3407 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3408 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
3409 ; if (NEBI (tmp_postinc, 0)) {
3410 {
3411 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3412   tmp_addr = ADDSI (tmp_addr, 1);
3413 }
3414   {
3415     SI opval = tmp_addr;
3416     SET_H_GR (FLD (f_operand1), opval);
3417     written |= (1 << 9);
3418     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3419   }
3420 }
3421 }
3422 ; tmp_tmp_mem; }));
3423 }
3424  else if (EQSI (tmp_rno, 4)) {
3425   tmp_newval = EXTHISI (({   SI tmp_addr;
3426   HI tmp_tmp_mem;
3427   BI tmp_postinc;
3428   tmp_postinc = FLD (f_memmode);
3429 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3430 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
3431 ; if (NEBI (tmp_postinc, 0)) {
3432 {
3433 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3434   tmp_addr = ADDSI (tmp_addr, 2);
3435 }
3436   {
3437     SI opval = tmp_addr;
3438     SET_H_GR (FLD (f_operand1), opval);
3439     written |= (1 << 9);
3440     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3441   }
3442 }
3443 }
3444 ; tmp_tmp_mem; }));
3445 }
3446  else if (EQSI (tmp_rno, 5)) {
3447   tmp_newval = EXTHISI (({   SI tmp_addr;
3448   HI tmp_tmp_mem;
3449   BI tmp_postinc;
3450   tmp_postinc = FLD (f_memmode);
3451 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3452 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
3453 ; if (NEBI (tmp_postinc, 0)) {
3454 {
3455 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3456   tmp_addr = ADDSI (tmp_addr, 2);
3457 }
3458   {
3459     SI opval = tmp_addr;
3460     SET_H_GR (FLD (f_operand1), opval);
3461     written |= (1 << 9);
3462     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3463   }
3464 }
3465 }
3466 ; tmp_tmp_mem; }));
3467 }
3468  else if (EQSI (tmp_rno, 8)) {
3469   tmp_newval = ({   SI tmp_addr;
3470   SI tmp_tmp_mem;
3471   BI tmp_postinc;
3472   tmp_postinc = FLD (f_memmode);
3473 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3474 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3475 ; if (NEBI (tmp_postinc, 0)) {
3476 {
3477 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3478   tmp_addr = ADDSI (tmp_addr, 4);
3479 }
3480   {
3481     SI opval = tmp_addr;
3482     SET_H_GR (FLD (f_operand1), opval);
3483     written |= (1 << 9);
3484     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3485   }
3486 }
3487 }
3488 ; tmp_tmp_mem; });
3489 }
3490  else if (EQSI (tmp_rno, 9)) {
3491   tmp_newval = ({   SI tmp_addr;
3492   SI tmp_tmp_mem;
3493   BI tmp_postinc;
3494   tmp_postinc = FLD (f_memmode);
3495 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3496 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3497 ; if (NEBI (tmp_postinc, 0)) {
3498 {
3499 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3500   tmp_addr = ADDSI (tmp_addr, 4);
3501 }
3502   {
3503     SI opval = tmp_addr;
3504     SET_H_GR (FLD (f_operand1), opval);
3505     written |= (1 << 9);
3506     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3507   }
3508 }
3509 }
3510 ; tmp_tmp_mem; });
3511 }
3512  else if (EQSI (tmp_rno, 10)) {
3513   tmp_newval = ({   SI tmp_addr;
3514   SI tmp_tmp_mem;
3515   BI tmp_postinc;
3516   tmp_postinc = FLD (f_memmode);
3517 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3518 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3519 ; if (NEBI (tmp_postinc, 0)) {
3520 {
3521 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3522   tmp_addr = ADDSI (tmp_addr, 4);
3523 }
3524   {
3525     SI opval = tmp_addr;
3526     SET_H_GR (FLD (f_operand1), opval);
3527     written |= (1 << 9);
3528     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3529   }
3530 }
3531 }
3532 ; tmp_tmp_mem; });
3533 }
3534  else if (EQSI (tmp_rno, 11)) {
3535   tmp_newval = ({   SI tmp_addr;
3536   SI tmp_tmp_mem;
3537   BI tmp_postinc;
3538   tmp_postinc = FLD (f_memmode);
3539 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3540 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3541 ; if (NEBI (tmp_postinc, 0)) {
3542 {
3543 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3544   tmp_addr = ADDSI (tmp_addr, 4);
3545 }
3546   {
3547     SI opval = tmp_addr;
3548     SET_H_GR (FLD (f_operand1), opval);
3549     written |= (1 << 9);
3550     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3551   }
3552 }
3553 }
3554 ; tmp_tmp_mem; });
3555 }
3556  else if (EQSI (tmp_rno, 12)) {
3557   tmp_newval = ({   SI tmp_addr;
3558   SI tmp_tmp_mem;
3559   BI tmp_postinc;
3560   tmp_postinc = FLD (f_memmode);
3561 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3562 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3563 ; if (NEBI (tmp_postinc, 0)) {
3564 {
3565 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3566   tmp_addr = ADDSI (tmp_addr, 4);
3567 }
3568   {
3569     SI opval = tmp_addr;
3570     SET_H_GR (FLD (f_operand1), opval);
3571     written |= (1 << 9);
3572     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3573   }
3574 }
3575 }
3576 ; tmp_tmp_mem; });
3577 }
3578  else if (EQSI (tmp_rno, 13)) {
3579   tmp_newval = ({   SI tmp_addr;
3580   SI tmp_tmp_mem;
3581   BI tmp_postinc;
3582   tmp_postinc = FLD (f_memmode);
3583 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3584 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3585 ; if (NEBI (tmp_postinc, 0)) {
3586 {
3587 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3588   tmp_addr = ADDSI (tmp_addr, 4);
3589 }
3590   {
3591     SI opval = tmp_addr;
3592     SET_H_GR (FLD (f_operand1), opval);
3593     written |= (1 << 9);
3594     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3595   }
3596 }
3597 }
3598 ; tmp_tmp_mem; });
3599 }
3600  else if (EQSI (tmp_rno, 7)) {
3601   tmp_newval = ({   SI tmp_addr;
3602   SI tmp_tmp_mem;
3603   BI tmp_postinc;
3604   tmp_postinc = FLD (f_memmode);
3605 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3606 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3607 ; if (NEBI (tmp_postinc, 0)) {
3608 {
3609 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3610   tmp_addr = ADDSI (tmp_addr, 4);
3611 }
3612   {
3613     SI opval = tmp_addr;
3614     SET_H_GR (FLD (f_operand1), opval);
3615     written |= (1 << 9);
3616     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3617   }
3618 }
3619 }
3620 ; tmp_tmp_mem; });
3621 }
3622  else if (EQSI (tmp_rno, 14)) {
3623   tmp_newval = ({   SI tmp_addr;
3624   SI tmp_tmp_mem;
3625   BI tmp_postinc;
3626   tmp_postinc = FLD (f_memmode);
3627 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3628 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3629 ; if (NEBI (tmp_postinc, 0)) {
3630 {
3631 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3632   tmp_addr = ADDSI (tmp_addr, 4);
3633 }
3634   {
3635     SI opval = tmp_addr;
3636     SET_H_GR (FLD (f_operand1), opval);
3637     written |= (1 << 9);
3638     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3639   }
3640 }
3641 }
3642 ; tmp_tmp_mem; });
3643 }
3644  else if (EQSI (tmp_rno, 15)) {
3645   tmp_newval = ({   SI tmp_addr;
3646   SI tmp_tmp_mem;
3647   BI tmp_postinc;
3648   tmp_postinc = FLD (f_memmode);
3649 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3650 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3651 ; if (NEBI (tmp_postinc, 0)) {
3652 {
3653 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3654   tmp_addr = ADDSI (tmp_addr, 4);
3655 }
3656   {
3657     SI opval = tmp_addr;
3658     SET_H_GR (FLD (f_operand1), opval);
3659     written |= (1 << 9);
3660     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3661   }
3662 }
3663 }
3664 ; tmp_tmp_mem; });
3665 }
3666  else {
3667 cgen_rtx_error (current_cpu, "Trying to set unimplemented special register");
3668 }
3669   {
3670     SI opval = tmp_newval;
3671     SET_H_SR (FLD (f_operand2), opval);
3672     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3673   }
3674 {
3675   {
3676     BI opval = 0;
3677     CPU (h_xbit) = opval;
3678     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3679   }
3680   {
3681     BI opval = 0;
3682     SET_H_INSN_PREFIXED_P (opval);
3683     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3684   }
3685 }
3686 }
3687
3688   abuf->written = written;
3689 #undef FLD
3690 }
3691   NEXT (vpc);
3692
3693   CASE (sem, INSN_MOVE_C_SPRV10_P0) : /* move ${sconst8},${Pd} */
3694 {
3695   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3696   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3697 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p0.f
3698   int UNUSED written = 0;
3699   IADDR UNUSED pc = abuf->addr;
3700   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3701
3702 {
3703   {
3704     SI opval = FLD (f_indir_pc__byte);
3705     SET_H_SR (FLD (f_operand2), opval);
3706     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3707   }
3708 {
3709   {
3710     BI opval = 0;
3711     CPU (h_xbit) = opval;
3712     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3713   }
3714   {
3715     BI opval = 0;
3716     SET_H_INSN_PREFIXED_P (opval);
3717     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3718   }
3719 }
3720 }
3721
3722 #undef FLD
3723 }
3724   NEXT (vpc);
3725
3726   CASE (sem, INSN_MOVE_C_SPRV10_P1) : /* move ${sconst8},${Pd} */
3727 {
3728   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3729   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3730 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p0.f
3731   int UNUSED written = 0;
3732   IADDR UNUSED pc = abuf->addr;
3733   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3734
3735 {
3736   {
3737     SI opval = FLD (f_indir_pc__byte);
3738     SET_H_SR (FLD (f_operand2), opval);
3739     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3740   }
3741 {
3742   {
3743     BI opval = 0;
3744     CPU (h_xbit) = opval;
3745     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3746   }
3747   {
3748     BI opval = 0;
3749     SET_H_INSN_PREFIXED_P (opval);
3750     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3751   }
3752 }
3753 }
3754
3755 #undef FLD
3756 }
3757   NEXT (vpc);
3758
3759   CASE (sem, INSN_MOVE_C_SPRV10_P4) : /* move ${sconst16},${Pd} */
3760 {
3761   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3762   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3763 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p4.f
3764   int UNUSED written = 0;
3765   IADDR UNUSED pc = abuf->addr;
3766   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3767
3768 {
3769   {
3770     SI opval = FLD (f_indir_pc__word);
3771     SET_H_SR (FLD (f_operand2), opval);
3772     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3773   }
3774 {
3775   {
3776     BI opval = 0;
3777     CPU (h_xbit) = opval;
3778     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3779   }
3780   {
3781     BI opval = 0;
3782     SET_H_INSN_PREFIXED_P (opval);
3783     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3784   }
3785 }
3786 }
3787
3788 #undef FLD
3789 }
3790   NEXT (vpc);
3791
3792   CASE (sem, INSN_MOVE_C_SPRV10_P5) : /* move ${sconst16},${Pd} */
3793 {
3794   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3795   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3796 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p4.f
3797   int UNUSED written = 0;
3798   IADDR UNUSED pc = abuf->addr;
3799   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3800
3801 {
3802   {
3803     SI opval = FLD (f_indir_pc__word);
3804     SET_H_SR (FLD (f_operand2), opval);
3805     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3806   }
3807 {
3808   {
3809     BI opval = 0;
3810     CPU (h_xbit) = opval;
3811     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3812   }
3813   {
3814     BI opval = 0;
3815     SET_H_INSN_PREFIXED_P (opval);
3816     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3817   }
3818 }
3819 }
3820
3821 #undef FLD
3822 }
3823   NEXT (vpc);
3824
3825   CASE (sem, INSN_MOVE_C_SPRV10_P8) : /* move ${const32},${Pd} */
3826 {
3827   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3828   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3829 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
3830   int UNUSED written = 0;
3831   IADDR UNUSED pc = abuf->addr;
3832   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3833
3834 {
3835   {
3836     SI opval = FLD (f_indir_pc__dword);
3837     SET_H_SR (FLD (f_operand2), opval);
3838     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3839   }
3840 {
3841   {
3842     BI opval = 0;
3843     CPU (h_xbit) = opval;
3844     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3845   }
3846   {
3847     BI opval = 0;
3848     SET_H_INSN_PREFIXED_P (opval);
3849     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3850   }
3851 }
3852 }
3853
3854 #undef FLD
3855 }
3856   NEXT (vpc);
3857
3858   CASE (sem, INSN_MOVE_C_SPRV10_P9) : /* move ${const32},${Pd} */
3859 {
3860   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3861   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3862 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
3863   int UNUSED written = 0;
3864   IADDR UNUSED pc = abuf->addr;
3865   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3866
3867 {
3868   {
3869     SI opval = FLD (f_indir_pc__dword);
3870     SET_H_SR (FLD (f_operand2), opval);
3871     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3872   }
3873 {
3874   {
3875     BI opval = 0;
3876     CPU (h_xbit) = opval;
3877     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3878   }
3879   {
3880     BI opval = 0;
3881     SET_H_INSN_PREFIXED_P (opval);
3882     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3883   }
3884 }
3885 }
3886
3887 #undef FLD
3888 }
3889   NEXT (vpc);
3890
3891   CASE (sem, INSN_MOVE_C_SPRV10_P10) : /* move ${const32},${Pd} */
3892 {
3893   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3894   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3895 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
3896   int UNUSED written = 0;
3897   IADDR UNUSED pc = abuf->addr;
3898   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3899
3900 {
3901   {
3902     SI opval = FLD (f_indir_pc__dword);
3903     SET_H_SR (FLD (f_operand2), opval);
3904     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3905   }
3906 {
3907   {
3908     BI opval = 0;
3909     CPU (h_xbit) = opval;
3910     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3911   }
3912   {
3913     BI opval = 0;
3914     SET_H_INSN_PREFIXED_P (opval);
3915     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3916   }
3917 }
3918 }
3919
3920 #undef FLD
3921 }
3922   NEXT (vpc);
3923
3924   CASE (sem, INSN_MOVE_C_SPRV10_P11) : /* move ${const32},${Pd} */
3925 {
3926   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3927   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3928 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
3929   int UNUSED written = 0;
3930   IADDR UNUSED pc = abuf->addr;
3931   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3932
3933 {
3934   {
3935     SI opval = FLD (f_indir_pc__dword);
3936     SET_H_SR (FLD (f_operand2), opval);
3937     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3938   }
3939 {
3940   {
3941     BI opval = 0;
3942     CPU (h_xbit) = opval;
3943     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3944   }
3945   {
3946     BI opval = 0;
3947     SET_H_INSN_PREFIXED_P (opval);
3948     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3949   }
3950 }
3951 }
3952
3953 #undef FLD
3954 }
3955   NEXT (vpc);
3956
3957   CASE (sem, INSN_MOVE_C_SPRV10_P12) : /* move ${const32},${Pd} */
3958 {
3959   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3960   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3961 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
3962   int UNUSED written = 0;
3963   IADDR UNUSED pc = abuf->addr;
3964   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3965
3966 {
3967   {
3968     SI opval = FLD (f_indir_pc__dword);
3969     SET_H_SR (FLD (f_operand2), opval);
3970     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3971   }
3972 {
3973   {
3974     BI opval = 0;
3975     CPU (h_xbit) = opval;
3976     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3977   }
3978   {
3979     BI opval = 0;
3980     SET_H_INSN_PREFIXED_P (opval);
3981     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3982   }
3983 }
3984 }
3985
3986 #undef FLD
3987 }
3988   NEXT (vpc);
3989
3990   CASE (sem, INSN_MOVE_C_SPRV10_P13) : /* move ${const32},${Pd} */
3991 {
3992   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3993   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3994 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
3995   int UNUSED written = 0;
3996   IADDR UNUSED pc = abuf->addr;
3997   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3998
3999 {
4000   {
4001     SI opval = FLD (f_indir_pc__dword);
4002     SET_H_SR (FLD (f_operand2), opval);
4003     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
4004   }
4005 {
4006   {
4007     BI opval = 0;
4008     CPU (h_xbit) = opval;
4009     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
4010   }
4011   {
4012     BI opval = 0;
4013     SET_H_INSN_PREFIXED_P (opval);
4014     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
4015   }
4016 }
4017 }
4018
4019 #undef FLD
4020 }
4021   NEXT (vpc);
4022
4023   CASE (sem, INSN_MOVE_C_SPRV10_P7) : /* move ${const32},${Pd} */
4024 {
4025   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4026   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4027 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
4028   int UNUSED written = 0;
4029   IADDR UNUSED pc = abuf->addr;
4030   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
4031
4032 {
4033   {
4034     SI opval = FLD (f_indir_pc__dword);
4035     SET_H_SR (FLD (f_operand2), opval);
4036     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
4037   }
4038 {
4039   {
4040     BI opval = 0;
4041     CPU (h_xbit) = opval;
4042     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
4043   }
4044   {
4045     BI opval = 0;
4046     SET_H_INSN_PREFIXED_P (opval);
4047     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
4048   }
4049 }
4050 }
4051
4052 #undef FLD
4053 }
4054   NEXT (vpc);
4055
4056   CASE (sem, INSN_MOVE_C_SPRV10_P14) : /* move ${const32},${Pd} */
4057 {
4058   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4059   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4060 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
4061   int UNUSED written = 0;
4062   IADDR UNUSED pc = abuf->addr;
4063   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
4064
4065 {
4066   {
4067     SI opval = FLD (f_indir_pc__dword);
4068     SET_H_SR (FLD (f_operand2), opval);
4069     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
4070   }
4071 {
4072   {
4073     BI opval = 0;
4074     CPU (h_xbit) = opval;
4075     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
4076   }
4077   {
4078     BI opval = 0;
4079     SET_H_INSN_PREFIXED_P (opval);
4080     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
4081   }
4082 }
4083 }
4084
4085 #undef FLD
4086 }
4087   NEXT (vpc);
4088
4089   CASE (sem, INSN_MOVE_C_SPRV10_P15) : /* move ${const32},${Pd} */
4090 {
4091   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4092   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4093 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
4094   int UNUSED written = 0;
4095   IADDR UNUSED pc = abuf->addr;
4096   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
4097
4098 {
4099   {
4100     SI opval = FLD (f_indir_pc__dword);
4101     SET_H_SR (FLD (f_operand2), opval);
4102     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
4103   }
4104 {
4105   {
4106     BI opval = 0;
4107     CPU (h_xbit) = opval;
4108     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
4109   }
4110   {
4111     BI opval = 0;
4112     SET_H_INSN_PREFIXED_P (opval);
4113     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
4114   }
4115 }
4116 }
4117
4118 #undef FLD
4119 }
4120   NEXT (vpc);
4121
4122   CASE (sem, INSN_MOVE_SPR_MV10) : /* move ${Ps},[${Rd-sfield}${inc}] */
4123 {
4124   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4125   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4126 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
4127   int UNUSED written = 0;
4128   IADDR UNUSED pc = abuf->addr;
4129   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4130
4131 {
4132   SI tmp_rno;
4133   tmp_rno = FLD (f_operand2);
4134 if (EQSI (tmp_rno, 0)) {
4135 {
4136   SI tmp_addr;
4137   BI tmp_postinc;
4138   tmp_postinc = FLD (f_memmode);
4139   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4140 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4141 if (EQBI (CPU (h_pbit), 0)) {
4142 {
4143   {
4144     QI opval = GET_H_SR (FLD (f_operand2));
4145     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4146     written |= (1 << 12);
4147     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4148   }
4149   {
4150     BI opval = CPU (h_pbit);
4151     CPU (h_cbit) = opval;
4152     written |= (1 << 10);
4153     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4154   }
4155 }
4156 } else {
4157   {
4158     BI opval = 1;
4159     CPU (h_cbit) = opval;
4160     written |= (1 << 10);
4161     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4162   }
4163 }
4164 } else {
4165   {
4166     QI opval = GET_H_SR (FLD (f_operand2));
4167     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4168     written |= (1 << 12);
4169     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4170   }
4171 }
4172 if (NEBI (tmp_postinc, 0)) {
4173 {
4174 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4175   tmp_addr = ADDSI (tmp_addr, 1);
4176 }
4177   {
4178     SI opval = tmp_addr;
4179     SET_H_GR (FLD (f_operand1), opval);
4180     written |= (1 << 9);
4181     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4182   }
4183 }
4184 }
4185 }
4186 }
4187  else if (EQSI (tmp_rno, 1)) {
4188 {
4189   SI tmp_addr;
4190   BI tmp_postinc;
4191   tmp_postinc = FLD (f_memmode);
4192   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4193 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4194 if (EQBI (CPU (h_pbit), 0)) {
4195 {
4196   {
4197     QI opval = GET_H_SR (FLD (f_operand2));
4198     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4199     written |= (1 << 12);
4200     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4201   }
4202   {
4203     BI opval = CPU (h_pbit);
4204     CPU (h_cbit) = opval;
4205     written |= (1 << 10);
4206     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4207   }
4208 }
4209 } else {
4210   {
4211     BI opval = 1;
4212     CPU (h_cbit) = opval;
4213     written |= (1 << 10);
4214     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4215   }
4216 }
4217 } else {
4218   {
4219     QI opval = GET_H_SR (FLD (f_operand2));
4220     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4221     written |= (1 << 12);
4222     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4223   }
4224 }
4225 if (NEBI (tmp_postinc, 0)) {
4226 {
4227 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4228   tmp_addr = ADDSI (tmp_addr, 1);
4229 }
4230   {
4231     SI opval = tmp_addr;
4232     SET_H_GR (FLD (f_operand1), opval);
4233     written |= (1 << 9);
4234     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4235   }
4236 }
4237 }
4238 }
4239 }
4240  else if (EQSI (tmp_rno, 4)) {
4241 {
4242   SI tmp_addr;
4243   BI tmp_postinc;
4244   tmp_postinc = FLD (f_memmode);
4245   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4246 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4247 if (EQBI (CPU (h_pbit), 0)) {
4248 {
4249   {
4250     HI opval = GET_H_SR (FLD (f_operand2));
4251     SETMEMHI (current_cpu, pc, tmp_addr, opval);
4252     written |= (1 << 11);
4253     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4254   }
4255   {
4256     BI opval = CPU (h_pbit);
4257     CPU (h_cbit) = opval;
4258     written |= (1 << 10);
4259     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4260   }
4261 }
4262 } else {
4263   {
4264     BI opval = 1;
4265     CPU (h_cbit) = opval;
4266     written |= (1 << 10);
4267     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4268   }
4269 }
4270 } else {
4271   {
4272     HI opval = GET_H_SR (FLD (f_operand2));
4273     SETMEMHI (current_cpu, pc, tmp_addr, opval);
4274     written |= (1 << 11);
4275     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4276   }
4277 }
4278 if (NEBI (tmp_postinc, 0)) {
4279 {
4280 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4281   tmp_addr = ADDSI (tmp_addr, 2);
4282 }
4283   {
4284     SI opval = tmp_addr;
4285     SET_H_GR (FLD (f_operand1), opval);
4286     written |= (1 << 9);
4287     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4288   }
4289 }
4290 }
4291 }
4292 }
4293  else if (EQSI (tmp_rno, 5)) {
4294 {
4295   SI tmp_addr;
4296   BI tmp_postinc;
4297   tmp_postinc = FLD (f_memmode);
4298   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4299 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4300 if (EQBI (CPU (h_pbit), 0)) {
4301 {
4302   {
4303     HI opval = GET_H_SR (FLD (f_operand2));
4304     SETMEMHI (current_cpu, pc, tmp_addr, opval);
4305     written |= (1 << 11);
4306     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4307   }
4308   {
4309     BI opval = CPU (h_pbit);
4310     CPU (h_cbit) = opval;
4311     written |= (1 << 10);
4312     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4313   }
4314 }
4315 } else {
4316   {
4317     BI opval = 1;
4318     CPU (h_cbit) = opval;
4319     written |= (1 << 10);
4320     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4321   }
4322 }
4323 } else {
4324   {
4325     HI opval = GET_H_SR (FLD (f_operand2));
4326     SETMEMHI (current_cpu, pc, tmp_addr, opval);
4327     written |= (1 << 11);
4328     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4329   }
4330 }
4331 if (NEBI (tmp_postinc, 0)) {
4332 {
4333 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4334   tmp_addr = ADDSI (tmp_addr, 2);
4335 }
4336   {
4337     SI opval = tmp_addr;
4338     SET_H_GR (FLD (f_operand1), opval);
4339     written |= (1 << 9);
4340     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4341   }
4342 }
4343 }
4344 }
4345 }
4346  else if (EQSI (tmp_rno, 8)) {
4347 {
4348   SI tmp_addr;
4349   BI tmp_postinc;
4350   tmp_postinc = FLD (f_memmode);
4351   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4352 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4353 if (EQBI (CPU (h_pbit), 0)) {
4354 {
4355   {
4356     SI opval = GET_H_SR (FLD (f_operand2));
4357     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4358     written |= (1 << 13);
4359     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4360   }
4361   {
4362     BI opval = CPU (h_pbit);
4363     CPU (h_cbit) = opval;
4364     written |= (1 << 10);
4365     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4366   }
4367 }
4368 } else {
4369   {
4370     BI opval = 1;
4371     CPU (h_cbit) = opval;
4372     written |= (1 << 10);
4373     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4374   }
4375 }
4376 } else {
4377   {
4378     SI opval = GET_H_SR (FLD (f_operand2));
4379     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4380     written |= (1 << 13);
4381     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4382   }
4383 }
4384 if (NEBI (tmp_postinc, 0)) {
4385 {
4386 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4387   tmp_addr = ADDSI (tmp_addr, 4);
4388 }
4389   {
4390     SI opval = tmp_addr;
4391     SET_H_GR (FLD (f_operand1), opval);
4392     written |= (1 << 9);
4393     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4394   }
4395 }
4396 }
4397 }
4398 }
4399  else if (EQSI (tmp_rno, 9)) {
4400 {
4401   SI tmp_addr;
4402   BI tmp_postinc;
4403   tmp_postinc = FLD (f_memmode);
4404   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4405 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4406 if (EQBI (CPU (h_pbit), 0)) {
4407 {
4408   {
4409     SI opval = GET_H_SR (FLD (f_operand2));
4410     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4411     written |= (1 << 13);
4412     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4413   }
4414   {
4415     BI opval = CPU (h_pbit);
4416     CPU (h_cbit) = opval;
4417     written |= (1 << 10);
4418     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4419   }
4420 }
4421 } else {
4422   {
4423     BI opval = 1;
4424     CPU (h_cbit) = opval;
4425     written |= (1 << 10);
4426     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4427   }
4428 }
4429 } else {
4430   {
4431     SI opval = GET_H_SR (FLD (f_operand2));
4432     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4433     written |= (1 << 13);
4434     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4435   }
4436 }
4437 if (NEBI (tmp_postinc, 0)) {
4438 {
4439 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4440   tmp_addr = ADDSI (tmp_addr, 4);
4441 }
4442   {
4443     SI opval = tmp_addr;
4444     SET_H_GR (FLD (f_operand1), opval);
4445     written |= (1 << 9);
4446     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4447   }
4448 }
4449 }
4450 }
4451 }
4452  else if (EQSI (tmp_rno, 10)) {
4453 {
4454   SI tmp_addr;
4455   BI tmp_postinc;
4456   tmp_postinc = FLD (f_memmode);
4457   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4458 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4459 if (EQBI (CPU (h_pbit), 0)) {
4460 {
4461   {
4462     SI opval = GET_H_SR (FLD (f_operand2));
4463     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4464     written |= (1 << 13);
4465     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4466   }
4467   {
4468     BI opval = CPU (h_pbit);
4469     CPU (h_cbit) = opval;
4470     written |= (1 << 10);
4471     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4472   }
4473 }
4474 } else {
4475   {
4476     BI opval = 1;
4477     CPU (h_cbit) = opval;
4478     written |= (1 << 10);
4479     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4480   }
4481 }
4482 } else {
4483   {
4484     SI opval = GET_H_SR (FLD (f_operand2));
4485     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4486     written |= (1 << 13);
4487     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4488   }
4489 }
4490 if (NEBI (tmp_postinc, 0)) {
4491 {
4492 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4493   tmp_addr = ADDSI (tmp_addr, 4);
4494 }
4495   {
4496     SI opval = tmp_addr;
4497     SET_H_GR (FLD (f_operand1), opval);
4498     written |= (1 << 9);
4499     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4500   }
4501 }
4502 }
4503 }
4504 }
4505  else if (EQSI (tmp_rno, 11)) {
4506 {
4507   SI tmp_addr;
4508   BI tmp_postinc;
4509   tmp_postinc = FLD (f_memmode);
4510   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4511 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4512 if (EQBI (CPU (h_pbit), 0)) {
4513 {
4514   {
4515     SI opval = GET_H_SR (FLD (f_operand2));
4516     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4517     written |= (1 << 13);
4518     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4519   }
4520   {
4521     BI opval = CPU (h_pbit);
4522     CPU (h_cbit) = opval;
4523     written |= (1 << 10);
4524     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4525   }
4526 }
4527 } else {
4528   {
4529     BI opval = 1;
4530     CPU (h_cbit) = opval;
4531     written |= (1 << 10);
4532     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4533   }
4534 }
4535 } else {
4536   {
4537     SI opval = GET_H_SR (FLD (f_operand2));
4538     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4539     written |= (1 << 13);
4540     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4541   }
4542 }
4543 if (NEBI (tmp_postinc, 0)) {
4544 {
4545 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4546   tmp_addr = ADDSI (tmp_addr, 4);
4547 }
4548   {
4549     SI opval = tmp_addr;
4550     SET_H_GR (FLD (f_operand1), opval);
4551     written |= (1 << 9);
4552     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4553   }
4554 }
4555 }
4556 }
4557 }
4558  else if (EQSI (tmp_rno, 12)) {
4559 {
4560   SI tmp_addr;
4561   BI tmp_postinc;
4562   tmp_postinc = FLD (f_memmode);
4563   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4564 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4565 if (EQBI (CPU (h_pbit), 0)) {
4566 {
4567   {
4568     SI opval = GET_H_SR (FLD (f_operand2));
4569     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4570     written |= (1 << 13);
4571     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4572   }
4573   {
4574     BI opval = CPU (h_pbit);
4575     CPU (h_cbit) = opval;
4576     written |= (1 << 10);
4577     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4578   }
4579 }
4580 } else {
4581   {
4582     BI opval = 1;
4583     CPU (h_cbit) = opval;
4584     written |= (1 << 10);
4585     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4586   }
4587 }
4588 } else {
4589   {
4590     SI opval = GET_H_SR (FLD (f_operand2));
4591     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4592     written |= (1 << 13);
4593     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4594   }
4595 }
4596 if (NEBI (tmp_postinc, 0)) {
4597 {
4598 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4599   tmp_addr = ADDSI (tmp_addr, 4);
4600 }
4601   {
4602     SI opval = tmp_addr;
4603     SET_H_GR (FLD (f_operand1), opval);
4604     written |= (1 << 9);
4605     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4606   }
4607 }
4608 }
4609 }
4610 }
4611  else if (EQSI (tmp_rno, 13)) {
4612 {
4613   SI tmp_addr;
4614   BI tmp_postinc;
4615   tmp_postinc = FLD (f_memmode);
4616   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4617 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4618 if (EQBI (CPU (h_pbit), 0)) {
4619 {
4620   {
4621     SI opval = GET_H_SR (FLD (f_operand2));
4622     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4623     written |= (1 << 13);
4624     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4625   }
4626   {
4627     BI opval = CPU (h_pbit);
4628     CPU (h_cbit) = opval;
4629     written |= (1 << 10);
4630     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4631   }
4632 }
4633 } else {
4634   {
4635     BI opval = 1;
4636     CPU (h_cbit) = opval;
4637     written |= (1 << 10);
4638     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4639   }
4640 }
4641 } else {
4642   {
4643     SI opval = GET_H_SR (FLD (f_operand2));
4644     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4645     written |= (1 << 13);
4646     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4647   }
4648 }
4649 if (NEBI (tmp_postinc, 0)) {
4650 {
4651 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4652   tmp_addr = ADDSI (tmp_addr, 4);
4653 }
4654   {
4655     SI opval = tmp_addr;
4656     SET_H_GR (FLD (f_operand1), opval);
4657     written |= (1 << 9);
4658     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4659   }
4660 }
4661 }
4662 }
4663 }
4664  else if (EQSI (tmp_rno, 7)) {
4665 {
4666   SI tmp_addr;
4667   BI tmp_postinc;
4668   tmp_postinc = FLD (f_memmode);
4669   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4670 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4671 if (EQBI (CPU (h_pbit), 0)) {
4672 {
4673   {
4674     SI opval = GET_H_SR (FLD (f_operand2));
4675     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4676     written |= (1 << 13);
4677     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4678   }
4679   {
4680     BI opval = CPU (h_pbit);
4681     CPU (h_cbit) = opval;
4682     written |= (1 << 10);
4683     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4684   }
4685 }
4686 } else {
4687   {
4688     BI opval = 1;
4689     CPU (h_cbit) = opval;
4690     written |= (1 << 10);
4691     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4692   }
4693 }
4694 } else {
4695   {
4696     SI opval = GET_H_SR (FLD (f_operand2));
4697     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4698     written |= (1 << 13);
4699     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4700   }
4701 }
4702 if (NEBI (tmp_postinc, 0)) {
4703 {
4704 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4705   tmp_addr = ADDSI (tmp_addr, 4);
4706 }
4707   {
4708     SI opval = tmp_addr;
4709     SET_H_GR (FLD (f_operand1), opval);
4710     written |= (1 << 9);
4711     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4712   }
4713 }
4714 }
4715 }
4716 }
4717  else if (EQSI (tmp_rno, 14)) {
4718 {
4719   SI tmp_addr;
4720   BI tmp_postinc;
4721   tmp_postinc = FLD (f_memmode);
4722   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4723 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4724 if (EQBI (CPU (h_pbit), 0)) {
4725 {
4726   {
4727     SI opval = GET_H_SR (FLD (f_operand2));
4728     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4729     written |= (1 << 13);
4730     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4731   }
4732   {
4733     BI opval = CPU (h_pbit);
4734     CPU (h_cbit) = opval;
4735     written |= (1 << 10);
4736     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4737   }
4738 }
4739 } else {
4740   {
4741     BI opval = 1;
4742     CPU (h_cbit) = opval;
4743     written |= (1 << 10);
4744     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4745   }
4746 }
4747 } else {
4748   {
4749     SI opval = GET_H_SR (FLD (f_operand2));
4750     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4751     written |= (1 << 13);
4752     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4753   }
4754 }
4755 if (NEBI (tmp_postinc, 0)) {
4756 {
4757 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4758   tmp_addr = ADDSI (tmp_addr, 4);
4759 }
4760   {
4761     SI opval = tmp_addr;
4762     SET_H_GR (FLD (f_operand1), opval);
4763     written |= (1 << 9);
4764     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4765   }
4766 }
4767 }
4768 }
4769 }
4770  else if (EQSI (tmp_rno, 15)) {
4771 {
4772   SI tmp_addr;
4773   BI tmp_postinc;
4774   tmp_postinc = FLD (f_memmode);
4775   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4776 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4777 if (EQBI (CPU (h_pbit), 0)) {
4778 {
4779   {
4780     SI opval = GET_H_SR (FLD (f_operand2));
4781     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4782     written |= (1 << 13);
4783     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4784   }
4785   {
4786     BI opval = CPU (h_pbit);
4787     CPU (h_cbit) = opval;
4788     written |= (1 << 10);
4789     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4790   }
4791 }
4792 } else {
4793   {
4794     BI opval = 1;
4795     CPU (h_cbit) = opval;
4796     written |= (1 << 10);
4797     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4798   }
4799 }
4800 } else {
4801   {
4802     SI opval = GET_H_SR (FLD (f_operand2));
4803     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4804     written |= (1 << 13);
4805     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4806   }
4807 }
4808 if (NEBI (tmp_postinc, 0)) {
4809 {
4810 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4811   tmp_addr = ADDSI (tmp_addr, 4);
4812 }
4813   {
4814     SI opval = tmp_addr;
4815     SET_H_GR (FLD (f_operand1), opval);
4816     written |= (1 << 9);
4817     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4818   }
4819 }
4820 }
4821 }
4822 }
4823  else {
4824 cgen_rtx_error (current_cpu, "write from unimplemented special register");
4825 }
4826 {
4827   {
4828     BI opval = 0;
4829     CPU (h_xbit) = opval;
4830     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
4831   }
4832   {
4833     BI opval = 0;
4834     SET_H_INSN_PREFIXED_P (opval);
4835     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
4836   }
4837 }
4838 }
4839
4840   abuf->written = written;
4841 #undef FLD
4842 }
4843   NEXT (vpc);
4844
4845   CASE (sem, INSN_SBFS) : /* sbfs [${Rd-sfield}${inc}] */
4846 {
4847   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4848   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4849 #define FLD(f) abuf->fields.fmt_empty.f
4850   int UNUSED written = 0;
4851   IADDR UNUSED pc = abuf->addr;
4852   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4853
4854 cgen_rtx_error (current_cpu, "SBFS isn't implemented");
4855
4856 #undef FLD
4857 }
4858   NEXT (vpc);
4859
4860   CASE (sem, INSN_MOVEM_R_M) : /* movem ${Rs-dfield},[${Rd-sfield}${inc}] */
4861 {
4862   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4863   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4864 #define FLD(f) abuf->fields.sfmt_movem_r_m.f
4865   int UNUSED written = 0;
4866   IADDR UNUSED pc = abuf->addr;
4867   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4868
4869 {
4870   SI tmp_addr;
4871   BI tmp_postinc;
4872   tmp_postinc = FLD (f_memmode);
4873 {
4874   SI tmp_dummy;
4875   tmp_dummy = GET_H_GR (FLD (f_operand2));
4876 }
4877   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4878 {
4879 if (GESI (FLD (f_operand2), 15)) {
4880 {
4881   SI tmp_tmp;
4882   tmp_tmp = GET_H_GR (((UINT) 15));
4883   {
4884     SI opval = tmp_tmp;
4885     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4886     written |= (1 << 23);
4887     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4888   }
4889   tmp_addr = ADDSI (tmp_addr, 4);
4890 }
4891 }
4892 if (GESI (FLD (f_operand2), 14)) {
4893 {
4894   SI tmp_tmp;
4895   tmp_tmp = GET_H_GR (((UINT) 14));
4896   {
4897     SI opval = tmp_tmp;
4898     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4899     written |= (1 << 23);
4900     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4901   }
4902   tmp_addr = ADDSI (tmp_addr, 4);
4903 }
4904 }
4905 if (GESI (FLD (f_operand2), 13)) {
4906 {
4907   SI tmp_tmp;
4908   tmp_tmp = GET_H_GR (((UINT) 13));
4909   {
4910     SI opval = tmp_tmp;
4911     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4912     written |= (1 << 23);
4913     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4914   }
4915   tmp_addr = ADDSI (tmp_addr, 4);
4916 }
4917 }
4918 if (GESI (FLD (f_operand2), 12)) {
4919 {
4920   SI tmp_tmp;
4921   tmp_tmp = GET_H_GR (((UINT) 12));
4922   {
4923     SI opval = tmp_tmp;
4924     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4925     written |= (1 << 23);
4926     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4927   }
4928   tmp_addr = ADDSI (tmp_addr, 4);
4929 }
4930 }
4931 if (GESI (FLD (f_operand2), 11)) {
4932 {
4933   SI tmp_tmp;
4934   tmp_tmp = GET_H_GR (((UINT) 11));
4935   {
4936     SI opval = tmp_tmp;
4937     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4938     written |= (1 << 23);
4939     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4940   }
4941   tmp_addr = ADDSI (tmp_addr, 4);
4942 }
4943 }
4944 if (GESI (FLD (f_operand2), 10)) {
4945 {
4946   SI tmp_tmp;
4947   tmp_tmp = GET_H_GR (((UINT) 10));
4948   {
4949     SI opval = tmp_tmp;
4950     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4951     written |= (1 << 23);
4952     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4953   }
4954   tmp_addr = ADDSI (tmp_addr, 4);
4955 }
4956 }
4957 if (GESI (FLD (f_operand2), 9)) {
4958 {
4959   SI tmp_tmp;
4960   tmp_tmp = GET_H_GR (((UINT) 9));
4961   {
4962     SI opval = tmp_tmp;
4963     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4964     written |= (1 << 23);
4965     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4966   }
4967   tmp_addr = ADDSI (tmp_addr, 4);
4968 }
4969 }
4970 if (GESI (FLD (f_operand2), 8)) {
4971 {
4972   SI tmp_tmp;
4973   tmp_tmp = GET_H_GR (((UINT) 8));
4974   {
4975     SI opval = tmp_tmp;
4976     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4977     written |= (1 << 23);
4978     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4979   }
4980   tmp_addr = ADDSI (tmp_addr, 4);
4981 }
4982 }
4983 if (GESI (FLD (f_operand2), 7)) {
4984 {
4985   SI tmp_tmp;
4986   tmp_tmp = GET_H_GR (((UINT) 7));
4987   {
4988     SI opval = tmp_tmp;
4989     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4990     written |= (1 << 23);
4991     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4992   }
4993   tmp_addr = ADDSI (tmp_addr, 4);
4994 }
4995 }
4996 if (GESI (FLD (f_operand2), 6)) {
4997 {
4998   SI tmp_tmp;
4999   tmp_tmp = GET_H_GR (((UINT) 6));
5000   {
5001     SI opval = tmp_tmp;
5002     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5003     written |= (1 << 23);
5004     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5005   }
5006   tmp_addr = ADDSI (tmp_addr, 4);
5007 }
5008 }
5009 if (GESI (FLD (f_operand2), 5)) {
5010 {
5011   SI tmp_tmp;
5012   tmp_tmp = GET_H_GR (((UINT) 5));
5013   {
5014     SI opval = tmp_tmp;
5015     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5016     written |= (1 << 23);
5017     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5018   }
5019   tmp_addr = ADDSI (tmp_addr, 4);
5020 }
5021 }
5022 if (GESI (FLD (f_operand2), 4)) {
5023 {
5024   SI tmp_tmp;
5025   tmp_tmp = GET_H_GR (((UINT) 4));
5026   {
5027     SI opval = tmp_tmp;
5028     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5029     written |= (1 << 23);
5030     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5031   }
5032   tmp_addr = ADDSI (tmp_addr, 4);
5033 }
5034 }
5035 if (GESI (FLD (f_operand2), 3)) {
5036 {
5037   SI tmp_tmp;
5038   tmp_tmp = GET_H_GR (((UINT) 3));
5039   {
5040     SI opval = tmp_tmp;
5041     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5042     written |= (1 << 23);
5043     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5044   }
5045   tmp_addr = ADDSI (tmp_addr, 4);
5046 }
5047 }
5048 if (GESI (FLD (f_operand2), 2)) {
5049 {
5050   SI tmp_tmp;
5051   tmp_tmp = GET_H_GR (((UINT) 2));
5052   {
5053     SI opval = tmp_tmp;
5054     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5055     written |= (1 << 23);
5056     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5057   }
5058   tmp_addr = ADDSI (tmp_addr, 4);
5059 }
5060 }
5061 if (GESI (FLD (f_operand2), 1)) {
5062 {
5063   SI tmp_tmp;
5064   tmp_tmp = GET_H_GR (((UINT) 1));
5065   {
5066     SI opval = tmp_tmp;
5067     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5068     written |= (1 << 23);
5069     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5070   }
5071   tmp_addr = ADDSI (tmp_addr, 4);
5072 }
5073 }
5074 if (GESI (FLD (f_operand2), 0)) {
5075 {
5076   SI tmp_tmp;
5077   tmp_tmp = GET_H_GR (((UINT) 0));
5078   {
5079     SI opval = tmp_tmp;
5080     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5081     written |= (1 << 23);
5082     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5083   }
5084   tmp_addr = ADDSI (tmp_addr, 4);
5085 }
5086 }
5087 }
5088 if (NEBI (tmp_postinc, 0)) {
5089   {
5090     SI opval = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (tmp_addr) : (CPU (h_prefixreg_pre_v32)));
5091     SET_H_GR (FLD (f_operand1), opval);
5092     written |= (1 << 22);
5093     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5094   }
5095 }
5096 {
5097   {
5098     BI opval = 0;
5099     CPU (h_xbit) = opval;
5100     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5101   }
5102   {
5103     BI opval = 0;
5104     SET_H_INSN_PREFIXED_P (opval);
5105     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5106   }
5107 }
5108 }
5109
5110   abuf->written = written;
5111 #undef FLD
5112 }
5113   NEXT (vpc);
5114
5115   CASE (sem, INSN_MOVEM_M_R) : /* movem [${Rs}${inc}],${Rd} */
5116 {
5117   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5118   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5119 #define FLD(f) abuf->fields.sfmt_movem_m_r.f
5120   int UNUSED written = 0;
5121   IADDR UNUSED pc = abuf->addr;
5122   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5123
5124 {
5125   SI tmp_addr;
5126   BI tmp_postinc;
5127   tmp_postinc = FLD (f_memmode);
5128   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
5129 {
5130   SI tmp_dummy;
5131   tmp_dummy = GET_H_GR (FLD (f_operand2));
5132 }
5133 {
5134 if (GESI (FLD (f_operand2), 14)) {
5135 {
5136   SI tmp_tmp;
5137   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5138   {
5139     SI opval = tmp_tmp;
5140     SET_H_GR (((UINT) 14), opval);
5141     written |= (1 << 14);
5142     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5143   }
5144   tmp_addr = ADDSI (tmp_addr, 4);
5145 }
5146 }
5147 if (GESI (FLD (f_operand2), 13)) {
5148 {
5149   SI tmp_tmp;
5150   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5151   {
5152     SI opval = tmp_tmp;
5153     SET_H_GR (((UINT) 13), opval);
5154     written |= (1 << 13);
5155     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5156   }
5157   tmp_addr = ADDSI (tmp_addr, 4);
5158 }
5159 }
5160 if (GESI (FLD (f_operand2), 12)) {
5161 {
5162   SI tmp_tmp;
5163   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5164   {
5165     SI opval = tmp_tmp;
5166     SET_H_GR (((UINT) 12), opval);
5167     written |= (1 << 12);
5168     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5169   }
5170   tmp_addr = ADDSI (tmp_addr, 4);
5171 }
5172 }
5173 if (GESI (FLD (f_operand2), 11)) {
5174 {
5175   SI tmp_tmp;
5176   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5177   {
5178     SI opval = tmp_tmp;
5179     SET_H_GR (((UINT) 11), opval);
5180     written |= (1 << 11);
5181     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5182   }
5183   tmp_addr = ADDSI (tmp_addr, 4);
5184 }
5185 }
5186 if (GESI (FLD (f_operand2), 10)) {
5187 {
5188   SI tmp_tmp;
5189   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5190   {
5191     SI opval = tmp_tmp;
5192     SET_H_GR (((UINT) 10), opval);
5193     written |= (1 << 10);
5194     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5195   }
5196   tmp_addr = ADDSI (tmp_addr, 4);
5197 }
5198 }
5199 if (GESI (FLD (f_operand2), 9)) {
5200 {
5201   SI tmp_tmp;
5202   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5203   {
5204     SI opval = tmp_tmp;
5205     SET_H_GR (((UINT) 9), opval);
5206     written |= (1 << 22);
5207     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5208   }
5209   tmp_addr = ADDSI (tmp_addr, 4);
5210 }
5211 }
5212 if (GESI (FLD (f_operand2), 8)) {
5213 {
5214   SI tmp_tmp;
5215   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5216   {
5217     SI opval = tmp_tmp;
5218     SET_H_GR (((UINT) 8), opval);
5219     written |= (1 << 21);
5220     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5221   }
5222   tmp_addr = ADDSI (tmp_addr, 4);
5223 }
5224 }
5225 if (GESI (FLD (f_operand2), 7)) {
5226 {
5227   SI tmp_tmp;
5228   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5229   {
5230     SI opval = tmp_tmp;
5231     SET_H_GR (((UINT) 7), opval);
5232     written |= (1 << 20);
5233     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5234   }
5235   tmp_addr = ADDSI (tmp_addr, 4);
5236 }
5237 }
5238 if (GESI (FLD (f_operand2), 6)) {
5239 {
5240   SI tmp_tmp;
5241   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5242   {
5243     SI opval = tmp_tmp;
5244     SET_H_GR (((UINT) 6), opval);
5245     written |= (1 << 19);
5246     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5247   }
5248   tmp_addr = ADDSI (tmp_addr, 4);
5249 }
5250 }
5251 if (GESI (FLD (f_operand2), 5)) {
5252 {
5253   SI tmp_tmp;
5254   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5255   {
5256     SI opval = tmp_tmp;
5257     SET_H_GR (((UINT) 5), opval);
5258     written |= (1 << 18);
5259     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5260   }
5261   tmp_addr = ADDSI (tmp_addr, 4);
5262 }
5263 }
5264 if (GESI (FLD (f_operand2), 4)) {
5265 {
5266   SI tmp_tmp;
5267   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5268   {
5269     SI opval = tmp_tmp;
5270     SET_H_GR (((UINT) 4), opval);
5271     written |= (1 << 17);
5272     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5273   }
5274   tmp_addr = ADDSI (tmp_addr, 4);
5275 }
5276 }
5277 if (GESI (FLD (f_operand2), 3)) {
5278 {
5279   SI tmp_tmp;
5280   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5281   {
5282     SI opval = tmp_tmp;
5283     SET_H_GR (((UINT) 3), opval);
5284     written |= (1 << 16);
5285     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5286   }
5287   tmp_addr = ADDSI (tmp_addr, 4);
5288 }
5289 }
5290 if (GESI (FLD (f_operand2), 2)) {
5291 {
5292   SI tmp_tmp;
5293   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5294   {
5295     SI opval = tmp_tmp;
5296     SET_H_GR (((UINT) 2), opval);
5297     written |= (1 << 15);
5298     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5299   }
5300   tmp_addr = ADDSI (tmp_addr, 4);
5301 }
5302 }
5303 if (GESI (FLD (f_operand2), 1)) {
5304 {
5305   SI tmp_tmp;
5306   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5307   {
5308     SI opval = tmp_tmp;
5309     SET_H_GR (((UINT) 1), opval);
5310     written |= (1 << 9);
5311     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5312   }
5313   tmp_addr = ADDSI (tmp_addr, 4);
5314 }
5315 }
5316 if (GESI (FLD (f_operand2), 0)) {
5317 {
5318   SI tmp_tmp;
5319   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5320   {
5321     SI opval = tmp_tmp;
5322     SET_H_GR (((UINT) 0), opval);
5323     written |= (1 << 8);
5324     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5325   }
5326   tmp_addr = ADDSI (tmp_addr, 4);
5327 }
5328 }
5329 }
5330 if (NEBI (tmp_postinc, 0)) {
5331   {
5332     SI opval = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (tmp_addr) : (CPU (h_prefixreg_pre_v32)));
5333     SET_H_GR (FLD (f_operand1), opval);
5334     written |= (1 << 7);
5335     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5336   }
5337 }
5338 {
5339   {
5340     BI opval = 0;
5341     CPU (h_xbit) = opval;
5342     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5343   }
5344   {
5345     BI opval = 0;
5346     SET_H_INSN_PREFIXED_P (opval);
5347     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5348   }
5349 }
5350 }
5351
5352   abuf->written = written;
5353 #undef FLD
5354 }
5355   NEXT (vpc);
5356
5357   CASE (sem, INSN_MOVEM_M_PC) : /* movem [${Rs}${inc}],${Rd} */
5358 {
5359   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5360   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5361 #define FLD(f) abuf->fields.sfmt_movem_m_r.f
5362   int UNUSED written = 0;
5363   IADDR UNUSED pc = abuf->addr;
5364   SEM_BRANCH_INIT
5365   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5366
5367 {
5368   SI tmp_addr;
5369   BI tmp_postinc;
5370   tmp_postinc = FLD (f_memmode);
5371   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
5372 {
5373   {
5374     USI opval = GETMEMSI (current_cpu, pc, tmp_addr);
5375     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
5376     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
5377   }
5378   tmp_addr = ADDSI (tmp_addr, 4);
5379 {
5380   SI tmp_tmp;
5381   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5382   {
5383     SI opval = tmp_tmp;
5384     SET_H_GR (((UINT) 14), opval);
5385     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5386   }
5387   tmp_addr = ADDSI (tmp_addr, 4);
5388 }
5389 {
5390   SI tmp_tmp;
5391   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5392   {
5393     SI opval = tmp_tmp;
5394     SET_H_GR (((UINT) 13), opval);
5395     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5396   }
5397   tmp_addr = ADDSI (tmp_addr, 4);
5398 }
5399 {
5400   SI tmp_tmp;
5401   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5402   {
5403     SI opval = tmp_tmp;
5404     SET_H_GR (((UINT) 12), opval);
5405     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5406   }
5407   tmp_addr = ADDSI (tmp_addr, 4);
5408 }
5409 {
5410   SI tmp_tmp;
5411   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5412   {
5413     SI opval = tmp_tmp;
5414     SET_H_GR (((UINT) 11), opval);
5415     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5416   }
5417   tmp_addr = ADDSI (tmp_addr, 4);
5418 }
5419 {
5420   SI tmp_tmp;
5421   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5422   {
5423     SI opval = tmp_tmp;
5424     SET_H_GR (((UINT) 10), opval);
5425     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5426   }
5427   tmp_addr = ADDSI (tmp_addr, 4);
5428 }
5429 {
5430   SI tmp_tmp;
5431   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5432   {
5433     SI opval = tmp_tmp;
5434     SET_H_GR (((UINT) 9), opval);
5435     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5436   }
5437   tmp_addr = ADDSI (tmp_addr, 4);
5438 }
5439 {
5440   SI tmp_tmp;
5441   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5442   {
5443     SI opval = tmp_tmp;
5444     SET_H_GR (((UINT) 8), opval);
5445     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5446   }
5447   tmp_addr = ADDSI (tmp_addr, 4);
5448 }
5449 {
5450   SI tmp_tmp;
5451   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5452   {
5453     SI opval = tmp_tmp;
5454     SET_H_GR (((UINT) 7), opval);
5455     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5456   }
5457   tmp_addr = ADDSI (tmp_addr, 4);
5458 }
5459 {
5460   SI tmp_tmp;
5461   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5462   {
5463     SI opval = tmp_tmp;
5464     SET_H_GR (((UINT) 6), opval);
5465     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5466   }
5467   tmp_addr = ADDSI (tmp_addr, 4);
5468 }
5469 {
5470   SI tmp_tmp;
5471   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5472   {
5473     SI opval = tmp_tmp;
5474     SET_H_GR (((UINT) 5), opval);
5475     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5476   }
5477   tmp_addr = ADDSI (tmp_addr, 4);
5478 }
5479 {
5480   SI tmp_tmp;
5481   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5482   {
5483     SI opval = tmp_tmp;
5484     SET_H_GR (((UINT) 4), opval);
5485     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5486   }
5487   tmp_addr = ADDSI (tmp_addr, 4);
5488 }
5489 {
5490   SI tmp_tmp;
5491   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5492   {
5493     SI opval = tmp_tmp;
5494     SET_H_GR (((UINT) 3), opval);
5495     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5496   }
5497   tmp_addr = ADDSI (tmp_addr, 4);
5498 }
5499 {
5500   SI tmp_tmp;
5501   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5502   {
5503     SI opval = tmp_tmp;
5504     SET_H_GR (((UINT) 2), opval);
5505     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5506   }
5507   tmp_addr = ADDSI (tmp_addr, 4);
5508 }
5509 {
5510   SI tmp_tmp;
5511   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5512   {
5513     SI opval = tmp_tmp;
5514     SET_H_GR (((UINT) 1), opval);
5515     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5516   }
5517   tmp_addr = ADDSI (tmp_addr, 4);
5518 }
5519 {
5520   SI tmp_tmp;
5521   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5522   {
5523     SI opval = tmp_tmp;
5524     SET_H_GR (((UINT) 0), opval);
5525     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5526   }
5527   tmp_addr = ADDSI (tmp_addr, 4);
5528 }
5529 }
5530 if (NEBI (tmp_postinc, 0)) {
5531   {
5532     SI opval = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (tmp_addr) : (CPU (h_prefixreg_pre_v32)));
5533     SET_H_GR (FLD (f_operand1), opval);
5534     written |= (1 << 5);
5535     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5536   }
5537 }
5538 {
5539   {
5540     BI opval = 0;
5541     CPU (h_xbit) = opval;
5542     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5543   }
5544   {
5545     BI opval = 0;
5546     SET_H_INSN_PREFIXED_P (opval);
5547     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5548   }
5549 }
5550 }
5551
5552   abuf->written = written;
5553   SEM_BRANCH_FINI (vpc);
5554 #undef FLD
5555 }
5556   NEXT (vpc);
5557
5558   CASE (sem, INSN_ADD_B_R) : /* add.b $Rs,$Rd */
5559 {
5560   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5561   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5562 #define FLD(f) abuf->fields.sfmt_add_b_r.f
5563   int UNUSED written = 0;
5564   IADDR UNUSED pc = abuf->addr;
5565   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5566
5567 {
5568   QI tmp_tmpopd;
5569   QI tmp_tmpops;
5570   BI tmp_carry;
5571   QI tmp_newval;
5572   tmp_tmpops = GET_H_GR (FLD (f_operand1));
5573   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5574   tmp_carry = CPU (h_cbit);
5575   tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5576 {
5577   SI tmp_oldregval;
5578   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
5579   {
5580     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
5581     SET_H_GR (FLD (f_operand2), opval);
5582     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5583   }
5584 }
5585 {
5586   {
5587     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
5588     CPU (h_cbit) = opval;
5589     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5590   }
5591   {
5592     BI opval = LTQI (tmp_newval, 0);
5593     CPU (h_nbit) = opval;
5594     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5595   }
5596   {
5597     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5598     CPU (h_zbit) = opval;
5599     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5600   }
5601   {
5602     BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
5603     CPU (h_vbit) = opval;
5604     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5605   }
5606 {
5607   {
5608     BI opval = 0;
5609     CPU (h_xbit) = opval;
5610     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5611   }
5612   {
5613     BI opval = 0;
5614     SET_H_INSN_PREFIXED_P (opval);
5615     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5616   }
5617 }
5618 }
5619 }
5620
5621 #undef FLD
5622 }
5623   NEXT (vpc);
5624
5625   CASE (sem, INSN_ADD_W_R) : /* add.w $Rs,$Rd */
5626 {
5627   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5628   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5629 #define FLD(f) abuf->fields.sfmt_add_b_r.f
5630   int UNUSED written = 0;
5631   IADDR UNUSED pc = abuf->addr;
5632   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5633
5634 {
5635   HI tmp_tmpopd;
5636   HI tmp_tmpops;
5637   BI tmp_carry;
5638   HI tmp_newval;
5639   tmp_tmpops = GET_H_GR (FLD (f_operand1));
5640   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5641   tmp_carry = CPU (h_cbit);
5642   tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5643 {
5644   SI tmp_oldregval;
5645   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
5646   {
5647     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
5648     SET_H_GR (FLD (f_operand2), opval);
5649     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5650   }
5651 }
5652 {
5653   {
5654     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
5655     CPU (h_cbit) = opval;
5656     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5657   }
5658   {
5659     BI opval = LTHI (tmp_newval, 0);
5660     CPU (h_nbit) = opval;
5661     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5662   }
5663   {
5664     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5665     CPU (h_zbit) = opval;
5666     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5667   }
5668   {
5669     BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
5670     CPU (h_vbit) = opval;
5671     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5672   }
5673 {
5674   {
5675     BI opval = 0;
5676     CPU (h_xbit) = opval;
5677     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5678   }
5679   {
5680     BI opval = 0;
5681     SET_H_INSN_PREFIXED_P (opval);
5682     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5683   }
5684 }
5685 }
5686 }
5687
5688 #undef FLD
5689 }
5690   NEXT (vpc);
5691
5692   CASE (sem, INSN_ADD_D_R) : /* add.d $Rs,$Rd */
5693 {
5694   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5695   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5696 #define FLD(f) abuf->fields.sfmt_add_b_r.f
5697   int UNUSED written = 0;
5698   IADDR UNUSED pc = abuf->addr;
5699   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5700
5701 {
5702   SI tmp_tmpopd;
5703   SI tmp_tmpops;
5704   BI tmp_carry;
5705   SI tmp_newval;
5706   tmp_tmpops = GET_H_GR (FLD (f_operand1));
5707   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5708   tmp_carry = CPU (h_cbit);
5709   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5710   {
5711     SI opval = tmp_newval;
5712     SET_H_GR (FLD (f_operand2), opval);
5713     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5714   }
5715 {
5716   {
5717     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
5718     CPU (h_cbit) = opval;
5719     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5720   }
5721   {
5722     BI opval = LTSI (tmp_newval, 0);
5723     CPU (h_nbit) = opval;
5724     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5725   }
5726   {
5727     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5728     CPU (h_zbit) = opval;
5729     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5730   }
5731   {
5732     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
5733     CPU (h_vbit) = opval;
5734     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5735   }
5736 {
5737   {
5738     BI opval = 0;
5739     CPU (h_xbit) = opval;
5740     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5741   }
5742   {
5743     BI opval = 0;
5744     SET_H_INSN_PREFIXED_P (opval);
5745     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5746   }
5747 }
5748 }
5749 }
5750
5751 #undef FLD
5752 }
5753   NEXT (vpc);
5754
5755   CASE (sem, INSN_ADD_M_B_M) : /* add-m.b [${Rs}${inc}],${Rd} */
5756 {
5757   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5758   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5759 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
5760   int UNUSED written = 0;
5761   IADDR UNUSED pc = abuf->addr;
5762   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5763
5764 {
5765   QI tmp_tmpopd;
5766   QI tmp_tmpops;
5767   BI tmp_carry;
5768   QI tmp_newval;
5769   tmp_tmpops = ({   SI tmp_addr;
5770   QI tmp_tmp_mem;
5771   BI tmp_postinc;
5772   tmp_postinc = FLD (f_memmode);
5773 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
5774 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
5775 ; if (NEBI (tmp_postinc, 0)) {
5776 {
5777 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
5778   tmp_addr = ADDSI (tmp_addr, 1);
5779 }
5780   {
5781     SI opval = tmp_addr;
5782     SET_H_GR (FLD (f_operand1), opval);
5783     written |= (1 << 12);
5784     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5785   }
5786 }
5787 }
5788 ; tmp_tmp_mem; });
5789   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5790   tmp_carry = CPU (h_cbit);
5791   tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5792 {
5793   SI tmp_oldregval;
5794   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
5795   {
5796     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
5797     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
5798     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5799   }
5800 }
5801 {
5802   {
5803     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
5804     CPU (h_cbit) = opval;
5805     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5806   }
5807   {
5808     BI opval = LTQI (tmp_newval, 0);
5809     CPU (h_nbit) = opval;
5810     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5811   }
5812   {
5813     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5814     CPU (h_zbit) = opval;
5815     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5816   }
5817   {
5818     BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
5819     CPU (h_vbit) = opval;
5820     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5821   }
5822 {
5823   {
5824     BI opval = 0;
5825     CPU (h_xbit) = opval;
5826     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5827   }
5828   {
5829     BI opval = 0;
5830     SET_H_INSN_PREFIXED_P (opval);
5831     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5832   }
5833 }
5834 }
5835 }
5836
5837   abuf->written = written;
5838 #undef FLD
5839 }
5840   NEXT (vpc);
5841
5842   CASE (sem, INSN_ADD_M_W_M) : /* add-m.w [${Rs}${inc}],${Rd} */
5843 {
5844   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5845   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5846 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
5847   int UNUSED written = 0;
5848   IADDR UNUSED pc = abuf->addr;
5849   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5850
5851 {
5852   HI tmp_tmpopd;
5853   HI tmp_tmpops;
5854   BI tmp_carry;
5855   HI tmp_newval;
5856   tmp_tmpops = ({   SI tmp_addr;
5857   HI tmp_tmp_mem;
5858   BI tmp_postinc;
5859   tmp_postinc = FLD (f_memmode);
5860 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
5861 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
5862 ; if (NEBI (tmp_postinc, 0)) {
5863 {
5864 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
5865   tmp_addr = ADDSI (tmp_addr, 2);
5866 }
5867   {
5868     SI opval = tmp_addr;
5869     SET_H_GR (FLD (f_operand1), opval);
5870     written |= (1 << 12);
5871     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5872   }
5873 }
5874 }
5875 ; tmp_tmp_mem; });
5876   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5877   tmp_carry = CPU (h_cbit);
5878   tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5879 {
5880   SI tmp_oldregval;
5881   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
5882   {
5883     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
5884     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
5885     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5886   }
5887 }
5888 {
5889   {
5890     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
5891     CPU (h_cbit) = opval;
5892     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5893   }
5894   {
5895     BI opval = LTHI (tmp_newval, 0);
5896     CPU (h_nbit) = opval;
5897     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5898   }
5899   {
5900     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5901     CPU (h_zbit) = opval;
5902     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5903   }
5904   {
5905     BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
5906     CPU (h_vbit) = opval;
5907     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5908   }
5909 {
5910   {
5911     BI opval = 0;
5912     CPU (h_xbit) = opval;
5913     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5914   }
5915   {
5916     BI opval = 0;
5917     SET_H_INSN_PREFIXED_P (opval);
5918     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5919   }
5920 }
5921 }
5922 }
5923
5924   abuf->written = written;
5925 #undef FLD
5926 }
5927   NEXT (vpc);
5928
5929   CASE (sem, INSN_ADD_M_D_M) : /* add-m.d [${Rs}${inc}],${Rd} */
5930 {
5931   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5932   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5933 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
5934   int UNUSED written = 0;
5935   IADDR UNUSED pc = abuf->addr;
5936   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5937
5938 {
5939   SI tmp_tmpopd;
5940   SI tmp_tmpops;
5941   BI tmp_carry;
5942   SI tmp_newval;
5943   tmp_tmpops = ({   SI tmp_addr;
5944   SI tmp_tmp_mem;
5945   BI tmp_postinc;
5946   tmp_postinc = FLD (f_memmode);
5947 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
5948 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
5949 ; if (NEBI (tmp_postinc, 0)) {
5950 {
5951 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
5952   tmp_addr = ADDSI (tmp_addr, 4);
5953 }
5954   {
5955     SI opval = tmp_addr;
5956     SET_H_GR (FLD (f_operand1), opval);
5957     written |= (1 << 11);
5958     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5959   }
5960 }
5961 }
5962 ; tmp_tmp_mem; });
5963   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5964   tmp_carry = CPU (h_cbit);
5965   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5966   {
5967     SI opval = tmp_newval;
5968     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
5969     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5970   }
5971 {
5972   {
5973     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
5974     CPU (h_cbit) = opval;
5975     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5976   }
5977   {
5978     BI opval = LTSI (tmp_newval, 0);
5979     CPU (h_nbit) = opval;
5980     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5981   }
5982   {
5983     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5984     CPU (h_zbit) = opval;
5985     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5986   }
5987   {
5988     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
5989     CPU (h_vbit) = opval;
5990     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5991   }
5992 {
5993   {
5994     BI opval = 0;
5995     CPU (h_xbit) = opval;
5996     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5997   }
5998   {
5999     BI opval = 0;
6000     SET_H_INSN_PREFIXED_P (opval);
6001     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6002   }
6003 }
6004 }
6005 }
6006
6007   abuf->written = written;
6008 #undef FLD
6009 }
6010   NEXT (vpc);
6011
6012   CASE (sem, INSN_ADDCBR) : /* add.b ${sconst8}],${Rd} */
6013 {
6014   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6015   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6016 #define FLD(f) abuf->fields.sfmt_addcbr.f
6017   int UNUSED written = 0;
6018   IADDR UNUSED pc = abuf->addr;
6019   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6020
6021 {
6022   QI tmp_tmpopd;
6023   QI tmp_tmpops;
6024   BI tmp_carry;
6025   QI tmp_newval;
6026   tmp_tmpops = FLD (f_indir_pc__byte);
6027   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6028   tmp_carry = CPU (h_cbit);
6029   tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6030 {
6031   SI tmp_oldregval;
6032   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
6033   {
6034     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
6035     SET_H_GR (FLD (f_operand2), opval);
6036     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6037   }
6038 }
6039 {
6040   {
6041     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
6042     CPU (h_cbit) = opval;
6043     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6044   }
6045   {
6046     BI opval = LTQI (tmp_newval, 0);
6047     CPU (h_nbit) = opval;
6048     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6049   }
6050   {
6051     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6052     CPU (h_zbit) = opval;
6053     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6054   }
6055   {
6056     BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
6057     CPU (h_vbit) = opval;
6058     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6059   }
6060 {
6061   {
6062     BI opval = 0;
6063     CPU (h_xbit) = opval;
6064     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6065   }
6066   {
6067     BI opval = 0;
6068     SET_H_INSN_PREFIXED_P (opval);
6069     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6070   }
6071 }
6072 }
6073 }
6074
6075 #undef FLD
6076 }
6077   NEXT (vpc);
6078
6079   CASE (sem, INSN_ADDCWR) : /* add.w ${sconst16}],${Rd} */
6080 {
6081   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6082   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6083 #define FLD(f) abuf->fields.sfmt_addcwr.f
6084   int UNUSED written = 0;
6085   IADDR UNUSED pc = abuf->addr;
6086   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6087
6088 {
6089   HI tmp_tmpopd;
6090   HI tmp_tmpops;
6091   BI tmp_carry;
6092   HI tmp_newval;
6093   tmp_tmpops = FLD (f_indir_pc__word);
6094   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6095   tmp_carry = CPU (h_cbit);
6096   tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6097 {
6098   SI tmp_oldregval;
6099   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
6100   {
6101     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
6102     SET_H_GR (FLD (f_operand2), opval);
6103     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6104   }
6105 }
6106 {
6107   {
6108     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
6109     CPU (h_cbit) = opval;
6110     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6111   }
6112   {
6113     BI opval = LTHI (tmp_newval, 0);
6114     CPU (h_nbit) = opval;
6115     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6116   }
6117   {
6118     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6119     CPU (h_zbit) = opval;
6120     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6121   }
6122   {
6123     BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
6124     CPU (h_vbit) = opval;
6125     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6126   }
6127 {
6128   {
6129     BI opval = 0;
6130     CPU (h_xbit) = opval;
6131     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6132   }
6133   {
6134     BI opval = 0;
6135     SET_H_INSN_PREFIXED_P (opval);
6136     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6137   }
6138 }
6139 }
6140 }
6141
6142 #undef FLD
6143 }
6144   NEXT (vpc);
6145
6146   CASE (sem, INSN_ADDCDR) : /* add.d ${const32}],${Rd} */
6147 {
6148   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6149   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6150 #define FLD(f) abuf->fields.sfmt_addcdr.f
6151   int UNUSED written = 0;
6152   IADDR UNUSED pc = abuf->addr;
6153   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
6154
6155 {
6156   SI tmp_tmpopd;
6157   SI tmp_tmpops;
6158   BI tmp_carry;
6159   SI tmp_newval;
6160   tmp_tmpops = FLD (f_indir_pc__dword);
6161   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6162   tmp_carry = CPU (h_cbit);
6163   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6164   {
6165     SI opval = tmp_newval;
6166     SET_H_GR (FLD (f_operand2), opval);
6167     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6168   }
6169 {
6170   {
6171     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6172     CPU (h_cbit) = opval;
6173     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6174   }
6175   {
6176     BI opval = LTSI (tmp_newval, 0);
6177     CPU (h_nbit) = opval;
6178     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6179   }
6180   {
6181     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6182     CPU (h_zbit) = opval;
6183     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6184   }
6185   {
6186     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6187     CPU (h_vbit) = opval;
6188     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6189   }
6190 {
6191   {
6192     BI opval = 0;
6193     CPU (h_xbit) = opval;
6194     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6195   }
6196   {
6197     BI opval = 0;
6198     SET_H_INSN_PREFIXED_P (opval);
6199     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6200   }
6201 }
6202 }
6203 }
6204
6205 #undef FLD
6206 }
6207   NEXT (vpc);
6208
6209   CASE (sem, INSN_ADDCPC) : /* add.d ${sconst32},PC */
6210 {
6211   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6212   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6213 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
6214   int UNUSED written = 0;
6215   IADDR UNUSED pc = abuf->addr;
6216   SEM_BRANCH_INIT
6217   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
6218
6219 {
6220   SI tmp_newpc;
6221   SI tmp_oldpc;
6222   SI tmp_offs;
6223   tmp_offs = FLD (f_indir_pc__dword);
6224   tmp_oldpc = ADDSI (pc, 6);
6225   tmp_newpc = ADDSI (tmp_oldpc, tmp_offs);
6226   {
6227     USI opval = tmp_newpc;
6228     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
6229     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
6230   }
6231 {
6232   {
6233     BI opval = ORIF (ANDIF (LTSI (tmp_offs, 0), LTSI (tmp_oldpc, 0)), ORIF (ANDIF (LTSI (tmp_oldpc, 0), GESI (tmp_newpc, 0)), ANDIF (LTSI (tmp_offs, 0), GESI (tmp_newpc, 0))));
6234     CPU (h_cbit) = opval;
6235     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6236   }
6237   {
6238     BI opval = LTSI (tmp_newpc, 0);
6239     CPU (h_nbit) = opval;
6240     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6241   }
6242   {
6243     BI opval = ANDIF (EQSI (tmp_newpc, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6244     CPU (h_zbit) = opval;
6245     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6246   }
6247   {
6248     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_offs, 0), LTSI (tmp_oldpc, 0)), GESI (tmp_newpc, 0)), ANDIF (ANDIF (GESI (tmp_offs, 0), GESI (tmp_oldpc, 0)), LTSI (tmp_newpc, 0)));
6249     CPU (h_vbit) = opval;
6250     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6251   }
6252 {
6253   {
6254     BI opval = 0;
6255     CPU (h_xbit) = opval;
6256     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6257   }
6258   {
6259     BI opval = 0;
6260     SET_H_INSN_PREFIXED_P (opval);
6261     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6262   }
6263 }
6264 }
6265 }
6266
6267   SEM_BRANCH_FINI (vpc);
6268 #undef FLD
6269 }
6270   NEXT (vpc);
6271
6272   CASE (sem, INSN_ADDS_B_R) : /* adds.b $Rs,$Rd */
6273 {
6274   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6275   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6276 #define FLD(f) abuf->fields.sfmt_add_b_r.f
6277   int UNUSED written = 0;
6278   IADDR UNUSED pc = abuf->addr;
6279   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6280
6281 {
6282   SI tmp_tmpopd;
6283   SI tmp_tmpops;
6284   BI tmp_carry;
6285   SI tmp_newval;
6286   tmp_tmpops = EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
6287   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6288   tmp_carry = CPU (h_cbit);
6289   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6290   {
6291     SI opval = tmp_newval;
6292     SET_H_GR (FLD (f_operand2), opval);
6293     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6294   }
6295 {
6296   {
6297     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6298     CPU (h_cbit) = opval;
6299     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6300   }
6301   {
6302     BI opval = LTSI (tmp_newval, 0);
6303     CPU (h_nbit) = opval;
6304     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6305   }
6306   {
6307     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6308     CPU (h_zbit) = opval;
6309     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6310   }
6311   {
6312     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6313     CPU (h_vbit) = opval;
6314     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6315   }
6316 {
6317   {
6318     BI opval = 0;
6319     CPU (h_xbit) = opval;
6320     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6321   }
6322   {
6323     BI opval = 0;
6324     SET_H_INSN_PREFIXED_P (opval);
6325     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6326   }
6327 }
6328 }
6329 }
6330
6331 #undef FLD
6332 }
6333   NEXT (vpc);
6334
6335   CASE (sem, INSN_ADDS_W_R) : /* adds.w $Rs,$Rd */
6336 {
6337   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6338   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6339 #define FLD(f) abuf->fields.sfmt_add_b_r.f
6340   int UNUSED written = 0;
6341   IADDR UNUSED pc = abuf->addr;
6342   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6343
6344 {
6345   SI tmp_tmpopd;
6346   SI tmp_tmpops;
6347   BI tmp_carry;
6348   SI tmp_newval;
6349   tmp_tmpops = EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
6350   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6351   tmp_carry = CPU (h_cbit);
6352   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6353   {
6354     SI opval = tmp_newval;
6355     SET_H_GR (FLD (f_operand2), opval);
6356     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6357   }
6358 {
6359   {
6360     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6361     CPU (h_cbit) = opval;
6362     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6363   }
6364   {
6365     BI opval = LTSI (tmp_newval, 0);
6366     CPU (h_nbit) = opval;
6367     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6368   }
6369   {
6370     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6371     CPU (h_zbit) = opval;
6372     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6373   }
6374   {
6375     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6376     CPU (h_vbit) = opval;
6377     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6378   }
6379 {
6380   {
6381     BI opval = 0;
6382     CPU (h_xbit) = opval;
6383     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6384   }
6385   {
6386     BI opval = 0;
6387     SET_H_INSN_PREFIXED_P (opval);
6388     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6389   }
6390 }
6391 }
6392 }
6393
6394 #undef FLD
6395 }
6396   NEXT (vpc);
6397
6398   CASE (sem, INSN_ADDS_M_B_M) : /* adds-m.b [${Rs}${inc}],$Rd */
6399 {
6400   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6401   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6402 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6403   int UNUSED written = 0;
6404   IADDR UNUSED pc = abuf->addr;
6405   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6406
6407 {
6408   SI tmp_tmpopd;
6409   SI tmp_tmpops;
6410   BI tmp_carry;
6411   SI tmp_newval;
6412   tmp_tmpops = EXTQISI (({   SI tmp_addr;
6413   QI tmp_tmp_mem;
6414   BI tmp_postinc;
6415   tmp_postinc = FLD (f_memmode);
6416 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
6417 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
6418 ; if (NEBI (tmp_postinc, 0)) {
6419 {
6420 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6421   tmp_addr = ADDSI (tmp_addr, 1);
6422 }
6423   {
6424     SI opval = tmp_addr;
6425     SET_H_GR (FLD (f_operand1), opval);
6426     written |= (1 << 11);
6427     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6428   }
6429 }
6430 }
6431 ; tmp_tmp_mem; }));
6432   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6433   tmp_carry = CPU (h_cbit);
6434   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6435   {
6436     SI opval = tmp_newval;
6437     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6438     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6439   }
6440 {
6441   {
6442     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6443     CPU (h_cbit) = opval;
6444     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6445   }
6446   {
6447     BI opval = LTSI (tmp_newval, 0);
6448     CPU (h_nbit) = opval;
6449     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6450   }
6451   {
6452     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6453     CPU (h_zbit) = opval;
6454     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6455   }
6456   {
6457     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6458     CPU (h_vbit) = opval;
6459     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6460   }
6461 {
6462   {
6463     BI opval = 0;
6464     CPU (h_xbit) = opval;
6465     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6466   }
6467   {
6468     BI opval = 0;
6469     SET_H_INSN_PREFIXED_P (opval);
6470     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6471   }
6472 }
6473 }
6474 }
6475
6476   abuf->written = written;
6477 #undef FLD
6478 }
6479   NEXT (vpc);
6480
6481   CASE (sem, INSN_ADDS_M_W_M) : /* adds-m.w [${Rs}${inc}],$Rd */
6482 {
6483   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6484   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6485 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6486   int UNUSED written = 0;
6487   IADDR UNUSED pc = abuf->addr;
6488   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6489
6490 {
6491   SI tmp_tmpopd;
6492   SI tmp_tmpops;
6493   BI tmp_carry;
6494   SI tmp_newval;
6495   tmp_tmpops = EXTHISI (({   SI tmp_addr;
6496   HI tmp_tmp_mem;
6497   BI tmp_postinc;
6498   tmp_postinc = FLD (f_memmode);
6499 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
6500 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
6501 ; if (NEBI (tmp_postinc, 0)) {
6502 {
6503 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6504   tmp_addr = ADDSI (tmp_addr, 2);
6505 }
6506   {
6507     SI opval = tmp_addr;
6508     SET_H_GR (FLD (f_operand1), opval);
6509     written |= (1 << 11);
6510     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6511   }
6512 }
6513 }
6514 ; tmp_tmp_mem; }));
6515   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6516   tmp_carry = CPU (h_cbit);
6517   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6518   {
6519     SI opval = tmp_newval;
6520     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6521     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6522   }
6523 {
6524   {
6525     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6526     CPU (h_cbit) = opval;
6527     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6528   }
6529   {
6530     BI opval = LTSI (tmp_newval, 0);
6531     CPU (h_nbit) = opval;
6532     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6533   }
6534   {
6535     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6536     CPU (h_zbit) = opval;
6537     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6538   }
6539   {
6540     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6541     CPU (h_vbit) = opval;
6542     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6543   }
6544 {
6545   {
6546     BI opval = 0;
6547     CPU (h_xbit) = opval;
6548     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6549   }
6550   {
6551     BI opval = 0;
6552     SET_H_INSN_PREFIXED_P (opval);
6553     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6554   }
6555 }
6556 }
6557 }
6558
6559   abuf->written = written;
6560 #undef FLD
6561 }
6562   NEXT (vpc);
6563
6564   CASE (sem, INSN_ADDSCBR) : /* [${Rs}${inc}],$Rd */
6565 {
6566   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6567   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6568 #define FLD(f) abuf->fields.sfmt_addcbr.f
6569   int UNUSED written = 0;
6570   IADDR UNUSED pc = abuf->addr;
6571   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6572
6573 {
6574   SI tmp_tmpopd;
6575   SI tmp_tmpops;
6576   BI tmp_carry;
6577   SI tmp_newval;
6578   tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
6579   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6580   tmp_carry = CPU (h_cbit);
6581   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6582   {
6583     SI opval = tmp_newval;
6584     SET_H_GR (FLD (f_operand2), opval);
6585     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6586   }
6587 {
6588   {
6589     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6590     CPU (h_cbit) = opval;
6591     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6592   }
6593   {
6594     BI opval = LTSI (tmp_newval, 0);
6595     CPU (h_nbit) = opval;
6596     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6597   }
6598   {
6599     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6600     CPU (h_zbit) = opval;
6601     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6602   }
6603   {
6604     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6605     CPU (h_vbit) = opval;
6606     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6607   }
6608 {
6609   {
6610     BI opval = 0;
6611     CPU (h_xbit) = opval;
6612     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6613   }
6614   {
6615     BI opval = 0;
6616     SET_H_INSN_PREFIXED_P (opval);
6617     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6618   }
6619 }
6620 }
6621 }
6622
6623 #undef FLD
6624 }
6625   NEXT (vpc);
6626
6627   CASE (sem, INSN_ADDSCWR) : /* [${Rs}${inc}],$Rd */
6628 {
6629   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6630   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6631 #define FLD(f) abuf->fields.sfmt_addcwr.f
6632   int UNUSED written = 0;
6633   IADDR UNUSED pc = abuf->addr;
6634   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6635
6636 {
6637   SI tmp_tmpopd;
6638   SI tmp_tmpops;
6639   BI tmp_carry;
6640   SI tmp_newval;
6641   tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
6642   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6643   tmp_carry = CPU (h_cbit);
6644   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6645   {
6646     SI opval = tmp_newval;
6647     SET_H_GR (FLD (f_operand2), opval);
6648     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6649   }
6650 {
6651   {
6652     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6653     CPU (h_cbit) = opval;
6654     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6655   }
6656   {
6657     BI opval = LTSI (tmp_newval, 0);
6658     CPU (h_nbit) = opval;
6659     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6660   }
6661   {
6662     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6663     CPU (h_zbit) = opval;
6664     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6665   }
6666   {
6667     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6668     CPU (h_vbit) = opval;
6669     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6670   }
6671 {
6672   {
6673     BI opval = 0;
6674     CPU (h_xbit) = opval;
6675     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6676   }
6677   {
6678     BI opval = 0;
6679     SET_H_INSN_PREFIXED_P (opval);
6680     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6681   }
6682 }
6683 }
6684 }
6685
6686 #undef FLD
6687 }
6688   NEXT (vpc);
6689
6690   CASE (sem, INSN_ADDSPCPC) : /* adds.w [PC],PC */
6691 {
6692   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6693   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6694 #define FLD(f) abuf->fields.fmt_empty.f
6695   int UNUSED written = 0;
6696   IADDR UNUSED pc = abuf->addr;
6697   SEM_BRANCH_INIT
6698   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6699
6700 {
6701   SI tmp_newpc;
6702   SI tmp_oldpc;
6703   HI tmp_offs;
6704 if (NOTBI (GET_H_INSN_PREFIXED_P ())) {
6705 cgen_rtx_error (current_cpu, "Unexpected adds.w [PC],PC without prefix");
6706 }
6707   tmp_offs = GETMEMHI (current_cpu, pc, CPU (h_prefixreg_pre_v32));
6708   tmp_oldpc = ADDSI (pc, 2);
6709   tmp_newpc = ADDSI (tmp_oldpc, tmp_offs);
6710   {
6711     USI opval = tmp_newpc;
6712     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
6713     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
6714   }
6715 {
6716   {
6717     BI opval = ORIF (ANDIF (LTSI (EXTHISI (tmp_offs), 0), LTSI (tmp_oldpc, 0)), ORIF (ANDIF (LTSI (tmp_oldpc, 0), GESI (tmp_newpc, 0)), ANDIF (LTSI (EXTHISI (tmp_offs), 0), GESI (tmp_newpc, 0))));
6718     CPU (h_cbit) = opval;
6719     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6720   }
6721   {
6722     BI opval = LTSI (tmp_newpc, 0);
6723     CPU (h_nbit) = opval;
6724     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6725   }
6726   {
6727     BI opval = ANDIF (EQSI (tmp_newpc, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6728     CPU (h_zbit) = opval;
6729     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6730   }
6731   {
6732     BI opval = ORIF (ANDIF (ANDIF (LTSI (EXTHISI (tmp_offs), 0), LTSI (tmp_oldpc, 0)), GESI (tmp_newpc, 0)), ANDIF (ANDIF (GESI (EXTHISI (tmp_offs), 0), GESI (tmp_oldpc, 0)), LTSI (tmp_newpc, 0)));
6733     CPU (h_vbit) = opval;
6734     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6735   }
6736 {
6737   {
6738     BI opval = 0;
6739     CPU (h_xbit) = opval;
6740     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6741   }
6742   {
6743     BI opval = 0;
6744     SET_H_INSN_PREFIXED_P (opval);
6745     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6746   }
6747 }
6748 }
6749 }
6750
6751   SEM_BRANCH_FINI (vpc);
6752 #undef FLD
6753 }
6754   NEXT (vpc);
6755
6756   CASE (sem, INSN_ADDU_B_R) : /* addu.b $Rs,$Rd */
6757 {
6758   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6759   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6760 #define FLD(f) abuf->fields.sfmt_add_b_r.f
6761   int UNUSED written = 0;
6762   IADDR UNUSED pc = abuf->addr;
6763   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6764
6765 {
6766   SI tmp_tmpopd;
6767   SI tmp_tmpops;
6768   BI tmp_carry;
6769   SI tmp_newval;
6770   tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
6771   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6772   tmp_carry = CPU (h_cbit);
6773   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6774   {
6775     SI opval = tmp_newval;
6776     SET_H_GR (FLD (f_operand2), opval);
6777     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6778   }
6779 {
6780   {
6781     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6782     CPU (h_cbit) = opval;
6783     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6784   }
6785   {
6786     BI opval = LTSI (tmp_newval, 0);
6787     CPU (h_nbit) = opval;
6788     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6789   }
6790   {
6791     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6792     CPU (h_zbit) = opval;
6793     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6794   }
6795   {
6796     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6797     CPU (h_vbit) = opval;
6798     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6799   }
6800 {
6801   {
6802     BI opval = 0;
6803     CPU (h_xbit) = opval;
6804     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6805   }
6806   {
6807     BI opval = 0;
6808     SET_H_INSN_PREFIXED_P (opval);
6809     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6810   }
6811 }
6812 }
6813 }
6814
6815 #undef FLD
6816 }
6817   NEXT (vpc);
6818
6819   CASE (sem, INSN_ADDU_W_R) : /* addu.w $Rs,$Rd */
6820 {
6821   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6822   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6823 #define FLD(f) abuf->fields.sfmt_add_b_r.f
6824   int UNUSED written = 0;
6825   IADDR UNUSED pc = abuf->addr;
6826   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6827
6828 {
6829   SI tmp_tmpopd;
6830   SI tmp_tmpops;
6831   BI tmp_carry;
6832   SI tmp_newval;
6833   tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
6834   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6835   tmp_carry = CPU (h_cbit);
6836   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6837   {
6838     SI opval = tmp_newval;
6839     SET_H_GR (FLD (f_operand2), opval);
6840     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6841   }
6842 {
6843   {
6844     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6845     CPU (h_cbit) = opval;
6846     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6847   }
6848   {
6849     BI opval = LTSI (tmp_newval, 0);
6850     CPU (h_nbit) = opval;
6851     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6852   }
6853   {
6854     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6855     CPU (h_zbit) = opval;
6856     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6857   }
6858   {
6859     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6860     CPU (h_vbit) = opval;
6861     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6862   }
6863 {
6864   {
6865     BI opval = 0;
6866     CPU (h_xbit) = opval;
6867     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6868   }
6869   {
6870     BI opval = 0;
6871     SET_H_INSN_PREFIXED_P (opval);
6872     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6873   }
6874 }
6875 }
6876 }
6877
6878 #undef FLD
6879 }
6880   NEXT (vpc);
6881
6882   CASE (sem, INSN_ADDU_M_B_M) : /* addu-m.b [${Rs}${inc}],$Rd */
6883 {
6884   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6885   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6886 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6887   int UNUSED written = 0;
6888   IADDR UNUSED pc = abuf->addr;
6889   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6890
6891 {
6892   SI tmp_tmpopd;
6893   SI tmp_tmpops;
6894   BI tmp_carry;
6895   SI tmp_newval;
6896   tmp_tmpops = ZEXTQISI (({   SI tmp_addr;
6897   QI tmp_tmp_mem;
6898   BI tmp_postinc;
6899   tmp_postinc = FLD (f_memmode);
6900 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
6901 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
6902 ; if (NEBI (tmp_postinc, 0)) {
6903 {
6904 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6905   tmp_addr = ADDSI (tmp_addr, 1);
6906 }
6907   {
6908     SI opval = tmp_addr;
6909     SET_H_GR (FLD (f_operand1), opval);
6910     written |= (1 << 11);
6911     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6912   }
6913 }
6914 }
6915 ; tmp_tmp_mem; }));
6916   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6917   tmp_carry = CPU (h_cbit);
6918   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6919   {
6920     SI opval = tmp_newval;
6921     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6922     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6923   }
6924 {
6925   {
6926     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6927     CPU (h_cbit) = opval;
6928     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6929   }
6930   {
6931     BI opval = LTSI (tmp_newval, 0);
6932     CPU (h_nbit) = opval;
6933     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6934   }
6935   {
6936     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6937     CPU (h_zbit) = opval;
6938     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6939   }
6940   {
6941     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6942     CPU (h_vbit) = opval;
6943     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6944   }
6945 {
6946   {
6947     BI opval = 0;
6948     CPU (h_xbit) = opval;
6949     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6950   }
6951   {
6952     BI opval = 0;
6953     SET_H_INSN_PREFIXED_P (opval);
6954     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6955   }
6956 }
6957 }
6958 }
6959
6960   abuf->written = written;
6961 #undef FLD
6962 }
6963   NEXT (vpc);
6964
6965   CASE (sem, INSN_ADDU_M_W_M) : /* addu-m.w [${Rs}${inc}],$Rd */
6966 {
6967   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6968   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6969 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6970   int UNUSED written = 0;
6971   IADDR UNUSED pc = abuf->addr;
6972   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6973
6974 {
6975   SI tmp_tmpopd;
6976   SI tmp_tmpops;
6977   BI tmp_carry;
6978   SI tmp_newval;
6979   tmp_tmpops = ZEXTHISI (({   SI tmp_addr;
6980   HI tmp_tmp_mem;
6981   BI tmp_postinc;
6982   tmp_postinc = FLD (f_memmode);
6983 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
6984 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
6985 ; if (NEBI (tmp_postinc, 0)) {
6986 {
6987 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6988   tmp_addr = ADDSI (tmp_addr, 2);
6989 }
6990   {
6991     SI opval = tmp_addr;
6992     SET_H_GR (FLD (f_operand1), opval);
6993     written |= (1 << 11);
6994     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6995   }
6996 }
6997 }
6998 ; tmp_tmp_mem; }));
6999   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7000   tmp_carry = CPU (h_cbit);
7001   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7002   {
7003     SI opval = tmp_newval;
7004     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7005     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7006   }
7007 {
7008   {
7009     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
7010     CPU (h_cbit) = opval;
7011     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7012   }
7013   {
7014     BI opval = LTSI (tmp_newval, 0);
7015     CPU (h_nbit) = opval;
7016     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7017   }
7018   {
7019     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7020     CPU (h_zbit) = opval;
7021     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7022   }
7023   {
7024     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7025     CPU (h_vbit) = opval;
7026     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7027   }
7028 {
7029   {
7030     BI opval = 0;
7031     CPU (h_xbit) = opval;
7032     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7033   }
7034   {
7035     BI opval = 0;
7036     SET_H_INSN_PREFIXED_P (opval);
7037     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7038   }
7039 }
7040 }
7041 }
7042
7043   abuf->written = written;
7044 #undef FLD
7045 }
7046   NEXT (vpc);
7047
7048   CASE (sem, INSN_ADDUCBR) : /* [${Rs}${inc}],$Rd */
7049 {
7050   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7051   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7052 #define FLD(f) abuf->fields.sfmt_addcbr.f
7053   int UNUSED written = 0;
7054   IADDR UNUSED pc = abuf->addr;
7055   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7056
7057 {
7058   SI tmp_tmpopd;
7059   SI tmp_tmpops;
7060   BI tmp_carry;
7061   SI tmp_newval;
7062   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
7063   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7064   tmp_carry = CPU (h_cbit);
7065   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7066   {
7067     SI opval = tmp_newval;
7068     SET_H_GR (FLD (f_operand2), opval);
7069     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7070   }
7071 {
7072   {
7073     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
7074     CPU (h_cbit) = opval;
7075     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7076   }
7077   {
7078     BI opval = LTSI (tmp_newval, 0);
7079     CPU (h_nbit) = opval;
7080     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7081   }
7082   {
7083     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7084     CPU (h_zbit) = opval;
7085     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7086   }
7087   {
7088     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7089     CPU (h_vbit) = opval;
7090     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7091   }
7092 {
7093   {
7094     BI opval = 0;
7095     CPU (h_xbit) = opval;
7096     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7097   }
7098   {
7099     BI opval = 0;
7100     SET_H_INSN_PREFIXED_P (opval);
7101     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7102   }
7103 }
7104 }
7105 }
7106
7107 #undef FLD
7108 }
7109   NEXT (vpc);
7110
7111   CASE (sem, INSN_ADDUCWR) : /* [${Rs}${inc}],$Rd */
7112 {
7113   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7114   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7115 #define FLD(f) abuf->fields.sfmt_addcwr.f
7116   int UNUSED written = 0;
7117   IADDR UNUSED pc = abuf->addr;
7118   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7119
7120 {
7121   SI tmp_tmpopd;
7122   SI tmp_tmpops;
7123   BI tmp_carry;
7124   SI tmp_newval;
7125   tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
7126   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7127   tmp_carry = CPU (h_cbit);
7128   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7129   {
7130     SI opval = tmp_newval;
7131     SET_H_GR (FLD (f_operand2), opval);
7132     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7133   }
7134 {
7135   {
7136     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
7137     CPU (h_cbit) = opval;
7138     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7139   }
7140   {
7141     BI opval = LTSI (tmp_newval, 0);
7142     CPU (h_nbit) = opval;
7143     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7144   }
7145   {
7146     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7147     CPU (h_zbit) = opval;
7148     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7149   }
7150   {
7151     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7152     CPU (h_vbit) = opval;
7153     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7154   }
7155 {
7156   {
7157     BI opval = 0;
7158     CPU (h_xbit) = opval;
7159     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7160   }
7161   {
7162     BI opval = 0;
7163     SET_H_INSN_PREFIXED_P (opval);
7164     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7165   }
7166 }
7167 }
7168 }
7169
7170 #undef FLD
7171 }
7172   NEXT (vpc);
7173
7174   CASE (sem, INSN_SUB_B_R) : /* sub.b $Rs,$Rd */
7175 {
7176   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7177   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7178 #define FLD(f) abuf->fields.sfmt_add_b_r.f
7179   int UNUSED written = 0;
7180   IADDR UNUSED pc = abuf->addr;
7181   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7182
7183 {
7184   QI tmp_tmpopd;
7185   QI tmp_tmpops;
7186   BI tmp_carry;
7187   QI tmp_newval;
7188   tmp_tmpops = GET_H_GR (FLD (f_operand1));
7189   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7190   tmp_carry = CPU (h_cbit);
7191   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7192 {
7193   SI tmp_oldregval;
7194   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
7195   {
7196     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
7197     SET_H_GR (FLD (f_operand2), opval);
7198     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7199   }
7200 }
7201 {
7202   {
7203     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
7204     CPU (h_cbit) = opval;
7205     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7206   }
7207   {
7208     BI opval = LTQI (tmp_newval, 0);
7209     CPU (h_nbit) = opval;
7210     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7211   }
7212   {
7213     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7214     CPU (h_zbit) = opval;
7215     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7216   }
7217   {
7218     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
7219     CPU (h_vbit) = opval;
7220     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7221   }
7222 {
7223   {
7224     BI opval = 0;
7225     CPU (h_xbit) = opval;
7226     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7227   }
7228   {
7229     BI opval = 0;
7230     SET_H_INSN_PREFIXED_P (opval);
7231     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7232   }
7233 }
7234 }
7235 }
7236
7237 #undef FLD
7238 }
7239   NEXT (vpc);
7240
7241   CASE (sem, INSN_SUB_W_R) : /* sub.w $Rs,$Rd */
7242 {
7243   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7244   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7245 #define FLD(f) abuf->fields.sfmt_add_b_r.f
7246   int UNUSED written = 0;
7247   IADDR UNUSED pc = abuf->addr;
7248   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7249
7250 {
7251   HI tmp_tmpopd;
7252   HI tmp_tmpops;
7253   BI tmp_carry;
7254   HI tmp_newval;
7255   tmp_tmpops = GET_H_GR (FLD (f_operand1));
7256   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7257   tmp_carry = CPU (h_cbit);
7258   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7259 {
7260   SI tmp_oldregval;
7261   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
7262   {
7263     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
7264     SET_H_GR (FLD (f_operand2), opval);
7265     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7266   }
7267 }
7268 {
7269   {
7270     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
7271     CPU (h_cbit) = opval;
7272     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7273   }
7274   {
7275     BI opval = LTHI (tmp_newval, 0);
7276     CPU (h_nbit) = opval;
7277     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7278   }
7279   {
7280     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7281     CPU (h_zbit) = opval;
7282     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7283   }
7284   {
7285     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
7286     CPU (h_vbit) = opval;
7287     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7288   }
7289 {
7290   {
7291     BI opval = 0;
7292     CPU (h_xbit) = opval;
7293     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7294   }
7295   {
7296     BI opval = 0;
7297     SET_H_INSN_PREFIXED_P (opval);
7298     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7299   }
7300 }
7301 }
7302 }
7303
7304 #undef FLD
7305 }
7306   NEXT (vpc);
7307
7308   CASE (sem, INSN_SUB_D_R) : /* sub.d $Rs,$Rd */
7309 {
7310   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7311   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7312 #define FLD(f) abuf->fields.sfmt_add_b_r.f
7313   int UNUSED written = 0;
7314   IADDR UNUSED pc = abuf->addr;
7315   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7316
7317 {
7318   SI tmp_tmpopd;
7319   SI tmp_tmpops;
7320   BI tmp_carry;
7321   SI tmp_newval;
7322   tmp_tmpops = GET_H_GR (FLD (f_operand1));
7323   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7324   tmp_carry = CPU (h_cbit);
7325   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7326   {
7327     SI opval = tmp_newval;
7328     SET_H_GR (FLD (f_operand2), opval);
7329     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7330   }
7331 {
7332   {
7333     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7334     CPU (h_cbit) = opval;
7335     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7336   }
7337   {
7338     BI opval = LTSI (tmp_newval, 0);
7339     CPU (h_nbit) = opval;
7340     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7341   }
7342   {
7343     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7344     CPU (h_zbit) = opval;
7345     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7346   }
7347   {
7348     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7349     CPU (h_vbit) = opval;
7350     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7351   }
7352 {
7353   {
7354     BI opval = 0;
7355     CPU (h_xbit) = opval;
7356     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7357   }
7358   {
7359     BI opval = 0;
7360     SET_H_INSN_PREFIXED_P (opval);
7361     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7362   }
7363 }
7364 }
7365 }
7366
7367 #undef FLD
7368 }
7369   NEXT (vpc);
7370
7371   CASE (sem, INSN_SUB_M_B_M) : /* sub-m.b [${Rs}${inc}],${Rd} */
7372 {
7373   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7374   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7375 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7376   int UNUSED written = 0;
7377   IADDR UNUSED pc = abuf->addr;
7378   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7379
7380 {
7381   QI tmp_tmpopd;
7382   QI tmp_tmpops;
7383   BI tmp_carry;
7384   QI tmp_newval;
7385   tmp_tmpops = ({   SI tmp_addr;
7386   QI tmp_tmp_mem;
7387   BI tmp_postinc;
7388   tmp_postinc = FLD (f_memmode);
7389 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
7390 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
7391 ; if (NEBI (tmp_postinc, 0)) {
7392 {
7393 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7394   tmp_addr = ADDSI (tmp_addr, 1);
7395 }
7396   {
7397     SI opval = tmp_addr;
7398     SET_H_GR (FLD (f_operand1), opval);
7399     written |= (1 << 12);
7400     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7401   }
7402 }
7403 }
7404 ; tmp_tmp_mem; });
7405   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7406   tmp_carry = CPU (h_cbit);
7407   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7408 {
7409   SI tmp_oldregval;
7410   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
7411   {
7412     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
7413     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7414     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7415   }
7416 }
7417 {
7418   {
7419     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
7420     CPU (h_cbit) = opval;
7421     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7422   }
7423   {
7424     BI opval = LTQI (tmp_newval, 0);
7425     CPU (h_nbit) = opval;
7426     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7427   }
7428   {
7429     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7430     CPU (h_zbit) = opval;
7431     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7432   }
7433   {
7434     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
7435     CPU (h_vbit) = opval;
7436     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7437   }
7438 {
7439   {
7440     BI opval = 0;
7441     CPU (h_xbit) = opval;
7442     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7443   }
7444   {
7445     BI opval = 0;
7446     SET_H_INSN_PREFIXED_P (opval);
7447     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7448   }
7449 }
7450 }
7451 }
7452
7453   abuf->written = written;
7454 #undef FLD
7455 }
7456   NEXT (vpc);
7457
7458   CASE (sem, INSN_SUB_M_W_M) : /* sub-m.w [${Rs}${inc}],${Rd} */
7459 {
7460   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7461   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7462 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7463   int UNUSED written = 0;
7464   IADDR UNUSED pc = abuf->addr;
7465   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7466
7467 {
7468   HI tmp_tmpopd;
7469   HI tmp_tmpops;
7470   BI tmp_carry;
7471   HI tmp_newval;
7472   tmp_tmpops = ({   SI tmp_addr;
7473   HI tmp_tmp_mem;
7474   BI tmp_postinc;
7475   tmp_postinc = FLD (f_memmode);
7476 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
7477 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
7478 ; if (NEBI (tmp_postinc, 0)) {
7479 {
7480 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7481   tmp_addr = ADDSI (tmp_addr, 2);
7482 }
7483   {
7484     SI opval = tmp_addr;
7485     SET_H_GR (FLD (f_operand1), opval);
7486     written |= (1 << 12);
7487     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7488   }
7489 }
7490 }
7491 ; tmp_tmp_mem; });
7492   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7493   tmp_carry = CPU (h_cbit);
7494   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7495 {
7496   SI tmp_oldregval;
7497   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
7498   {
7499     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
7500     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7501     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7502   }
7503 }
7504 {
7505   {
7506     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
7507     CPU (h_cbit) = opval;
7508     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7509   }
7510   {
7511     BI opval = LTHI (tmp_newval, 0);
7512     CPU (h_nbit) = opval;
7513     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7514   }
7515   {
7516     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7517     CPU (h_zbit) = opval;
7518     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7519   }
7520   {
7521     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
7522     CPU (h_vbit) = opval;
7523     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7524   }
7525 {
7526   {
7527     BI opval = 0;
7528     CPU (h_xbit) = opval;
7529     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7530   }
7531   {
7532     BI opval = 0;
7533     SET_H_INSN_PREFIXED_P (opval);
7534     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7535   }
7536 }
7537 }
7538 }
7539
7540   abuf->written = written;
7541 #undef FLD
7542 }
7543   NEXT (vpc);
7544
7545   CASE (sem, INSN_SUB_M_D_M) : /* sub-m.d [${Rs}${inc}],${Rd} */
7546 {
7547   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7548   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7549 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7550   int UNUSED written = 0;
7551   IADDR UNUSED pc = abuf->addr;
7552   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7553
7554 {
7555   SI tmp_tmpopd;
7556   SI tmp_tmpops;
7557   BI tmp_carry;
7558   SI tmp_newval;
7559   tmp_tmpops = ({   SI tmp_addr;
7560   SI tmp_tmp_mem;
7561   BI tmp_postinc;
7562   tmp_postinc = FLD (f_memmode);
7563 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
7564 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
7565 ; if (NEBI (tmp_postinc, 0)) {
7566 {
7567 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7568   tmp_addr = ADDSI (tmp_addr, 4);
7569 }
7570   {
7571     SI opval = tmp_addr;
7572     SET_H_GR (FLD (f_operand1), opval);
7573     written |= (1 << 11);
7574     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7575   }
7576 }
7577 }
7578 ; tmp_tmp_mem; });
7579   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7580   tmp_carry = CPU (h_cbit);
7581   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7582   {
7583     SI opval = tmp_newval;
7584     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7585     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7586   }
7587 {
7588   {
7589     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7590     CPU (h_cbit) = opval;
7591     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7592   }
7593   {
7594     BI opval = LTSI (tmp_newval, 0);
7595     CPU (h_nbit) = opval;
7596     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7597   }
7598   {
7599     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7600     CPU (h_zbit) = opval;
7601     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7602   }
7603   {
7604     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7605     CPU (h_vbit) = opval;
7606     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7607   }
7608 {
7609   {
7610     BI opval = 0;
7611     CPU (h_xbit) = opval;
7612     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7613   }
7614   {
7615     BI opval = 0;
7616     SET_H_INSN_PREFIXED_P (opval);
7617     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7618   }
7619 }
7620 }
7621 }
7622
7623   abuf->written = written;
7624 #undef FLD
7625 }
7626   NEXT (vpc);
7627
7628   CASE (sem, INSN_SUBCBR) : /* sub.b ${sconst8}],${Rd} */
7629 {
7630   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7631   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7632 #define FLD(f) abuf->fields.sfmt_addcbr.f
7633   int UNUSED written = 0;
7634   IADDR UNUSED pc = abuf->addr;
7635   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7636
7637 {
7638   QI tmp_tmpopd;
7639   QI tmp_tmpops;
7640   BI tmp_carry;
7641   QI tmp_newval;
7642   tmp_tmpops = FLD (f_indir_pc__byte);
7643   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7644   tmp_carry = CPU (h_cbit);
7645   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7646 {
7647   SI tmp_oldregval;
7648   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
7649   {
7650     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
7651     SET_H_GR (FLD (f_operand2), opval);
7652     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7653   }
7654 }
7655 {
7656   {
7657     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
7658     CPU (h_cbit) = opval;
7659     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7660   }
7661   {
7662     BI opval = LTQI (tmp_newval, 0);
7663     CPU (h_nbit) = opval;
7664     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7665   }
7666   {
7667     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7668     CPU (h_zbit) = opval;
7669     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7670   }
7671   {
7672     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
7673     CPU (h_vbit) = opval;
7674     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7675   }
7676 {
7677   {
7678     BI opval = 0;
7679     CPU (h_xbit) = opval;
7680     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7681   }
7682   {
7683     BI opval = 0;
7684     SET_H_INSN_PREFIXED_P (opval);
7685     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7686   }
7687 }
7688 }
7689 }
7690
7691 #undef FLD
7692 }
7693   NEXT (vpc);
7694
7695   CASE (sem, INSN_SUBCWR) : /* sub.w ${sconst16}],${Rd} */
7696 {
7697   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7698   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7699 #define FLD(f) abuf->fields.sfmt_addcwr.f
7700   int UNUSED written = 0;
7701   IADDR UNUSED pc = abuf->addr;
7702   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7703
7704 {
7705   HI tmp_tmpopd;
7706   HI tmp_tmpops;
7707   BI tmp_carry;
7708   HI tmp_newval;
7709   tmp_tmpops = FLD (f_indir_pc__word);
7710   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7711   tmp_carry = CPU (h_cbit);
7712   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7713 {
7714   SI tmp_oldregval;
7715   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
7716   {
7717     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
7718     SET_H_GR (FLD (f_operand2), opval);
7719     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7720   }
7721 }
7722 {
7723   {
7724     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
7725     CPU (h_cbit) = opval;
7726     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7727   }
7728   {
7729     BI opval = LTHI (tmp_newval, 0);
7730     CPU (h_nbit) = opval;
7731     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7732   }
7733   {
7734     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7735     CPU (h_zbit) = opval;
7736     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7737   }
7738   {
7739     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
7740     CPU (h_vbit) = opval;
7741     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7742   }
7743 {
7744   {
7745     BI opval = 0;
7746     CPU (h_xbit) = opval;
7747     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7748   }
7749   {
7750     BI opval = 0;
7751     SET_H_INSN_PREFIXED_P (opval);
7752     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7753   }
7754 }
7755 }
7756 }
7757
7758 #undef FLD
7759 }
7760   NEXT (vpc);
7761
7762   CASE (sem, INSN_SUBCDR) : /* sub.d ${const32}],${Rd} */
7763 {
7764   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7765   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7766 #define FLD(f) abuf->fields.sfmt_addcdr.f
7767   int UNUSED written = 0;
7768   IADDR UNUSED pc = abuf->addr;
7769   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
7770
7771 {
7772   SI tmp_tmpopd;
7773   SI tmp_tmpops;
7774   BI tmp_carry;
7775   SI tmp_newval;
7776   tmp_tmpops = FLD (f_indir_pc__dword);
7777   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7778   tmp_carry = CPU (h_cbit);
7779   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7780   {
7781     SI opval = tmp_newval;
7782     SET_H_GR (FLD (f_operand2), opval);
7783     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7784   }
7785 {
7786   {
7787     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7788     CPU (h_cbit) = opval;
7789     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7790   }
7791   {
7792     BI opval = LTSI (tmp_newval, 0);
7793     CPU (h_nbit) = opval;
7794     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7795   }
7796   {
7797     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7798     CPU (h_zbit) = opval;
7799     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7800   }
7801   {
7802     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7803     CPU (h_vbit) = opval;
7804     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7805   }
7806 {
7807   {
7808     BI opval = 0;
7809     CPU (h_xbit) = opval;
7810     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7811   }
7812   {
7813     BI opval = 0;
7814     SET_H_INSN_PREFIXED_P (opval);
7815     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7816   }
7817 }
7818 }
7819 }
7820
7821 #undef FLD
7822 }
7823   NEXT (vpc);
7824
7825   CASE (sem, INSN_SUBS_B_R) : /* subs.b $Rs,$Rd */
7826 {
7827   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7828   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7829 #define FLD(f) abuf->fields.sfmt_add_b_r.f
7830   int UNUSED written = 0;
7831   IADDR UNUSED pc = abuf->addr;
7832   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7833
7834 {
7835   SI tmp_tmpopd;
7836   SI tmp_tmpops;
7837   BI tmp_carry;
7838   SI tmp_newval;
7839   tmp_tmpops = EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
7840   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7841   tmp_carry = CPU (h_cbit);
7842   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7843   {
7844     SI opval = tmp_newval;
7845     SET_H_GR (FLD (f_operand2), opval);
7846     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7847   }
7848 {
7849   {
7850     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7851     CPU (h_cbit) = opval;
7852     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7853   }
7854   {
7855     BI opval = LTSI (tmp_newval, 0);
7856     CPU (h_nbit) = opval;
7857     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7858   }
7859   {
7860     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7861     CPU (h_zbit) = opval;
7862     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7863   }
7864   {
7865     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7866     CPU (h_vbit) = opval;
7867     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7868   }
7869 {
7870   {
7871     BI opval = 0;
7872     CPU (h_xbit) = opval;
7873     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7874   }
7875   {
7876     BI opval = 0;
7877     SET_H_INSN_PREFIXED_P (opval);
7878     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7879   }
7880 }
7881 }
7882 }
7883
7884 #undef FLD
7885 }
7886   NEXT (vpc);
7887
7888   CASE (sem, INSN_SUBS_W_R) : /* subs.w $Rs,$Rd */
7889 {
7890   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7891   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7892 #define FLD(f) abuf->fields.sfmt_add_b_r.f
7893   int UNUSED written = 0;
7894   IADDR UNUSED pc = abuf->addr;
7895   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7896
7897 {
7898   SI tmp_tmpopd;
7899   SI tmp_tmpops;
7900   BI tmp_carry;
7901   SI tmp_newval;
7902   tmp_tmpops = EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
7903   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7904   tmp_carry = CPU (h_cbit);
7905   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7906   {
7907     SI opval = tmp_newval;
7908     SET_H_GR (FLD (f_operand2), opval);
7909     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7910   }
7911 {
7912   {
7913     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7914     CPU (h_cbit) = opval;
7915     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7916   }
7917   {
7918     BI opval = LTSI (tmp_newval, 0);
7919     CPU (h_nbit) = opval;
7920     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7921   }
7922   {
7923     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7924     CPU (h_zbit) = opval;
7925     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7926   }
7927   {
7928     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7929     CPU (h_vbit) = opval;
7930     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7931   }
7932 {
7933   {
7934     BI opval = 0;
7935     CPU (h_xbit) = opval;
7936     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7937   }
7938   {
7939     BI opval = 0;
7940     SET_H_INSN_PREFIXED_P (opval);
7941     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7942   }
7943 }
7944 }
7945 }
7946
7947 #undef FLD
7948 }
7949   NEXT (vpc);
7950
7951   CASE (sem, INSN_SUBS_M_B_M) : /* subs-m.b [${Rs}${inc}],$Rd */
7952 {
7953   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7954   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7955 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7956   int UNUSED written = 0;
7957   IADDR UNUSED pc = abuf->addr;
7958   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7959
7960 {
7961   SI tmp_tmpopd;
7962   SI tmp_tmpops;
7963   BI tmp_carry;
7964   SI tmp_newval;
7965   tmp_tmpops = EXTQISI (({   SI tmp_addr;
7966   QI tmp_tmp_mem;
7967   BI tmp_postinc;
7968   tmp_postinc = FLD (f_memmode);
7969 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
7970 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
7971 ; if (NEBI (tmp_postinc, 0)) {
7972 {
7973 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7974   tmp_addr = ADDSI (tmp_addr, 1);
7975 }
7976   {
7977     SI opval = tmp_addr;
7978     SET_H_GR (FLD (f_operand1), opval);
7979     written |= (1 << 11);
7980     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7981   }
7982 }
7983 }
7984 ; tmp_tmp_mem; }));
7985   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7986   tmp_carry = CPU (h_cbit);
7987   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7988   {
7989     SI opval = tmp_newval;
7990     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7991     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7992   }
7993 {
7994   {
7995     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7996     CPU (h_cbit) = opval;
7997     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7998   }
7999   {
8000     BI opval = LTSI (tmp_newval, 0);
8001     CPU (h_nbit) = opval;
8002     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8003   }
8004   {
8005     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8006     CPU (h_zbit) = opval;
8007     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8008   }
8009   {
8010     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8011     CPU (h_vbit) = opval;
8012     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8013   }
8014 {
8015   {
8016     BI opval = 0;
8017     CPU (h_xbit) = opval;
8018     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8019   }
8020   {
8021     BI opval = 0;
8022     SET_H_INSN_PREFIXED_P (opval);
8023     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8024   }
8025 }
8026 }
8027 }
8028
8029   abuf->written = written;
8030 #undef FLD
8031 }
8032   NEXT (vpc);
8033
8034   CASE (sem, INSN_SUBS_M_W_M) : /* subs-m.w [${Rs}${inc}],$Rd */
8035 {
8036   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8037   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8038 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
8039   int UNUSED written = 0;
8040   IADDR UNUSED pc = abuf->addr;
8041   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8042
8043 {
8044   SI tmp_tmpopd;
8045   SI tmp_tmpops;
8046   BI tmp_carry;
8047   SI tmp_newval;
8048   tmp_tmpops = EXTHISI (({   SI tmp_addr;
8049   HI tmp_tmp_mem;
8050   BI tmp_postinc;
8051   tmp_postinc = FLD (f_memmode);
8052 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
8053 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
8054 ; if (NEBI (tmp_postinc, 0)) {
8055 {
8056 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8057   tmp_addr = ADDSI (tmp_addr, 2);
8058 }
8059   {
8060     SI opval = tmp_addr;
8061     SET_H_GR (FLD (f_operand1), opval);
8062     written |= (1 << 11);
8063     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8064   }
8065 }
8066 }
8067 ; tmp_tmp_mem; }));
8068   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8069   tmp_carry = CPU (h_cbit);
8070   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8071   {
8072     SI opval = tmp_newval;
8073     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
8074     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8075   }
8076 {
8077   {
8078     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8079     CPU (h_cbit) = opval;
8080     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8081   }
8082   {
8083     BI opval = LTSI (tmp_newval, 0);
8084     CPU (h_nbit) = opval;
8085     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8086   }
8087   {
8088     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8089     CPU (h_zbit) = opval;
8090     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8091   }
8092   {
8093     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8094     CPU (h_vbit) = opval;
8095     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8096   }
8097 {
8098   {
8099     BI opval = 0;
8100     CPU (h_xbit) = opval;
8101     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8102   }
8103   {
8104     BI opval = 0;
8105     SET_H_INSN_PREFIXED_P (opval);
8106     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8107   }
8108 }
8109 }
8110 }
8111
8112   abuf->written = written;
8113 #undef FLD
8114 }
8115   NEXT (vpc);
8116
8117   CASE (sem, INSN_SUBSCBR) : /* [${Rs}${inc}],$Rd */
8118 {
8119   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8120   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8121 #define FLD(f) abuf->fields.sfmt_addcbr.f
8122   int UNUSED written = 0;
8123   IADDR UNUSED pc = abuf->addr;
8124   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
8125
8126 {
8127   SI tmp_tmpopd;
8128   SI tmp_tmpops;
8129   BI tmp_carry;
8130   SI tmp_newval;
8131   tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
8132   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8133   tmp_carry = CPU (h_cbit);
8134   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8135   {
8136     SI opval = tmp_newval;
8137     SET_H_GR (FLD (f_operand2), opval);
8138     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8139   }
8140 {
8141   {
8142     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8143     CPU (h_cbit) = opval;
8144     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8145   }
8146   {
8147     BI opval = LTSI (tmp_newval, 0);
8148     CPU (h_nbit) = opval;
8149     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8150   }
8151   {
8152     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8153     CPU (h_zbit) = opval;
8154     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8155   }
8156   {
8157     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8158     CPU (h_vbit) = opval;
8159     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8160   }
8161 {
8162   {
8163     BI opval = 0;
8164     CPU (h_xbit) = opval;
8165     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8166   }
8167   {
8168     BI opval = 0;
8169     SET_H_INSN_PREFIXED_P (opval);
8170     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8171   }
8172 }
8173 }
8174 }
8175
8176 #undef FLD
8177 }
8178   NEXT (vpc);
8179
8180   CASE (sem, INSN_SUBSCWR) : /* [${Rs}${inc}],$Rd */
8181 {
8182   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8183   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8184 #define FLD(f) abuf->fields.sfmt_addcwr.f
8185   int UNUSED written = 0;
8186   IADDR UNUSED pc = abuf->addr;
8187   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
8188
8189 {
8190   SI tmp_tmpopd;
8191   SI tmp_tmpops;
8192   BI tmp_carry;
8193   SI tmp_newval;
8194   tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
8195   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8196   tmp_carry = CPU (h_cbit);
8197   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8198   {
8199     SI opval = tmp_newval;
8200     SET_H_GR (FLD (f_operand2), opval);
8201     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8202   }
8203 {
8204   {
8205     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8206     CPU (h_cbit) = opval;
8207     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8208   }
8209   {
8210     BI opval = LTSI (tmp_newval, 0);
8211     CPU (h_nbit) = opval;
8212     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8213   }
8214   {
8215     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8216     CPU (h_zbit) = opval;
8217     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8218   }
8219   {
8220     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8221     CPU (h_vbit) = opval;
8222     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8223   }
8224 {
8225   {
8226     BI opval = 0;
8227     CPU (h_xbit) = opval;
8228     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8229   }
8230   {
8231     BI opval = 0;
8232     SET_H_INSN_PREFIXED_P (opval);
8233     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8234   }
8235 }
8236 }
8237 }
8238
8239 #undef FLD
8240 }
8241   NEXT (vpc);
8242
8243   CASE (sem, INSN_SUBU_B_R) : /* subu.b $Rs,$Rd */
8244 {
8245   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8246   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8247 #define FLD(f) abuf->fields.sfmt_add_b_r.f
8248   int UNUSED written = 0;
8249   IADDR UNUSED pc = abuf->addr;
8250   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8251
8252 {
8253   SI tmp_tmpopd;
8254   SI tmp_tmpops;
8255   BI tmp_carry;
8256   SI tmp_newval;
8257   tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
8258   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8259   tmp_carry = CPU (h_cbit);
8260   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8261   {
8262     SI opval = tmp_newval;
8263     SET_H_GR (FLD (f_operand2), opval);
8264     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8265   }
8266 {
8267   {
8268     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8269     CPU (h_cbit) = opval;
8270     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8271   }
8272   {
8273     BI opval = LTSI (tmp_newval, 0);
8274     CPU (h_nbit) = opval;
8275     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8276   }
8277   {
8278     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8279     CPU (h_zbit) = opval;
8280     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8281   }
8282   {
8283     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8284     CPU (h_vbit) = opval;
8285     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8286   }
8287 {
8288   {
8289     BI opval = 0;
8290     CPU (h_xbit) = opval;
8291     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8292   }
8293   {
8294     BI opval = 0;
8295     SET_H_INSN_PREFIXED_P (opval);
8296     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8297   }
8298 }
8299 }
8300 }
8301
8302 #undef FLD
8303 }
8304   NEXT (vpc);
8305
8306   CASE (sem, INSN_SUBU_W_R) : /* subu.w $Rs,$Rd */
8307 {
8308   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8309   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8310 #define FLD(f) abuf->fields.sfmt_add_b_r.f
8311   int UNUSED written = 0;
8312   IADDR UNUSED pc = abuf->addr;
8313   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8314
8315 {
8316   SI tmp_tmpopd;
8317   SI tmp_tmpops;
8318   BI tmp_carry;
8319   SI tmp_newval;
8320   tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
8321   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8322   tmp_carry = CPU (h_cbit);
8323   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8324   {
8325     SI opval = tmp_newval;
8326     SET_H_GR (FLD (f_operand2), opval);
8327     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8328   }
8329 {
8330   {
8331     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8332     CPU (h_cbit) = opval;
8333     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8334   }
8335   {
8336     BI opval = LTSI (tmp_newval, 0);
8337     CPU (h_nbit) = opval;
8338     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8339   }
8340   {
8341     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8342     CPU (h_zbit) = opval;
8343     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8344   }
8345   {
8346     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8347     CPU (h_vbit) = opval;
8348     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8349   }
8350 {
8351   {
8352     BI opval = 0;
8353     CPU (h_xbit) = opval;
8354     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8355   }
8356   {
8357     BI opval = 0;
8358     SET_H_INSN_PREFIXED_P (opval);
8359     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8360   }
8361 }
8362 }
8363 }
8364
8365 #undef FLD
8366 }
8367   NEXT (vpc);
8368
8369   CASE (sem, INSN_SUBU_M_B_M) : /* subu-m.b [${Rs}${inc}],$Rd */
8370 {
8371   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8372   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8373 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
8374   int UNUSED written = 0;
8375   IADDR UNUSED pc = abuf->addr;
8376   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8377
8378 {
8379   SI tmp_tmpopd;
8380   SI tmp_tmpops;
8381   BI tmp_carry;
8382   SI tmp_newval;
8383   tmp_tmpops = ZEXTQISI (({   SI tmp_addr;
8384   QI tmp_tmp_mem;
8385   BI tmp_postinc;
8386   tmp_postinc = FLD (f_memmode);
8387 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
8388 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
8389 ; if (NEBI (tmp_postinc, 0)) {
8390 {
8391 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8392   tmp_addr = ADDSI (tmp_addr, 1);
8393 }
8394   {
8395     SI opval = tmp_addr;
8396     SET_H_GR (FLD (f_operand1), opval);
8397     written |= (1 << 11);
8398     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8399   }
8400 }
8401 }
8402 ; tmp_tmp_mem; }));
8403   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8404   tmp_carry = CPU (h_cbit);
8405   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8406   {
8407     SI opval = tmp_newval;
8408     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
8409     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8410   }
8411 {
8412   {
8413     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8414     CPU (h_cbit) = opval;
8415     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8416   }
8417   {
8418     BI opval = LTSI (tmp_newval, 0);
8419     CPU (h_nbit) = opval;
8420     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8421   }
8422   {
8423     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8424     CPU (h_zbit) = opval;
8425     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8426   }
8427   {
8428     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8429     CPU (h_vbit) = opval;
8430     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8431   }
8432 {
8433   {
8434     BI opval = 0;
8435     CPU (h_xbit) = opval;
8436     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8437   }
8438   {
8439     BI opval = 0;
8440     SET_H_INSN_PREFIXED_P (opval);
8441     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8442   }
8443 }
8444 }
8445 }
8446
8447   abuf->written = written;
8448 #undef FLD
8449 }
8450   NEXT (vpc);
8451
8452   CASE (sem, INSN_SUBU_M_W_M) : /* subu-m.w [${Rs}${inc}],$Rd */
8453 {
8454   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8455   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8456 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
8457   int UNUSED written = 0;
8458   IADDR UNUSED pc = abuf->addr;
8459   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8460
8461 {
8462   SI tmp_tmpopd;
8463   SI tmp_tmpops;
8464   BI tmp_carry;
8465   SI tmp_newval;
8466   tmp_tmpops = ZEXTHISI (({   SI tmp_addr;
8467   HI tmp_tmp_mem;
8468   BI tmp_postinc;
8469   tmp_postinc = FLD (f_memmode);
8470 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
8471 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
8472 ; if (NEBI (tmp_postinc, 0)) {
8473 {
8474 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8475   tmp_addr = ADDSI (tmp_addr, 2);
8476 }
8477   {
8478     SI opval = tmp_addr;
8479     SET_H_GR (FLD (f_operand1), opval);
8480     written |= (1 << 11);
8481     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8482   }
8483 }
8484 }
8485 ; tmp_tmp_mem; }));
8486   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8487   tmp_carry = CPU (h_cbit);
8488   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8489   {
8490     SI opval = tmp_newval;
8491     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
8492     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8493   }
8494 {
8495   {
8496     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8497     CPU (h_cbit) = opval;
8498     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8499   }
8500   {
8501     BI opval = LTSI (tmp_newval, 0);
8502     CPU (h_nbit) = opval;
8503     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8504   }
8505   {
8506     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8507     CPU (h_zbit) = opval;
8508     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8509   }
8510   {
8511     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8512     CPU (h_vbit) = opval;
8513     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8514   }
8515 {
8516   {
8517     BI opval = 0;
8518     CPU (h_xbit) = opval;
8519     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8520   }
8521   {
8522     BI opval = 0;
8523     SET_H_INSN_PREFIXED_P (opval);
8524     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8525   }
8526 }
8527 }
8528 }
8529
8530   abuf->written = written;
8531 #undef FLD
8532 }
8533   NEXT (vpc);
8534
8535   CASE (sem, INSN_SUBUCBR) : /* [${Rs}${inc}],$Rd */
8536 {
8537   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8538   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8539 #define FLD(f) abuf->fields.sfmt_addcbr.f
8540   int UNUSED written = 0;
8541   IADDR UNUSED pc = abuf->addr;
8542   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
8543
8544 {
8545   SI tmp_tmpopd;
8546   SI tmp_tmpops;
8547   BI tmp_carry;
8548   SI tmp_newval;
8549   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
8550   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8551   tmp_carry = CPU (h_cbit);
8552   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8553   {
8554     SI opval = tmp_newval;
8555     SET_H_GR (FLD (f_operand2), opval);
8556     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8557   }
8558 {
8559   {
8560     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8561     CPU (h_cbit) = opval;
8562     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8563   }
8564   {
8565     BI opval = LTSI (tmp_newval, 0);
8566     CPU (h_nbit) = opval;
8567     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8568   }
8569   {
8570     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8571     CPU (h_zbit) = opval;
8572     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8573   }
8574   {
8575     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8576     CPU (h_vbit) = opval;
8577     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8578   }
8579 {
8580   {
8581     BI opval = 0;
8582     CPU (h_xbit) = opval;
8583     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8584   }
8585   {
8586     BI opval = 0;
8587     SET_H_INSN_PREFIXED_P (opval);
8588     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8589   }
8590 }
8591 }
8592 }
8593
8594 #undef FLD
8595 }
8596   NEXT (vpc);
8597
8598   CASE (sem, INSN_SUBUCWR) : /* [${Rs}${inc}],$Rd */
8599 {
8600   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8601   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8602 #define FLD(f) abuf->fields.sfmt_addcwr.f
8603   int UNUSED written = 0;
8604   IADDR UNUSED pc = abuf->addr;
8605   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
8606
8607 {
8608   SI tmp_tmpopd;
8609   SI tmp_tmpops;
8610   BI tmp_carry;
8611   SI tmp_newval;
8612   tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
8613   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8614   tmp_carry = CPU (h_cbit);
8615   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8616   {
8617     SI opval = tmp_newval;
8618     SET_H_GR (FLD (f_operand2), opval);
8619     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8620   }
8621 {
8622   {
8623     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8624     CPU (h_cbit) = opval;
8625     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8626   }
8627   {
8628     BI opval = LTSI (tmp_newval, 0);
8629     CPU (h_nbit) = opval;
8630     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8631   }
8632   {
8633     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8634     CPU (h_zbit) = opval;
8635     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8636   }
8637   {
8638     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8639     CPU (h_vbit) = opval;
8640     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8641   }
8642 {
8643   {
8644     BI opval = 0;
8645     CPU (h_xbit) = opval;
8646     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8647   }
8648   {
8649     BI opval = 0;
8650     SET_H_INSN_PREFIXED_P (opval);
8651     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8652   }
8653 }
8654 }
8655 }
8656
8657 #undef FLD
8658 }
8659   NEXT (vpc);
8660
8661   CASE (sem, INSN_ADDI_B_R) : /* addi.b ${Rs-dfield}.m,${Rd-sfield} */
8662 {
8663   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8664   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8665 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
8666   int UNUSED written = 0;
8667   IADDR UNUSED pc = abuf->addr;
8668   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8669
8670 {
8671   {
8672     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 1));
8673     SET_H_GR (FLD (f_operand1), opval);
8674     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8675   }
8676 {
8677   {
8678     BI opval = 0;
8679     CPU (h_xbit) = opval;
8680     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8681   }
8682   {
8683     BI opval = 0;
8684     SET_H_INSN_PREFIXED_P (opval);
8685     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8686   }
8687 }
8688 }
8689
8690 #undef FLD
8691 }
8692   NEXT (vpc);
8693
8694   CASE (sem, INSN_ADDI_W_R) : /* addi.w ${Rs-dfield}.m,${Rd-sfield} */
8695 {
8696   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8697   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8698 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
8699   int UNUSED written = 0;
8700   IADDR UNUSED pc = abuf->addr;
8701   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8702
8703 {
8704   {
8705     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 2));
8706     SET_H_GR (FLD (f_operand1), opval);
8707     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8708   }
8709 {
8710   {
8711     BI opval = 0;
8712     CPU (h_xbit) = opval;
8713     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8714   }
8715   {
8716     BI opval = 0;
8717     SET_H_INSN_PREFIXED_P (opval);
8718     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8719   }
8720 }
8721 }
8722
8723 #undef FLD
8724 }
8725   NEXT (vpc);
8726
8727   CASE (sem, INSN_ADDI_D_R) : /* addi.d ${Rs-dfield}.m,${Rd-sfield} */
8728 {
8729   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8730   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8731 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
8732   int UNUSED written = 0;
8733   IADDR UNUSED pc = abuf->addr;
8734   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8735
8736 {
8737   {
8738     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 4));
8739     SET_H_GR (FLD (f_operand1), opval);
8740     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8741   }
8742 {
8743   {
8744     BI opval = 0;
8745     CPU (h_xbit) = opval;
8746     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8747   }
8748   {
8749     BI opval = 0;
8750     SET_H_INSN_PREFIXED_P (opval);
8751     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8752   }
8753 }
8754 }
8755
8756 #undef FLD
8757 }
8758   NEXT (vpc);
8759
8760   CASE (sem, INSN_NEG_B_R) : /* neg.b $Rs,$Rd */
8761 {
8762   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8763   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8764 #define FLD(f) abuf->fields.sfmt_add_b_r.f
8765   int UNUSED written = 0;
8766   IADDR UNUSED pc = abuf->addr;
8767   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8768
8769 {
8770   QI tmp_tmpopd;
8771   QI tmp_tmpops;
8772   BI tmp_carry;
8773   QI tmp_newval;
8774   tmp_tmpops = GET_H_GR (FLD (f_operand1));
8775   tmp_tmpopd = 0;
8776   tmp_carry = CPU (h_cbit);
8777   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8778 {
8779   SI tmp_oldregval;
8780   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
8781   {
8782     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
8783     SET_H_GR (FLD (f_operand2), opval);
8784     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8785   }
8786 }
8787 {
8788   {
8789     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
8790     CPU (h_cbit) = opval;
8791     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8792   }
8793   {
8794     BI opval = LTQI (tmp_newval, 0);
8795     CPU (h_nbit) = opval;
8796     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8797   }
8798   {
8799     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8800     CPU (h_zbit) = opval;
8801     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8802   }
8803   {
8804     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
8805     CPU (h_vbit) = opval;
8806     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8807   }
8808 {
8809   {
8810     BI opval = 0;
8811     CPU (h_xbit) = opval;
8812     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8813   }
8814   {
8815     BI opval = 0;
8816     SET_H_INSN_PREFIXED_P (opval);
8817     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8818   }
8819 }
8820 }
8821 }
8822
8823 #undef FLD
8824 }
8825   NEXT (vpc);
8826
8827   CASE (sem, INSN_NEG_W_R) : /* neg.w $Rs,$Rd */
8828 {
8829   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8830   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8831 #define FLD(f) abuf->fields.sfmt_add_b_r.f
8832   int UNUSED written = 0;
8833   IADDR UNUSED pc = abuf->addr;
8834   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8835
8836 {
8837   HI tmp_tmpopd;
8838   HI tmp_tmpops;
8839   BI tmp_carry;
8840   HI tmp_newval;
8841   tmp_tmpops = GET_H_GR (FLD (f_operand1));
8842   tmp_tmpopd = 0;
8843   tmp_carry = CPU (h_cbit);
8844   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8845 {
8846   SI tmp_oldregval;
8847   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
8848   {
8849     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
8850     SET_H_GR (FLD (f_operand2), opval);
8851     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8852   }
8853 }
8854 {
8855   {
8856     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
8857     CPU (h_cbit) = opval;
8858     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8859   }
8860   {
8861     BI opval = LTHI (tmp_newval, 0);
8862     CPU (h_nbit) = opval;
8863     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8864   }
8865   {
8866     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8867     CPU (h_zbit) = opval;
8868     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8869   }
8870   {
8871     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
8872     CPU (h_vbit) = opval;
8873     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8874   }
8875 {
8876   {
8877     BI opval = 0;
8878     CPU (h_xbit) = opval;
8879     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8880   }
8881   {
8882     BI opval = 0;
8883     SET_H_INSN_PREFIXED_P (opval);
8884     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8885   }
8886 }
8887 }
8888 }
8889
8890 #undef FLD
8891 }
8892   NEXT (vpc);
8893
8894   CASE (sem, INSN_NEG_D_R) : /* neg.d $Rs,$Rd */
8895 {
8896   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8897   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8898 #define FLD(f) abuf->fields.sfmt_add_b_r.f
8899   int UNUSED written = 0;
8900   IADDR UNUSED pc = abuf->addr;
8901   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8902
8903 {
8904   SI tmp_tmpopd;
8905   SI tmp_tmpops;
8906   BI tmp_carry;
8907   SI tmp_newval;
8908   tmp_tmpops = GET_H_GR (FLD (f_operand1));
8909   tmp_tmpopd = 0;
8910   tmp_carry = CPU (h_cbit);
8911   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8912   {
8913     SI opval = tmp_newval;
8914     SET_H_GR (FLD (f_operand2), opval);
8915     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8916   }
8917 {
8918   {
8919     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8920     CPU (h_cbit) = opval;
8921     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8922   }
8923   {
8924     BI opval = LTSI (tmp_newval, 0);
8925     CPU (h_nbit) = opval;
8926     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8927   }
8928   {
8929     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8930     CPU (h_zbit) = opval;
8931     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8932   }
8933   {
8934     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8935     CPU (h_vbit) = opval;
8936     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8937   }
8938 {
8939   {
8940     BI opval = 0;
8941     CPU (h_xbit) = opval;
8942     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8943   }
8944   {
8945     BI opval = 0;
8946     SET_H_INSN_PREFIXED_P (opval);
8947     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8948   }
8949 }
8950 }
8951 }
8952
8953 #undef FLD
8954 }
8955   NEXT (vpc);
8956
8957   CASE (sem, INSN_TEST_M_B_M) : /* test-m.b [${Rs}${inc}] */
8958 {
8959   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8960   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8961 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
8962   int UNUSED written = 0;
8963   IADDR UNUSED pc = abuf->addr;
8964   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8965
8966 {
8967   QI tmp_tmpd;
8968   tmp_tmpd = ({   SI tmp_addr;
8969   QI tmp_tmp_mem;
8970   BI tmp_postinc;
8971   tmp_postinc = FLD (f_memmode);
8972 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
8973 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
8974 ; if (NEBI (tmp_postinc, 0)) {
8975 {
8976 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8977   tmp_addr = ADDSI (tmp_addr, 1);
8978 }
8979   {
8980     SI opval = tmp_addr;
8981     SET_H_GR (FLD (f_operand1), opval);
8982     written |= (1 << 8);
8983     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8984   }
8985 }
8986 }
8987 ; tmp_tmp_mem; });
8988 {
8989   QI tmp_tmpopd;
8990   QI tmp_tmpops;
8991   BI tmp_carry;
8992   QI tmp_newval;
8993   tmp_tmpops = 0;
8994   tmp_tmpopd = tmp_tmpd;
8995   tmp_carry = CPU (h_cbit);
8996   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8997 ((void) 0); /*nop*/
8998 {
8999   {
9000     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
9001     CPU (h_cbit) = opval;
9002     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9003   }
9004   {
9005     BI opval = LTQI (tmp_newval, 0);
9006     CPU (h_nbit) = opval;
9007     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9008   }
9009   {
9010     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9011     CPU (h_zbit) = opval;
9012     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9013   }
9014   {
9015     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
9016     CPU (h_vbit) = opval;
9017     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9018   }
9019 {
9020   {
9021     BI opval = 0;
9022     CPU (h_xbit) = opval;
9023     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9024   }
9025   {
9026     BI opval = 0;
9027     SET_H_INSN_PREFIXED_P (opval);
9028     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9029   }
9030 }
9031 }
9032 }
9033 }
9034
9035   abuf->written = written;
9036 #undef FLD
9037 }
9038   NEXT (vpc);
9039
9040   CASE (sem, INSN_TEST_M_W_M) : /* test-m.w [${Rs}${inc}] */
9041 {
9042   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9043   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9044 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
9045   int UNUSED written = 0;
9046   IADDR UNUSED pc = abuf->addr;
9047   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9048
9049 {
9050   HI tmp_tmpd;
9051   tmp_tmpd = ({   SI tmp_addr;
9052   HI tmp_tmp_mem;
9053   BI tmp_postinc;
9054   tmp_postinc = FLD (f_memmode);
9055 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
9056 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
9057 ; if (NEBI (tmp_postinc, 0)) {
9058 {
9059 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9060   tmp_addr = ADDSI (tmp_addr, 2);
9061 }
9062   {
9063     SI opval = tmp_addr;
9064     SET_H_GR (FLD (f_operand1), opval);
9065     written |= (1 << 8);
9066     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9067   }
9068 }
9069 }
9070 ; tmp_tmp_mem; });
9071 {
9072   HI tmp_tmpopd;
9073   HI tmp_tmpops;
9074   BI tmp_carry;
9075   HI tmp_newval;
9076   tmp_tmpops = 0;
9077   tmp_tmpopd = tmp_tmpd;
9078   tmp_carry = CPU (h_cbit);
9079   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
9080 ((void) 0); /*nop*/
9081 {
9082   {
9083     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
9084     CPU (h_cbit) = opval;
9085     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9086   }
9087   {
9088     BI opval = LTHI (tmp_newval, 0);
9089     CPU (h_nbit) = opval;
9090     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9091   }
9092   {
9093     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9094     CPU (h_zbit) = opval;
9095     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9096   }
9097   {
9098     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
9099     CPU (h_vbit) = opval;
9100     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9101   }
9102 {
9103   {
9104     BI opval = 0;
9105     CPU (h_xbit) = opval;
9106     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9107   }
9108   {
9109     BI opval = 0;
9110     SET_H_INSN_PREFIXED_P (opval);
9111     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9112   }
9113 }
9114 }
9115 }
9116 }
9117
9118   abuf->written = written;
9119 #undef FLD
9120 }
9121   NEXT (vpc);
9122
9123   CASE (sem, INSN_TEST_M_D_M) : /* test-m.d [${Rs}${inc}] */
9124 {
9125   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9126   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9127 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
9128   int UNUSED written = 0;
9129   IADDR UNUSED pc = abuf->addr;
9130   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9131
9132 {
9133   SI tmp_tmpd;
9134   tmp_tmpd = ({   SI tmp_addr;
9135   SI tmp_tmp_mem;
9136   BI tmp_postinc;
9137   tmp_postinc = FLD (f_memmode);
9138 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
9139 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
9140 ; if (NEBI (tmp_postinc, 0)) {
9141 {
9142 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9143   tmp_addr = ADDSI (tmp_addr, 4);
9144 }
9145   {
9146     SI opval = tmp_addr;
9147     SET_H_GR (FLD (f_operand1), opval);
9148     written |= (1 << 8);
9149     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9150   }
9151 }
9152 }
9153 ; tmp_tmp_mem; });
9154 {
9155   SI tmp_tmpopd;
9156   SI tmp_tmpops;
9157   BI tmp_carry;
9158   SI tmp_newval;
9159   tmp_tmpops = 0;
9160   tmp_tmpopd = tmp_tmpd;
9161   tmp_carry = CPU (h_cbit);
9162   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
9163 ((void) 0); /*nop*/
9164 {
9165   {
9166     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
9167     CPU (h_cbit) = opval;
9168     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9169   }
9170   {
9171     BI opval = LTSI (tmp_newval, 0);
9172     CPU (h_nbit) = opval;
9173     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9174   }
9175   {
9176     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9177     CPU (h_zbit) = opval;
9178     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9179   }
9180   {
9181     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
9182     CPU (h_vbit) = opval;
9183     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9184   }
9185 {
9186   {
9187     BI opval = 0;
9188     CPU (h_xbit) = opval;
9189     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9190   }
9191   {
9192     BI opval = 0;
9193     SET_H_INSN_PREFIXED_P (opval);
9194     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9195   }
9196 }
9197 }
9198 }
9199 }
9200
9201   abuf->written = written;
9202 #undef FLD
9203 }
9204   NEXT (vpc);
9205
9206   CASE (sem, INSN_MOVE_R_M_B_M) : /* move-r-m.b ${Rs-dfield},[${Rd-sfield}${inc}] */
9207 {
9208   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9209   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9210 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
9211   int UNUSED written = 0;
9212   IADDR UNUSED pc = abuf->addr;
9213   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9214
9215 {
9216   QI tmp_tmpd;
9217   tmp_tmpd = GET_H_GR (FLD (f_operand2));
9218 {
9219   SI tmp_addr;
9220   BI tmp_postinc;
9221   tmp_postinc = FLD (f_memmode);
9222   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
9223 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
9224 if (EQBI (CPU (h_pbit), 0)) {
9225 {
9226   {
9227     QI opval = tmp_tmpd;
9228     SETMEMQI (current_cpu, pc, tmp_addr, opval);
9229     written |= (1 << 10);
9230     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9231   }
9232   {
9233     BI opval = CPU (h_pbit);
9234     CPU (h_cbit) = opval;
9235     written |= (1 << 9);
9236     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9237   }
9238 }
9239 } else {
9240   {
9241     BI opval = 1;
9242     CPU (h_cbit) = opval;
9243     written |= (1 << 9);
9244     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9245   }
9246 }
9247 } else {
9248   {
9249     QI opval = tmp_tmpd;
9250     SETMEMQI (current_cpu, pc, tmp_addr, opval);
9251     written |= (1 << 10);
9252     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9253   }
9254 }
9255 if (NEBI (tmp_postinc, 0)) {
9256 {
9257 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9258   tmp_addr = ADDSI (tmp_addr, 1);
9259 }
9260   {
9261     SI opval = tmp_addr;
9262     SET_H_GR (FLD (f_operand1), opval);
9263     written |= (1 << 8);
9264     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9265   }
9266 }
9267 }
9268 }
9269 {
9270   {
9271     BI opval = 0;
9272     CPU (h_xbit) = opval;
9273     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9274   }
9275   {
9276     BI opval = 0;
9277     SET_H_INSN_PREFIXED_P (opval);
9278     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9279   }
9280 }
9281 }
9282
9283   abuf->written = written;
9284 #undef FLD
9285 }
9286   NEXT (vpc);
9287
9288   CASE (sem, INSN_MOVE_R_M_W_M) : /* move-r-m.w ${Rs-dfield},[${Rd-sfield}${inc}] */
9289 {
9290   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9291   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9292 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
9293   int UNUSED written = 0;
9294   IADDR UNUSED pc = abuf->addr;
9295   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9296
9297 {
9298   HI tmp_tmpd;
9299   tmp_tmpd = GET_H_GR (FLD (f_operand2));
9300 {
9301   SI tmp_addr;
9302   BI tmp_postinc;
9303   tmp_postinc = FLD (f_memmode);
9304   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
9305 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
9306 if (EQBI (CPU (h_pbit), 0)) {
9307 {
9308   {
9309     HI opval = tmp_tmpd;
9310     SETMEMHI (current_cpu, pc, tmp_addr, opval);
9311     written |= (1 << 10);
9312     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9313   }
9314   {
9315     BI opval = CPU (h_pbit);
9316     CPU (h_cbit) = opval;
9317     written |= (1 << 9);
9318     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9319   }
9320 }
9321 } else {
9322   {
9323     BI opval = 1;
9324     CPU (h_cbit) = opval;
9325     written |= (1 << 9);
9326     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9327   }
9328 }
9329 } else {
9330   {
9331     HI opval = tmp_tmpd;
9332     SETMEMHI (current_cpu, pc, tmp_addr, opval);
9333     written |= (1 << 10);
9334     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9335   }
9336 }
9337 if (NEBI (tmp_postinc, 0)) {
9338 {
9339 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9340   tmp_addr = ADDSI (tmp_addr, 2);
9341 }
9342   {
9343     SI opval = tmp_addr;
9344     SET_H_GR (FLD (f_operand1), opval);
9345     written |= (1 << 8);
9346     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9347   }
9348 }
9349 }
9350 }
9351 {
9352   {
9353     BI opval = 0;
9354     CPU (h_xbit) = opval;
9355     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9356   }
9357   {
9358     BI opval = 0;
9359     SET_H_INSN_PREFIXED_P (opval);
9360     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9361   }
9362 }
9363 }
9364
9365   abuf->written = written;
9366 #undef FLD
9367 }
9368   NEXT (vpc);
9369
9370   CASE (sem, INSN_MOVE_R_M_D_M) : /* move-r-m.d ${Rs-dfield},[${Rd-sfield}${inc}] */
9371 {
9372   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9373   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9374 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
9375   int UNUSED written = 0;
9376   IADDR UNUSED pc = abuf->addr;
9377   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9378
9379 {
9380   SI tmp_tmpd;
9381   tmp_tmpd = GET_H_GR (FLD (f_operand2));
9382 {
9383   SI tmp_addr;
9384   BI tmp_postinc;
9385   tmp_postinc = FLD (f_memmode);
9386   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
9387 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
9388 if (EQBI (CPU (h_pbit), 0)) {
9389 {
9390   {
9391     SI opval = tmp_tmpd;
9392     SETMEMSI (current_cpu, pc, tmp_addr, opval);
9393     written |= (1 << 10);
9394     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9395   }
9396   {
9397     BI opval = CPU (h_pbit);
9398     CPU (h_cbit) = opval;
9399     written |= (1 << 9);
9400     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9401   }
9402 }
9403 } else {
9404   {
9405     BI opval = 1;
9406     CPU (h_cbit) = opval;
9407     written |= (1 << 9);
9408     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9409   }
9410 }
9411 } else {
9412   {
9413     SI opval = tmp_tmpd;
9414     SETMEMSI (current_cpu, pc, tmp_addr, opval);
9415     written |= (1 << 10);
9416     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9417   }
9418 }
9419 if (NEBI (tmp_postinc, 0)) {
9420 {
9421 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9422   tmp_addr = ADDSI (tmp_addr, 4);
9423 }
9424   {
9425     SI opval = tmp_addr;
9426     SET_H_GR (FLD (f_operand1), opval);
9427     written |= (1 << 8);
9428     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9429   }
9430 }
9431 }
9432 }
9433 {
9434   {
9435     BI opval = 0;
9436     CPU (h_xbit) = opval;
9437     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9438   }
9439   {
9440     BI opval = 0;
9441     SET_H_INSN_PREFIXED_P (opval);
9442     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9443   }
9444 }
9445 }
9446
9447   abuf->written = written;
9448 #undef FLD
9449 }
9450   NEXT (vpc);
9451
9452   CASE (sem, INSN_MULS_B) : /* muls.b $Rs,$Rd */
9453 {
9454   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9455   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9456 #define FLD(f) abuf->fields.sfmt_muls_b.f
9457   int UNUSED written = 0;
9458   IADDR UNUSED pc = abuf->addr;
9459   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9460
9461 {
9462   DI tmp_src1;
9463   DI tmp_src2;
9464   DI tmp_tmpr;
9465   tmp_src1 = EXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
9466   tmp_src2 = EXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand2))));
9467   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9468   {
9469     SI opval = TRUNCDISI (tmp_tmpr);
9470     SET_H_GR (FLD (f_operand2), opval);
9471     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9472   }
9473   {
9474     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9475     SET_H_SR (((UINT) 7), opval);
9476     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9477   }
9478 {
9479   {
9480     BI opval = ANDIF (GET_H_V32_NON_V32 (), CPU (h_cbit));
9481     CPU (h_cbit) = opval;
9482     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9483   }
9484   {
9485     BI opval = LTDI (tmp_tmpr, 0);
9486     CPU (h_nbit) = opval;
9487     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9488   }
9489   {
9490     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9491     CPU (h_zbit) = opval;
9492     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9493   }
9494   {
9495     BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
9496     CPU (h_vbit) = opval;
9497     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9498   }
9499 {
9500   {
9501     BI opval = 0;
9502     CPU (h_xbit) = opval;
9503     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9504   }
9505   {
9506     BI opval = 0;
9507     SET_H_INSN_PREFIXED_P (opval);
9508     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9509   }
9510 }
9511 }
9512 }
9513
9514 #undef FLD
9515 }
9516   NEXT (vpc);
9517
9518   CASE (sem, INSN_MULS_W) : /* muls.w $Rs,$Rd */
9519 {
9520   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9521   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9522 #define FLD(f) abuf->fields.sfmt_muls_b.f
9523   int UNUSED written = 0;
9524   IADDR UNUSED pc = abuf->addr;
9525   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9526
9527 {
9528   DI tmp_src1;
9529   DI tmp_src2;
9530   DI tmp_tmpr;
9531   tmp_src1 = EXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
9532   tmp_src2 = EXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand2))));
9533   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9534   {
9535     SI opval = TRUNCDISI (tmp_tmpr);
9536     SET_H_GR (FLD (f_operand2), opval);
9537     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9538   }
9539   {
9540     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9541     SET_H_SR (((UINT) 7), opval);
9542     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9543   }
9544 {
9545   {
9546     BI opval = ANDIF (GET_H_V32_NON_V32 (), CPU (h_cbit));
9547     CPU (h_cbit) = opval;
9548     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9549   }
9550   {
9551     BI opval = LTDI (tmp_tmpr, 0);
9552     CPU (h_nbit) = opval;
9553     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9554   }
9555   {
9556     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9557     CPU (h_zbit) = opval;
9558     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9559   }
9560   {
9561     BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
9562     CPU (h_vbit) = opval;
9563     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9564   }
9565 {
9566   {
9567     BI opval = 0;
9568     CPU (h_xbit) = opval;
9569     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9570   }
9571   {
9572     BI opval = 0;
9573     SET_H_INSN_PREFIXED_P (opval);
9574     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9575   }
9576 }
9577 }
9578 }
9579
9580 #undef FLD
9581 }
9582   NEXT (vpc);
9583
9584   CASE (sem, INSN_MULS_D) : /* muls.d $Rs,$Rd */
9585 {
9586   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9587   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9588 #define FLD(f) abuf->fields.sfmt_muls_b.f
9589   int UNUSED written = 0;
9590   IADDR UNUSED pc = abuf->addr;
9591   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9592
9593 {
9594   DI tmp_src1;
9595   DI tmp_src2;
9596   DI tmp_tmpr;
9597   tmp_src1 = EXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand1))));
9598   tmp_src2 = EXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand2))));
9599   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9600   {
9601     SI opval = TRUNCDISI (tmp_tmpr);
9602     SET_H_GR (FLD (f_operand2), opval);
9603     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9604   }
9605   {
9606     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9607     SET_H_SR (((UINT) 7), opval);
9608     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9609   }
9610 {
9611   {
9612     BI opval = ANDIF (GET_H_V32_NON_V32 (), CPU (h_cbit));
9613     CPU (h_cbit) = opval;
9614     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9615   }
9616   {
9617     BI opval = LTDI (tmp_tmpr, 0);
9618     CPU (h_nbit) = opval;
9619     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9620   }
9621   {
9622     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9623     CPU (h_zbit) = opval;
9624     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9625   }
9626   {
9627     BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
9628     CPU (h_vbit) = opval;
9629     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9630   }
9631 {
9632   {
9633     BI opval = 0;
9634     CPU (h_xbit) = opval;
9635     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9636   }
9637   {
9638     BI opval = 0;
9639     SET_H_INSN_PREFIXED_P (opval);
9640     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9641   }
9642 }
9643 }
9644 }
9645
9646 #undef FLD
9647 }
9648   NEXT (vpc);
9649
9650   CASE (sem, INSN_MULU_B) : /* mulu.b $Rs,$Rd */
9651 {
9652   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9653   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9654 #define FLD(f) abuf->fields.sfmt_muls_b.f
9655   int UNUSED written = 0;
9656   IADDR UNUSED pc = abuf->addr;
9657   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9658
9659 {
9660   DI tmp_src1;
9661   DI tmp_src2;
9662   DI tmp_tmpr;
9663   tmp_src1 = ZEXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
9664   tmp_src2 = ZEXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand2))));
9665   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9666   {
9667     SI opval = TRUNCDISI (tmp_tmpr);
9668     SET_H_GR (FLD (f_operand2), opval);
9669     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9670   }
9671   {
9672     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9673     SET_H_SR (((UINT) 7), opval);
9674     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9675   }
9676 {
9677   {
9678     BI opval = ANDIF (GET_H_V32_NON_V32 (), CPU (h_cbit));
9679     CPU (h_cbit) = opval;
9680     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9681   }
9682   {
9683     BI opval = LTDI (tmp_tmpr, 0);
9684     CPU (h_nbit) = opval;
9685     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9686   }
9687   {
9688     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9689     CPU (h_zbit) = opval;
9690     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9691   }
9692   {
9693     BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
9694     CPU (h_vbit) = opval;
9695     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9696   }
9697 {
9698   {
9699     BI opval = 0;
9700     CPU (h_xbit) = opval;
9701     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9702   }
9703   {
9704     BI opval = 0;
9705     SET_H_INSN_PREFIXED_P (opval);
9706     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9707   }
9708 }
9709 }
9710 }
9711
9712 #undef FLD
9713 }
9714   NEXT (vpc);
9715
9716   CASE (sem, INSN_MULU_W) : /* mulu.w $Rs,$Rd */
9717 {
9718   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9719   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9720 #define FLD(f) abuf->fields.sfmt_muls_b.f
9721   int UNUSED written = 0;
9722   IADDR UNUSED pc = abuf->addr;
9723   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9724
9725 {
9726   DI tmp_src1;
9727   DI tmp_src2;
9728   DI tmp_tmpr;
9729   tmp_src1 = ZEXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
9730   tmp_src2 = ZEXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand2))));
9731   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9732   {
9733     SI opval = TRUNCDISI (tmp_tmpr);
9734     SET_H_GR (FLD (f_operand2), opval);
9735     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9736   }
9737   {
9738     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9739     SET_H_SR (((UINT) 7), opval);
9740     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9741   }
9742 {
9743   {
9744     BI opval = ANDIF (GET_H_V32_NON_V32 (), CPU (h_cbit));
9745     CPU (h_cbit) = opval;
9746     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9747   }
9748   {
9749     BI opval = LTDI (tmp_tmpr, 0);
9750     CPU (h_nbit) = opval;
9751     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9752   }
9753   {
9754     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9755     CPU (h_zbit) = opval;
9756     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9757   }
9758   {
9759     BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
9760     CPU (h_vbit) = opval;
9761     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9762   }
9763 {
9764   {
9765     BI opval = 0;
9766     CPU (h_xbit) = opval;
9767     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9768   }
9769   {
9770     BI opval = 0;
9771     SET_H_INSN_PREFIXED_P (opval);
9772     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9773   }
9774 }
9775 }
9776 }
9777
9778 #undef FLD
9779 }
9780   NEXT (vpc);
9781
9782   CASE (sem, INSN_MULU_D) : /* mulu.d $Rs,$Rd */
9783 {
9784   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9785   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9786 #define FLD(f) abuf->fields.sfmt_muls_b.f
9787   int UNUSED written = 0;
9788   IADDR UNUSED pc = abuf->addr;
9789   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9790
9791 {
9792   DI tmp_src1;
9793   DI tmp_src2;
9794   DI tmp_tmpr;
9795   tmp_src1 = ZEXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand1))));
9796   tmp_src2 = ZEXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand2))));
9797   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9798   {
9799     SI opval = TRUNCDISI (tmp_tmpr);
9800     SET_H_GR (FLD (f_operand2), opval);
9801     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9802   }
9803   {
9804     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9805     SET_H_SR (((UINT) 7), opval);
9806     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9807   }
9808 {
9809   {
9810     BI opval = ANDIF (GET_H_V32_NON_V32 (), CPU (h_cbit));
9811     CPU (h_cbit) = opval;
9812     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9813   }
9814   {
9815     BI opval = LTDI (tmp_tmpr, 0);
9816     CPU (h_nbit) = opval;
9817     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9818   }
9819   {
9820     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9821     CPU (h_zbit) = opval;
9822     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9823   }
9824   {
9825     BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
9826     CPU (h_vbit) = opval;
9827     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9828   }
9829 {
9830   {
9831     BI opval = 0;
9832     CPU (h_xbit) = opval;
9833     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9834   }
9835   {
9836     BI opval = 0;
9837     SET_H_INSN_PREFIXED_P (opval);
9838     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9839   }
9840 }
9841 }
9842 }
9843
9844 #undef FLD
9845 }
9846   NEXT (vpc);
9847
9848   CASE (sem, INSN_MSTEP) : /* mstep $Rs,$Rd */
9849 {
9850   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9851   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9852 #define FLD(f) abuf->fields.sfmt_muls_b.f
9853   int UNUSED written = 0;
9854   IADDR UNUSED pc = abuf->addr;
9855   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9856
9857 {
9858   SI tmp_tmpd;
9859   SI tmp_tmps;
9860   tmp_tmps = GET_H_GR (FLD (f_operand1));
9861   tmp_tmpd = ADDSI (SLLSI (GET_H_GR (FLD (f_operand2)), 1), ((CPU (h_nbit)) ? (tmp_tmps) : (0)));
9862   {
9863     SI opval = tmp_tmpd;
9864     SET_H_GR (FLD (f_operand2), opval);
9865     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9866   }
9867 {
9868   {
9869     BI opval = LTSI (tmp_tmpd, 0);
9870     CPU (h_nbit) = opval;
9871     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9872   }
9873   {
9874     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
9875     CPU (h_zbit) = opval;
9876     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9877   }
9878 SET_H_CBIT_MOVE (0);
9879 SET_H_VBIT_MOVE (0);
9880 {
9881   {
9882     BI opval = 0;
9883     CPU (h_xbit) = opval;
9884     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9885   }
9886   {
9887     BI opval = 0;
9888     SET_H_INSN_PREFIXED_P (opval);
9889     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9890   }
9891 }
9892 }
9893 }
9894
9895 #undef FLD
9896 }
9897   NEXT (vpc);
9898
9899   CASE (sem, INSN_DSTEP) : /* dstep $Rs,$Rd */
9900 {
9901   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9902   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9903 #define FLD(f) abuf->fields.sfmt_muls_b.f
9904   int UNUSED written = 0;
9905   IADDR UNUSED pc = abuf->addr;
9906   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9907
9908 {
9909   SI tmp_tmp;
9910   SI tmp_tmps;
9911   SI tmp_tmpd;
9912   tmp_tmps = GET_H_GR (FLD (f_operand1));
9913   tmp_tmp = SLLSI (GET_H_GR (FLD (f_operand2)), 1);
9914   tmp_tmpd = ((GEUSI (tmp_tmp, tmp_tmps)) ? (SUBSI (tmp_tmp, tmp_tmps)) : (tmp_tmp));
9915   {
9916     SI opval = tmp_tmpd;
9917     SET_H_GR (FLD (f_operand2), opval);
9918     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9919   }
9920 {
9921   {
9922     BI opval = LTSI (tmp_tmpd, 0);
9923     CPU (h_nbit) = opval;
9924     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9925   }
9926   {
9927     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
9928     CPU (h_zbit) = opval;
9929     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9930   }
9931 SET_H_CBIT_MOVE (0);
9932 SET_H_VBIT_MOVE (0);
9933 {
9934   {
9935     BI opval = 0;
9936     CPU (h_xbit) = opval;
9937     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9938   }
9939   {
9940     BI opval = 0;
9941     SET_H_INSN_PREFIXED_P (opval);
9942     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9943   }
9944 }
9945 }
9946 }
9947
9948 #undef FLD
9949 }
9950   NEXT (vpc);
9951
9952   CASE (sem, INSN_ABS) : /* abs $Rs,$Rd */
9953 {
9954   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9955   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9956 #define FLD(f) abuf->fields.sfmt_muls_b.f
9957   int UNUSED written = 0;
9958   IADDR UNUSED pc = abuf->addr;
9959   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9960
9961 {
9962   SI tmp_tmpd;
9963   tmp_tmpd = ABSSI (GET_H_GR (FLD (f_operand1)));
9964   {
9965     SI opval = tmp_tmpd;
9966     SET_H_GR (FLD (f_operand2), opval);
9967     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9968   }
9969 {
9970   {
9971     BI opval = LTSI (tmp_tmpd, 0);
9972     CPU (h_nbit) = opval;
9973     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9974   }
9975   {
9976     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
9977     CPU (h_zbit) = opval;
9978     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9979   }
9980 SET_H_CBIT_MOVE (0);
9981 SET_H_VBIT_MOVE (0);
9982 {
9983   {
9984     BI opval = 0;
9985     CPU (h_xbit) = opval;
9986     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9987   }
9988   {
9989     BI opval = 0;
9990     SET_H_INSN_PREFIXED_P (opval);
9991     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9992   }
9993 }
9994 }
9995 }
9996
9997 #undef FLD
9998 }
9999   NEXT (vpc);
10000
10001   CASE (sem, INSN_AND_B_R) : /* and.b $Rs,$Rd */
10002 {
10003   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10004   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10005 #define FLD(f) abuf->fields.sfmt_add_b_r.f
10006   int UNUSED written = 0;
10007   IADDR UNUSED pc = abuf->addr;
10008   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10009
10010 {
10011   QI tmp_tmpd;
10012   tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10013 {
10014   SI tmp_oldregval;
10015   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
10016   {
10017     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10018     SET_H_GR (FLD (f_operand2), opval);
10019     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10020   }
10021 }
10022 {
10023   {
10024     BI opval = LTQI (tmp_tmpd, 0);
10025     CPU (h_nbit) = opval;
10026     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10027   }
10028   {
10029     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10030     CPU (h_zbit) = opval;
10031     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10032   }
10033 SET_H_CBIT_MOVE (0);
10034 SET_H_VBIT_MOVE (0);
10035 {
10036   {
10037     BI opval = 0;
10038     CPU (h_xbit) = opval;
10039     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10040   }
10041   {
10042     BI opval = 0;
10043     SET_H_INSN_PREFIXED_P (opval);
10044     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10045   }
10046 }
10047 }
10048 }
10049
10050 #undef FLD
10051 }
10052   NEXT (vpc);
10053
10054   CASE (sem, INSN_AND_W_R) : /* and.w $Rs,$Rd */
10055 {
10056   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10057   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10058 #define FLD(f) abuf->fields.sfmt_add_b_r.f
10059   int UNUSED written = 0;
10060   IADDR UNUSED pc = abuf->addr;
10061   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10062
10063 {
10064   HI tmp_tmpd;
10065   tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10066 {
10067   SI tmp_oldregval;
10068   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
10069   {
10070     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10071     SET_H_GR (FLD (f_operand2), opval);
10072     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10073   }
10074 }
10075 {
10076   {
10077     BI opval = LTHI (tmp_tmpd, 0);
10078     CPU (h_nbit) = opval;
10079     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10080   }
10081   {
10082     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10083     CPU (h_zbit) = opval;
10084     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10085   }
10086 SET_H_CBIT_MOVE (0);
10087 SET_H_VBIT_MOVE (0);
10088 {
10089   {
10090     BI opval = 0;
10091     CPU (h_xbit) = opval;
10092     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10093   }
10094   {
10095     BI opval = 0;
10096     SET_H_INSN_PREFIXED_P (opval);
10097     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10098   }
10099 }
10100 }
10101 }
10102
10103 #undef FLD
10104 }
10105   NEXT (vpc);
10106
10107   CASE (sem, INSN_AND_D_R) : /* and.d $Rs,$Rd */
10108 {
10109   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10110   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10111 #define FLD(f) abuf->fields.sfmt_add_b_r.f
10112   int UNUSED written = 0;
10113   IADDR UNUSED pc = abuf->addr;
10114   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10115
10116 {
10117   SI tmp_tmpd;
10118   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10119   {
10120     SI opval = tmp_tmpd;
10121     SET_H_GR (FLD (f_operand2), opval);
10122     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10123   }
10124 {
10125   {
10126     BI opval = LTSI (tmp_tmpd, 0);
10127     CPU (h_nbit) = opval;
10128     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10129   }
10130   {
10131     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10132     CPU (h_zbit) = opval;
10133     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10134   }
10135 SET_H_CBIT_MOVE (0);
10136 SET_H_VBIT_MOVE (0);
10137 {
10138   {
10139     BI opval = 0;
10140     CPU (h_xbit) = opval;
10141     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10142   }
10143   {
10144     BI opval = 0;
10145     SET_H_INSN_PREFIXED_P (opval);
10146     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10147   }
10148 }
10149 }
10150 }
10151
10152 #undef FLD
10153 }
10154   NEXT (vpc);
10155
10156   CASE (sem, INSN_AND_M_B_M) : /* and-m.b [${Rs}${inc}],${Rd} */
10157 {
10158   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10159   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10160 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10161   int UNUSED written = 0;
10162   IADDR UNUSED pc = abuf->addr;
10163   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10164
10165 {
10166   QI tmp_tmpd;
10167   tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10168   QI tmp_tmp_mem;
10169   BI tmp_postinc;
10170   tmp_postinc = FLD (f_memmode);
10171 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
10172 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
10173 ; if (NEBI (tmp_postinc, 0)) {
10174 {
10175 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10176   tmp_addr = ADDSI (tmp_addr, 1);
10177 }
10178   {
10179     SI opval = tmp_addr;
10180     SET_H_GR (FLD (f_operand1), opval);
10181     written |= (1 << 11);
10182     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10183   }
10184 }
10185 }
10186 ; tmp_tmp_mem; }));
10187 {
10188   SI tmp_oldregval;
10189   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
10190   {
10191     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10192     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10193     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10194   }
10195 }
10196 {
10197   {
10198     BI opval = LTQI (tmp_tmpd, 0);
10199     CPU (h_nbit) = opval;
10200     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10201   }
10202   {
10203     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10204     CPU (h_zbit) = opval;
10205     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10206   }
10207 SET_H_CBIT_MOVE (0);
10208 SET_H_VBIT_MOVE (0);
10209 {
10210   {
10211     BI opval = 0;
10212     CPU (h_xbit) = opval;
10213     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10214   }
10215   {
10216     BI opval = 0;
10217     SET_H_INSN_PREFIXED_P (opval);
10218     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10219   }
10220 }
10221 }
10222 }
10223
10224   abuf->written = written;
10225 #undef FLD
10226 }
10227   NEXT (vpc);
10228
10229   CASE (sem, INSN_AND_M_W_M) : /* and-m.w [${Rs}${inc}],${Rd} */
10230 {
10231   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10232   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10233 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10234   int UNUSED written = 0;
10235   IADDR UNUSED pc = abuf->addr;
10236   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10237
10238 {
10239   HI tmp_tmpd;
10240   tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10241   HI tmp_tmp_mem;
10242   BI tmp_postinc;
10243   tmp_postinc = FLD (f_memmode);
10244 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
10245 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
10246 ; if (NEBI (tmp_postinc, 0)) {
10247 {
10248 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10249   tmp_addr = ADDSI (tmp_addr, 2);
10250 }
10251   {
10252     SI opval = tmp_addr;
10253     SET_H_GR (FLD (f_operand1), opval);
10254     written |= (1 << 11);
10255     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10256   }
10257 }
10258 }
10259 ; tmp_tmp_mem; }));
10260 {
10261   SI tmp_oldregval;
10262   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
10263   {
10264     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10265     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10266     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10267   }
10268 }
10269 {
10270   {
10271     BI opval = LTHI (tmp_tmpd, 0);
10272     CPU (h_nbit) = opval;
10273     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10274   }
10275   {
10276     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10277     CPU (h_zbit) = opval;
10278     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10279   }
10280 SET_H_CBIT_MOVE (0);
10281 SET_H_VBIT_MOVE (0);
10282 {
10283   {
10284     BI opval = 0;
10285     CPU (h_xbit) = opval;
10286     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10287   }
10288   {
10289     BI opval = 0;
10290     SET_H_INSN_PREFIXED_P (opval);
10291     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10292   }
10293 }
10294 }
10295 }
10296
10297   abuf->written = written;
10298 #undef FLD
10299 }
10300   NEXT (vpc);
10301
10302   CASE (sem, INSN_AND_M_D_M) : /* and-m.d [${Rs}${inc}],${Rd} */
10303 {
10304   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10305   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10306 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10307   int UNUSED written = 0;
10308   IADDR UNUSED pc = abuf->addr;
10309   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10310
10311 {
10312   SI tmp_tmpd;
10313   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10314   SI tmp_tmp_mem;
10315   BI tmp_postinc;
10316   tmp_postinc = FLD (f_memmode);
10317 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
10318 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
10319 ; if (NEBI (tmp_postinc, 0)) {
10320 {
10321 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10322   tmp_addr = ADDSI (tmp_addr, 4);
10323 }
10324   {
10325     SI opval = tmp_addr;
10326     SET_H_GR (FLD (f_operand1), opval);
10327     written |= (1 << 10);
10328     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10329   }
10330 }
10331 }
10332 ; tmp_tmp_mem; }));
10333   {
10334     SI opval = tmp_tmpd;
10335     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10336     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10337   }
10338 {
10339   {
10340     BI opval = LTSI (tmp_tmpd, 0);
10341     CPU (h_nbit) = opval;
10342     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10343   }
10344   {
10345     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10346     CPU (h_zbit) = opval;
10347     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10348   }
10349 SET_H_CBIT_MOVE (0);
10350 SET_H_VBIT_MOVE (0);
10351 {
10352   {
10353     BI opval = 0;
10354     CPU (h_xbit) = opval;
10355     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10356   }
10357   {
10358     BI opval = 0;
10359     SET_H_INSN_PREFIXED_P (opval);
10360     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10361   }
10362 }
10363 }
10364 }
10365
10366   abuf->written = written;
10367 #undef FLD
10368 }
10369   NEXT (vpc);
10370
10371   CASE (sem, INSN_ANDCBR) : /* and.b ${sconst8}],${Rd} */
10372 {
10373   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10374   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10375 #define FLD(f) abuf->fields.sfmt_addcbr.f
10376   int UNUSED written = 0;
10377   IADDR UNUSED pc = abuf->addr;
10378   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
10379
10380 {
10381   QI tmp_tmpd;
10382   tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__byte));
10383 {
10384   SI tmp_oldregval;
10385   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
10386   {
10387     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10388     SET_H_GR (FLD (f_operand2), opval);
10389     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10390   }
10391 }
10392 {
10393   {
10394     BI opval = LTQI (tmp_tmpd, 0);
10395     CPU (h_nbit) = opval;
10396     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10397   }
10398   {
10399     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10400     CPU (h_zbit) = opval;
10401     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10402   }
10403 SET_H_CBIT_MOVE (0);
10404 SET_H_VBIT_MOVE (0);
10405 {
10406   {
10407     BI opval = 0;
10408     CPU (h_xbit) = opval;
10409     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10410   }
10411   {
10412     BI opval = 0;
10413     SET_H_INSN_PREFIXED_P (opval);
10414     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10415   }
10416 }
10417 }
10418 }
10419
10420 #undef FLD
10421 }
10422   NEXT (vpc);
10423
10424   CASE (sem, INSN_ANDCWR) : /* and.w ${sconst16}],${Rd} */
10425 {
10426   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10427   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10428 #define FLD(f) abuf->fields.sfmt_addcwr.f
10429   int UNUSED written = 0;
10430   IADDR UNUSED pc = abuf->addr;
10431   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
10432
10433 {
10434   HI tmp_tmpd;
10435   tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__word));
10436 {
10437   SI tmp_oldregval;
10438   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
10439   {
10440     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10441     SET_H_GR (FLD (f_operand2), opval);
10442     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10443   }
10444 }
10445 {
10446   {
10447     BI opval = LTHI (tmp_tmpd, 0);
10448     CPU (h_nbit) = opval;
10449     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10450   }
10451   {
10452     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10453     CPU (h_zbit) = opval;
10454     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10455   }
10456 SET_H_CBIT_MOVE (0);
10457 SET_H_VBIT_MOVE (0);
10458 {
10459   {
10460     BI opval = 0;
10461     CPU (h_xbit) = opval;
10462     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10463   }
10464   {
10465     BI opval = 0;
10466     SET_H_INSN_PREFIXED_P (opval);
10467     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10468   }
10469 }
10470 }
10471 }
10472
10473 #undef FLD
10474 }
10475   NEXT (vpc);
10476
10477   CASE (sem, INSN_ANDCDR) : /* and.d ${const32}],${Rd} */
10478 {
10479   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10480   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10481 #define FLD(f) abuf->fields.sfmt_addcdr.f
10482   int UNUSED written = 0;
10483   IADDR UNUSED pc = abuf->addr;
10484   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
10485
10486 {
10487   SI tmp_tmpd;
10488   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
10489   {
10490     SI opval = tmp_tmpd;
10491     SET_H_GR (FLD (f_operand2), opval);
10492     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10493   }
10494 {
10495   {
10496     BI opval = LTSI (tmp_tmpd, 0);
10497     CPU (h_nbit) = opval;
10498     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10499   }
10500   {
10501     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10502     CPU (h_zbit) = opval;
10503     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10504   }
10505 SET_H_CBIT_MOVE (0);
10506 SET_H_VBIT_MOVE (0);
10507 {
10508   {
10509     BI opval = 0;
10510     CPU (h_xbit) = opval;
10511     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10512   }
10513   {
10514     BI opval = 0;
10515     SET_H_INSN_PREFIXED_P (opval);
10516     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10517   }
10518 }
10519 }
10520 }
10521
10522 #undef FLD
10523 }
10524   NEXT (vpc);
10525
10526   CASE (sem, INSN_ANDQ) : /* andq $i,$Rd */
10527 {
10528   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10529   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10530 #define FLD(f) abuf->fields.sfmt_andq.f
10531   int UNUSED written = 0;
10532   IADDR UNUSED pc = abuf->addr;
10533   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10534
10535 {
10536   SI tmp_tmpd;
10537   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), FLD (f_s6));
10538   {
10539     SI opval = tmp_tmpd;
10540     SET_H_GR (FLD (f_operand2), opval);
10541     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10542   }
10543 {
10544   {
10545     BI opval = LTSI (tmp_tmpd, 0);
10546     CPU (h_nbit) = opval;
10547     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10548   }
10549   {
10550     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10551     CPU (h_zbit) = opval;
10552     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10553   }
10554 SET_H_CBIT_MOVE (0);
10555 SET_H_VBIT_MOVE (0);
10556 {
10557   {
10558     BI opval = 0;
10559     CPU (h_xbit) = opval;
10560     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10561   }
10562   {
10563     BI opval = 0;
10564     SET_H_INSN_PREFIXED_P (opval);
10565     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10566   }
10567 }
10568 }
10569 }
10570
10571 #undef FLD
10572 }
10573   NEXT (vpc);
10574
10575   CASE (sem, INSN_ORR_B_R) : /* orr.b $Rs,$Rd */
10576 {
10577   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10578   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10579 #define FLD(f) abuf->fields.sfmt_add_b_r.f
10580   int UNUSED written = 0;
10581   IADDR UNUSED pc = abuf->addr;
10582   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10583
10584 {
10585   QI tmp_tmpd;
10586   tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10587 {
10588   SI tmp_oldregval;
10589   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
10590   {
10591     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10592     SET_H_GR (FLD (f_operand2), opval);
10593     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10594   }
10595 }
10596 {
10597   {
10598     BI opval = LTQI (tmp_tmpd, 0);
10599     CPU (h_nbit) = opval;
10600     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10601   }
10602   {
10603     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10604     CPU (h_zbit) = opval;
10605     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10606   }
10607 SET_H_CBIT_MOVE (0);
10608 SET_H_VBIT_MOVE (0);
10609 {
10610   {
10611     BI opval = 0;
10612     CPU (h_xbit) = opval;
10613     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10614   }
10615   {
10616     BI opval = 0;
10617     SET_H_INSN_PREFIXED_P (opval);
10618     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10619   }
10620 }
10621 }
10622 }
10623
10624 #undef FLD
10625 }
10626   NEXT (vpc);
10627
10628   CASE (sem, INSN_ORR_W_R) : /* orr.w $Rs,$Rd */
10629 {
10630   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10631   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10632 #define FLD(f) abuf->fields.sfmt_add_b_r.f
10633   int UNUSED written = 0;
10634   IADDR UNUSED pc = abuf->addr;
10635   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10636
10637 {
10638   HI tmp_tmpd;
10639   tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10640 {
10641   SI tmp_oldregval;
10642   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
10643   {
10644     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10645     SET_H_GR (FLD (f_operand2), opval);
10646     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10647   }
10648 }
10649 {
10650   {
10651     BI opval = LTHI (tmp_tmpd, 0);
10652     CPU (h_nbit) = opval;
10653     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10654   }
10655   {
10656     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10657     CPU (h_zbit) = opval;
10658     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10659   }
10660 SET_H_CBIT_MOVE (0);
10661 SET_H_VBIT_MOVE (0);
10662 {
10663   {
10664     BI opval = 0;
10665     CPU (h_xbit) = opval;
10666     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10667   }
10668   {
10669     BI opval = 0;
10670     SET_H_INSN_PREFIXED_P (opval);
10671     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10672   }
10673 }
10674 }
10675 }
10676
10677 #undef FLD
10678 }
10679   NEXT (vpc);
10680
10681   CASE (sem, INSN_ORR_D_R) : /* orr.d $Rs,$Rd */
10682 {
10683   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10684   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10685 #define FLD(f) abuf->fields.sfmt_add_b_r.f
10686   int UNUSED written = 0;
10687   IADDR UNUSED pc = abuf->addr;
10688   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10689
10690 {
10691   SI tmp_tmpd;
10692   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10693   {
10694     SI opval = tmp_tmpd;
10695     SET_H_GR (FLD (f_operand2), opval);
10696     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10697   }
10698 {
10699   {
10700     BI opval = LTSI (tmp_tmpd, 0);
10701     CPU (h_nbit) = opval;
10702     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10703   }
10704   {
10705     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10706     CPU (h_zbit) = opval;
10707     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10708   }
10709 SET_H_CBIT_MOVE (0);
10710 SET_H_VBIT_MOVE (0);
10711 {
10712   {
10713     BI opval = 0;
10714     CPU (h_xbit) = opval;
10715     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10716   }
10717   {
10718     BI opval = 0;
10719     SET_H_INSN_PREFIXED_P (opval);
10720     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10721   }
10722 }
10723 }
10724 }
10725
10726 #undef FLD
10727 }
10728   NEXT (vpc);
10729
10730   CASE (sem, INSN_OR_M_B_M) : /* or-m.b [${Rs}${inc}],${Rd} */
10731 {
10732   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10733   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10734 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10735   int UNUSED written = 0;
10736   IADDR UNUSED pc = abuf->addr;
10737   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10738
10739 {
10740   QI tmp_tmpd;
10741   tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10742   QI tmp_tmp_mem;
10743   BI tmp_postinc;
10744   tmp_postinc = FLD (f_memmode);
10745 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
10746 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
10747 ; if (NEBI (tmp_postinc, 0)) {
10748 {
10749 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10750   tmp_addr = ADDSI (tmp_addr, 1);
10751 }
10752   {
10753     SI opval = tmp_addr;
10754     SET_H_GR (FLD (f_operand1), opval);
10755     written |= (1 << 11);
10756     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10757   }
10758 }
10759 }
10760 ; tmp_tmp_mem; }));
10761 {
10762   SI tmp_oldregval;
10763   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
10764   {
10765     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10766     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10767     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10768   }
10769 }
10770 {
10771   {
10772     BI opval = LTQI (tmp_tmpd, 0);
10773     CPU (h_nbit) = opval;
10774     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10775   }
10776   {
10777     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10778     CPU (h_zbit) = opval;
10779     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10780   }
10781 SET_H_CBIT_MOVE (0);
10782 SET_H_VBIT_MOVE (0);
10783 {
10784   {
10785     BI opval = 0;
10786     CPU (h_xbit) = opval;
10787     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10788   }
10789   {
10790     BI opval = 0;
10791     SET_H_INSN_PREFIXED_P (opval);
10792     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10793   }
10794 }
10795 }
10796 }
10797
10798   abuf->written = written;
10799 #undef FLD
10800 }
10801   NEXT (vpc);
10802
10803   CASE (sem, INSN_OR_M_W_M) : /* or-m.w [${Rs}${inc}],${Rd} */
10804 {
10805   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10806   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10807 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10808   int UNUSED written = 0;
10809   IADDR UNUSED pc = abuf->addr;
10810   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10811
10812 {
10813   HI tmp_tmpd;
10814   tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10815   HI tmp_tmp_mem;
10816   BI tmp_postinc;
10817   tmp_postinc = FLD (f_memmode);
10818 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
10819 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
10820 ; if (NEBI (tmp_postinc, 0)) {
10821 {
10822 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10823   tmp_addr = ADDSI (tmp_addr, 2);
10824 }
10825   {
10826     SI opval = tmp_addr;
10827     SET_H_GR (FLD (f_operand1), opval);
10828     written |= (1 << 11);
10829     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10830   }
10831 }
10832 }
10833 ; tmp_tmp_mem; }));
10834 {
10835   SI tmp_oldregval;
10836   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
10837   {
10838     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10839     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10840     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10841   }
10842 }
10843 {
10844   {
10845     BI opval = LTHI (tmp_tmpd, 0);
10846     CPU (h_nbit) = opval;
10847     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10848   }
10849   {
10850     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10851     CPU (h_zbit) = opval;
10852     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10853   }
10854 SET_H_CBIT_MOVE (0);
10855 SET_H_VBIT_MOVE (0);
10856 {
10857   {
10858     BI opval = 0;
10859     CPU (h_xbit) = opval;
10860     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10861   }
10862   {
10863     BI opval = 0;
10864     SET_H_INSN_PREFIXED_P (opval);
10865     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10866   }
10867 }
10868 }
10869 }
10870
10871   abuf->written = written;
10872 #undef FLD
10873 }
10874   NEXT (vpc);
10875
10876   CASE (sem, INSN_OR_M_D_M) : /* or-m.d [${Rs}${inc}],${Rd} */
10877 {
10878   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10879   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10880 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10881   int UNUSED written = 0;
10882   IADDR UNUSED pc = abuf->addr;
10883   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10884
10885 {
10886   SI tmp_tmpd;
10887   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10888   SI tmp_tmp_mem;
10889   BI tmp_postinc;
10890   tmp_postinc = FLD (f_memmode);
10891 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
10892 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
10893 ; if (NEBI (tmp_postinc, 0)) {
10894 {
10895 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10896   tmp_addr = ADDSI (tmp_addr, 4);
10897 }
10898   {
10899     SI opval = tmp_addr;
10900     SET_H_GR (FLD (f_operand1), opval);
10901     written |= (1 << 10);
10902     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10903   }
10904 }
10905 }
10906 ; tmp_tmp_mem; }));
10907   {
10908     SI opval = tmp_tmpd;
10909     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10910     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10911   }
10912 {
10913   {
10914     BI opval = LTSI (tmp_tmpd, 0);
10915     CPU (h_nbit) = opval;
10916     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10917   }
10918   {
10919     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10920     CPU (h_zbit) = opval;
10921     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10922   }
10923 SET_H_CBIT_MOVE (0);
10924 SET_H_VBIT_MOVE (0);
10925 {
10926   {
10927     BI opval = 0;
10928     CPU (h_xbit) = opval;
10929     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10930   }
10931   {
10932     BI opval = 0;
10933     SET_H_INSN_PREFIXED_P (opval);
10934     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10935   }
10936 }
10937 }
10938 }
10939
10940   abuf->written = written;
10941 #undef FLD
10942 }
10943   NEXT (vpc);
10944
10945   CASE (sem, INSN_ORCBR) : /* or.b ${sconst8}],${Rd} */
10946 {
10947   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10948   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10949 #define FLD(f) abuf->fields.sfmt_addcbr.f
10950   int UNUSED written = 0;
10951   IADDR UNUSED pc = abuf->addr;
10952   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
10953
10954 {
10955   QI tmp_tmpd;
10956   tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__byte));
10957 {
10958   SI tmp_oldregval;
10959   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
10960   {
10961     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10962     SET_H_GR (FLD (f_operand2), opval);
10963     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10964   }
10965 }
10966 {
10967   {
10968     BI opval = LTQI (tmp_tmpd, 0);
10969     CPU (h_nbit) = opval;
10970     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10971   }
10972   {
10973     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10974     CPU (h_zbit) = opval;
10975     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10976   }
10977 SET_H_CBIT_MOVE (0);
10978 SET_H_VBIT_MOVE (0);
10979 {
10980   {
10981     BI opval = 0;
10982     CPU (h_xbit) = opval;
10983     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10984   }
10985   {
10986     BI opval = 0;
10987     SET_H_INSN_PREFIXED_P (opval);
10988     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10989   }
10990 }
10991 }
10992 }
10993
10994 #undef FLD
10995 }
10996   NEXT (vpc);
10997
10998   CASE (sem, INSN_ORCWR) : /* or.w ${sconst16}],${Rd} */
10999 {
11000   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11001   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11002 #define FLD(f) abuf->fields.sfmt_addcwr.f
11003   int UNUSED written = 0;
11004   IADDR UNUSED pc = abuf->addr;
11005   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
11006
11007 {
11008   HI tmp_tmpd;
11009   tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__word));
11010 {
11011   SI tmp_oldregval;
11012   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
11013   {
11014     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
11015     SET_H_GR (FLD (f_operand2), opval);
11016     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11017   }
11018 }
11019 {
11020   {
11021     BI opval = LTHI (tmp_tmpd, 0);
11022     CPU (h_nbit) = opval;
11023     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11024   }
11025   {
11026     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11027     CPU (h_zbit) = opval;
11028     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11029   }
11030 SET_H_CBIT_MOVE (0);
11031 SET_H_VBIT_MOVE (0);
11032 {
11033   {
11034     BI opval = 0;
11035     CPU (h_xbit) = opval;
11036     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11037   }
11038   {
11039     BI opval = 0;
11040     SET_H_INSN_PREFIXED_P (opval);
11041     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11042   }
11043 }
11044 }
11045 }
11046
11047 #undef FLD
11048 }
11049   NEXT (vpc);
11050
11051   CASE (sem, INSN_ORCDR) : /* or.d ${const32}],${Rd} */
11052 {
11053   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11054   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11055 #define FLD(f) abuf->fields.sfmt_addcdr.f
11056   int UNUSED written = 0;
11057   IADDR UNUSED pc = abuf->addr;
11058   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
11059
11060 {
11061   SI tmp_tmpd;
11062   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
11063   {
11064     SI opval = tmp_tmpd;
11065     SET_H_GR (FLD (f_operand2), opval);
11066     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11067   }
11068 {
11069   {
11070     BI opval = LTSI (tmp_tmpd, 0);
11071     CPU (h_nbit) = opval;
11072     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11073   }
11074   {
11075     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11076     CPU (h_zbit) = opval;
11077     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11078   }
11079 SET_H_CBIT_MOVE (0);
11080 SET_H_VBIT_MOVE (0);
11081 {
11082   {
11083     BI opval = 0;
11084     CPU (h_xbit) = opval;
11085     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11086   }
11087   {
11088     BI opval = 0;
11089     SET_H_INSN_PREFIXED_P (opval);
11090     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11091   }
11092 }
11093 }
11094 }
11095
11096 #undef FLD
11097 }
11098   NEXT (vpc);
11099
11100   CASE (sem, INSN_ORQ) : /* orq $i,$Rd */
11101 {
11102   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11103   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11104 #define FLD(f) abuf->fields.sfmt_andq.f
11105   int UNUSED written = 0;
11106   IADDR UNUSED pc = abuf->addr;
11107   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11108
11109 {
11110   SI tmp_tmpd;
11111   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), FLD (f_s6));
11112   {
11113     SI opval = tmp_tmpd;
11114     SET_H_GR (FLD (f_operand2), opval);
11115     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11116   }
11117 {
11118   {
11119     BI opval = LTSI (tmp_tmpd, 0);
11120     CPU (h_nbit) = opval;
11121     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11122   }
11123   {
11124     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11125     CPU (h_zbit) = opval;
11126     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11127   }
11128 SET_H_CBIT_MOVE (0);
11129 SET_H_VBIT_MOVE (0);
11130 {
11131   {
11132     BI opval = 0;
11133     CPU (h_xbit) = opval;
11134     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11135   }
11136   {
11137     BI opval = 0;
11138     SET_H_INSN_PREFIXED_P (opval);
11139     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11140   }
11141 }
11142 }
11143 }
11144
11145 #undef FLD
11146 }
11147   NEXT (vpc);
11148
11149   CASE (sem, INSN_XOR) : /* xor $Rs,$Rd */
11150 {
11151   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11152   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11153 #define FLD(f) abuf->fields.sfmt_muls_b.f
11154   int UNUSED written = 0;
11155   IADDR UNUSED pc = abuf->addr;
11156   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11157
11158 {
11159   SI tmp_tmpd;
11160   tmp_tmpd = XORSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
11161   {
11162     SI opval = tmp_tmpd;
11163     SET_H_GR (FLD (f_operand2), opval);
11164     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11165   }
11166 {
11167   {
11168     BI opval = LTSI (tmp_tmpd, 0);
11169     CPU (h_nbit) = opval;
11170     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11171   }
11172   {
11173     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11174     CPU (h_zbit) = opval;
11175     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11176   }
11177 SET_H_CBIT_MOVE (0);
11178 SET_H_VBIT_MOVE (0);
11179 {
11180   {
11181     BI opval = 0;
11182     CPU (h_xbit) = opval;
11183     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11184   }
11185   {
11186     BI opval = 0;
11187     SET_H_INSN_PREFIXED_P (opval);
11188     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11189   }
11190 }
11191 }
11192 }
11193
11194 #undef FLD
11195 }
11196   NEXT (vpc);
11197
11198   CASE (sem, INSN_SWAP) : /* swap${swapoption} ${Rs} */
11199 {
11200   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11201   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11202 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
11203   int UNUSED written = 0;
11204   IADDR UNUSED pc = abuf->addr;
11205   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11206
11207 {
11208   SI tmp_tmps;
11209   SI tmp_tmpd;
11210   tmp_tmps = GET_H_GR (FLD (f_operand1));
11211   tmp_tmpd = ({   SI tmp_tmpcode;
11212   SI tmp_tmpval;
11213   SI tmp_tmpres;
11214   tmp_tmpcode = FLD (f_operand2);
11215 ;   tmp_tmpval = tmp_tmps;
11216 ; if (EQSI (tmp_tmpcode, 0)) {
11217   tmp_tmpres = (cgen_rtx_error (current_cpu, "SWAP without swap modifier isn't implemented"), 0);
11218 }
11219  else if (EQSI (tmp_tmpcode, 1)) {
11220   tmp_tmpres = ({   SI tmp_tmpr;
11221   tmp_tmpr = tmp_tmpval;
11222 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11223 }
11224  else if (EQSI (tmp_tmpcode, 2)) {
11225   tmp_tmpres = ({   SI tmp_tmpb;
11226   tmp_tmpb = tmp_tmpval;
11227 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11228 }
11229  else if (EQSI (tmp_tmpcode, 3)) {
11230   tmp_tmpres = ({   SI tmp_tmpr;
11231   tmp_tmpr = ({   SI tmp_tmpb;
11232   tmp_tmpb = tmp_tmpval;
11233 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11234 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11235 }
11236  else if (EQSI (tmp_tmpcode, 4)) {
11237   tmp_tmpres = ({   SI tmp_tmpb;
11238   tmp_tmpb = tmp_tmpval;
11239 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11240 }
11241  else if (EQSI (tmp_tmpcode, 5)) {
11242   tmp_tmpres = ({   SI tmp_tmpr;
11243   tmp_tmpr = ({   SI tmp_tmpb;
11244   tmp_tmpb = tmp_tmpval;
11245 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11246 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11247 }
11248  else if (EQSI (tmp_tmpcode, 6)) {
11249   tmp_tmpres = ({   SI tmp_tmpb;
11250   tmp_tmpb = ({   SI tmp_tmpb;
11251   tmp_tmpb = tmp_tmpval;
11252 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11253 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11254 }
11255  else if (EQSI (tmp_tmpcode, 7)) {
11256   tmp_tmpres = ({   SI tmp_tmpr;
11257   tmp_tmpr = ({   SI tmp_tmpb;
11258   tmp_tmpb = ({   SI tmp_tmpb;
11259   tmp_tmpb = tmp_tmpval;
11260 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11261 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11262 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11263 }
11264  else if (EQSI (tmp_tmpcode, 8)) {
11265   tmp_tmpres = INVSI (tmp_tmpval);
11266 }
11267  else if (EQSI (tmp_tmpcode, 9)) {
11268   tmp_tmpres = ({   SI tmp_tmpr;
11269   tmp_tmpr = INVSI (tmp_tmpval);
11270 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11271 }
11272  else if (EQSI (tmp_tmpcode, 10)) {
11273   tmp_tmpres = ({   SI tmp_tmpb;
11274   tmp_tmpb = INVSI (tmp_tmpval);
11275 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11276 }
11277  else if (EQSI (tmp_tmpcode, 11)) {
11278   tmp_tmpres = ({   SI tmp_tmpr;
11279   tmp_tmpr = ({   SI tmp_tmpb;
11280   tmp_tmpb = INVSI (tmp_tmpval);
11281 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11282 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11283 }
11284  else if (EQSI (tmp_tmpcode, 12)) {
11285   tmp_tmpres = ({   SI tmp_tmpb;
11286   tmp_tmpb = INVSI (tmp_tmpval);
11287 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11288 }
11289  else if (EQSI (tmp_tmpcode, 13)) {
11290   tmp_tmpres = ({   SI tmp_tmpr;
11291   tmp_tmpr = ({   SI tmp_tmpb;
11292   tmp_tmpb = INVSI (tmp_tmpval);
11293 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11294 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11295 }
11296  else if (EQSI (tmp_tmpcode, 14)) {
11297   tmp_tmpres = ({   SI tmp_tmpb;
11298   tmp_tmpb = ({   SI tmp_tmpb;
11299   tmp_tmpb = INVSI (tmp_tmpval);
11300 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11301 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11302 }
11303  else if (EQSI (tmp_tmpcode, 15)) {
11304   tmp_tmpres = ({   SI tmp_tmpr;
11305   tmp_tmpr = ({   SI tmp_tmpb;
11306   tmp_tmpb = ({   SI tmp_tmpb;
11307   tmp_tmpb = INVSI (tmp_tmpval);
11308 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11309 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11310 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11311 }
11312 ; tmp_tmpres; });
11313   {
11314     SI opval = tmp_tmpd;
11315     SET_H_GR (FLD (f_operand1), opval);
11316     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11317   }
11318 {
11319   {
11320     BI opval = LTSI (tmp_tmpd, 0);
11321     CPU (h_nbit) = opval;
11322     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11323   }
11324   {
11325     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11326     CPU (h_zbit) = opval;
11327     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11328   }
11329 SET_H_CBIT_MOVE (0);
11330 SET_H_VBIT_MOVE (0);
11331 {
11332   {
11333     BI opval = 0;
11334     CPU (h_xbit) = opval;
11335     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11336   }
11337   {
11338     BI opval = 0;
11339     SET_H_INSN_PREFIXED_P (opval);
11340     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11341   }
11342 }
11343 }
11344 }
11345
11346 #undef FLD
11347 }
11348   NEXT (vpc);
11349
11350   CASE (sem, INSN_ASRR_B_R) : /* asrr.b $Rs,$Rd */
11351 {
11352   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11353   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11354 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11355   int UNUSED written = 0;
11356   IADDR UNUSED pc = abuf->addr;
11357   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11358
11359 {
11360   QI tmp_tmpd;
11361   SI tmp_cnt1;
11362   SI tmp_cnt2;
11363   tmp_cnt1 = GET_H_GR (FLD (f_operand1));
11364   tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
11365   tmp_tmpd = SRASI (EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
11366 {
11367   SI tmp_oldregval;
11368   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
11369   {
11370     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
11371     SET_H_GR (FLD (f_operand2), opval);
11372     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11373   }
11374 }
11375 {
11376   {
11377     BI opval = LTQI (tmp_tmpd, 0);
11378     CPU (h_nbit) = opval;
11379     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11380   }
11381   {
11382     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11383     CPU (h_zbit) = opval;
11384     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11385   }
11386 SET_H_CBIT_MOVE (0);
11387 SET_H_VBIT_MOVE (0);
11388 {
11389   {
11390     BI opval = 0;
11391     CPU (h_xbit) = opval;
11392     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11393   }
11394   {
11395     BI opval = 0;
11396     SET_H_INSN_PREFIXED_P (opval);
11397     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11398   }
11399 }
11400 }
11401 }
11402
11403 #undef FLD
11404 }
11405   NEXT (vpc);
11406
11407   CASE (sem, INSN_ASRR_W_R) : /* asrr.w $Rs,$Rd */
11408 {
11409   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11410   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11411 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11412   int UNUSED written = 0;
11413   IADDR UNUSED pc = abuf->addr;
11414   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11415
11416 {
11417   HI tmp_tmpd;
11418   SI tmp_cnt1;
11419   SI tmp_cnt2;
11420   tmp_cnt1 = GET_H_GR (FLD (f_operand1));
11421   tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
11422   tmp_tmpd = SRASI (EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
11423 {
11424   SI tmp_oldregval;
11425   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
11426   {
11427     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
11428     SET_H_GR (FLD (f_operand2), opval);
11429     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11430   }
11431 }
11432 {
11433   {
11434     BI opval = LTHI (tmp_tmpd, 0);
11435     CPU (h_nbit) = opval;
11436     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11437   }
11438   {
11439     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11440     CPU (h_zbit) = opval;
11441     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11442   }
11443 SET_H_CBIT_MOVE (0);
11444 SET_H_VBIT_MOVE (0);
11445 {
11446   {
11447     BI opval = 0;
11448     CPU (h_xbit) = opval;
11449     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11450   }
11451   {
11452     BI opval = 0;
11453     SET_H_INSN_PREFIXED_P (opval);
11454     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11455   }
11456 }
11457 }
11458 }
11459
11460 #undef FLD
11461 }
11462   NEXT (vpc);
11463
11464   CASE (sem, INSN_ASRR_D_R) : /* asrr.d $Rs,$Rd */
11465 {
11466   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11467   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11468 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11469   int UNUSED written = 0;
11470   IADDR UNUSED pc = abuf->addr;
11471   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11472
11473 {
11474   SI tmp_tmpd;
11475   SI tmp_cnt1;
11476   SI tmp_cnt2;
11477   tmp_cnt1 = GET_H_GR (FLD (f_operand1));
11478   tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
11479   tmp_tmpd = SRASI (EXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
11480   {
11481     SI opval = tmp_tmpd;
11482     SET_H_GR (FLD (f_operand2), opval);
11483     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11484   }
11485 {
11486   {
11487     BI opval = LTSI (tmp_tmpd, 0);
11488     CPU (h_nbit) = opval;
11489     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11490   }
11491   {
11492     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11493     CPU (h_zbit) = opval;
11494     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11495   }
11496 SET_H_CBIT_MOVE (0);
11497 SET_H_VBIT_MOVE (0);
11498 {
11499   {
11500     BI opval = 0;
11501     CPU (h_xbit) = opval;
11502     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11503   }
11504   {
11505     BI opval = 0;
11506     SET_H_INSN_PREFIXED_P (opval);
11507     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11508   }
11509 }
11510 }
11511 }
11512
11513 #undef FLD
11514 }
11515   NEXT (vpc);
11516
11517   CASE (sem, INSN_ASRQ) : /* asrq $c,${Rd} */
11518 {
11519   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11520   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11521 #define FLD(f) abuf->fields.sfmt_asrq.f
11522   int UNUSED written = 0;
11523   IADDR UNUSED pc = abuf->addr;
11524   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11525
11526 {
11527   SI tmp_tmpd;
11528   tmp_tmpd = SRASI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
11529   {
11530     SI opval = tmp_tmpd;
11531     SET_H_GR (FLD (f_operand2), opval);
11532     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11533   }
11534 {
11535   {
11536     BI opval = LTSI (tmp_tmpd, 0);
11537     CPU (h_nbit) = opval;
11538     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11539   }
11540   {
11541     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11542     CPU (h_zbit) = opval;
11543     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11544   }
11545 SET_H_CBIT_MOVE (0);
11546 SET_H_VBIT_MOVE (0);
11547 {
11548   {
11549     BI opval = 0;
11550     CPU (h_xbit) = opval;
11551     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11552   }
11553   {
11554     BI opval = 0;
11555     SET_H_INSN_PREFIXED_P (opval);
11556     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11557   }
11558 }
11559 }
11560 }
11561
11562 #undef FLD
11563 }
11564   NEXT (vpc);
11565
11566   CASE (sem, INSN_LSRR_B_R) : /* lsrr.b $Rs,$Rd */
11567 {
11568   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11569   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11570 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11571   int UNUSED written = 0;
11572   IADDR UNUSED pc = abuf->addr;
11573   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11574
11575 {
11576   SI tmp_tmpd;
11577   SI tmp_cnt;
11578   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11579   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11580 {
11581   SI tmp_oldregval;
11582   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
11583   {
11584     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
11585     SET_H_GR (FLD (f_operand2), opval);
11586     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11587   }
11588 }
11589 {
11590   {
11591     BI opval = LTQI (tmp_tmpd, 0);
11592     CPU (h_nbit) = opval;
11593     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11594   }
11595   {
11596     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11597     CPU (h_zbit) = opval;
11598     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11599   }
11600 SET_H_CBIT_MOVE (0);
11601 SET_H_VBIT_MOVE (0);
11602 {
11603   {
11604     BI opval = 0;
11605     CPU (h_xbit) = opval;
11606     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11607   }
11608   {
11609     BI opval = 0;
11610     SET_H_INSN_PREFIXED_P (opval);
11611     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11612   }
11613 }
11614 }
11615 }
11616
11617 #undef FLD
11618 }
11619   NEXT (vpc);
11620
11621   CASE (sem, INSN_LSRR_W_R) : /* lsrr.w $Rs,$Rd */
11622 {
11623   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11624   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11625 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11626   int UNUSED written = 0;
11627   IADDR UNUSED pc = abuf->addr;
11628   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11629
11630 {
11631   SI tmp_tmpd;
11632   SI tmp_cnt;
11633   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11634   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11635 {
11636   SI tmp_oldregval;
11637   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
11638   {
11639     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
11640     SET_H_GR (FLD (f_operand2), opval);
11641     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11642   }
11643 }
11644 {
11645   {
11646     BI opval = LTHI (tmp_tmpd, 0);
11647     CPU (h_nbit) = opval;
11648     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11649   }
11650   {
11651     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11652     CPU (h_zbit) = opval;
11653     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11654   }
11655 SET_H_CBIT_MOVE (0);
11656 SET_H_VBIT_MOVE (0);
11657 {
11658   {
11659     BI opval = 0;
11660     CPU (h_xbit) = opval;
11661     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11662   }
11663   {
11664     BI opval = 0;
11665     SET_H_INSN_PREFIXED_P (opval);
11666     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11667   }
11668 }
11669 }
11670 }
11671
11672 #undef FLD
11673 }
11674   NEXT (vpc);
11675
11676   CASE (sem, INSN_LSRR_D_R) : /* lsrr.d $Rs,$Rd */
11677 {
11678   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11679   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11680 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11681   int UNUSED written = 0;
11682   IADDR UNUSED pc = abuf->addr;
11683   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11684
11685 {
11686   SI tmp_tmpd;
11687   SI tmp_cnt;
11688   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11689   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11690   {
11691     SI opval = tmp_tmpd;
11692     SET_H_GR (FLD (f_operand2), opval);
11693     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11694   }
11695 {
11696   {
11697     BI opval = LTSI (tmp_tmpd, 0);
11698     CPU (h_nbit) = opval;
11699     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11700   }
11701   {
11702     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11703     CPU (h_zbit) = opval;
11704     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11705   }
11706 SET_H_CBIT_MOVE (0);
11707 SET_H_VBIT_MOVE (0);
11708 {
11709   {
11710     BI opval = 0;
11711     CPU (h_xbit) = opval;
11712     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11713   }
11714   {
11715     BI opval = 0;
11716     SET_H_INSN_PREFIXED_P (opval);
11717     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11718   }
11719 }
11720 }
11721 }
11722
11723 #undef FLD
11724 }
11725   NEXT (vpc);
11726
11727   CASE (sem, INSN_LSRQ) : /* lsrq $c,${Rd} */
11728 {
11729   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11730   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11731 #define FLD(f) abuf->fields.sfmt_asrq.f
11732   int UNUSED written = 0;
11733   IADDR UNUSED pc = abuf->addr;
11734   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11735
11736 {
11737   SI tmp_tmpd;
11738   tmp_tmpd = SRLSI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
11739   {
11740     SI opval = tmp_tmpd;
11741     SET_H_GR (FLD (f_operand2), opval);
11742     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11743   }
11744 {
11745   {
11746     BI opval = LTSI (tmp_tmpd, 0);
11747     CPU (h_nbit) = opval;
11748     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11749   }
11750   {
11751     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11752     CPU (h_zbit) = opval;
11753     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11754   }
11755 SET_H_CBIT_MOVE (0);
11756 SET_H_VBIT_MOVE (0);
11757 {
11758   {
11759     BI opval = 0;
11760     CPU (h_xbit) = opval;
11761     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11762   }
11763   {
11764     BI opval = 0;
11765     SET_H_INSN_PREFIXED_P (opval);
11766     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11767   }
11768 }
11769 }
11770 }
11771
11772 #undef FLD
11773 }
11774   NEXT (vpc);
11775
11776   CASE (sem, INSN_LSLR_B_R) : /* lslr.b $Rs,$Rd */
11777 {
11778   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11779   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11780 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11781   int UNUSED written = 0;
11782   IADDR UNUSED pc = abuf->addr;
11783   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11784
11785 {
11786   SI tmp_tmpd;
11787   SI tmp_cnt;
11788   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11789   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11790 {
11791   SI tmp_oldregval;
11792   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
11793   {
11794     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
11795     SET_H_GR (FLD (f_operand2), opval);
11796     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11797   }
11798 }
11799 {
11800   {
11801     BI opval = LTQI (tmp_tmpd, 0);
11802     CPU (h_nbit) = opval;
11803     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11804   }
11805   {
11806     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11807     CPU (h_zbit) = opval;
11808     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11809   }
11810 SET_H_CBIT_MOVE (0);
11811 SET_H_VBIT_MOVE (0);
11812 {
11813   {
11814     BI opval = 0;
11815     CPU (h_xbit) = opval;
11816     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11817   }
11818   {
11819     BI opval = 0;
11820     SET_H_INSN_PREFIXED_P (opval);
11821     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11822   }
11823 }
11824 }
11825 }
11826
11827 #undef FLD
11828 }
11829   NEXT (vpc);
11830
11831   CASE (sem, INSN_LSLR_W_R) : /* lslr.w $Rs,$Rd */
11832 {
11833   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11834   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11835 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11836   int UNUSED written = 0;
11837   IADDR UNUSED pc = abuf->addr;
11838   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11839
11840 {
11841   SI tmp_tmpd;
11842   SI tmp_cnt;
11843   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11844   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11845 {
11846   SI tmp_oldregval;
11847   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
11848   {
11849     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
11850     SET_H_GR (FLD (f_operand2), opval);
11851     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11852   }
11853 }
11854 {
11855   {
11856     BI opval = LTHI (tmp_tmpd, 0);
11857     CPU (h_nbit) = opval;
11858     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11859   }
11860   {
11861     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11862     CPU (h_zbit) = opval;
11863     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11864   }
11865 SET_H_CBIT_MOVE (0);
11866 SET_H_VBIT_MOVE (0);
11867 {
11868   {
11869     BI opval = 0;
11870     CPU (h_xbit) = opval;
11871     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11872   }
11873   {
11874     BI opval = 0;
11875     SET_H_INSN_PREFIXED_P (opval);
11876     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11877   }
11878 }
11879 }
11880 }
11881
11882 #undef FLD
11883 }
11884   NEXT (vpc);
11885
11886   CASE (sem, INSN_LSLR_D_R) : /* lslr.d $Rs,$Rd */
11887 {
11888   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11889   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11890 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11891   int UNUSED written = 0;
11892   IADDR UNUSED pc = abuf->addr;
11893   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11894
11895 {
11896   SI tmp_tmpd;
11897   SI tmp_cnt;
11898   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11899   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11900   {
11901     SI opval = tmp_tmpd;
11902     SET_H_GR (FLD (f_operand2), opval);
11903     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11904   }
11905 {
11906   {
11907     BI opval = LTSI (tmp_tmpd, 0);
11908     CPU (h_nbit) = opval;
11909     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11910   }
11911   {
11912     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11913     CPU (h_zbit) = opval;
11914     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11915   }
11916 SET_H_CBIT_MOVE (0);
11917 SET_H_VBIT_MOVE (0);
11918 {
11919   {
11920     BI opval = 0;
11921     CPU (h_xbit) = opval;
11922     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11923   }
11924   {
11925     BI opval = 0;
11926     SET_H_INSN_PREFIXED_P (opval);
11927     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11928   }
11929 }
11930 }
11931 }
11932
11933 #undef FLD
11934 }
11935   NEXT (vpc);
11936
11937   CASE (sem, INSN_LSLQ) : /* lslq $c,${Rd} */
11938 {
11939   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11940   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11941 #define FLD(f) abuf->fields.sfmt_asrq.f
11942   int UNUSED written = 0;
11943   IADDR UNUSED pc = abuf->addr;
11944   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11945
11946 {
11947   SI tmp_tmpd;
11948   tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
11949   {
11950     SI opval = tmp_tmpd;
11951     SET_H_GR (FLD (f_operand2), opval);
11952     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11953   }
11954 {
11955   {
11956     BI opval = LTSI (tmp_tmpd, 0);
11957     CPU (h_nbit) = opval;
11958     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11959   }
11960   {
11961     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11962     CPU (h_zbit) = opval;
11963     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11964   }
11965 SET_H_CBIT_MOVE (0);
11966 SET_H_VBIT_MOVE (0);
11967 {
11968   {
11969     BI opval = 0;
11970     CPU (h_xbit) = opval;
11971     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11972   }
11973   {
11974     BI opval = 0;
11975     SET_H_INSN_PREFIXED_P (opval);
11976     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11977   }
11978 }
11979 }
11980 }
11981
11982 #undef FLD
11983 }
11984   NEXT (vpc);
11985
11986   CASE (sem, INSN_BTST) : /* $Rs,$Rd */
11987 {
11988   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11989   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11990 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11991   int UNUSED written = 0;
11992   IADDR UNUSED pc = abuf->addr;
11993   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11994
11995 {
11996   SI tmp_tmpd;
11997   SI tmp_cnt;
11998   tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), SUBSI (31, ANDSI (GET_H_GR (FLD (f_operand1)), 31)));
11999 {
12000   {
12001     BI opval = LTSI (tmp_tmpd, 0);
12002     CPU (h_nbit) = opval;
12003     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12004   }
12005   {
12006     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12007     CPU (h_zbit) = opval;
12008     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12009   }
12010 SET_H_CBIT_MOVE (0);
12011 SET_H_VBIT_MOVE (0);
12012 {
12013   {
12014     BI opval = 0;
12015     CPU (h_xbit) = opval;
12016     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12017   }
12018   {
12019     BI opval = 0;
12020     SET_H_INSN_PREFIXED_P (opval);
12021     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12022   }
12023 }
12024 }
12025 }
12026
12027 #undef FLD
12028 }
12029   NEXT (vpc);
12030
12031   CASE (sem, INSN_BTSTQ) : /* btstq $c,${Rd} */
12032 {
12033   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12034   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12035 #define FLD(f) abuf->fields.sfmt_asrq.f
12036   int UNUSED written = 0;
12037   IADDR UNUSED pc = abuf->addr;
12038   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12039
12040 {
12041   SI tmp_tmpd;
12042   tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), SUBSI (31, FLD (f_u5)));
12043 {
12044   {
12045     BI opval = LTSI (tmp_tmpd, 0);
12046     CPU (h_nbit) = opval;
12047     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12048   }
12049   {
12050     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12051     CPU (h_zbit) = opval;
12052     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12053   }
12054 SET_H_CBIT_MOVE (0);
12055 SET_H_VBIT_MOVE (0);
12056 {
12057   {
12058     BI opval = 0;
12059     CPU (h_xbit) = opval;
12060     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12061   }
12062   {
12063     BI opval = 0;
12064     SET_H_INSN_PREFIXED_P (opval);
12065     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12066   }
12067 }
12068 }
12069 }
12070
12071 #undef FLD
12072 }
12073   NEXT (vpc);
12074
12075   CASE (sem, INSN_SETF) : /* setf ${list-of-flags} */
12076 {
12077   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12078   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12079 #define FLD(f) abuf->fields.sfmt_setf.f
12080   int UNUSED written = 0;
12081   IADDR UNUSED pc = abuf->addr;
12082   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12083
12084 {
12085   SI tmp_tmp;
12086   tmp_tmp = FLD (f_dstsrc);
12087 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 0)), 0)) {
12088   {
12089     BI opval = 1;
12090     CPU (h_cbit) = opval;
12091     written |= (1 << 1);
12092     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
12093   }
12094 }
12095 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 1)), 0)) {
12096   {
12097     BI opval = 1;
12098     CPU (h_vbit) = opval;
12099     written |= (1 << 7);
12100     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
12101   }
12102 }
12103 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 2)), 0)) {
12104   {
12105     BI opval = 1;
12106     CPU (h_zbit) = opval;
12107     written |= (1 << 9);
12108     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12109   }
12110 }
12111 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 3)), 0)) {
12112   {
12113     BI opval = 1;
12114     CPU (h_nbit) = opval;
12115     written |= (1 << 3);
12116     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12117   }
12118 }
12119 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
12120   {
12121     BI opval = 1;
12122     CPU (h_xbit) = opval;
12123     written |= (1 << 8);
12124     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12125   }
12126 }
12127 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 5)), 0)) {
12128   {
12129     BI opval = 1;
12130     SET_H_IBIT (opval);
12131     written |= (1 << 2);
12132     TRACE_RESULT (current_cpu, abuf, "ibit", 'x', opval);
12133   }
12134 }
12135 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 6)), 0)) {
12136   {
12137     BI opval = 1;
12138     SET_H_UBIT (opval);
12139     written |= (1 << 6);
12140     TRACE_RESULT (current_cpu, abuf, "ubit", 'x', opval);
12141   }
12142 }
12143 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 7)), 0)) {
12144   {
12145     BI opval = 1;
12146     CPU (h_pbit) = opval;
12147     written |= (1 << 4);
12148     TRACE_RESULT (current_cpu, abuf, "pbit", 'x', opval);
12149   }
12150 }
12151   {
12152     BI opval = 0;
12153     SET_H_INSN_PREFIXED_P (opval);
12154     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12155   }
12156 if (EQSI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
12157   {
12158     BI opval = 0;
12159     CPU (h_xbit) = opval;
12160     written |= (1 << 8);
12161     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12162   }
12163 }
12164 }
12165
12166   abuf->written = written;
12167 #undef FLD
12168 }
12169   NEXT (vpc);
12170
12171   CASE (sem, INSN_CLEARF) : /* clearf ${list-of-flags} */
12172 {
12173   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12174   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12175 #define FLD(f) abuf->fields.sfmt_setf.f
12176   int UNUSED written = 0;
12177   IADDR UNUSED pc = abuf->addr;
12178   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12179
12180 {
12181   SI tmp_tmp;
12182   tmp_tmp = FLD (f_dstsrc);
12183 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 0)), 0)) {
12184   {
12185     BI opval = 0;
12186     CPU (h_cbit) = opval;
12187     written |= (1 << 1);
12188     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
12189   }
12190 }
12191 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 1)), 0)) {
12192   {
12193     BI opval = 0;
12194     CPU (h_vbit) = opval;
12195     written |= (1 << 7);
12196     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
12197   }
12198 }
12199 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 2)), 0)) {
12200   {
12201     BI opval = 0;
12202     CPU (h_zbit) = opval;
12203     written |= (1 << 9);
12204     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12205   }
12206 }
12207 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 3)), 0)) {
12208   {
12209     BI opval = 0;
12210     CPU (h_nbit) = opval;
12211     written |= (1 << 3);
12212     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12213   }
12214 }
12215 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
12216   {
12217     BI opval = 0;
12218     CPU (h_xbit) = opval;
12219     written |= (1 << 8);
12220     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12221   }
12222 }
12223 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 5)), 0)) {
12224   {
12225     BI opval = 0;
12226     SET_H_IBIT (opval);
12227     written |= (1 << 2);
12228     TRACE_RESULT (current_cpu, abuf, "ibit", 'x', opval);
12229   }
12230 }
12231 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 6)), 0)) {
12232   {
12233     BI opval = 0;
12234     SET_H_UBIT (opval);
12235     written |= (1 << 6);
12236     TRACE_RESULT (current_cpu, abuf, "ubit", 'x', opval);
12237   }
12238 }
12239 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 7)), 0)) {
12240   {
12241     BI opval = 0;
12242     CPU (h_pbit) = opval;
12243     written |= (1 << 4);
12244     TRACE_RESULT (current_cpu, abuf, "pbit", 'x', opval);
12245   }
12246 }
12247 {
12248   {
12249     BI opval = 0;
12250     CPU (h_xbit) = opval;
12251     written |= (1 << 8);
12252     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12253   }
12254   {
12255     BI opval = 0;
12256     SET_H_INSN_PREFIXED_P (opval);
12257     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12258   }
12259 }
12260 }
12261
12262   abuf->written = written;
12263 #undef FLD
12264 }
12265   NEXT (vpc);
12266
12267   CASE (sem, INSN_BCC_B) : /* b${cc} ${o-pcrel} */
12268 {
12269   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12270   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12271 #define FLD(f) abuf->fields.sfmt_bcc_b.f
12272   int UNUSED written = 0;
12273   IADDR UNUSED pc = abuf->addr;
12274   SEM_BRANCH_INIT
12275   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12276
12277 {
12278   BI tmp_truthval;
12279   tmp_truthval = ({   SI tmp_tmpcond;
12280   BI tmp_condres;
12281   tmp_tmpcond = FLD (f_operand2);
12282 ; if (EQSI (tmp_tmpcond, 0)) {
12283   tmp_condres = NOTBI (CPU (h_cbit));
12284 }
12285  else if (EQSI (tmp_tmpcond, 1)) {
12286   tmp_condres = CPU (h_cbit);
12287 }
12288  else if (EQSI (tmp_tmpcond, 2)) {
12289   tmp_condres = NOTBI (CPU (h_zbit));
12290 }
12291  else if (EQSI (tmp_tmpcond, 3)) {
12292   tmp_condres = CPU (h_zbit);
12293 }
12294  else if (EQSI (tmp_tmpcond, 4)) {
12295   tmp_condres = NOTBI (CPU (h_vbit));
12296 }
12297  else if (EQSI (tmp_tmpcond, 5)) {
12298   tmp_condres = CPU (h_vbit);
12299 }
12300  else if (EQSI (tmp_tmpcond, 6)) {
12301   tmp_condres = NOTBI (CPU (h_nbit));
12302 }
12303  else if (EQSI (tmp_tmpcond, 7)) {
12304   tmp_condres = CPU (h_nbit);
12305 }
12306  else if (EQSI (tmp_tmpcond, 8)) {
12307   tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
12308 }
12309  else if (EQSI (tmp_tmpcond, 9)) {
12310   tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
12311 }
12312  else if (EQSI (tmp_tmpcond, 10)) {
12313   tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
12314 }
12315  else if (EQSI (tmp_tmpcond, 11)) {
12316   tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
12317 }
12318  else if (EQSI (tmp_tmpcond, 12)) {
12319   tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
12320 }
12321  else if (EQSI (tmp_tmpcond, 13)) {
12322   tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
12323 }
12324  else if (EQSI (tmp_tmpcond, 14)) {
12325   tmp_condres = 1;
12326 }
12327  else if (EQSI (tmp_tmpcond, 15)) {
12328   tmp_condres = CPU (h_pbit);
12329 }
12330 ; tmp_condres; });
12331 crisv10f_branch_taken (current_cpu, pc, FLD (i_o_pcrel), tmp_truthval);
12332 {
12333   {
12334     BI opval = 0;
12335     CPU (h_xbit) = opval;
12336     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12337   }
12338   {
12339     BI opval = 0;
12340     SET_H_INSN_PREFIXED_P (opval);
12341     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12342   }
12343 }
12344 if (tmp_truthval) {
12345 {
12346   {
12347     USI opval = FLD (i_o_pcrel);
12348     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12349     written |= (1 << 8);
12350     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12351   }
12352 }
12353 }
12354 }
12355
12356   abuf->written = written;
12357   SEM_BRANCH_FINI (vpc);
12358 #undef FLD
12359 }
12360   NEXT (vpc);
12361
12362   CASE (sem, INSN_BA_B) : /* ba ${o-pcrel} */
12363 {
12364   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12365   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12366 #define FLD(f) abuf->fields.sfmt_bcc_b.f
12367   int UNUSED written = 0;
12368   IADDR UNUSED pc = abuf->addr;
12369   SEM_BRANCH_INIT
12370   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12371
12372 {
12373 {
12374   {
12375     BI opval = 0;
12376     CPU (h_xbit) = opval;
12377     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12378   }
12379   {
12380     BI opval = 0;
12381     SET_H_INSN_PREFIXED_P (opval);
12382     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12383   }
12384 }
12385 {
12386   {
12387     USI opval = FLD (i_o_pcrel);
12388     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12389     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12390   }
12391 }
12392 }
12393
12394   SEM_BRANCH_FINI (vpc);
12395 #undef FLD
12396 }
12397   NEXT (vpc);
12398
12399   CASE (sem, INSN_BCC_W) : /* b${cc} ${o-word-pcrel} */
12400 {
12401   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12402   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12403 #define FLD(f) abuf->fields.sfmt_bcc_w.f
12404   int UNUSED written = 0;
12405   IADDR UNUSED pc = abuf->addr;
12406   SEM_BRANCH_INIT
12407   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
12408
12409 {
12410   BI tmp_truthval;
12411   tmp_truthval = ({   SI tmp_tmpcond;
12412   BI tmp_condres;
12413   tmp_tmpcond = FLD (f_operand2);
12414 ; if (EQSI (tmp_tmpcond, 0)) {
12415   tmp_condres = NOTBI (CPU (h_cbit));
12416 }
12417  else if (EQSI (tmp_tmpcond, 1)) {
12418   tmp_condres = CPU (h_cbit);
12419 }
12420  else if (EQSI (tmp_tmpcond, 2)) {
12421   tmp_condres = NOTBI (CPU (h_zbit));
12422 }
12423  else if (EQSI (tmp_tmpcond, 3)) {
12424   tmp_condres = CPU (h_zbit);
12425 }
12426  else if (EQSI (tmp_tmpcond, 4)) {
12427   tmp_condres = NOTBI (CPU (h_vbit));
12428 }
12429  else if (EQSI (tmp_tmpcond, 5)) {
12430   tmp_condres = CPU (h_vbit);
12431 }
12432  else if (EQSI (tmp_tmpcond, 6)) {
12433   tmp_condres = NOTBI (CPU (h_nbit));
12434 }
12435  else if (EQSI (tmp_tmpcond, 7)) {
12436   tmp_condres = CPU (h_nbit);
12437 }
12438  else if (EQSI (tmp_tmpcond, 8)) {
12439   tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
12440 }
12441  else if (EQSI (tmp_tmpcond, 9)) {
12442   tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
12443 }
12444  else if (EQSI (tmp_tmpcond, 10)) {
12445   tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
12446 }
12447  else if (EQSI (tmp_tmpcond, 11)) {
12448   tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
12449 }
12450  else if (EQSI (tmp_tmpcond, 12)) {
12451   tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
12452 }
12453  else if (EQSI (tmp_tmpcond, 13)) {
12454   tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
12455 }
12456  else if (EQSI (tmp_tmpcond, 14)) {
12457   tmp_condres = 1;
12458 }
12459  else if (EQSI (tmp_tmpcond, 15)) {
12460   tmp_condres = CPU (h_pbit);
12461 }
12462 ; tmp_condres; });
12463 crisv10f_branch_taken (current_cpu, pc, FLD (i_o_word_pcrel), tmp_truthval);
12464 {
12465   {
12466     BI opval = 0;
12467     CPU (h_xbit) = opval;
12468     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12469   }
12470   {
12471     BI opval = 0;
12472     SET_H_INSN_PREFIXED_P (opval);
12473     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12474   }
12475 }
12476 if (tmp_truthval) {
12477 {
12478   {
12479     USI opval = FLD (i_o_word_pcrel);
12480     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12481     written |= (1 << 8);
12482     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12483   }
12484 }
12485 }
12486 }
12487
12488   abuf->written = written;
12489   SEM_BRANCH_FINI (vpc);
12490 #undef FLD
12491 }
12492   NEXT (vpc);
12493
12494   CASE (sem, INSN_BA_W) : /* ba ${o-word-pcrel} */
12495 {
12496   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12497   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12498 #define FLD(f) abuf->fields.sfmt_bcc_w.f
12499   int UNUSED written = 0;
12500   IADDR UNUSED pc = abuf->addr;
12501   SEM_BRANCH_INIT
12502   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
12503
12504 {
12505 {
12506   {
12507     BI opval = 0;
12508     CPU (h_xbit) = opval;
12509     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12510   }
12511   {
12512     BI opval = 0;
12513     SET_H_INSN_PREFIXED_P (opval);
12514     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12515   }
12516 }
12517 {
12518   {
12519     USI opval = FLD (i_o_word_pcrel);
12520     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12521     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12522   }
12523 }
12524 }
12525
12526   SEM_BRANCH_FINI (vpc);
12527 #undef FLD
12528 }
12529   NEXT (vpc);
12530
12531   CASE (sem, INSN_JUMP_R) : /* jump/jsr/jir ${Rs} */
12532 {
12533   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12534   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12535 #define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
12536   int UNUSED written = 0;
12537   IADDR UNUSED pc = abuf->addr;
12538   SEM_BRANCH_INIT
12539   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12540
12541 {
12542   {
12543     SI opval = ADDSI (pc, 2);
12544     SET_H_SR (FLD (f_operand2), opval);
12545     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12546   }
12547   {
12548     USI opval = GET_H_GR (FLD (f_operand1));
12549     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
12550     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12551   }
12552 {
12553   {
12554     BI opval = 0;
12555     CPU (h_xbit) = opval;
12556     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12557   }
12558   {
12559     BI opval = 0;
12560     SET_H_INSN_PREFIXED_P (opval);
12561     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12562   }
12563 }
12564 }
12565
12566   SEM_BRANCH_FINI (vpc);
12567 #undef FLD
12568 }
12569   NEXT (vpc);
12570
12571   CASE (sem, INSN_JUMP_M) : /* jump/jsr/jir [${Rs}${inc}] */
12572 {
12573   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12574   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12575 #define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
12576   int UNUSED written = 0;
12577   IADDR UNUSED pc = abuf->addr;
12578   SEM_BRANCH_INIT
12579   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12580
12581 {
12582   {
12583     SI opval = ADDSI (pc, 2);
12584     SET_H_SR (FLD (f_operand2), opval);
12585     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12586   }
12587   {
12588     USI opval = ({   SI tmp_addr;
12589   SI tmp_tmp_mem;
12590   BI tmp_postinc;
12591   tmp_postinc = FLD (f_memmode);
12592 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
12593 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
12594 ; if (NEBI (tmp_postinc, 0)) {
12595 {
12596 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
12597   tmp_addr = ADDSI (tmp_addr, 4);
12598 }
12599   {
12600     SI opval = tmp_addr;
12601     SET_H_GR (FLD (f_operand1), opval);
12602     written |= (1 << 7);
12603     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12604   }
12605 }
12606 }
12607 ; tmp_tmp_mem; });
12608     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
12609     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12610   }
12611 {
12612   {
12613     BI opval = 0;
12614     CPU (h_xbit) = opval;
12615     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12616   }
12617   {
12618     BI opval = 0;
12619     SET_H_INSN_PREFIXED_P (opval);
12620     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12621   }
12622 }
12623 }
12624
12625   abuf->written = written;
12626   SEM_BRANCH_FINI (vpc);
12627 #undef FLD
12628 }
12629   NEXT (vpc);
12630
12631   CASE (sem, INSN_JUMP_C) : /* jump/jsr/jir ${const32} */
12632 {
12633   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12634   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12635 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
12636   int UNUSED written = 0;
12637   IADDR UNUSED pc = abuf->addr;
12638   SEM_BRANCH_INIT
12639   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
12640
12641 {
12642   {
12643     SI opval = ADDSI (pc, 6);
12644     SET_H_SR (FLD (f_operand2), opval);
12645     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12646   }
12647   {
12648     USI opval = FLD (f_indir_pc__dword);
12649     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12650     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12651   }
12652 {
12653   {
12654     BI opval = 0;
12655     CPU (h_xbit) = opval;
12656     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12657   }
12658   {
12659     BI opval = 0;
12660     SET_H_INSN_PREFIXED_P (opval);
12661     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12662   }
12663 }
12664 }
12665
12666   SEM_BRANCH_FINI (vpc);
12667 #undef FLD
12668 }
12669   NEXT (vpc);
12670
12671   CASE (sem, INSN_BREAK) : /* break $n */
12672 {
12673   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12674   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12675 #define FLD(f) abuf->fields.sfmt_break.f
12676   int UNUSED written = 0;
12677   IADDR UNUSED pc = abuf->addr;
12678   SEM_BRANCH_INIT
12679   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12680
12681 {
12682 {
12683   {
12684     BI opval = 0;
12685     CPU (h_xbit) = opval;
12686     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12687   }
12688   {
12689     BI opval = 0;
12690     SET_H_INSN_PREFIXED_P (opval);
12691     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12692   }
12693 }
12694   {
12695     USI opval = crisv10f_break_handler (current_cpu, FLD (f_u4), pc);
12696     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
12697     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12698   }
12699 }
12700
12701   SEM_BRANCH_FINI (vpc);
12702 #undef FLD
12703 }
12704   NEXT (vpc);
12705
12706   CASE (sem, INSN_BOUND_R_B_R) : /* bound-r.b ${Rs},${Rd} */
12707 {
12708   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12709   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12710 #define FLD(f) abuf->fields.sfmt_muls_b.f
12711   int UNUSED written = 0;
12712   IADDR UNUSED pc = abuf->addr;
12713   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12714
12715 {
12716   SI tmp_tmpopd;
12717   SI tmp_tmpops;
12718   SI tmp_newval;
12719   tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
12720   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
12721   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
12722   {
12723     SI opval = tmp_newval;
12724     SET_H_GR (FLD (f_operand2), opval);
12725     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12726   }
12727 {
12728   {
12729     BI opval = LTSI (tmp_newval, 0);
12730     CPU (h_nbit) = opval;
12731     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12732   }
12733   {
12734     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12735     CPU (h_zbit) = opval;
12736     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12737   }
12738 SET_H_CBIT_MOVE (0);
12739 SET_H_VBIT_MOVE (0);
12740 {
12741   {
12742     BI opval = 0;
12743     CPU (h_xbit) = opval;
12744     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12745   }
12746   {
12747     BI opval = 0;
12748     SET_H_INSN_PREFIXED_P (opval);
12749     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12750   }
12751 }
12752 }
12753 }
12754
12755 #undef FLD
12756 }
12757   NEXT (vpc);
12758
12759   CASE (sem, INSN_BOUND_R_W_R) : /* bound-r.w ${Rs},${Rd} */
12760 {
12761   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12762   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12763 #define FLD(f) abuf->fields.sfmt_muls_b.f
12764   int UNUSED written = 0;
12765   IADDR UNUSED pc = abuf->addr;
12766   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12767
12768 {
12769   SI tmp_tmpopd;
12770   SI tmp_tmpops;
12771   SI tmp_newval;
12772   tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
12773   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
12774   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
12775   {
12776     SI opval = tmp_newval;
12777     SET_H_GR (FLD (f_operand2), opval);
12778     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12779   }
12780 {
12781   {
12782     BI opval = LTSI (tmp_newval, 0);
12783     CPU (h_nbit) = opval;
12784     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12785   }
12786   {
12787     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12788     CPU (h_zbit) = opval;
12789     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12790   }
12791 SET_H_CBIT_MOVE (0);
12792 SET_H_VBIT_MOVE (0);
12793 {
12794   {
12795     BI opval = 0;
12796     CPU (h_xbit) = opval;
12797     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12798   }
12799   {
12800     BI opval = 0;
12801     SET_H_INSN_PREFIXED_P (opval);
12802     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12803   }
12804 }
12805 }
12806 }
12807
12808 #undef FLD
12809 }
12810   NEXT (vpc);
12811
12812   CASE (sem, INSN_BOUND_R_D_R) : /* bound-r.d ${Rs},${Rd} */
12813 {
12814   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12815   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12816 #define FLD(f) abuf->fields.sfmt_muls_b.f
12817   int UNUSED written = 0;
12818   IADDR UNUSED pc = abuf->addr;
12819   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12820
12821 {
12822   SI tmp_tmpopd;
12823   SI tmp_tmpops;
12824   SI tmp_newval;
12825   tmp_tmpops = TRUNCSISI (GET_H_GR (FLD (f_operand1)));
12826   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
12827   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
12828   {
12829     SI opval = tmp_newval;
12830     SET_H_GR (FLD (f_operand2), opval);
12831     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12832   }
12833 {
12834   {
12835     BI opval = LTSI (tmp_newval, 0);
12836     CPU (h_nbit) = opval;
12837     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12838   }
12839   {
12840     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12841     CPU (h_zbit) = opval;
12842     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12843   }
12844 SET_H_CBIT_MOVE (0);
12845 SET_H_VBIT_MOVE (0);
12846 {
12847   {
12848     BI opval = 0;
12849     CPU (h_xbit) = opval;
12850     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12851   }
12852   {
12853     BI opval = 0;
12854     SET_H_INSN_PREFIXED_P (opval);
12855     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12856   }
12857 }
12858 }
12859 }
12860
12861 #undef FLD
12862 }
12863   NEXT (vpc);
12864
12865   CASE (sem, INSN_BOUND_M_B_M) : /* bound-m.b [${Rs}${inc}],${Rd} */
12866 {
12867   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12868   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12869 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
12870   int UNUSED written = 0;
12871   IADDR UNUSED pc = abuf->addr;
12872   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12873
12874 {
12875   SI tmp_tmpopd;
12876   SI tmp_tmpops;
12877   SI tmp_newval;
12878   tmp_tmpops = ZEXTQISI (({   SI tmp_addr;
12879   QI tmp_tmp_mem;
12880   BI tmp_postinc;
12881   tmp_postinc = FLD (f_memmode);
12882 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
12883 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
12884 ; if (NEBI (tmp_postinc, 0)) {
12885 {
12886 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
12887   tmp_addr = ADDSI (tmp_addr, 1);
12888 }
12889   {
12890     SI opval = tmp_addr;
12891     SET_H_GR (FLD (f_operand1), opval);
12892     written |= (1 << 9);
12893     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12894   }
12895 }
12896 }
12897 ; tmp_tmp_mem; }));
12898   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
12899   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
12900 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
12901   {
12902     SI opval = tmp_newval;
12903     SET_H_GR (FLD (f_operand1), opval);
12904     written |= (1 << 9);
12905     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12906   }
12907 } else {
12908   {
12909     SI opval = tmp_newval;
12910     SET_H_GR (FLD (f_operand2), opval);
12911     written |= (1 << 8);
12912     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12913   }
12914 }
12915 {
12916   {
12917     BI opval = LTSI (tmp_newval, 0);
12918     CPU (h_nbit) = opval;
12919     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12920   }
12921   {
12922     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12923     CPU (h_zbit) = opval;
12924     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12925   }
12926 SET_H_CBIT_MOVE (0);
12927 SET_H_VBIT_MOVE (0);
12928 {
12929   {
12930     BI opval = 0;
12931     CPU (h_xbit) = opval;
12932     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12933   }
12934   {
12935     BI opval = 0;
12936     SET_H_INSN_PREFIXED_P (opval);
12937     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12938   }
12939 }
12940 }
12941 }
12942
12943   abuf->written = written;
12944 #undef FLD
12945 }
12946   NEXT (vpc);
12947
12948   CASE (sem, INSN_BOUND_M_W_M) : /* bound-m.w [${Rs}${inc}],${Rd} */
12949 {
12950   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12951   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12952 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
12953   int UNUSED written = 0;
12954   IADDR UNUSED pc = abuf->addr;
12955   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12956
12957 {
12958   SI tmp_tmpopd;
12959   SI tmp_tmpops;
12960   SI tmp_newval;
12961   tmp_tmpops = ZEXTHISI (({   SI tmp_addr;
12962   HI tmp_tmp_mem;
12963   BI tmp_postinc;
12964   tmp_postinc = FLD (f_memmode);
12965 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
12966 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
12967 ; if (NEBI (tmp_postinc, 0)) {
12968 {
12969 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
12970   tmp_addr = ADDSI (tmp_addr, 2);
12971 }
12972   {
12973     SI opval = tmp_addr;
12974     SET_H_GR (FLD (f_operand1), opval);
12975     written |= (1 << 9);
12976     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12977   }
12978 }
12979 }
12980 ; tmp_tmp_mem; }));
12981   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
12982   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
12983 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
12984   {
12985     SI opval = tmp_newval;
12986     SET_H_GR (FLD (f_operand1), opval);
12987     written |= (1 << 9);
12988     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12989   }
12990 } else {
12991   {
12992     SI opval = tmp_newval;
12993     SET_H_GR (FLD (f_operand2), opval);
12994     written |= (1 << 8);
12995     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12996   }
12997 }
12998 {
12999   {
13000     BI opval = LTSI (tmp_newval, 0);
13001     CPU (h_nbit) = opval;
13002     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13003   }
13004   {
13005     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13006     CPU (h_zbit) = opval;
13007     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13008   }
13009 SET_H_CBIT_MOVE (0);
13010 SET_H_VBIT_MOVE (0);
13011 {
13012   {
13013     BI opval = 0;
13014     CPU (h_xbit) = opval;
13015     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13016   }
13017   {
13018     BI opval = 0;
13019     SET_H_INSN_PREFIXED_P (opval);
13020     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13021   }
13022 }
13023 }
13024 }
13025
13026   abuf->written = written;
13027 #undef FLD
13028 }
13029   NEXT (vpc);
13030
13031   CASE (sem, INSN_BOUND_M_D_M) : /* bound-m.d [${Rs}${inc}],${Rd} */
13032 {
13033   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13034   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13035 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
13036   int UNUSED written = 0;
13037   IADDR UNUSED pc = abuf->addr;
13038   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13039
13040 {
13041   SI tmp_tmpopd;
13042   SI tmp_tmpops;
13043   SI tmp_newval;
13044   tmp_tmpops = ({   SI tmp_addr;
13045   SI tmp_tmp_mem;
13046   BI tmp_postinc;
13047   tmp_postinc = FLD (f_memmode);
13048 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
13049 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
13050 ; if (NEBI (tmp_postinc, 0)) {
13051 {
13052 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13053   tmp_addr = ADDSI (tmp_addr, 4);
13054 }
13055   {
13056     SI opval = tmp_addr;
13057     SET_H_GR (FLD (f_operand1), opval);
13058     written |= (1 << 9);
13059     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13060   }
13061 }
13062 }
13063 ; tmp_tmp_mem; });
13064   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13065   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13066 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
13067   {
13068     SI opval = tmp_newval;
13069     SET_H_GR (FLD (f_operand1), opval);
13070     written |= (1 << 9);
13071     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13072   }
13073 } else {
13074   {
13075     SI opval = tmp_newval;
13076     SET_H_GR (FLD (f_operand2), opval);
13077     written |= (1 << 8);
13078     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13079   }
13080 }
13081 {
13082   {
13083     BI opval = LTSI (tmp_newval, 0);
13084     CPU (h_nbit) = opval;
13085     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13086   }
13087   {
13088     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13089     CPU (h_zbit) = opval;
13090     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13091   }
13092 SET_H_CBIT_MOVE (0);
13093 SET_H_VBIT_MOVE (0);
13094 {
13095   {
13096     BI opval = 0;
13097     CPU (h_xbit) = opval;
13098     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13099   }
13100   {
13101     BI opval = 0;
13102     SET_H_INSN_PREFIXED_P (opval);
13103     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13104   }
13105 }
13106 }
13107 }
13108
13109   abuf->written = written;
13110 #undef FLD
13111 }
13112   NEXT (vpc);
13113
13114   CASE (sem, INSN_BOUND_CB) : /* bound.b [PC+],${Rd} */
13115 {
13116   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13117   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13118 #define FLD(f) abuf->fields.sfmt_bound_cb.f
13119   int UNUSED written = 0;
13120   IADDR UNUSED pc = abuf->addr;
13121   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
13122
13123 {
13124   SI tmp_tmpopd;
13125   SI tmp_tmpops;
13126   SI tmp_newval;
13127   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
13128   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13129   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13130   {
13131     SI opval = tmp_newval;
13132     SET_H_GR (FLD (f_operand2), opval);
13133     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13134   }
13135 {
13136   {
13137     BI opval = LTSI (tmp_newval, 0);
13138     CPU (h_nbit) = opval;
13139     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13140   }
13141   {
13142     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13143     CPU (h_zbit) = opval;
13144     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13145   }
13146 SET_H_CBIT_MOVE (0);
13147 SET_H_VBIT_MOVE (0);
13148 {
13149   {
13150     BI opval = 0;
13151     CPU (h_xbit) = opval;
13152     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13153   }
13154   {
13155     BI opval = 0;
13156     SET_H_INSN_PREFIXED_P (opval);
13157     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13158   }
13159 }
13160 }
13161 }
13162
13163 #undef FLD
13164 }
13165   NEXT (vpc);
13166
13167   CASE (sem, INSN_BOUND_CW) : /* bound.w [PC+],${Rd} */
13168 {
13169   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13170   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13171 #define FLD(f) abuf->fields.sfmt_bound_cw.f
13172   int UNUSED written = 0;
13173   IADDR UNUSED pc = abuf->addr;
13174   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
13175
13176 {
13177   SI tmp_tmpopd;
13178   SI tmp_tmpops;
13179   SI tmp_newval;
13180   tmp_tmpops = ZEXTSISI (FLD (f_indir_pc__word));
13181   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13182   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13183   {
13184     SI opval = tmp_newval;
13185     SET_H_GR (FLD (f_operand2), opval);
13186     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13187   }
13188 {
13189   {
13190     BI opval = LTSI (tmp_newval, 0);
13191     CPU (h_nbit) = opval;
13192     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13193   }
13194   {
13195     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13196     CPU (h_zbit) = opval;
13197     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13198   }
13199 SET_H_CBIT_MOVE (0);
13200 SET_H_VBIT_MOVE (0);
13201 {
13202   {
13203     BI opval = 0;
13204     CPU (h_xbit) = opval;
13205     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13206   }
13207   {
13208     BI opval = 0;
13209     SET_H_INSN_PREFIXED_P (opval);
13210     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13211   }
13212 }
13213 }
13214 }
13215
13216 #undef FLD
13217 }
13218   NEXT (vpc);
13219
13220   CASE (sem, INSN_BOUND_CD) : /* bound.d [PC+],${Rd} */
13221 {
13222   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13223   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13224 #define FLD(f) abuf->fields.sfmt_bound_cd.f
13225   int UNUSED written = 0;
13226   IADDR UNUSED pc = abuf->addr;
13227   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
13228
13229 {
13230   SI tmp_tmpopd;
13231   SI tmp_tmpops;
13232   SI tmp_newval;
13233   tmp_tmpops = FLD (f_indir_pc__dword);
13234   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13235   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13236   {
13237     SI opval = tmp_newval;
13238     SET_H_GR (FLD (f_operand2), opval);
13239     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13240   }
13241 {
13242   {
13243     BI opval = LTSI (tmp_newval, 0);
13244     CPU (h_nbit) = opval;
13245     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13246   }
13247   {
13248     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13249     CPU (h_zbit) = opval;
13250     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13251   }
13252 SET_H_CBIT_MOVE (0);
13253 SET_H_VBIT_MOVE (0);
13254 {
13255   {
13256     BI opval = 0;
13257     CPU (h_xbit) = opval;
13258     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13259   }
13260   {
13261     BI opval = 0;
13262     SET_H_INSN_PREFIXED_P (opval);
13263     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13264   }
13265 }
13266 }
13267 }
13268
13269 #undef FLD
13270 }
13271   NEXT (vpc);
13272
13273   CASE (sem, INSN_SCC) : /* s${cc} ${Rd-sfield} */
13274 {
13275   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13276   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13277 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
13278   int UNUSED written = 0;
13279   IADDR UNUSED pc = abuf->addr;
13280   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13281
13282 {
13283   BI tmp_truthval;
13284   tmp_truthval = ({   SI tmp_tmpcond;
13285   BI tmp_condres;
13286   tmp_tmpcond = FLD (f_operand2);
13287 ; if (EQSI (tmp_tmpcond, 0)) {
13288   tmp_condres = NOTBI (CPU (h_cbit));
13289 }
13290  else if (EQSI (tmp_tmpcond, 1)) {
13291   tmp_condres = CPU (h_cbit);
13292 }
13293  else if (EQSI (tmp_tmpcond, 2)) {
13294   tmp_condres = NOTBI (CPU (h_zbit));
13295 }
13296  else if (EQSI (tmp_tmpcond, 3)) {
13297   tmp_condres = CPU (h_zbit);
13298 }
13299  else if (EQSI (tmp_tmpcond, 4)) {
13300   tmp_condres = NOTBI (CPU (h_vbit));
13301 }
13302  else if (EQSI (tmp_tmpcond, 5)) {
13303   tmp_condres = CPU (h_vbit);
13304 }
13305  else if (EQSI (tmp_tmpcond, 6)) {
13306   tmp_condres = NOTBI (CPU (h_nbit));
13307 }
13308  else if (EQSI (tmp_tmpcond, 7)) {
13309   tmp_condres = CPU (h_nbit);
13310 }
13311  else if (EQSI (tmp_tmpcond, 8)) {
13312   tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
13313 }
13314  else if (EQSI (tmp_tmpcond, 9)) {
13315   tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
13316 }
13317  else if (EQSI (tmp_tmpcond, 10)) {
13318   tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
13319 }
13320  else if (EQSI (tmp_tmpcond, 11)) {
13321   tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
13322 }
13323  else if (EQSI (tmp_tmpcond, 12)) {
13324   tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
13325 }
13326  else if (EQSI (tmp_tmpcond, 13)) {
13327   tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
13328 }
13329  else if (EQSI (tmp_tmpcond, 14)) {
13330   tmp_condres = 1;
13331 }
13332  else if (EQSI (tmp_tmpcond, 15)) {
13333   tmp_condres = CPU (h_pbit);
13334 }
13335 ; tmp_condres; });
13336   {
13337     SI opval = ZEXTBISI (tmp_truthval);
13338     SET_H_GR (FLD (f_operand1), opval);
13339     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13340   }
13341 {
13342   {
13343     BI opval = 0;
13344     CPU (h_xbit) = opval;
13345     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13346   }
13347   {
13348     BI opval = 0;
13349     SET_H_INSN_PREFIXED_P (opval);
13350     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13351   }
13352 }
13353 }
13354
13355 #undef FLD
13356 }
13357   NEXT (vpc);
13358
13359   CASE (sem, INSN_LZ) : /* lz ${Rs},${Rd} */
13360 {
13361   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13362   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13363 #define FLD(f) abuf->fields.sfmt_muls_b.f
13364   int UNUSED written = 0;
13365   IADDR UNUSED pc = abuf->addr;
13366   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13367
13368 {
13369   SI tmp_tmpd;
13370   SI tmp_tmp;
13371   tmp_tmp = GET_H_GR (FLD (f_operand1));
13372   tmp_tmpd = 0;
13373 {
13374 if (GESI (tmp_tmp, 0)) {
13375 {
13376   tmp_tmp = SLLSI (tmp_tmp, 1);
13377   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13378 }
13379 }
13380 if (GESI (tmp_tmp, 0)) {
13381 {
13382   tmp_tmp = SLLSI (tmp_tmp, 1);
13383   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13384 }
13385 }
13386 if (GESI (tmp_tmp, 0)) {
13387 {
13388   tmp_tmp = SLLSI (tmp_tmp, 1);
13389   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13390 }
13391 }
13392 if (GESI (tmp_tmp, 0)) {
13393 {
13394   tmp_tmp = SLLSI (tmp_tmp, 1);
13395   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13396 }
13397 }
13398 if (GESI (tmp_tmp, 0)) {
13399 {
13400   tmp_tmp = SLLSI (tmp_tmp, 1);
13401   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13402 }
13403 }
13404 if (GESI (tmp_tmp, 0)) {
13405 {
13406   tmp_tmp = SLLSI (tmp_tmp, 1);
13407   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13408 }
13409 }
13410 if (GESI (tmp_tmp, 0)) {
13411 {
13412   tmp_tmp = SLLSI (tmp_tmp, 1);
13413   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13414 }
13415 }
13416 if (GESI (tmp_tmp, 0)) {
13417 {
13418   tmp_tmp = SLLSI (tmp_tmp, 1);
13419   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13420 }
13421 }
13422 if (GESI (tmp_tmp, 0)) {
13423 {
13424   tmp_tmp = SLLSI (tmp_tmp, 1);
13425   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13426 }
13427 }
13428 if (GESI (tmp_tmp, 0)) {
13429 {
13430   tmp_tmp = SLLSI (tmp_tmp, 1);
13431   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13432 }
13433 }
13434 if (GESI (tmp_tmp, 0)) {
13435 {
13436   tmp_tmp = SLLSI (tmp_tmp, 1);
13437   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13438 }
13439 }
13440 if (GESI (tmp_tmp, 0)) {
13441 {
13442   tmp_tmp = SLLSI (tmp_tmp, 1);
13443   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13444 }
13445 }
13446 if (GESI (tmp_tmp, 0)) {
13447 {
13448   tmp_tmp = SLLSI (tmp_tmp, 1);
13449   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13450 }
13451 }
13452 if (GESI (tmp_tmp, 0)) {
13453 {
13454   tmp_tmp = SLLSI (tmp_tmp, 1);
13455   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13456 }
13457 }
13458 if (GESI (tmp_tmp, 0)) {
13459 {
13460   tmp_tmp = SLLSI (tmp_tmp, 1);
13461   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13462 }
13463 }
13464 if (GESI (tmp_tmp, 0)) {
13465 {
13466   tmp_tmp = SLLSI (tmp_tmp, 1);
13467   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13468 }
13469 }
13470 if (GESI (tmp_tmp, 0)) {
13471 {
13472   tmp_tmp = SLLSI (tmp_tmp, 1);
13473   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13474 }
13475 }
13476 if (GESI (tmp_tmp, 0)) {
13477 {
13478   tmp_tmp = SLLSI (tmp_tmp, 1);
13479   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13480 }
13481 }
13482 if (GESI (tmp_tmp, 0)) {
13483 {
13484   tmp_tmp = SLLSI (tmp_tmp, 1);
13485   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13486 }
13487 }
13488 if (GESI (tmp_tmp, 0)) {
13489 {
13490   tmp_tmp = SLLSI (tmp_tmp, 1);
13491   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13492 }
13493 }
13494 if (GESI (tmp_tmp, 0)) {
13495 {
13496   tmp_tmp = SLLSI (tmp_tmp, 1);
13497   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13498 }
13499 }
13500 if (GESI (tmp_tmp, 0)) {
13501 {
13502   tmp_tmp = SLLSI (tmp_tmp, 1);
13503   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13504 }
13505 }
13506 if (GESI (tmp_tmp, 0)) {
13507 {
13508   tmp_tmp = SLLSI (tmp_tmp, 1);
13509   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13510 }
13511 }
13512 if (GESI (tmp_tmp, 0)) {
13513 {
13514   tmp_tmp = SLLSI (tmp_tmp, 1);
13515   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13516 }
13517 }
13518 if (GESI (tmp_tmp, 0)) {
13519 {
13520   tmp_tmp = SLLSI (tmp_tmp, 1);
13521   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13522 }
13523 }
13524 if (GESI (tmp_tmp, 0)) {
13525 {
13526   tmp_tmp = SLLSI (tmp_tmp, 1);
13527   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13528 }
13529 }
13530 if (GESI (tmp_tmp, 0)) {
13531 {
13532   tmp_tmp = SLLSI (tmp_tmp, 1);
13533   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13534 }
13535 }
13536 if (GESI (tmp_tmp, 0)) {
13537 {
13538   tmp_tmp = SLLSI (tmp_tmp, 1);
13539   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13540 }
13541 }
13542 if (GESI (tmp_tmp, 0)) {
13543 {
13544   tmp_tmp = SLLSI (tmp_tmp, 1);
13545   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13546 }
13547 }
13548 if (GESI (tmp_tmp, 0)) {
13549 {
13550   tmp_tmp = SLLSI (tmp_tmp, 1);
13551   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13552 }
13553 }
13554 if (GESI (tmp_tmp, 0)) {
13555 {
13556   tmp_tmp = SLLSI (tmp_tmp, 1);
13557   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13558 }
13559 }
13560 if (GESI (tmp_tmp, 0)) {
13561 {
13562   tmp_tmp = SLLSI (tmp_tmp, 1);
13563   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13564 }
13565 }
13566 }
13567   {
13568     SI opval = tmp_tmpd;
13569     SET_H_GR (FLD (f_operand2), opval);
13570     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13571   }
13572 {
13573   {
13574     BI opval = LTSI (tmp_tmpd, 0);
13575     CPU (h_nbit) = opval;
13576     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13577   }
13578   {
13579     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13580     CPU (h_zbit) = opval;
13581     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13582   }
13583 SET_H_CBIT_MOVE (0);
13584 SET_H_VBIT_MOVE (0);
13585 {
13586   {
13587     BI opval = 0;
13588     CPU (h_xbit) = opval;
13589     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13590   }
13591   {
13592     BI opval = 0;
13593     SET_H_INSN_PREFIXED_P (opval);
13594     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13595   }
13596 }
13597 }
13598 }
13599
13600 #undef FLD
13601 }
13602   NEXT (vpc);
13603
13604   CASE (sem, INSN_ADDOQ) : /* addoq $o,$Rs,ACR */
13605 {
13606   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13607   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13608 #define FLD(f) abuf->fields.sfmt_addoq.f
13609   int UNUSED written = 0;
13610   IADDR UNUSED pc = abuf->addr;
13611   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13612
13613 {
13614   {
13615     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), FLD (f_s8));
13616     CPU (h_prefixreg_pre_v32) = opval;
13617     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13618   }
13619   {
13620     BI opval = 1;
13621     SET_H_INSN_PREFIXED_P (opval);
13622     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13623   }
13624 }
13625
13626 #undef FLD
13627 }
13628   NEXT (vpc);
13629
13630   CASE (sem, INSN_BDAPQPC) : /* bdapq $o,PC */
13631 {
13632   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13633   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13634 #define FLD(f) abuf->fields.sfmt_addoq.f
13635   int UNUSED written = 0;
13636   IADDR UNUSED pc = abuf->addr;
13637   SEM_BRANCH_INIT
13638   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13639
13640 {
13641   {
13642     SI opval = ADDSI (ADDSI (pc, 2), FLD (f_s8));
13643     CPU (h_prefixreg_pre_v32) = opval;
13644     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13645   }
13646   {
13647     BI opval = 1;
13648     SET_H_INSN_PREFIXED_P (opval);
13649     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13650   }
13651 cris_flush_simulator_decode_cache (current_cpu, pc);
13652 }
13653
13654   SEM_BRANCH_FINI (vpc);
13655 #undef FLD
13656 }
13657   NEXT (vpc);
13658
13659   CASE (sem, INSN_ADDO_M_B_M) : /* addo-m.b [${Rs}${inc}],$Rd,ACR */
13660 {
13661   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13662   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13663 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
13664   int UNUSED written = 0;
13665   IADDR UNUSED pc = abuf->addr;
13666   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13667
13668 {
13669   QI tmp_tmps;
13670   tmp_tmps = ({   SI tmp_addr;
13671   QI tmp_tmp_mem;
13672   BI tmp_postinc;
13673   tmp_postinc = FLD (f_memmode);
13674 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
13675 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
13676 ; if (NEBI (tmp_postinc, 0)) {
13677 {
13678 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13679   tmp_addr = ADDSI (tmp_addr, 1);
13680 }
13681   {
13682     SI opval = tmp_addr;
13683     SET_H_GR (FLD (f_operand1), opval);
13684     written |= (1 << 6);
13685     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13686   }
13687 }
13688 }
13689 ; tmp_tmp_mem; });
13690   {
13691     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTQISI (tmp_tmps));
13692     CPU (h_prefixreg_pre_v32) = opval;
13693     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13694   }
13695   {
13696     BI opval = 1;
13697     SET_H_INSN_PREFIXED_P (opval);
13698     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13699   }
13700 }
13701
13702   abuf->written = written;
13703 #undef FLD
13704 }
13705   NEXT (vpc);
13706
13707   CASE (sem, INSN_ADDO_M_W_M) : /* addo-m.w [${Rs}${inc}],$Rd,ACR */
13708 {
13709   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13710   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13711 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
13712   int UNUSED written = 0;
13713   IADDR UNUSED pc = abuf->addr;
13714   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13715
13716 {
13717   HI tmp_tmps;
13718   tmp_tmps = ({   SI tmp_addr;
13719   HI tmp_tmp_mem;
13720   BI tmp_postinc;
13721   tmp_postinc = FLD (f_memmode);
13722 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
13723 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
13724 ; if (NEBI (tmp_postinc, 0)) {
13725 {
13726 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13727   tmp_addr = ADDSI (tmp_addr, 2);
13728 }
13729   {
13730     SI opval = tmp_addr;
13731     SET_H_GR (FLD (f_operand1), opval);
13732     written |= (1 << 6);
13733     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13734   }
13735 }
13736 }
13737 ; tmp_tmp_mem; });
13738   {
13739     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTHISI (tmp_tmps));
13740     CPU (h_prefixreg_pre_v32) = opval;
13741     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13742   }
13743   {
13744     BI opval = 1;
13745     SET_H_INSN_PREFIXED_P (opval);
13746     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13747   }
13748 }
13749
13750   abuf->written = written;
13751 #undef FLD
13752 }
13753   NEXT (vpc);
13754
13755   CASE (sem, INSN_ADDO_M_D_M) : /* addo-m.d [${Rs}${inc}],$Rd,ACR */
13756 {
13757   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13758   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13759 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
13760   int UNUSED written = 0;
13761   IADDR UNUSED pc = abuf->addr;
13762   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13763
13764 {
13765   SI tmp_tmps;
13766   tmp_tmps = ({   SI tmp_addr;
13767   SI tmp_tmp_mem;
13768   BI tmp_postinc;
13769   tmp_postinc = FLD (f_memmode);
13770 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
13771 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
13772 ; if (NEBI (tmp_postinc, 0)) {
13773 {
13774 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13775   tmp_addr = ADDSI (tmp_addr, 4);
13776 }
13777   {
13778     SI opval = tmp_addr;
13779     SET_H_GR (FLD (f_operand1), opval);
13780     written |= (1 << 6);
13781     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13782   }
13783 }
13784 }
13785 ; tmp_tmp_mem; });
13786   {
13787     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), tmp_tmps);
13788     CPU (h_prefixreg_pre_v32) = opval;
13789     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13790   }
13791   {
13792     BI opval = 1;
13793     SET_H_INSN_PREFIXED_P (opval);
13794     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13795   }
13796 }
13797
13798   abuf->written = written;
13799 #undef FLD
13800 }
13801   NEXT (vpc);
13802
13803   CASE (sem, INSN_ADDO_CB) : /* addo.b [PC+],$Rd,ACR */
13804 {
13805   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13806   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13807 #define FLD(f) abuf->fields.sfmt_bound_cb.f
13808   int UNUSED written = 0;
13809   IADDR UNUSED pc = abuf->addr;
13810   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
13811
13812 {
13813   {
13814     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte))));
13815     CPU (h_prefixreg_pre_v32) = opval;
13816     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13817   }
13818   {
13819     BI opval = 1;
13820     SET_H_INSN_PREFIXED_P (opval);
13821     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13822   }
13823 }
13824
13825 #undef FLD
13826 }
13827   NEXT (vpc);
13828
13829   CASE (sem, INSN_ADDO_CW) : /* addo.w [PC+],$Rd,ACR */
13830 {
13831   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13832   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13833 #define FLD(f) abuf->fields.sfmt_bound_cw.f
13834   int UNUSED written = 0;
13835   IADDR UNUSED pc = abuf->addr;
13836   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
13837
13838 {
13839   {
13840     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word))));
13841     CPU (h_prefixreg_pre_v32) = opval;
13842     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13843   }
13844   {
13845     BI opval = 1;
13846     SET_H_INSN_PREFIXED_P (opval);
13847     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13848   }
13849 }
13850
13851 #undef FLD
13852 }
13853   NEXT (vpc);
13854
13855   CASE (sem, INSN_ADDO_CD) : /* addo.d [PC+],$Rd,ACR */
13856 {
13857   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13858   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13859 #define FLD(f) abuf->fields.sfmt_bound_cd.f
13860   int UNUSED written = 0;
13861   IADDR UNUSED pc = abuf->addr;
13862   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
13863
13864 {
13865   {
13866     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
13867     CPU (h_prefixreg_pre_v32) = opval;
13868     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13869   }
13870   {
13871     BI opval = 1;
13872     SET_H_INSN_PREFIXED_P (opval);
13873     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13874   }
13875 }
13876
13877 #undef FLD
13878 }
13879   NEXT (vpc);
13880
13881   CASE (sem, INSN_DIP_M) : /* dip [${Rs}${inc}] */
13882 {
13883   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13884   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13885 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
13886   int UNUSED written = 0;
13887   IADDR UNUSED pc = abuf->addr;
13888   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13889
13890 {
13891   SI tmp_tmps;
13892   tmp_tmps = ({   SI tmp_addr;
13893   SI tmp_tmp_mem;
13894   BI tmp_postinc;
13895   tmp_postinc = FLD (f_memmode);
13896 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
13897 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
13898 ; if (NEBI (tmp_postinc, 0)) {
13899 {
13900 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13901   tmp_addr = ADDSI (tmp_addr, 4);
13902 }
13903   {
13904     SI opval = tmp_addr;
13905     SET_H_GR (FLD (f_operand1), opval);
13906     written |= (1 << 5);
13907     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13908   }
13909 }
13910 }
13911 ; tmp_tmp_mem; });
13912   {
13913     SI opval = tmp_tmps;
13914     CPU (h_prefixreg_pre_v32) = opval;
13915     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13916   }
13917   {
13918     BI opval = 1;
13919     SET_H_INSN_PREFIXED_P (opval);
13920     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13921   }
13922 }
13923
13924   abuf->written = written;
13925 #undef FLD
13926 }
13927   NEXT (vpc);
13928
13929   CASE (sem, INSN_DIP_C) : /* dip [PC+] */
13930 {
13931   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13932   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13933 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
13934   int UNUSED written = 0;
13935   IADDR UNUSED pc = abuf->addr;
13936   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
13937
13938 {
13939   {
13940     SI opval = FLD (f_indir_pc__dword);
13941     CPU (h_prefixreg_pre_v32) = opval;
13942     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13943   }
13944   {
13945     BI opval = 1;
13946     SET_H_INSN_PREFIXED_P (opval);
13947     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13948   }
13949 }
13950
13951 #undef FLD
13952 }
13953   NEXT (vpc);
13954
13955   CASE (sem, INSN_ADDI_ACR_B_R) : /* addi-acr.b ${Rs-dfield}.m,${Rd-sfield},ACR */
13956 {
13957   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13958   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13959 #define FLD(f) abuf->fields.sfmt_add_b_r.f
13960   int UNUSED written = 0;
13961   IADDR UNUSED pc = abuf->addr;
13962   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13963
13964 {
13965   {
13966     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 1));
13967     CPU (h_prefixreg_pre_v32) = opval;
13968     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13969   }
13970   {
13971     BI opval = 1;
13972     SET_H_INSN_PREFIXED_P (opval);
13973     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13974   }
13975 }
13976
13977 #undef FLD
13978 }
13979   NEXT (vpc);
13980
13981   CASE (sem, INSN_ADDI_ACR_W_R) : /* addi-acr.w ${Rs-dfield}.m,${Rd-sfield},ACR */
13982 {
13983   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13984   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13985 #define FLD(f) abuf->fields.sfmt_add_b_r.f
13986   int UNUSED written = 0;
13987   IADDR UNUSED pc = abuf->addr;
13988   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13989
13990 {
13991   {
13992     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 2));
13993     CPU (h_prefixreg_pre_v32) = opval;
13994     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13995   }
13996   {
13997     BI opval = 1;
13998     SET_H_INSN_PREFIXED_P (opval);
13999     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
14000   }
14001 }
14002
14003 #undef FLD
14004 }
14005   NEXT (vpc);
14006
14007   CASE (sem, INSN_ADDI_ACR_D_R) : /* addi-acr.d ${Rs-dfield}.m,${Rd-sfield},ACR */
14008 {
14009   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14010   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14011 #define FLD(f) abuf->fields.sfmt_add_b_r.f
14012   int UNUSED written = 0;
14013   IADDR UNUSED pc = abuf->addr;
14014   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14015
14016 {
14017   {
14018     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 4));
14019     CPU (h_prefixreg_pre_v32) = opval;
14020     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
14021   }
14022   {
14023     BI opval = 1;
14024     SET_H_INSN_PREFIXED_P (opval);
14025     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
14026   }
14027 }
14028
14029 #undef FLD
14030 }
14031   NEXT (vpc);
14032
14033   CASE (sem, INSN_BIAP_PC_B_R) : /* biap-pc.b ${Rs-dfield}.m,PC */
14034 {
14035   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14036   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14037 #define FLD(f) abuf->fields.sfmt_addoq.f
14038   int UNUSED written = 0;
14039   IADDR UNUSED pc = abuf->addr;
14040   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14041
14042 {
14043   {
14044     SI opval = ADDSI (ADDSI (pc, 4), MULSI (GET_H_GR (FLD (f_operand2)), 1));
14045     CPU (h_prefixreg_pre_v32) = opval;
14046     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
14047   }
14048   {
14049     BI opval = 1;
14050     SET_H_INSN_PREFIXED_P (opval);
14051     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
14052   }
14053 }
14054
14055 #undef FLD
14056 }
14057   NEXT (vpc);
14058
14059   CASE (sem, INSN_BIAP_PC_W_R) : /* biap-pc.w ${Rs-dfield}.m,PC */
14060 {
14061   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14062   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14063 #define FLD(f) abuf->fields.sfmt_addoq.f
14064   int UNUSED written = 0;
14065   IADDR UNUSED pc = abuf->addr;
14066   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14067
14068 {
14069   {
14070     SI opval = ADDSI (ADDSI (pc, 4), MULSI (GET_H_GR (FLD (f_operand2)), 2));
14071     CPU (h_prefixreg_pre_v32) = opval;
14072     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
14073   }
14074   {
14075     BI opval = 1;
14076     SET_H_INSN_PREFIXED_P (opval);
14077     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
14078   }
14079 }
14080
14081 #undef FLD
14082 }
14083   NEXT (vpc);
14084
14085   CASE (sem, INSN_BIAP_PC_D_R) : /* biap-pc.d ${Rs-dfield}.m,PC */
14086 {
14087   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14088   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14089 #define FLD(f) abuf->fields.sfmt_addoq.f
14090   int UNUSED written = 0;
14091   IADDR UNUSED pc = abuf->addr;
14092   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14093
14094 {
14095   {
14096     SI opval = ADDSI (ADDSI (pc, 4), MULSI (GET_H_GR (FLD (f_operand2)), 4));
14097     CPU (h_prefixreg_pre_v32) = opval;
14098     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
14099   }
14100   {
14101     BI opval = 1;
14102     SET_H_INSN_PREFIXED_P (opval);
14103     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
14104   }
14105 }
14106
14107 #undef FLD
14108 }
14109   NEXT (vpc);
14110
14111
14112     }
14113   ENDSWITCH (sem) /* End of semantic switch.  */
14114
14115   /* At this point `vpc' contains the next insn to execute.  */
14116 }
14117
14118 #undef DEFINE_SWITCH
14119 #endif /* DEFINE_SWITCH */