sim/cris/semcrisv32f-switch.c

   1 /* Simulator instruction semantics for crisv32f.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996-2005 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #ifdef DEFINE_LABELS
  26
  27   /* The labels have the case they have because the enum of insn types
  28      is all uppercase and in the non-stdc case the insn symbol is built
  29      into the enum name.  */
  30
  31   static struct {
  32     int index;
  33     void *label;
  34   } labels[] = {
  35     { CRISV32F_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
  36     { CRISV32F_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
  37     { CRISV32F_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
  38     { CRISV32F_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
  39     { CRISV32F_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
  40     { CRISV32F_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
  41     { CRISV32F_INSN_MOVE_B_R, && case_sem_INSN_MOVE_B_R },
  42     { CRISV32F_INSN_MOVE_W_R, && case_sem_INSN_MOVE_W_R },
  43     { CRISV32F_INSN_MOVE_D_R, && case_sem_INSN_MOVE_D_R },
  44     { CRISV32F_INSN_MOVEQ, && case_sem_INSN_MOVEQ },
  45     { CRISV32F_INSN_MOVS_B_R, && case_sem_INSN_MOVS_B_R },
  46     { CRISV32F_INSN_MOVS_W_R, && case_sem_INSN_MOVS_W_R },
  47     { CRISV32F_INSN_MOVU_B_R, && case_sem_INSN_MOVU_B_R },
  48     { CRISV32F_INSN_MOVU_W_R, && case_sem_INSN_MOVU_W_R },
  49     { CRISV32F_INSN_MOVECBR, && case_sem_INSN_MOVECBR },
  50     { CRISV32F_INSN_MOVECWR, && case_sem_INSN_MOVECWR },
  51     { CRISV32F_INSN_MOVECDR, && case_sem_INSN_MOVECDR },
  52     { CRISV32F_INSN_MOVSCBR, && case_sem_INSN_MOVSCBR },
  53     { CRISV32F_INSN_MOVSCWR, && case_sem_INSN_MOVSCWR },
  54     { CRISV32F_INSN_MOVUCBR, && case_sem_INSN_MOVUCBR },
  55     { CRISV32F_INSN_MOVUCWR, && case_sem_INSN_MOVUCWR },
  56     { CRISV32F_INSN_ADDQ, && case_sem_INSN_ADDQ },
  57     { CRISV32F_INSN_SUBQ, && case_sem_INSN_SUBQ },
  58     { CRISV32F_INSN_CMP_R_B_R, && case_sem_INSN_CMP_R_B_R },
  59     { CRISV32F_INSN_CMP_R_W_R, && case_sem_INSN_CMP_R_W_R },
  60     { CRISV32F_INSN_CMP_R_D_R, && case_sem_INSN_CMP_R_D_R },
  61     { CRISV32F_INSN_CMP_M_B_M, && case_sem_INSN_CMP_M_B_M },
  62     { CRISV32F_INSN_CMP_M_W_M, && case_sem_INSN_CMP_M_W_M },
  63     { CRISV32F_INSN_CMP_M_D_M, && case_sem_INSN_CMP_M_D_M },
  64     { CRISV32F_INSN_CMPCBR, && case_sem_INSN_CMPCBR },
  65     { CRISV32F_INSN_CMPCWR, && case_sem_INSN_CMPCWR },
  66     { CRISV32F_INSN_CMPCDR, && case_sem_INSN_CMPCDR },
  67     { CRISV32F_INSN_CMPQ, && case_sem_INSN_CMPQ },
  68     { CRISV32F_INSN_CMPS_M_B_M, && case_sem_INSN_CMPS_M_B_M },
  69     { CRISV32F_INSN_CMPS_M_W_M, && case_sem_INSN_CMPS_M_W_M },
  70     { CRISV32F_INSN_CMPSCBR, && case_sem_INSN_CMPSCBR },
  71     { CRISV32F_INSN_CMPSCWR, && case_sem_INSN_CMPSCWR },
  72     { CRISV32F_INSN_CMPU_M_B_M, && case_sem_INSN_CMPU_M_B_M },
  73     { CRISV32F_INSN_CMPU_M_W_M, && case_sem_INSN_CMPU_M_W_M },
  74     { CRISV32F_INSN_CMPUCBR, && case_sem_INSN_CMPUCBR },
  75     { CRISV32F_INSN_CMPUCWR, && case_sem_INSN_CMPUCWR },
  76     { CRISV32F_INSN_MOVE_M_B_M, && case_sem_INSN_MOVE_M_B_M },
  77     { CRISV32F_INSN_MOVE_M_W_M, && case_sem_INSN_MOVE_M_W_M },
  78     { CRISV32F_INSN_MOVE_M_D_M, && case_sem_INSN_MOVE_M_D_M },
  79     { CRISV32F_INSN_MOVS_M_B_M, && case_sem_INSN_MOVS_M_B_M },
  80     { CRISV32F_INSN_MOVS_M_W_M, && case_sem_INSN_MOVS_M_W_M },
  81     { CRISV32F_INSN_MOVU_M_B_M, && case_sem_INSN_MOVU_M_B_M },
  82     { CRISV32F_INSN_MOVU_M_W_M, && case_sem_INSN_MOVU_M_W_M },
  83     { CRISV32F_INSN_MOVE_R_SPRV32, && case_sem_INSN_MOVE_R_SPRV32 },
  84     { CRISV32F_INSN_MOVE_SPR_RV32, && case_sem_INSN_MOVE_SPR_RV32 },
  85     { CRISV32F_INSN_MOVE_M_SPRV32, && case_sem_INSN_MOVE_M_SPRV32 },
  86     { CRISV32F_INSN_MOVE_C_SPRV32_P2, && case_sem_INSN_MOVE_C_SPRV32_P2 },
  87     { CRISV32F_INSN_MOVE_C_SPRV32_P3, && case_sem_INSN_MOVE_C_SPRV32_P3 },
  88     { CRISV32F_INSN_MOVE_C_SPRV32_P5, && case_sem_INSN_MOVE_C_SPRV32_P5 },
  89     { CRISV32F_INSN_MOVE_C_SPRV32_P6, && case_sem_INSN_MOVE_C_SPRV32_P6 },
  90     { CRISV32F_INSN_MOVE_C_SPRV32_P7, && case_sem_INSN_MOVE_C_SPRV32_P7 },
  91     { CRISV32F_INSN_MOVE_C_SPRV32_P9, && case_sem_INSN_MOVE_C_SPRV32_P9 },
  92     { CRISV32F_INSN_MOVE_C_SPRV32_P10, && case_sem_INSN_MOVE_C_SPRV32_P10 },
  93     { CRISV32F_INSN_MOVE_C_SPRV32_P11, && case_sem_INSN_MOVE_C_SPRV32_P11 },
  94     { CRISV32F_INSN_MOVE_C_SPRV32_P12, && case_sem_INSN_MOVE_C_SPRV32_P12 },
  95     { CRISV32F_INSN_MOVE_C_SPRV32_P13, && case_sem_INSN_MOVE_C_SPRV32_P13 },
  96     { CRISV32F_INSN_MOVE_C_SPRV32_P14, && case_sem_INSN_MOVE_C_SPRV32_P14 },
  97     { CRISV32F_INSN_MOVE_C_SPRV32_P15, && case_sem_INSN_MOVE_C_SPRV32_P15 },
  98     { CRISV32F_INSN_MOVE_SPR_MV32, && case_sem_INSN_MOVE_SPR_MV32 },
  99     { CRISV32F_INSN_MOVE_SS_R, && case_sem_INSN_MOVE_SS_R },
 100     { CRISV32F_INSN_MOVE_R_SS, && case_sem_INSN_MOVE_R_SS },
 101     { CRISV32F_INSN_MOVEM_R_M_V32, && case_sem_INSN_MOVEM_R_M_V32 },
 102     { CRISV32F_INSN_MOVEM_M_R_V32, && case_sem_INSN_MOVEM_M_R_V32 },
 103     { CRISV32F_INSN_ADD_B_R, && case_sem_INSN_ADD_B_R },
 104     { CRISV32F_INSN_ADD_W_R, && case_sem_INSN_ADD_W_R },
 105     { CRISV32F_INSN_ADD_D_R, && case_sem_INSN_ADD_D_R },
 106     { CRISV32F_INSN_ADD_M_B_M, && case_sem_INSN_ADD_M_B_M },
 107     { CRISV32F_INSN_ADD_M_W_M, && case_sem_INSN_ADD_M_W_M },
 108     { CRISV32F_INSN_ADD_M_D_M, && case_sem_INSN_ADD_M_D_M },
 109     { CRISV32F_INSN_ADDCBR, && case_sem_INSN_ADDCBR },
 110     { CRISV32F_INSN_ADDCWR, && case_sem_INSN_ADDCWR },
 111     { CRISV32F_INSN_ADDCDR, && case_sem_INSN_ADDCDR },
 112     { CRISV32F_INSN_ADDS_B_R, && case_sem_INSN_ADDS_B_R },
 113     { CRISV32F_INSN_ADDS_W_R, && case_sem_INSN_ADDS_W_R },
 114     { CRISV32F_INSN_ADDS_M_B_M, && case_sem_INSN_ADDS_M_B_M },
 115     { CRISV32F_INSN_ADDS_M_W_M, && case_sem_INSN_ADDS_M_W_M },
 116     { CRISV32F_INSN_ADDSCBR, && case_sem_INSN_ADDSCBR },
 117     { CRISV32F_INSN_ADDSCWR, && case_sem_INSN_ADDSCWR },
 118     { CRISV32F_INSN_ADDU_B_R, && case_sem_INSN_ADDU_B_R },
 119     { CRISV32F_INSN_ADDU_W_R, && case_sem_INSN_ADDU_W_R },
 120     { CRISV32F_INSN_ADDU_M_B_M, && case_sem_INSN_ADDU_M_B_M },
 121     { CRISV32F_INSN_ADDU_M_W_M, && case_sem_INSN_ADDU_M_W_M },
 122     { CRISV32F_INSN_ADDUCBR, && case_sem_INSN_ADDUCBR },
 123     { CRISV32F_INSN_ADDUCWR, && case_sem_INSN_ADDUCWR },
 124     { CRISV32F_INSN_SUB_B_R, && case_sem_INSN_SUB_B_R },
 125     { CRISV32F_INSN_SUB_W_R, && case_sem_INSN_SUB_W_R },
 126     { CRISV32F_INSN_SUB_D_R, && case_sem_INSN_SUB_D_R },
 127     { CRISV32F_INSN_SUB_M_B_M, && case_sem_INSN_SUB_M_B_M },
 128     { CRISV32F_INSN_SUB_M_W_M, && case_sem_INSN_SUB_M_W_M },
 129     { CRISV32F_INSN_SUB_M_D_M, && case_sem_INSN_SUB_M_D_M },
 130     { CRISV32F_INSN_SUBCBR, && case_sem_INSN_SUBCBR },
 131     { CRISV32F_INSN_SUBCWR, && case_sem_INSN_SUBCWR },
 132     { CRISV32F_INSN_SUBCDR, && case_sem_INSN_SUBCDR },
 133     { CRISV32F_INSN_SUBS_B_R, && case_sem_INSN_SUBS_B_R },
 134     { CRISV32F_INSN_SUBS_W_R, && case_sem_INSN_SUBS_W_R },
 135     { CRISV32F_INSN_SUBS_M_B_M, && case_sem_INSN_SUBS_M_B_M },
 136     { CRISV32F_INSN_SUBS_M_W_M, && case_sem_INSN_SUBS_M_W_M },
 137     { CRISV32F_INSN_SUBSCBR, && case_sem_INSN_SUBSCBR },
 138     { CRISV32F_INSN_SUBSCWR, && case_sem_INSN_SUBSCWR },
 139     { CRISV32F_INSN_SUBU_B_R, && case_sem_INSN_SUBU_B_R },
 140     { CRISV32F_INSN_SUBU_W_R, && case_sem_INSN_SUBU_W_R },
 141     { CRISV32F_INSN_SUBU_M_B_M, && case_sem_INSN_SUBU_M_B_M },
 142     { CRISV32F_INSN_SUBU_M_W_M, && case_sem_INSN_SUBU_M_W_M },
 143     { CRISV32F_INSN_SUBUCBR, && case_sem_INSN_SUBUCBR },
 144     { CRISV32F_INSN_SUBUCWR, && case_sem_INSN_SUBUCWR },
 145     { CRISV32F_INSN_ADDC_R, && case_sem_INSN_ADDC_R },
 146     { CRISV32F_INSN_ADDC_M, && case_sem_INSN_ADDC_M },
 147     { CRISV32F_INSN_ADDC_C, && case_sem_INSN_ADDC_C },
 148     { CRISV32F_INSN_LAPC_D, && case_sem_INSN_LAPC_D },
 149     { CRISV32F_INSN_LAPCQ, && case_sem_INSN_LAPCQ },
 150     { CRISV32F_INSN_ADDI_B_R, && case_sem_INSN_ADDI_B_R },
 151     { CRISV32F_INSN_ADDI_W_R, && case_sem_INSN_ADDI_W_R },
 152     { CRISV32F_INSN_ADDI_D_R, && case_sem_INSN_ADDI_D_R },
 153     { CRISV32F_INSN_NEG_B_R, && case_sem_INSN_NEG_B_R },
 154     { CRISV32F_INSN_NEG_W_R, && case_sem_INSN_NEG_W_R },
 155     { CRISV32F_INSN_NEG_D_R, && case_sem_INSN_NEG_D_R },
 156     { CRISV32F_INSN_TEST_M_B_M, && case_sem_INSN_TEST_M_B_M },
 157     { CRISV32F_INSN_TEST_M_W_M, && case_sem_INSN_TEST_M_W_M },
 158     { CRISV32F_INSN_TEST_M_D_M, && case_sem_INSN_TEST_M_D_M },
 159     { CRISV32F_INSN_MOVE_R_M_B_M, && case_sem_INSN_MOVE_R_M_B_M },
 160     { CRISV32F_INSN_MOVE_R_M_W_M, && case_sem_INSN_MOVE_R_M_W_M },
 161     { CRISV32F_INSN_MOVE_R_M_D_M, && case_sem_INSN_MOVE_R_M_D_M },
 162     { CRISV32F_INSN_MULS_B, && case_sem_INSN_MULS_B },
 163     { CRISV32F_INSN_MULS_W, && case_sem_INSN_MULS_W },
 164     { CRISV32F_INSN_MULS_D, && case_sem_INSN_MULS_D },
 165     { CRISV32F_INSN_MULU_B, && case_sem_INSN_MULU_B },
 166     { CRISV32F_INSN_MULU_W, && case_sem_INSN_MULU_W },
 167     { CRISV32F_INSN_MULU_D, && case_sem_INSN_MULU_D },
 168     { CRISV32F_INSN_MCP, && case_sem_INSN_MCP },
 169     { CRISV32F_INSN_DSTEP, && case_sem_INSN_DSTEP },
 170     { CRISV32F_INSN_ABS, && case_sem_INSN_ABS },
 171     { CRISV32F_INSN_AND_B_R, && case_sem_INSN_AND_B_R },
 172     { CRISV32F_INSN_AND_W_R, && case_sem_INSN_AND_W_R },
 173     { CRISV32F_INSN_AND_D_R, && case_sem_INSN_AND_D_R },
 174     { CRISV32F_INSN_AND_M_B_M, && case_sem_INSN_AND_M_B_M },
 175     { CRISV32F_INSN_AND_M_W_M, && case_sem_INSN_AND_M_W_M },
 176     { CRISV32F_INSN_AND_M_D_M, && case_sem_INSN_AND_M_D_M },
 177     { CRISV32F_INSN_ANDCBR, && case_sem_INSN_ANDCBR },
 178     { CRISV32F_INSN_ANDCWR, && case_sem_INSN_ANDCWR },
 179     { CRISV32F_INSN_ANDCDR, && case_sem_INSN_ANDCDR },
 180     { CRISV32F_INSN_ANDQ, && case_sem_INSN_ANDQ },
 181     { CRISV32F_INSN_ORR_B_R, && case_sem_INSN_ORR_B_R },
 182     { CRISV32F_INSN_ORR_W_R, && case_sem_INSN_ORR_W_R },
 183     { CRISV32F_INSN_ORR_D_R, && case_sem_INSN_ORR_D_R },
 184     { CRISV32F_INSN_OR_M_B_M, && case_sem_INSN_OR_M_B_M },
 185     { CRISV32F_INSN_OR_M_W_M, && case_sem_INSN_OR_M_W_M },
 186     { CRISV32F_INSN_OR_M_D_M, && case_sem_INSN_OR_M_D_M },
 187     { CRISV32F_INSN_ORCBR, && case_sem_INSN_ORCBR },
 188     { CRISV32F_INSN_ORCWR, && case_sem_INSN_ORCWR },
 189     { CRISV32F_INSN_ORCDR, && case_sem_INSN_ORCDR },
 190     { CRISV32F_INSN_ORQ, && case_sem_INSN_ORQ },
 191     { CRISV32F_INSN_XOR, && case_sem_INSN_XOR },
 192     { CRISV32F_INSN_SWAP, && case_sem_INSN_SWAP },
 193     { CRISV32F_INSN_ASRR_B_R, && case_sem_INSN_ASRR_B_R },
 194     { CRISV32F_INSN_ASRR_W_R, && case_sem_INSN_ASRR_W_R },
 195     { CRISV32F_INSN_ASRR_D_R, && case_sem_INSN_ASRR_D_R },
 196     { CRISV32F_INSN_ASRQ, && case_sem_INSN_ASRQ },
 197     { CRISV32F_INSN_LSRR_B_R, && case_sem_INSN_LSRR_B_R },
 198     { CRISV32F_INSN_LSRR_W_R, && case_sem_INSN_LSRR_W_R },
 199     { CRISV32F_INSN_LSRR_D_R, && case_sem_INSN_LSRR_D_R },
 200     { CRISV32F_INSN_LSRQ, && case_sem_INSN_LSRQ },
 201     { CRISV32F_INSN_LSLR_B_R, && case_sem_INSN_LSLR_B_R },
 202     { CRISV32F_INSN_LSLR_W_R, && case_sem_INSN_LSLR_W_R },
 203     { CRISV32F_INSN_LSLR_D_R, && case_sem_INSN_LSLR_D_R },
 204     { CRISV32F_INSN_LSLQ, && case_sem_INSN_LSLQ },
 205     { CRISV32F_INSN_BTST, && case_sem_INSN_BTST },
 206     { CRISV32F_INSN_BTSTQ, && case_sem_INSN_BTSTQ },
 207     { CRISV32F_INSN_SETF, && case_sem_INSN_SETF },
 208     { CRISV32F_INSN_CLEARF, && case_sem_INSN_CLEARF },
 209     { CRISV32F_INSN_RFE, && case_sem_INSN_RFE },
 210     { CRISV32F_INSN_SFE, && case_sem_INSN_SFE },
 211     { CRISV32F_INSN_RFG, && case_sem_INSN_RFG },
 212     { CRISV32F_INSN_RFN, && case_sem_INSN_RFN },
 213     { CRISV32F_INSN_HALT, && case_sem_INSN_HALT },
 214     { CRISV32F_INSN_BCC_B, && case_sem_INSN_BCC_B },
 215     { CRISV32F_INSN_BA_B, && case_sem_INSN_BA_B },
 216     { CRISV32F_INSN_BCC_W, && case_sem_INSN_BCC_W },
 217     { CRISV32F_INSN_BA_W, && case_sem_INSN_BA_W },
 218     { CRISV32F_INSN_JAS_R, && case_sem_INSN_JAS_R },
 219     { CRISV32F_INSN_JAS_C, && case_sem_INSN_JAS_C },
 220     { CRISV32F_INSN_JUMP_P, && case_sem_INSN_JUMP_P },
 221     { CRISV32F_INSN_BAS_C, && case_sem_INSN_BAS_C },
 222     { CRISV32F_INSN_JASC_R, && case_sem_INSN_JASC_R },
 223     { CRISV32F_INSN_JASC_C, && case_sem_INSN_JASC_C },
 224     { CRISV32F_INSN_BASC_C, && case_sem_INSN_BASC_C },
 225     { CRISV32F_INSN_BREAK, && case_sem_INSN_BREAK },
 226     { CRISV32F_INSN_BOUND_R_B_R, && case_sem_INSN_BOUND_R_B_R },
 227     { CRISV32F_INSN_BOUND_R_W_R, && case_sem_INSN_BOUND_R_W_R },
 228     { CRISV32F_INSN_BOUND_R_D_R, && case_sem_INSN_BOUND_R_D_R },
 229     { CRISV32F_INSN_BOUND_CB, && case_sem_INSN_BOUND_CB },
 230     { CRISV32F_INSN_BOUND_CW, && case_sem_INSN_BOUND_CW },
 231     { CRISV32F_INSN_BOUND_CD, && case_sem_INSN_BOUND_CD },
 232     { CRISV32F_INSN_SCC, && case_sem_INSN_SCC },
 233     { CRISV32F_INSN_LZ, && case_sem_INSN_LZ },
 234     { CRISV32F_INSN_ADDOQ, && case_sem_INSN_ADDOQ },
 235     { CRISV32F_INSN_ADDO_M_B_M, && case_sem_INSN_ADDO_M_B_M },
 236     { CRISV32F_INSN_ADDO_M_W_M, && case_sem_INSN_ADDO_M_W_M },
 237     { CRISV32F_INSN_ADDO_M_D_M, && case_sem_INSN_ADDO_M_D_M },
 238     { CRISV32F_INSN_ADDO_CB, && case_sem_INSN_ADDO_CB },
 239     { CRISV32F_INSN_ADDO_CW, && case_sem_INSN_ADDO_CW },
 240     { CRISV32F_INSN_ADDO_CD, && case_sem_INSN_ADDO_CD },
 241     { CRISV32F_INSN_ADDI_ACR_B_R, && case_sem_INSN_ADDI_ACR_B_R },
 242     { CRISV32F_INSN_ADDI_ACR_W_R, && case_sem_INSN_ADDI_ACR_W_R },
 243     { CRISV32F_INSN_ADDI_ACR_D_R, && case_sem_INSN_ADDI_ACR_D_R },
 244     { CRISV32F_INSN_FIDXI, && case_sem_INSN_FIDXI },
 245     { CRISV32F_INSN_FTAGI, && case_sem_INSN_FTAGI },
 246     { CRISV32F_INSN_FIDXD, && case_sem_INSN_FIDXD },
 247     { CRISV32F_INSN_FTAGD, && case_sem_INSN_FTAGD },
 248     { 0, 0 }
 249   };
 250   int i;
 251
 252   for (i = 0; labels[i].label != 0; ++i)
 253     {
 254 #if FAST_P
 255       CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
 256 #else
 257       CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
 258 #endif
 259     }
 260
 261 #undef DEFINE_LABELS
 262 #endif /* DEFINE_LABELS */
 263
 264 #ifdef DEFINE_SWITCH
 265
 266 /* If hyper-fast [well not unnecessarily slow] execution is selected, turn
 267    off frills like tracing and profiling.  */
 268 /* FIXME: A better way would be to have TRACE_RESULT check for something
 269    that can cause it to be optimized out.  Another way would be to emit
 270    special handlers into the instruction "stream".  */
 271
 272 #if FAST_P
 273 #undef TRACE_RESULT
 274 #define TRACE_RESULT(cpu, abuf, name, type, val)
 275 #endif
 276
 277 #undef GET_ATTR
 278 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 279 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
 280 #else
 281 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
 282 #endif
 283
 284 {
 285
 286 #if WITH_SCACHE_PBB
 287
 288 /* Branch to next handler without going around main loop.  */
 289 #define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
 290 SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 291
 292 #else /* ! WITH_SCACHE_PBB */
 293
 294 #define NEXT(vpc) BREAK (sem)
 295 #ifdef __GNUC__
 296 #if FAST_P
 297   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
 298 #else
 299   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
 300 #endif
 301 #else
 302   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
 303 #endif
 304
 305 #endif /* ! WITH_SCACHE_PBB */
 306
 307     {
 308
 309   CASE (sem, INSN_X_INVALID) : /* --invalid-- */
 310 {
 311   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 312   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 313 #define FLD(f) abuf->fields.fmt_empty.f
 314   int UNUSED written = 0;
 315   IADDR UNUSED pc = abuf->addr;
 316   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 317
 318   {
 319     /* Update the recorded pc in the cpu state struct.
 320        Only necessary for WITH_SCACHE case, but to avoid the
 321        conditional compilation ....  */
 322     SET_H_PC (pc);
 323     /* Virtual insns have zero size.  Overwrite vpc with address of next insn
 324        using the default-insn-bitsize spec.  When executing insns in parallel
 325        we may want to queue the fault and continue execution.  */
 326     vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 327     vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
 328   }
 329
 330 #undef FLD
 331 }
 332   NEXT (vpc);
 333
 334   CASE (sem, INSN_X_AFTER) : /* --after-- */
 335 {
 336   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 337   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 338 #define FLD(f) abuf->fields.fmt_empty.f
 339   int UNUSED written = 0;
 340   IADDR UNUSED pc = abuf->addr;
 341   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 342
 343   {
 344 #if WITH_SCACHE_PBB_CRISV32F
 345     crisv32f_pbb_after (current_cpu, sem_arg);
 346 #endif
 347   }
 348
 349 #undef FLD
 350 }
 351   NEXT (vpc);
 352
 353   CASE (sem, INSN_X_BEFORE) : /* --before-- */
 354 {
 355   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 356   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 357 #define FLD(f) abuf->fields.fmt_empty.f
 358   int UNUSED written = 0;
 359   IADDR UNUSED pc = abuf->addr;
 360   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 361
 362   {
 363 #if WITH_SCACHE_PBB_CRISV32F
 364     crisv32f_pbb_before (current_cpu, sem_arg);
 365 #endif
 366   }
 367
 368 #undef FLD
 369 }
 370   NEXT (vpc);
 371
 372   CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
 373 {
 374   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 375   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 376 #define FLD(f) abuf->fields.fmt_empty.f
 377   int UNUSED written = 0;
 378   IADDR UNUSED pc = abuf->addr;
 379   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 380
 381   {
 382 #if WITH_SCACHE_PBB_CRISV32F
 383 #ifdef DEFINE_SWITCH
 384     vpc = crisv32f_pbb_cti_chain (current_cpu, sem_arg,
 385                                pbb_br_type, pbb_br_npc);
 386     BREAK (sem);
 387 #else
 388     /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
 389     vpc = crisv32f_pbb_cti_chain (current_cpu, sem_arg,
 390                                CPU_PBB_BR_TYPE (current_cpu),
 391                                CPU_PBB_BR_NPC (current_cpu));
 392 #endif
 393 #endif
 394   }
 395
 396 #undef FLD
 397 }
 398   NEXT (vpc);
 399
 400   CASE (sem, INSN_X_CHAIN) : /* --chain-- */
 401 {
 402   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 403   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 404 #define FLD(f) abuf->fields.fmt_empty.f
 405   int UNUSED written = 0;
 406   IADDR UNUSED pc = abuf->addr;
 407   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 408
 409   {
 410 #if WITH_SCACHE_PBB_CRISV32F
 411     vpc = crisv32f_pbb_chain (current_cpu, sem_arg);
 412 #ifdef DEFINE_SWITCH
 413     BREAK (sem);
 414 #endif
 415 #endif
 416   }
 417
 418 #undef FLD
 419 }
 420   NEXT (vpc);
 421
 422   CASE (sem, INSN_X_BEGIN) : /* --begin-- */
 423 {
 424   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 425   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 426 #define FLD(f) abuf->fields.fmt_empty.f
 427   int UNUSED written = 0;
 428   IADDR UNUSED pc = abuf->addr;
 429   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 430
 431   {
 432 #if WITH_SCACHE_PBB_CRISV32F
 433 #if defined DEFINE_SWITCH || defined FAST_P
 434     /* In the switch case FAST_P is a constant, allowing several optimizations
 435        in any called inline functions.  */
 436     vpc = crisv32f_pbb_begin (current_cpu, FAST_P);
 437 #else
 438 #if 0 /* cgen engine can't handle dynamic fast/full switching yet.  */
 439     vpc = crisv32f_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
 440 #else
 441     vpc = crisv32f_pbb_begin (current_cpu, 0);
 442 #endif
 443 #endif
 444 #endif
 445   }
 446
 447 #undef FLD
 448 }
 449   NEXT (vpc);
 450
 451   CASE (sem, INSN_MOVE_B_R) : /* move.b move.m ${Rs},${Rd} */
 452 {
 453   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 454   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 455 #define FLD(f) abuf->fields.sfmt_addc_m.f
 456   int UNUSED written = 0;
 457   IADDR UNUSED pc = abuf->addr;
 458   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 459
 460 {
 461   QI tmp_newval;
 462   tmp_newval = GET_H_GR (FLD (f_operand1));
 463 {
 464   SI tmp_oldregval;
 465   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
 466   {
 467     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
 468     SET_H_GR (FLD (f_operand2), opval);
 469     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 470   }
 471 }
 472 {
 473   {
 474     BI opval = LTQI (tmp_newval, 0);
 475     CPU (h_nbit) = opval;
 476     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 477   }
 478   {
 479     BI opval = ANDIF (EQQI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 480     CPU (h_zbit) = opval;
 481     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 482   }
 483 SET_H_CBIT_MOVE (0);
 484 SET_H_VBIT_MOVE (0);
 485 {
 486   {
 487     BI opval = 0;
 488     CPU (h_xbit) = opval;
 489     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 490   }
 491   {
 492     BI opval = 0;
 493     SET_H_INSN_PREFIXED_P (opval);
 494     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 495   }
 496 }
 497 }
 498 }
 499
 500 #undef FLD
 501 }
 502   NEXT (vpc);
 503
 504   CASE (sem, INSN_MOVE_W_R) : /* move.w move.m ${Rs},${Rd} */
 505 {
 506   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 507   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 508 #define FLD(f) abuf->fields.sfmt_addc_m.f
 509   int UNUSED written = 0;
 510   IADDR UNUSED pc = abuf->addr;
 511   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 512
 513 {
 514   HI tmp_newval;
 515   tmp_newval = GET_H_GR (FLD (f_operand1));
 516 {
 517   SI tmp_oldregval;
 518   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
 519   {
 520     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
 521     SET_H_GR (FLD (f_operand2), opval);
 522     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 523   }
 524 }
 525 {
 526   {
 527     BI opval = LTHI (tmp_newval, 0);
 528     CPU (h_nbit) = opval;
 529     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 530   }
 531   {
 532     BI opval = ANDIF (EQHI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 533     CPU (h_zbit) = opval;
 534     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 535   }
 536 SET_H_CBIT_MOVE (0);
 537 SET_H_VBIT_MOVE (0);
 538 {
 539   {
 540     BI opval = 0;
 541     CPU (h_xbit) = opval;
 542     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 543   }
 544   {
 545     BI opval = 0;
 546     SET_H_INSN_PREFIXED_P (opval);
 547     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 548   }
 549 }
 550 }
 551 }
 552
 553 #undef FLD
 554 }
 555   NEXT (vpc);
 556
 557   CASE (sem, INSN_MOVE_D_R) : /* move.d move.m ${Rs},${Rd} */
 558 {
 559   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 560   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 561 #define FLD(f) abuf->fields.sfmt_addc_m.f
 562   int UNUSED written = 0;
 563   IADDR UNUSED pc = abuf->addr;
 564   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 565
 566 {
 567   SI tmp_newval;
 568   tmp_newval = GET_H_GR (FLD (f_operand1));
 569   {
 570     SI opval = tmp_newval;
 571     SET_H_GR (FLD (f_operand2), opval);
 572     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 573   }
 574 {
 575   {
 576     BI opval = LTSI (tmp_newval, 0);
 577     CPU (h_nbit) = opval;
 578     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 579   }
 580   {
 581     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 582     CPU (h_zbit) = opval;
 583     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 584   }
 585 SET_H_CBIT_MOVE (0);
 586 SET_H_VBIT_MOVE (0);
 587 {
 588   {
 589     BI opval = 0;
 590     CPU (h_xbit) = opval;
 591     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 592   }
 593   {
 594     BI opval = 0;
 595     SET_H_INSN_PREFIXED_P (opval);
 596     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 597   }
 598 }
 599 }
 600 }
 601
 602 #undef FLD
 603 }
 604   NEXT (vpc);
 605
 606   CASE (sem, INSN_MOVEQ) : /* moveq $i,$Rd */
 607 {
 608   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 609   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 610 #define FLD(f) abuf->fields.sfmt_moveq.f
 611   int UNUSED written = 0;
 612   IADDR UNUSED pc = abuf->addr;
 613   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 614
 615 {
 616   SI tmp_newval;
 617   tmp_newval = FLD (f_s6);
 618   {
 619     SI opval = tmp_newval;
 620     SET_H_GR (FLD (f_operand2), opval);
 621     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 622   }
 623 {
 624 SET_H_NBIT_MOVE (LTSI (tmp_newval, 0));
 625 SET_H_ZBIT_MOVE (ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))));
 626 SET_H_CBIT_MOVE (0);
 627 SET_H_VBIT_MOVE (0);
 628 {
 629   {
 630     BI opval = 0;
 631     CPU (h_xbit) = opval;
 632     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 633   }
 634   {
 635     BI opval = 0;
 636     SET_H_INSN_PREFIXED_P (opval);
 637     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 638   }
 639 }
 640 }
 641 }
 642
 643 #undef FLD
 644 }
 645   NEXT (vpc);
 646
 647   CASE (sem, INSN_MOVS_B_R) : /* movs.b movs.m ${Rs},${Rd} */
 648 {
 649   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 650   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 651 #define FLD(f) abuf->fields.sfmt_muls_b.f
 652   int UNUSED written = 0;
 653   IADDR UNUSED pc = abuf->addr;
 654   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 655
 656 {
 657   QI tmp_newval;
 658   tmp_newval = GET_H_GR (FLD (f_operand1));
 659   {
 660     SI opval = EXTQISI (tmp_newval);
 661     SET_H_GR (FLD (f_operand2), opval);
 662     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 663   }
 664 {
 665   {
 666     BI opval = LTSI (tmp_newval, 0);
 667     CPU (h_nbit) = opval;
 668     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 669   }
 670   {
 671     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 672     CPU (h_zbit) = opval;
 673     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 674   }
 675 SET_H_CBIT_MOVE (0);
 676 SET_H_VBIT_MOVE (0);
 677 {
 678   {
 679     BI opval = 0;
 680     CPU (h_xbit) = opval;
 681     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 682   }
 683   {
 684     BI opval = 0;
 685     SET_H_INSN_PREFIXED_P (opval);
 686     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 687   }
 688 }
 689 }
 690 }
 691
 692 #undef FLD
 693 }
 694   NEXT (vpc);
 695
 696   CASE (sem, INSN_MOVS_W_R) : /* movs.w movs.m ${Rs},${Rd} */
 697 {
 698   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 699   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 700 #define FLD(f) abuf->fields.sfmt_muls_b.f
 701   int UNUSED written = 0;
 702   IADDR UNUSED pc = abuf->addr;
 703   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 704
 705 {
 706   HI tmp_newval;
 707   tmp_newval = GET_H_GR (FLD (f_operand1));
 708   {
 709     SI opval = EXTHISI (tmp_newval);
 710     SET_H_GR (FLD (f_operand2), opval);
 711     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 712   }
 713 {
 714   {
 715     BI opval = LTSI (tmp_newval, 0);
 716     CPU (h_nbit) = opval;
 717     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 718   }
 719   {
 720     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 721     CPU (h_zbit) = opval;
 722     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 723   }
 724 SET_H_CBIT_MOVE (0);
 725 SET_H_VBIT_MOVE (0);
 726 {
 727   {
 728     BI opval = 0;
 729     CPU (h_xbit) = opval;
 730     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 731   }
 732   {
 733     BI opval = 0;
 734     SET_H_INSN_PREFIXED_P (opval);
 735     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 736   }
 737 }
 738 }
 739 }
 740
 741 #undef FLD
 742 }
 743   NEXT (vpc);
 744
 745   CASE (sem, INSN_MOVU_B_R) : /* movu.b movu.m ${Rs},${Rd} */
 746 {
 747   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 748   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 749 #define FLD(f) abuf->fields.sfmt_muls_b.f
 750   int UNUSED written = 0;
 751   IADDR UNUSED pc = abuf->addr;
 752   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 753
 754 {
 755   QI tmp_newval;
 756   tmp_newval = GET_H_GR (FLD (f_operand1));
 757   {
 758     SI opval = ZEXTQISI (tmp_newval);
 759     SET_H_GR (FLD (f_operand2), opval);
 760     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 761   }
 762 {
 763   {
 764     BI opval = LTSI (tmp_newval, 0);
 765     CPU (h_nbit) = opval;
 766     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 767   }
 768   {
 769     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 770     CPU (h_zbit) = opval;
 771     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 772   }
 773 SET_H_CBIT_MOVE (0);
 774 SET_H_VBIT_MOVE (0);
 775 {
 776   {
 777     BI opval = 0;
 778     CPU (h_xbit) = opval;
 779     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 780   }
 781   {
 782     BI opval = 0;
 783     SET_H_INSN_PREFIXED_P (opval);
 784     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 785   }
 786 }
 787 }
 788 }
 789
 790 #undef FLD
 791 }
 792   NEXT (vpc);
 793
 794   CASE (sem, INSN_MOVU_W_R) : /* movu.w movu.m ${Rs},${Rd} */
 795 {
 796   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 797   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 798 #define FLD(f) abuf->fields.sfmt_muls_b.f
 799   int UNUSED written = 0;
 800   IADDR UNUSED pc = abuf->addr;
 801   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 802
 803 {
 804   HI tmp_newval;
 805   tmp_newval = GET_H_GR (FLD (f_operand1));
 806   {
 807     SI opval = ZEXTHISI (tmp_newval);
 808     SET_H_GR (FLD (f_operand2), opval);
 809     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 810   }
 811 {
 812   {
 813     BI opval = LTSI (tmp_newval, 0);
 814     CPU (h_nbit) = opval;
 815     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 816   }
 817   {
 818     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 819     CPU (h_zbit) = opval;
 820     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 821   }
 822 SET_H_CBIT_MOVE (0);
 823 SET_H_VBIT_MOVE (0);
 824 {
 825   {
 826     BI opval = 0;
 827     CPU (h_xbit) = opval;
 828     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 829   }
 830   {
 831     BI opval = 0;
 832     SET_H_INSN_PREFIXED_P (opval);
 833     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 834   }
 835 }
 836 }
 837 }
 838
 839 #undef FLD
 840 }
 841   NEXT (vpc);
 842
 843   CASE (sem, INSN_MOVECBR) : /* move.b ${sconst8},${Rd} */
 844 {
 845   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 846   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 847 #define FLD(f) abuf->fields.sfmt_addcbr.f
 848   int UNUSED written = 0;
 849   IADDR UNUSED pc = abuf->addr;
 850   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 851
 852 {
 853   QI tmp_newval;
 854   tmp_newval = FLD (f_indir_pc__byte);
 855 {
 856   SI tmp_oldregval;
 857   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
 858   {
 859     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
 860     SET_H_GR (FLD (f_operand2), opval);
 861     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 862   }
 863 }
 864 {
 865   {
 866     BI opval = LTQI (tmp_newval, 0);
 867     CPU (h_nbit) = opval;
 868     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 869   }
 870   {
 871     BI opval = ANDIF (EQQI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 872     CPU (h_zbit) = opval;
 873     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 874   }
 875 SET_H_CBIT_MOVE (0);
 876 SET_H_VBIT_MOVE (0);
 877 {
 878   {
 879     BI opval = 0;
 880     CPU (h_xbit) = opval;
 881     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 882   }
 883   {
 884     BI opval = 0;
 885     SET_H_INSN_PREFIXED_P (opval);
 886     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 887   }
 888 }
 889 }
 890 }
 891
 892 #undef FLD
 893 }
 894   NEXT (vpc);
 895
 896   CASE (sem, INSN_MOVECWR) : /* move.w ${sconst16},${Rd} */
 897 {
 898   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 899   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 900 #define FLD(f) abuf->fields.sfmt_addcwr.f
 901   int UNUSED written = 0;
 902   IADDR UNUSED pc = abuf->addr;
 903   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 904
 905 {
 906   HI tmp_newval;
 907   tmp_newval = FLD (f_indir_pc__word);
 908 {
 909   SI tmp_oldregval;
 910   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
 911   {
 912     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
 913     SET_H_GR (FLD (f_operand2), opval);
 914     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 915   }
 916 }
 917 {
 918   {
 919     BI opval = LTHI (tmp_newval, 0);
 920     CPU (h_nbit) = opval;
 921     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 922   }
 923   {
 924     BI opval = ANDIF (EQHI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 925     CPU (h_zbit) = opval;
 926     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 927   }
 928 SET_H_CBIT_MOVE (0);
 929 SET_H_VBIT_MOVE (0);
 930 {
 931   {
 932     BI opval = 0;
 933     CPU (h_xbit) = opval;
 934     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 935   }
 936   {
 937     BI opval = 0;
 938     SET_H_INSN_PREFIXED_P (opval);
 939     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 940   }
 941 }
 942 }
 943 }
 944
 945 #undef FLD
 946 }
 947   NEXT (vpc);
 948
 949   CASE (sem, INSN_MOVECDR) : /* move.d ${const32},${Rd} */
 950 {
 951   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 952   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 953 #define FLD(f) abuf->fields.sfmt_bound_cd.f
 954   int UNUSED written = 0;
 955   IADDR UNUSED pc = abuf->addr;
 956   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
 957
 958 {
 959   SI tmp_newval;
 960   tmp_newval = FLD (f_indir_pc__dword);
 961   {
 962     SI opval = tmp_newval;
 963     SET_H_GR (FLD (f_operand2), opval);
 964     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 965   }
 966 {
 967   {
 968     BI opval = LTSI (tmp_newval, 0);
 969     CPU (h_nbit) = opval;
 970     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 971   }
 972   {
 973     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 974     CPU (h_zbit) = opval;
 975     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 976   }
 977 SET_H_CBIT_MOVE (0);
 978 SET_H_VBIT_MOVE (0);
 979 {
 980   {
 981     BI opval = 0;
 982     CPU (h_xbit) = opval;
 983     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 984   }
 985   {
 986     BI opval = 0;
 987     SET_H_INSN_PREFIXED_P (opval);
 988     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 989   }
 990 }
 991 }
 992 }
 993
 994 #undef FLD
 995 }
 996   NEXT (vpc);
 997
 998   CASE (sem, INSN_MOVSCBR) : /* movs.b ${sconst8},${Rd} */
 999 {
1000   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1001   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1002 #define FLD(f) abuf->fields.sfmt_bound_cb.f
1003   int UNUSED written = 0;
1004   IADDR UNUSED pc = abuf->addr;
1005   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1006
1007 {
1008   SI tmp_newval;
1009   tmp_newval = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
1010   {
1011     SI opval = tmp_newval;
1012     SET_H_GR (FLD (f_operand2), opval);
1013     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1014   }
1015 {
1016   {
1017     BI opval = LTSI (tmp_newval, 0);
1018     CPU (h_nbit) = opval;
1019     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1020   }
1021   {
1022     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1023     CPU (h_zbit) = opval;
1024     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1025   }
1026 SET_H_CBIT_MOVE (0);
1027 SET_H_VBIT_MOVE (0);
1028 {
1029   {
1030     BI opval = 0;
1031     CPU (h_xbit) = opval;
1032     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1033   }
1034   {
1035     BI opval = 0;
1036     SET_H_INSN_PREFIXED_P (opval);
1037     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1038   }
1039 }
1040 }
1041 }
1042
1043 #undef FLD
1044 }
1045   NEXT (vpc);
1046
1047   CASE (sem, INSN_MOVSCWR) : /* movs.w ${sconst16},${Rd} */
1048 {
1049   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1050   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1051 #define FLD(f) abuf->fields.sfmt_bound_cw.f
1052   int UNUSED written = 0;
1053   IADDR UNUSED pc = abuf->addr;
1054   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1055
1056 {
1057   SI tmp_newval;
1058   tmp_newval = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
1059   {
1060     SI opval = tmp_newval;
1061     SET_H_GR (FLD (f_operand2), opval);
1062     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1063   }
1064 {
1065   {
1066     BI opval = LTSI (tmp_newval, 0);
1067     CPU (h_nbit) = opval;
1068     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1069   }
1070   {
1071     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1072     CPU (h_zbit) = opval;
1073     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1074   }
1075 SET_H_CBIT_MOVE (0);
1076 SET_H_VBIT_MOVE (0);
1077 {
1078   {
1079     BI opval = 0;
1080     CPU (h_xbit) = opval;
1081     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1082   }
1083   {
1084     BI opval = 0;
1085     SET_H_INSN_PREFIXED_P (opval);
1086     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1087   }
1088 }
1089 }
1090 }
1091
1092 #undef FLD
1093 }
1094   NEXT (vpc);
1095
1096   CASE (sem, INSN_MOVUCBR) : /* movu.b ${uconst8},${Rd} */
1097 {
1098   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1099   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1100 #define FLD(f) abuf->fields.sfmt_bound_cb.f
1101   int UNUSED written = 0;
1102   IADDR UNUSED pc = abuf->addr;
1103   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1104
1105 {
1106   SI tmp_newval;
1107   tmp_newval = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
1108   {
1109     SI opval = tmp_newval;
1110     SET_H_GR (FLD (f_operand2), opval);
1111     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1112   }
1113 {
1114   {
1115     BI opval = LTSI (tmp_newval, 0);
1116     CPU (h_nbit) = opval;
1117     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1118   }
1119   {
1120     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1121     CPU (h_zbit) = opval;
1122     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1123   }
1124 SET_H_CBIT_MOVE (0);
1125 SET_H_VBIT_MOVE (0);
1126 {
1127   {
1128     BI opval = 0;
1129     CPU (h_xbit) = opval;
1130     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1131   }
1132   {
1133     BI opval = 0;
1134     SET_H_INSN_PREFIXED_P (opval);
1135     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1136   }
1137 }
1138 }
1139 }
1140
1141 #undef FLD
1142 }
1143   NEXT (vpc);
1144
1145   CASE (sem, INSN_MOVUCWR) : /* movu.w ${uconst16},${Rd} */
1146 {
1147   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1148   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1149 #define FLD(f) abuf->fields.sfmt_bound_cw.f
1150   int UNUSED written = 0;
1151   IADDR UNUSED pc = abuf->addr;
1152   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1153
1154 {
1155   SI tmp_newval;
1156   tmp_newval = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
1157   {
1158     SI opval = tmp_newval;
1159     SET_H_GR (FLD (f_operand2), opval);
1160     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1161   }
1162 {
1163   {
1164     BI opval = LTSI (tmp_newval, 0);
1165     CPU (h_nbit) = opval;
1166     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1167   }
1168   {
1169     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1170     CPU (h_zbit) = opval;
1171     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1172   }
1173 SET_H_CBIT_MOVE (0);
1174 SET_H_VBIT_MOVE (0);
1175 {
1176   {
1177     BI opval = 0;
1178     CPU (h_xbit) = opval;
1179     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1180   }
1181   {
1182     BI opval = 0;
1183     SET_H_INSN_PREFIXED_P (opval);
1184     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1185   }
1186 }
1187 }
1188 }
1189
1190 #undef FLD
1191 }
1192   NEXT (vpc);
1193
1194   CASE (sem, INSN_ADDQ) : /* addq $j,$Rd */
1195 {
1196   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1197   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1198 #define FLD(f) abuf->fields.sfmt_addq.f
1199   int UNUSED written = 0;
1200   IADDR UNUSED pc = abuf->addr;
1201   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1202
1203 {
1204   SI tmp_tmpopd;
1205   SI tmp_tmpops;
1206   BI tmp_carry;
1207   SI tmp_newval;
1208   tmp_tmpops = FLD (f_u6);
1209   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1210   tmp_carry = CPU (h_cbit);
1211   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1212   {
1213     SI opval = tmp_newval;
1214     SET_H_GR (FLD (f_operand2), opval);
1215     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1216   }
1217 {
1218   {
1219     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
1220     CPU (h_cbit) = opval;
1221     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1222   }
1223   {
1224     BI opval = LTSI (tmp_newval, 0);
1225     CPU (h_nbit) = opval;
1226     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1227   }
1228   {
1229     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1230     CPU (h_zbit) = opval;
1231     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1232   }
1233   {
1234     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1235     CPU (h_vbit) = opval;
1236     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1237   }
1238 {
1239   {
1240     BI opval = 0;
1241     CPU (h_xbit) = opval;
1242     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1243   }
1244   {
1245     BI opval = 0;
1246     SET_H_INSN_PREFIXED_P (opval);
1247     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1248   }
1249 }
1250 }
1251 }
1252
1253 #undef FLD
1254 }
1255   NEXT (vpc);
1256
1257   CASE (sem, INSN_SUBQ) : /* subq $j,$Rd */
1258 {
1259   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1260   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1261 #define FLD(f) abuf->fields.sfmt_addq.f
1262   int UNUSED written = 0;
1263   IADDR UNUSED pc = abuf->addr;
1264   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1265
1266 {
1267   SI tmp_tmpopd;
1268   SI tmp_tmpops;
1269   BI tmp_carry;
1270   SI tmp_newval;
1271   tmp_tmpops = FLD (f_u6);
1272   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1273   tmp_carry = CPU (h_cbit);
1274   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1275   {
1276     SI opval = tmp_newval;
1277     SET_H_GR (FLD (f_operand2), opval);
1278     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1279   }
1280 {
1281   {
1282     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1283     CPU (h_cbit) = opval;
1284     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1285   }
1286   {
1287     BI opval = LTSI (tmp_newval, 0);
1288     CPU (h_nbit) = opval;
1289     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1290   }
1291   {
1292     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1293     CPU (h_zbit) = opval;
1294     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1295   }
1296   {
1297     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1298     CPU (h_vbit) = opval;
1299     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1300   }
1301 {
1302   {
1303     BI opval = 0;
1304     CPU (h_xbit) = opval;
1305     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1306   }
1307   {
1308     BI opval = 0;
1309     SET_H_INSN_PREFIXED_P (opval);
1310     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1311   }
1312 }
1313 }
1314 }
1315
1316 #undef FLD
1317 }
1318   NEXT (vpc);
1319
1320   CASE (sem, INSN_CMP_R_B_R) : /* cmp-r.b $Rs,$Rd */
1321 {
1322   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1323   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1324 #define FLD(f) abuf->fields.sfmt_muls_b.f
1325   int UNUSED written = 0;
1326   IADDR UNUSED pc = abuf->addr;
1327   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1328
1329 {
1330   QI tmp_tmpopd;
1331   QI tmp_tmpops;
1332   BI tmp_carry;
1333   QI tmp_newval;
1334   tmp_tmpops = GET_H_GR (FLD (f_operand1));
1335   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1336   tmp_carry = CPU (h_cbit);
1337   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1338 ((void) 0); /*nop*/
1339 {
1340   {
1341     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
1342     CPU (h_cbit) = opval;
1343     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1344   }
1345   {
1346     BI opval = LTQI (tmp_newval, 0);
1347     CPU (h_nbit) = opval;
1348     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1349   }
1350   {
1351     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1352     CPU (h_zbit) = opval;
1353     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1354   }
1355   {
1356     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
1357     CPU (h_vbit) = opval;
1358     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1359   }
1360 {
1361   {
1362     BI opval = 0;
1363     CPU (h_xbit) = opval;
1364     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1365   }
1366   {
1367     BI opval = 0;
1368     SET_H_INSN_PREFIXED_P (opval);
1369     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1370   }
1371 }
1372 }
1373 }
1374
1375 #undef FLD
1376 }
1377   NEXT (vpc);
1378
1379   CASE (sem, INSN_CMP_R_W_R) : /* cmp-r.w $Rs,$Rd */
1380 {
1381   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1382   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1383 #define FLD(f) abuf->fields.sfmt_muls_b.f
1384   int UNUSED written = 0;
1385   IADDR UNUSED pc = abuf->addr;
1386   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1387
1388 {
1389   HI tmp_tmpopd;
1390   HI tmp_tmpops;
1391   BI tmp_carry;
1392   HI tmp_newval;
1393   tmp_tmpops = GET_H_GR (FLD (f_operand1));
1394   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1395   tmp_carry = CPU (h_cbit);
1396   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1397 ((void) 0); /*nop*/
1398 {
1399   {
1400     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
1401     CPU (h_cbit) = opval;
1402     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1403   }
1404   {
1405     BI opval = LTHI (tmp_newval, 0);
1406     CPU (h_nbit) = opval;
1407     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1408   }
1409   {
1410     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1411     CPU (h_zbit) = opval;
1412     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1413   }
1414   {
1415     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
1416     CPU (h_vbit) = opval;
1417     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1418   }
1419 {
1420   {
1421     BI opval = 0;
1422     CPU (h_xbit) = opval;
1423     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1424   }
1425   {
1426     BI opval = 0;
1427     SET_H_INSN_PREFIXED_P (opval);
1428     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1429   }
1430 }
1431 }
1432 }
1433
1434 #undef FLD
1435 }
1436   NEXT (vpc);
1437
1438   CASE (sem, INSN_CMP_R_D_R) : /* cmp-r.d $Rs,$Rd */
1439 {
1440   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1441   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1442 #define FLD(f) abuf->fields.sfmt_muls_b.f
1443   int UNUSED written = 0;
1444   IADDR UNUSED pc = abuf->addr;
1445   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1446
1447 {
1448   SI tmp_tmpopd;
1449   SI tmp_tmpops;
1450   BI tmp_carry;
1451   SI tmp_newval;
1452   tmp_tmpops = GET_H_GR (FLD (f_operand1));
1453   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1454   tmp_carry = CPU (h_cbit);
1455   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1456 ((void) 0); /*nop*/
1457 {
1458   {
1459     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1460     CPU (h_cbit) = opval;
1461     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1462   }
1463   {
1464     BI opval = LTSI (tmp_newval, 0);
1465     CPU (h_nbit) = opval;
1466     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1467   }
1468   {
1469     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1470     CPU (h_zbit) = opval;
1471     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1472   }
1473   {
1474     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1475     CPU (h_vbit) = opval;
1476     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1477   }
1478 {
1479   {
1480     BI opval = 0;
1481     CPU (h_xbit) = opval;
1482     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1483   }
1484   {
1485     BI opval = 0;
1486     SET_H_INSN_PREFIXED_P (opval);
1487     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1488   }
1489 }
1490 }
1491 }
1492
1493 #undef FLD
1494 }
1495   NEXT (vpc);
1496
1497   CASE (sem, INSN_CMP_M_B_M) : /* cmp-m.b [${Rs}${inc}],${Rd} */
1498 {
1499   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1500   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1501 #define FLD(f) abuf->fields.sfmt_addc_m.f
1502   int UNUSED written = 0;
1503   IADDR UNUSED pc = abuf->addr;
1504   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1505
1506 {
1507   QI tmp_tmpopd;
1508   QI tmp_tmpops;
1509   BI tmp_carry;
1510   QI tmp_newval;
1511   tmp_tmpops = ({   SI tmp_addr;
1512   QI tmp_tmp_mem;
1513   BI tmp_postinc;
1514   tmp_postinc = FLD (f_memmode);
1515 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
1516 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
1517 ; if (NEBI (tmp_postinc, 0)) {
1518 {
1519 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
1520   tmp_addr = ADDSI (tmp_addr, 1);
1521 }
1522   {
1523     SI opval = tmp_addr;
1524     SET_H_GR (FLD (f_operand1), opval);
1525     written |= (1 << 9);
1526     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1527   }
1528 }
1529 }
1530 ; tmp_tmp_mem; });
1531   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1532   tmp_carry = CPU (h_cbit);
1533   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1534 ((void) 0); /*nop*/
1535 {
1536   {
1537     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
1538     CPU (h_cbit) = opval;
1539     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1540   }
1541   {
1542     BI opval = LTQI (tmp_newval, 0);
1543     CPU (h_nbit) = opval;
1544     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1545   }
1546   {
1547     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1548     CPU (h_zbit) = opval;
1549     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1550   }
1551   {
1552     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
1553     CPU (h_vbit) = opval;
1554     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1555   }
1556 {
1557   {
1558     BI opval = 0;
1559     CPU (h_xbit) = opval;
1560     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1561   }
1562   {
1563     BI opval = 0;
1564     SET_H_INSN_PREFIXED_P (opval);
1565     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1566   }
1567 }
1568 }
1569 }
1570
1571   abuf->written = written;
1572 #undef FLD
1573 }
1574   NEXT (vpc);
1575
1576   CASE (sem, INSN_CMP_M_W_M) : /* cmp-m.w [${Rs}${inc}],${Rd} */
1577 {
1578   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1579   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1580 #define FLD(f) abuf->fields.sfmt_addc_m.f
1581   int UNUSED written = 0;
1582   IADDR UNUSED pc = abuf->addr;
1583   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1584
1585 {
1586   HI tmp_tmpopd;
1587   HI tmp_tmpops;
1588   BI tmp_carry;
1589   HI tmp_newval;
1590   tmp_tmpops = ({   SI tmp_addr;
1591   HI tmp_tmp_mem;
1592   BI tmp_postinc;
1593   tmp_postinc = FLD (f_memmode);
1594 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
1595 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
1596 ; if (NEBI (tmp_postinc, 0)) {
1597 {
1598 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
1599   tmp_addr = ADDSI (tmp_addr, 2);
1600 }
1601   {
1602     SI opval = tmp_addr;
1603     SET_H_GR (FLD (f_operand1), opval);
1604     written |= (1 << 9);
1605     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1606   }
1607 }
1608 }
1609 ; tmp_tmp_mem; });
1610   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1611   tmp_carry = CPU (h_cbit);
1612   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1613 ((void) 0); /*nop*/
1614 {
1615   {
1616     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
1617     CPU (h_cbit) = opval;
1618     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1619   }
1620   {
1621     BI opval = LTHI (tmp_newval, 0);
1622     CPU (h_nbit) = opval;
1623     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1624   }
1625   {
1626     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1627     CPU (h_zbit) = opval;
1628     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1629   }
1630   {
1631     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
1632     CPU (h_vbit) = opval;
1633     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1634   }
1635 {
1636   {
1637     BI opval = 0;
1638     CPU (h_xbit) = opval;
1639     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1640   }
1641   {
1642     BI opval = 0;
1643     SET_H_INSN_PREFIXED_P (opval);
1644     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1645   }
1646 }
1647 }
1648 }
1649
1650   abuf->written = written;
1651 #undef FLD
1652 }
1653   NEXT (vpc);
1654
1655   CASE (sem, INSN_CMP_M_D_M) : /* cmp-m.d [${Rs}${inc}],${Rd} */
1656 {
1657   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1658   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1659 #define FLD(f) abuf->fields.sfmt_addc_m.f
1660   int UNUSED written = 0;
1661   IADDR UNUSED pc = abuf->addr;
1662   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1663
1664 {
1665   SI tmp_tmpopd;
1666   SI tmp_tmpops;
1667   BI tmp_carry;
1668   SI tmp_newval;
1669   tmp_tmpops = ({   SI tmp_addr;
1670   SI tmp_tmp_mem;
1671   BI tmp_postinc;
1672   tmp_postinc = FLD (f_memmode);
1673 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
1674 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
1675 ; if (NEBI (tmp_postinc, 0)) {
1676 {
1677 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
1678   tmp_addr = ADDSI (tmp_addr, 4);
1679 }
1680   {
1681     SI opval = tmp_addr;
1682     SET_H_GR (FLD (f_operand1), opval);
1683     written |= (1 << 9);
1684     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1685   }
1686 }
1687 }
1688 ; tmp_tmp_mem; });
1689   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1690   tmp_carry = CPU (h_cbit);
1691   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1692 ((void) 0); /*nop*/
1693 {
1694   {
1695     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1696     CPU (h_cbit) = opval;
1697     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1698   }
1699   {
1700     BI opval = LTSI (tmp_newval, 0);
1701     CPU (h_nbit) = opval;
1702     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1703   }
1704   {
1705     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1706     CPU (h_zbit) = opval;
1707     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1708   }
1709   {
1710     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1711     CPU (h_vbit) = opval;
1712     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1713   }
1714 {
1715   {
1716     BI opval = 0;
1717     CPU (h_xbit) = opval;
1718     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1719   }
1720   {
1721     BI opval = 0;
1722     SET_H_INSN_PREFIXED_P (opval);
1723     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1724   }
1725 }
1726 }
1727 }
1728
1729   abuf->written = written;
1730 #undef FLD
1731 }
1732   NEXT (vpc);
1733
1734   CASE (sem, INSN_CMPCBR) : /* cmp.b $sconst8,$Rd */
1735 {
1736   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1737   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1738 #define FLD(f) abuf->fields.sfmt_bound_cb.f
1739   int UNUSED written = 0;
1740   IADDR UNUSED pc = abuf->addr;
1741   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1742
1743 {
1744   QI tmp_tmpopd;
1745   QI tmp_tmpops;
1746   BI tmp_carry;
1747   QI tmp_newval;
1748   tmp_tmpops = TRUNCSIQI (FLD (f_indir_pc__byte));
1749   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1750   tmp_carry = CPU (h_cbit);
1751   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1752 ((void) 0); /*nop*/
1753 {
1754   {
1755     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
1756     CPU (h_cbit) = opval;
1757     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1758   }
1759   {
1760     BI opval = LTQI (tmp_newval, 0);
1761     CPU (h_nbit) = opval;
1762     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1763   }
1764   {
1765     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1766     CPU (h_zbit) = opval;
1767     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1768   }
1769   {
1770     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
1771     CPU (h_vbit) = opval;
1772     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1773   }
1774 {
1775   {
1776     BI opval = 0;
1777     CPU (h_xbit) = opval;
1778     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1779   }
1780   {
1781     BI opval = 0;
1782     SET_H_INSN_PREFIXED_P (opval);
1783     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1784   }
1785 }
1786 }
1787 }
1788
1789 #undef FLD
1790 }
1791   NEXT (vpc);
1792
1793   CASE (sem, INSN_CMPCWR) : /* cmp.w $sconst16,$Rd */
1794 {
1795   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1796   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1797 #define FLD(f) abuf->fields.sfmt_bound_cw.f
1798   int UNUSED written = 0;
1799   IADDR UNUSED pc = abuf->addr;
1800   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1801
1802 {
1803   HI tmp_tmpopd;
1804   HI tmp_tmpops;
1805   BI tmp_carry;
1806   HI tmp_newval;
1807   tmp_tmpops = TRUNCSIHI (FLD (f_indir_pc__word));
1808   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1809   tmp_carry = CPU (h_cbit);
1810   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1811 ((void) 0); /*nop*/
1812 {
1813   {
1814     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
1815     CPU (h_cbit) = opval;
1816     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1817   }
1818   {
1819     BI opval = LTHI (tmp_newval, 0);
1820     CPU (h_nbit) = opval;
1821     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1822   }
1823   {
1824     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1825     CPU (h_zbit) = opval;
1826     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1827   }
1828   {
1829     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
1830     CPU (h_vbit) = opval;
1831     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1832   }
1833 {
1834   {
1835     BI opval = 0;
1836     CPU (h_xbit) = opval;
1837     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1838   }
1839   {
1840     BI opval = 0;
1841     SET_H_INSN_PREFIXED_P (opval);
1842     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1843   }
1844 }
1845 }
1846 }
1847
1848 #undef FLD
1849 }
1850   NEXT (vpc);
1851
1852   CASE (sem, INSN_CMPCDR) : /* cmp.d $const32,$Rd */
1853 {
1854   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1855   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1856 #define FLD(f) abuf->fields.sfmt_bound_cd.f
1857   int UNUSED written = 0;
1858   IADDR UNUSED pc = abuf->addr;
1859   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
1860
1861 {
1862   SI tmp_tmpopd;
1863   SI tmp_tmpops;
1864   BI tmp_carry;
1865   SI tmp_newval;
1866   tmp_tmpops = FLD (f_indir_pc__dword);
1867   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1868   tmp_carry = CPU (h_cbit);
1869   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1870 ((void) 0); /*nop*/
1871 {
1872   {
1873     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1874     CPU (h_cbit) = opval;
1875     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1876   }
1877   {
1878     BI opval = LTSI (tmp_newval, 0);
1879     CPU (h_nbit) = opval;
1880     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1881   }
1882   {
1883     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1884     CPU (h_zbit) = opval;
1885     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1886   }
1887   {
1888     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1889     CPU (h_vbit) = opval;
1890     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1891   }
1892 {
1893   {
1894     BI opval = 0;
1895     CPU (h_xbit) = opval;
1896     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1897   }
1898   {
1899     BI opval = 0;
1900     SET_H_INSN_PREFIXED_P (opval);
1901     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1902   }
1903 }
1904 }
1905 }
1906
1907 #undef FLD
1908 }
1909   NEXT (vpc);
1910
1911   CASE (sem, INSN_CMPQ) : /* cmpq $i,$Rd */
1912 {
1913   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1914   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1915 #define FLD(f) abuf->fields.sfmt_andq.f
1916   int UNUSED written = 0;
1917   IADDR UNUSED pc = abuf->addr;
1918   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1919
1920 {
1921   SI tmp_tmpopd;
1922   SI tmp_tmpops;
1923   BI tmp_carry;
1924   SI tmp_newval;
1925   tmp_tmpops = FLD (f_s6);
1926   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1927   tmp_carry = CPU (h_cbit);
1928   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1929 ((void) 0); /*nop*/
1930 {
1931   {
1932     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1933     CPU (h_cbit) = opval;
1934     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1935   }
1936   {
1937     BI opval = LTSI (tmp_newval, 0);
1938     CPU (h_nbit) = opval;
1939     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1940   }
1941   {
1942     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1943     CPU (h_zbit) = opval;
1944     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1945   }
1946   {
1947     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1948     CPU (h_vbit) = opval;
1949     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1950   }
1951 {
1952   {
1953     BI opval = 0;
1954     CPU (h_xbit) = opval;
1955     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1956   }
1957   {
1958     BI opval = 0;
1959     SET_H_INSN_PREFIXED_P (opval);
1960     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1961   }
1962 }
1963 }
1964 }
1965
1966 #undef FLD
1967 }
1968   NEXT (vpc);
1969
1970   CASE (sem, INSN_CMPS_M_B_M) : /* cmps-m.b [${Rs}${inc}],$Rd */
1971 {
1972   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1973   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1974 #define FLD(f) abuf->fields.sfmt_addc_m.f
1975   int UNUSED written = 0;
1976   IADDR UNUSED pc = abuf->addr;
1977   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1978
1979 {
1980   SI tmp_tmpopd;
1981   SI tmp_tmpops;
1982   BI tmp_carry;
1983   SI tmp_newval;
1984   tmp_tmpops = EXTQISI (({   SI tmp_addr;
1985   QI tmp_tmp_mem;
1986   BI tmp_postinc;
1987   tmp_postinc = FLD (f_memmode);
1988 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
1989 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
1990 ; if (NEBI (tmp_postinc, 0)) {
1991 {
1992 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
1993   tmp_addr = ADDSI (tmp_addr, 1);
1994 }
1995   {
1996     SI opval = tmp_addr;
1997     SET_H_GR (FLD (f_operand1), opval);
1998     written |= (1 << 9);
1999     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2000   }
2001 }
2002 }
2003 ; tmp_tmp_mem; }));
2004   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2005   tmp_carry = CPU (h_cbit);
2006   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2007 ((void) 0); /*nop*/
2008 {
2009   {
2010     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2011     CPU (h_cbit) = opval;
2012     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2013   }
2014   {
2015     BI opval = LTSI (tmp_newval, 0);
2016     CPU (h_nbit) = opval;
2017     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2018   }
2019   {
2020     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2021     CPU (h_zbit) = opval;
2022     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2023   }
2024   {
2025     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2026     CPU (h_vbit) = opval;
2027     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2028   }
2029 {
2030   {
2031     BI opval = 0;
2032     CPU (h_xbit) = opval;
2033     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2034   }
2035   {
2036     BI opval = 0;
2037     SET_H_INSN_PREFIXED_P (opval);
2038     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2039   }
2040 }
2041 }
2042 }
2043
2044   abuf->written = written;
2045 #undef FLD
2046 }
2047   NEXT (vpc);
2048
2049   CASE (sem, INSN_CMPS_M_W_M) : /* cmps-m.w [${Rs}${inc}],$Rd */
2050 {
2051   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2052   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2053 #define FLD(f) abuf->fields.sfmt_addc_m.f
2054   int UNUSED written = 0;
2055   IADDR UNUSED pc = abuf->addr;
2056   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2057
2058 {
2059   SI tmp_tmpopd;
2060   SI tmp_tmpops;
2061   BI tmp_carry;
2062   SI tmp_newval;
2063   tmp_tmpops = EXTHISI (({   SI tmp_addr;
2064   HI tmp_tmp_mem;
2065   BI tmp_postinc;
2066   tmp_postinc = FLD (f_memmode);
2067 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2068 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2069 ; if (NEBI (tmp_postinc, 0)) {
2070 {
2071 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2072   tmp_addr = ADDSI (tmp_addr, 2);
2073 }
2074   {
2075     SI opval = tmp_addr;
2076     SET_H_GR (FLD (f_operand1), opval);
2077     written |= (1 << 9);
2078     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2079   }
2080 }
2081 }
2082 ; tmp_tmp_mem; }));
2083   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2084   tmp_carry = CPU (h_cbit);
2085   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2086 ((void) 0); /*nop*/
2087 {
2088   {
2089     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2090     CPU (h_cbit) = opval;
2091     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2092   }
2093   {
2094     BI opval = LTSI (tmp_newval, 0);
2095     CPU (h_nbit) = opval;
2096     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2097   }
2098   {
2099     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2100     CPU (h_zbit) = opval;
2101     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2102   }
2103   {
2104     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2105     CPU (h_vbit) = opval;
2106     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2107   }
2108 {
2109   {
2110     BI opval = 0;
2111     CPU (h_xbit) = opval;
2112     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2113   }
2114   {
2115     BI opval = 0;
2116     SET_H_INSN_PREFIXED_P (opval);
2117     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2118   }
2119 }
2120 }
2121 }
2122
2123   abuf->written = written;
2124 #undef FLD
2125 }
2126   NEXT (vpc);
2127
2128   CASE (sem, INSN_CMPSCBR) : /* [${Rs}${inc}],$Rd */
2129 {
2130   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2131   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2132 #define FLD(f) abuf->fields.sfmt_bound_cb.f
2133   int UNUSED written = 0;
2134   IADDR UNUSED pc = abuf->addr;
2135   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2136
2137 {
2138   SI tmp_tmpopd;
2139   SI tmp_tmpops;
2140   BI tmp_carry;
2141   SI tmp_newval;
2142   tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
2143   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2144   tmp_carry = CPU (h_cbit);
2145   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2146 ((void) 0); /*nop*/
2147 {
2148   {
2149     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2150     CPU (h_cbit) = opval;
2151     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2152   }
2153   {
2154     BI opval = LTSI (tmp_newval, 0);
2155     CPU (h_nbit) = opval;
2156     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2157   }
2158   {
2159     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2160     CPU (h_zbit) = opval;
2161     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2162   }
2163   {
2164     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2165     CPU (h_vbit) = opval;
2166     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2167   }
2168 {
2169   {
2170     BI opval = 0;
2171     CPU (h_xbit) = opval;
2172     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2173   }
2174   {
2175     BI opval = 0;
2176     SET_H_INSN_PREFIXED_P (opval);
2177     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2178   }
2179 }
2180 }
2181 }
2182
2183 #undef FLD
2184 }
2185   NEXT (vpc);
2186
2187   CASE (sem, INSN_CMPSCWR) : /* [${Rs}${inc}],$Rd */
2188 {
2189   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2190   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2191 #define FLD(f) abuf->fields.sfmt_bound_cw.f
2192   int UNUSED written = 0;
2193   IADDR UNUSED pc = abuf->addr;
2194   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2195
2196 {
2197   SI tmp_tmpopd;
2198   SI tmp_tmpops;
2199   BI tmp_carry;
2200   SI tmp_newval;
2201   tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
2202   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2203   tmp_carry = CPU (h_cbit);
2204   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2205 ((void) 0); /*nop*/
2206 {
2207   {
2208     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2209     CPU (h_cbit) = opval;
2210     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2211   }
2212   {
2213     BI opval = LTSI (tmp_newval, 0);
2214     CPU (h_nbit) = opval;
2215     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2216   }
2217   {
2218     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2219     CPU (h_zbit) = opval;
2220     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2221   }
2222   {
2223     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2224     CPU (h_vbit) = opval;
2225     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2226   }
2227 {
2228   {
2229     BI opval = 0;
2230     CPU (h_xbit) = opval;
2231     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2232   }
2233   {
2234     BI opval = 0;
2235     SET_H_INSN_PREFIXED_P (opval);
2236     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2237   }
2238 }
2239 }
2240 }
2241
2242 #undef FLD
2243 }
2244   NEXT (vpc);
2245
2246   CASE (sem, INSN_CMPU_M_B_M) : /* cmpu-m.b [${Rs}${inc}],$Rd */
2247 {
2248   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2249   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2250 #define FLD(f) abuf->fields.sfmt_addc_m.f
2251   int UNUSED written = 0;
2252   IADDR UNUSED pc = abuf->addr;
2253   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2254
2255 {
2256   SI tmp_tmpopd;
2257   SI tmp_tmpops;
2258   BI tmp_carry;
2259   SI tmp_newval;
2260   tmp_tmpops = ZEXTQISI (({   SI tmp_addr;
2261   QI tmp_tmp_mem;
2262   BI tmp_postinc;
2263   tmp_postinc = FLD (f_memmode);
2264 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2265 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2266 ; if (NEBI (tmp_postinc, 0)) {
2267 {
2268 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2269   tmp_addr = ADDSI (tmp_addr, 1);
2270 }
2271   {
2272     SI opval = tmp_addr;
2273     SET_H_GR (FLD (f_operand1), opval);
2274     written |= (1 << 9);
2275     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2276   }
2277 }
2278 }
2279 ; tmp_tmp_mem; }));
2280   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2281   tmp_carry = CPU (h_cbit);
2282   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2283 ((void) 0); /*nop*/
2284 {
2285   {
2286     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2287     CPU (h_cbit) = opval;
2288     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2289   }
2290   {
2291     BI opval = LTSI (tmp_newval, 0);
2292     CPU (h_nbit) = opval;
2293     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2294   }
2295   {
2296     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2297     CPU (h_zbit) = opval;
2298     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2299   }
2300   {
2301     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2302     CPU (h_vbit) = opval;
2303     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2304   }
2305 {
2306   {
2307     BI opval = 0;
2308     CPU (h_xbit) = opval;
2309     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2310   }
2311   {
2312     BI opval = 0;
2313     SET_H_INSN_PREFIXED_P (opval);
2314     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2315   }
2316 }
2317 }
2318 }
2319
2320   abuf->written = written;
2321 #undef FLD
2322 }
2323   NEXT (vpc);
2324
2325   CASE (sem, INSN_CMPU_M_W_M) : /* cmpu-m.w [${Rs}${inc}],$Rd */
2326 {
2327   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2328   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2329 #define FLD(f) abuf->fields.sfmt_addc_m.f
2330   int UNUSED written = 0;
2331   IADDR UNUSED pc = abuf->addr;
2332   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2333
2334 {
2335   SI tmp_tmpopd;
2336   SI tmp_tmpops;
2337   BI tmp_carry;
2338   SI tmp_newval;
2339   tmp_tmpops = ZEXTHISI (({   SI tmp_addr;
2340   HI tmp_tmp_mem;
2341   BI tmp_postinc;
2342   tmp_postinc = FLD (f_memmode);
2343 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2344 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2345 ; if (NEBI (tmp_postinc, 0)) {
2346 {
2347 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2348   tmp_addr = ADDSI (tmp_addr, 2);
2349 }
2350   {
2351     SI opval = tmp_addr;
2352     SET_H_GR (FLD (f_operand1), opval);
2353     written |= (1 << 9);
2354     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2355   }
2356 }
2357 }
2358 ; tmp_tmp_mem; }));
2359   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2360   tmp_carry = CPU (h_cbit);
2361   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2362 ((void) 0); /*nop*/
2363 {
2364   {
2365     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2366     CPU (h_cbit) = opval;
2367     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2368   }
2369   {
2370     BI opval = LTSI (tmp_newval, 0);
2371     CPU (h_nbit) = opval;
2372     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2373   }
2374   {
2375     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2376     CPU (h_zbit) = opval;
2377     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2378   }
2379   {
2380     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2381     CPU (h_vbit) = opval;
2382     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2383   }
2384 {
2385   {
2386     BI opval = 0;
2387     CPU (h_xbit) = opval;
2388     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2389   }
2390   {
2391     BI opval = 0;
2392     SET_H_INSN_PREFIXED_P (opval);
2393     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2394   }
2395 }
2396 }
2397 }
2398
2399   abuf->written = written;
2400 #undef FLD
2401 }
2402   NEXT (vpc);
2403
2404   CASE (sem, INSN_CMPUCBR) : /* [${Rs}${inc}],$Rd */
2405 {
2406   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2407   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2408 #define FLD(f) abuf->fields.sfmt_bound_cb.f
2409   int UNUSED written = 0;
2410   IADDR UNUSED pc = abuf->addr;
2411   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2412
2413 {
2414   SI tmp_tmpopd;
2415   SI tmp_tmpops;
2416   BI tmp_carry;
2417   SI tmp_newval;
2418   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
2419   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2420   tmp_carry = CPU (h_cbit);
2421   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2422 ((void) 0); /*nop*/
2423 {
2424   {
2425     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2426     CPU (h_cbit) = opval;
2427     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2428   }
2429   {
2430     BI opval = LTSI (tmp_newval, 0);
2431     CPU (h_nbit) = opval;
2432     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2433   }
2434   {
2435     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2436     CPU (h_zbit) = opval;
2437     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2438   }
2439   {
2440     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2441     CPU (h_vbit) = opval;
2442     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2443   }
2444 {
2445   {
2446     BI opval = 0;
2447     CPU (h_xbit) = opval;
2448     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2449   }
2450   {
2451     BI opval = 0;
2452     SET_H_INSN_PREFIXED_P (opval);
2453     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2454   }
2455 }
2456 }
2457 }
2458
2459 #undef FLD
2460 }
2461   NEXT (vpc);
2462
2463   CASE (sem, INSN_CMPUCWR) : /* [${Rs}${inc}],$Rd */
2464 {
2465   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2466   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2467 #define FLD(f) abuf->fields.sfmt_bound_cw.f
2468   int UNUSED written = 0;
2469   IADDR UNUSED pc = abuf->addr;
2470   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2471
2472 {
2473   SI tmp_tmpopd;
2474   SI tmp_tmpops;
2475   BI tmp_carry;
2476   SI tmp_newval;
2477   tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
2478   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2479   tmp_carry = CPU (h_cbit);
2480   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2481 ((void) 0); /*nop*/
2482 {
2483   {
2484     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2485     CPU (h_cbit) = opval;
2486     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2487   }
2488   {
2489     BI opval = LTSI (tmp_newval, 0);
2490     CPU (h_nbit) = opval;
2491     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2492   }
2493   {
2494     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2495     CPU (h_zbit) = opval;
2496     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2497   }
2498   {
2499     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2500     CPU (h_vbit) = opval;
2501     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2502   }
2503 {
2504   {
2505     BI opval = 0;
2506     CPU (h_xbit) = opval;
2507     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2508   }
2509   {
2510     BI opval = 0;
2511     SET_H_INSN_PREFIXED_P (opval);
2512     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2513   }
2514 }
2515 }
2516 }
2517
2518 #undef FLD
2519 }
2520   NEXT (vpc);
2521
2522   CASE (sem, INSN_MOVE_M_B_M) : /* move-m.b [${Rs}${inc}],${Rd} */
2523 {
2524   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2525   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2526 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
2527   int UNUSED written = 0;
2528   IADDR UNUSED pc = abuf->addr;
2529   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2530
2531 {
2532   SI tmp_tmp;
2533   tmp_tmp = ({   SI tmp_addr;
2534   QI tmp_tmp_mem;
2535   BI tmp_postinc;
2536   tmp_postinc = FLD (f_memmode);
2537 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2538 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2539 ; if (NEBI (tmp_postinc, 0)) {
2540 {
2541 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2542   tmp_addr = ADDSI (tmp_addr, 1);
2543 }
2544   {
2545     SI opval = tmp_addr;
2546     SET_H_GR (FLD (f_operand1), opval);
2547     written |= (1 << 10);
2548     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2549   }
2550 }
2551 }
2552 ; tmp_tmp_mem; });
2553 {
2554   SI tmp_oldregval;
2555   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
2556   {
2557     SI opval = ORSI (ANDSI (tmp_tmp, 255), ANDSI (tmp_oldregval, 0xffffff00));
2558     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
2559     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2560   }
2561 }
2562 {
2563   {
2564     BI opval = LTQI (tmp_tmp, 0);
2565     CPU (h_nbit) = opval;
2566     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2567   }
2568   {
2569     BI opval = ANDIF (EQQI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2570     CPU (h_zbit) = opval;
2571     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2572   }
2573 SET_H_CBIT_MOVE (0);
2574 SET_H_VBIT_MOVE (0);
2575 {
2576   {
2577     BI opval = 0;
2578     CPU (h_xbit) = opval;
2579     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2580   }
2581   {
2582     BI opval = 0;
2583     SET_H_INSN_PREFIXED_P (opval);
2584     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2585   }
2586 }
2587 }
2588 }
2589
2590   abuf->written = written;
2591 #undef FLD
2592 }
2593   NEXT (vpc);
2594
2595   CASE (sem, INSN_MOVE_M_W_M) : /* move-m.w [${Rs}${inc}],${Rd} */
2596 {
2597   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2598   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2599 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
2600   int UNUSED written = 0;
2601   IADDR UNUSED pc = abuf->addr;
2602   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2603
2604 {
2605   SI tmp_tmp;
2606   tmp_tmp = ({   SI tmp_addr;
2607   HI tmp_tmp_mem;
2608   BI tmp_postinc;
2609   tmp_postinc = FLD (f_memmode);
2610 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2611 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2612 ; if (NEBI (tmp_postinc, 0)) {
2613 {
2614 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2615   tmp_addr = ADDSI (tmp_addr, 2);
2616 }
2617   {
2618     SI opval = tmp_addr;
2619     SET_H_GR (FLD (f_operand1), opval);
2620     written |= (1 << 10);
2621     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2622   }
2623 }
2624 }
2625 ; tmp_tmp_mem; });
2626 {
2627   SI tmp_oldregval;
2628   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
2629   {
2630     SI opval = ORSI (ANDSI (tmp_tmp, 65535), ANDSI (tmp_oldregval, 0xffff0000));
2631     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
2632     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2633   }
2634 }
2635 {
2636   {
2637     BI opval = LTHI (tmp_tmp, 0);
2638     CPU (h_nbit) = opval;
2639     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2640   }
2641   {
2642     BI opval = ANDIF (EQHI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2643     CPU (h_zbit) = opval;
2644     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2645   }
2646 SET_H_CBIT_MOVE (0);
2647 SET_H_VBIT_MOVE (0);
2648 {
2649   {
2650     BI opval = 0;
2651     CPU (h_xbit) = opval;
2652     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2653   }
2654   {
2655     BI opval = 0;
2656     SET_H_INSN_PREFIXED_P (opval);
2657     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2658   }
2659 }
2660 }
2661 }
2662
2663   abuf->written = written;
2664 #undef FLD
2665 }
2666   NEXT (vpc);
2667
2668   CASE (sem, INSN_MOVE_M_D_M) : /* move-m.d [${Rs}${inc}],${Rd} */
2669 {
2670   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2671   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2672 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
2673   int UNUSED written = 0;
2674   IADDR UNUSED pc = abuf->addr;
2675   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2676
2677 {
2678   SI tmp_tmp;
2679   tmp_tmp = ({   SI tmp_addr;
2680   SI tmp_tmp_mem;
2681   BI tmp_postinc;
2682   tmp_postinc = FLD (f_memmode);
2683 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2684 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
2685 ; if (NEBI (tmp_postinc, 0)) {
2686 {
2687 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2688   tmp_addr = ADDSI (tmp_addr, 4);
2689 }
2690   {
2691     SI opval = tmp_addr;
2692     SET_H_GR (FLD (f_operand1), opval);
2693     written |= (1 << 9);
2694     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2695   }
2696 }
2697 }
2698 ; tmp_tmp_mem; });
2699   {
2700     SI opval = tmp_tmp;
2701     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
2702     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2703   }
2704 {
2705   {
2706     BI opval = LTSI (tmp_tmp, 0);
2707     CPU (h_nbit) = opval;
2708     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2709   }
2710   {
2711     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2712     CPU (h_zbit) = opval;
2713     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2714   }
2715 SET_H_CBIT_MOVE (0);
2716 SET_H_VBIT_MOVE (0);
2717 {
2718   {
2719     BI opval = 0;
2720     CPU (h_xbit) = opval;
2721     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2722   }
2723   {
2724     BI opval = 0;
2725     SET_H_INSN_PREFIXED_P (opval);
2726     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2727   }
2728 }
2729 }
2730 }
2731
2732   abuf->written = written;
2733 #undef FLD
2734 }
2735   NEXT (vpc);
2736
2737   CASE (sem, INSN_MOVS_M_B_M) : /* movs-m.b [${Rs}${inc}],${Rd} */
2738 {
2739   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2740   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2741 #define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
2742   int UNUSED written = 0;
2743   IADDR UNUSED pc = abuf->addr;
2744   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2745
2746 {
2747   SI tmp_tmp;
2748   tmp_tmp = EXTQISI (({   SI tmp_addr;
2749   QI tmp_tmp_mem;
2750   BI tmp_postinc;
2751   tmp_postinc = FLD (f_memmode);
2752 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2753 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2754 ; if (NEBI (tmp_postinc, 0)) {
2755 {
2756 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2757   tmp_addr = ADDSI (tmp_addr, 1);
2758 }
2759   {
2760     SI opval = tmp_addr;
2761     SET_H_GR (FLD (f_operand1), opval);
2762     written |= (1 << 8);
2763     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2764   }
2765 }
2766 }
2767 ; tmp_tmp_mem; }));
2768 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
2769   {
2770     SI opval = tmp_tmp;
2771     SET_H_GR (FLD (f_operand1), opval);
2772     written |= (1 << 8);
2773     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2774   }
2775 } else {
2776   {
2777     SI opval = tmp_tmp;
2778     SET_H_GR (FLD (f_operand2), opval);
2779     written |= (1 << 7);
2780     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2781   }
2782 }
2783 {
2784   {
2785     BI opval = LTSI (tmp_tmp, 0);
2786     CPU (h_nbit) = opval;
2787     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2788   }
2789   {
2790     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2791     CPU (h_zbit) = opval;
2792     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2793   }
2794 SET_H_CBIT_MOVE (0);
2795 SET_H_VBIT_MOVE (0);
2796 {
2797   {
2798     BI opval = 0;
2799     CPU (h_xbit) = opval;
2800     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2801   }
2802   {
2803     BI opval = 0;
2804     SET_H_INSN_PREFIXED_P (opval);
2805     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2806   }
2807 }
2808 }
2809 }
2810
2811   abuf->written = written;
2812 #undef FLD
2813 }
2814   NEXT (vpc);
2815
2816   CASE (sem, INSN_MOVS_M_W_M) : /* movs-m.w [${Rs}${inc}],${Rd} */
2817 {
2818   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2819   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2820 #define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
2821   int UNUSED written = 0;
2822   IADDR UNUSED pc = abuf->addr;
2823   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2824
2825 {
2826   SI tmp_tmp;
2827   tmp_tmp = EXTHISI (({   SI tmp_addr;
2828   HI tmp_tmp_mem;
2829   BI tmp_postinc;
2830   tmp_postinc = FLD (f_memmode);
2831 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2832 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2833 ; if (NEBI (tmp_postinc, 0)) {
2834 {
2835 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2836   tmp_addr = ADDSI (tmp_addr, 2);
2837 }
2838   {
2839     SI opval = tmp_addr;
2840     SET_H_GR (FLD (f_operand1), opval);
2841     written |= (1 << 8);
2842     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2843   }
2844 }
2845 }
2846 ; tmp_tmp_mem; }));
2847 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
2848   {
2849     SI opval = tmp_tmp;
2850     SET_H_GR (FLD (f_operand1), opval);
2851     written |= (1 << 8);
2852     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2853   }
2854 } else {
2855   {
2856     SI opval = tmp_tmp;
2857     SET_H_GR (FLD (f_operand2), opval);
2858     written |= (1 << 7);
2859     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2860   }
2861 }
2862 {
2863   {
2864     BI opval = LTSI (tmp_tmp, 0);
2865     CPU (h_nbit) = opval;
2866     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2867   }
2868   {
2869     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2870     CPU (h_zbit) = opval;
2871     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2872   }
2873 SET_H_CBIT_MOVE (0);
2874 SET_H_VBIT_MOVE (0);
2875 {
2876   {
2877     BI opval = 0;
2878     CPU (h_xbit) = opval;
2879     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2880   }
2881   {
2882     BI opval = 0;
2883     SET_H_INSN_PREFIXED_P (opval);
2884     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2885   }
2886 }
2887 }
2888 }
2889
2890   abuf->written = written;
2891 #undef FLD
2892 }
2893   NEXT (vpc);
2894
2895   CASE (sem, INSN_MOVU_M_B_M) : /* movu-m.b [${Rs}${inc}],${Rd} */
2896 {
2897   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2898   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2899 #define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
2900   int UNUSED written = 0;
2901   IADDR UNUSED pc = abuf->addr;
2902   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2903
2904 {
2905   SI tmp_tmp;
2906   tmp_tmp = ZEXTQISI (({   SI tmp_addr;
2907   QI tmp_tmp_mem;
2908   BI tmp_postinc;
2909   tmp_postinc = FLD (f_memmode);
2910 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2911 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2912 ; if (NEBI (tmp_postinc, 0)) {
2913 {
2914 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2915   tmp_addr = ADDSI (tmp_addr, 1);
2916 }
2917   {
2918     SI opval = tmp_addr;
2919     SET_H_GR (FLD (f_operand1), opval);
2920     written |= (1 << 8);
2921     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2922   }
2923 }
2924 }
2925 ; tmp_tmp_mem; }));
2926 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
2927   {
2928     SI opval = tmp_tmp;
2929     SET_H_GR (FLD (f_operand1), opval);
2930     written |= (1 << 8);
2931     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2932   }
2933 } else {
2934   {
2935     SI opval = tmp_tmp;
2936     SET_H_GR (FLD (f_operand2), opval);
2937     written |= (1 << 7);
2938     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2939   }
2940 }
2941 {
2942   {
2943     BI opval = LTSI (tmp_tmp, 0);
2944     CPU (h_nbit) = opval;
2945     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2946   }
2947   {
2948     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2949     CPU (h_zbit) = opval;
2950     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2951   }
2952 SET_H_CBIT_MOVE (0);
2953 SET_H_VBIT_MOVE (0);
2954 {
2955   {
2956     BI opval = 0;
2957     CPU (h_xbit) = opval;
2958     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2959   }
2960   {
2961     BI opval = 0;
2962     SET_H_INSN_PREFIXED_P (opval);
2963     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2964   }
2965 }
2966 }
2967 }
2968
2969   abuf->written = written;
2970 #undef FLD
2971 }
2972   NEXT (vpc);
2973
2974   CASE (sem, INSN_MOVU_M_W_M) : /* movu-m.w [${Rs}${inc}],${Rd} */
2975 {
2976   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2977   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2978 #define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
2979   int UNUSED written = 0;
2980   IADDR UNUSED pc = abuf->addr;
2981   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2982
2983 {
2984   SI tmp_tmp;
2985   tmp_tmp = ZEXTHISI (({   SI tmp_addr;
2986   HI tmp_tmp_mem;
2987   BI tmp_postinc;
2988   tmp_postinc = FLD (f_memmode);
2989 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2990 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2991 ; if (NEBI (tmp_postinc, 0)) {
2992 {
2993 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2994   tmp_addr = ADDSI (tmp_addr, 2);
2995 }
2996   {
2997     SI opval = tmp_addr;
2998     SET_H_GR (FLD (f_operand1), opval);
2999     written |= (1 << 8);
3000     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3001   }
3002 }
3003 }
3004 ; tmp_tmp_mem; }));
3005 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
3006   {
3007     SI opval = tmp_tmp;
3008     SET_H_GR (FLD (f_operand1), opval);
3009     written |= (1 << 8);
3010     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3011   }
3012 } else {
3013   {
3014     SI opval = tmp_tmp;
3015     SET_H_GR (FLD (f_operand2), opval);
3016     written |= (1 << 7);
3017     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3018   }
3019 }
3020 {
3021   {
3022     BI opval = LTSI (tmp_tmp, 0);
3023     CPU (h_nbit) = opval;
3024     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
3025   }
3026   {
3027     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
3028     CPU (h_zbit) = opval;
3029     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
3030   }
3031 SET_H_CBIT_MOVE (0);
3032 SET_H_VBIT_MOVE (0);
3033 {
3034   {
3035     BI opval = 0;
3036     CPU (h_xbit) = opval;
3037     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3038   }
3039   {
3040     BI opval = 0;
3041     SET_H_INSN_PREFIXED_P (opval);
3042     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3043   }
3044 }
3045 }
3046 }
3047
3048   abuf->written = written;
3049 #undef FLD
3050 }
3051   NEXT (vpc);
3052
3053   CASE (sem, INSN_MOVE_R_SPRV32) : /* move ${Rs},${Pd} */
3054 {
3055   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3056   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3057 #define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
3058   int UNUSED written = 0;
3059   IADDR UNUSED pc = abuf->addr;
3060   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3061
3062 {
3063   SI tmp_tmp;
3064   SI tmp_rno;
3065   tmp_tmp = GET_H_GR (FLD (f_operand1));
3066   tmp_rno = FLD (f_operand2);
3067 if (ORIF (ORIF (EQSI (tmp_rno, 0), EQSI (tmp_rno, 1)), ORIF (EQSI (tmp_rno, 4), EQSI (tmp_rno, 8)))) {
3068 cgen_rtx_error (current_cpu, "move-r-spr: trying to set a read-only special register");
3069 }
3070  else {
3071   {
3072     SI opval = tmp_tmp;
3073     SET_H_SR (FLD (f_operand2), opval);
3074     written |= (1 << 2);
3075     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3076   }
3077 }
3078 {
3079   {
3080     BI opval = 0;
3081     CPU (h_xbit) = opval;
3082     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3083   }
3084   {
3085     BI opval = 0;
3086     SET_H_INSN_PREFIXED_P (opval);
3087     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3088   }
3089 }
3090 }
3091
3092   abuf->written = written;
3093 #undef FLD
3094 }
3095   NEXT (vpc);
3096
3097   CASE (sem, INSN_MOVE_SPR_RV32) : /* move ${Ps},${Rd-sfield} */
3098 {
3099   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3100   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3101 #define FLD(f) abuf->fields.sfmt_mcp.f
3102   int UNUSED written = 0;
3103   IADDR UNUSED pc = abuf->addr;
3104   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3105
3106 {
3107   SI tmp_grno;
3108   SI tmp_prno;
3109   SI tmp_newval;
3110   tmp_prno = FLD (f_operand2);
3111   tmp_newval = GET_H_SR (FLD (f_operand2));
3112 if (EQSI (tmp_prno, 2)) {
3113 {
3114   SI tmp_oldregval;
3115   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1));
3116   {
3117     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
3118     SET_H_GR (FLD (f_operand1), opval);
3119     written |= (1 << 4);
3120     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3121   }
3122 }
3123 }
3124  else if (EQSI (tmp_prno, 3)) {
3125 {
3126   SI tmp_oldregval;
3127   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1));
3128   {
3129     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
3130     SET_H_GR (FLD (f_operand1), opval);
3131     written |= (1 << 4);
3132     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3133   }
3134 }
3135 }
3136  else if (EQSI (tmp_prno, 5)) {
3137   {
3138     SI opval = tmp_newval;
3139     SET_H_GR (FLD (f_operand1), opval);
3140     written |= (1 << 4);
3141     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3142   }
3143 }
3144  else if (EQSI (tmp_prno, 6)) {
3145   {
3146     SI opval = tmp_newval;
3147     SET_H_GR (FLD (f_operand1), opval);
3148     written |= (1 << 4);
3149     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3150   }
3151 }
3152  else if (EQSI (tmp_prno, 7)) {
3153   {
3154     SI opval = tmp_newval;
3155     SET_H_GR (FLD (f_operand1), opval);
3156     written |= (1 << 4);
3157     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3158   }
3159 }
3160  else if (EQSI (tmp_prno, 9)) {
3161   {
3162     SI opval = tmp_newval;
3163     SET_H_GR (FLD (f_operand1), opval);
3164     written |= (1 << 4);
3165     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3166   }
3167 }
3168  else if (EQSI (tmp_prno, 10)) {
3169   {
3170     SI opval = tmp_newval;
3171     SET_H_GR (FLD (f_operand1), opval);
3172     written |= (1 << 4);
3173     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3174   }
3175 }
3176  else if (EQSI (tmp_prno, 11)) {
3177   {
3178     SI opval = tmp_newval;
3179     SET_H_GR (FLD (f_operand1), opval);
3180     written |= (1 << 4);
3181     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3182   }
3183 }
3184  else if (EQSI (tmp_prno, 12)) {
3185   {
3186     SI opval = tmp_newval;
3187     SET_H_GR (FLD (f_operand1), opval);
3188     written |= (1 << 4);
3189     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3190   }
3191 }
3192  else if (EQSI (tmp_prno, 13)) {
3193   {
3194     SI opval = tmp_newval;
3195     SET_H_GR (FLD (f_operand1), opval);
3196     written |= (1 << 4);
3197     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3198   }
3199 }
3200  else if (EQSI (tmp_prno, 14)) {
3201   {
3202     SI opval = tmp_newval;
3203     SET_H_GR (FLD (f_operand1), opval);
3204     written |= (1 << 4);
3205     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3206   }
3207 }
3208  else if (EQSI (tmp_prno, 15)) {
3209   {
3210     SI opval = tmp_newval;
3211     SET_H_GR (FLD (f_operand1), opval);
3212     written |= (1 << 4);
3213     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3214   }
3215 }
3216  else if (EQSI (tmp_prno, 0)) {
3217 {
3218   SI tmp_oldregval;
3219   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1));
3220   {
3221     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
3222     SET_H_GR (FLD (f_operand1), opval);
3223     written |= (1 << 4);
3224     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3225   }
3226 }
3227 }
3228  else if (EQSI (tmp_prno, 1)) {
3229 {
3230   SI tmp_oldregval;
3231   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1));
3232   {
3233     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
3234     SET_H_GR (FLD (f_operand1), opval);
3235     written |= (1 << 4);
3236     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3237   }
3238 }
3239 }
3240  else if (EQSI (tmp_prno, 4)) {
3241 {
3242   SI tmp_oldregval;
3243   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1));
3244   {
3245     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
3246     SET_H_GR (FLD (f_operand1), opval);
3247     written |= (1 << 4);
3248     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3249   }
3250 }
3251 }
3252  else if (EQSI (tmp_prno, 8)) {
3253   {
3254     SI opval = tmp_newval;
3255     SET_H_GR (FLD (f_operand1), opval);
3256     written |= (1 << 4);
3257     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3258   }
3259 }
3260  else {
3261 cgen_rtx_error (current_cpu, "move-spr-r from unimplemented register");
3262 }
3263 {
3264   {
3265     BI opval = 0;
3266     CPU (h_xbit) = opval;
3267     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3268   }
3269   {
3270     BI opval = 0;
3271     SET_H_INSN_PREFIXED_P (opval);
3272     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3273   }
3274 }
3275 }
3276
3277   abuf->written = written;
3278 #undef FLD
3279 }
3280   NEXT (vpc);
3281
3282   CASE (sem, INSN_MOVE_M_SPRV32) : /* move [${Rs}${inc}],${Pd} */
3283 {
3284   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3285   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3286 #define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
3287   int UNUSED written = 0;
3288   IADDR UNUSED pc = abuf->addr;
3289   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3290
3291 {
3292   SI tmp_rno;
3293   SI tmp_newval;
3294   tmp_rno = FLD (f_operand2);
3295 if (EQSI (tmp_rno, 2)) {
3296   tmp_newval = EXTQISI (({   SI tmp_addr;
3297   QI tmp_tmp_mem;
3298   BI tmp_postinc;
3299   tmp_postinc = FLD (f_memmode);
3300 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3301 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
3302 ; if (NEBI (tmp_postinc, 0)) {
3303 {
3304 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3305   tmp_addr = ADDSI (tmp_addr, 1);
3306 }
3307   {
3308     SI opval = tmp_addr;
3309     SET_H_GR (FLD (f_operand1), opval);
3310     written |= (1 << 8);
3311     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3312   }
3313 }
3314 }
3315 ; tmp_tmp_mem; }));
3316 }
3317  else if (EQSI (tmp_rno, 3)) {
3318   tmp_newval = EXTQISI (({   SI tmp_addr;
3319   QI tmp_tmp_mem;
3320   BI tmp_postinc;
3321   tmp_postinc = FLD (f_memmode);
3322 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3323 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
3324 ; if (NEBI (tmp_postinc, 0)) {
3325 {
3326 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3327   tmp_addr = ADDSI (tmp_addr, 1);
3328 }
3329   {
3330     SI opval = tmp_addr;
3331     SET_H_GR (FLD (f_operand1), opval);
3332     written |= (1 << 8);
3333     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3334   }
3335 }
3336 }
3337 ; tmp_tmp_mem; }));
3338 }
3339  else if (EQSI (tmp_rno, 5)) {
3340   tmp_newval = ({   SI tmp_addr;
3341   SI tmp_tmp_mem;
3342   BI tmp_postinc;
3343   tmp_postinc = FLD (f_memmode);
3344 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3345 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3346 ; if (NEBI (tmp_postinc, 0)) {
3347 {
3348 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3349   tmp_addr = ADDSI (tmp_addr, 4);
3350 }
3351   {
3352     SI opval = tmp_addr;
3353     SET_H_GR (FLD (f_operand1), opval);
3354     written |= (1 << 8);
3355     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3356   }
3357 }
3358 }
3359 ; tmp_tmp_mem; });
3360 }
3361  else if (EQSI (tmp_rno, 6)) {
3362   tmp_newval = ({   SI tmp_addr;
3363   SI tmp_tmp_mem;
3364   BI tmp_postinc;
3365   tmp_postinc = FLD (f_memmode);
3366 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3367 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3368 ; if (NEBI (tmp_postinc, 0)) {
3369 {
3370 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3371   tmp_addr = ADDSI (tmp_addr, 4);
3372 }
3373   {
3374     SI opval = tmp_addr;
3375     SET_H_GR (FLD (f_operand1), opval);
3376     written |= (1 << 8);
3377     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3378   }
3379 }
3380 }
3381 ; tmp_tmp_mem; });
3382 }
3383  else if (EQSI (tmp_rno, 7)) {
3384   tmp_newval = ({   SI tmp_addr;
3385   SI tmp_tmp_mem;
3386   BI tmp_postinc;
3387   tmp_postinc = FLD (f_memmode);
3388 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3389 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3390 ; if (NEBI (tmp_postinc, 0)) {
3391 {
3392 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3393   tmp_addr = ADDSI (tmp_addr, 4);
3394 }
3395   {
3396     SI opval = tmp_addr;
3397     SET_H_GR (FLD (f_operand1), opval);
3398     written |= (1 << 8);
3399     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3400   }
3401 }
3402 }
3403 ; tmp_tmp_mem; });
3404 }
3405  else if (EQSI (tmp_rno, 9)) {
3406   tmp_newval = ({   SI tmp_addr;
3407   SI tmp_tmp_mem;
3408   BI tmp_postinc;
3409   tmp_postinc = FLD (f_memmode);
3410 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3411 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3412 ; if (NEBI (tmp_postinc, 0)) {
3413 {
3414 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3415   tmp_addr = ADDSI (tmp_addr, 4);
3416 }
3417   {
3418     SI opval = tmp_addr;
3419     SET_H_GR (FLD (f_operand1), opval);
3420     written |= (1 << 8);
3421     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3422   }
3423 }
3424 }
3425 ; tmp_tmp_mem; });
3426 }
3427  else if (EQSI (tmp_rno, 10)) {
3428   tmp_newval = ({   SI tmp_addr;
3429   SI tmp_tmp_mem;
3430   BI tmp_postinc;
3431   tmp_postinc = FLD (f_memmode);
3432 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3433 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3434 ; if (NEBI (tmp_postinc, 0)) {
3435 {
3436 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3437   tmp_addr = ADDSI (tmp_addr, 4);
3438 }
3439   {
3440     SI opval = tmp_addr;
3441     SET_H_GR (FLD (f_operand1), opval);
3442     written |= (1 << 8);
3443     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3444   }
3445 }
3446 }
3447 ; tmp_tmp_mem; });
3448 }
3449  else if (EQSI (tmp_rno, 11)) {
3450   tmp_newval = ({   SI tmp_addr;
3451   SI tmp_tmp_mem;
3452   BI tmp_postinc;
3453   tmp_postinc = FLD (f_memmode);
3454 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3455 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3456 ; if (NEBI (tmp_postinc, 0)) {
3457 {
3458 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3459   tmp_addr = ADDSI (tmp_addr, 4);
3460 }
3461   {
3462     SI opval = tmp_addr;
3463     SET_H_GR (FLD (f_operand1), opval);
3464     written |= (1 << 8);
3465     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3466   }
3467 }
3468 }
3469 ; tmp_tmp_mem; });
3470 }
3471  else if (EQSI (tmp_rno, 12)) {
3472   tmp_newval = ({   SI tmp_addr;
3473   SI tmp_tmp_mem;
3474   BI tmp_postinc;
3475   tmp_postinc = FLD (f_memmode);
3476 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3477 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3478 ; if (NEBI (tmp_postinc, 0)) {
3479 {
3480 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3481   tmp_addr = ADDSI (tmp_addr, 4);
3482 }
3483   {
3484     SI opval = tmp_addr;
3485     SET_H_GR (FLD (f_operand1), opval);
3486     written |= (1 << 8);
3487     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3488   }
3489 }
3490 }
3491 ; tmp_tmp_mem; });
3492 }
3493  else if (EQSI (tmp_rno, 13)) {
3494   tmp_newval = ({   SI tmp_addr;
3495   SI tmp_tmp_mem;
3496   BI tmp_postinc;
3497   tmp_postinc = FLD (f_memmode);
3498 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3499 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3500 ; if (NEBI (tmp_postinc, 0)) {
3501 {
3502 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3503   tmp_addr = ADDSI (tmp_addr, 4);
3504 }
3505   {
3506     SI opval = tmp_addr;
3507     SET_H_GR (FLD (f_operand1), opval);
3508     written |= (1 << 8);
3509     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3510   }
3511 }
3512 }
3513 ; tmp_tmp_mem; });
3514 }
3515  else if (EQSI (tmp_rno, 14)) {
3516   tmp_newval = ({   SI tmp_addr;
3517   SI tmp_tmp_mem;
3518   BI tmp_postinc;
3519   tmp_postinc = FLD (f_memmode);
3520 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3521 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3522 ; if (NEBI (tmp_postinc, 0)) {
3523 {
3524 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3525   tmp_addr = ADDSI (tmp_addr, 4);
3526 }
3527   {
3528     SI opval = tmp_addr;
3529     SET_H_GR (FLD (f_operand1), opval);
3530     written |= (1 << 8);
3531     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3532   }
3533 }
3534 }
3535 ; tmp_tmp_mem; });
3536 }
3537  else if (EQSI (tmp_rno, 15)) {
3538   tmp_newval = ({   SI tmp_addr;
3539   SI tmp_tmp_mem;
3540   BI tmp_postinc;
3541   tmp_postinc = FLD (f_memmode);
3542 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3543 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3544 ; if (NEBI (tmp_postinc, 0)) {
3545 {
3546 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3547   tmp_addr = ADDSI (tmp_addr, 4);
3548 }
3549   {
3550     SI opval = tmp_addr;
3551     SET_H_GR (FLD (f_operand1), opval);
3552     written |= (1 << 8);
3553     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3554   }
3555 }
3556 }
3557 ; tmp_tmp_mem; });
3558 }
3559  else {
3560 cgen_rtx_error (current_cpu, "Trying to set unimplemented special register");
3561 }
3562   {
3563     SI opval = tmp_newval;
3564     SET_H_SR (FLD (f_operand2), opval);
3565     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3566   }
3567 {
3568   {
3569     BI opval = 0;
3570     CPU (h_xbit) = opval;
3571     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3572   }
3573   {
3574     BI opval = 0;
3575     SET_H_INSN_PREFIXED_P (opval);
3576     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3577   }
3578 }
3579 }
3580
3581   abuf->written = written;
3582 #undef FLD
3583 }
3584   NEXT (vpc);
3585
3586   CASE (sem, INSN_MOVE_C_SPRV32_P2) : /* move ${const32},${Pd} */
3587 {
3588   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3589   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3590 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3591   int UNUSED written = 0;
3592   IADDR UNUSED pc = abuf->addr;
3593   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3594
3595 {
3596   {
3597     SI opval = FLD (f_indir_pc__dword);
3598     SET_H_SR (FLD (f_operand2), opval);
3599     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3600   }
3601 {
3602   {
3603     BI opval = 0;
3604     CPU (h_xbit) = opval;
3605     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3606   }
3607   {
3608     BI opval = 0;
3609     SET_H_INSN_PREFIXED_P (opval);
3610     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3611   }
3612 }
3613 }
3614
3615 #undef FLD
3616 }
3617   NEXT (vpc);
3618
3619   CASE (sem, INSN_MOVE_C_SPRV32_P3) : /* move ${const32},${Pd} */
3620 {
3621   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3622   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3623 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3624   int UNUSED written = 0;
3625   IADDR UNUSED pc = abuf->addr;
3626   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3627
3628 {
3629   {
3630     SI opval = FLD (f_indir_pc__dword);
3631     SET_H_SR (FLD (f_operand2), opval);
3632     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3633   }
3634 {
3635   {
3636     BI opval = 0;
3637     CPU (h_xbit) = opval;
3638     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3639   }
3640   {
3641     BI opval = 0;
3642     SET_H_INSN_PREFIXED_P (opval);
3643     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3644   }
3645 }
3646 }
3647
3648 #undef FLD
3649 }
3650   NEXT (vpc);
3651
3652   CASE (sem, INSN_MOVE_C_SPRV32_P5) : /* move ${const32},${Pd} */
3653 {
3654   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3655   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3656 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3657   int UNUSED written = 0;
3658   IADDR UNUSED pc = abuf->addr;
3659   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3660
3661 {
3662   {
3663     SI opval = FLD (f_indir_pc__dword);
3664     SET_H_SR (FLD (f_operand2), opval);
3665     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3666   }
3667 {
3668   {
3669     BI opval = 0;
3670     CPU (h_xbit) = opval;
3671     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3672   }
3673   {
3674     BI opval = 0;
3675     SET_H_INSN_PREFIXED_P (opval);
3676     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3677   }
3678 }
3679 }
3680
3681 #undef FLD
3682 }
3683   NEXT (vpc);
3684
3685   CASE (sem, INSN_MOVE_C_SPRV32_P6) : /* move ${const32},${Pd} */
3686 {
3687   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3688   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3689 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3690   int UNUSED written = 0;
3691   IADDR UNUSED pc = abuf->addr;
3692   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3693
3694 {
3695   {
3696     SI opval = FLD (f_indir_pc__dword);
3697     SET_H_SR (FLD (f_operand2), opval);
3698     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3699   }
3700 {
3701   {
3702     BI opval = 0;
3703     CPU (h_xbit) = opval;
3704     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3705   }
3706   {
3707     BI opval = 0;
3708     SET_H_INSN_PREFIXED_P (opval);
3709     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3710   }
3711 }
3712 }
3713
3714 #undef FLD
3715 }
3716   NEXT (vpc);
3717
3718   CASE (sem, INSN_MOVE_C_SPRV32_P7) : /* move ${const32},${Pd} */
3719 {
3720   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3721   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3722 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3723   int UNUSED written = 0;
3724   IADDR UNUSED pc = abuf->addr;
3725   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3726
3727 {
3728   {
3729     SI opval = FLD (f_indir_pc__dword);
3730     SET_H_SR (FLD (f_operand2), opval);
3731     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3732   }
3733 {
3734   {
3735     BI opval = 0;
3736     CPU (h_xbit) = opval;
3737     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3738   }
3739   {
3740     BI opval = 0;
3741     SET_H_INSN_PREFIXED_P (opval);
3742     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3743   }
3744 }
3745 }
3746
3747 #undef FLD
3748 }
3749   NEXT (vpc);
3750
3751   CASE (sem, INSN_MOVE_C_SPRV32_P9) : /* move ${const32},${Pd} */
3752 {
3753   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3754   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3755 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3756   int UNUSED written = 0;
3757   IADDR UNUSED pc = abuf->addr;
3758   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3759
3760 {
3761   {
3762     SI opval = FLD (f_indir_pc__dword);
3763     SET_H_SR (FLD (f_operand2), opval);
3764     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3765   }
3766 {
3767   {
3768     BI opval = 0;
3769     CPU (h_xbit) = opval;
3770     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3771   }
3772   {
3773     BI opval = 0;
3774     SET_H_INSN_PREFIXED_P (opval);
3775     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3776   }
3777 }
3778 }
3779
3780 #undef FLD
3781 }
3782   NEXT (vpc);
3783
3784   CASE (sem, INSN_MOVE_C_SPRV32_P10) : /* move ${const32},${Pd} */
3785 {
3786   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3787   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3788 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3789   int UNUSED written = 0;
3790   IADDR UNUSED pc = abuf->addr;
3791   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3792
3793 {
3794   {
3795     SI opval = FLD (f_indir_pc__dword);
3796     SET_H_SR (FLD (f_operand2), opval);
3797     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3798   }
3799 {
3800   {
3801     BI opval = 0;
3802     CPU (h_xbit) = opval;
3803     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3804   }
3805   {
3806     BI opval = 0;
3807     SET_H_INSN_PREFIXED_P (opval);
3808     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3809   }
3810 }
3811 }
3812
3813 #undef FLD
3814 }
3815   NEXT (vpc);
3816
3817   CASE (sem, INSN_MOVE_C_SPRV32_P11) : /* move ${const32},${Pd} */
3818 {
3819   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3820   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3821 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3822   int UNUSED written = 0;
3823   IADDR UNUSED pc = abuf->addr;
3824   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3825
3826 {
3827   {
3828     SI opval = FLD (f_indir_pc__dword);
3829     SET_H_SR (FLD (f_operand2), opval);
3830     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3831   }
3832 {
3833   {
3834     BI opval = 0;
3835     CPU (h_xbit) = opval;
3836     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3837   }
3838   {
3839     BI opval = 0;
3840     SET_H_INSN_PREFIXED_P (opval);
3841     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3842   }
3843 }
3844 }
3845
3846 #undef FLD
3847 }
3848   NEXT (vpc);
3849
3850   CASE (sem, INSN_MOVE_C_SPRV32_P12) : /* move ${const32},${Pd} */
3851 {
3852   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3853   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3854 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3855   int UNUSED written = 0;
3856   IADDR UNUSED pc = abuf->addr;
3857   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3858
3859 {
3860   {
3861     SI opval = FLD (f_indir_pc__dword);
3862     SET_H_SR (FLD (f_operand2), opval);
3863     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3864   }
3865 {
3866   {
3867     BI opval = 0;
3868     CPU (h_xbit) = opval;
3869     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3870   }
3871   {
3872     BI opval = 0;
3873     SET_H_INSN_PREFIXED_P (opval);
3874     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3875   }
3876 }
3877 }
3878
3879 #undef FLD
3880 }
3881   NEXT (vpc);
3882
3883   CASE (sem, INSN_MOVE_C_SPRV32_P13) : /* move ${const32},${Pd} */
3884 {
3885   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3886   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3887 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3888   int UNUSED written = 0;
3889   IADDR UNUSED pc = abuf->addr;
3890   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3891
3892 {
3893   {
3894     SI opval = FLD (f_indir_pc__dword);
3895     SET_H_SR (FLD (f_operand2), opval);
3896     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3897   }
3898 {
3899   {
3900     BI opval = 0;
3901     CPU (h_xbit) = opval;
3902     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3903   }
3904   {
3905     BI opval = 0;
3906     SET_H_INSN_PREFIXED_P (opval);
3907     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3908   }
3909 }
3910 }
3911
3912 #undef FLD
3913 }
3914   NEXT (vpc);
3915
3916   CASE (sem, INSN_MOVE_C_SPRV32_P14) : /* move ${const32},${Pd} */
3917 {
3918   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3919   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3920 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3921   int UNUSED written = 0;
3922   IADDR UNUSED pc = abuf->addr;
3923   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3924
3925 {
3926   {
3927     SI opval = FLD (f_indir_pc__dword);
3928     SET_H_SR (FLD (f_operand2), opval);
3929     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3930   }
3931 {
3932   {
3933     BI opval = 0;
3934     CPU (h_xbit) = opval;
3935     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3936   }
3937   {
3938     BI opval = 0;
3939     SET_H_INSN_PREFIXED_P (opval);
3940     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3941   }
3942 }
3943 }
3944
3945 #undef FLD
3946 }
3947   NEXT (vpc);
3948
3949   CASE (sem, INSN_MOVE_C_SPRV32_P15) : /* move ${const32},${Pd} */
3950 {
3951   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3952   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3953 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3954   int UNUSED written = 0;
3955   IADDR UNUSED pc = abuf->addr;
3956   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3957
3958 {
3959   {
3960     SI opval = FLD (f_indir_pc__dword);
3961     SET_H_SR (FLD (f_operand2), opval);
3962     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3963   }
3964 {
3965   {
3966     BI opval = 0;
3967     CPU (h_xbit) = opval;
3968     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3969   }
3970   {
3971     BI opval = 0;
3972     SET_H_INSN_PREFIXED_P (opval);
3973     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3974   }
3975 }
3976 }
3977
3978 #undef FLD
3979 }
3980   NEXT (vpc);
3981
3982   CASE (sem, INSN_MOVE_SPR_MV32) : /* move ${Ps},[${Rd-sfield}${inc}] */
3983 {
3984   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3985   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3986 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
3987   int UNUSED written = 0;
3988   IADDR UNUSED pc = abuf->addr;
3989   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3990
3991 {
3992   SI tmp_rno;
3993   tmp_rno = FLD (f_operand2);
3994 if (EQSI (tmp_rno, 2)) {
3995 {
3996   SI tmp_addr;
3997   BI tmp_postinc;
3998   tmp_postinc = FLD (f_memmode);
3999   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4000 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4001 if (EQBI (CPU (h_pbit), 0)) {
4002 {
4003   {
4004     QI opval = GET_H_SR (FLD (f_operand2));
4005     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4006     written |= (1 << 12);
4007     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4008   }
4009   {
4010     BI opval = CPU (h_pbit);
4011     CPU (h_cbit) = opval;
4012     written |= (1 << 10);
4013     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4014   }
4015 }
4016 } else {
4017   {
4018     BI opval = 1;
4019     CPU (h_cbit) = opval;
4020     written |= (1 << 10);
4021     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4022   }
4023 }
4024 } else {
4025   {
4026     QI opval = GET_H_SR (FLD (f_operand2));
4027     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4028     written |= (1 << 12);
4029     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4030   }
4031 }
4032 if (NEBI (tmp_postinc, 0)) {
4033 {
4034 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4035   tmp_addr = ADDSI (tmp_addr, 1);
4036 }
4037   {
4038     SI opval = tmp_addr;
4039     SET_H_GR (FLD (f_operand1), opval);
4040     written |= (1 << 9);
4041     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4042   }
4043 }
4044 }
4045 }
4046 }
4047  else if (EQSI (tmp_rno, 3)) {
4048 {
4049   SI tmp_addr;
4050   BI tmp_postinc;
4051   tmp_postinc = FLD (f_memmode);
4052   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4053 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4054 if (EQBI (CPU (h_pbit), 0)) {
4055 {
4056   {
4057     QI opval = GET_H_SR (FLD (f_operand2));
4058     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4059     written |= (1 << 12);
4060     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4061   }
4062   {
4063     BI opval = CPU (h_pbit);
4064     CPU (h_cbit) = opval;
4065     written |= (1 << 10);
4066     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4067   }
4068 }
4069 } else {
4070   {
4071     BI opval = 1;
4072     CPU (h_cbit) = opval;
4073     written |= (1 << 10);
4074     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4075   }
4076 }
4077 } else {
4078   {
4079     QI opval = GET_H_SR (FLD (f_operand2));
4080     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4081     written |= (1 << 12);
4082     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4083   }
4084 }
4085 if (NEBI (tmp_postinc, 0)) {
4086 {
4087 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4088   tmp_addr = ADDSI (tmp_addr, 1);
4089 }
4090   {
4091     SI opval = tmp_addr;
4092     SET_H_GR (FLD (f_operand1), opval);
4093     written |= (1 << 9);
4094     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4095   }
4096 }
4097 }
4098 }
4099 }
4100  else if (EQSI (tmp_rno, 5)) {
4101 {
4102   SI tmp_addr;
4103   BI tmp_postinc;
4104   tmp_postinc = FLD (f_memmode);
4105   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4106 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4107 if (EQBI (CPU (h_pbit), 0)) {
4108 {
4109   {
4110     SI opval = GET_H_SR (FLD (f_operand2));
4111     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4112     written |= (1 << 13);
4113     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4114   }
4115   {
4116     BI opval = CPU (h_pbit);
4117     CPU (h_cbit) = opval;
4118     written |= (1 << 10);
4119     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4120   }
4121 }
4122 } else {
4123   {
4124     BI opval = 1;
4125     CPU (h_cbit) = opval;
4126     written |= (1 << 10);
4127     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4128   }
4129 }
4130 } else {
4131   {
4132     SI opval = GET_H_SR (FLD (f_operand2));
4133     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4134     written |= (1 << 13);
4135     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4136   }
4137 }
4138 if (NEBI (tmp_postinc, 0)) {
4139 {
4140 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4141   tmp_addr = ADDSI (tmp_addr, 4);
4142 }
4143   {
4144     SI opval = tmp_addr;
4145     SET_H_GR (FLD (f_operand1), opval);
4146     written |= (1 << 9);
4147     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4148   }
4149 }
4150 }
4151 }
4152 }
4153  else if (EQSI (tmp_rno, 6)) {
4154 {
4155   SI tmp_addr;
4156   BI tmp_postinc;
4157   tmp_postinc = FLD (f_memmode);
4158   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4159 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4160 if (EQBI (CPU (h_pbit), 0)) {
4161 {
4162   {
4163     SI opval = GET_H_SR (FLD (f_operand2));
4164     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4165     written |= (1 << 13);
4166     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4167   }
4168   {
4169     BI opval = CPU (h_pbit);
4170     CPU (h_cbit) = opval;
4171     written |= (1 << 10);
4172     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4173   }
4174 }
4175 } else {
4176   {
4177     BI opval = 1;
4178     CPU (h_cbit) = opval;
4179     written |= (1 << 10);
4180     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4181   }
4182 }
4183 } else {
4184   {
4185     SI opval = GET_H_SR (FLD (f_operand2));
4186     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4187     written |= (1 << 13);
4188     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4189   }
4190 }
4191 if (NEBI (tmp_postinc, 0)) {
4192 {
4193 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4194   tmp_addr = ADDSI (tmp_addr, 4);
4195 }
4196   {
4197     SI opval = tmp_addr;
4198     SET_H_GR (FLD (f_operand1), opval);
4199     written |= (1 << 9);
4200     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4201   }
4202 }
4203 }
4204 }
4205 }
4206  else if (EQSI (tmp_rno, 7)) {
4207 {
4208   SI tmp_addr;
4209   BI tmp_postinc;
4210   tmp_postinc = FLD (f_memmode);
4211   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4212 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4213 if (EQBI (CPU (h_pbit), 0)) {
4214 {
4215   {
4216     SI opval = GET_H_SR (FLD (f_operand2));
4217     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4218     written |= (1 << 13);
4219     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4220   }
4221   {
4222     BI opval = CPU (h_pbit);
4223     CPU (h_cbit) = opval;
4224     written |= (1 << 10);
4225     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4226   }
4227 }
4228 } else {
4229   {
4230     BI opval = 1;
4231     CPU (h_cbit) = opval;
4232     written |= (1 << 10);
4233     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4234   }
4235 }
4236 } else {
4237   {
4238     SI opval = GET_H_SR (FLD (f_operand2));
4239     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4240     written |= (1 << 13);
4241     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4242   }
4243 }
4244 if (NEBI (tmp_postinc, 0)) {
4245 {
4246 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4247   tmp_addr = ADDSI (tmp_addr, 4);
4248 }
4249   {
4250     SI opval = tmp_addr;
4251     SET_H_GR (FLD (f_operand1), opval);
4252     written |= (1 << 9);
4253     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4254   }
4255 }
4256 }
4257 }
4258 }
4259  else if (EQSI (tmp_rno, 9)) {
4260 {
4261   SI tmp_addr;
4262   BI tmp_postinc;
4263   tmp_postinc = FLD (f_memmode);
4264   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4265 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4266 if (EQBI (CPU (h_pbit), 0)) {
4267 {
4268   {
4269     SI opval = GET_H_SR (FLD (f_operand2));
4270     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4271     written |= (1 << 13);
4272     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4273   }
4274   {
4275     BI opval = CPU (h_pbit);
4276     CPU (h_cbit) = opval;
4277     written |= (1 << 10);
4278     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4279   }
4280 }
4281 } else {
4282   {
4283     BI opval = 1;
4284     CPU (h_cbit) = opval;
4285     written |= (1 << 10);
4286     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4287   }
4288 }
4289 } else {
4290   {
4291     SI opval = GET_H_SR (FLD (f_operand2));
4292     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4293     written |= (1 << 13);
4294     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4295   }
4296 }
4297 if (NEBI (tmp_postinc, 0)) {
4298 {
4299 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4300   tmp_addr = ADDSI (tmp_addr, 4);
4301 }
4302   {
4303     SI opval = tmp_addr;
4304     SET_H_GR (FLD (f_operand1), opval);
4305     written |= (1 << 9);
4306     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4307   }
4308 }
4309 }
4310 }
4311 }
4312  else if (EQSI (tmp_rno, 10)) {
4313 {
4314   SI tmp_addr;
4315   BI tmp_postinc;
4316   tmp_postinc = FLD (f_memmode);
4317   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4318 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4319 if (EQBI (CPU (h_pbit), 0)) {
4320 {
4321   {
4322     SI opval = GET_H_SR (FLD (f_operand2));
4323     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4324     written |= (1 << 13);
4325     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4326   }
4327   {
4328     BI opval = CPU (h_pbit);
4329     CPU (h_cbit) = opval;
4330     written |= (1 << 10);
4331     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4332   }
4333 }
4334 } else {
4335   {
4336     BI opval = 1;
4337     CPU (h_cbit) = opval;
4338     written |= (1 << 10);
4339     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4340   }
4341 }
4342 } else {
4343   {
4344     SI opval = GET_H_SR (FLD (f_operand2));
4345     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4346     written |= (1 << 13);
4347     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4348   }
4349 }
4350 if (NEBI (tmp_postinc, 0)) {
4351 {
4352 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4353   tmp_addr = ADDSI (tmp_addr, 4);
4354 }
4355   {
4356     SI opval = tmp_addr;
4357     SET_H_GR (FLD (f_operand1), opval);
4358     written |= (1 << 9);
4359     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4360   }
4361 }
4362 }
4363 }
4364 }
4365  else if (EQSI (tmp_rno, 11)) {
4366 {
4367   SI tmp_addr;
4368   BI tmp_postinc;
4369   tmp_postinc = FLD (f_memmode);
4370   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4371 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4372 if (EQBI (CPU (h_pbit), 0)) {
4373 {
4374   {
4375     SI opval = GET_H_SR (FLD (f_operand2));
4376     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4377     written |= (1 << 13);
4378     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4379   }
4380   {
4381     BI opval = CPU (h_pbit);
4382     CPU (h_cbit) = opval;
4383     written |= (1 << 10);
4384     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4385   }
4386 }
4387 } else {
4388   {
4389     BI opval = 1;
4390     CPU (h_cbit) = opval;
4391     written |= (1 << 10);
4392     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4393   }
4394 }
4395 } else {
4396   {
4397     SI opval = GET_H_SR (FLD (f_operand2));
4398     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4399     written |= (1 << 13);
4400     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4401   }
4402 }
4403 if (NEBI (tmp_postinc, 0)) {
4404 {
4405 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4406   tmp_addr = ADDSI (tmp_addr, 4);
4407 }
4408   {
4409     SI opval = tmp_addr;
4410     SET_H_GR (FLD (f_operand1), opval);
4411     written |= (1 << 9);
4412     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4413   }
4414 }
4415 }
4416 }
4417 }
4418  else if (EQSI (tmp_rno, 12)) {
4419 {
4420   SI tmp_addr;
4421   BI tmp_postinc;
4422   tmp_postinc = FLD (f_memmode);
4423   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4424 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4425 if (EQBI (CPU (h_pbit), 0)) {
4426 {
4427   {
4428     SI opval = GET_H_SR (FLD (f_operand2));
4429     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4430     written |= (1 << 13);
4431     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4432   }
4433   {
4434     BI opval = CPU (h_pbit);
4435     CPU (h_cbit) = opval;
4436     written |= (1 << 10);
4437     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4438   }
4439 }
4440 } else {
4441   {
4442     BI opval = 1;
4443     CPU (h_cbit) = opval;
4444     written |= (1 << 10);
4445     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4446   }
4447 }
4448 } else {
4449   {
4450     SI opval = GET_H_SR (FLD (f_operand2));
4451     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4452     written |= (1 << 13);
4453     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4454   }
4455 }
4456 if (NEBI (tmp_postinc, 0)) {
4457 {
4458 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4459   tmp_addr = ADDSI (tmp_addr, 4);
4460 }
4461   {
4462     SI opval = tmp_addr;
4463     SET_H_GR (FLD (f_operand1), opval);
4464     written |= (1 << 9);
4465     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4466   }
4467 }
4468 }
4469 }
4470 }
4471  else if (EQSI (tmp_rno, 13)) {
4472 {
4473   SI tmp_addr;
4474   BI tmp_postinc;
4475   tmp_postinc = FLD (f_memmode);
4476   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4477 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4478 if (EQBI (CPU (h_pbit), 0)) {
4479 {
4480   {
4481     SI opval = GET_H_SR (FLD (f_operand2));
4482     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4483     written |= (1 << 13);
4484     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4485   }
4486   {
4487     BI opval = CPU (h_pbit);
4488     CPU (h_cbit) = opval;
4489     written |= (1 << 10);
4490     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4491   }
4492 }
4493 } else {
4494   {
4495     BI opval = 1;
4496     CPU (h_cbit) = opval;
4497     written |= (1 << 10);
4498     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4499   }
4500 }
4501 } else {
4502   {
4503     SI opval = GET_H_SR (FLD (f_operand2));
4504     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4505     written |= (1 << 13);
4506     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4507   }
4508 }
4509 if (NEBI (tmp_postinc, 0)) {
4510 {
4511 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4512   tmp_addr = ADDSI (tmp_addr, 4);
4513 }
4514   {
4515     SI opval = tmp_addr;
4516     SET_H_GR (FLD (f_operand1), opval);
4517     written |= (1 << 9);
4518     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4519   }
4520 }
4521 }
4522 }
4523 }
4524  else if (EQSI (tmp_rno, 14)) {
4525 {
4526   SI tmp_addr;
4527   BI tmp_postinc;
4528   tmp_postinc = FLD (f_memmode);
4529   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4530 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4531 if (EQBI (CPU (h_pbit), 0)) {
4532 {
4533   {
4534     SI opval = GET_H_SR (FLD (f_operand2));
4535     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4536     written |= (1 << 13);
4537     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4538   }
4539   {
4540     BI opval = CPU (h_pbit);
4541     CPU (h_cbit) = opval;
4542     written |= (1 << 10);
4543     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4544   }
4545 }
4546 } else {
4547   {
4548     BI opval = 1;
4549     CPU (h_cbit) = opval;
4550     written |= (1 << 10);
4551     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4552   }
4553 }
4554 } else {
4555   {
4556     SI opval = GET_H_SR (FLD (f_operand2));
4557     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4558     written |= (1 << 13);
4559     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4560   }
4561 }
4562 if (NEBI (tmp_postinc, 0)) {
4563 {
4564 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4565   tmp_addr = ADDSI (tmp_addr, 4);
4566 }
4567   {
4568     SI opval = tmp_addr;
4569     SET_H_GR (FLD (f_operand1), opval);
4570     written |= (1 << 9);
4571     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4572   }
4573 }
4574 }
4575 }
4576 }
4577  else if (EQSI (tmp_rno, 15)) {
4578 {
4579   SI tmp_addr;
4580   BI tmp_postinc;
4581   tmp_postinc = FLD (f_memmode);
4582   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4583 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4584 if (EQBI (CPU (h_pbit), 0)) {
4585 {
4586   {
4587     SI opval = GET_H_SR (FLD (f_operand2));
4588     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4589     written |= (1 << 13);
4590     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4591   }
4592   {
4593     BI opval = CPU (h_pbit);
4594     CPU (h_cbit) = opval;
4595     written |= (1 << 10);
4596     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4597   }
4598 }
4599 } else {
4600   {
4601     BI opval = 1;
4602     CPU (h_cbit) = opval;
4603     written |= (1 << 10);
4604     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4605   }
4606 }
4607 } else {
4608   {
4609     SI opval = GET_H_SR (FLD (f_operand2));
4610     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4611     written |= (1 << 13);
4612     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4613   }
4614 }
4615 if (NEBI (tmp_postinc, 0)) {
4616 {
4617 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4618   tmp_addr = ADDSI (tmp_addr, 4);
4619 }
4620   {
4621     SI opval = tmp_addr;
4622     SET_H_GR (FLD (f_operand1), opval);
4623     written |= (1 << 9);
4624     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4625   }
4626 }
4627 }
4628 }
4629 }
4630  else if (EQSI (tmp_rno, 0)) {
4631 {
4632   SI tmp_addr;
4633   BI tmp_postinc;
4634   tmp_postinc = FLD (f_memmode);
4635   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4636 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4637 if (EQBI (CPU (h_pbit), 0)) {
4638 {
4639   {
4640     QI opval = GET_H_SR (FLD (f_operand2));
4641     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4642     written |= (1 << 12);
4643     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4644   }
4645   {
4646     BI opval = CPU (h_pbit);
4647     CPU (h_cbit) = opval;
4648     written |= (1 << 10);
4649     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4650   }
4651 }
4652 } else {
4653   {
4654     BI opval = 1;
4655     CPU (h_cbit) = opval;
4656     written |= (1 << 10);
4657     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4658   }
4659 }
4660 } else {
4661   {
4662     QI opval = GET_H_SR (FLD (f_operand2));
4663     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4664     written |= (1 << 12);
4665     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4666   }
4667 }
4668 if (NEBI (tmp_postinc, 0)) {
4669 {
4670 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4671   tmp_addr = ADDSI (tmp_addr, 1);
4672 }
4673   {
4674     SI opval = tmp_addr;
4675     SET_H_GR (FLD (f_operand1), opval);
4676     written |= (1 << 9);
4677     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4678   }
4679 }
4680 }
4681 }
4682 }
4683  else if (EQSI (tmp_rno, 1)) {
4684 {
4685   SI tmp_addr;
4686   BI tmp_postinc;
4687   tmp_postinc = FLD (f_memmode);
4688   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4689 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4690 if (EQBI (CPU (h_pbit), 0)) {
4691 {
4692   {
4693     QI opval = GET_H_SR (FLD (f_operand2));
4694     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4695     written |= (1 << 12);
4696     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4697   }
4698   {
4699     BI opval = CPU (h_pbit);
4700     CPU (h_cbit) = opval;
4701     written |= (1 << 10);
4702     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4703   }
4704 }
4705 } else {
4706   {
4707     BI opval = 1;
4708     CPU (h_cbit) = opval;
4709     written |= (1 << 10);
4710     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4711   }
4712 }
4713 } else {
4714   {
4715     QI opval = GET_H_SR (FLD (f_operand2));
4716     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4717     written |= (1 << 12);
4718     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4719   }
4720 }
4721 if (NEBI (tmp_postinc, 0)) {
4722 {
4723 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4724   tmp_addr = ADDSI (tmp_addr, 1);
4725 }
4726   {
4727     SI opval = tmp_addr;
4728     SET_H_GR (FLD (f_operand1), opval);
4729     written |= (1 << 9);
4730     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4731   }
4732 }
4733 }
4734 }
4735 }
4736  else if (EQSI (tmp_rno, 4)) {
4737 {
4738   SI tmp_addr;
4739   BI tmp_postinc;
4740   tmp_postinc = FLD (f_memmode);
4741   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4742 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4743 if (EQBI (CPU (h_pbit), 0)) {
4744 {
4745   {
4746     HI opval = GET_H_SR (FLD (f_operand2));
4747     SETMEMHI (current_cpu, pc, tmp_addr, opval);
4748     written |= (1 << 11);
4749     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4750   }
4751   {
4752     BI opval = CPU (h_pbit);
4753     CPU (h_cbit) = opval;
4754     written |= (1 << 10);
4755     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4756   }
4757 }
4758 } else {
4759   {
4760     BI opval = 1;
4761     CPU (h_cbit) = opval;
4762     written |= (1 << 10);
4763     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4764   }
4765 }
4766 } else {
4767   {
4768     HI opval = GET_H_SR (FLD (f_operand2));
4769     SETMEMHI (current_cpu, pc, tmp_addr, opval);
4770     written |= (1 << 11);
4771     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4772   }
4773 }
4774 if (NEBI (tmp_postinc, 0)) {
4775 {
4776 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4777   tmp_addr = ADDSI (tmp_addr, 2);
4778 }
4779   {
4780     SI opval = tmp_addr;
4781     SET_H_GR (FLD (f_operand1), opval);
4782     written |= (1 << 9);
4783     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4784   }
4785 }
4786 }
4787 }
4788 }
4789  else if (EQSI (tmp_rno, 8)) {
4790 {
4791   SI tmp_addr;
4792   BI tmp_postinc;
4793   tmp_postinc = FLD (f_memmode);
4794   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4795 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4796 if (EQBI (CPU (h_pbit), 0)) {
4797 {
4798   {
4799     SI opval = GET_H_SR (FLD (f_operand2));
4800     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4801     written |= (1 << 13);
4802     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4803   }
4804   {
4805     BI opval = CPU (h_pbit);
4806     CPU (h_cbit) = opval;
4807     written |= (1 << 10);
4808     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4809   }
4810 }
4811 } else {
4812   {
4813     BI opval = 1;
4814     CPU (h_cbit) = opval;
4815     written |= (1 << 10);
4816     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4817   }
4818 }
4819 } else {
4820   {
4821     SI opval = GET_H_SR (FLD (f_operand2));
4822     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4823     written |= (1 << 13);
4824     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4825   }
4826 }
4827 if (NEBI (tmp_postinc, 0)) {
4828 {
4829 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4830   tmp_addr = ADDSI (tmp_addr, 4);
4831 }
4832   {
4833     SI opval = tmp_addr;
4834     SET_H_GR (FLD (f_operand1), opval);
4835     written |= (1 << 9);
4836     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4837   }
4838 }
4839 }
4840 }
4841 }
4842  else {
4843 cgen_rtx_error (current_cpu, "write from unimplemented special register");
4844 }
4845 {
4846   {
4847     BI opval = 0;
4848     CPU (h_xbit) = opval;
4849     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
4850   }
4851   {
4852     BI opval = 0;
4853     SET_H_INSN_PREFIXED_P (opval);
4854     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
4855   }
4856 }
4857 }
4858
4859   abuf->written = written;
4860 #undef FLD
4861 }
4862   NEXT (vpc);
4863
4864   CASE (sem, INSN_MOVE_SS_R) : /* move ${Ss},${Rd-sfield} */
4865 {
4866   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4867   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4868 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
4869   int UNUSED written = 0;
4870   IADDR UNUSED pc = abuf->addr;
4871   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4872
4873 {
4874   {
4875     SI opval = GET_H_SUPR (FLD (f_operand2));
4876     SET_H_GR (FLD (f_operand1), opval);
4877     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4878   }
4879 {
4880   {
4881     BI opval = 0;
4882     CPU (h_xbit) = opval;
4883     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
4884   }
4885   {
4886     BI opval = 0;
4887     SET_H_INSN_PREFIXED_P (opval);
4888     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
4889   }
4890 }
4891 }
4892
4893 #undef FLD
4894 }
4895   NEXT (vpc);
4896
4897   CASE (sem, INSN_MOVE_R_SS) : /* move ${Rs},${Sd} */
4898 {
4899   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4900   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4901 #define FLD(f) abuf->fields.sfmt_mcp.f
4902   int UNUSED written = 0;
4903   IADDR UNUSED pc = abuf->addr;
4904   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4905
4906 {
4907   {
4908     SI opval = GET_H_GR (FLD (f_operand1));
4909     SET_H_SUPR (FLD (f_operand2), opval);
4910     TRACE_RESULT (current_cpu, abuf, "supr", 'x', opval);
4911   }
4912 {
4913   {
4914     BI opval = 0;
4915     CPU (h_xbit) = opval;
4916     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
4917   }
4918   {
4919     BI opval = 0;
4920     SET_H_INSN_PREFIXED_P (opval);
4921     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
4922   }
4923 }
4924 }
4925
4926 #undef FLD
4927 }
4928   NEXT (vpc);
4929
4930   CASE (sem, INSN_MOVEM_R_M_V32) : /* movem ${Rs-dfield},[${Rd-sfield}${inc}] */
4931 {
4932   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4933   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4934 #define FLD(f) abuf->fields.sfmt_movem_r_m_v32.f
4935   int UNUSED written = 0;
4936   IADDR UNUSED pc = abuf->addr;
4937   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4938
4939 {
4940   SI tmp_addr;
4941   BI tmp_postinc;
4942   tmp_postinc = FLD (f_memmode);
4943 {
4944   SI tmp_dummy;
4945   tmp_dummy = GET_H_GR (FLD (f_operand2));
4946 }
4947   tmp_addr = GET_H_GR (FLD (f_operand1));
4948 {
4949 if (GESI (FLD (f_operand2), 0)) {
4950 {
4951   SI tmp_tmp;
4952   tmp_tmp = GET_H_GR (((UINT) 0));
4953   {
4954     SI opval = tmp_tmp;
4955     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4956     written |= (1 << 21);
4957     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4958   }
4959   tmp_addr = ADDSI (tmp_addr, 4);
4960 }
4961 }
4962 if (GESI (FLD (f_operand2), 1)) {
4963 {
4964   SI tmp_tmp;
4965   tmp_tmp = GET_H_GR (((UINT) 1));
4966   {
4967     SI opval = tmp_tmp;
4968     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4969     written |= (1 << 21);
4970     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4971   }
4972   tmp_addr = ADDSI (tmp_addr, 4);
4973 }
4974 }
4975 if (GESI (FLD (f_operand2), 2)) {
4976 {
4977   SI tmp_tmp;
4978   tmp_tmp = GET_H_GR (((UINT) 2));
4979   {
4980     SI opval = tmp_tmp;
4981     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4982     written |= (1 << 21);
4983     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4984   }
4985   tmp_addr = ADDSI (tmp_addr, 4);
4986 }
4987 }
4988 if (GESI (FLD (f_operand2), 3)) {
4989 {
4990   SI tmp_tmp;
4991   tmp_tmp = GET_H_GR (((UINT) 3));
4992   {
4993     SI opval = tmp_tmp;
4994     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4995     written |= (1 << 21);
4996     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4997   }
4998   tmp_addr = ADDSI (tmp_addr, 4);
4999 }
5000 }
5001 if (GESI (FLD (f_operand2), 4)) {
5002 {
5003   SI tmp_tmp;
5004   tmp_tmp = GET_H_GR (((UINT) 4));
5005   {
5006     SI opval = tmp_tmp;
5007     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5008     written |= (1 << 21);
5009     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5010   }
5011   tmp_addr = ADDSI (tmp_addr, 4);
5012 }
5013 }
5014 if (GESI (FLD (f_operand2), 5)) {
5015 {
5016   SI tmp_tmp;
5017   tmp_tmp = GET_H_GR (((UINT) 5));
5018   {
5019     SI opval = tmp_tmp;
5020     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5021     written |= (1 << 21);
5022     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5023   }
5024   tmp_addr = ADDSI (tmp_addr, 4);
5025 }
5026 }
5027 if (GESI (FLD (f_operand2), 6)) {
5028 {
5029   SI tmp_tmp;
5030   tmp_tmp = GET_H_GR (((UINT) 6));
5031   {
5032     SI opval = tmp_tmp;
5033     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5034     written |= (1 << 21);
5035     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5036   }
5037   tmp_addr = ADDSI (tmp_addr, 4);
5038 }
5039 }
5040 if (GESI (FLD (f_operand2), 7)) {
5041 {
5042   SI tmp_tmp;
5043   tmp_tmp = GET_H_GR (((UINT) 7));
5044   {
5045     SI opval = tmp_tmp;
5046     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5047     written |= (1 << 21);
5048     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5049   }
5050   tmp_addr = ADDSI (tmp_addr, 4);
5051 }
5052 }
5053 if (GESI (FLD (f_operand2), 8)) {
5054 {
5055   SI tmp_tmp;
5056   tmp_tmp = GET_H_GR (((UINT) 8));
5057   {
5058     SI opval = tmp_tmp;
5059     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5060     written |= (1 << 21);
5061     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5062   }
5063   tmp_addr = ADDSI (tmp_addr, 4);
5064 }
5065 }
5066 if (GESI (FLD (f_operand2), 9)) {
5067 {
5068   SI tmp_tmp;
5069   tmp_tmp = GET_H_GR (((UINT) 9));
5070   {
5071     SI opval = tmp_tmp;
5072     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5073     written |= (1 << 21);
5074     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5075   }
5076   tmp_addr = ADDSI (tmp_addr, 4);
5077 }
5078 }
5079 if (GESI (FLD (f_operand2), 10)) {
5080 {
5081   SI tmp_tmp;
5082   tmp_tmp = GET_H_GR (((UINT) 10));
5083   {
5084     SI opval = tmp_tmp;
5085     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5086     written |= (1 << 21);
5087     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5088   }
5089   tmp_addr = ADDSI (tmp_addr, 4);
5090 }
5091 }
5092 if (GESI (FLD (f_operand2), 11)) {
5093 {
5094   SI tmp_tmp;
5095   tmp_tmp = GET_H_GR (((UINT) 11));
5096   {
5097     SI opval = tmp_tmp;
5098     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5099     written |= (1 << 21);
5100     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5101   }
5102   tmp_addr = ADDSI (tmp_addr, 4);
5103 }
5104 }
5105 if (GESI (FLD (f_operand2), 12)) {
5106 {
5107   SI tmp_tmp;
5108   tmp_tmp = GET_H_GR (((UINT) 12));
5109   {
5110     SI opval = tmp_tmp;
5111     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5112     written |= (1 << 21);
5113     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5114   }
5115   tmp_addr = ADDSI (tmp_addr, 4);
5116 }
5117 }
5118 if (GESI (FLD (f_operand2), 13)) {
5119 {
5120   SI tmp_tmp;
5121   tmp_tmp = GET_H_GR (((UINT) 13));
5122   {
5123     SI opval = tmp_tmp;
5124     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5125     written |= (1 << 21);
5126     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5127   }
5128   tmp_addr = ADDSI (tmp_addr, 4);
5129 }
5130 }
5131 if (GESI (FLD (f_operand2), 14)) {
5132 {
5133   SI tmp_tmp;
5134   tmp_tmp = GET_H_GR (((UINT) 14));
5135   {
5136     SI opval = tmp_tmp;
5137     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5138     written |= (1 << 21);
5139     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5140   }
5141   tmp_addr = ADDSI (tmp_addr, 4);
5142 }
5143 }
5144 if (GESI (FLD (f_operand2), 15)) {
5145 {
5146   SI tmp_tmp;
5147   tmp_tmp = GET_H_GR (((UINT) 15));
5148   {
5149     SI opval = tmp_tmp;
5150     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5151     written |= (1 << 21);
5152     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5153   }
5154   tmp_addr = ADDSI (tmp_addr, 4);
5155 }
5156 }
5157 }
5158 if (NEBI (tmp_postinc, 0)) {
5159   {
5160     SI opval = tmp_addr;
5161     SET_H_GR (FLD (f_operand1), opval);
5162     written |= (1 << 20);
5163     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5164   }
5165 }
5166 {
5167   {
5168     BI opval = 0;
5169     CPU (h_xbit) = opval;
5170     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5171   }
5172   {
5173     BI opval = 0;
5174     SET_H_INSN_PREFIXED_P (opval);
5175     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5176   }
5177 }
5178 }
5179
5180   abuf->written = written;
5181 #undef FLD
5182 }
5183   NEXT (vpc);
5184
5185   CASE (sem, INSN_MOVEM_M_R_V32) : /* movem [${Rs}${inc}],${Rd} */
5186 {
5187   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5188   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5189 #define FLD(f) abuf->fields.sfmt_movem_m_r_v32.f
5190   int UNUSED written = 0;
5191   IADDR UNUSED pc = abuf->addr;
5192   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5193
5194 {
5195   SI tmp_addr;
5196   BI tmp_postinc;
5197   tmp_postinc = FLD (f_memmode);
5198   tmp_addr = GET_H_GR (FLD (f_operand1));
5199 {
5200   SI tmp_dummy;
5201   tmp_dummy = GET_H_GR (FLD (f_operand2));
5202 }
5203 {
5204 if (GESI (FLD (f_operand2), 0)) {
5205 {
5206   SI tmp_tmp;
5207   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5208   {
5209     SI opval = tmp_tmp;
5210     SET_H_GR (((UINT) 0), opval);
5211     written |= (1 << 6);
5212     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5213   }
5214   tmp_addr = ADDSI (tmp_addr, 4);
5215 }
5216 }
5217 if (GESI (FLD (f_operand2), 1)) {
5218 {
5219   SI tmp_tmp;
5220   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5221   {
5222     SI opval = tmp_tmp;
5223     SET_H_GR (((UINT) 1), opval);
5224     written |= (1 << 7);
5225     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5226   }
5227   tmp_addr = ADDSI (tmp_addr, 4);
5228 }
5229 }
5230 if (GESI (FLD (f_operand2), 2)) {
5231 {
5232   SI tmp_tmp;
5233   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5234   {
5235     SI opval = tmp_tmp;
5236     SET_H_GR (((UINT) 2), opval);
5237     written |= (1 << 14);
5238     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5239   }
5240   tmp_addr = ADDSI (tmp_addr, 4);
5241 }
5242 }
5243 if (GESI (FLD (f_operand2), 3)) {
5244 {
5245   SI tmp_tmp;
5246   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5247   {
5248     SI opval = tmp_tmp;
5249     SET_H_GR (((UINT) 3), opval);
5250     written |= (1 << 15);
5251     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5252   }
5253   tmp_addr = ADDSI (tmp_addr, 4);
5254 }
5255 }
5256 if (GESI (FLD (f_operand2), 4)) {
5257 {
5258   SI tmp_tmp;
5259   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5260   {
5261     SI opval = tmp_tmp;
5262     SET_H_GR (((UINT) 4), opval);
5263     written |= (1 << 16);
5264     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5265   }
5266   tmp_addr = ADDSI (tmp_addr, 4);
5267 }
5268 }
5269 if (GESI (FLD (f_operand2), 5)) {
5270 {
5271   SI tmp_tmp;
5272   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5273   {
5274     SI opval = tmp_tmp;
5275     SET_H_GR (((UINT) 5), opval);
5276     written |= (1 << 17);
5277     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5278   }
5279   tmp_addr = ADDSI (tmp_addr, 4);
5280 }
5281 }
5282 if (GESI (FLD (f_operand2), 6)) {
5283 {
5284   SI tmp_tmp;
5285   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5286   {
5287     SI opval = tmp_tmp;
5288     SET_H_GR (((UINT) 6), opval);
5289     written |= (1 << 18);
5290     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5291   }
5292   tmp_addr = ADDSI (tmp_addr, 4);
5293 }
5294 }
5295 if (GESI (FLD (f_operand2), 7)) {
5296 {
5297   SI tmp_tmp;
5298   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5299   {
5300     SI opval = tmp_tmp;
5301     SET_H_GR (((UINT) 7), opval);
5302     written |= (1 << 19);
5303     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5304   }
5305   tmp_addr = ADDSI (tmp_addr, 4);
5306 }
5307 }
5308 if (GESI (FLD (f_operand2), 8)) {
5309 {
5310   SI tmp_tmp;
5311   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5312   {
5313     SI opval = tmp_tmp;
5314     SET_H_GR (((UINT) 8), opval);
5315     written |= (1 << 20);
5316     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5317   }
5318   tmp_addr = ADDSI (tmp_addr, 4);
5319 }
5320 }
5321 if (GESI (FLD (f_operand2), 9)) {
5322 {
5323   SI tmp_tmp;
5324   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5325   {
5326     SI opval = tmp_tmp;
5327     SET_H_GR (((UINT) 9), opval);
5328     written |= (1 << 21);
5329     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5330   }
5331   tmp_addr = ADDSI (tmp_addr, 4);
5332 }
5333 }
5334 if (GESI (FLD (f_operand2), 10)) {
5335 {
5336   SI tmp_tmp;
5337   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5338   {
5339     SI opval = tmp_tmp;
5340     SET_H_GR (((UINT) 10), opval);
5341     written |= (1 << 8);
5342     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5343   }
5344   tmp_addr = ADDSI (tmp_addr, 4);
5345 }
5346 }
5347 if (GESI (FLD (f_operand2), 11)) {
5348 {
5349   SI tmp_tmp;
5350   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5351   {
5352     SI opval = tmp_tmp;
5353     SET_H_GR (((UINT) 11), opval);
5354     written |= (1 << 9);
5355     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5356   }
5357   tmp_addr = ADDSI (tmp_addr, 4);
5358 }
5359 }
5360 if (GESI (FLD (f_operand2), 12)) {
5361 {
5362   SI tmp_tmp;
5363   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5364   {
5365     SI opval = tmp_tmp;
5366     SET_H_GR (((UINT) 12), opval);
5367     written |= (1 << 10);
5368     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5369   }
5370   tmp_addr = ADDSI (tmp_addr, 4);
5371 }
5372 }
5373 if (GESI (FLD (f_operand2), 13)) {
5374 {
5375   SI tmp_tmp;
5376   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5377   {
5378     SI opval = tmp_tmp;
5379     SET_H_GR (((UINT) 13), opval);
5380     written |= (1 << 11);
5381     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5382   }
5383   tmp_addr = ADDSI (tmp_addr, 4);
5384 }
5385 }
5386 if (GESI (FLD (f_operand2), 14)) {
5387 {
5388   SI tmp_tmp;
5389   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5390   {
5391     SI opval = tmp_tmp;
5392     SET_H_GR (((UINT) 14), opval);
5393     written |= (1 << 12);
5394     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5395   }
5396   tmp_addr = ADDSI (tmp_addr, 4);
5397 }
5398 }
5399 if (GESI (FLD (f_operand2), 15)) {
5400 {
5401   SI tmp_tmp;
5402   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5403   {
5404     SI opval = tmp_tmp;
5405     SET_H_GR (((UINT) 15), opval);
5406     written |= (1 << 13);
5407     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5408   }
5409   tmp_addr = ADDSI (tmp_addr, 4);
5410 }
5411 }
5412 }
5413 if (NEBI (tmp_postinc, 0)) {
5414   {
5415     SI opval = tmp_addr;
5416     SET_H_GR (FLD (f_operand1), opval);
5417     written |= (1 << 5);
5418     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5419   }
5420 }
5421 {
5422   {
5423     BI opval = 0;
5424     CPU (h_xbit) = opval;
5425     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5426   }
5427   {
5428     BI opval = 0;
5429     SET_H_INSN_PREFIXED_P (opval);
5430     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5431   }
5432 }
5433 }
5434
5435   abuf->written = written;
5436 #undef FLD
5437 }
5438   NEXT (vpc);
5439
5440   CASE (sem, INSN_ADD_B_R) : /* add.b $Rs,$Rd */
5441 {
5442   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5443   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5444 #define FLD(f) abuf->fields.sfmt_addc_m.f
5445   int UNUSED written = 0;
5446   IADDR UNUSED pc = abuf->addr;
5447   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5448
5449 {
5450   QI tmp_tmpopd;
5451   QI tmp_tmpops;
5452   BI tmp_carry;
5453   QI tmp_newval;
5454   tmp_tmpops = GET_H_GR (FLD (f_operand1));
5455   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5456   tmp_carry = CPU (h_cbit);
5457   tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5458 {
5459   SI tmp_oldregval;
5460   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
5461   {
5462     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
5463     SET_H_GR (FLD (f_operand2), opval);
5464     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5465   }
5466 }
5467 {
5468   {
5469     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
5470     CPU (h_cbit) = opval;
5471     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5472   }
5473   {
5474     BI opval = LTQI (tmp_newval, 0);
5475     CPU (h_nbit) = opval;
5476     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5477   }
5478   {
5479     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5480     CPU (h_zbit) = opval;
5481     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5482   }
5483   {
5484     BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
5485     CPU (h_vbit) = opval;
5486     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5487   }
5488 {
5489   {
5490     BI opval = 0;
5491     CPU (h_xbit) = opval;
5492     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5493   }
5494   {
5495     BI opval = 0;
5496     SET_H_INSN_PREFIXED_P (opval);
5497     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5498   }
5499 }
5500 }
5501 }
5502
5503 #undef FLD
5504 }
5505   NEXT (vpc);
5506
5507   CASE (sem, INSN_ADD_W_R) : /* add.w $Rs,$Rd */
5508 {
5509   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5510   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5511 #define FLD(f) abuf->fields.sfmt_addc_m.f
5512   int UNUSED written = 0;
5513   IADDR UNUSED pc = abuf->addr;
5514   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5515
5516 {
5517   HI tmp_tmpopd;
5518   HI tmp_tmpops;
5519   BI tmp_carry;
5520   HI tmp_newval;
5521   tmp_tmpops = GET_H_GR (FLD (f_operand1));
5522   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5523   tmp_carry = CPU (h_cbit);
5524   tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5525 {
5526   SI tmp_oldregval;
5527   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
5528   {
5529     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
5530     SET_H_GR (FLD (f_operand2), opval);
5531     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5532   }
5533 }
5534 {
5535   {
5536     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
5537     CPU (h_cbit) = opval;
5538     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5539   }
5540   {
5541     BI opval = LTHI (tmp_newval, 0);
5542     CPU (h_nbit) = opval;
5543     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5544   }
5545   {
5546     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5547     CPU (h_zbit) = opval;
5548     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5549   }
5550   {
5551     BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
5552     CPU (h_vbit) = opval;
5553     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5554   }
5555 {
5556   {
5557     BI opval = 0;
5558     CPU (h_xbit) = opval;
5559     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5560   }
5561   {
5562     BI opval = 0;
5563     SET_H_INSN_PREFIXED_P (opval);
5564     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5565   }
5566 }
5567 }
5568 }
5569
5570 #undef FLD
5571 }
5572   NEXT (vpc);
5573
5574   CASE (sem, INSN_ADD_D_R) : /* add.d $Rs,$Rd */
5575 {
5576   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5577   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5578 #define FLD(f) abuf->fields.sfmt_addc_m.f
5579   int UNUSED written = 0;
5580   IADDR UNUSED pc = abuf->addr;
5581   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5582
5583 {
5584   SI tmp_tmpopd;
5585   SI tmp_tmpops;
5586   BI tmp_carry;
5587   SI tmp_newval;
5588   tmp_tmpops = GET_H_GR (FLD (f_operand1));
5589   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5590   tmp_carry = CPU (h_cbit);
5591   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5592   {
5593     SI opval = tmp_newval;
5594     SET_H_GR (FLD (f_operand2), opval);
5595     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5596   }
5597 {
5598   {
5599     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
5600     CPU (h_cbit) = opval;
5601     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5602   }
5603   {
5604     BI opval = LTSI (tmp_newval, 0);
5605     CPU (h_nbit) = opval;
5606     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5607   }
5608   {
5609     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5610     CPU (h_zbit) = opval;
5611     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5612   }
5613   {
5614     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
5615     CPU (h_vbit) = opval;
5616     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5617   }
5618 {
5619   {
5620     BI opval = 0;
5621     CPU (h_xbit) = opval;
5622     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5623   }
5624   {
5625     BI opval = 0;
5626     SET_H_INSN_PREFIXED_P (opval);
5627     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5628   }
5629 }
5630 }
5631 }
5632
5633 #undef FLD
5634 }
5635   NEXT (vpc);
5636
5637   CASE (sem, INSN_ADD_M_B_M) : /* add-m.b [${Rs}${inc}],${Rd} */
5638 {
5639   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5640   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5641 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
5642   int UNUSED written = 0;
5643   IADDR UNUSED pc = abuf->addr;
5644   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5645
5646 {
5647   QI tmp_tmpopd;
5648   QI tmp_tmpops;
5649   BI tmp_carry;
5650   QI tmp_newval;
5651   tmp_tmpops = ({   SI tmp_addr;
5652   QI tmp_tmp_mem;
5653   BI tmp_postinc;
5654   tmp_postinc = FLD (f_memmode);
5655 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
5656 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
5657 ; if (NEBI (tmp_postinc, 0)) {
5658 {
5659 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
5660   tmp_addr = ADDSI (tmp_addr, 1);
5661 }
5662   {
5663     SI opval = tmp_addr;
5664     SET_H_GR (FLD (f_operand1), opval);
5665     written |= (1 << 12);
5666     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5667   }
5668 }
5669 }
5670 ; tmp_tmp_mem; });
5671   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5672   tmp_carry = CPU (h_cbit);
5673   tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5674 {
5675   SI tmp_oldregval;
5676   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
5677   {
5678     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
5679     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
5680     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5681   }
5682 }
5683 {
5684   {
5685     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
5686     CPU (h_cbit) = opval;
5687     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5688   }
5689   {
5690     BI opval = LTQI (tmp_newval, 0);
5691     CPU (h_nbit) = opval;
5692     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5693   }
5694   {
5695     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5696     CPU (h_zbit) = opval;
5697     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5698   }
5699   {
5700     BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
5701     CPU (h_vbit) = opval;
5702     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5703   }
5704 {
5705   {
5706     BI opval = 0;
5707     CPU (h_xbit) = opval;
5708     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5709   }
5710   {
5711     BI opval = 0;
5712     SET_H_INSN_PREFIXED_P (opval);
5713     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5714   }
5715 }
5716 }
5717 }
5718
5719   abuf->written = written;
5720 #undef FLD
5721 }
5722   NEXT (vpc);
5723
5724   CASE (sem, INSN_ADD_M_W_M) : /* add-m.w [${Rs}${inc}],${Rd} */
5725 {
5726   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5727   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5728 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
5729   int UNUSED written = 0;
5730   IADDR UNUSED pc = abuf->addr;
5731   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5732
5733 {
5734   HI tmp_tmpopd;
5735   HI tmp_tmpops;
5736   BI tmp_carry;
5737   HI tmp_newval;
5738   tmp_tmpops = ({   SI tmp_addr;
5739   HI tmp_tmp_mem;
5740   BI tmp_postinc;
5741   tmp_postinc = FLD (f_memmode);
5742 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
5743 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
5744 ; if (NEBI (tmp_postinc, 0)) {
5745 {
5746 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
5747   tmp_addr = ADDSI (tmp_addr, 2);
5748 }
5749   {
5750     SI opval = tmp_addr;
5751     SET_H_GR (FLD (f_operand1), opval);
5752     written |= (1 << 12);
5753     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5754   }
5755 }
5756 }
5757 ; tmp_tmp_mem; });
5758   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5759   tmp_carry = CPU (h_cbit);
5760   tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5761 {
5762   SI tmp_oldregval;
5763   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
5764   {
5765     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
5766     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
5767     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5768   }
5769 }
5770 {
5771   {
5772     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
5773     CPU (h_cbit) = opval;
5774     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5775   }
5776   {
5777     BI opval = LTHI (tmp_newval, 0);
5778     CPU (h_nbit) = opval;
5779     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5780   }
5781   {
5782     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5783     CPU (h_zbit) = opval;
5784     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5785   }
5786   {
5787     BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
5788     CPU (h_vbit) = opval;
5789     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5790   }
5791 {
5792   {
5793     BI opval = 0;
5794     CPU (h_xbit) = opval;
5795     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5796   }
5797   {
5798     BI opval = 0;
5799     SET_H_INSN_PREFIXED_P (opval);
5800     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5801   }
5802 }
5803 }
5804 }
5805
5806   abuf->written = written;
5807 #undef FLD
5808 }
5809   NEXT (vpc);
5810
5811   CASE (sem, INSN_ADD_M_D_M) : /* add-m.d [${Rs}${inc}],${Rd} */
5812 {
5813   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5814   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5815 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
5816   int UNUSED written = 0;
5817   IADDR UNUSED pc = abuf->addr;
5818   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5819
5820 {
5821   SI tmp_tmpopd;
5822   SI tmp_tmpops;
5823   BI tmp_carry;
5824   SI tmp_newval;
5825   tmp_tmpops = ({   SI tmp_addr;
5826   SI tmp_tmp_mem;
5827   BI tmp_postinc;
5828   tmp_postinc = FLD (f_memmode);
5829 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
5830 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
5831 ; if (NEBI (tmp_postinc, 0)) {
5832 {
5833 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
5834   tmp_addr = ADDSI (tmp_addr, 4);
5835 }
5836   {
5837     SI opval = tmp_addr;
5838     SET_H_GR (FLD (f_operand1), opval);
5839     written |= (1 << 11);
5840     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5841   }
5842 }
5843 }
5844 ; tmp_tmp_mem; });
5845   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5846   tmp_carry = CPU (h_cbit);
5847   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5848   {
5849     SI opval = tmp_newval;
5850     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
5851     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5852   }
5853 {
5854   {
5855     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
5856     CPU (h_cbit) = opval;
5857     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5858   }
5859   {
5860     BI opval = LTSI (tmp_newval, 0);
5861     CPU (h_nbit) = opval;
5862     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5863   }
5864   {
5865     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5866     CPU (h_zbit) = opval;
5867     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5868   }
5869   {
5870     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
5871     CPU (h_vbit) = opval;
5872     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5873   }
5874 {
5875   {
5876     BI opval = 0;
5877     CPU (h_xbit) = opval;
5878     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5879   }
5880   {
5881     BI opval = 0;
5882     SET_H_INSN_PREFIXED_P (opval);
5883     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5884   }
5885 }
5886 }
5887 }
5888
5889   abuf->written = written;
5890 #undef FLD
5891 }
5892   NEXT (vpc);
5893
5894   CASE (sem, INSN_ADDCBR) : /* add.b ${sconst8}],${Rd} */
5895 {
5896   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5897   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5898 #define FLD(f) abuf->fields.sfmt_addcbr.f
5899   int UNUSED written = 0;
5900   IADDR UNUSED pc = abuf->addr;
5901   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
5902
5903 {
5904   QI tmp_tmpopd;
5905   QI tmp_tmpops;
5906   BI tmp_carry;
5907   QI tmp_newval;
5908   tmp_tmpops = FLD (f_indir_pc__byte);
5909   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5910   tmp_carry = CPU (h_cbit);
5911   tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5912 {
5913   SI tmp_oldregval;
5914   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
5915   {
5916     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
5917     SET_H_GR (FLD (f_operand2), opval);
5918     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5919   }
5920 }
5921 {
5922   {
5923     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
5924     CPU (h_cbit) = opval;
5925     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5926   }
5927   {
5928     BI opval = LTQI (tmp_newval, 0);
5929     CPU (h_nbit) = opval;
5930     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5931   }
5932   {
5933     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5934     CPU (h_zbit) = opval;
5935     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5936   }
5937   {
5938     BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
5939     CPU (h_vbit) = opval;
5940     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5941   }
5942 {
5943   {
5944     BI opval = 0;
5945     CPU (h_xbit) = opval;
5946     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5947   }
5948   {
5949     BI opval = 0;
5950     SET_H_INSN_PREFIXED_P (opval);
5951     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5952   }
5953 }
5954 }
5955 }
5956
5957 #undef FLD
5958 }
5959   NEXT (vpc);
5960
5961   CASE (sem, INSN_ADDCWR) : /* add.w ${sconst16}],${Rd} */
5962 {
5963   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5964   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5965 #define FLD(f) abuf->fields.sfmt_addcwr.f
5966   int UNUSED written = 0;
5967   IADDR UNUSED pc = abuf->addr;
5968   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
5969
5970 {
5971   HI tmp_tmpopd;
5972   HI tmp_tmpops;
5973   BI tmp_carry;
5974   HI tmp_newval;
5975   tmp_tmpops = FLD (f_indir_pc__word);
5976   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5977   tmp_carry = CPU (h_cbit);
5978   tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5979 {
5980   SI tmp_oldregval;
5981   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
5982   {
5983     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
5984     SET_H_GR (FLD (f_operand2), opval);
5985     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5986   }
5987 }
5988 {
5989   {
5990     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
5991     CPU (h_cbit) = opval;
5992     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5993   }
5994   {
5995     BI opval = LTHI (tmp_newval, 0);
5996     CPU (h_nbit) = opval;
5997     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5998   }
5999   {
6000     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6001     CPU (h_zbit) = opval;
6002     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6003   }
6004   {
6005     BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
6006     CPU (h_vbit) = opval;
6007     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6008   }
6009 {
6010   {
6011     BI opval = 0;
6012     CPU (h_xbit) = opval;
6013     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6014   }
6015   {
6016     BI opval = 0;
6017     SET_H_INSN_PREFIXED_P (opval);
6018     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6019   }
6020 }
6021 }
6022 }
6023
6024 #undef FLD
6025 }
6026   NEXT (vpc);
6027
6028   CASE (sem, INSN_ADDCDR) : /* add.d ${const32}],${Rd} */
6029 {
6030   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6031   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6032 #define FLD(f) abuf->fields.sfmt_addcdr.f
6033   int UNUSED written = 0;
6034   IADDR UNUSED pc = abuf->addr;
6035   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
6036
6037 {
6038   SI tmp_tmpopd;
6039   SI tmp_tmpops;
6040   BI tmp_carry;
6041   SI tmp_newval;
6042   tmp_tmpops = FLD (f_indir_pc__dword);
6043   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6044   tmp_carry = CPU (h_cbit);
6045   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6046   {
6047     SI opval = tmp_newval;
6048     SET_H_GR (FLD (f_operand2), opval);
6049     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6050   }
6051 {
6052   {
6053     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6054     CPU (h_cbit) = opval;
6055     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6056   }
6057   {
6058     BI opval = LTSI (tmp_newval, 0);
6059     CPU (h_nbit) = opval;
6060     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6061   }
6062   {
6063     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6064     CPU (h_zbit) = opval;
6065     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6066   }
6067   {
6068     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6069     CPU (h_vbit) = opval;
6070     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6071   }
6072 {
6073   {
6074     BI opval = 0;
6075     CPU (h_xbit) = opval;
6076     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6077   }
6078   {
6079     BI opval = 0;
6080     SET_H_INSN_PREFIXED_P (opval);
6081     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6082   }
6083 }
6084 }
6085 }
6086
6087 #undef FLD
6088 }
6089   NEXT (vpc);
6090
6091   CASE (sem, INSN_ADDS_B_R) : /* adds.b $Rs,$Rd */
6092 {
6093   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6094   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6095 #define FLD(f) abuf->fields.sfmt_addc_m.f
6096   int UNUSED written = 0;
6097   IADDR UNUSED pc = abuf->addr;
6098   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6099
6100 {
6101   SI tmp_tmpopd;
6102   SI tmp_tmpops;
6103   BI tmp_carry;
6104   SI tmp_newval;
6105   tmp_tmpops = EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
6106   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6107   tmp_carry = CPU (h_cbit);
6108   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6109   {
6110     SI opval = tmp_newval;
6111     SET_H_GR (FLD (f_operand2), opval);
6112     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6113   }
6114 {
6115   {
6116     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6117     CPU (h_cbit) = opval;
6118     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6119   }
6120   {
6121     BI opval = LTSI (tmp_newval, 0);
6122     CPU (h_nbit) = opval;
6123     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6124   }
6125   {
6126     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6127     CPU (h_zbit) = opval;
6128     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6129   }
6130   {
6131     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6132     CPU (h_vbit) = opval;
6133     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6134   }
6135 {
6136   {
6137     BI opval = 0;
6138     CPU (h_xbit) = opval;
6139     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6140   }
6141   {
6142     BI opval = 0;
6143     SET_H_INSN_PREFIXED_P (opval);
6144     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6145   }
6146 }
6147 }
6148 }
6149
6150 #undef FLD
6151 }
6152   NEXT (vpc);
6153
6154   CASE (sem, INSN_ADDS_W_R) : /* adds.w $Rs,$Rd */
6155 {
6156   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6157   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6158 #define FLD(f) abuf->fields.sfmt_addc_m.f
6159   int UNUSED written = 0;
6160   IADDR UNUSED pc = abuf->addr;
6161   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6162
6163 {
6164   SI tmp_tmpopd;
6165   SI tmp_tmpops;
6166   BI tmp_carry;
6167   SI tmp_newval;
6168   tmp_tmpops = EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
6169   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6170   tmp_carry = CPU (h_cbit);
6171   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6172   {
6173     SI opval = tmp_newval;
6174     SET_H_GR (FLD (f_operand2), opval);
6175     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6176   }
6177 {
6178   {
6179     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6180     CPU (h_cbit) = opval;
6181     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6182   }
6183   {
6184     BI opval = LTSI (tmp_newval, 0);
6185     CPU (h_nbit) = opval;
6186     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6187   }
6188   {
6189     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6190     CPU (h_zbit) = opval;
6191     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6192   }
6193   {
6194     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6195     CPU (h_vbit) = opval;
6196     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6197   }
6198 {
6199   {
6200     BI opval = 0;
6201     CPU (h_xbit) = opval;
6202     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6203   }
6204   {
6205     BI opval = 0;
6206     SET_H_INSN_PREFIXED_P (opval);
6207     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6208   }
6209 }
6210 }
6211 }
6212
6213 #undef FLD
6214 }
6215   NEXT (vpc);
6216
6217   CASE (sem, INSN_ADDS_M_B_M) : /* adds-m.b [${Rs}${inc}],$Rd */
6218 {
6219   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6220   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6221 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6222   int UNUSED written = 0;
6223   IADDR UNUSED pc = abuf->addr;
6224   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6225
6226 {
6227   SI tmp_tmpopd;
6228   SI tmp_tmpops;
6229   BI tmp_carry;
6230   SI tmp_newval;
6231   tmp_tmpops = EXTQISI (({   SI tmp_addr;
6232   QI tmp_tmp_mem;
6233   BI tmp_postinc;
6234   tmp_postinc = FLD (f_memmode);
6235 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
6236 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
6237 ; if (NEBI (tmp_postinc, 0)) {
6238 {
6239 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6240   tmp_addr = ADDSI (tmp_addr, 1);
6241 }
6242   {
6243     SI opval = tmp_addr;
6244     SET_H_GR (FLD (f_operand1), opval);
6245     written |= (1 << 11);
6246     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6247   }
6248 }
6249 }
6250 ; tmp_tmp_mem; }));
6251   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6252   tmp_carry = CPU (h_cbit);
6253   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6254   {
6255     SI opval = tmp_newval;
6256     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6257     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6258   }
6259 {
6260   {
6261     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6262     CPU (h_cbit) = opval;
6263     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6264   }
6265   {
6266     BI opval = LTSI (tmp_newval, 0);
6267     CPU (h_nbit) = opval;
6268     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6269   }
6270   {
6271     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6272     CPU (h_zbit) = opval;
6273     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6274   }
6275   {
6276     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6277     CPU (h_vbit) = opval;
6278     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6279   }
6280 {
6281   {
6282     BI opval = 0;
6283     CPU (h_xbit) = opval;
6284     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6285   }
6286   {
6287     BI opval = 0;
6288     SET_H_INSN_PREFIXED_P (opval);
6289     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6290   }
6291 }
6292 }
6293 }
6294
6295   abuf->written = written;
6296 #undef FLD
6297 }
6298   NEXT (vpc);
6299
6300   CASE (sem, INSN_ADDS_M_W_M) : /* adds-m.w [${Rs}${inc}],$Rd */
6301 {
6302   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6303   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6304 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6305   int UNUSED written = 0;
6306   IADDR UNUSED pc = abuf->addr;
6307   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6308
6309 {
6310   SI tmp_tmpopd;
6311   SI tmp_tmpops;
6312   BI tmp_carry;
6313   SI tmp_newval;
6314   tmp_tmpops = EXTHISI (({   SI tmp_addr;
6315   HI tmp_tmp_mem;
6316   BI tmp_postinc;
6317   tmp_postinc = FLD (f_memmode);
6318 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
6319 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
6320 ; if (NEBI (tmp_postinc, 0)) {
6321 {
6322 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6323   tmp_addr = ADDSI (tmp_addr, 2);
6324 }
6325   {
6326     SI opval = tmp_addr;
6327     SET_H_GR (FLD (f_operand1), opval);
6328     written |= (1 << 11);
6329     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6330   }
6331 }
6332 }
6333 ; tmp_tmp_mem; }));
6334   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6335   tmp_carry = CPU (h_cbit);
6336   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6337   {
6338     SI opval = tmp_newval;
6339     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6340     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6341   }
6342 {
6343   {
6344     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6345     CPU (h_cbit) = opval;
6346     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6347   }
6348   {
6349     BI opval = LTSI (tmp_newval, 0);
6350     CPU (h_nbit) = opval;
6351     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6352   }
6353   {
6354     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6355     CPU (h_zbit) = opval;
6356     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6357   }
6358   {
6359     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6360     CPU (h_vbit) = opval;
6361     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6362   }
6363 {
6364   {
6365     BI opval = 0;
6366     CPU (h_xbit) = opval;
6367     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6368   }
6369   {
6370     BI opval = 0;
6371     SET_H_INSN_PREFIXED_P (opval);
6372     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6373   }
6374 }
6375 }
6376 }
6377
6378   abuf->written = written;
6379 #undef FLD
6380 }
6381   NEXT (vpc);
6382
6383   CASE (sem, INSN_ADDSCBR) : /* [${Rs}${inc}],$Rd */
6384 {
6385   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6386   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6387 #define FLD(f) abuf->fields.sfmt_addcbr.f
6388   int UNUSED written = 0;
6389   IADDR UNUSED pc = abuf->addr;
6390   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6391
6392 {
6393   SI tmp_tmpopd;
6394   SI tmp_tmpops;
6395   BI tmp_carry;
6396   SI tmp_newval;
6397   tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
6398   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6399   tmp_carry = CPU (h_cbit);
6400   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6401   {
6402     SI opval = tmp_newval;
6403     SET_H_GR (FLD (f_operand2), opval);
6404     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6405   }
6406 {
6407   {
6408     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6409     CPU (h_cbit) = opval;
6410     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6411   }
6412   {
6413     BI opval = LTSI (tmp_newval, 0);
6414     CPU (h_nbit) = opval;
6415     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6416   }
6417   {
6418     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6419     CPU (h_zbit) = opval;
6420     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6421   }
6422   {
6423     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6424     CPU (h_vbit) = opval;
6425     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6426   }
6427 {
6428   {
6429     BI opval = 0;
6430     CPU (h_xbit) = opval;
6431     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6432   }
6433   {
6434     BI opval = 0;
6435     SET_H_INSN_PREFIXED_P (opval);
6436     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6437   }
6438 }
6439 }
6440 }
6441
6442 #undef FLD
6443 }
6444   NEXT (vpc);
6445
6446   CASE (sem, INSN_ADDSCWR) : /* [${Rs}${inc}],$Rd */
6447 {
6448   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6449   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6450 #define FLD(f) abuf->fields.sfmt_addcwr.f
6451   int UNUSED written = 0;
6452   IADDR UNUSED pc = abuf->addr;
6453   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6454
6455 {
6456   SI tmp_tmpopd;
6457   SI tmp_tmpops;
6458   BI tmp_carry;
6459   SI tmp_newval;
6460   tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
6461   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6462   tmp_carry = CPU (h_cbit);
6463   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6464   {
6465     SI opval = tmp_newval;
6466     SET_H_GR (FLD (f_operand2), opval);
6467     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6468   }
6469 {
6470   {
6471     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6472     CPU (h_cbit) = opval;
6473     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6474   }
6475   {
6476     BI opval = LTSI (tmp_newval, 0);
6477     CPU (h_nbit) = opval;
6478     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6479   }
6480   {
6481     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6482     CPU (h_zbit) = opval;
6483     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6484   }
6485   {
6486     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6487     CPU (h_vbit) = opval;
6488     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6489   }
6490 {
6491   {
6492     BI opval = 0;
6493     CPU (h_xbit) = opval;
6494     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6495   }
6496   {
6497     BI opval = 0;
6498     SET_H_INSN_PREFIXED_P (opval);
6499     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6500   }
6501 }
6502 }
6503 }
6504
6505 #undef FLD
6506 }
6507   NEXT (vpc);
6508
6509   CASE (sem, INSN_ADDU_B_R) : /* addu.b $Rs,$Rd */
6510 {
6511   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6512   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6513 #define FLD(f) abuf->fields.sfmt_addc_m.f
6514   int UNUSED written = 0;
6515   IADDR UNUSED pc = abuf->addr;
6516   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6517
6518 {
6519   SI tmp_tmpopd;
6520   SI tmp_tmpops;
6521   BI tmp_carry;
6522   SI tmp_newval;
6523   tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
6524   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6525   tmp_carry = CPU (h_cbit);
6526   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6527   {
6528     SI opval = tmp_newval;
6529     SET_H_GR (FLD (f_operand2), opval);
6530     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6531   }
6532 {
6533   {
6534     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6535     CPU (h_cbit) = opval;
6536     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6537   }
6538   {
6539     BI opval = LTSI (tmp_newval, 0);
6540     CPU (h_nbit) = opval;
6541     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6542   }
6543   {
6544     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6545     CPU (h_zbit) = opval;
6546     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6547   }
6548   {
6549     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6550     CPU (h_vbit) = opval;
6551     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6552   }
6553 {
6554   {
6555     BI opval = 0;
6556     CPU (h_xbit) = opval;
6557     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6558   }
6559   {
6560     BI opval = 0;
6561     SET_H_INSN_PREFIXED_P (opval);
6562     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6563   }
6564 }
6565 }
6566 }
6567
6568 #undef FLD
6569 }
6570   NEXT (vpc);
6571
6572   CASE (sem, INSN_ADDU_W_R) : /* addu.w $Rs,$Rd */
6573 {
6574   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6575   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6576 #define FLD(f) abuf->fields.sfmt_addc_m.f
6577   int UNUSED written = 0;
6578   IADDR UNUSED pc = abuf->addr;
6579   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6580
6581 {
6582   SI tmp_tmpopd;
6583   SI tmp_tmpops;
6584   BI tmp_carry;
6585   SI tmp_newval;
6586   tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
6587   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6588   tmp_carry = CPU (h_cbit);
6589   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6590   {
6591     SI opval = tmp_newval;
6592     SET_H_GR (FLD (f_operand2), opval);
6593     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6594   }
6595 {
6596   {
6597     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6598     CPU (h_cbit) = opval;
6599     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6600   }
6601   {
6602     BI opval = LTSI (tmp_newval, 0);
6603     CPU (h_nbit) = opval;
6604     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6605   }
6606   {
6607     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6608     CPU (h_zbit) = opval;
6609     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6610   }
6611   {
6612     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6613     CPU (h_vbit) = opval;
6614     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6615   }
6616 {
6617   {
6618     BI opval = 0;
6619     CPU (h_xbit) = opval;
6620     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6621   }
6622   {
6623     BI opval = 0;
6624     SET_H_INSN_PREFIXED_P (opval);
6625     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6626   }
6627 }
6628 }
6629 }
6630
6631 #undef FLD
6632 }
6633   NEXT (vpc);
6634
6635   CASE (sem, INSN_ADDU_M_B_M) : /* addu-m.b [${Rs}${inc}],$Rd */
6636 {
6637   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6638   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6639 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6640   int UNUSED written = 0;
6641   IADDR UNUSED pc = abuf->addr;
6642   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6643
6644 {
6645   SI tmp_tmpopd;
6646   SI tmp_tmpops;
6647   BI tmp_carry;
6648   SI tmp_newval;
6649   tmp_tmpops = ZEXTQISI (({   SI tmp_addr;
6650   QI tmp_tmp_mem;
6651   BI tmp_postinc;
6652   tmp_postinc = FLD (f_memmode);
6653 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
6654 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
6655 ; if (NEBI (tmp_postinc, 0)) {
6656 {
6657 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6658   tmp_addr = ADDSI (tmp_addr, 1);
6659 }
6660   {
6661     SI opval = tmp_addr;
6662     SET_H_GR (FLD (f_operand1), opval);
6663     written |= (1 << 11);
6664     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6665   }
6666 }
6667 }
6668 ; tmp_tmp_mem; }));
6669   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6670   tmp_carry = CPU (h_cbit);
6671   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6672   {
6673     SI opval = tmp_newval;
6674     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6675     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6676   }
6677 {
6678   {
6679     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6680     CPU (h_cbit) = opval;
6681     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6682   }
6683   {
6684     BI opval = LTSI (tmp_newval, 0);
6685     CPU (h_nbit) = opval;
6686     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6687   }
6688   {
6689     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6690     CPU (h_zbit) = opval;
6691     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6692   }
6693   {
6694     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6695     CPU (h_vbit) = opval;
6696     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6697   }
6698 {
6699   {
6700     BI opval = 0;
6701     CPU (h_xbit) = opval;
6702     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6703   }
6704   {
6705     BI opval = 0;
6706     SET_H_INSN_PREFIXED_P (opval);
6707     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6708   }
6709 }
6710 }
6711 }
6712
6713   abuf->written = written;
6714 #undef FLD
6715 }
6716   NEXT (vpc);
6717
6718   CASE (sem, INSN_ADDU_M_W_M) : /* addu-m.w [${Rs}${inc}],$Rd */
6719 {
6720   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6721   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6722 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6723   int UNUSED written = 0;
6724   IADDR UNUSED pc = abuf->addr;
6725   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6726
6727 {
6728   SI tmp_tmpopd;
6729   SI tmp_tmpops;
6730   BI tmp_carry;
6731   SI tmp_newval;
6732   tmp_tmpops = ZEXTHISI (({   SI tmp_addr;
6733   HI tmp_tmp_mem;
6734   BI tmp_postinc;
6735   tmp_postinc = FLD (f_memmode);
6736 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
6737 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
6738 ; if (NEBI (tmp_postinc, 0)) {
6739 {
6740 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6741   tmp_addr = ADDSI (tmp_addr, 2);
6742 }
6743   {
6744     SI opval = tmp_addr;
6745     SET_H_GR (FLD (f_operand1), opval);
6746     written |= (1 << 11);
6747     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6748   }
6749 }
6750 }
6751 ; tmp_tmp_mem; }));
6752   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6753   tmp_carry = CPU (h_cbit);
6754   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6755   {
6756     SI opval = tmp_newval;
6757     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6758     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6759   }
6760 {
6761   {
6762     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6763     CPU (h_cbit) = opval;
6764     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6765   }
6766   {
6767     BI opval = LTSI (tmp_newval, 0);
6768     CPU (h_nbit) = opval;
6769     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6770   }
6771   {
6772     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6773     CPU (h_zbit) = opval;
6774     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6775   }
6776   {
6777     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6778     CPU (h_vbit) = opval;
6779     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6780   }
6781 {
6782   {
6783     BI opval = 0;
6784     CPU (h_xbit) = opval;
6785     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6786   }
6787   {
6788     BI opval = 0;
6789     SET_H_INSN_PREFIXED_P (opval);
6790     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6791   }
6792 }
6793 }
6794 }
6795
6796   abuf->written = written;
6797 #undef FLD
6798 }
6799   NEXT (vpc);
6800
6801   CASE (sem, INSN_ADDUCBR) : /* [${Rs}${inc}],$Rd */
6802 {
6803   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6804   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6805 #define FLD(f) abuf->fields.sfmt_addcbr.f
6806   int UNUSED written = 0;
6807   IADDR UNUSED pc = abuf->addr;
6808   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6809
6810 {
6811   SI tmp_tmpopd;
6812   SI tmp_tmpops;
6813   BI tmp_carry;
6814   SI tmp_newval;
6815   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
6816   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6817   tmp_carry = CPU (h_cbit);
6818   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6819   {
6820     SI opval = tmp_newval;
6821     SET_H_GR (FLD (f_operand2), opval);
6822     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6823   }
6824 {
6825   {
6826     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6827     CPU (h_cbit) = opval;
6828     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6829   }
6830   {
6831     BI opval = LTSI (tmp_newval, 0);
6832     CPU (h_nbit) = opval;
6833     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6834   }
6835   {
6836     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6837     CPU (h_zbit) = opval;
6838     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6839   }
6840   {
6841     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6842     CPU (h_vbit) = opval;
6843     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6844   }
6845 {
6846   {
6847     BI opval = 0;
6848     CPU (h_xbit) = opval;
6849     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6850   }
6851   {
6852     BI opval = 0;
6853     SET_H_INSN_PREFIXED_P (opval);
6854     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6855   }
6856 }
6857 }
6858 }
6859
6860 #undef FLD
6861 }
6862   NEXT (vpc);
6863
6864   CASE (sem, INSN_ADDUCWR) : /* [${Rs}${inc}],$Rd */
6865 {
6866   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6867   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6868 #define FLD(f) abuf->fields.sfmt_addcwr.f
6869   int UNUSED written = 0;
6870   IADDR UNUSED pc = abuf->addr;
6871   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6872
6873 {
6874   SI tmp_tmpopd;
6875   SI tmp_tmpops;
6876   BI tmp_carry;
6877   SI tmp_newval;
6878   tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
6879   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6880   tmp_carry = CPU (h_cbit);
6881   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6882   {
6883     SI opval = tmp_newval;
6884     SET_H_GR (FLD (f_operand2), opval);
6885     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6886   }
6887 {
6888   {
6889     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6890     CPU (h_cbit) = opval;
6891     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6892   }
6893   {
6894     BI opval = LTSI (tmp_newval, 0);
6895     CPU (h_nbit) = opval;
6896     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6897   }
6898   {
6899     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6900     CPU (h_zbit) = opval;
6901     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6902   }
6903   {
6904     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6905     CPU (h_vbit) = opval;
6906     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6907   }
6908 {
6909   {
6910     BI opval = 0;
6911     CPU (h_xbit) = opval;
6912     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6913   }
6914   {
6915     BI opval = 0;
6916     SET_H_INSN_PREFIXED_P (opval);
6917     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6918   }
6919 }
6920 }
6921 }
6922
6923 #undef FLD
6924 }
6925   NEXT (vpc);
6926
6927   CASE (sem, INSN_SUB_B_R) : /* sub.b $Rs,$Rd */
6928 {
6929   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6930   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6931 #define FLD(f) abuf->fields.sfmt_addc_m.f
6932   int UNUSED written = 0;
6933   IADDR UNUSED pc = abuf->addr;
6934   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6935
6936 {
6937   QI tmp_tmpopd;
6938   QI tmp_tmpops;
6939   BI tmp_carry;
6940   QI tmp_newval;
6941   tmp_tmpops = GET_H_GR (FLD (f_operand1));
6942   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6943   tmp_carry = CPU (h_cbit);
6944   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6945 {
6946   SI tmp_oldregval;
6947   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
6948   {
6949     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
6950     SET_H_GR (FLD (f_operand2), opval);
6951     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6952   }
6953 }
6954 {
6955   {
6956     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
6957     CPU (h_cbit) = opval;
6958     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6959   }
6960   {
6961     BI opval = LTQI (tmp_newval, 0);
6962     CPU (h_nbit) = opval;
6963     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6964   }
6965   {
6966     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6967     CPU (h_zbit) = opval;
6968     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6969   }
6970   {
6971     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
6972     CPU (h_vbit) = opval;
6973     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6974   }
6975 {
6976   {
6977     BI opval = 0;
6978     CPU (h_xbit) = opval;
6979     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6980   }
6981   {
6982     BI opval = 0;
6983     SET_H_INSN_PREFIXED_P (opval);
6984     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6985   }
6986 }
6987 }
6988 }
6989
6990 #undef FLD
6991 }
6992   NEXT (vpc);
6993
6994   CASE (sem, INSN_SUB_W_R) : /* sub.w $Rs,$Rd */
6995 {
6996   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6997   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6998 #define FLD(f) abuf->fields.sfmt_addc_m.f
6999   int UNUSED written = 0;
7000   IADDR UNUSED pc = abuf->addr;
7001   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7002
7003 {
7004   HI tmp_tmpopd;
7005   HI tmp_tmpops;
7006   BI tmp_carry;
7007   HI tmp_newval;
7008   tmp_tmpops = GET_H_GR (FLD (f_operand1));
7009   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7010   tmp_carry = CPU (h_cbit);
7011   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7012 {
7013   SI tmp_oldregval;
7014   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
7015   {
7016     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
7017     SET_H_GR (FLD (f_operand2), opval);
7018     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7019   }
7020 }
7021 {
7022   {
7023     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
7024     CPU (h_cbit) = opval;
7025     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7026   }
7027   {
7028     BI opval = LTHI (tmp_newval, 0);
7029     CPU (h_nbit) = opval;
7030     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7031   }
7032   {
7033     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7034     CPU (h_zbit) = opval;
7035     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7036   }
7037   {
7038     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
7039     CPU (h_vbit) = opval;
7040     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7041   }
7042 {
7043   {
7044     BI opval = 0;
7045     CPU (h_xbit) = opval;
7046     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7047   }
7048   {
7049     BI opval = 0;
7050     SET_H_INSN_PREFIXED_P (opval);
7051     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7052   }
7053 }
7054 }
7055 }
7056
7057 #undef FLD
7058 }
7059   NEXT (vpc);
7060
7061   CASE (sem, INSN_SUB_D_R) : /* sub.d $Rs,$Rd */
7062 {
7063   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7064   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7065 #define FLD(f) abuf->fields.sfmt_addc_m.f
7066   int UNUSED written = 0;
7067   IADDR UNUSED pc = abuf->addr;
7068   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7069
7070 {
7071   SI tmp_tmpopd;
7072   SI tmp_tmpops;
7073   BI tmp_carry;
7074   SI tmp_newval;
7075   tmp_tmpops = GET_H_GR (FLD (f_operand1));
7076   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7077   tmp_carry = CPU (h_cbit);
7078   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7079   {
7080     SI opval = tmp_newval;
7081     SET_H_GR (FLD (f_operand2), opval);
7082     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7083   }
7084 {
7085   {
7086     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7087     CPU (h_cbit) = opval;
7088     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7089   }
7090   {
7091     BI opval = LTSI (tmp_newval, 0);
7092     CPU (h_nbit) = opval;
7093     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7094   }
7095   {
7096     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7097     CPU (h_zbit) = opval;
7098     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7099   }
7100   {
7101     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7102     CPU (h_vbit) = opval;
7103     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7104   }
7105 {
7106   {
7107     BI opval = 0;
7108     CPU (h_xbit) = opval;
7109     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7110   }
7111   {
7112     BI opval = 0;
7113     SET_H_INSN_PREFIXED_P (opval);
7114     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7115   }
7116 }
7117 }
7118 }
7119
7120 #undef FLD
7121 }
7122   NEXT (vpc);
7123
7124   CASE (sem, INSN_SUB_M_B_M) : /* sub-m.b [${Rs}${inc}],${Rd} */
7125 {
7126   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7127   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7128 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7129   int UNUSED written = 0;
7130   IADDR UNUSED pc = abuf->addr;
7131   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7132
7133 {
7134   QI tmp_tmpopd;
7135   QI tmp_tmpops;
7136   BI tmp_carry;
7137   QI tmp_newval;
7138   tmp_tmpops = ({   SI tmp_addr;
7139   QI tmp_tmp_mem;
7140   BI tmp_postinc;
7141   tmp_postinc = FLD (f_memmode);
7142 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
7143 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
7144 ; if (NEBI (tmp_postinc, 0)) {
7145 {
7146 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7147   tmp_addr = ADDSI (tmp_addr, 1);
7148 }
7149   {
7150     SI opval = tmp_addr;
7151     SET_H_GR (FLD (f_operand1), opval);
7152     written |= (1 << 12);
7153     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7154   }
7155 }
7156 }
7157 ; tmp_tmp_mem; });
7158   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7159   tmp_carry = CPU (h_cbit);
7160   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7161 {
7162   SI tmp_oldregval;
7163   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
7164   {
7165     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
7166     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7167     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7168   }
7169 }
7170 {
7171   {
7172     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
7173     CPU (h_cbit) = opval;
7174     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7175   }
7176   {
7177     BI opval = LTQI (tmp_newval, 0);
7178     CPU (h_nbit) = opval;
7179     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7180   }
7181   {
7182     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7183     CPU (h_zbit) = opval;
7184     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7185   }
7186   {
7187     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
7188     CPU (h_vbit) = opval;
7189     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7190   }
7191 {
7192   {
7193     BI opval = 0;
7194     CPU (h_xbit) = opval;
7195     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7196   }
7197   {
7198     BI opval = 0;
7199     SET_H_INSN_PREFIXED_P (opval);
7200     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7201   }
7202 }
7203 }
7204 }
7205
7206   abuf->written = written;
7207 #undef FLD
7208 }
7209   NEXT (vpc);
7210
7211   CASE (sem, INSN_SUB_M_W_M) : /* sub-m.w [${Rs}${inc}],${Rd} */
7212 {
7213   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7214   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7215 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7216   int UNUSED written = 0;
7217   IADDR UNUSED pc = abuf->addr;
7218   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7219
7220 {
7221   HI tmp_tmpopd;
7222   HI tmp_tmpops;
7223   BI tmp_carry;
7224   HI tmp_newval;
7225   tmp_tmpops = ({   SI tmp_addr;
7226   HI tmp_tmp_mem;
7227   BI tmp_postinc;
7228   tmp_postinc = FLD (f_memmode);
7229 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
7230 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
7231 ; if (NEBI (tmp_postinc, 0)) {
7232 {
7233 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7234   tmp_addr = ADDSI (tmp_addr, 2);
7235 }
7236   {
7237     SI opval = tmp_addr;
7238     SET_H_GR (FLD (f_operand1), opval);
7239     written |= (1 << 12);
7240     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7241   }
7242 }
7243 }
7244 ; tmp_tmp_mem; });
7245   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7246   tmp_carry = CPU (h_cbit);
7247   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7248 {
7249   SI tmp_oldregval;
7250   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
7251   {
7252     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
7253     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7254     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7255   }
7256 }
7257 {
7258   {
7259     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
7260     CPU (h_cbit) = opval;
7261     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7262   }
7263   {
7264     BI opval = LTHI (tmp_newval, 0);
7265     CPU (h_nbit) = opval;
7266     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7267   }
7268   {
7269     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7270     CPU (h_zbit) = opval;
7271     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7272   }
7273   {
7274     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
7275     CPU (h_vbit) = opval;
7276     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7277   }
7278 {
7279   {
7280     BI opval = 0;
7281     CPU (h_xbit) = opval;
7282     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7283   }
7284   {
7285     BI opval = 0;
7286     SET_H_INSN_PREFIXED_P (opval);
7287     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7288   }
7289 }
7290 }
7291 }
7292
7293   abuf->written = written;
7294 #undef FLD
7295 }
7296   NEXT (vpc);
7297
7298   CASE (sem, INSN_SUB_M_D_M) : /* sub-m.d [${Rs}${inc}],${Rd} */
7299 {
7300   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7301   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7302 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7303   int UNUSED written = 0;
7304   IADDR UNUSED pc = abuf->addr;
7305   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7306
7307 {
7308   SI tmp_tmpopd;
7309   SI tmp_tmpops;
7310   BI tmp_carry;
7311   SI tmp_newval;
7312   tmp_tmpops = ({   SI tmp_addr;
7313   SI tmp_tmp_mem;
7314   BI tmp_postinc;
7315   tmp_postinc = FLD (f_memmode);
7316 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
7317 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
7318 ; if (NEBI (tmp_postinc, 0)) {
7319 {
7320 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7321   tmp_addr = ADDSI (tmp_addr, 4);
7322 }
7323   {
7324     SI opval = tmp_addr;
7325     SET_H_GR (FLD (f_operand1), opval);
7326     written |= (1 << 11);
7327     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7328   }
7329 }
7330 }
7331 ; tmp_tmp_mem; });
7332   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7333   tmp_carry = CPU (h_cbit);
7334   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7335   {
7336     SI opval = tmp_newval;
7337     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7338     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7339   }
7340 {
7341   {
7342     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7343     CPU (h_cbit) = opval;
7344     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7345   }
7346   {
7347     BI opval = LTSI (tmp_newval, 0);
7348     CPU (h_nbit) = opval;
7349     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7350   }
7351   {
7352     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7353     CPU (h_zbit) = opval;
7354     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7355   }
7356   {
7357     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7358     CPU (h_vbit) = opval;
7359     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7360   }
7361 {
7362   {
7363     BI opval = 0;
7364     CPU (h_xbit) = opval;
7365     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7366   }
7367   {
7368     BI opval = 0;
7369     SET_H_INSN_PREFIXED_P (opval);
7370     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7371   }
7372 }
7373 }
7374 }
7375
7376   abuf->written = written;
7377 #undef FLD
7378 }
7379   NEXT (vpc);
7380
7381   CASE (sem, INSN_SUBCBR) : /* sub.b ${sconst8}],${Rd} */
7382 {
7383   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7384   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7385 #define FLD(f) abuf->fields.sfmt_addcbr.f
7386   int UNUSED written = 0;
7387   IADDR UNUSED pc = abuf->addr;
7388   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7389
7390 {
7391   QI tmp_tmpopd;
7392   QI tmp_tmpops;
7393   BI tmp_carry;
7394   QI tmp_newval;
7395   tmp_tmpops = FLD (f_indir_pc__byte);
7396   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7397   tmp_carry = CPU (h_cbit);
7398   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7399 {
7400   SI tmp_oldregval;
7401   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
7402   {
7403     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
7404     SET_H_GR (FLD (f_operand2), opval);
7405     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7406   }
7407 }
7408 {
7409   {
7410     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
7411     CPU (h_cbit) = opval;
7412     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7413   }
7414   {
7415     BI opval = LTQI (tmp_newval, 0);
7416     CPU (h_nbit) = opval;
7417     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7418   }
7419   {
7420     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7421     CPU (h_zbit) = opval;
7422     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7423   }
7424   {
7425     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
7426     CPU (h_vbit) = opval;
7427     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7428   }
7429 {
7430   {
7431     BI opval = 0;
7432     CPU (h_xbit) = opval;
7433     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7434   }
7435   {
7436     BI opval = 0;
7437     SET_H_INSN_PREFIXED_P (opval);
7438     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7439   }
7440 }
7441 }
7442 }
7443
7444 #undef FLD
7445 }
7446   NEXT (vpc);
7447
7448   CASE (sem, INSN_SUBCWR) : /* sub.w ${sconst16}],${Rd} */
7449 {
7450   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7451   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7452 #define FLD(f) abuf->fields.sfmt_addcwr.f
7453   int UNUSED written = 0;
7454   IADDR UNUSED pc = abuf->addr;
7455   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7456
7457 {
7458   HI tmp_tmpopd;
7459   HI tmp_tmpops;
7460   BI tmp_carry;
7461   HI tmp_newval;
7462   tmp_tmpops = FLD (f_indir_pc__word);
7463   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7464   tmp_carry = CPU (h_cbit);
7465   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7466 {
7467   SI tmp_oldregval;
7468   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
7469   {
7470     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
7471     SET_H_GR (FLD (f_operand2), opval);
7472     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7473   }
7474 }
7475 {
7476   {
7477     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
7478     CPU (h_cbit) = opval;
7479     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7480   }
7481   {
7482     BI opval = LTHI (tmp_newval, 0);
7483     CPU (h_nbit) = opval;
7484     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7485   }
7486   {
7487     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7488     CPU (h_zbit) = opval;
7489     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7490   }
7491   {
7492     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
7493     CPU (h_vbit) = opval;
7494     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7495   }
7496 {
7497   {
7498     BI opval = 0;
7499     CPU (h_xbit) = opval;
7500     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7501   }
7502   {
7503     BI opval = 0;
7504     SET_H_INSN_PREFIXED_P (opval);
7505     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7506   }
7507 }
7508 }
7509 }
7510
7511 #undef FLD
7512 }
7513   NEXT (vpc);
7514
7515   CASE (sem, INSN_SUBCDR) : /* sub.d ${const32}],${Rd} */
7516 {
7517   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7518   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7519 #define FLD(f) abuf->fields.sfmt_addcdr.f
7520   int UNUSED written = 0;
7521   IADDR UNUSED pc = abuf->addr;
7522   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
7523
7524 {
7525   SI tmp_tmpopd;
7526   SI tmp_tmpops;
7527   BI tmp_carry;
7528   SI tmp_newval;
7529   tmp_tmpops = FLD (f_indir_pc__dword);
7530   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7531   tmp_carry = CPU (h_cbit);
7532   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7533   {
7534     SI opval = tmp_newval;
7535     SET_H_GR (FLD (f_operand2), opval);
7536     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7537   }
7538 {
7539   {
7540     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7541     CPU (h_cbit) = opval;
7542     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7543   }
7544   {
7545     BI opval = LTSI (tmp_newval, 0);
7546     CPU (h_nbit) = opval;
7547     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7548   }
7549   {
7550     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7551     CPU (h_zbit) = opval;
7552     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7553   }
7554   {
7555     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7556     CPU (h_vbit) = opval;
7557     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7558   }
7559 {
7560   {
7561     BI opval = 0;
7562     CPU (h_xbit) = opval;
7563     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7564   }
7565   {
7566     BI opval = 0;
7567     SET_H_INSN_PREFIXED_P (opval);
7568     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7569   }
7570 }
7571 }
7572 }
7573
7574 #undef FLD
7575 }
7576   NEXT (vpc);
7577
7578   CASE (sem, INSN_SUBS_B_R) : /* subs.b $Rs,$Rd */
7579 {
7580   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7581   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7582 #define FLD(f) abuf->fields.sfmt_addc_m.f
7583   int UNUSED written = 0;
7584   IADDR UNUSED pc = abuf->addr;
7585   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7586
7587 {
7588   SI tmp_tmpopd;
7589   SI tmp_tmpops;
7590   BI tmp_carry;
7591   SI tmp_newval;
7592   tmp_tmpops = EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
7593   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7594   tmp_carry = CPU (h_cbit);
7595   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7596   {
7597     SI opval = tmp_newval;
7598     SET_H_GR (FLD (f_operand2), opval);
7599     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7600   }
7601 {
7602   {
7603     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7604     CPU (h_cbit) = opval;
7605     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7606   }
7607   {
7608     BI opval = LTSI (tmp_newval, 0);
7609     CPU (h_nbit) = opval;
7610     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7611   }
7612   {
7613     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7614     CPU (h_zbit) = opval;
7615     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7616   }
7617   {
7618     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7619     CPU (h_vbit) = opval;
7620     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7621   }
7622 {
7623   {
7624     BI opval = 0;
7625     CPU (h_xbit) = opval;
7626     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7627   }
7628   {
7629     BI opval = 0;
7630     SET_H_INSN_PREFIXED_P (opval);
7631     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7632   }
7633 }
7634 }
7635 }
7636
7637 #undef FLD
7638 }
7639   NEXT (vpc);
7640
7641   CASE (sem, INSN_SUBS_W_R) : /* subs.w $Rs,$Rd */
7642 {
7643   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7644   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7645 #define FLD(f) abuf->fields.sfmt_addc_m.f
7646   int UNUSED written = 0;
7647   IADDR UNUSED pc = abuf->addr;
7648   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7649
7650 {
7651   SI tmp_tmpopd;
7652   SI tmp_tmpops;
7653   BI tmp_carry;
7654   SI tmp_newval;
7655   tmp_tmpops = EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
7656   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7657   tmp_carry = CPU (h_cbit);
7658   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7659   {
7660     SI opval = tmp_newval;
7661     SET_H_GR (FLD (f_operand2), opval);
7662     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7663   }
7664 {
7665   {
7666     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7667     CPU (h_cbit) = opval;
7668     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7669   }
7670   {
7671     BI opval = LTSI (tmp_newval, 0);
7672     CPU (h_nbit) = opval;
7673     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7674   }
7675   {
7676     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7677     CPU (h_zbit) = opval;
7678     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7679   }
7680   {
7681     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7682     CPU (h_vbit) = opval;
7683     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7684   }
7685 {
7686   {
7687     BI opval = 0;
7688     CPU (h_xbit) = opval;
7689     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7690   }
7691   {
7692     BI opval = 0;
7693     SET_H_INSN_PREFIXED_P (opval);
7694     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7695   }
7696 }
7697 }
7698 }
7699
7700 #undef FLD
7701 }
7702   NEXT (vpc);
7703
7704   CASE (sem, INSN_SUBS_M_B_M) : /* subs-m.b [${Rs}${inc}],$Rd */
7705 {
7706   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7707   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7708 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7709   int UNUSED written = 0;
7710   IADDR UNUSED pc = abuf->addr;
7711   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7712
7713 {
7714   SI tmp_tmpopd;
7715   SI tmp_tmpops;
7716   BI tmp_carry;
7717   SI tmp_newval;
7718   tmp_tmpops = EXTQISI (({   SI tmp_addr;
7719   QI tmp_tmp_mem;
7720   BI tmp_postinc;
7721   tmp_postinc = FLD (f_memmode);
7722 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
7723 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
7724 ; if (NEBI (tmp_postinc, 0)) {
7725 {
7726 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7727   tmp_addr = ADDSI (tmp_addr, 1);
7728 }
7729   {
7730     SI opval = tmp_addr;
7731     SET_H_GR (FLD (f_operand1), opval);
7732     written |= (1 << 11);
7733     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7734   }
7735 }
7736 }
7737 ; tmp_tmp_mem; }));
7738   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7739   tmp_carry = CPU (h_cbit);
7740   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7741   {
7742     SI opval = tmp_newval;
7743     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7744     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7745   }
7746 {
7747   {
7748     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7749     CPU (h_cbit) = opval;
7750     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7751   }
7752   {
7753     BI opval = LTSI (tmp_newval, 0);
7754     CPU (h_nbit) = opval;
7755     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7756   }
7757   {
7758     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7759     CPU (h_zbit) = opval;
7760     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7761   }
7762   {
7763     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7764     CPU (h_vbit) = opval;
7765     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7766   }
7767 {
7768   {
7769     BI opval = 0;
7770     CPU (h_xbit) = opval;
7771     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7772   }
7773   {
7774     BI opval = 0;
7775     SET_H_INSN_PREFIXED_P (opval);
7776     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7777   }
7778 }
7779 }
7780 }
7781
7782   abuf->written = written;
7783 #undef FLD
7784 }
7785   NEXT (vpc);
7786
7787   CASE (sem, INSN_SUBS_M_W_M) : /* subs-m.w [${Rs}${inc}],$Rd */
7788 {
7789   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7790   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7791 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7792   int UNUSED written = 0;
7793   IADDR UNUSED pc = abuf->addr;
7794   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7795
7796 {
7797   SI tmp_tmpopd;
7798   SI tmp_tmpops;
7799   BI tmp_carry;
7800   SI tmp_newval;
7801   tmp_tmpops = EXTHISI (({   SI tmp_addr;
7802   HI tmp_tmp_mem;
7803   BI tmp_postinc;
7804   tmp_postinc = FLD (f_memmode);
7805 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
7806 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
7807 ; if (NEBI (tmp_postinc, 0)) {
7808 {
7809 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7810   tmp_addr = ADDSI (tmp_addr, 2);
7811 }
7812   {
7813     SI opval = tmp_addr;
7814     SET_H_GR (FLD (f_operand1), opval);
7815     written |= (1 << 11);
7816     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7817   }
7818 }
7819 }
7820 ; tmp_tmp_mem; }));
7821   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7822   tmp_carry = CPU (h_cbit);
7823   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7824   {
7825     SI opval = tmp_newval;
7826     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7827     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7828   }
7829 {
7830   {
7831     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7832     CPU (h_cbit) = opval;
7833     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7834   }
7835   {
7836     BI opval = LTSI (tmp_newval, 0);
7837     CPU (h_nbit) = opval;
7838     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7839   }
7840   {
7841     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7842     CPU (h_zbit) = opval;
7843     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7844   }
7845   {
7846     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7847     CPU (h_vbit) = opval;
7848     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7849   }
7850 {
7851   {
7852     BI opval = 0;
7853     CPU (h_xbit) = opval;
7854     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7855   }
7856   {
7857     BI opval = 0;
7858     SET_H_INSN_PREFIXED_P (opval);
7859     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7860   }
7861 }
7862 }
7863 }
7864
7865   abuf->written = written;
7866 #undef FLD
7867 }
7868   NEXT (vpc);
7869
7870   CASE (sem, INSN_SUBSCBR) : /* [${Rs}${inc}],$Rd */
7871 {
7872   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7873   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7874 #define FLD(f) abuf->fields.sfmt_addcbr.f
7875   int UNUSED written = 0;
7876   IADDR UNUSED pc = abuf->addr;
7877   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7878
7879 {
7880   SI tmp_tmpopd;
7881   SI tmp_tmpops;
7882   BI tmp_carry;
7883   SI tmp_newval;
7884   tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
7885   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7886   tmp_carry = CPU (h_cbit);
7887   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7888   {
7889     SI opval = tmp_newval;
7890     SET_H_GR (FLD (f_operand2), opval);
7891     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7892   }
7893 {
7894   {
7895     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7896     CPU (h_cbit) = opval;
7897     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7898   }
7899   {
7900     BI opval = LTSI (tmp_newval, 0);
7901     CPU (h_nbit) = opval;
7902     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7903   }
7904   {
7905     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7906     CPU (h_zbit) = opval;
7907     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7908   }
7909   {
7910     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7911     CPU (h_vbit) = opval;
7912     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7913   }
7914 {
7915   {
7916     BI opval = 0;
7917     CPU (h_xbit) = opval;
7918     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7919   }
7920   {
7921     BI opval = 0;
7922     SET_H_INSN_PREFIXED_P (opval);
7923     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7924   }
7925 }
7926 }
7927 }
7928
7929 #undef FLD
7930 }
7931   NEXT (vpc);
7932
7933   CASE (sem, INSN_SUBSCWR) : /* [${Rs}${inc}],$Rd */
7934 {
7935   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7936   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7937 #define FLD(f) abuf->fields.sfmt_addcwr.f
7938   int UNUSED written = 0;
7939   IADDR UNUSED pc = abuf->addr;
7940   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7941
7942 {
7943   SI tmp_tmpopd;
7944   SI tmp_tmpops;
7945   BI tmp_carry;
7946   SI tmp_newval;
7947   tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
7948   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7949   tmp_carry = CPU (h_cbit);
7950   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7951   {
7952     SI opval = tmp_newval;
7953     SET_H_GR (FLD (f_operand2), opval);
7954     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7955   }
7956 {
7957   {
7958     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7959     CPU (h_cbit) = opval;
7960     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7961   }
7962   {
7963     BI opval = LTSI (tmp_newval, 0);
7964     CPU (h_nbit) = opval;
7965     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7966   }
7967   {
7968     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7969     CPU (h_zbit) = opval;
7970     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7971   }
7972   {
7973     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7974     CPU (h_vbit) = opval;
7975     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7976   }
7977 {
7978   {
7979     BI opval = 0;
7980     CPU (h_xbit) = opval;
7981     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7982   }
7983   {
7984     BI opval = 0;
7985     SET_H_INSN_PREFIXED_P (opval);
7986     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7987   }
7988 }
7989 }
7990 }
7991
7992 #undef FLD
7993 }
7994   NEXT (vpc);
7995
7996   CASE (sem, INSN_SUBU_B_R) : /* subu.b $Rs,$Rd */
7997 {
7998   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7999   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8000 #define FLD(f) abuf->fields.sfmt_addc_m.f
8001   int UNUSED written = 0;
8002   IADDR UNUSED pc = abuf->addr;
8003   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8004
8005 {
8006   SI tmp_tmpopd;
8007   SI tmp_tmpops;
8008   BI tmp_carry;
8009   SI tmp_newval;
8010   tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
8011   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8012   tmp_carry = CPU (h_cbit);
8013   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8014   {
8015     SI opval = tmp_newval;
8016     SET_H_GR (FLD (f_operand2), opval);
8017     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8018   }
8019 {
8020   {
8021     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8022     CPU (h_cbit) = opval;
8023     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8024   }
8025   {
8026     BI opval = LTSI (tmp_newval, 0);
8027     CPU (h_nbit) = opval;
8028     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8029   }
8030   {
8031     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8032     CPU (h_zbit) = opval;
8033     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8034   }
8035   {
8036     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8037     CPU (h_vbit) = opval;
8038     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8039   }
8040 {
8041   {
8042     BI opval = 0;
8043     CPU (h_xbit) = opval;
8044     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8045   }
8046   {
8047     BI opval = 0;
8048     SET_H_INSN_PREFIXED_P (opval);
8049     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8050   }
8051 }
8052 }
8053 }
8054
8055 #undef FLD
8056 }
8057   NEXT (vpc);
8058
8059   CASE (sem, INSN_SUBU_W_R) : /* subu.w $Rs,$Rd */
8060 {
8061   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8062   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8063 #define FLD(f) abuf->fields.sfmt_addc_m.f
8064   int UNUSED written = 0;
8065   IADDR UNUSED pc = abuf->addr;
8066   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8067
8068 {
8069   SI tmp_tmpopd;
8070   SI tmp_tmpops;
8071   BI tmp_carry;
8072   SI tmp_newval;
8073   tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
8074   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8075   tmp_carry = CPU (h_cbit);
8076   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8077   {
8078     SI opval = tmp_newval;
8079     SET_H_GR (FLD (f_operand2), opval);
8080     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8081   }
8082 {
8083   {
8084     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8085     CPU (h_cbit) = opval;
8086     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8087   }
8088   {
8089     BI opval = LTSI (tmp_newval, 0);
8090     CPU (h_nbit) = opval;
8091     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8092   }
8093   {
8094     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8095     CPU (h_zbit) = opval;
8096     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8097   }
8098   {
8099     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8100     CPU (h_vbit) = opval;
8101     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8102   }
8103 {
8104   {
8105     BI opval = 0;
8106     CPU (h_xbit) = opval;
8107     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8108   }
8109   {
8110     BI opval = 0;
8111     SET_H_INSN_PREFIXED_P (opval);
8112     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8113   }
8114 }
8115 }
8116 }
8117
8118 #undef FLD
8119 }
8120   NEXT (vpc);
8121
8122   CASE (sem, INSN_SUBU_M_B_M) : /* subu-m.b [${Rs}${inc}],$Rd */
8123 {
8124   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8125   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8126 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
8127   int UNUSED written = 0;
8128   IADDR UNUSED pc = abuf->addr;
8129   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8130
8131 {
8132   SI tmp_tmpopd;
8133   SI tmp_tmpops;
8134   BI tmp_carry;
8135   SI tmp_newval;
8136   tmp_tmpops = ZEXTQISI (({   SI tmp_addr;
8137   QI tmp_tmp_mem;
8138   BI tmp_postinc;
8139   tmp_postinc = FLD (f_memmode);
8140 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
8141 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
8142 ; if (NEBI (tmp_postinc, 0)) {
8143 {
8144 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8145   tmp_addr = ADDSI (tmp_addr, 1);
8146 }
8147   {
8148     SI opval = tmp_addr;
8149     SET_H_GR (FLD (f_operand1), opval);
8150     written |= (1 << 11);
8151     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8152   }
8153 }
8154 }
8155 ; tmp_tmp_mem; }));
8156   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8157   tmp_carry = CPU (h_cbit);
8158   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8159   {
8160     SI opval = tmp_newval;
8161     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
8162     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8163   }
8164 {
8165   {
8166     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8167     CPU (h_cbit) = opval;
8168     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8169   }
8170   {
8171     BI opval = LTSI (tmp_newval, 0);
8172     CPU (h_nbit) = opval;
8173     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8174   }
8175   {
8176     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8177     CPU (h_zbit) = opval;
8178     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8179   }
8180   {
8181     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8182     CPU (h_vbit) = opval;
8183     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8184   }
8185 {
8186   {
8187     BI opval = 0;
8188     CPU (h_xbit) = opval;
8189     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8190   }
8191   {
8192     BI opval = 0;
8193     SET_H_INSN_PREFIXED_P (opval);
8194     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8195   }
8196 }
8197 }
8198 }
8199
8200   abuf->written = written;
8201 #undef FLD
8202 }
8203   NEXT (vpc);
8204
8205   CASE (sem, INSN_SUBU_M_W_M) : /* subu-m.w [${Rs}${inc}],$Rd */
8206 {
8207   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8208   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8209 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
8210   int UNUSED written = 0;
8211   IADDR UNUSED pc = abuf->addr;
8212   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8213
8214 {
8215   SI tmp_tmpopd;
8216   SI tmp_tmpops;
8217   BI tmp_carry;
8218   SI tmp_newval;
8219   tmp_tmpops = ZEXTHISI (({   SI tmp_addr;
8220   HI tmp_tmp_mem;
8221   BI tmp_postinc;
8222   tmp_postinc = FLD (f_memmode);
8223 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
8224 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
8225 ; if (NEBI (tmp_postinc, 0)) {
8226 {
8227 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8228   tmp_addr = ADDSI (tmp_addr, 2);
8229 }
8230   {
8231     SI opval = tmp_addr;
8232     SET_H_GR (FLD (f_operand1), opval);
8233     written |= (1 << 11);
8234     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8235   }
8236 }
8237 }
8238 ; tmp_tmp_mem; }));
8239   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8240   tmp_carry = CPU (h_cbit);
8241   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8242   {
8243     SI opval = tmp_newval;
8244     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
8245     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8246   }
8247 {
8248   {
8249     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8250     CPU (h_cbit) = opval;
8251     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8252   }
8253   {
8254     BI opval = LTSI (tmp_newval, 0);
8255     CPU (h_nbit) = opval;
8256     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8257   }
8258   {
8259     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8260     CPU (h_zbit) = opval;
8261     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8262   }
8263   {
8264     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8265     CPU (h_vbit) = opval;
8266     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8267   }
8268 {
8269   {
8270     BI opval = 0;
8271     CPU (h_xbit) = opval;
8272     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8273   }
8274   {
8275     BI opval = 0;
8276     SET_H_INSN_PREFIXED_P (opval);
8277     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8278   }
8279 }
8280 }
8281 }
8282
8283   abuf->written = written;
8284 #undef FLD
8285 }
8286   NEXT (vpc);
8287
8288   CASE (sem, INSN_SUBUCBR) : /* [${Rs}${inc}],$Rd */
8289 {
8290   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8291   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8292 #define FLD(f) abuf->fields.sfmt_addcbr.f
8293   int UNUSED written = 0;
8294   IADDR UNUSED pc = abuf->addr;
8295   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
8296
8297 {
8298   SI tmp_tmpopd;
8299   SI tmp_tmpops;
8300   BI tmp_carry;
8301   SI tmp_newval;
8302   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
8303   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8304   tmp_carry = CPU (h_cbit);
8305   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8306   {
8307     SI opval = tmp_newval;
8308     SET_H_GR (FLD (f_operand2), opval);
8309     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8310   }
8311 {
8312   {
8313     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8314     CPU (h_cbit) = opval;
8315     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8316   }
8317   {
8318     BI opval = LTSI (tmp_newval, 0);
8319     CPU (h_nbit) = opval;
8320     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8321   }
8322   {
8323     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8324     CPU (h_zbit) = opval;
8325     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8326   }
8327   {
8328     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8329     CPU (h_vbit) = opval;
8330     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8331   }
8332 {
8333   {
8334     BI opval = 0;
8335     CPU (h_xbit) = opval;
8336     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8337   }
8338   {
8339     BI opval = 0;
8340     SET_H_INSN_PREFIXED_P (opval);
8341     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8342   }
8343 }
8344 }
8345 }
8346
8347 #undef FLD
8348 }
8349   NEXT (vpc);
8350
8351   CASE (sem, INSN_SUBUCWR) : /* [${Rs}${inc}],$Rd */
8352 {
8353   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8354   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8355 #define FLD(f) abuf->fields.sfmt_addcwr.f
8356   int UNUSED written = 0;
8357   IADDR UNUSED pc = abuf->addr;
8358   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
8359
8360 {
8361   SI tmp_tmpopd;
8362   SI tmp_tmpops;
8363   BI tmp_carry;
8364   SI tmp_newval;
8365   tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
8366   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8367   tmp_carry = CPU (h_cbit);
8368   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8369   {
8370     SI opval = tmp_newval;
8371     SET_H_GR (FLD (f_operand2), opval);
8372     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8373   }
8374 {
8375   {
8376     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8377     CPU (h_cbit) = opval;
8378     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8379   }
8380   {
8381     BI opval = LTSI (tmp_newval, 0);
8382     CPU (h_nbit) = opval;
8383     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8384   }
8385   {
8386     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8387     CPU (h_zbit) = opval;
8388     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8389   }
8390   {
8391     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8392     CPU (h_vbit) = opval;
8393     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8394   }
8395 {
8396   {
8397     BI opval = 0;
8398     CPU (h_xbit) = opval;
8399     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8400   }
8401   {
8402     BI opval = 0;
8403     SET_H_INSN_PREFIXED_P (opval);
8404     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8405   }
8406 }
8407 }
8408 }
8409
8410 #undef FLD
8411 }
8412   NEXT (vpc);
8413
8414   CASE (sem, INSN_ADDC_R) : /* addc $Rs,$Rd */
8415 {
8416   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8417   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8418 #define FLD(f) abuf->fields.sfmt_addc_m.f
8419   int UNUSED written = 0;
8420   IADDR UNUSED pc = abuf->addr;
8421   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8422
8423 {
8424 CPU (h_xbit) = 1;
8425 {
8426   SI tmp_tmpopd;
8427   SI tmp_tmpops;
8428   BI tmp_carry;
8429   SI tmp_newval;
8430   tmp_tmpops = GET_H_GR (FLD (f_operand1));
8431   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8432   tmp_carry = CPU (h_cbit);
8433   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8434   {
8435     SI opval = tmp_newval;
8436     SET_H_GR (FLD (f_operand2), opval);
8437     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8438   }
8439 {
8440   {
8441     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
8442     CPU (h_cbit) = opval;
8443     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8444   }
8445   {
8446     BI opval = LTSI (tmp_newval, 0);
8447     CPU (h_nbit) = opval;
8448     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8449   }
8450   {
8451     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8452     CPU (h_zbit) = opval;
8453     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8454   }
8455   {
8456     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8457     CPU (h_vbit) = opval;
8458     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8459   }
8460 {
8461   {
8462     BI opval = 0;
8463     CPU (h_xbit) = opval;
8464     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8465   }
8466   {
8467     BI opval = 0;
8468     SET_H_INSN_PREFIXED_P (opval);
8469     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8470   }
8471 }
8472 }
8473 }
8474 }
8475
8476 #undef FLD
8477 }
8478   NEXT (vpc);
8479
8480   CASE (sem, INSN_ADDC_M) : /* addc [${Rs}${inc}],${Rd} */
8481 {
8482   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8483   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8484 #define FLD(f) abuf->fields.sfmt_addc_m.f
8485   int UNUSED written = 0;
8486   IADDR UNUSED pc = abuf->addr;
8487   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8488
8489 {
8490 CPU (h_xbit) = 1;
8491 {
8492   SI tmp_tmpopd;
8493   SI tmp_tmpops;
8494   BI tmp_carry;
8495   SI tmp_newval;
8496   tmp_tmpops = ({   SI tmp_addr;
8497   SI tmp_tmp_mem;
8498   BI tmp_postinc;
8499   tmp_postinc = FLD (f_memmode);
8500 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
8501 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
8502 ; if (NEBI (tmp_postinc, 0)) {
8503 {
8504 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8505   tmp_addr = ADDSI (tmp_addr, 4);
8506 }
8507   {
8508     SI opval = tmp_addr;
8509     SET_H_GR (FLD (f_operand1), opval);
8510     written |= (1 << 10);
8511     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8512   }
8513 }
8514 }
8515 ; tmp_tmp_mem; });
8516   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8517   tmp_carry = CPU (h_cbit);
8518   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8519   {
8520     SI opval = tmp_newval;
8521     SET_H_GR (FLD (f_operand2), opval);
8522     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8523   }
8524 {
8525   {
8526     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
8527     CPU (h_cbit) = opval;
8528     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8529   }
8530   {
8531     BI opval = LTSI (tmp_newval, 0);
8532     CPU (h_nbit) = opval;
8533     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8534   }
8535   {
8536     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8537     CPU (h_zbit) = opval;
8538     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8539   }
8540   {
8541     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8542     CPU (h_vbit) = opval;
8543     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8544   }
8545 {
8546   {
8547     BI opval = 0;
8548     CPU (h_xbit) = opval;
8549     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8550   }
8551   {
8552     BI opval = 0;
8553     SET_H_INSN_PREFIXED_P (opval);
8554     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8555   }
8556 }
8557 }
8558 }
8559 }
8560
8561   abuf->written = written;
8562 #undef FLD
8563 }
8564   NEXT (vpc);
8565
8566   CASE (sem, INSN_ADDC_C) : /* addc ${const32},${Rd} */
8567 {
8568   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8569   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8570 #define FLD(f) abuf->fields.sfmt_addcdr.f
8571   int UNUSED written = 0;
8572   IADDR UNUSED pc = abuf->addr;
8573   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
8574
8575 {
8576 CPU (h_xbit) = 1;
8577 {
8578   SI tmp_tmpopd;
8579   SI tmp_tmpops;
8580   BI tmp_carry;
8581   SI tmp_newval;
8582   tmp_tmpops = FLD (f_indir_pc__dword);
8583   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8584   tmp_carry = CPU (h_cbit);
8585   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8586   {
8587     SI opval = tmp_newval;
8588     SET_H_GR (FLD (f_operand2), opval);
8589     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8590   }
8591 {
8592   {
8593     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
8594     CPU (h_cbit) = opval;
8595     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8596   }
8597   {
8598     BI opval = LTSI (tmp_newval, 0);
8599     CPU (h_nbit) = opval;
8600     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8601   }
8602   {
8603     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8604     CPU (h_zbit) = opval;
8605     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8606   }
8607   {
8608     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8609     CPU (h_vbit) = opval;
8610     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8611   }
8612 {
8613   {
8614     BI opval = 0;
8615     CPU (h_xbit) = opval;
8616     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8617   }
8618   {
8619     BI opval = 0;
8620     SET_H_INSN_PREFIXED_P (opval);
8621     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8622   }
8623 }
8624 }
8625 }
8626 }
8627
8628 #undef FLD
8629 }
8630   NEXT (vpc);
8631
8632   CASE (sem, INSN_LAPC_D) : /* lapc.d ${const32-pcrel},${Rd} */
8633 {
8634   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8635   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8636 #define FLD(f) abuf->fields.sfmt_lapc_d.f
8637   int UNUSED written = 0;
8638   IADDR UNUSED pc = abuf->addr;
8639   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
8640
8641 {
8642   {
8643     SI opval = FLD (i_const32_pcrel);
8644     SET_H_GR (FLD (f_operand2), opval);
8645     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8646   }
8647 {
8648   {
8649     BI opval = 0;
8650     CPU (h_xbit) = opval;
8651     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8652   }
8653   {
8654     BI opval = 0;
8655     SET_H_INSN_PREFIXED_P (opval);
8656     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8657   }
8658 }
8659 }
8660
8661 #undef FLD
8662 }
8663   NEXT (vpc);
8664
8665   CASE (sem, INSN_LAPCQ) : /* lapcq ${qo},${Rd} */
8666 {
8667   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8668   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8669 #define FLD(f) abuf->fields.sfmt_lapcq.f
8670   int UNUSED written = 0;
8671   IADDR UNUSED pc = abuf->addr;
8672   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8673
8674 {
8675   {
8676     SI opval = FLD (i_qo);
8677     SET_H_GR (FLD (f_operand2), opval);
8678     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8679   }
8680 {
8681   {
8682     BI opval = 0;
8683     CPU (h_xbit) = opval;
8684     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8685   }
8686   {
8687     BI opval = 0;
8688     SET_H_INSN_PREFIXED_P (opval);
8689     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8690   }
8691 }
8692 }
8693
8694 #undef FLD
8695 }
8696   NEXT (vpc);
8697
8698   CASE (sem, INSN_ADDI_B_R) : /* addi.b ${Rs-dfield}.m,${Rd-sfield} */
8699 {
8700   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8701   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8702 #define FLD(f) abuf->fields.sfmt_addc_m.f
8703   int UNUSED written = 0;
8704   IADDR UNUSED pc = abuf->addr;
8705   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8706
8707 {
8708   {
8709     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 1));
8710     SET_H_GR (FLD (f_operand1), opval);
8711     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8712   }
8713 {
8714   {
8715     BI opval = 0;
8716     CPU (h_xbit) = opval;
8717     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8718   }
8719   {
8720     BI opval = 0;
8721     SET_H_INSN_PREFIXED_P (opval);
8722     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8723   }
8724 }
8725 }
8726
8727 #undef FLD
8728 }
8729   NEXT (vpc);
8730
8731   CASE (sem, INSN_ADDI_W_R) : /* addi.w ${Rs-dfield}.m,${Rd-sfield} */
8732 {
8733   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8734   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8735 #define FLD(f) abuf->fields.sfmt_addc_m.f
8736   int UNUSED written = 0;
8737   IADDR UNUSED pc = abuf->addr;
8738   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8739
8740 {
8741   {
8742     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 2));
8743     SET_H_GR (FLD (f_operand1), opval);
8744     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8745   }
8746 {
8747   {
8748     BI opval = 0;
8749     CPU (h_xbit) = opval;
8750     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8751   }
8752   {
8753     BI opval = 0;
8754     SET_H_INSN_PREFIXED_P (opval);
8755     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8756   }
8757 }
8758 }
8759
8760 #undef FLD
8761 }
8762   NEXT (vpc);
8763
8764   CASE (sem, INSN_ADDI_D_R) : /* addi.d ${Rs-dfield}.m,${Rd-sfield} */
8765 {
8766   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8767   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8768 #define FLD(f) abuf->fields.sfmt_addc_m.f
8769   int UNUSED written = 0;
8770   IADDR UNUSED pc = abuf->addr;
8771   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8772
8773 {
8774   {
8775     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 4));
8776     SET_H_GR (FLD (f_operand1), opval);
8777     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8778   }
8779 {
8780   {
8781     BI opval = 0;
8782     CPU (h_xbit) = opval;
8783     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8784   }
8785   {
8786     BI opval = 0;
8787     SET_H_INSN_PREFIXED_P (opval);
8788     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8789   }
8790 }
8791 }
8792
8793 #undef FLD
8794 }
8795   NEXT (vpc);
8796
8797   CASE (sem, INSN_NEG_B_R) : /* neg.b $Rs,$Rd */
8798 {
8799   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8800   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8801 #define FLD(f) abuf->fields.sfmt_addc_m.f
8802   int UNUSED written = 0;
8803   IADDR UNUSED pc = abuf->addr;
8804   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8805
8806 {
8807   QI tmp_tmpopd;
8808   QI tmp_tmpops;
8809   BI tmp_carry;
8810   QI tmp_newval;
8811   tmp_tmpops = GET_H_GR (FLD (f_operand1));
8812   tmp_tmpopd = 0;
8813   tmp_carry = CPU (h_cbit);
8814   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8815 {
8816   SI tmp_oldregval;
8817   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
8818   {
8819     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
8820     SET_H_GR (FLD (f_operand2), opval);
8821     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8822   }
8823 }
8824 {
8825   {
8826     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
8827     CPU (h_cbit) = opval;
8828     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8829   }
8830   {
8831     BI opval = LTQI (tmp_newval, 0);
8832     CPU (h_nbit) = opval;
8833     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8834   }
8835   {
8836     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8837     CPU (h_zbit) = opval;
8838     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8839   }
8840   {
8841     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
8842     CPU (h_vbit) = opval;
8843     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8844   }
8845 {
8846   {
8847     BI opval = 0;
8848     CPU (h_xbit) = opval;
8849     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8850   }
8851   {
8852     BI opval = 0;
8853     SET_H_INSN_PREFIXED_P (opval);
8854     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8855   }
8856 }
8857 }
8858 }
8859
8860 #undef FLD
8861 }
8862   NEXT (vpc);
8863
8864   CASE (sem, INSN_NEG_W_R) : /* neg.w $Rs,$Rd */
8865 {
8866   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8867   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8868 #define FLD(f) abuf->fields.sfmt_addc_m.f
8869   int UNUSED written = 0;
8870   IADDR UNUSED pc = abuf->addr;
8871   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8872
8873 {
8874   HI tmp_tmpopd;
8875   HI tmp_tmpops;
8876   BI tmp_carry;
8877   HI tmp_newval;
8878   tmp_tmpops = GET_H_GR (FLD (f_operand1));
8879   tmp_tmpopd = 0;
8880   tmp_carry = CPU (h_cbit);
8881   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8882 {
8883   SI tmp_oldregval;
8884   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
8885   {
8886     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
8887     SET_H_GR (FLD (f_operand2), opval);
8888     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8889   }
8890 }
8891 {
8892   {
8893     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
8894     CPU (h_cbit) = opval;
8895     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8896   }
8897   {
8898     BI opval = LTHI (tmp_newval, 0);
8899     CPU (h_nbit) = opval;
8900     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8901   }
8902   {
8903     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8904     CPU (h_zbit) = opval;
8905     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8906   }
8907   {
8908     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
8909     CPU (h_vbit) = opval;
8910     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8911   }
8912 {
8913   {
8914     BI opval = 0;
8915     CPU (h_xbit) = opval;
8916     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8917   }
8918   {
8919     BI opval = 0;
8920     SET_H_INSN_PREFIXED_P (opval);
8921     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8922   }
8923 }
8924 }
8925 }
8926
8927 #undef FLD
8928 }
8929   NEXT (vpc);
8930
8931   CASE (sem, INSN_NEG_D_R) : /* neg.d $Rs,$Rd */
8932 {
8933   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8934   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8935 #define FLD(f) abuf->fields.sfmt_addc_m.f
8936   int UNUSED written = 0;
8937   IADDR UNUSED pc = abuf->addr;
8938   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8939
8940 {
8941   SI tmp_tmpopd;
8942   SI tmp_tmpops;
8943   BI tmp_carry;
8944   SI tmp_newval;
8945   tmp_tmpops = GET_H_GR (FLD (f_operand1));
8946   tmp_tmpopd = 0;
8947   tmp_carry = CPU (h_cbit);
8948   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8949   {
8950     SI opval = tmp_newval;
8951     SET_H_GR (FLD (f_operand2), opval);
8952     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8953   }
8954 {
8955   {
8956     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8957     CPU (h_cbit) = opval;
8958     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8959   }
8960   {
8961     BI opval = LTSI (tmp_newval, 0);
8962     CPU (h_nbit) = opval;
8963     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8964   }
8965   {
8966     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8967     CPU (h_zbit) = opval;
8968     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8969   }
8970   {
8971     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8972     CPU (h_vbit) = opval;
8973     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8974   }
8975 {
8976   {
8977     BI opval = 0;
8978     CPU (h_xbit) = opval;
8979     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8980   }
8981   {
8982     BI opval = 0;
8983     SET_H_INSN_PREFIXED_P (opval);
8984     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8985   }
8986 }
8987 }
8988 }
8989
8990 #undef FLD
8991 }
8992   NEXT (vpc);
8993
8994   CASE (sem, INSN_TEST_M_B_M) : /* test-m.b [${Rs}${inc}] */
8995 {
8996   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8997   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8998 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
8999   int UNUSED written = 0;
9000   IADDR UNUSED pc = abuf->addr;
9001   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9002
9003 {
9004   QI tmp_tmpd;
9005   tmp_tmpd = ({   SI tmp_addr;
9006   QI tmp_tmp_mem;
9007   BI tmp_postinc;
9008   tmp_postinc = FLD (f_memmode);
9009 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
9010 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
9011 ; if (NEBI (tmp_postinc, 0)) {
9012 {
9013 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9014   tmp_addr = ADDSI (tmp_addr, 1);
9015 }
9016   {
9017     SI opval = tmp_addr;
9018     SET_H_GR (FLD (f_operand1), opval);
9019     written |= (1 << 8);
9020     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9021   }
9022 }
9023 }
9024 ; tmp_tmp_mem; });
9025 {
9026   QI tmp_tmpopd;
9027   QI tmp_tmpops;
9028   BI tmp_carry;
9029   QI tmp_newval;
9030   tmp_tmpops = 0;
9031   tmp_tmpopd = tmp_tmpd;
9032   tmp_carry = CPU (h_cbit);
9033   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
9034 ((void) 0); /*nop*/
9035 {
9036   {
9037     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
9038     CPU (h_cbit) = opval;
9039     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9040   }
9041   {
9042     BI opval = LTQI (tmp_newval, 0);
9043     CPU (h_nbit) = opval;
9044     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9045   }
9046   {
9047     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9048     CPU (h_zbit) = opval;
9049     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9050   }
9051   {
9052     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
9053     CPU (h_vbit) = opval;
9054     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9055   }
9056 {
9057   {
9058     BI opval = 0;
9059     CPU (h_xbit) = opval;
9060     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9061   }
9062   {
9063     BI opval = 0;
9064     SET_H_INSN_PREFIXED_P (opval);
9065     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9066   }
9067 }
9068 }
9069 }
9070 }
9071
9072   abuf->written = written;
9073 #undef FLD
9074 }
9075   NEXT (vpc);
9076
9077   CASE (sem, INSN_TEST_M_W_M) : /* test-m.w [${Rs}${inc}] */
9078 {
9079   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9080   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9081 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
9082   int UNUSED written = 0;
9083   IADDR UNUSED pc = abuf->addr;
9084   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9085
9086 {
9087   HI tmp_tmpd;
9088   tmp_tmpd = ({   SI tmp_addr;
9089   HI tmp_tmp_mem;
9090   BI tmp_postinc;
9091   tmp_postinc = FLD (f_memmode);
9092 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
9093 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
9094 ; if (NEBI (tmp_postinc, 0)) {
9095 {
9096 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9097   tmp_addr = ADDSI (tmp_addr, 2);
9098 }
9099   {
9100     SI opval = tmp_addr;
9101     SET_H_GR (FLD (f_operand1), opval);
9102     written |= (1 << 8);
9103     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9104   }
9105 }
9106 }
9107 ; tmp_tmp_mem; });
9108 {
9109   HI tmp_tmpopd;
9110   HI tmp_tmpops;
9111   BI tmp_carry;
9112   HI tmp_newval;
9113   tmp_tmpops = 0;
9114   tmp_tmpopd = tmp_tmpd;
9115   tmp_carry = CPU (h_cbit);
9116   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
9117 ((void) 0); /*nop*/
9118 {
9119   {
9120     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
9121     CPU (h_cbit) = opval;
9122     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9123   }
9124   {
9125     BI opval = LTHI (tmp_newval, 0);
9126     CPU (h_nbit) = opval;
9127     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9128   }
9129   {
9130     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9131     CPU (h_zbit) = opval;
9132     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9133   }
9134   {
9135     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
9136     CPU (h_vbit) = opval;
9137     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9138   }
9139 {
9140   {
9141     BI opval = 0;
9142     CPU (h_xbit) = opval;
9143     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9144   }
9145   {
9146     BI opval = 0;
9147     SET_H_INSN_PREFIXED_P (opval);
9148     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9149   }
9150 }
9151 }
9152 }
9153 }
9154
9155   abuf->written = written;
9156 #undef FLD
9157 }
9158   NEXT (vpc);
9159
9160   CASE (sem, INSN_TEST_M_D_M) : /* test-m.d [${Rs}${inc}] */
9161 {
9162   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9163   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9164 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
9165   int UNUSED written = 0;
9166   IADDR UNUSED pc = abuf->addr;
9167   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9168
9169 {
9170   SI tmp_tmpd;
9171   tmp_tmpd = ({   SI tmp_addr;
9172   SI tmp_tmp_mem;
9173   BI tmp_postinc;
9174   tmp_postinc = FLD (f_memmode);
9175 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
9176 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
9177 ; if (NEBI (tmp_postinc, 0)) {
9178 {
9179 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9180   tmp_addr = ADDSI (tmp_addr, 4);
9181 }
9182   {
9183     SI opval = tmp_addr;
9184     SET_H_GR (FLD (f_operand1), opval);
9185     written |= (1 << 8);
9186     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9187   }
9188 }
9189 }
9190 ; tmp_tmp_mem; });
9191 {
9192   SI tmp_tmpopd;
9193   SI tmp_tmpops;
9194   BI tmp_carry;
9195   SI tmp_newval;
9196   tmp_tmpops = 0;
9197   tmp_tmpopd = tmp_tmpd;
9198   tmp_carry = CPU (h_cbit);
9199   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
9200 ((void) 0); /*nop*/
9201 {
9202   {
9203     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
9204     CPU (h_cbit) = opval;
9205     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9206   }
9207   {
9208     BI opval = LTSI (tmp_newval, 0);
9209     CPU (h_nbit) = opval;
9210     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9211   }
9212   {
9213     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9214     CPU (h_zbit) = opval;
9215     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9216   }
9217   {
9218     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
9219     CPU (h_vbit) = opval;
9220     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9221   }
9222 {
9223   {
9224     BI opval = 0;
9225     CPU (h_xbit) = opval;
9226     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9227   }
9228   {
9229     BI opval = 0;
9230     SET_H_INSN_PREFIXED_P (opval);
9231     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9232   }
9233 }
9234 }
9235 }
9236 }
9237
9238   abuf->written = written;
9239 #undef FLD
9240 }
9241   NEXT (vpc);
9242
9243   CASE (sem, INSN_MOVE_R_M_B_M) : /* move-r-m.b ${Rs-dfield},[${Rd-sfield}${inc}] */
9244 {
9245   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9246   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9247 #define FLD(f) abuf->fields.sfmt_addc_m.f
9248   int UNUSED written = 0;
9249   IADDR UNUSED pc = abuf->addr;
9250   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9251
9252 {
9253   QI tmp_tmpd;
9254   tmp_tmpd = GET_H_GR (FLD (f_operand2));
9255 {
9256   SI tmp_addr;
9257   BI tmp_postinc;
9258   tmp_postinc = FLD (f_memmode);
9259   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
9260 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
9261 if (EQBI (CPU (h_pbit), 0)) {
9262 {
9263   {
9264     QI opval = tmp_tmpd;
9265     SETMEMQI (current_cpu, pc, tmp_addr, opval);
9266     written |= (1 << 10);
9267     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9268   }
9269   {
9270     BI opval = CPU (h_pbit);
9271     CPU (h_cbit) = opval;
9272     written |= (1 << 9);
9273     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9274   }
9275 }
9276 } else {
9277   {
9278     BI opval = 1;
9279     CPU (h_cbit) = opval;
9280     written |= (1 << 9);
9281     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9282   }
9283 }
9284 } else {
9285   {
9286     QI opval = tmp_tmpd;
9287     SETMEMQI (current_cpu, pc, tmp_addr, opval);
9288     written |= (1 << 10);
9289     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9290   }
9291 }
9292 if (NEBI (tmp_postinc, 0)) {
9293 {
9294 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9295   tmp_addr = ADDSI (tmp_addr, 1);
9296 }
9297   {
9298     SI opval = tmp_addr;
9299     SET_H_GR (FLD (f_operand1), opval);
9300     written |= (1 << 8);
9301     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9302   }
9303 }
9304 }
9305 }
9306 {
9307   {
9308     BI opval = 0;
9309     CPU (h_xbit) = opval;
9310     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9311   }
9312   {
9313     BI opval = 0;
9314     SET_H_INSN_PREFIXED_P (opval);
9315     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9316   }
9317 }
9318 }
9319
9320   abuf->written = written;
9321 #undef FLD
9322 }
9323   NEXT (vpc);
9324
9325   CASE (sem, INSN_MOVE_R_M_W_M) : /* move-r-m.w ${Rs-dfield},[${Rd-sfield}${inc}] */
9326 {
9327   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9328   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9329 #define FLD(f) abuf->fields.sfmt_addc_m.f
9330   int UNUSED written = 0;
9331   IADDR UNUSED pc = abuf->addr;
9332   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9333
9334 {
9335   HI tmp_tmpd;
9336   tmp_tmpd = GET_H_GR (FLD (f_operand2));
9337 {
9338   SI tmp_addr;
9339   BI tmp_postinc;
9340   tmp_postinc = FLD (f_memmode);
9341   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
9342 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
9343 if (EQBI (CPU (h_pbit), 0)) {
9344 {
9345   {
9346     HI opval = tmp_tmpd;
9347     SETMEMHI (current_cpu, pc, tmp_addr, opval);
9348     written |= (1 << 10);
9349     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9350   }
9351   {
9352     BI opval = CPU (h_pbit);
9353     CPU (h_cbit) = opval;
9354     written |= (1 << 9);
9355     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9356   }
9357 }
9358 } else {
9359   {
9360     BI opval = 1;
9361     CPU (h_cbit) = opval;
9362     written |= (1 << 9);
9363     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9364   }
9365 }
9366 } else {
9367   {
9368     HI opval = tmp_tmpd;
9369     SETMEMHI (current_cpu, pc, tmp_addr, opval);
9370     written |= (1 << 10);
9371     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9372   }
9373 }
9374 if (NEBI (tmp_postinc, 0)) {
9375 {
9376 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9377   tmp_addr = ADDSI (tmp_addr, 2);
9378 }
9379   {
9380     SI opval = tmp_addr;
9381     SET_H_GR (FLD (f_operand1), opval);
9382     written |= (1 << 8);
9383     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9384   }
9385 }
9386 }
9387 }
9388 {
9389   {
9390     BI opval = 0;
9391     CPU (h_xbit) = opval;
9392     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9393   }
9394   {
9395     BI opval = 0;
9396     SET_H_INSN_PREFIXED_P (opval);
9397     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9398   }
9399 }
9400 }
9401
9402   abuf->written = written;
9403 #undef FLD
9404 }
9405   NEXT (vpc);
9406
9407   CASE (sem, INSN_MOVE_R_M_D_M) : /* move-r-m.d ${Rs-dfield},[${Rd-sfield}${inc}] */
9408 {
9409   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9410   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9411 #define FLD(f) abuf->fields.sfmt_addc_m.f
9412   int UNUSED written = 0;
9413   IADDR UNUSED pc = abuf->addr;
9414   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9415
9416 {
9417   SI tmp_tmpd;
9418   tmp_tmpd = GET_H_GR (FLD (f_operand2));
9419 {
9420   SI tmp_addr;
9421   BI tmp_postinc;
9422   tmp_postinc = FLD (f_memmode);
9423   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
9424 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
9425 if (EQBI (CPU (h_pbit), 0)) {
9426 {
9427   {
9428     SI opval = tmp_tmpd;
9429     SETMEMSI (current_cpu, pc, tmp_addr, opval);
9430     written |= (1 << 10);
9431     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9432   }
9433   {
9434     BI opval = CPU (h_pbit);
9435     CPU (h_cbit) = opval;
9436     written |= (1 << 9);
9437     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9438   }
9439 }
9440 } else {
9441   {
9442     BI opval = 1;
9443     CPU (h_cbit) = opval;
9444     written |= (1 << 9);
9445     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9446   }
9447 }
9448 } else {
9449   {
9450     SI opval = tmp_tmpd;
9451     SETMEMSI (current_cpu, pc, tmp_addr, opval);
9452     written |= (1 << 10);
9453     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9454   }
9455 }
9456 if (NEBI (tmp_postinc, 0)) {
9457 {
9458 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9459   tmp_addr = ADDSI (tmp_addr, 4);
9460 }
9461   {
9462     SI opval = tmp_addr;
9463     SET_H_GR (FLD (f_operand1), opval);
9464     written |= (1 << 8);
9465     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9466   }
9467 }
9468 }
9469 }
9470 {
9471   {
9472     BI opval = 0;
9473     CPU (h_xbit) = opval;
9474     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9475   }
9476   {
9477     BI opval = 0;
9478     SET_H_INSN_PREFIXED_P (opval);
9479     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9480   }
9481 }
9482 }
9483
9484   abuf->written = written;
9485 #undef FLD
9486 }
9487   NEXT (vpc);
9488
9489   CASE (sem, INSN_MULS_B) : /* muls.b $Rs,$Rd */
9490 {
9491   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9492   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9493 #define FLD(f) abuf->fields.sfmt_muls_b.f
9494   int UNUSED written = 0;
9495   IADDR UNUSED pc = abuf->addr;
9496   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9497
9498 {
9499   DI tmp_src1;
9500   DI tmp_src2;
9501   DI tmp_tmpr;
9502   tmp_src1 = EXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
9503   tmp_src2 = EXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand2))));
9504   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9505   {
9506     SI opval = TRUNCDISI (tmp_tmpr);
9507     SET_H_GR (FLD (f_operand2), opval);
9508     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9509   }
9510   {
9511     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9512     SET_H_SR (((UINT) 7), opval);
9513     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9514   }
9515 {
9516   {
9517     BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
9518     CPU (h_cbit) = opval;
9519     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9520   }
9521   {
9522     BI opval = LTDI (tmp_tmpr, 0);
9523     CPU (h_nbit) = opval;
9524     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9525   }
9526   {
9527     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9528     CPU (h_zbit) = opval;
9529     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9530   }
9531   {
9532     BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
9533     CPU (h_vbit) = opval;
9534     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9535   }
9536 {
9537   {
9538     BI opval = 0;
9539     CPU (h_xbit) = opval;
9540     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9541   }
9542   {
9543     BI opval = 0;
9544     SET_H_INSN_PREFIXED_P (opval);
9545     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9546   }
9547 }
9548 }
9549 }
9550
9551 #undef FLD
9552 }
9553   NEXT (vpc);
9554
9555   CASE (sem, INSN_MULS_W) : /* muls.w $Rs,$Rd */
9556 {
9557   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9558   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9559 #define FLD(f) abuf->fields.sfmt_muls_b.f
9560   int UNUSED written = 0;
9561   IADDR UNUSED pc = abuf->addr;
9562   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9563
9564 {
9565   DI tmp_src1;
9566   DI tmp_src2;
9567   DI tmp_tmpr;
9568   tmp_src1 = EXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
9569   tmp_src2 = EXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand2))));
9570   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9571   {
9572     SI opval = TRUNCDISI (tmp_tmpr);
9573     SET_H_GR (FLD (f_operand2), opval);
9574     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9575   }
9576   {
9577     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9578     SET_H_SR (((UINT) 7), opval);
9579     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9580   }
9581 {
9582   {
9583     BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
9584     CPU (h_cbit) = opval;
9585     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9586   }
9587   {
9588     BI opval = LTDI (tmp_tmpr, 0);
9589     CPU (h_nbit) = opval;
9590     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9591   }
9592   {
9593     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9594     CPU (h_zbit) = opval;
9595     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9596   }
9597   {
9598     BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
9599     CPU (h_vbit) = opval;
9600     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9601   }
9602 {
9603   {
9604     BI opval = 0;
9605     CPU (h_xbit) = opval;
9606     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9607   }
9608   {
9609     BI opval = 0;
9610     SET_H_INSN_PREFIXED_P (opval);
9611     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9612   }
9613 }
9614 }
9615 }
9616
9617 #undef FLD
9618 }
9619   NEXT (vpc);
9620
9621   CASE (sem, INSN_MULS_D) : /* muls.d $Rs,$Rd */
9622 {
9623   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9624   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9625 #define FLD(f) abuf->fields.sfmt_muls_b.f
9626   int UNUSED written = 0;
9627   IADDR UNUSED pc = abuf->addr;
9628   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9629
9630 {
9631   DI tmp_src1;
9632   DI tmp_src2;
9633   DI tmp_tmpr;
9634   tmp_src1 = EXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand1))));
9635   tmp_src2 = EXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand2))));
9636   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9637   {
9638     SI opval = TRUNCDISI (tmp_tmpr);
9639     SET_H_GR (FLD (f_operand2), opval);
9640     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9641   }
9642   {
9643     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9644     SET_H_SR (((UINT) 7), opval);
9645     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9646   }
9647 {
9648   {
9649     BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
9650     CPU (h_cbit) = opval;
9651     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9652   }
9653   {
9654     BI opval = LTDI (tmp_tmpr, 0);
9655     CPU (h_nbit) = opval;
9656     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9657   }
9658   {
9659     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9660     CPU (h_zbit) = opval;
9661     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9662   }
9663   {
9664     BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
9665     CPU (h_vbit) = opval;
9666     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9667   }
9668 {
9669   {
9670     BI opval = 0;
9671     CPU (h_xbit) = opval;
9672     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9673   }
9674   {
9675     BI opval = 0;
9676     SET_H_INSN_PREFIXED_P (opval);
9677     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9678   }
9679 }
9680 }
9681 }
9682
9683 #undef FLD
9684 }
9685   NEXT (vpc);
9686
9687   CASE (sem, INSN_MULU_B) : /* mulu.b $Rs,$Rd */
9688 {
9689   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9690   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9691 #define FLD(f) abuf->fields.sfmt_muls_b.f
9692   int UNUSED written = 0;
9693   IADDR UNUSED pc = abuf->addr;
9694   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9695
9696 {
9697   DI tmp_src1;
9698   DI tmp_src2;
9699   DI tmp_tmpr;
9700   tmp_src1 = ZEXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
9701   tmp_src2 = ZEXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand2))));
9702   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9703   {
9704     SI opval = TRUNCDISI (tmp_tmpr);
9705     SET_H_GR (FLD (f_operand2), opval);
9706     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9707   }
9708   {
9709     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9710     SET_H_SR (((UINT) 7), opval);
9711     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9712   }
9713 {
9714   {
9715     BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
9716     CPU (h_cbit) = opval;
9717     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9718   }
9719   {
9720     BI opval = LTDI (tmp_tmpr, 0);
9721     CPU (h_nbit) = opval;
9722     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9723   }
9724   {
9725     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9726     CPU (h_zbit) = opval;
9727     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9728   }
9729   {
9730     BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
9731     CPU (h_vbit) = opval;
9732     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9733   }
9734 {
9735   {
9736     BI opval = 0;
9737     CPU (h_xbit) = opval;
9738     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9739   }
9740   {
9741     BI opval = 0;
9742     SET_H_INSN_PREFIXED_P (opval);
9743     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9744   }
9745 }
9746 }
9747 }
9748
9749 #undef FLD
9750 }
9751   NEXT (vpc);
9752
9753   CASE (sem, INSN_MULU_W) : /* mulu.w $Rs,$Rd */
9754 {
9755   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9756   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9757 #define FLD(f) abuf->fields.sfmt_muls_b.f
9758   int UNUSED written = 0;
9759   IADDR UNUSED pc = abuf->addr;
9760   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9761
9762 {
9763   DI tmp_src1;
9764   DI tmp_src2;
9765   DI tmp_tmpr;
9766   tmp_src1 = ZEXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
9767   tmp_src2 = ZEXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand2))));
9768   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9769   {
9770     SI opval = TRUNCDISI (tmp_tmpr);
9771     SET_H_GR (FLD (f_operand2), opval);
9772     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9773   }
9774   {
9775     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9776     SET_H_SR (((UINT) 7), opval);
9777     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9778   }
9779 {
9780   {
9781     BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
9782     CPU (h_cbit) = opval;
9783     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9784   }
9785   {
9786     BI opval = LTDI (tmp_tmpr, 0);
9787     CPU (h_nbit) = opval;
9788     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9789   }
9790   {
9791     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9792     CPU (h_zbit) = opval;
9793     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9794   }
9795   {
9796     BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
9797     CPU (h_vbit) = opval;
9798     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9799   }
9800 {
9801   {
9802     BI opval = 0;
9803     CPU (h_xbit) = opval;
9804     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9805   }
9806   {
9807     BI opval = 0;
9808     SET_H_INSN_PREFIXED_P (opval);
9809     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9810   }
9811 }
9812 }
9813 }
9814
9815 #undef FLD
9816 }
9817   NEXT (vpc);
9818
9819   CASE (sem, INSN_MULU_D) : /* mulu.d $Rs,$Rd */
9820 {
9821   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9822   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9823 #define FLD(f) abuf->fields.sfmt_muls_b.f
9824   int UNUSED written = 0;
9825   IADDR UNUSED pc = abuf->addr;
9826   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9827
9828 {
9829   DI tmp_src1;
9830   DI tmp_src2;
9831   DI tmp_tmpr;
9832   tmp_src1 = ZEXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand1))));
9833   tmp_src2 = ZEXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand2))));
9834   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9835   {
9836     SI opval = TRUNCDISI (tmp_tmpr);
9837     SET_H_GR (FLD (f_operand2), opval);
9838     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9839   }
9840   {
9841     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9842     SET_H_SR (((UINT) 7), opval);
9843     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9844   }
9845 {
9846   {
9847     BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
9848     CPU (h_cbit) = opval;
9849     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9850   }
9851   {
9852     BI opval = LTDI (tmp_tmpr, 0);
9853     CPU (h_nbit) = opval;
9854     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9855   }
9856   {
9857     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9858     CPU (h_zbit) = opval;
9859     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9860   }
9861   {
9862     BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
9863     CPU (h_vbit) = opval;
9864     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9865   }
9866 {
9867   {
9868     BI opval = 0;
9869     CPU (h_xbit) = opval;
9870     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9871   }
9872   {
9873     BI opval = 0;
9874     SET_H_INSN_PREFIXED_P (opval);
9875     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9876   }
9877 }
9878 }
9879 }
9880
9881 #undef FLD
9882 }
9883   NEXT (vpc);
9884
9885   CASE (sem, INSN_MCP) : /* mcp $Ps,$Rd */
9886 {
9887   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9888   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9889 #define FLD(f) abuf->fields.sfmt_mcp.f
9890   int UNUSED written = 0;
9891   IADDR UNUSED pc = abuf->addr;
9892   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9893
9894 {
9895 CPU (h_xbit) = 1;
9896 CPU (h_zbit) = 1;
9897 {
9898   SI tmp_tmpopd;
9899   SI tmp_tmpops;
9900   BI tmp_carry;
9901   SI tmp_newval;
9902   tmp_tmpops = GET_H_SR (FLD (f_operand2));
9903   tmp_tmpopd = GET_H_GR (FLD (f_operand1));
9904   tmp_carry = CPU (h_rbit);
9905   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
9906   {
9907     SI opval = tmp_newval;
9908     SET_H_GR (FLD (f_operand1), opval);
9909     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9910   }
9911 {
9912   {
9913     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
9914     CPU (h_rbit) = opval;
9915     TRACE_RESULT (current_cpu, abuf, "rbit", 'x', opval);
9916   }
9917   {
9918     BI opval = LTSI (tmp_newval, 0);
9919     CPU (h_nbit) = opval;
9920     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9921   }
9922   {
9923     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9924     CPU (h_zbit) = opval;
9925     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9926   }
9927   {
9928     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
9929     CPU (h_vbit) = opval;
9930     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9931   }
9932 {
9933   {
9934     BI opval = 0;
9935     CPU (h_xbit) = opval;
9936     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9937   }
9938   {
9939     BI opval = 0;
9940     SET_H_INSN_PREFIXED_P (opval);
9941     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9942   }
9943 }
9944 }
9945 }
9946 }
9947
9948 #undef FLD
9949 }
9950   NEXT (vpc);
9951
9952   CASE (sem, INSN_DSTEP) : /* dstep $Rs,$Rd */
9953 {
9954   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9955   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9956 #define FLD(f) abuf->fields.sfmt_muls_b.f
9957   int UNUSED written = 0;
9958   IADDR UNUSED pc = abuf->addr;
9959   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9960
9961 {
9962   SI tmp_tmp;
9963   SI tmp_tmps;
9964   SI tmp_tmpd;
9965   tmp_tmps = GET_H_GR (FLD (f_operand1));
9966   tmp_tmp = SLLSI (GET_H_GR (FLD (f_operand2)), 1);
9967   tmp_tmpd = ((GEUSI (tmp_tmp, tmp_tmps)) ? (SUBSI (tmp_tmp, tmp_tmps)) : (tmp_tmp));
9968   {
9969     SI opval = tmp_tmpd;
9970     SET_H_GR (FLD (f_operand2), opval);
9971     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9972   }
9973 {
9974   {
9975     BI opval = LTSI (tmp_tmpd, 0);
9976     CPU (h_nbit) = opval;
9977     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9978   }
9979   {
9980     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
9981     CPU (h_zbit) = opval;
9982     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9983   }
9984 SET_H_CBIT_MOVE (0);
9985 SET_H_VBIT_MOVE (0);
9986 {
9987   {
9988     BI opval = 0;
9989     CPU (h_xbit) = opval;
9990     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9991   }
9992   {
9993     BI opval = 0;
9994     SET_H_INSN_PREFIXED_P (opval);
9995     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9996   }
9997 }
9998 }
9999 }
10000
10001 #undef FLD
10002 }
10003   NEXT (vpc);
10004
10005   CASE (sem, INSN_ABS) : /* abs $Rs,$Rd */
10006 {
10007   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10008   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10009 #define FLD(f) abuf->fields.sfmt_muls_b.f
10010   int UNUSED written = 0;
10011   IADDR UNUSED pc = abuf->addr;
10012   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10013
10014 {
10015   SI tmp_tmpd;
10016   tmp_tmpd = ABSSI (GET_H_GR (FLD (f_operand1)));
10017   {
10018     SI opval = tmp_tmpd;
10019     SET_H_GR (FLD (f_operand2), opval);
10020     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10021   }
10022 {
10023   {
10024     BI opval = LTSI (tmp_tmpd, 0);
10025     CPU (h_nbit) = opval;
10026     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10027   }
10028   {
10029     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10030     CPU (h_zbit) = opval;
10031     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10032   }
10033 SET_H_CBIT_MOVE (0);
10034 SET_H_VBIT_MOVE (0);
10035 {
10036   {
10037     BI opval = 0;
10038     CPU (h_xbit) = opval;
10039     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10040   }
10041   {
10042     BI opval = 0;
10043     SET_H_INSN_PREFIXED_P (opval);
10044     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10045   }
10046 }
10047 }
10048 }
10049
10050 #undef FLD
10051 }
10052   NEXT (vpc);
10053
10054   CASE (sem, INSN_AND_B_R) : /* and.b $Rs,$Rd */
10055 {
10056   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10057   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10058 #define FLD(f) abuf->fields.sfmt_addc_m.f
10059   int UNUSED written = 0;
10060   IADDR UNUSED pc = abuf->addr;
10061   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10062
10063 {
10064   QI tmp_tmpd;
10065   tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10066 {
10067   SI tmp_oldregval;
10068   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
10069   {
10070     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10071     SET_H_GR (FLD (f_operand2), opval);
10072     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10073   }
10074 }
10075 {
10076   {
10077     BI opval = LTQI (tmp_tmpd, 0);
10078     CPU (h_nbit) = opval;
10079     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10080   }
10081   {
10082     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10083     CPU (h_zbit) = opval;
10084     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10085   }
10086 SET_H_CBIT_MOVE (0);
10087 SET_H_VBIT_MOVE (0);
10088 {
10089   {
10090     BI opval = 0;
10091     CPU (h_xbit) = opval;
10092     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10093   }
10094   {
10095     BI opval = 0;
10096     SET_H_INSN_PREFIXED_P (opval);
10097     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10098   }
10099 }
10100 }
10101 }
10102
10103 #undef FLD
10104 }
10105   NEXT (vpc);
10106
10107   CASE (sem, INSN_AND_W_R) : /* and.w $Rs,$Rd */
10108 {
10109   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10110   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10111 #define FLD(f) abuf->fields.sfmt_addc_m.f
10112   int UNUSED written = 0;
10113   IADDR UNUSED pc = abuf->addr;
10114   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10115
10116 {
10117   HI tmp_tmpd;
10118   tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10119 {
10120   SI tmp_oldregval;
10121   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
10122   {
10123     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10124     SET_H_GR (FLD (f_operand2), opval);
10125     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10126   }
10127 }
10128 {
10129   {
10130     BI opval = LTHI (tmp_tmpd, 0);
10131     CPU (h_nbit) = opval;
10132     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10133   }
10134   {
10135     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10136     CPU (h_zbit) = opval;
10137     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10138   }
10139 SET_H_CBIT_MOVE (0);
10140 SET_H_VBIT_MOVE (0);
10141 {
10142   {
10143     BI opval = 0;
10144     CPU (h_xbit) = opval;
10145     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10146   }
10147   {
10148     BI opval = 0;
10149     SET_H_INSN_PREFIXED_P (opval);
10150     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10151   }
10152 }
10153 }
10154 }
10155
10156 #undef FLD
10157 }
10158   NEXT (vpc);
10159
10160   CASE (sem, INSN_AND_D_R) : /* and.d $Rs,$Rd */
10161 {
10162   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10163   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10164 #define FLD(f) abuf->fields.sfmt_addc_m.f
10165   int UNUSED written = 0;
10166   IADDR UNUSED pc = abuf->addr;
10167   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10168
10169 {
10170   SI tmp_tmpd;
10171   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10172   {
10173     SI opval = tmp_tmpd;
10174     SET_H_GR (FLD (f_operand2), opval);
10175     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10176   }
10177 {
10178   {
10179     BI opval = LTSI (tmp_tmpd, 0);
10180     CPU (h_nbit) = opval;
10181     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10182   }
10183   {
10184     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10185     CPU (h_zbit) = opval;
10186     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10187   }
10188 SET_H_CBIT_MOVE (0);
10189 SET_H_VBIT_MOVE (0);
10190 {
10191   {
10192     BI opval = 0;
10193     CPU (h_xbit) = opval;
10194     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10195   }
10196   {
10197     BI opval = 0;
10198     SET_H_INSN_PREFIXED_P (opval);
10199     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10200   }
10201 }
10202 }
10203 }
10204
10205 #undef FLD
10206 }
10207   NEXT (vpc);
10208
10209   CASE (sem, INSN_AND_M_B_M) : /* and-m.b [${Rs}${inc}],${Rd} */
10210 {
10211   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10212   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10213 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10214   int UNUSED written = 0;
10215   IADDR UNUSED pc = abuf->addr;
10216   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10217
10218 {
10219   QI tmp_tmpd;
10220   tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10221   QI tmp_tmp_mem;
10222   BI tmp_postinc;
10223   tmp_postinc = FLD (f_memmode);
10224 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
10225 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
10226 ; if (NEBI (tmp_postinc, 0)) {
10227 {
10228 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10229   tmp_addr = ADDSI (tmp_addr, 1);
10230 }
10231   {
10232     SI opval = tmp_addr;
10233     SET_H_GR (FLD (f_operand1), opval);
10234     written |= (1 << 11);
10235     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10236   }
10237 }
10238 }
10239 ; tmp_tmp_mem; }));
10240 {
10241   SI tmp_oldregval;
10242   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
10243   {
10244     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10245     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10246     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10247   }
10248 }
10249 {
10250   {
10251     BI opval = LTQI (tmp_tmpd, 0);
10252     CPU (h_nbit) = opval;
10253     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10254   }
10255   {
10256     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10257     CPU (h_zbit) = opval;
10258     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10259   }
10260 SET_H_CBIT_MOVE (0);
10261 SET_H_VBIT_MOVE (0);
10262 {
10263   {
10264     BI opval = 0;
10265     CPU (h_xbit) = opval;
10266     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10267   }
10268   {
10269     BI opval = 0;
10270     SET_H_INSN_PREFIXED_P (opval);
10271     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10272   }
10273 }
10274 }
10275 }
10276
10277   abuf->written = written;
10278 #undef FLD
10279 }
10280   NEXT (vpc);
10281
10282   CASE (sem, INSN_AND_M_W_M) : /* and-m.w [${Rs}${inc}],${Rd} */
10283 {
10284   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10285   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10286 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10287   int UNUSED written = 0;
10288   IADDR UNUSED pc = abuf->addr;
10289   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10290
10291 {
10292   HI tmp_tmpd;
10293   tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10294   HI tmp_tmp_mem;
10295   BI tmp_postinc;
10296   tmp_postinc = FLD (f_memmode);
10297 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
10298 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
10299 ; if (NEBI (tmp_postinc, 0)) {
10300 {
10301 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10302   tmp_addr = ADDSI (tmp_addr, 2);
10303 }
10304   {
10305     SI opval = tmp_addr;
10306     SET_H_GR (FLD (f_operand1), opval);
10307     written |= (1 << 11);
10308     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10309   }
10310 }
10311 }
10312 ; tmp_tmp_mem; }));
10313 {
10314   SI tmp_oldregval;
10315   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
10316   {
10317     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10318     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10319     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10320   }
10321 }
10322 {
10323   {
10324     BI opval = LTHI (tmp_tmpd, 0);
10325     CPU (h_nbit) = opval;
10326     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10327   }
10328   {
10329     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10330     CPU (h_zbit) = opval;
10331     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10332   }
10333 SET_H_CBIT_MOVE (0);
10334 SET_H_VBIT_MOVE (0);
10335 {
10336   {
10337     BI opval = 0;
10338     CPU (h_xbit) = opval;
10339     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10340   }
10341   {
10342     BI opval = 0;
10343     SET_H_INSN_PREFIXED_P (opval);
10344     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10345   }
10346 }
10347 }
10348 }
10349
10350   abuf->written = written;
10351 #undef FLD
10352 }
10353   NEXT (vpc);
10354
10355   CASE (sem, INSN_AND_M_D_M) : /* and-m.d [${Rs}${inc}],${Rd} */
10356 {
10357   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10358   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10359 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10360   int UNUSED written = 0;
10361   IADDR UNUSED pc = abuf->addr;
10362   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10363
10364 {
10365   SI tmp_tmpd;
10366   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10367   SI tmp_tmp_mem;
10368   BI tmp_postinc;
10369   tmp_postinc = FLD (f_memmode);
10370 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
10371 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
10372 ; if (NEBI (tmp_postinc, 0)) {
10373 {
10374 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10375   tmp_addr = ADDSI (tmp_addr, 4);
10376 }
10377   {
10378     SI opval = tmp_addr;
10379     SET_H_GR (FLD (f_operand1), opval);
10380     written |= (1 << 10);
10381     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10382   }
10383 }
10384 }
10385 ; tmp_tmp_mem; }));
10386   {
10387     SI opval = tmp_tmpd;
10388     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10389     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10390   }
10391 {
10392   {
10393     BI opval = LTSI (tmp_tmpd, 0);
10394     CPU (h_nbit) = opval;
10395     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10396   }
10397   {
10398     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10399     CPU (h_zbit) = opval;
10400     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10401   }
10402 SET_H_CBIT_MOVE (0);
10403 SET_H_VBIT_MOVE (0);
10404 {
10405   {
10406     BI opval = 0;
10407     CPU (h_xbit) = opval;
10408     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10409   }
10410   {
10411     BI opval = 0;
10412     SET_H_INSN_PREFIXED_P (opval);
10413     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10414   }
10415 }
10416 }
10417 }
10418
10419   abuf->written = written;
10420 #undef FLD
10421 }
10422   NEXT (vpc);
10423
10424   CASE (sem, INSN_ANDCBR) : /* and.b ${sconst8}],${Rd} */
10425 {
10426   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10427   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10428 #define FLD(f) abuf->fields.sfmt_addcbr.f
10429   int UNUSED written = 0;
10430   IADDR UNUSED pc = abuf->addr;
10431   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
10432
10433 {
10434   QI tmp_tmpd;
10435   tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__byte));
10436 {
10437   SI tmp_oldregval;
10438   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
10439   {
10440     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10441     SET_H_GR (FLD (f_operand2), opval);
10442     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10443   }
10444 }
10445 {
10446   {
10447     BI opval = LTQI (tmp_tmpd, 0);
10448     CPU (h_nbit) = opval;
10449     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10450   }
10451   {
10452     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10453     CPU (h_zbit) = opval;
10454     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10455   }
10456 SET_H_CBIT_MOVE (0);
10457 SET_H_VBIT_MOVE (0);
10458 {
10459   {
10460     BI opval = 0;
10461     CPU (h_xbit) = opval;
10462     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10463   }
10464   {
10465     BI opval = 0;
10466     SET_H_INSN_PREFIXED_P (opval);
10467     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10468   }
10469 }
10470 }
10471 }
10472
10473 #undef FLD
10474 }
10475   NEXT (vpc);
10476
10477   CASE (sem, INSN_ANDCWR) : /* and.w ${sconst16}],${Rd} */
10478 {
10479   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10480   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10481 #define FLD(f) abuf->fields.sfmt_addcwr.f
10482   int UNUSED written = 0;
10483   IADDR UNUSED pc = abuf->addr;
10484   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
10485
10486 {
10487   HI tmp_tmpd;
10488   tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__word));
10489 {
10490   SI tmp_oldregval;
10491   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
10492   {
10493     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10494     SET_H_GR (FLD (f_operand2), opval);
10495     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10496   }
10497 }
10498 {
10499   {
10500     BI opval = LTHI (tmp_tmpd, 0);
10501     CPU (h_nbit) = opval;
10502     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10503   }
10504   {
10505     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10506     CPU (h_zbit) = opval;
10507     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10508   }
10509 SET_H_CBIT_MOVE (0);
10510 SET_H_VBIT_MOVE (0);
10511 {
10512   {
10513     BI opval = 0;
10514     CPU (h_xbit) = opval;
10515     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10516   }
10517   {
10518     BI opval = 0;
10519     SET_H_INSN_PREFIXED_P (opval);
10520     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10521   }
10522 }
10523 }
10524 }
10525
10526 #undef FLD
10527 }
10528   NEXT (vpc);
10529
10530   CASE (sem, INSN_ANDCDR) : /* and.d ${const32}],${Rd} */
10531 {
10532   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10533   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10534 #define FLD(f) abuf->fields.sfmt_addcdr.f
10535   int UNUSED written = 0;
10536   IADDR UNUSED pc = abuf->addr;
10537   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
10538
10539 {
10540   SI tmp_tmpd;
10541   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
10542   {
10543     SI opval = tmp_tmpd;
10544     SET_H_GR (FLD (f_operand2), opval);
10545     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10546   }
10547 {
10548   {
10549     BI opval = LTSI (tmp_tmpd, 0);
10550     CPU (h_nbit) = opval;
10551     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10552   }
10553   {
10554     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10555     CPU (h_zbit) = opval;
10556     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10557   }
10558 SET_H_CBIT_MOVE (0);
10559 SET_H_VBIT_MOVE (0);
10560 {
10561   {
10562     BI opval = 0;
10563     CPU (h_xbit) = opval;
10564     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10565   }
10566   {
10567     BI opval = 0;
10568     SET_H_INSN_PREFIXED_P (opval);
10569     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10570   }
10571 }
10572 }
10573 }
10574
10575 #undef FLD
10576 }
10577   NEXT (vpc);
10578
10579   CASE (sem, INSN_ANDQ) : /* andq $i,$Rd */
10580 {
10581   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10582   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10583 #define FLD(f) abuf->fields.sfmt_andq.f
10584   int UNUSED written = 0;
10585   IADDR UNUSED pc = abuf->addr;
10586   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10587
10588 {
10589   SI tmp_tmpd;
10590   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), FLD (f_s6));
10591   {
10592     SI opval = tmp_tmpd;
10593     SET_H_GR (FLD (f_operand2), opval);
10594     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10595   }
10596 {
10597   {
10598     BI opval = LTSI (tmp_tmpd, 0);
10599     CPU (h_nbit) = opval;
10600     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10601   }
10602   {
10603     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10604     CPU (h_zbit) = opval;
10605     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10606   }
10607 SET_H_CBIT_MOVE (0);
10608 SET_H_VBIT_MOVE (0);
10609 {
10610   {
10611     BI opval = 0;
10612     CPU (h_xbit) = opval;
10613     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10614   }
10615   {
10616     BI opval = 0;
10617     SET_H_INSN_PREFIXED_P (opval);
10618     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10619   }
10620 }
10621 }
10622 }
10623
10624 #undef FLD
10625 }
10626   NEXT (vpc);
10627
10628   CASE (sem, INSN_ORR_B_R) : /* orr.b $Rs,$Rd */
10629 {
10630   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10631   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10632 #define FLD(f) abuf->fields.sfmt_addc_m.f
10633   int UNUSED written = 0;
10634   IADDR UNUSED pc = abuf->addr;
10635   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10636
10637 {
10638   QI tmp_tmpd;
10639   tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10640 {
10641   SI tmp_oldregval;
10642   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
10643   {
10644     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10645     SET_H_GR (FLD (f_operand2), opval);
10646     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10647   }
10648 }
10649 {
10650   {
10651     BI opval = LTQI (tmp_tmpd, 0);
10652     CPU (h_nbit) = opval;
10653     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10654   }
10655   {
10656     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10657     CPU (h_zbit) = opval;
10658     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10659   }
10660 SET_H_CBIT_MOVE (0);
10661 SET_H_VBIT_MOVE (0);
10662 {
10663   {
10664     BI opval = 0;
10665     CPU (h_xbit) = opval;
10666     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10667   }
10668   {
10669     BI opval = 0;
10670     SET_H_INSN_PREFIXED_P (opval);
10671     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10672   }
10673 }
10674 }
10675 }
10676
10677 #undef FLD
10678 }
10679   NEXT (vpc);
10680
10681   CASE (sem, INSN_ORR_W_R) : /* orr.w $Rs,$Rd */
10682 {
10683   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10684   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10685 #define FLD(f) abuf->fields.sfmt_addc_m.f
10686   int UNUSED written = 0;
10687   IADDR UNUSED pc = abuf->addr;
10688   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10689
10690 {
10691   HI tmp_tmpd;
10692   tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10693 {
10694   SI tmp_oldregval;
10695   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
10696   {
10697     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10698     SET_H_GR (FLD (f_operand2), opval);
10699     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10700   }
10701 }
10702 {
10703   {
10704     BI opval = LTHI (tmp_tmpd, 0);
10705     CPU (h_nbit) = opval;
10706     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10707   }
10708   {
10709     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10710     CPU (h_zbit) = opval;
10711     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10712   }
10713 SET_H_CBIT_MOVE (0);
10714 SET_H_VBIT_MOVE (0);
10715 {
10716   {
10717     BI opval = 0;
10718     CPU (h_xbit) = opval;
10719     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10720   }
10721   {
10722     BI opval = 0;
10723     SET_H_INSN_PREFIXED_P (opval);
10724     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10725   }
10726 }
10727 }
10728 }
10729
10730 #undef FLD
10731 }
10732   NEXT (vpc);
10733
10734   CASE (sem, INSN_ORR_D_R) : /* orr.d $Rs,$Rd */
10735 {
10736   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10737   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10738 #define FLD(f) abuf->fields.sfmt_addc_m.f
10739   int UNUSED written = 0;
10740   IADDR UNUSED pc = abuf->addr;
10741   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10742
10743 {
10744   SI tmp_tmpd;
10745   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10746   {
10747     SI opval = tmp_tmpd;
10748     SET_H_GR (FLD (f_operand2), opval);
10749     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10750   }
10751 {
10752   {
10753     BI opval = LTSI (tmp_tmpd, 0);
10754     CPU (h_nbit) = opval;
10755     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10756   }
10757   {
10758     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10759     CPU (h_zbit) = opval;
10760     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10761   }
10762 SET_H_CBIT_MOVE (0);
10763 SET_H_VBIT_MOVE (0);
10764 {
10765   {
10766     BI opval = 0;
10767     CPU (h_xbit) = opval;
10768     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10769   }
10770   {
10771     BI opval = 0;
10772     SET_H_INSN_PREFIXED_P (opval);
10773     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10774   }
10775 }
10776 }
10777 }
10778
10779 #undef FLD
10780 }
10781   NEXT (vpc);
10782
10783   CASE (sem, INSN_OR_M_B_M) : /* or-m.b [${Rs}${inc}],${Rd} */
10784 {
10785   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10786   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10787 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10788   int UNUSED written = 0;
10789   IADDR UNUSED pc = abuf->addr;
10790   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10791
10792 {
10793   QI tmp_tmpd;
10794   tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10795   QI tmp_tmp_mem;
10796   BI tmp_postinc;
10797   tmp_postinc = FLD (f_memmode);
10798 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
10799 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
10800 ; if (NEBI (tmp_postinc, 0)) {
10801 {
10802 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10803   tmp_addr = ADDSI (tmp_addr, 1);
10804 }
10805   {
10806     SI opval = tmp_addr;
10807     SET_H_GR (FLD (f_operand1), opval);
10808     written |= (1 << 11);
10809     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10810   }
10811 }
10812 }
10813 ; tmp_tmp_mem; }));
10814 {
10815   SI tmp_oldregval;
10816   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
10817   {
10818     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10819     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10820     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10821   }
10822 }
10823 {
10824   {
10825     BI opval = LTQI (tmp_tmpd, 0);
10826     CPU (h_nbit) = opval;
10827     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10828   }
10829   {
10830     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10831     CPU (h_zbit) = opval;
10832     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10833   }
10834 SET_H_CBIT_MOVE (0);
10835 SET_H_VBIT_MOVE (0);
10836 {
10837   {
10838     BI opval = 0;
10839     CPU (h_xbit) = opval;
10840     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10841   }
10842   {
10843     BI opval = 0;
10844     SET_H_INSN_PREFIXED_P (opval);
10845     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10846   }
10847 }
10848 }
10849 }
10850
10851   abuf->written = written;
10852 #undef FLD
10853 }
10854   NEXT (vpc);
10855
10856   CASE (sem, INSN_OR_M_W_M) : /* or-m.w [${Rs}${inc}],${Rd} */
10857 {
10858   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10859   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10860 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10861   int UNUSED written = 0;
10862   IADDR UNUSED pc = abuf->addr;
10863   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10864
10865 {
10866   HI tmp_tmpd;
10867   tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10868   HI tmp_tmp_mem;
10869   BI tmp_postinc;
10870   tmp_postinc = FLD (f_memmode);
10871 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
10872 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
10873 ; if (NEBI (tmp_postinc, 0)) {
10874 {
10875 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10876   tmp_addr = ADDSI (tmp_addr, 2);
10877 }
10878   {
10879     SI opval = tmp_addr;
10880     SET_H_GR (FLD (f_operand1), opval);
10881     written |= (1 << 11);
10882     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10883   }
10884 }
10885 }
10886 ; tmp_tmp_mem; }));
10887 {
10888   SI tmp_oldregval;
10889   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
10890   {
10891     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10892     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10893     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10894   }
10895 }
10896 {
10897   {
10898     BI opval = LTHI (tmp_tmpd, 0);
10899     CPU (h_nbit) = opval;
10900     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10901   }
10902   {
10903     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10904     CPU (h_zbit) = opval;
10905     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10906   }
10907 SET_H_CBIT_MOVE (0);
10908 SET_H_VBIT_MOVE (0);
10909 {
10910   {
10911     BI opval = 0;
10912     CPU (h_xbit) = opval;
10913     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10914   }
10915   {
10916     BI opval = 0;
10917     SET_H_INSN_PREFIXED_P (opval);
10918     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10919   }
10920 }
10921 }
10922 }
10923
10924   abuf->written = written;
10925 #undef FLD
10926 }
10927   NEXT (vpc);
10928
10929   CASE (sem, INSN_OR_M_D_M) : /* or-m.d [${Rs}${inc}],${Rd} */
10930 {
10931   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10932   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10933 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10934   int UNUSED written = 0;
10935   IADDR UNUSED pc = abuf->addr;
10936   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10937
10938 {
10939   SI tmp_tmpd;
10940   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10941   SI tmp_tmp_mem;
10942   BI tmp_postinc;
10943   tmp_postinc = FLD (f_memmode);
10944 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
10945 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
10946 ; if (NEBI (tmp_postinc, 0)) {
10947 {
10948 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10949   tmp_addr = ADDSI (tmp_addr, 4);
10950 }
10951   {
10952     SI opval = tmp_addr;
10953     SET_H_GR (FLD (f_operand1), opval);
10954     written |= (1 << 10);
10955     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10956   }
10957 }
10958 }
10959 ; tmp_tmp_mem; }));
10960   {
10961     SI opval = tmp_tmpd;
10962     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10963     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10964   }
10965 {
10966   {
10967     BI opval = LTSI (tmp_tmpd, 0);
10968     CPU (h_nbit) = opval;
10969     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10970   }
10971   {
10972     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10973     CPU (h_zbit) = opval;
10974     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10975   }
10976 SET_H_CBIT_MOVE (0);
10977 SET_H_VBIT_MOVE (0);
10978 {
10979   {
10980     BI opval = 0;
10981     CPU (h_xbit) = opval;
10982     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10983   }
10984   {
10985     BI opval = 0;
10986     SET_H_INSN_PREFIXED_P (opval);
10987     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10988   }
10989 }
10990 }
10991 }
10992
10993   abuf->written = written;
10994 #undef FLD
10995 }
10996   NEXT (vpc);
10997
10998   CASE (sem, INSN_ORCBR) : /* or.b ${sconst8}],${Rd} */
10999 {
11000   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11001   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11002 #define FLD(f) abuf->fields.sfmt_addcbr.f
11003   int UNUSED written = 0;
11004   IADDR UNUSED pc = abuf->addr;
11005   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
11006
11007 {
11008   QI tmp_tmpd;
11009   tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__byte));
11010 {
11011   SI tmp_oldregval;
11012   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
11013   {
11014     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
11015     SET_H_GR (FLD (f_operand2), opval);
11016     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11017   }
11018 }
11019 {
11020   {
11021     BI opval = LTQI (tmp_tmpd, 0);
11022     CPU (h_nbit) = opval;
11023     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11024   }
11025   {
11026     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11027     CPU (h_zbit) = opval;
11028     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11029   }
11030 SET_H_CBIT_MOVE (0);
11031 SET_H_VBIT_MOVE (0);
11032 {
11033   {
11034     BI opval = 0;
11035     CPU (h_xbit) = opval;
11036     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11037   }
11038   {
11039     BI opval = 0;
11040     SET_H_INSN_PREFIXED_P (opval);
11041     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11042   }
11043 }
11044 }
11045 }
11046
11047 #undef FLD
11048 }
11049   NEXT (vpc);
11050
11051   CASE (sem, INSN_ORCWR) : /* or.w ${sconst16}],${Rd} */
11052 {
11053   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11054   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11055 #define FLD(f) abuf->fields.sfmt_addcwr.f
11056   int UNUSED written = 0;
11057   IADDR UNUSED pc = abuf->addr;
11058   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
11059
11060 {
11061   HI tmp_tmpd;
11062   tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__word));
11063 {
11064   SI tmp_oldregval;
11065   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
11066   {
11067     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
11068     SET_H_GR (FLD (f_operand2), opval);
11069     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11070   }
11071 }
11072 {
11073   {
11074     BI opval = LTHI (tmp_tmpd, 0);
11075     CPU (h_nbit) = opval;
11076     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11077   }
11078   {
11079     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11080     CPU (h_zbit) = opval;
11081     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11082   }
11083 SET_H_CBIT_MOVE (0);
11084 SET_H_VBIT_MOVE (0);
11085 {
11086   {
11087     BI opval = 0;
11088     CPU (h_xbit) = opval;
11089     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11090   }
11091   {
11092     BI opval = 0;
11093     SET_H_INSN_PREFIXED_P (opval);
11094     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11095   }
11096 }
11097 }
11098 }
11099
11100 #undef FLD
11101 }
11102   NEXT (vpc);
11103
11104   CASE (sem, INSN_ORCDR) : /* or.d ${const32}],${Rd} */
11105 {
11106   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11107   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11108 #define FLD(f) abuf->fields.sfmt_addcdr.f
11109   int UNUSED written = 0;
11110   IADDR UNUSED pc = abuf->addr;
11111   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
11112
11113 {
11114   SI tmp_tmpd;
11115   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
11116   {
11117     SI opval = tmp_tmpd;
11118     SET_H_GR (FLD (f_operand2), opval);
11119     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11120   }
11121 {
11122   {
11123     BI opval = LTSI (tmp_tmpd, 0);
11124     CPU (h_nbit) = opval;
11125     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11126   }
11127   {
11128     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11129     CPU (h_zbit) = opval;
11130     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11131   }
11132 SET_H_CBIT_MOVE (0);
11133 SET_H_VBIT_MOVE (0);
11134 {
11135   {
11136     BI opval = 0;
11137     CPU (h_xbit) = opval;
11138     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11139   }
11140   {
11141     BI opval = 0;
11142     SET_H_INSN_PREFIXED_P (opval);
11143     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11144   }
11145 }
11146 }
11147 }
11148
11149 #undef FLD
11150 }
11151   NEXT (vpc);
11152
11153   CASE (sem, INSN_ORQ) : /* orq $i,$Rd */
11154 {
11155   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11156   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11157 #define FLD(f) abuf->fields.sfmt_andq.f
11158   int UNUSED written = 0;
11159   IADDR UNUSED pc = abuf->addr;
11160   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11161
11162 {
11163   SI tmp_tmpd;
11164   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), FLD (f_s6));
11165   {
11166     SI opval = tmp_tmpd;
11167     SET_H_GR (FLD (f_operand2), opval);
11168     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11169   }
11170 {
11171   {
11172     BI opval = LTSI (tmp_tmpd, 0);
11173     CPU (h_nbit) = opval;
11174     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11175   }
11176   {
11177     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11178     CPU (h_zbit) = opval;
11179     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11180   }
11181 SET_H_CBIT_MOVE (0);
11182 SET_H_VBIT_MOVE (0);
11183 {
11184   {
11185     BI opval = 0;
11186     CPU (h_xbit) = opval;
11187     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11188   }
11189   {
11190     BI opval = 0;
11191     SET_H_INSN_PREFIXED_P (opval);
11192     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11193   }
11194 }
11195 }
11196 }
11197
11198 #undef FLD
11199 }
11200   NEXT (vpc);
11201
11202   CASE (sem, INSN_XOR) : /* xor $Rs,$Rd */
11203 {
11204   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11205   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11206 #define FLD(f) abuf->fields.sfmt_muls_b.f
11207   int UNUSED written = 0;
11208   IADDR UNUSED pc = abuf->addr;
11209   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11210
11211 {
11212   SI tmp_tmpd;
11213   tmp_tmpd = XORSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
11214   {
11215     SI opval = tmp_tmpd;
11216     SET_H_GR (FLD (f_operand2), opval);
11217     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11218   }
11219 {
11220   {
11221     BI opval = LTSI (tmp_tmpd, 0);
11222     CPU (h_nbit) = opval;
11223     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11224   }
11225   {
11226     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11227     CPU (h_zbit) = opval;
11228     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11229   }
11230 SET_H_CBIT_MOVE (0);
11231 SET_H_VBIT_MOVE (0);
11232 {
11233   {
11234     BI opval = 0;
11235     CPU (h_xbit) = opval;
11236     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11237   }
11238   {
11239     BI opval = 0;
11240     SET_H_INSN_PREFIXED_P (opval);
11241     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11242   }
11243 }
11244 }
11245 }
11246
11247 #undef FLD
11248 }
11249   NEXT (vpc);
11250
11251   CASE (sem, INSN_SWAP) : /* swap${swapoption} ${Rs} */
11252 {
11253   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11254   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11255 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
11256   int UNUSED written = 0;
11257   IADDR UNUSED pc = abuf->addr;
11258   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11259
11260 {
11261   SI tmp_tmps;
11262   SI tmp_tmpd;
11263   tmp_tmps = GET_H_GR (FLD (f_operand1));
11264   tmp_tmpd = ({   SI tmp_tmpcode;
11265   SI tmp_tmpval;
11266   SI tmp_tmpres;
11267   tmp_tmpcode = FLD (f_operand2);
11268 ;   tmp_tmpval = tmp_tmps;
11269 ; if (EQSI (tmp_tmpcode, 0)) {
11270   tmp_tmpres = (cgen_rtx_error (current_cpu, "SWAP without swap modifier isn't implemented"), 0);
11271 }
11272  else if (EQSI (tmp_tmpcode, 1)) {
11273   tmp_tmpres = ({   SI tmp_tmpr;
11274   tmp_tmpr = tmp_tmpval;
11275 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11276 }
11277  else if (EQSI (tmp_tmpcode, 2)) {
11278   tmp_tmpres = ({   SI tmp_tmpb;
11279   tmp_tmpb = tmp_tmpval;
11280 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11281 }
11282  else if (EQSI (tmp_tmpcode, 3)) {
11283   tmp_tmpres = ({   SI tmp_tmpr;
11284   tmp_tmpr = ({   SI tmp_tmpb;
11285   tmp_tmpb = tmp_tmpval;
11286 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11287 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11288 }
11289  else if (EQSI (tmp_tmpcode, 4)) {
11290   tmp_tmpres = ({   SI tmp_tmpb;
11291   tmp_tmpb = tmp_tmpval;
11292 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11293 }
11294  else if (EQSI (tmp_tmpcode, 5)) {
11295   tmp_tmpres = ({   SI tmp_tmpr;
11296   tmp_tmpr = ({   SI tmp_tmpb;
11297   tmp_tmpb = tmp_tmpval;
11298 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11299 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11300 }
11301  else if (EQSI (tmp_tmpcode, 6)) {
11302   tmp_tmpres = ({   SI tmp_tmpb;
11303   tmp_tmpb = ({   SI tmp_tmpb;
11304   tmp_tmpb = tmp_tmpval;
11305 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11306 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11307 }
11308  else if (EQSI (tmp_tmpcode, 7)) {
11309   tmp_tmpres = ({   SI tmp_tmpr;
11310   tmp_tmpr = ({   SI tmp_tmpb;
11311   tmp_tmpb = ({   SI tmp_tmpb;
11312   tmp_tmpb = tmp_tmpval;
11313 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11314 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11315 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11316 }
11317  else if (EQSI (tmp_tmpcode, 8)) {
11318   tmp_tmpres = INVSI (tmp_tmpval);
11319 }
11320  else if (EQSI (tmp_tmpcode, 9)) {
11321   tmp_tmpres = ({   SI tmp_tmpr;
11322   tmp_tmpr = INVSI (tmp_tmpval);
11323 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11324 }
11325  else if (EQSI (tmp_tmpcode, 10)) {
11326   tmp_tmpres = ({   SI tmp_tmpb;
11327   tmp_tmpb = INVSI (tmp_tmpval);
11328 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11329 }
11330  else if (EQSI (tmp_tmpcode, 11)) {
11331   tmp_tmpres = ({   SI tmp_tmpr;
11332   tmp_tmpr = ({   SI tmp_tmpb;
11333   tmp_tmpb = INVSI (tmp_tmpval);
11334 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11335 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11336 }
11337  else if (EQSI (tmp_tmpcode, 12)) {
11338   tmp_tmpres = ({   SI tmp_tmpb;
11339   tmp_tmpb = INVSI (tmp_tmpval);
11340 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11341 }
11342  else if (EQSI (tmp_tmpcode, 13)) {
11343   tmp_tmpres = ({   SI tmp_tmpr;
11344   tmp_tmpr = ({   SI tmp_tmpb;
11345   tmp_tmpb = INVSI (tmp_tmpval);
11346 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11347 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11348 }
11349  else if (EQSI (tmp_tmpcode, 14)) {
11350   tmp_tmpres = ({   SI tmp_tmpb;
11351   tmp_tmpb = ({   SI tmp_tmpb;
11352   tmp_tmpb = INVSI (tmp_tmpval);
11353 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11354 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11355 }
11356  else if (EQSI (tmp_tmpcode, 15)) {
11357   tmp_tmpres = ({   SI tmp_tmpr;
11358   tmp_tmpr = ({   SI tmp_tmpb;
11359   tmp_tmpb = ({   SI tmp_tmpb;
11360   tmp_tmpb = INVSI (tmp_tmpval);
11361 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11362 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11363 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11364 }
11365 ; tmp_tmpres; });
11366   {
11367     SI opval = tmp_tmpd;
11368     SET_H_GR (FLD (f_operand1), opval);
11369     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11370   }
11371 {
11372   {
11373     BI opval = LTSI (tmp_tmpd, 0);
11374     CPU (h_nbit) = opval;
11375     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11376   }
11377   {
11378     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11379     CPU (h_zbit) = opval;
11380     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11381   }
11382 SET_H_CBIT_MOVE (0);
11383 SET_H_VBIT_MOVE (0);
11384 {
11385   {
11386     BI opval = 0;
11387     CPU (h_xbit) = opval;
11388     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11389   }
11390   {
11391     BI opval = 0;
11392     SET_H_INSN_PREFIXED_P (opval);
11393     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11394   }
11395 }
11396 }
11397 }
11398
11399 #undef FLD
11400 }
11401   NEXT (vpc);
11402
11403   CASE (sem, INSN_ASRR_B_R) : /* asrr.b $Rs,$Rd */
11404 {
11405   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11406   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11407 #define FLD(f) abuf->fields.sfmt_addc_m.f
11408   int UNUSED written = 0;
11409   IADDR UNUSED pc = abuf->addr;
11410   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11411
11412 {
11413   QI tmp_tmpd;
11414   SI tmp_cnt1;
11415   SI tmp_cnt2;
11416   tmp_cnt1 = GET_H_GR (FLD (f_operand1));
11417   tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
11418   tmp_tmpd = SRASI (EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
11419 {
11420   SI tmp_oldregval;
11421   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
11422   {
11423     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
11424     SET_H_GR (FLD (f_operand2), opval);
11425     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11426   }
11427 }
11428 {
11429   {
11430     BI opval = LTQI (tmp_tmpd, 0);
11431     CPU (h_nbit) = opval;
11432     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11433   }
11434   {
11435     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11436     CPU (h_zbit) = opval;
11437     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11438   }
11439 SET_H_CBIT_MOVE (0);
11440 SET_H_VBIT_MOVE (0);
11441 {
11442   {
11443     BI opval = 0;
11444     CPU (h_xbit) = opval;
11445     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11446   }
11447   {
11448     BI opval = 0;
11449     SET_H_INSN_PREFIXED_P (opval);
11450     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11451   }
11452 }
11453 }
11454 }
11455
11456 #undef FLD
11457 }
11458   NEXT (vpc);
11459
11460   CASE (sem, INSN_ASRR_W_R) : /* asrr.w $Rs,$Rd */
11461 {
11462   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11463   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11464 #define FLD(f) abuf->fields.sfmt_addc_m.f
11465   int UNUSED written = 0;
11466   IADDR UNUSED pc = abuf->addr;
11467   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11468
11469 {
11470   HI tmp_tmpd;
11471   SI tmp_cnt1;
11472   SI tmp_cnt2;
11473   tmp_cnt1 = GET_H_GR (FLD (f_operand1));
11474   tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
11475   tmp_tmpd = SRASI (EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
11476 {
11477   SI tmp_oldregval;
11478   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
11479   {
11480     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
11481     SET_H_GR (FLD (f_operand2), opval);
11482     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11483   }
11484 }
11485 {
11486   {
11487     BI opval = LTHI (tmp_tmpd, 0);
11488     CPU (h_nbit) = opval;
11489     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11490   }
11491   {
11492     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11493     CPU (h_zbit) = opval;
11494     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11495   }
11496 SET_H_CBIT_MOVE (0);
11497 SET_H_VBIT_MOVE (0);
11498 {
11499   {
11500     BI opval = 0;
11501     CPU (h_xbit) = opval;
11502     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11503   }
11504   {
11505     BI opval = 0;
11506     SET_H_INSN_PREFIXED_P (opval);
11507     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11508   }
11509 }
11510 }
11511 }
11512
11513 #undef FLD
11514 }
11515   NEXT (vpc);
11516
11517   CASE (sem, INSN_ASRR_D_R) : /* asrr.d $Rs,$Rd */
11518 {
11519   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11520   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11521 #define FLD(f) abuf->fields.sfmt_addc_m.f
11522   int UNUSED written = 0;
11523   IADDR UNUSED pc = abuf->addr;
11524   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11525
11526 {
11527   SI tmp_tmpd;
11528   SI tmp_cnt1;
11529   SI tmp_cnt2;
11530   tmp_cnt1 = GET_H_GR (FLD (f_operand1));
11531   tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
11532   tmp_tmpd = SRASI (EXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
11533   {
11534     SI opval = tmp_tmpd;
11535     SET_H_GR (FLD (f_operand2), opval);
11536     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11537   }
11538 {
11539   {
11540     BI opval = LTSI (tmp_tmpd, 0);
11541     CPU (h_nbit) = opval;
11542     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11543   }
11544   {
11545     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11546     CPU (h_zbit) = opval;
11547     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11548   }
11549 SET_H_CBIT_MOVE (0);
11550 SET_H_VBIT_MOVE (0);
11551 {
11552   {
11553     BI opval = 0;
11554     CPU (h_xbit) = opval;
11555     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11556   }
11557   {
11558     BI opval = 0;
11559     SET_H_INSN_PREFIXED_P (opval);
11560     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11561   }
11562 }
11563 }
11564 }
11565
11566 #undef FLD
11567 }
11568   NEXT (vpc);
11569
11570   CASE (sem, INSN_ASRQ) : /* asrq $c,${Rd} */
11571 {
11572   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11573   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11574 #define FLD(f) abuf->fields.sfmt_asrq.f
11575   int UNUSED written = 0;
11576   IADDR UNUSED pc = abuf->addr;
11577   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11578
11579 {
11580   SI tmp_tmpd;
11581   tmp_tmpd = SRASI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
11582   {
11583     SI opval = tmp_tmpd;
11584     SET_H_GR (FLD (f_operand2), opval);
11585     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11586   }
11587 {
11588   {
11589     BI opval = LTSI (tmp_tmpd, 0);
11590     CPU (h_nbit) = opval;
11591     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11592   }
11593   {
11594     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11595     CPU (h_zbit) = opval;
11596     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11597   }
11598 SET_H_CBIT_MOVE (0);
11599 SET_H_VBIT_MOVE (0);
11600 {
11601   {
11602     BI opval = 0;
11603     CPU (h_xbit) = opval;
11604     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11605   }
11606   {
11607     BI opval = 0;
11608     SET_H_INSN_PREFIXED_P (opval);
11609     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11610   }
11611 }
11612 }
11613 }
11614
11615 #undef FLD
11616 }
11617   NEXT (vpc);
11618
11619   CASE (sem, INSN_LSRR_B_R) : /* lsrr.b $Rs,$Rd */
11620 {
11621   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11622   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11623 #define FLD(f) abuf->fields.sfmt_addc_m.f
11624   int UNUSED written = 0;
11625   IADDR UNUSED pc = abuf->addr;
11626   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11627
11628 {
11629   SI tmp_tmpd;
11630   SI tmp_cnt;
11631   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11632   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11633 {
11634   SI tmp_oldregval;
11635   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
11636   {
11637     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
11638     SET_H_GR (FLD (f_operand2), opval);
11639     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11640   }
11641 }
11642 {
11643   {
11644     BI opval = LTQI (tmp_tmpd, 0);
11645     CPU (h_nbit) = opval;
11646     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11647   }
11648   {
11649     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11650     CPU (h_zbit) = opval;
11651     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11652   }
11653 SET_H_CBIT_MOVE (0);
11654 SET_H_VBIT_MOVE (0);
11655 {
11656   {
11657     BI opval = 0;
11658     CPU (h_xbit) = opval;
11659     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11660   }
11661   {
11662     BI opval = 0;
11663     SET_H_INSN_PREFIXED_P (opval);
11664     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11665   }
11666 }
11667 }
11668 }
11669
11670 #undef FLD
11671 }
11672   NEXT (vpc);
11673
11674   CASE (sem, INSN_LSRR_W_R) : /* lsrr.w $Rs,$Rd */
11675 {
11676   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11677   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11678 #define FLD(f) abuf->fields.sfmt_addc_m.f
11679   int UNUSED written = 0;
11680   IADDR UNUSED pc = abuf->addr;
11681   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11682
11683 {
11684   SI tmp_tmpd;
11685   SI tmp_cnt;
11686   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11687   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11688 {
11689   SI tmp_oldregval;
11690   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
11691   {
11692     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
11693     SET_H_GR (FLD (f_operand2), opval);
11694     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11695   }
11696 }
11697 {
11698   {
11699     BI opval = LTHI (tmp_tmpd, 0);
11700     CPU (h_nbit) = opval;
11701     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11702   }
11703   {
11704     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11705     CPU (h_zbit) = opval;
11706     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11707   }
11708 SET_H_CBIT_MOVE (0);
11709 SET_H_VBIT_MOVE (0);
11710 {
11711   {
11712     BI opval = 0;
11713     CPU (h_xbit) = opval;
11714     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11715   }
11716   {
11717     BI opval = 0;
11718     SET_H_INSN_PREFIXED_P (opval);
11719     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11720   }
11721 }
11722 }
11723 }
11724
11725 #undef FLD
11726 }
11727   NEXT (vpc);
11728
11729   CASE (sem, INSN_LSRR_D_R) : /* lsrr.d $Rs,$Rd */
11730 {
11731   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11732   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11733 #define FLD(f) abuf->fields.sfmt_addc_m.f
11734   int UNUSED written = 0;
11735   IADDR UNUSED pc = abuf->addr;
11736   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11737
11738 {
11739   SI tmp_tmpd;
11740   SI tmp_cnt;
11741   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11742   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11743   {
11744     SI opval = tmp_tmpd;
11745     SET_H_GR (FLD (f_operand2), opval);
11746     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11747   }
11748 {
11749   {
11750     BI opval = LTSI (tmp_tmpd, 0);
11751     CPU (h_nbit) = opval;
11752     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11753   }
11754   {
11755     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11756     CPU (h_zbit) = opval;
11757     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11758   }
11759 SET_H_CBIT_MOVE (0);
11760 SET_H_VBIT_MOVE (0);
11761 {
11762   {
11763     BI opval = 0;
11764     CPU (h_xbit) = opval;
11765     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11766   }
11767   {
11768     BI opval = 0;
11769     SET_H_INSN_PREFIXED_P (opval);
11770     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11771   }
11772 }
11773 }
11774 }
11775
11776 #undef FLD
11777 }
11778   NEXT (vpc);
11779
11780   CASE (sem, INSN_LSRQ) : /* lsrq $c,${Rd} */
11781 {
11782   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11783   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11784 #define FLD(f) abuf->fields.sfmt_asrq.f
11785   int UNUSED written = 0;
11786   IADDR UNUSED pc = abuf->addr;
11787   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11788
11789 {
11790   SI tmp_tmpd;
11791   tmp_tmpd = SRLSI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
11792   {
11793     SI opval = tmp_tmpd;
11794     SET_H_GR (FLD (f_operand2), opval);
11795     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11796   }
11797 {
11798   {
11799     BI opval = LTSI (tmp_tmpd, 0);
11800     CPU (h_nbit) = opval;
11801     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11802   }
11803   {
11804     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11805     CPU (h_zbit) = opval;
11806     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11807   }
11808 SET_H_CBIT_MOVE (0);
11809 SET_H_VBIT_MOVE (0);
11810 {
11811   {
11812     BI opval = 0;
11813     CPU (h_xbit) = opval;
11814     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11815   }
11816   {
11817     BI opval = 0;
11818     SET_H_INSN_PREFIXED_P (opval);
11819     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11820   }
11821 }
11822 }
11823 }
11824
11825 #undef FLD
11826 }
11827   NEXT (vpc);
11828
11829   CASE (sem, INSN_LSLR_B_R) : /* lslr.b $Rs,$Rd */
11830 {
11831   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11832   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11833 #define FLD(f) abuf->fields.sfmt_addc_m.f
11834   int UNUSED written = 0;
11835   IADDR UNUSED pc = abuf->addr;
11836   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11837
11838 {
11839   SI tmp_tmpd;
11840   SI tmp_cnt;
11841   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11842   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11843 {
11844   SI tmp_oldregval;
11845   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
11846   {
11847     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
11848     SET_H_GR (FLD (f_operand2), opval);
11849     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11850   }
11851 }
11852 {
11853   {
11854     BI opval = LTQI (tmp_tmpd, 0);
11855     CPU (h_nbit) = opval;
11856     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11857   }
11858   {
11859     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11860     CPU (h_zbit) = opval;
11861     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11862   }
11863 SET_H_CBIT_MOVE (0);
11864 SET_H_VBIT_MOVE (0);
11865 {
11866   {
11867     BI opval = 0;
11868     CPU (h_xbit) = opval;
11869     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11870   }
11871   {
11872     BI opval = 0;
11873     SET_H_INSN_PREFIXED_P (opval);
11874     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11875   }
11876 }
11877 }
11878 }
11879
11880 #undef FLD
11881 }
11882   NEXT (vpc);
11883
11884   CASE (sem, INSN_LSLR_W_R) : /* lslr.w $Rs,$Rd */
11885 {
11886   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11887   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11888 #define FLD(f) abuf->fields.sfmt_addc_m.f
11889   int UNUSED written = 0;
11890   IADDR UNUSED pc = abuf->addr;
11891   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11892
11893 {
11894   SI tmp_tmpd;
11895   SI tmp_cnt;
11896   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11897   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11898 {
11899   SI tmp_oldregval;
11900   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
11901   {
11902     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
11903     SET_H_GR (FLD (f_operand2), opval);
11904     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11905   }
11906 }
11907 {
11908   {
11909     BI opval = LTHI (tmp_tmpd, 0);
11910     CPU (h_nbit) = opval;
11911     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11912   }
11913   {
11914     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11915     CPU (h_zbit) = opval;
11916     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11917   }
11918 SET_H_CBIT_MOVE (0);
11919 SET_H_VBIT_MOVE (0);
11920 {
11921   {
11922     BI opval = 0;
11923     CPU (h_xbit) = opval;
11924     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11925   }
11926   {
11927     BI opval = 0;
11928     SET_H_INSN_PREFIXED_P (opval);
11929     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11930   }
11931 }
11932 }
11933 }
11934
11935 #undef FLD
11936 }
11937   NEXT (vpc);
11938
11939   CASE (sem, INSN_LSLR_D_R) : /* lslr.d $Rs,$Rd */
11940 {
11941   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11942   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11943 #define FLD(f) abuf->fields.sfmt_addc_m.f
11944   int UNUSED written = 0;
11945   IADDR UNUSED pc = abuf->addr;
11946   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11947
11948 {
11949   SI tmp_tmpd;
11950   SI tmp_cnt;
11951   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11952   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11953   {
11954     SI opval = tmp_tmpd;
11955     SET_H_GR (FLD (f_operand2), opval);
11956     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11957   }
11958 {
11959   {
11960     BI opval = LTSI (tmp_tmpd, 0);
11961     CPU (h_nbit) = opval;
11962     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11963   }
11964   {
11965     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11966     CPU (h_zbit) = opval;
11967     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11968   }
11969 SET_H_CBIT_MOVE (0);
11970 SET_H_VBIT_MOVE (0);
11971 {
11972   {
11973     BI opval = 0;
11974     CPU (h_xbit) = opval;
11975     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11976   }
11977   {
11978     BI opval = 0;
11979     SET_H_INSN_PREFIXED_P (opval);
11980     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11981   }
11982 }
11983 }
11984 }
11985
11986 #undef FLD
11987 }
11988   NEXT (vpc);
11989
11990   CASE (sem, INSN_LSLQ) : /* lslq $c,${Rd} */
11991 {
11992   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11993   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11994 #define FLD(f) abuf->fields.sfmt_asrq.f
11995   int UNUSED written = 0;
11996   IADDR UNUSED pc = abuf->addr;
11997   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11998
11999 {
12000   SI tmp_tmpd;
12001   tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
12002   {
12003     SI opval = tmp_tmpd;
12004     SET_H_GR (FLD (f_operand2), opval);
12005     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12006   }
12007 {
12008   {
12009     BI opval = LTSI (tmp_tmpd, 0);
12010     CPU (h_nbit) = opval;
12011     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12012   }
12013   {
12014     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12015     CPU (h_zbit) = opval;
12016     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12017   }
12018 SET_H_CBIT_MOVE (0);
12019 SET_H_VBIT_MOVE (0);
12020 {
12021   {
12022     BI opval = 0;
12023     CPU (h_xbit) = opval;
12024     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12025   }
12026   {
12027     BI opval = 0;
12028     SET_H_INSN_PREFIXED_P (opval);
12029     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12030   }
12031 }
12032 }
12033 }
12034
12035 #undef FLD
12036 }
12037   NEXT (vpc);
12038
12039   CASE (sem, INSN_BTST) : /* $Rs,$Rd */
12040 {
12041   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12042   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12043 #define FLD(f) abuf->fields.sfmt_muls_b.f
12044   int UNUSED written = 0;
12045   IADDR UNUSED pc = abuf->addr;
12046   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12047
12048 {
12049   SI tmp_tmpd;
12050   SI tmp_cnt;
12051   tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), SUBSI (31, ANDSI (GET_H_GR (FLD (f_operand1)), 31)));
12052 {
12053   {
12054     BI opval = LTSI (tmp_tmpd, 0);
12055     CPU (h_nbit) = opval;
12056     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12057   }
12058   {
12059     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12060     CPU (h_zbit) = opval;
12061     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12062   }
12063 SET_H_CBIT_MOVE (0);
12064 SET_H_VBIT_MOVE (0);
12065 {
12066   {
12067     BI opval = 0;
12068     CPU (h_xbit) = opval;
12069     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12070   }
12071   {
12072     BI opval = 0;
12073     SET_H_INSN_PREFIXED_P (opval);
12074     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12075   }
12076 }
12077 }
12078 }
12079
12080 #undef FLD
12081 }
12082   NEXT (vpc);
12083
12084   CASE (sem, INSN_BTSTQ) : /* btstq $c,${Rd} */
12085 {
12086   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12087   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12088 #define FLD(f) abuf->fields.sfmt_asrq.f
12089   int UNUSED written = 0;
12090   IADDR UNUSED pc = abuf->addr;
12091   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12092
12093 {
12094   SI tmp_tmpd;
12095   tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), SUBSI (31, FLD (f_u5)));
12096 {
12097   {
12098     BI opval = LTSI (tmp_tmpd, 0);
12099     CPU (h_nbit) = opval;
12100     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12101   }
12102   {
12103     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12104     CPU (h_zbit) = opval;
12105     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12106   }
12107 SET_H_CBIT_MOVE (0);
12108 SET_H_VBIT_MOVE (0);
12109 {
12110   {
12111     BI opval = 0;
12112     CPU (h_xbit) = opval;
12113     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12114   }
12115   {
12116     BI opval = 0;
12117     SET_H_INSN_PREFIXED_P (opval);
12118     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12119   }
12120 }
12121 }
12122 }
12123
12124 #undef FLD
12125 }
12126   NEXT (vpc);
12127
12128   CASE (sem, INSN_SETF) : /* setf ${list-of-flags} */
12129 {
12130   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12131   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12132 #define FLD(f) abuf->fields.sfmt_setf.f
12133   int UNUSED written = 0;
12134   IADDR UNUSED pc = abuf->addr;
12135   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12136
12137 {
12138   SI tmp_tmp;
12139   tmp_tmp = FLD (f_dstsrc);
12140 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 0)), 0)) {
12141   {
12142     BI opval = 1;
12143     CPU (h_cbit) = opval;
12144     written |= (1 << 1);
12145     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
12146   }
12147 }
12148 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 1)), 0)) {
12149   {
12150     BI opval = 1;
12151     CPU (h_vbit) = opval;
12152     written |= (1 << 7);
12153     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
12154   }
12155 }
12156 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 2)), 0)) {
12157   {
12158     BI opval = 1;
12159     CPU (h_zbit) = opval;
12160     written |= (1 << 9);
12161     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12162   }
12163 }
12164 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 3)), 0)) {
12165   {
12166     BI opval = 1;
12167     CPU (h_nbit) = opval;
12168     written |= (1 << 3);
12169     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12170   }
12171 }
12172 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
12173   {
12174     BI opval = 1;
12175     CPU (h_xbit) = opval;
12176     written |= (1 << 8);
12177     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12178   }
12179 }
12180 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 5)), 0)) {
12181   {
12182     BI opval = 1;
12183     SET_H_IBIT (opval);
12184     written |= (1 << 2);
12185     TRACE_RESULT (current_cpu, abuf, "ibit", 'x', opval);
12186   }
12187 }
12188 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 6)), 0)) {
12189   {
12190     BI opval = 1;
12191     SET_H_UBIT (opval);
12192     written |= (1 << 6);
12193     TRACE_RESULT (current_cpu, abuf, "ubit", 'x', opval);
12194   }
12195 }
12196 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 7)), 0)) {
12197   {
12198     BI opval = 1;
12199     CPU (h_pbit) = opval;
12200     written |= (1 << 4);
12201     TRACE_RESULT (current_cpu, abuf, "pbit", 'x', opval);
12202   }
12203 }
12204   {
12205     BI opval = 0;
12206     SET_H_INSN_PREFIXED_P (opval);
12207     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12208   }
12209 if (EQSI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
12210   {
12211     BI opval = 0;
12212     CPU (h_xbit) = opval;
12213     written |= (1 << 8);
12214     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12215   }
12216 }
12217 }
12218
12219   abuf->written = written;
12220 #undef FLD
12221 }
12222   NEXT (vpc);
12223
12224   CASE (sem, INSN_CLEARF) : /* clearf ${list-of-flags} */
12225 {
12226   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12227   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12228 #define FLD(f) abuf->fields.sfmt_setf.f
12229   int UNUSED written = 0;
12230   IADDR UNUSED pc = abuf->addr;
12231   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12232
12233 {
12234   SI tmp_tmp;
12235   tmp_tmp = FLD (f_dstsrc);
12236 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 0)), 0)) {
12237   {
12238     BI opval = 0;
12239     CPU (h_cbit) = opval;
12240     written |= (1 << 1);
12241     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
12242   }
12243 }
12244 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 1)), 0)) {
12245   {
12246     BI opval = 0;
12247     CPU (h_vbit) = opval;
12248     written |= (1 << 7);
12249     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
12250   }
12251 }
12252 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 2)), 0)) {
12253   {
12254     BI opval = 0;
12255     CPU (h_zbit) = opval;
12256     written |= (1 << 9);
12257     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12258   }
12259 }
12260 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 3)), 0)) {
12261   {
12262     BI opval = 0;
12263     CPU (h_nbit) = opval;
12264     written |= (1 << 3);
12265     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12266   }
12267 }
12268 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
12269   {
12270     BI opval = 0;
12271     CPU (h_xbit) = opval;
12272     written |= (1 << 8);
12273     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12274   }
12275 }
12276 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 5)), 0)) {
12277   {
12278     BI opval = 0;
12279     SET_H_IBIT (opval);
12280     written |= (1 << 2);
12281     TRACE_RESULT (current_cpu, abuf, "ibit", 'x', opval);
12282   }
12283 }
12284 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 6)), 0)) {
12285   {
12286     BI opval = 0;
12287     SET_H_UBIT (opval);
12288     written |= (1 << 6);
12289     TRACE_RESULT (current_cpu, abuf, "ubit", 'x', opval);
12290   }
12291 }
12292 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 7)), 0)) {
12293   {
12294     BI opval = 0;
12295     CPU (h_pbit) = opval;
12296     written |= (1 << 4);
12297     TRACE_RESULT (current_cpu, abuf, "pbit", 'x', opval);
12298   }
12299 }
12300 {
12301   {
12302     BI opval = 0;
12303     CPU (h_xbit) = opval;
12304     written |= (1 << 8);
12305     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12306   }
12307   {
12308     BI opval = 0;
12309     SET_H_INSN_PREFIXED_P (opval);
12310     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12311   }
12312 }
12313 }
12314
12315   abuf->written = written;
12316 #undef FLD
12317 }
12318   NEXT (vpc);
12319
12320   CASE (sem, INSN_RFE) : /* rfe */
12321 {
12322   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12323   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12324 #define FLD(f) abuf->fields.sfmt_rfe.f
12325   int UNUSED written = 0;
12326   IADDR UNUSED pc = abuf->addr;
12327   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12328
12329 {
12330   USI tmp_oldccs;
12331   USI tmp_samebits;
12332   USI tmp_shiftbits;
12333   USI tmp_keepmask;
12334   BI tmp_p1;
12335   tmp_oldccs = GET_H_SR (((UINT) 13));
12336   tmp_keepmask = 0xc0000000;
12337   tmp_samebits = ANDSI (tmp_oldccs, tmp_keepmask);
12338   tmp_shiftbits = ANDSI (SRLSI (ANDSI (tmp_oldccs, 1073609728), 10), INVSI (tmp_keepmask));
12339   tmp_p1 = NESI (0, ANDSI (tmp_oldccs, 131072));
12340   {
12341     SI opval = ORSI (ORSI (tmp_samebits, tmp_shiftbits), ((ANDBI (CPU (h_rbit), NOTBI (tmp_p1))) ? (0) : (128)));
12342     SET_H_SR (((UINT) 13), opval);
12343     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12344   }
12345 }
12346
12347 #undef FLD
12348 }
12349   NEXT (vpc);
12350
12351   CASE (sem, INSN_SFE) : /* sfe */
12352 {
12353   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12354   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12355 #define FLD(f) abuf->fields.sfmt_rfe.f
12356   int UNUSED written = 0;
12357   IADDR UNUSED pc = abuf->addr;
12358   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12359
12360 {
12361   SI tmp_oldccs;
12362   SI tmp_savemask;
12363   tmp_savemask = 0xc0000000;
12364   tmp_oldccs = GET_H_SR (((UINT) 13));
12365   {
12366     SI opval = ORSI (ANDSI (tmp_savemask, tmp_oldccs), ANDSI (INVSI (tmp_savemask), SLLSI (tmp_oldccs, 10)));
12367     SET_H_SR (((UINT) 13), opval);
12368     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12369   }
12370 }
12371
12372 #undef FLD
12373 }
12374   NEXT (vpc);
12375
12376   CASE (sem, INSN_RFG) : /* rfg */
12377 {
12378   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12379   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12380 #define FLD(f) abuf->fields.fmt_empty.f
12381   int UNUSED written = 0;
12382   IADDR UNUSED pc = abuf->addr;
12383   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12384
12385 crisv32f_rfg_handler (current_cpu, pc);
12386
12387 #undef FLD
12388 }
12389   NEXT (vpc);
12390
12391   CASE (sem, INSN_RFN) : /* rfn */
12392 {
12393   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12394   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12395 #define FLD(f) abuf->fields.sfmt_rfe.f
12396   int UNUSED written = 0;
12397   IADDR UNUSED pc = abuf->addr;
12398   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12399
12400 {
12401 {
12402   USI tmp_oldccs;
12403   USI tmp_samebits;
12404   USI tmp_shiftbits;
12405   USI tmp_keepmask;
12406   BI tmp_p1;
12407   tmp_oldccs = GET_H_SR (((UINT) 13));
12408   tmp_keepmask = 0xc0000000;
12409   tmp_samebits = ANDSI (tmp_oldccs, tmp_keepmask);
12410   tmp_shiftbits = ANDSI (SRLSI (ANDSI (tmp_oldccs, 1073609728), 10), INVSI (tmp_keepmask));
12411   tmp_p1 = NESI (0, ANDSI (tmp_oldccs, 131072));
12412   {
12413     SI opval = ORSI (ORSI (tmp_samebits, tmp_shiftbits), ((ANDBI (CPU (h_rbit), NOTBI (tmp_p1))) ? (0) : (128)));
12414     SET_H_SR (((UINT) 13), opval);
12415     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12416   }
12417 }
12418   {
12419     BI opval = 1;
12420     SET_H_MBIT (opval);
12421     TRACE_RESULT (current_cpu, abuf, "mbit", 'x', opval);
12422   }
12423 }
12424
12425 #undef FLD
12426 }
12427   NEXT (vpc);
12428
12429   CASE (sem, INSN_HALT) : /* halt */
12430 {
12431   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12432   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12433 #define FLD(f) abuf->fields.fmt_empty.f
12434   int UNUSED written = 0;
12435   IADDR UNUSED pc = abuf->addr;
12436   SEM_BRANCH_INIT
12437   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12438
12439   {
12440     USI opval = crisv32f_halt_handler (current_cpu, pc);
12441     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
12442     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12443   }
12444
12445   SEM_BRANCH_FINI (vpc);
12446 #undef FLD
12447 }
12448   NEXT (vpc);
12449
12450   CASE (sem, INSN_BCC_B) : /* b${cc} ${o-pcrel} */
12451 {
12452   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12453   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12454 #define FLD(f) abuf->fields.sfmt_bcc_b.f
12455   int UNUSED written = 0;
12456   IADDR UNUSED pc = abuf->addr;
12457   SEM_BRANCH_INIT
12458   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12459
12460 {
12461   BI tmp_truthval;
12462   tmp_truthval = ({   SI tmp_tmpcond;
12463   BI tmp_condres;
12464   tmp_tmpcond = FLD (f_operand2);
12465 ; if (EQSI (tmp_tmpcond, 0)) {
12466   tmp_condres = NOTBI (CPU (h_cbit));
12467 }
12468  else if (EQSI (tmp_tmpcond, 1)) {
12469   tmp_condres = CPU (h_cbit);
12470 }
12471  else if (EQSI (tmp_tmpcond, 2)) {
12472   tmp_condres = NOTBI (CPU (h_zbit));
12473 }
12474  else if (EQSI (tmp_tmpcond, 3)) {
12475   tmp_condres = CPU (h_zbit);
12476 }
12477  else if (EQSI (tmp_tmpcond, 4)) {
12478   tmp_condres = NOTBI (CPU (h_vbit));
12479 }
12480  else if (EQSI (tmp_tmpcond, 5)) {
12481   tmp_condres = CPU (h_vbit);
12482 }
12483  else if (EQSI (tmp_tmpcond, 6)) {
12484   tmp_condres = NOTBI (CPU (h_nbit));
12485 }
12486  else if (EQSI (tmp_tmpcond, 7)) {
12487   tmp_condres = CPU (h_nbit);
12488 }
12489  else if (EQSI (tmp_tmpcond, 8)) {
12490   tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
12491 }
12492  else if (EQSI (tmp_tmpcond, 9)) {
12493   tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
12494 }
12495  else if (EQSI (tmp_tmpcond, 10)) {
12496   tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
12497 }
12498  else if (EQSI (tmp_tmpcond, 11)) {
12499   tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
12500 }
12501  else if (EQSI (tmp_tmpcond, 12)) {
12502   tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
12503 }
12504  else if (EQSI (tmp_tmpcond, 13)) {
12505   tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
12506 }
12507  else if (EQSI (tmp_tmpcond, 14)) {
12508   tmp_condres = 1;
12509 }
12510  else if (EQSI (tmp_tmpcond, 15)) {
12511   tmp_condres = CPU (h_pbit);
12512 }
12513 ; tmp_condres; });
12514 crisv32f_branch_taken (current_cpu, pc, FLD (i_o_pcrel), tmp_truthval);
12515 {
12516   {
12517     BI opval = 0;
12518     CPU (h_xbit) = opval;
12519     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12520   }
12521   {
12522     BI opval = 0;
12523     SET_H_INSN_PREFIXED_P (opval);
12524     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12525   }
12526 }
12527 if (tmp_truthval) {
12528 {
12529   {
12530     USI opval = FLD (i_o_pcrel);
12531     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12532     written |= (1 << 8);
12533     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12534   }
12535 }
12536 }
12537 }
12538
12539   abuf->written = written;
12540   SEM_BRANCH_FINI (vpc);
12541 #undef FLD
12542 }
12543   NEXT (vpc);
12544
12545   CASE (sem, INSN_BA_B) : /* ba ${o-pcrel} */
12546 {
12547   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12548   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12549 #define FLD(f) abuf->fields.sfmt_bcc_b.f
12550   int UNUSED written = 0;
12551   IADDR UNUSED pc = abuf->addr;
12552   SEM_BRANCH_INIT
12553   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12554
12555 {
12556 {
12557   {
12558     BI opval = 0;
12559     CPU (h_xbit) = opval;
12560     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12561   }
12562   {
12563     BI opval = 0;
12564     SET_H_INSN_PREFIXED_P (opval);
12565     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12566   }
12567 }
12568 {
12569   {
12570     USI opval = FLD (i_o_pcrel);
12571     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12572     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12573   }
12574 }
12575 }
12576
12577   SEM_BRANCH_FINI (vpc);
12578 #undef FLD
12579 }
12580   NEXT (vpc);
12581
12582   CASE (sem, INSN_BCC_W) : /* b${cc} ${o-word-pcrel} */
12583 {
12584   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12585   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12586 #define FLD(f) abuf->fields.sfmt_bcc_w.f
12587   int UNUSED written = 0;
12588   IADDR UNUSED pc = abuf->addr;
12589   SEM_BRANCH_INIT
12590   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
12591
12592 {
12593   BI tmp_truthval;
12594   tmp_truthval = ({   SI tmp_tmpcond;
12595   BI tmp_condres;
12596   tmp_tmpcond = FLD (f_operand2);
12597 ; if (EQSI (tmp_tmpcond, 0)) {
12598   tmp_condres = NOTBI (CPU (h_cbit));
12599 }
12600  else if (EQSI (tmp_tmpcond, 1)) {
12601   tmp_condres = CPU (h_cbit);
12602 }
12603  else if (EQSI (tmp_tmpcond, 2)) {
12604   tmp_condres = NOTBI (CPU (h_zbit));
12605 }
12606  else if (EQSI (tmp_tmpcond, 3)) {
12607   tmp_condres = CPU (h_zbit);
12608 }
12609  else if (EQSI (tmp_tmpcond, 4)) {
12610   tmp_condres = NOTBI (CPU (h_vbit));
12611 }
12612  else if (EQSI (tmp_tmpcond, 5)) {
12613   tmp_condres = CPU (h_vbit);
12614 }
12615  else if (EQSI (tmp_tmpcond, 6)) {
12616   tmp_condres = NOTBI (CPU (h_nbit));
12617 }
12618  else if (EQSI (tmp_tmpcond, 7)) {
12619   tmp_condres = CPU (h_nbit);
12620 }
12621  else if (EQSI (tmp_tmpcond, 8)) {
12622   tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
12623 }
12624  else if (EQSI (tmp_tmpcond, 9)) {
12625   tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
12626 }
12627  else if (EQSI (tmp_tmpcond, 10)) {
12628   tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
12629 }
12630  else if (EQSI (tmp_tmpcond, 11)) {
12631   tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
12632 }
12633  else if (EQSI (tmp_tmpcond, 12)) {
12634   tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
12635 }
12636  else if (EQSI (tmp_tmpcond, 13)) {
12637   tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
12638 }
12639  else if (EQSI (tmp_tmpcond, 14)) {
12640   tmp_condres = 1;
12641 }
12642  else if (EQSI (tmp_tmpcond, 15)) {
12643   tmp_condres = CPU (h_pbit);
12644 }
12645 ; tmp_condres; });
12646 crisv32f_branch_taken (current_cpu, pc, FLD (i_o_word_pcrel), tmp_truthval);
12647 {
12648   {
12649     BI opval = 0;
12650     CPU (h_xbit) = opval;
12651     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12652   }
12653   {
12654     BI opval = 0;
12655     SET_H_INSN_PREFIXED_P (opval);
12656     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12657   }
12658 }
12659 if (tmp_truthval) {
12660 {
12661   {
12662     USI opval = FLD (i_o_word_pcrel);
12663     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12664     written |= (1 << 8);
12665     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12666   }
12667 }
12668 }
12669 }
12670
12671   abuf->written = written;
12672   SEM_BRANCH_FINI (vpc);
12673 #undef FLD
12674 }
12675   NEXT (vpc);
12676
12677   CASE (sem, INSN_BA_W) : /* ba ${o-word-pcrel} */
12678 {
12679   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12680   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12681 #define FLD(f) abuf->fields.sfmt_bcc_w.f
12682   int UNUSED written = 0;
12683   IADDR UNUSED pc = abuf->addr;
12684   SEM_BRANCH_INIT
12685   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
12686
12687 {
12688 {
12689   {
12690     BI opval = 0;
12691     CPU (h_xbit) = opval;
12692     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12693   }
12694   {
12695     BI opval = 0;
12696     SET_H_INSN_PREFIXED_P (opval);
12697     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12698   }
12699 }
12700 {
12701   {
12702     USI opval = FLD (i_o_word_pcrel);
12703     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12704     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12705   }
12706 }
12707 }
12708
12709   SEM_BRANCH_FINI (vpc);
12710 #undef FLD
12711 }
12712   NEXT (vpc);
12713
12714   CASE (sem, INSN_JAS_R) : /* jas ${Rs},${Pd} */
12715 {
12716   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12717   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12718 #define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
12719   int UNUSED written = 0;
12720   IADDR UNUSED pc = abuf->addr;
12721   SEM_BRANCH_INIT
12722   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12723
12724 {
12725 {
12726   {
12727     BI opval = 0;
12728     CPU (h_xbit) = opval;
12729     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12730   }
12731   {
12732     BI opval = 0;
12733     SET_H_INSN_PREFIXED_P (opval);
12734     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12735   }
12736 }
12737 if (ANDIF (EQSI (FLD (f_operand1), 1), EQSI (FLD (f_operand2), 11))) {
12738 cris_flush_simulator_decode_cache (current_cpu, pc);
12739 }
12740 {
12741 {
12742   {
12743     SI opval = ADDSI (pc, 4);
12744     SET_H_SR (FLD (f_operand2), opval);
12745     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12746   }
12747   {
12748     USI opval = GET_H_GR (FLD (f_operand1));
12749     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
12750     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12751   }
12752 }
12753 }
12754 }
12755
12756   SEM_BRANCH_FINI (vpc);
12757 #undef FLD
12758 }
12759   NEXT (vpc);
12760
12761   CASE (sem, INSN_JAS_C) : /* jas ${const32},${Pd} */
12762 {
12763   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12764   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12765 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
12766   int UNUSED written = 0;
12767   IADDR UNUSED pc = abuf->addr;
12768   SEM_BRANCH_INIT
12769   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
12770
12771 {
12772 {
12773   {
12774     BI opval = 0;
12775     CPU (h_xbit) = opval;
12776     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12777   }
12778   {
12779     BI opval = 0;
12780     SET_H_INSN_PREFIXED_P (opval);
12781     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12782   }
12783 }
12784 {
12785 {
12786   {
12787     SI opval = ADDSI (pc, 8);
12788     SET_H_SR (FLD (f_operand2), opval);
12789     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12790   }
12791   {
12792     USI opval = FLD (f_indir_pc__dword);
12793     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12794     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12795   }
12796 }
12797 }
12798 }
12799
12800   SEM_BRANCH_FINI (vpc);
12801 #undef FLD
12802 }
12803   NEXT (vpc);
12804
12805   CASE (sem, INSN_JUMP_P) : /* jump ${Ps} */
12806 {
12807   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12808   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12809 #define FLD(f) abuf->fields.sfmt_mcp.f
12810   int UNUSED written = 0;
12811   IADDR UNUSED pc = abuf->addr;
12812   SEM_BRANCH_INIT
12813   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12814
12815 {
12816 {
12817   {
12818     BI opval = 0;
12819     CPU (h_xbit) = opval;
12820     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12821   }
12822   {
12823     BI opval = 0;
12824     SET_H_INSN_PREFIXED_P (opval);
12825     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12826   }
12827 }
12828 {
12829   {
12830     USI opval = GET_H_SR (FLD (f_operand2));
12831     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
12832     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12833   }
12834 }
12835 }
12836
12837   SEM_BRANCH_FINI (vpc);
12838 #undef FLD
12839 }
12840   NEXT (vpc);
12841
12842   CASE (sem, INSN_BAS_C) : /* bas ${const32},${Pd} */
12843 {
12844   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12845   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12846 #define FLD(f) abuf->fields.sfmt_bas_c.f
12847   int UNUSED written = 0;
12848   IADDR UNUSED pc = abuf->addr;
12849   SEM_BRANCH_INIT
12850   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
12851
12852 {
12853 {
12854   {
12855     BI opval = 0;
12856     CPU (h_xbit) = opval;
12857     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12858   }
12859   {
12860     BI opval = 0;
12861     SET_H_INSN_PREFIXED_P (opval);
12862     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12863   }
12864 }
12865 {
12866 {
12867   {
12868     SI opval = ADDSI (pc, 8);
12869     SET_H_SR (FLD (f_operand2), opval);
12870     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12871   }
12872   {
12873     USI opval = FLD (i_const32_pcrel);
12874     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
12875     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12876   }
12877 }
12878 }
12879 }
12880
12881   SEM_BRANCH_FINI (vpc);
12882 #undef FLD
12883 }
12884   NEXT (vpc);
12885
12886   CASE (sem, INSN_JASC_R) : /* jasc ${Rs},${Pd} */
12887 {
12888   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12889   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12890 #define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
12891   int UNUSED written = 0;
12892   IADDR UNUSED pc = abuf->addr;
12893   SEM_BRANCH_INIT
12894   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12895
12896 {
12897 {
12898   {
12899     BI opval = 0;
12900     CPU (h_xbit) = opval;
12901     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12902   }
12903   {
12904     BI opval = 0;
12905     SET_H_INSN_PREFIXED_P (opval);
12906     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12907   }
12908 }
12909 {
12910 {
12911   {
12912     SI opval = ADDSI (pc, 8);
12913     SET_H_SR (FLD (f_operand2), opval);
12914     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12915   }
12916   {
12917     USI opval = GET_H_GR (FLD (f_operand1));
12918     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
12919     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12920   }
12921 }
12922 }
12923 }
12924
12925   SEM_BRANCH_FINI (vpc);
12926 #undef FLD
12927 }
12928   NEXT (vpc);
12929
12930   CASE (sem, INSN_JASC_C) : /* jasc ${const32},${Pd} */
12931 {
12932   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12933   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12934 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
12935   int UNUSED written = 0;
12936   IADDR UNUSED pc = abuf->addr;
12937   SEM_BRANCH_INIT
12938   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
12939
12940 {
12941 {
12942   {
12943     BI opval = 0;
12944     CPU (h_xbit) = opval;
12945     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12946   }
12947   {
12948     BI opval = 0;
12949     SET_H_INSN_PREFIXED_P (opval);
12950     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12951   }
12952 }
12953 {
12954 {
12955   {
12956     SI opval = ADDSI (pc, 12);
12957     SET_H_SR (FLD (f_operand2), opval);
12958     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12959   }
12960   {
12961     USI opval = FLD (f_indir_pc__dword);
12962     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12963     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12964   }
12965 }
12966 }
12967 }
12968
12969   SEM_BRANCH_FINI (vpc);
12970 #undef FLD
12971 }
12972   NEXT (vpc);
12973
12974   CASE (sem, INSN_BASC_C) : /* basc ${const32},${Pd} */
12975 {
12976   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12977   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12978 #define FLD(f) abuf->fields.sfmt_bas_c.f
12979   int UNUSED written = 0;
12980   IADDR UNUSED pc = abuf->addr;
12981   SEM_BRANCH_INIT
12982   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
12983
12984 {
12985 {
12986   {
12987     BI opval = 0;
12988     CPU (h_xbit) = opval;
12989     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12990   }
12991   {
12992     BI opval = 0;
12993     SET_H_INSN_PREFIXED_P (opval);
12994     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12995   }
12996 }
12997 {
12998 {
12999   {
13000     SI opval = ADDSI (pc, 12);
13001     SET_H_SR (FLD (f_operand2), opval);
13002     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
13003   }
13004   {
13005     USI opval = FLD (i_const32_pcrel);
13006     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
13007     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
13008   }
13009 }
13010 }
13011 }
13012
13013   SEM_BRANCH_FINI (vpc);
13014 #undef FLD
13015 }
13016   NEXT (vpc);
13017
13018   CASE (sem, INSN_BREAK) : /* break $n */
13019 {
13020   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13021   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13022 #define FLD(f) abuf->fields.sfmt_break.f
13023   int UNUSED written = 0;
13024   IADDR UNUSED pc = abuf->addr;
13025   SEM_BRANCH_INIT
13026   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13027
13028 {
13029 {
13030   {
13031     BI opval = 0;
13032     CPU (h_xbit) = opval;
13033     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13034   }
13035   {
13036     BI opval = 0;
13037     SET_H_INSN_PREFIXED_P (opval);
13038     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13039   }
13040 }
13041   {
13042     USI opval = crisv32f_break_handler (current_cpu, FLD (f_u4), pc);
13043     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
13044     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
13045   }
13046 }
13047
13048   SEM_BRANCH_FINI (vpc);
13049 #undef FLD
13050 }
13051   NEXT (vpc);
13052
13053   CASE (sem, INSN_BOUND_R_B_R) : /* bound-r.b ${Rs},${Rd} */
13054 {
13055   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13056   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13057 #define FLD(f) abuf->fields.sfmt_muls_b.f
13058   int UNUSED written = 0;
13059   IADDR UNUSED pc = abuf->addr;
13060   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13061
13062 {
13063   SI tmp_tmpopd;
13064   SI tmp_tmpops;
13065   SI tmp_newval;
13066   tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
13067   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13068   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13069   {
13070     SI opval = tmp_newval;
13071     SET_H_GR (FLD (f_operand2), opval);
13072     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13073   }
13074 {
13075   {
13076     BI opval = LTSI (tmp_newval, 0);
13077     CPU (h_nbit) = opval;
13078     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13079   }
13080   {
13081     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13082     CPU (h_zbit) = opval;
13083     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13084   }
13085 SET_H_CBIT_MOVE (0);
13086 SET_H_VBIT_MOVE (0);
13087 {
13088   {
13089     BI opval = 0;
13090     CPU (h_xbit) = opval;
13091     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13092   }
13093   {
13094     BI opval = 0;
13095     SET_H_INSN_PREFIXED_P (opval);
13096     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13097   }
13098 }
13099 }
13100 }
13101
13102 #undef FLD
13103 }
13104   NEXT (vpc);
13105
13106   CASE (sem, INSN_BOUND_R_W_R) : /* bound-r.w ${Rs},${Rd} */
13107 {
13108   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13109   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13110 #define FLD(f) abuf->fields.sfmt_muls_b.f
13111   int UNUSED written = 0;
13112   IADDR UNUSED pc = abuf->addr;
13113   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13114
13115 {
13116   SI tmp_tmpopd;
13117   SI tmp_tmpops;
13118   SI tmp_newval;
13119   tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
13120   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13121   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13122   {
13123     SI opval = tmp_newval;
13124     SET_H_GR (FLD (f_operand2), opval);
13125     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13126   }
13127 {
13128   {
13129     BI opval = LTSI (tmp_newval, 0);
13130     CPU (h_nbit) = opval;
13131     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13132   }
13133   {
13134     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13135     CPU (h_zbit) = opval;
13136     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13137   }
13138 SET_H_CBIT_MOVE (0);
13139 SET_H_VBIT_MOVE (0);
13140 {
13141   {
13142     BI opval = 0;
13143     CPU (h_xbit) = opval;
13144     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13145   }
13146   {
13147     BI opval = 0;
13148     SET_H_INSN_PREFIXED_P (opval);
13149     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13150   }
13151 }
13152 }
13153 }
13154
13155 #undef FLD
13156 }
13157   NEXT (vpc);
13158
13159   CASE (sem, INSN_BOUND_R_D_R) : /* bound-r.d ${Rs},${Rd} */
13160 {
13161   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13162   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13163 #define FLD(f) abuf->fields.sfmt_muls_b.f
13164   int UNUSED written = 0;
13165   IADDR UNUSED pc = abuf->addr;
13166   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13167
13168 {
13169   SI tmp_tmpopd;
13170   SI tmp_tmpops;
13171   SI tmp_newval;
13172   tmp_tmpops = TRUNCSISI (GET_H_GR (FLD (f_operand1)));
13173   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13174   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13175   {
13176     SI opval = tmp_newval;
13177     SET_H_GR (FLD (f_operand2), opval);
13178     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13179   }
13180 {
13181   {
13182     BI opval = LTSI (tmp_newval, 0);
13183     CPU (h_nbit) = opval;
13184     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13185   }
13186   {
13187     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13188     CPU (h_zbit) = opval;
13189     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13190   }
13191 SET_H_CBIT_MOVE (0);
13192 SET_H_VBIT_MOVE (0);
13193 {
13194   {
13195     BI opval = 0;
13196     CPU (h_xbit) = opval;
13197     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13198   }
13199   {
13200     BI opval = 0;
13201     SET_H_INSN_PREFIXED_P (opval);
13202     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13203   }
13204 }
13205 }
13206 }
13207
13208 #undef FLD
13209 }
13210   NEXT (vpc);
13211
13212   CASE (sem, INSN_BOUND_CB) : /* bound.b [PC+],${Rd} */
13213 {
13214   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13215   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13216 #define FLD(f) abuf->fields.sfmt_bound_cb.f
13217   int UNUSED written = 0;
13218   IADDR UNUSED pc = abuf->addr;
13219   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
13220
13221 {
13222   SI tmp_tmpopd;
13223   SI tmp_tmpops;
13224   SI tmp_newval;
13225   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
13226   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13227   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13228   {
13229     SI opval = tmp_newval;
13230     SET_H_GR (FLD (f_operand2), opval);
13231     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13232   }
13233 {
13234   {
13235     BI opval = LTSI (tmp_newval, 0);
13236     CPU (h_nbit) = opval;
13237     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13238   }
13239   {
13240     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13241     CPU (h_zbit) = opval;
13242     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13243   }
13244 SET_H_CBIT_MOVE (0);
13245 SET_H_VBIT_MOVE (0);
13246 {
13247   {
13248     BI opval = 0;
13249     CPU (h_xbit) = opval;
13250     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13251   }
13252   {
13253     BI opval = 0;
13254     SET_H_INSN_PREFIXED_P (opval);
13255     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13256   }
13257 }
13258 }
13259 }
13260
13261 #undef FLD
13262 }
13263   NEXT (vpc);
13264
13265   CASE (sem, INSN_BOUND_CW) : /* bound.w [PC+],${Rd} */
13266 {
13267   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13268   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13269 #define FLD(f) abuf->fields.sfmt_bound_cw.f
13270   int UNUSED written = 0;
13271   IADDR UNUSED pc = abuf->addr;
13272   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
13273
13274 {
13275   SI tmp_tmpopd;
13276   SI tmp_tmpops;
13277   SI tmp_newval;
13278   tmp_tmpops = ZEXTSISI (FLD (f_indir_pc__word));
13279   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13280   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13281   {
13282     SI opval = tmp_newval;
13283     SET_H_GR (FLD (f_operand2), opval);
13284     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13285   }
13286 {
13287   {
13288     BI opval = LTSI (tmp_newval, 0);
13289     CPU (h_nbit) = opval;
13290     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13291   }
13292   {
13293     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13294     CPU (h_zbit) = opval;
13295     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13296   }
13297 SET_H_CBIT_MOVE (0);
13298 SET_H_VBIT_MOVE (0);
13299 {
13300   {
13301     BI opval = 0;
13302     CPU (h_xbit) = opval;
13303     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13304   }
13305   {
13306     BI opval = 0;
13307     SET_H_INSN_PREFIXED_P (opval);
13308     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13309   }
13310 }
13311 }
13312 }
13313
13314 #undef FLD
13315 }
13316   NEXT (vpc);
13317
13318   CASE (sem, INSN_BOUND_CD) : /* bound.d [PC+],${Rd} */
13319 {
13320   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13321   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13322 #define FLD(f) abuf->fields.sfmt_bound_cd.f
13323   int UNUSED written = 0;
13324   IADDR UNUSED pc = abuf->addr;
13325   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
13326
13327 {
13328   SI tmp_tmpopd;
13329   SI tmp_tmpops;
13330   SI tmp_newval;
13331   tmp_tmpops = FLD (f_indir_pc__dword);
13332   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13333   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13334   {
13335     SI opval = tmp_newval;
13336     SET_H_GR (FLD (f_operand2), opval);
13337     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13338   }
13339 {
13340   {
13341     BI opval = LTSI (tmp_newval, 0);
13342     CPU (h_nbit) = opval;
13343     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13344   }
13345   {
13346     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13347     CPU (h_zbit) = opval;
13348     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13349   }
13350 SET_H_CBIT_MOVE (0);
13351 SET_H_VBIT_MOVE (0);
13352 {
13353   {
13354     BI opval = 0;
13355     CPU (h_xbit) = opval;
13356     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13357   }
13358   {
13359     BI opval = 0;
13360     SET_H_INSN_PREFIXED_P (opval);
13361     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13362   }
13363 }
13364 }
13365 }
13366
13367 #undef FLD
13368 }
13369   NEXT (vpc);
13370
13371   CASE (sem, INSN_SCC) : /* s${cc} ${Rd-sfield} */
13372 {
13373   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13374   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13375 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
13376   int UNUSED written = 0;
13377   IADDR UNUSED pc = abuf->addr;
13378   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13379
13380 {
13381   BI tmp_truthval;
13382   tmp_truthval = ({   SI tmp_tmpcond;
13383   BI tmp_condres;
13384   tmp_tmpcond = FLD (f_operand2);
13385 ; if (EQSI (tmp_tmpcond, 0)) {
13386   tmp_condres = NOTBI (CPU (h_cbit));
13387 }
13388  else if (EQSI (tmp_tmpcond, 1)) {
13389   tmp_condres = CPU (h_cbit);
13390 }
13391  else if (EQSI (tmp_tmpcond, 2)) {
13392   tmp_condres = NOTBI (CPU (h_zbit));
13393 }
13394  else if (EQSI (tmp_tmpcond, 3)) {
13395   tmp_condres = CPU (h_zbit);
13396 }
13397  else if (EQSI (tmp_tmpcond, 4)) {
13398   tmp_condres = NOTBI (CPU (h_vbit));
13399 }
13400  else if (EQSI (tmp_tmpcond, 5)) {
13401   tmp_condres = CPU (h_vbit);
13402 }
13403  else if (EQSI (tmp_tmpcond, 6)) {
13404   tmp_condres = NOTBI (CPU (h_nbit));
13405 }
13406  else if (EQSI (tmp_tmpcond, 7)) {
13407   tmp_condres = CPU (h_nbit);
13408 }
13409  else if (EQSI (tmp_tmpcond, 8)) {
13410   tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
13411 }
13412  else if (EQSI (tmp_tmpcond, 9)) {
13413   tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
13414 }
13415  else if (EQSI (tmp_tmpcond, 10)) {
13416   tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
13417 }
13418  else if (EQSI (tmp_tmpcond, 11)) {
13419   tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
13420 }
13421  else if (EQSI (tmp_tmpcond, 12)) {
13422   tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
13423 }
13424  else if (EQSI (tmp_tmpcond, 13)) {
13425   tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
13426 }
13427  else if (EQSI (tmp_tmpcond, 14)) {
13428   tmp_condres = 1;
13429 }
13430  else if (EQSI (tmp_tmpcond, 15)) {
13431   tmp_condres = CPU (h_pbit);
13432 }
13433 ; tmp_condres; });
13434   {
13435     SI opval = ZEXTBISI (tmp_truthval);
13436     SET_H_GR (FLD (f_operand1), opval);
13437     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13438   }
13439 {
13440   {
13441     BI opval = 0;
13442     CPU (h_xbit) = opval;
13443     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13444   }
13445   {
13446     BI opval = 0;
13447     SET_H_INSN_PREFIXED_P (opval);
13448     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13449   }
13450 }
13451 }
13452
13453 #undef FLD
13454 }
13455   NEXT (vpc);
13456
13457   CASE (sem, INSN_LZ) : /* lz ${Rs},${Rd} */
13458 {
13459   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13460   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13461 #define FLD(f) abuf->fields.sfmt_muls_b.f
13462   int UNUSED written = 0;
13463   IADDR UNUSED pc = abuf->addr;
13464   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13465
13466 {
13467   SI tmp_tmpd;
13468   SI tmp_tmp;
13469   tmp_tmp = GET_H_GR (FLD (f_operand1));
13470   tmp_tmpd = 0;
13471 {
13472 if (GESI (tmp_tmp, 0)) {
13473 {
13474   tmp_tmp = SLLSI (tmp_tmp, 1);
13475   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13476 }
13477 }
13478 if (GESI (tmp_tmp, 0)) {
13479 {
13480   tmp_tmp = SLLSI (tmp_tmp, 1);
13481   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13482 }
13483 }
13484 if (GESI (tmp_tmp, 0)) {
13485 {
13486   tmp_tmp = SLLSI (tmp_tmp, 1);
13487   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13488 }
13489 }
13490 if (GESI (tmp_tmp, 0)) {
13491 {
13492   tmp_tmp = SLLSI (tmp_tmp, 1);
13493   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13494 }
13495 }
13496 if (GESI (tmp_tmp, 0)) {
13497 {
13498   tmp_tmp = SLLSI (tmp_tmp, 1);
13499   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13500 }
13501 }
13502 if (GESI (tmp_tmp, 0)) {
13503 {
13504   tmp_tmp = SLLSI (tmp_tmp, 1);
13505   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13506 }
13507 }
13508 if (GESI (tmp_tmp, 0)) {
13509 {
13510   tmp_tmp = SLLSI (tmp_tmp, 1);
13511   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13512 }
13513 }
13514 if (GESI (tmp_tmp, 0)) {
13515 {
13516   tmp_tmp = SLLSI (tmp_tmp, 1);
13517   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13518 }
13519 }
13520 if (GESI (tmp_tmp, 0)) {
13521 {
13522   tmp_tmp = SLLSI (tmp_tmp, 1);
13523   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13524 }
13525 }
13526 if (GESI (tmp_tmp, 0)) {
13527 {
13528   tmp_tmp = SLLSI (tmp_tmp, 1);
13529   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13530 }
13531 }
13532 if (GESI (tmp_tmp, 0)) {
13533 {
13534   tmp_tmp = SLLSI (tmp_tmp, 1);
13535   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13536 }
13537 }
13538 if (GESI (tmp_tmp, 0)) {
13539 {
13540   tmp_tmp = SLLSI (tmp_tmp, 1);
13541   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13542 }
13543 }
13544 if (GESI (tmp_tmp, 0)) {
13545 {
13546   tmp_tmp = SLLSI (tmp_tmp, 1);
13547   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13548 }
13549 }
13550 if (GESI (tmp_tmp, 0)) {
13551 {
13552   tmp_tmp = SLLSI (tmp_tmp, 1);
13553   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13554 }
13555 }
13556 if (GESI (tmp_tmp, 0)) {
13557 {
13558   tmp_tmp = SLLSI (tmp_tmp, 1);
13559   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13560 }
13561 }
13562 if (GESI (tmp_tmp, 0)) {
13563 {
13564   tmp_tmp = SLLSI (tmp_tmp, 1);
13565   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13566 }
13567 }
13568 if (GESI (tmp_tmp, 0)) {
13569 {
13570   tmp_tmp = SLLSI (tmp_tmp, 1);
13571   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13572 }
13573 }
13574 if (GESI (tmp_tmp, 0)) {
13575 {
13576   tmp_tmp = SLLSI (tmp_tmp, 1);
13577   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13578 }
13579 }
13580 if (GESI (tmp_tmp, 0)) {
13581 {
13582   tmp_tmp = SLLSI (tmp_tmp, 1);
13583   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13584 }
13585 }
13586 if (GESI (tmp_tmp, 0)) {
13587 {
13588   tmp_tmp = SLLSI (tmp_tmp, 1);
13589   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13590 }
13591 }
13592 if (GESI (tmp_tmp, 0)) {
13593 {
13594   tmp_tmp = SLLSI (tmp_tmp, 1);
13595   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13596 }
13597 }
13598 if (GESI (tmp_tmp, 0)) {
13599 {
13600   tmp_tmp = SLLSI (tmp_tmp, 1);
13601   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13602 }
13603 }
13604 if (GESI (tmp_tmp, 0)) {
13605 {
13606   tmp_tmp = SLLSI (tmp_tmp, 1);
13607   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13608 }
13609 }
13610 if (GESI (tmp_tmp, 0)) {
13611 {
13612   tmp_tmp = SLLSI (tmp_tmp, 1);
13613   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13614 }
13615 }
13616 if (GESI (tmp_tmp, 0)) {
13617 {
13618   tmp_tmp = SLLSI (tmp_tmp, 1);
13619   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13620 }
13621 }
13622 if (GESI (tmp_tmp, 0)) {
13623 {
13624   tmp_tmp = SLLSI (tmp_tmp, 1);
13625   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13626 }
13627 }
13628 if (GESI (tmp_tmp, 0)) {
13629 {
13630   tmp_tmp = SLLSI (tmp_tmp, 1);
13631   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13632 }
13633 }
13634 if (GESI (tmp_tmp, 0)) {
13635 {
13636   tmp_tmp = SLLSI (tmp_tmp, 1);
13637   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13638 }
13639 }
13640 if (GESI (tmp_tmp, 0)) {
13641 {
13642   tmp_tmp = SLLSI (tmp_tmp, 1);
13643   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13644 }
13645 }
13646 if (GESI (tmp_tmp, 0)) {
13647 {
13648   tmp_tmp = SLLSI (tmp_tmp, 1);
13649   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13650 }
13651 }
13652 if (GESI (tmp_tmp, 0)) {
13653 {
13654   tmp_tmp = SLLSI (tmp_tmp, 1);
13655   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13656 }
13657 }
13658 if (GESI (tmp_tmp, 0)) {
13659 {
13660   tmp_tmp = SLLSI (tmp_tmp, 1);
13661   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13662 }
13663 }
13664 }
13665   {
13666     SI opval = tmp_tmpd;
13667     SET_H_GR (FLD (f_operand2), opval);
13668     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13669   }
13670 {
13671   {
13672     BI opval = LTSI (tmp_tmpd, 0);
13673     CPU (h_nbit) = opval;
13674     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13675   }
13676   {
13677     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13678     CPU (h_zbit) = opval;
13679     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13680   }
13681 SET_H_CBIT_MOVE (0);
13682 SET_H_VBIT_MOVE (0);
13683 {
13684   {
13685     BI opval = 0;
13686     CPU (h_xbit) = opval;
13687     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13688   }
13689   {
13690     BI opval = 0;
13691     SET_H_INSN_PREFIXED_P (opval);
13692     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13693   }
13694 }
13695 }
13696 }
13697
13698 #undef FLD
13699 }
13700   NEXT (vpc);
13701
13702   CASE (sem, INSN_ADDOQ) : /* addoq $o,$Rs,ACR */
13703 {
13704   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13705   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13706 #define FLD(f) abuf->fields.sfmt_addoq.f
13707   int UNUSED written = 0;
13708   IADDR UNUSED pc = abuf->addr;
13709   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13710
13711 {
13712   {
13713     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), FLD (f_s8));
13714     SET_H_PREFIXREG_V32 (opval);
13715     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13716   }
13717   {
13718     BI opval = 1;
13719     SET_H_INSN_PREFIXED_P (opval);
13720     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13721   }
13722 }
13723
13724 #undef FLD
13725 }
13726   NEXT (vpc);
13727
13728   CASE (sem, INSN_ADDO_M_B_M) : /* addo-m.b [${Rs}${inc}],$Rd,ACR */
13729 {
13730   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13731   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13732 #define FLD(f) abuf->fields.sfmt_addc_m.f
13733   int UNUSED written = 0;
13734   IADDR UNUSED pc = abuf->addr;
13735   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13736
13737 {
13738   QI tmp_tmps;
13739   tmp_tmps = ({   SI tmp_addr;
13740   QI tmp_tmp_mem;
13741   BI tmp_postinc;
13742   tmp_postinc = FLD (f_memmode);
13743 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
13744 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
13745 ; if (NEBI (tmp_postinc, 0)) {
13746 {
13747 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13748   tmp_addr = ADDSI (tmp_addr, 1);
13749 }
13750   {
13751     SI opval = tmp_addr;
13752     SET_H_GR (FLD (f_operand1), opval);
13753     written |= (1 << 6);
13754     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13755   }
13756 }
13757 }
13758 ; tmp_tmp_mem; });
13759   {
13760     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTQISI (tmp_tmps));
13761     SET_H_PREFIXREG_V32 (opval);
13762     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13763   }
13764   {
13765     BI opval = 1;
13766     SET_H_INSN_PREFIXED_P (opval);
13767     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13768   }
13769 }
13770
13771   abuf->written = written;
13772 #undef FLD
13773 }
13774   NEXT (vpc);
13775
13776   CASE (sem, INSN_ADDO_M_W_M) : /* addo-m.w [${Rs}${inc}],$Rd,ACR */
13777 {
13778   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13779   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13780 #define FLD(f) abuf->fields.sfmt_addc_m.f
13781   int UNUSED written = 0;
13782   IADDR UNUSED pc = abuf->addr;
13783   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13784
13785 {
13786   HI tmp_tmps;
13787   tmp_tmps = ({   SI tmp_addr;
13788   HI tmp_tmp_mem;
13789   BI tmp_postinc;
13790   tmp_postinc = FLD (f_memmode);
13791 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
13792 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
13793 ; if (NEBI (tmp_postinc, 0)) {
13794 {
13795 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13796   tmp_addr = ADDSI (tmp_addr, 2);
13797 }
13798   {
13799     SI opval = tmp_addr;
13800     SET_H_GR (FLD (f_operand1), opval);
13801     written |= (1 << 6);
13802     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13803   }
13804 }
13805 }
13806 ; tmp_tmp_mem; });
13807   {
13808     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTHISI (tmp_tmps));
13809     SET_H_PREFIXREG_V32 (opval);
13810     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13811   }
13812   {
13813     BI opval = 1;
13814     SET_H_INSN_PREFIXED_P (opval);
13815     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13816   }
13817 }
13818
13819   abuf->written = written;
13820 #undef FLD
13821 }
13822   NEXT (vpc);
13823
13824   CASE (sem, INSN_ADDO_M_D_M) : /* addo-m.d [${Rs}${inc}],$Rd,ACR */
13825 {
13826   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13827   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13828 #define FLD(f) abuf->fields.sfmt_addc_m.f
13829   int UNUSED written = 0;
13830   IADDR UNUSED pc = abuf->addr;
13831   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13832
13833 {
13834   SI tmp_tmps;
13835   tmp_tmps = ({   SI tmp_addr;
13836   SI tmp_tmp_mem;
13837   BI tmp_postinc;
13838   tmp_postinc = FLD (f_memmode);
13839 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
13840 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
13841 ; if (NEBI (tmp_postinc, 0)) {
13842 {
13843 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13844   tmp_addr = ADDSI (tmp_addr, 4);
13845 }
13846   {
13847     SI opval = tmp_addr;
13848     SET_H_GR (FLD (f_operand1), opval);
13849     written |= (1 << 6);
13850     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13851   }
13852 }
13853 }
13854 ; tmp_tmp_mem; });
13855   {
13856     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), tmp_tmps);
13857     SET_H_PREFIXREG_V32 (opval);
13858     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13859   }
13860   {
13861     BI opval = 1;
13862     SET_H_INSN_PREFIXED_P (opval);
13863     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13864   }
13865 }
13866
13867   abuf->written = written;
13868 #undef FLD
13869 }
13870   NEXT (vpc);
13871
13872   CASE (sem, INSN_ADDO_CB) : /* addo.b [PC+],$Rd,ACR */
13873 {
13874   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13875   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13876 #define FLD(f) abuf->fields.sfmt_bound_cb.f
13877   int UNUSED written = 0;
13878   IADDR UNUSED pc = abuf->addr;
13879   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
13880
13881 {
13882   {
13883     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte))));
13884     SET_H_PREFIXREG_V32 (opval);
13885     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13886   }
13887   {
13888     BI opval = 1;
13889     SET_H_INSN_PREFIXED_P (opval);
13890     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13891   }
13892 }
13893
13894 #undef FLD
13895 }
13896   NEXT (vpc);
13897
13898   CASE (sem, INSN_ADDO_CW) : /* addo.w [PC+],$Rd,ACR */
13899 {
13900   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13901   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13902 #define FLD(f) abuf->fields.sfmt_bound_cw.f
13903   int UNUSED written = 0;
13904   IADDR UNUSED pc = abuf->addr;
13905   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
13906
13907 {
13908   {
13909     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word))));
13910     SET_H_PREFIXREG_V32 (opval);
13911     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13912   }
13913   {
13914     BI opval = 1;
13915     SET_H_INSN_PREFIXED_P (opval);
13916     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13917   }
13918 }
13919
13920 #undef FLD
13921 }
13922   NEXT (vpc);
13923
13924   CASE (sem, INSN_ADDO_CD) : /* addo.d [PC+],$Rd,ACR */
13925 {
13926   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13927   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13928 #define FLD(f) abuf->fields.sfmt_bound_cd.f
13929   int UNUSED written = 0;
13930   IADDR UNUSED pc = abuf->addr;
13931   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
13932
13933 {
13934   {
13935     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
13936     SET_H_PREFIXREG_V32 (opval);
13937     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13938   }
13939   {
13940     BI opval = 1;
13941     SET_H_INSN_PREFIXED_P (opval);
13942     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13943   }
13944 }
13945
13946 #undef FLD
13947 }
13948   NEXT (vpc);
13949
13950   CASE (sem, INSN_ADDI_ACR_B_R) : /* addi-acr.b ${Rs-dfield}.m,${Rd-sfield},ACR */
13951 {
13952   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13953   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13954 #define FLD(f) abuf->fields.sfmt_muls_b.f
13955   int UNUSED written = 0;
13956   IADDR UNUSED pc = abuf->addr;
13957   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13958
13959 {
13960   {
13961     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 1));
13962     SET_H_PREFIXREG_V32 (opval);
13963     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13964   }
13965   {
13966     BI opval = 1;
13967     SET_H_INSN_PREFIXED_P (opval);
13968     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13969   }
13970 }
13971
13972 #undef FLD
13973 }
13974   NEXT (vpc);
13975
13976   CASE (sem, INSN_ADDI_ACR_W_R) : /* addi-acr.w ${Rs-dfield}.m,${Rd-sfield},ACR */
13977 {
13978   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13979   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13980 #define FLD(f) abuf->fields.sfmt_muls_b.f
13981   int UNUSED written = 0;
13982   IADDR UNUSED pc = abuf->addr;
13983   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13984
13985 {
13986   {
13987     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 2));
13988     SET_H_PREFIXREG_V32 (opval);
13989     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13990   }
13991   {
13992     BI opval = 1;
13993     SET_H_INSN_PREFIXED_P (opval);
13994     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13995   }
13996 }
13997
13998 #undef FLD
13999 }
14000   NEXT (vpc);
14001
14002   CASE (sem, INSN_ADDI_ACR_D_R) : /* addi-acr.d ${Rs-dfield}.m,${Rd-sfield},ACR */
14003 {
14004   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14005   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14006 #define FLD(f) abuf->fields.sfmt_muls_b.f
14007   int UNUSED written = 0;
14008   IADDR UNUSED pc = abuf->addr;
14009   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14010
14011 {
14012   {
14013     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 4));
14014     SET_H_PREFIXREG_V32 (opval);
14015     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
14016   }
14017   {
14018     BI opval = 1;
14019     SET_H_INSN_PREFIXED_P (opval);
14020     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
14021   }
14022 }
14023
14024 #undef FLD
14025 }
14026   NEXT (vpc);
14027
14028   CASE (sem, INSN_FIDXI) : /* fidxi [$Rs] */
14029 {
14030   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14031   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14032 #define FLD(f) abuf->fields.sfmt_mcp.f
14033   int UNUSED written = 0;
14034   IADDR UNUSED pc = abuf->addr;
14035   SEM_BRANCH_INIT
14036   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14037
14038   {
14039     USI opval = crisv32f_fidxi_handler (current_cpu, pc, GET_H_GR (FLD (f_operand1)));
14040     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
14041     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
14042   }
14043
14044   SEM_BRANCH_FINI (vpc);
14045 #undef FLD
14046 }
14047   NEXT (vpc);
14048
14049   CASE (sem, INSN_FTAGI) : /* fidxi [$Rs] */
14050 {
14051   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14052   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14053 #define FLD(f) abuf->fields.sfmt_mcp.f
14054   int UNUSED written = 0;
14055   IADDR UNUSED pc = abuf->addr;
14056   SEM_BRANCH_INIT
14057   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14058
14059   {
14060     USI opval = crisv32f_ftagi_handler (current_cpu, pc, GET_H_GR (FLD (f_operand1)));
14061     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
14062     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
14063   }
14064
14065   SEM_BRANCH_FINI (vpc);
14066 #undef FLD
14067 }
14068   NEXT (vpc);
14069
14070   CASE (sem, INSN_FIDXD) : /* fidxd [$Rs] */
14071 {
14072   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14073   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14074 #define FLD(f) abuf->fields.sfmt_mcp.f
14075   int UNUSED written = 0;
14076   IADDR UNUSED pc = abuf->addr;
14077   SEM_BRANCH_INIT
14078   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14079
14080   {
14081     USI opval = crisv32f_fidxd_handler (current_cpu, pc, GET_H_GR (FLD (f_operand1)));
14082     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
14083     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
14084   }
14085
14086   SEM_BRANCH_FINI (vpc);
14087 #undef FLD
14088 }
14089   NEXT (vpc);
14090
14091   CASE (sem, INSN_FTAGD) : /* ftagd [$Rs] */
14092 {
14093   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14094   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14095 #define FLD(f) abuf->fields.sfmt_mcp.f
14096   int UNUSED written = 0;
14097   IADDR UNUSED pc = abuf->addr;
14098   SEM_BRANCH_INIT
14099   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14100
14101   {
14102     USI opval = crisv32f_ftagd_handler (current_cpu, pc, GET_H_GR (FLD (f_operand1)));
14103     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
14104     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
14105   }
14106
14107   SEM_BRANCH_FINI (vpc);
14108 #undef FLD
14109 }
14110   NEXT (vpc);
14111
14112
14113     }
14114   ENDSWITCH (sem) /* End of semantic switch.  */
14115
14116   /* At this point `vpc' contains the next insn to execute.  */
14117 }
14118
14119 #undef DEFINE_SWITCH
14120 #endif /* DEFINE_SWITCH */