Add LMA_P and DO_WRITE arguments to sim/common/sim-load.c:sim_load_file().
[deliverable/binutils-gdb.git] / sim / d10v / interp.c
1 #include <signal.h>
2 #include "sysdep.h"
3 #include "bfd.h"
4 #include "callback.h"
5 #include "remote-sim.h"
6
7 #include "d10v_sim.h"
8
9 #define IMEM_SIZE 18 /* D10V instruction memory size is 18 bits */
10 #define DMEM_SIZE 16 /* Data memory is 64K (but only 32K internal RAM) */
11 #define UMEM_SIZE 17 /* each unified memory region is 17 bits */
12
13 enum _leftright { LEFT_FIRST, RIGHT_FIRST };
14
15 static char *myname;
16 static SIM_OPEN_KIND sim_kind;
17 int d10v_debug;
18 host_callback *d10v_callback;
19 unsigned long ins_type_counters[ (int)INS_MAX ];
20
21 uint16 OP[4];
22
23 static int init_text_p = 0;
24 /* non-zero if we opened prog_bfd */
25 static int prog_bfd_was_opened_p;
26 bfd *prog_bfd;
27 asection *text;
28 bfd_vma text_start;
29 bfd_vma text_end;
30
31 static long hash PARAMS ((long insn, int format));
32 static struct hash_entry *lookup_hash PARAMS ((uint32 ins, int size));
33 static void get_operands PARAMS ((struct simops *s, uint32 ins));
34 static void do_long PARAMS ((uint32 ins));
35 static void do_2_short PARAMS ((uint16 ins1, uint16 ins2, enum _leftright leftright));
36 static void do_parallel PARAMS ((uint16 ins1, uint16 ins2));
37 static char *add_commas PARAMS ((char *buf, int sizeof_buf, unsigned long value));
38 static void init_system PARAMS ((void));
39 extern void sim_set_profile PARAMS ((int n));
40 extern void sim_set_profile_size PARAMS ((int n));
41
42 #ifndef INLINE
43 #if defined(__GNUC__) && defined(__OPTIMIZE__)
44 #define INLINE __inline__
45 #else
46 #define INLINE
47 #endif
48 #endif
49
50 #define MAX_HASH 63
51 struct hash_entry
52 {
53 struct hash_entry *next;
54 long opcode;
55 long mask;
56 int size;
57 struct simops *ops;
58 };
59
60 struct hash_entry hash_table[MAX_HASH+1];
61
62 INLINE static long
63 hash(insn, format)
64 long insn;
65 int format;
66 {
67 if (format & LONG_OPCODE)
68 return ((insn & 0x3F000000) >> 24);
69 else
70 return((insn & 0x7E00) >> 9);
71 }
72
73 INLINE static struct hash_entry *
74 lookup_hash (ins, size)
75 uint32 ins;
76 int size;
77 {
78 struct hash_entry *h;
79
80 if (size)
81 h = &hash_table[(ins & 0x3F000000) >> 24];
82 else
83 h = &hash_table[(ins & 0x7E00) >> 9];
84
85 while ((ins & h->mask) != h->opcode || h->size != size)
86 {
87 if (h->next == NULL)
88 {
89 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR looking up hash for %x at PC %x\n",ins, PC);
90 exit (1);
91 }
92 h = h->next;
93 }
94 return (h);
95 }
96
97 INLINE static void
98 get_operands (struct simops *s, uint32 ins)
99 {
100 int i, shift, bits, flags;
101 uint32 mask;
102 for (i=0; i < s->numops; i++)
103 {
104 shift = s->operands[3*i];
105 bits = s->operands[3*i+1];
106 flags = s->operands[3*i+2];
107 mask = 0x7FFFFFFF >> (31 - bits);
108 OP[i] = (ins >> shift) & mask;
109 }
110 }
111
112 bfd_vma
113 decode_pc ()
114 {
115 asection *s;
116 if (!init_text_p)
117 {
118 init_text_p = 1;
119 for (s = prog_bfd->sections; s; s = s->next)
120 if (strcmp (bfd_get_section_name (prog_bfd, s), ".text") == 0)
121 {
122 text = s;
123 text_start = bfd_get_section_vma (prog_bfd, s);
124 text_end = text_start + bfd_section_size (prog_bfd, s);
125 break;
126 }
127 }
128
129 return (PC << 2) + text_start;
130 }
131
132 static void
133 do_long (ins)
134 uint32 ins;
135 {
136 struct hash_entry *h;
137 #ifdef DEBUG
138 if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
139 (*d10v_callback->printf_filtered) (d10v_callback, "do_long 0x%x\n", ins);
140 #endif
141 h = lookup_hash (ins, 1);
142 get_operands (h->ops, ins);
143 State.ins_type = INS_LONG;
144 ins_type_counters[ (int)State.ins_type ]++;
145 (h->ops->func)();
146 }
147
148 static void
149 do_2_short (ins1, ins2, leftright)
150 uint16 ins1, ins2;
151 enum _leftright leftright;
152 {
153 struct hash_entry *h;
154 reg_t orig_pc = PC;
155 enum _ins_type first, second;
156
157 #ifdef DEBUG
158 if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
159 (*d10v_callback->printf_filtered) (d10v_callback, "do_2_short 0x%x (%s) -> 0x%x\n",
160 ins1, (leftright) ? "left" : "right", ins2);
161 #endif
162
163 if (leftright == LEFT_FIRST)
164 {
165 first = INS_LEFT;
166 second = INS_RIGHT;
167 ins_type_counters[ (int)INS_LEFTRIGHT ]++;
168 }
169 else
170 {
171 first = INS_RIGHT;
172 second = INS_LEFT;
173 ins_type_counters[ (int)INS_RIGHTLEFT ]++;
174 }
175
176 h = lookup_hash (ins1, 0);
177 get_operands (h->ops, ins1);
178 State.ins_type = first;
179 ins_type_counters[ (int)State.ins_type ]++;
180 (h->ops->func)();
181
182 /* If the PC has changed (ie, a jump), don't do the second instruction */
183 if (orig_pc == PC && !State.exception)
184 {
185 h = lookup_hash (ins2, 0);
186 get_operands (h->ops, ins2);
187 State.ins_type = second;
188 ins_type_counters[ (int)State.ins_type ]++;
189 ins_type_counters[ (int)INS_CYCLES ]++;
190 (h->ops->func)();
191 }
192 else if (orig_pc != PC && !State.exception)
193 ins_type_counters[ (int)INS_COND_JUMP ]++;
194 }
195
196 static void
197 do_parallel (ins1, ins2)
198 uint16 ins1, ins2;
199 {
200 struct hash_entry *h1, *h2;
201 #ifdef DEBUG
202 if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
203 (*d10v_callback->printf_filtered) (d10v_callback, "do_parallel 0x%x || 0x%x\n", ins1, ins2);
204 #endif
205 ins_type_counters[ (int)INS_PARALLEL ]++;
206 h1 = lookup_hash (ins1, 0);
207 h2 = lookup_hash (ins2, 0);
208
209 if (h1->ops->exec_type == PARONLY)
210 {
211 get_operands (h1->ops, ins1);
212 State.ins_type = INS_LEFT_COND_TEST;
213 ins_type_counters[ (int)State.ins_type ]++;
214 (h1->ops->func)();
215 if (State.exe)
216 {
217 ins_type_counters[ (int)INS_COND_TRUE ]++;
218 get_operands (h2->ops, ins2);
219 State.ins_type = INS_RIGHT_COND_EXE;
220 ins_type_counters[ (int)State.ins_type ]++;
221 (h2->ops->func)();
222 }
223 else
224 ins_type_counters[ (int)INS_COND_FALSE ]++;
225 }
226 else if (h2->ops->exec_type == PARONLY)
227 {
228 get_operands (h2->ops, ins2);
229 State.ins_type = INS_RIGHT_COND_TEST;
230 ins_type_counters[ (int)State.ins_type ]++;
231 (h2->ops->func)();
232 if (State.exe)
233 {
234 ins_type_counters[ (int)INS_COND_TRUE ]++;
235 get_operands (h1->ops, ins1);
236 State.ins_type = INS_LEFT_COND_EXE;
237 ins_type_counters[ (int)State.ins_type ]++;
238 (h1->ops->func)();
239 }
240 else
241 ins_type_counters[ (int)INS_COND_FALSE ]++;
242 }
243 else
244 {
245 get_operands (h1->ops, ins1);
246 State.ins_type = INS_LEFT_PARALLEL;
247 ins_type_counters[ (int)State.ins_type ]++;
248 (h1->ops->func)();
249 if (!State.exception)
250 {
251 get_operands (h2->ops, ins2);
252 State.ins_type = INS_RIGHT_PARALLEL;
253 ins_type_counters[ (int)State.ins_type ]++;
254 (h2->ops->func)();
255 }
256 }
257 }
258
259 static char *
260 add_commas(buf, sizeof_buf, value)
261 char *buf;
262 int sizeof_buf;
263 unsigned long value;
264 {
265 int comma = 3;
266 char *endbuf = buf + sizeof_buf - 1;
267
268 *--endbuf = '\0';
269 do {
270 if (comma-- == 0)
271 {
272 *--endbuf = ',';
273 comma = 2;
274 }
275
276 *--endbuf = (value % 10) + '0';
277 } while ((value /= 10) != 0);
278
279 return endbuf;
280 }
281
282 void
283 sim_size (power)
284 int power;
285
286 {
287 int i;
288
289 if (State.imem)
290 {
291 for (i=0;i<128;i++)
292 {
293 if (State.umem[i])
294 {
295 free (State.umem[i]);
296 State.umem[i] = NULL;
297 }
298 }
299 free (State.imem);
300 free (State.dmem);
301 }
302
303 State.imem = (uint8 *)calloc(1,1<<IMEM_SIZE);
304 State.dmem = (uint8 *)calloc(1,1<<DMEM_SIZE);
305 for (i=1;i<127;i++)
306 State.umem[i] = NULL;
307 State.umem[0] = (uint8 *)calloc(1,1<<UMEM_SIZE);
308 State.umem[1] = (uint8 *)calloc(1,1<<UMEM_SIZE);
309 State.umem[2] = (uint8 *)calloc(1,1<<UMEM_SIZE);
310 State.umem[127] = (uint8 *)calloc(1,1<<UMEM_SIZE);
311 if (!State.imem || !State.dmem || !State.umem[0] || !State.umem[1] || !State.umem[2] || !State.umem[127] )
312 {
313 (*d10v_callback->printf_filtered) (d10v_callback, "Memory allocation failed.\n");
314 exit(1);
315 }
316
317 SET_IMAP0(0x1000);
318 SET_IMAP1(0x1000);
319 SET_DMAP(0);
320
321 #ifdef DEBUG
322 if ((d10v_debug & DEBUG_MEMSIZE) != 0)
323 {
324 char buffer[20];
325 (*d10v_callback->printf_filtered) (d10v_callback,
326 "Allocated %s bytes instruction memory and\n",
327 add_commas (buffer, sizeof (buffer), (1UL<<IMEM_SIZE)));
328
329 (*d10v_callback->printf_filtered) (d10v_callback, " %s bytes data memory.\n",
330 add_commas (buffer, sizeof (buffer), (1UL<<IMEM_SIZE)));
331 }
332 #endif
333 }
334
335 static void
336 init_system ()
337 {
338 if (!State.imem)
339 sim_size(1);
340 }
341
342 static int
343 xfer_mem (addr, buffer, size, write)
344 SIM_ADDR addr;
345 unsigned char *buffer;
346 int size;
347 int write;
348 {
349 if (!State.imem)
350 init_system ();
351
352 #ifdef DEBUG
353 if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
354 {
355 if (write)
356 (*d10v_callback->printf_filtered) (d10v_callback, "sim_write %d bytes to 0x%x\n", size, addr);
357 else
358 (*d10v_callback->printf_filtered) (d10v_callback, "sim_read %d bytes from 0x%x\n", size, addr);
359 }
360 #endif
361
362 /* to access data, we use the following mapping */
363 /* 0x01000000 - 0x0103ffff : instruction memory */
364 /* 0x02000000 - 0x0200ffff : data memory */
365 /* 0x00000000 - 0x00ffffff : unified memory */
366
367 if ( (addr & 0x03000000) == 0)
368 {
369 /* UNIFIED MEMORY */
370 int segment;
371 segment = addr >> UMEM_SIZE;
372 addr &= 0x1ffff;
373 if (!State.umem[segment])
374 {
375 #ifdef DEBUG
376 (*d10v_callback->printf_filtered) (d10v_callback,"Allocating %s bytes unified memory to region %d\n",
377 add_commas (buffer, sizeof (buffer), (1UL<<IMEM_SIZE)), segment);
378 #endif
379 State.umem[segment] = (uint8 *)calloc(1,1<<UMEM_SIZE);
380 }
381 if (!State.umem[segment])
382 {
383 (*d10v_callback->printf_filtered) (d10v_callback, "Memory allocation failed.\n");
384 exit(1);
385 }
386 /* FIXME: need to check size and read/write multiple segments if necessary */
387 if (write)
388 memcpy (State.umem[segment]+addr, buffer, size) ;
389 else
390 memcpy (buffer, State.umem[segment]+addr, size);
391 }
392 else if ( (addr & 0x03000000) == 0x02000000)
393 {
394 /* DATA MEMORY */
395 addr &= ~0x02000000;
396 if (size > (1<<(DMEM_SIZE-1)))
397 {
398 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: data section is only %d bytes.\n",1<<(DMEM_SIZE-1));
399 exit(1);
400 }
401 if (write)
402 memcpy (State.dmem+addr, buffer, size);
403 else
404 memcpy (buffer, State.dmem+addr, size);
405 }
406 else if ( (addr & 0x03000000) == 0x01000000)
407 {
408 /* INSTRUCTION MEMORY */
409 addr &= ~0x01000000;
410 if (size > (1<<IMEM_SIZE))
411 {
412 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: inst section is only %d bytes.\n",1<<IMEM_SIZE);
413 exit(1);
414 }
415 if (write)
416 memcpy (State.imem+addr, buffer, size);
417 else
418 memcpy (buffer, State.imem+addr, size);
419 }
420 else if (write)
421 {
422 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: address 0x%x is not in valid range\n",addr);
423 (*d10v_callback->printf_filtered) (d10v_callback, "Instruction addresses start at 0x01000000\n");
424 (*d10v_callback->printf_filtered) (d10v_callback, "Data addresses start at 0x02000000\n");
425 (*d10v_callback->printf_filtered) (d10v_callback, "Unified addresses start at 0x00000000\n");
426 exit(1);
427 }
428 else
429 return 0;
430
431 return size;
432 }
433
434
435 static int
436 sim_write_phys (sd, addr, buffer, size)
437 SIM_DESC sd;
438 SIM_ADDR addr;
439 unsigned char *buffer;
440 int size;
441 {
442 return xfer_mem( addr, buffer, size, 1);
443 }
444
445 int
446 sim_write (sd, addr, buffer, size)
447 SIM_DESC sd;
448 SIM_ADDR addr;
449 unsigned char *buffer;
450 int size;
451 {
452 /* FIXME: this should be performing a virtual transfer */
453 return xfer_mem( addr, buffer, size, 1);
454 }
455
456 int
457 sim_read (sd, addr, buffer, size)
458 SIM_DESC sd;
459 SIM_ADDR addr;
460 unsigned char *buffer;
461 int size;
462 {
463 /* FIXME: this should be performing a virtual transfer */
464 return xfer_mem( addr, buffer, size, 0);
465 }
466
467
468 SIM_DESC
469 sim_open (kind, callback, abfd, argv)
470 SIM_OPEN_KIND kind;
471 host_callback *callback;
472 struct _bfd *abfd;
473 char **argv;
474 {
475 struct simops *s;
476 struct hash_entry *h;
477 static int init_p = 0;
478 char **p;
479
480 sim_kind = kind;
481 d10v_callback = callback;
482 myname = argv[0];
483
484 for (p = argv + 1; *p; ++p)
485 {
486 #ifdef DEBUG
487 if (strcmp (*p, "-t") == 0)
488 d10v_debug = DEBUG;
489 else
490 #endif
491 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: unsupported option(s): %s\n",*p);
492 }
493
494 /* put all the opcodes in the hash table */
495 if (!init_p++)
496 {
497 for (s = Simops; s->func; s++)
498 {
499 h = &hash_table[hash(s->opcode,s->format)];
500
501 /* go to the last entry in the chain */
502 while (h->next)
503 h = h->next;
504
505 if (h->ops)
506 {
507 h->next = (struct hash_entry *) calloc(1,sizeof(struct hash_entry));
508 if (!h->next)
509 perror ("malloc failure");
510
511 h = h->next;
512 }
513 h->ops = s;
514 h->mask = s->mask;
515 h->opcode = s->opcode;
516 h->size = s->is_long;
517 }
518 }
519
520 /* Fudge our descriptor. */
521 return (SIM_DESC) 1;
522 }
523
524
525 void
526 sim_close (sd, quitting)
527 SIM_DESC sd;
528 int quitting;
529 {
530 if (prog_bfd != NULL && prog_bfd_was_opened_p)
531 bfd_close (prog_bfd);
532 }
533
534 void
535 sim_set_profile (n)
536 int n;
537 {
538 (*d10v_callback->printf_filtered) (d10v_callback, "sim_set_profile %d\n",n);
539 }
540
541 void
542 sim_set_profile_size (n)
543 int n;
544 {
545 (*d10v_callback->printf_filtered) (d10v_callback, "sim_set_profile_size %d\n",n);
546 }
547
548
549 uint8 *
550 dmem_addr( addr )
551 uint32 addr;
552 {
553 int seg;
554
555 addr &= 0xffff;
556
557 if (addr > 0xbfff)
558 {
559 if ( (addr & 0xfff0) != 0xff00)
560 {
561 (*d10v_callback->printf_filtered) (d10v_callback, "Data address 0x%lx is in I/O space, pc = 0x%lx.\n",
562 (long)addr, (long)decode_pc ());
563 State.exception = SIGBUS;
564 }
565
566 return State.dmem + addr;
567 }
568
569 if (addr > 0x7fff)
570 {
571 if (DMAP & 0x1000)
572 {
573 /* instruction memory */
574 return (DMAP & 0xf) * 0x4000 + State.imem;
575 }
576 /* unified memory */
577 /* this is ugly because we allocate unified memory in 128K segments and */
578 /* dmap addresses 16k segments */
579 seg = (DMAP & 0x3ff) >> 3;
580 if (State.umem[seg] == NULL)
581 {
582 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: unified memory region %d unmapped, pc = 0x%lx\n",
583 seg, (long)decode_pc ());
584 State.exception = SIGBUS;
585 }
586 return State.umem[seg] + (DMAP & 7) * 0x4000;
587 }
588
589 return State.dmem + addr;
590 }
591
592
593 static uint8 *
594 pc_addr()
595 {
596 uint32 pc = ((uint32)PC) << 2;
597 uint16 imap;
598
599 if (pc & 0x20000)
600 imap = IMAP1;
601 else
602 imap = IMAP0;
603
604 if (imap & 0x1000)
605 return State.imem + pc;
606
607 if (State.umem[imap & 0xff] == NULL)
608 {
609 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: unified memory region %d unmapped, pc = 0x%lx\n",
610 imap & 0xff, (long)PC);
611 State.exception = SIGBUS;
612 return 0;
613 }
614
615 /* Discard upper bit(s) of PC in case IMAP1 selects unified memory. */
616 pc &= (1 << UMEM_SIZE) - 1;
617
618 return State.umem[imap & 0xff] + pc;
619 }
620
621
622 static int stop_simulator;
623
624 static void
625 sim_ctrl_c()
626 {
627 stop_simulator = 1;
628 }
629
630
631 int
632 sim_stop (sd)
633 SIM_DESC sd;
634 {
635 stop_simulator = 1;
636 return 1;
637 }
638
639
640 /* Run (or resume) the program. */
641 void
642 sim_resume (sd, step, siggnal)
643 SIM_DESC sd;
644 int step, siggnal;
645 {
646 void (*prev) ();
647 uint32 inst;
648
649 /* (*d10v_callback->printf_filtered) (d10v_callback, "sim_resume (%d,%d) PC=0x%x\n",step,siggnal,PC); */
650 State.exception = 0;
651 prev = signal(SIGINT, sim_ctrl_c);
652 stop_simulator = step;
653
654 do
655 {
656 inst = get_longword( pc_addr() );
657 State.pc_changed = 0;
658 ins_type_counters[ (int)INS_CYCLES ]++;
659 switch (inst & 0xC0000000)
660 {
661 case 0xC0000000:
662 /* long instruction */
663 do_long (inst & 0x3FFFFFFF);
664 break;
665 case 0x80000000:
666 /* R -> L */
667 do_2_short ( inst & 0x7FFF, (inst & 0x3FFF8000) >> 15, 0);
668 break;
669 case 0x40000000:
670 /* L -> R */
671 do_2_short ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF, 1);
672 break;
673 case 0:
674 do_parallel ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF);
675 break;
676 }
677
678 if (State.RP && PC == RPT_E)
679 {
680 RPT_C -= 1;
681 if (RPT_C == 0)
682 {
683 State.RP = 0;
684 PC++;
685 }
686 else
687 PC = RPT_S;
688 }
689 else if (!State.pc_changed)
690 PC++;
691 }
692 while ( !State.exception && !stop_simulator);
693
694 if (step && !State.exception)
695 State.exception = SIGTRAP;
696
697 signal(SIGINT, prev);
698 }
699
700 int
701 sim_trace (sd)
702 SIM_DESC sd;
703 {
704 #ifdef DEBUG
705 d10v_debug = DEBUG;
706 #endif
707 sim_resume (sd, 0, 0);
708 return 1;
709 }
710
711 void
712 sim_info (sd, verbose)
713 SIM_DESC sd;
714 int verbose;
715 {
716 char buf1[40];
717 char buf2[40];
718 char buf3[40];
719 char buf4[40];
720 char buf5[40];
721 unsigned long left = ins_type_counters[ (int)INS_LEFT ] + ins_type_counters[ (int)INS_LEFT_COND_EXE ];
722 unsigned long left_nops = ins_type_counters[ (int)INS_LEFT_NOPS ];
723 unsigned long left_parallel = ins_type_counters[ (int)INS_LEFT_PARALLEL ];
724 unsigned long left_cond = ins_type_counters[ (int)INS_LEFT_COND_TEST ];
725 unsigned long left_total = left + left_parallel + left_cond + left_nops;
726
727 unsigned long right = ins_type_counters[ (int)INS_RIGHT ] + ins_type_counters[ (int)INS_RIGHT_COND_EXE ];
728 unsigned long right_nops = ins_type_counters[ (int)INS_RIGHT_NOPS ];
729 unsigned long right_parallel = ins_type_counters[ (int)INS_RIGHT_PARALLEL ];
730 unsigned long right_cond = ins_type_counters[ (int)INS_RIGHT_COND_TEST ];
731 unsigned long right_total = right + right_parallel + right_cond + right_nops;
732
733 unsigned long unknown = ins_type_counters[ (int)INS_UNKNOWN ];
734 unsigned long ins_long = ins_type_counters[ (int)INS_LONG ];
735 unsigned long parallel = ins_type_counters[ (int)INS_PARALLEL ];
736 unsigned long leftright = ins_type_counters[ (int)INS_LEFTRIGHT ];
737 unsigned long rightleft = ins_type_counters[ (int)INS_RIGHTLEFT ];
738 unsigned long cond_true = ins_type_counters[ (int)INS_COND_TRUE ];
739 unsigned long cond_false = ins_type_counters[ (int)INS_COND_FALSE ];
740 unsigned long cond_jump = ins_type_counters[ (int)INS_COND_JUMP ];
741 unsigned long cycles = ins_type_counters[ (int)INS_CYCLES ];
742 unsigned long total = (unknown + left_total + right_total + ins_long);
743
744 int size = strlen (add_commas (buf1, sizeof (buf1), total));
745 int parallel_size = strlen (add_commas (buf1, sizeof (buf1),
746 (left_parallel > right_parallel) ? left_parallel : right_parallel));
747 int cond_size = strlen (add_commas (buf1, sizeof (buf1), (left_cond > right_cond) ? left_cond : right_cond));
748 int nop_size = strlen (add_commas (buf1, sizeof (buf1), (left_nops > right_nops) ? left_nops : right_nops));
749 int normal_size = strlen (add_commas (buf1, sizeof (buf1), (left > right) ? left : right));
750
751 (*d10v_callback->printf_filtered) (d10v_callback,
752 "executed %*s left instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
753 size, add_commas (buf1, sizeof (buf1), left_total),
754 normal_size, add_commas (buf2, sizeof (buf2), left),
755 parallel_size, add_commas (buf3, sizeof (buf3), left_parallel),
756 cond_size, add_commas (buf4, sizeof (buf4), left_cond),
757 nop_size, add_commas (buf5, sizeof (buf5), left_nops));
758
759 (*d10v_callback->printf_filtered) (d10v_callback,
760 "executed %*s right instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
761 size, add_commas (buf1, sizeof (buf1), right_total),
762 normal_size, add_commas (buf2, sizeof (buf2), right),
763 parallel_size, add_commas (buf3, sizeof (buf3), right_parallel),
764 cond_size, add_commas (buf4, sizeof (buf4), right_cond),
765 nop_size, add_commas (buf5, sizeof (buf5), right_nops));
766
767 if (ins_long)
768 (*d10v_callback->printf_filtered) (d10v_callback,
769 "executed %*s long instruction(s)\n",
770 size, add_commas (buf1, sizeof (buf1), ins_long));
771
772 if (parallel)
773 (*d10v_callback->printf_filtered) (d10v_callback,
774 "executed %*s parallel instruction(s)\n",
775 size, add_commas (buf1, sizeof (buf1), parallel));
776
777 if (leftright)
778 (*d10v_callback->printf_filtered) (d10v_callback,
779 "executed %*s instruction(s) encoded L->R\n",
780 size, add_commas (buf1, sizeof (buf1), leftright));
781
782 if (rightleft)
783 (*d10v_callback->printf_filtered) (d10v_callback,
784 "executed %*s instruction(s) encoded R->L\n",
785 size, add_commas (buf1, sizeof (buf1), rightleft));
786
787 if (unknown)
788 (*d10v_callback->printf_filtered) (d10v_callback,
789 "executed %*s unknown instruction(s)\n",
790 size, add_commas (buf1, sizeof (buf1), unknown));
791
792 if (cond_true)
793 (*d10v_callback->printf_filtered) (d10v_callback,
794 "executed %*s instruction(s) due to EXExxx condition being true\n",
795 size, add_commas (buf1, sizeof (buf1), cond_true));
796
797 if (cond_false)
798 (*d10v_callback->printf_filtered) (d10v_callback,
799 "skipped %*s instruction(s) due to EXExxx condition being false\n",
800 size, add_commas (buf1, sizeof (buf1), cond_false));
801
802 if (cond_jump)
803 (*d10v_callback->printf_filtered) (d10v_callback,
804 "skipped %*s instruction(s) due to conditional branch succeeding\n",
805 size, add_commas (buf1, sizeof (buf1), cond_jump));
806
807 (*d10v_callback->printf_filtered) (d10v_callback,
808 "executed %*s cycle(s)\n",
809 size, add_commas (buf1, sizeof (buf1), cycles));
810
811 (*d10v_callback->printf_filtered) (d10v_callback,
812 "executed %*s total instructions\n",
813 size, add_commas (buf1, sizeof (buf1), total));
814 }
815
816 SIM_RC
817 sim_create_inferior (sd, abfd, argv, env)
818 SIM_DESC sd;
819 struct _bfd *abfd;
820 char **argv;
821 char **env;
822 {
823 bfd_vma start_address;
824
825 /* reset all state information */
826 memset (&State.regs, 0, (int)&State.imem - (int)&State.regs[0]);
827
828 /* set PC */
829 if (abfd != NULL)
830 start_address = bfd_get_start_address (prog_bfd);
831 else
832 start_address = 0xffc0 << 2;
833 #ifdef DEBUG
834 if (d10v_debug)
835 (*d10v_callback->printf_filtered) (d10v_callback, "sim_create_inferior: PC=0x%lx\n", (long) start_address);
836 #endif
837 PC = start_address >> 2;
838
839 /* cpu resets imap0 to 0 and imap1 to 0x7f, but D10V-EVA board */
840 /* resets imap0 and imap1 to 0x1000. */
841
842 SET_IMAP0(0x1000);
843 SET_IMAP1(0x1000);
844 SET_DMAP(0);
845
846 return SIM_RC_OK;
847 }
848
849
850 void
851 sim_set_callbacks (p)
852 host_callback *p;
853 {
854 d10v_callback = p;
855 }
856
857 void
858 sim_stop_reason (sd, reason, sigrc)
859 SIM_DESC sd;
860 enum sim_stop *reason;
861 int *sigrc;
862 {
863 /* (*d10v_callback->printf_filtered) (d10v_callback, "sim_stop_reason: PC=0x%x\n",PC<<2); */
864
865 switch (State.exception)
866 {
867 case SIG_D10V_STOP: /* stop instruction */
868 *reason = sim_exited;
869 *sigrc = 0;
870 break;
871
872 case SIG_D10V_EXIT: /* exit trap */
873 *reason = sim_exited;
874 *sigrc = State.regs[2];
875 break;
876
877 default: /* some signal */
878 *reason = sim_stopped;
879 *sigrc = State.exception;
880 break;
881 }
882 }
883
884 void
885 sim_fetch_register (sd, rn, memory)
886 SIM_DESC sd;
887 int rn;
888 unsigned char *memory;
889 {
890 if (!State.imem)
891 init_system();
892
893 if (rn > 34)
894 WRITE_64 (memory, State.a[rn-35]);
895 else if (rn == 32)
896 WRITE_16 (memory, IMAP0);
897 else if (rn == 33)
898 WRITE_16 (memory, IMAP1);
899 else if (rn == 34)
900 WRITE_16 (memory, DMAP);
901 else
902 WRITE_16 (memory, State.regs[rn]);
903 }
904
905 void
906 sim_store_register (sd, rn, memory)
907 SIM_DESC sd;
908 int rn;
909 unsigned char *memory;
910 {
911 if (!State.imem)
912 init_system();
913
914 if (rn > 34)
915 State.a[rn-35] = READ_64 (memory) & MASK40;
916 else if (rn == 34)
917 SET_DMAP( READ_16(memory) );
918 else if (rn == 33)
919 SET_IMAP1( READ_16(memory) );
920 else if (rn == 32)
921 SET_IMAP0( READ_16(memory) );
922 else
923 State.regs[rn]= READ_16 (memory);
924 }
925
926
927 void
928 sim_do_command (sd, cmd)
929 SIM_DESC sd;
930 char *cmd;
931 {
932 (*d10v_callback->printf_filtered) (d10v_callback, "sim_do_command: %s\n",cmd);
933 }
934
935 SIM_RC
936 sim_load (sd, prog, abfd, from_tty)
937 SIM_DESC sd;
938 char *prog;
939 bfd *abfd;
940 int from_tty;
941 {
942 extern bfd *sim_load_file (); /* ??? Don't know where this should live. */
943
944 if (prog_bfd != NULL && prog_bfd_was_opened_p)
945 bfd_close (prog_bfd);
946 prog_bfd = sim_load_file (sd, myname, d10v_callback, prog, abfd,
947 sim_kind == SIM_OPEN_DEBUG,
948 0, sim_write_phys);
949 if (prog_bfd == NULL)
950 return SIM_RC_FAIL;
951 prog_bfd_was_opened_p = abfd == NULL;
952 return SIM_RC_OK;
953 }
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