ef34f9423b34d6cf0073f697bccd388d642ce92b
13 #include "sys/syscall.h"
15 extern char *strrchr ();
48 move_to_cr (int cr
, reg_t val
)
53 State
.sp
[State
.SM
] = State
.regs
[SP_IDX
]; /* save old SP */
54 State
.SM
= (val
& PSW_SM_BIT
) != 0;
55 State
.EA
= (val
& PSW_EA_BIT
) != 0;
56 State
.DB
= (val
& PSW_DB_BIT
) != 0;
57 State
.DM
= (val
& PSW_DM_BIT
) != 0;
58 State
.IE
= (val
& PSW_IE_BIT
) != 0;
59 State
.RP
= (val
& PSW_RP_BIT
) != 0;
60 State
.MD
= (val
& PSW_MD_BIT
) != 0;
61 State
.FX
= (val
& PSW_FX_BIT
) != 0;
62 State
.ST
= (val
& PSW_ST_BIT
) != 0;
63 State
.F0
= (val
& PSW_F0_BIT
) != 0;
64 State
.F1
= (val
& PSW_F1_BIT
) != 0;
65 State
.C
= (val
& PSW_C_BIT
) != 0;
66 State
.regs
[SP_IDX
] = State
.sp
[State
.SM
]; /* restore new SP */
67 if (State
.ST
&& !State
.FX
)
69 (*d10v_callback
->printf_filtered
)
71 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
73 State
.exception
= SIGILL
;
75 State
.cregs
[cr
] = (val
& ~0x4032);
79 State
.cregs
[cr
] = (val
& ~0x4032);
83 State
.cregs
[cr
] = (val
& ~0x1);
86 State
.cregs
[cr
] = val
;
98 if (State
.SM
) val
|= PSW_SM_BIT
;
99 if (State
.EA
) val
|= PSW_EA_BIT
;
100 if (State
.DB
) val
|= PSW_DB_BIT
;
101 if (State
.DM
) val
|= PSW_DM_BIT
;
102 if (State
.IE
) val
|= PSW_IE_BIT
;
103 if (State
.RP
) val
|= PSW_RP_BIT
;
104 if (State
.MD
) val
|= PSW_MD_BIT
;
105 if (State
.FX
) val
|= PSW_FX_BIT
;
106 if (State
.ST
) val
|= PSW_ST_BIT
;
107 if (State
.F0
) val
|= PSW_F0_BIT
;
108 if (State
.F1
) val
|= PSW_F1_BIT
;
109 if (State
.C
) val
|= PSW_C_BIT
;
112 val
= State
.cregs
[cr
];
120 static void trace_input_func
PARAMS ((char *name
,
125 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
127 static void trace_output_func
PARAMS ((enum op_types result
));
129 #define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0)
131 #ifndef SIZE_INSTRUCTION
132 #define SIZE_INSTRUCTION 8
135 #ifndef SIZE_OPERANDS
136 #define SIZE_OPERANDS 18
140 #define SIZE_VALUES 13
143 #ifndef SIZE_LOCATION
144 #define SIZE_LOCATION 20
151 #ifndef SIZE_LINE_NUMBER
152 #define SIZE_LINE_NUMBER 4
156 trace_input_func (name
, in1
, in2
, in3
)
169 const char *filename
;
170 const char *functionname
;
171 unsigned int linenumber
;
174 if ((d10v_debug
& DEBUG_TRACE
) == 0)
177 switch (State
.ins_type
)
180 case INS_UNKNOWN
: type
= " ?"; break;
181 case INS_LEFT
: type
= " L"; break;
182 case INS_RIGHT
: type
= " R"; break;
183 case INS_LEFT_PARALLEL
: type
= "*L"; break;
184 case INS_RIGHT_PARALLEL
: type
= "*R"; break;
185 case INS_LEFT_COND_TEST
: type
= "?L"; break;
186 case INS_RIGHT_COND_TEST
: type
= "?R"; break;
187 case INS_LEFT_COND_EXE
: type
= "&L"; break;
188 case INS_RIGHT_COND_EXE
: type
= "&R"; break;
189 case INS_LONG
: type
= " B"; break;
192 if ((d10v_debug
& DEBUG_LINE_NUMBER
) == 0)
193 (*d10v_callback
->printf_filtered
) (d10v_callback
,
195 SIZE_PC
, (unsigned)PC
,
197 SIZE_INSTRUCTION
, name
);
202 byte_pc
= decode_pc ();
203 if (text
&& byte_pc
>= text_start
&& byte_pc
< text_end
)
205 filename
= (const char *)0;
206 functionname
= (const char *)0;
208 if (bfd_find_nearest_line (prog_bfd
, text
, (struct symbol_cache_entry
**)0, byte_pc
- text_start
,
209 &filename
, &functionname
, &linenumber
))
214 sprintf (p
, "#%-*d ", SIZE_LINE_NUMBER
, linenumber
);
219 sprintf (p
, "%-*s ", SIZE_LINE_NUMBER
+1, "---");
220 p
+= SIZE_LINE_NUMBER
+2;
225 sprintf (p
, "%s ", functionname
);
230 char *q
= strrchr (filename
, '/');
231 sprintf (p
, "%s ", (q
) ? q
+1 : filename
);
240 (*d10v_callback
->printf_filtered
) (d10v_callback
,
241 "0x%.*x %s: %-*.*s %-*s ",
242 SIZE_PC
, (unsigned)PC
,
244 SIZE_LOCATION
, SIZE_LOCATION
, buf
,
245 SIZE_INSTRUCTION
, name
);
253 for (i
= 0; i
< 3; i
++)
268 sprintf (p
, "%sr%d", comma
, OP
[i
]);
276 sprintf (p
, "%scr%d", comma
, OP
[i
]);
282 case OP_ACCUM_OUTPUT
:
283 case OP_ACCUM_REVERSE
:
284 sprintf (p
, "%sa%d", comma
, OP
[i
]);
290 sprintf (p
, "%s%d", comma
, OP
[i
]);
296 sprintf (p
, "%s%d", comma
, SEXT8(OP
[i
]));
302 sprintf (p
, "%s%d", comma
, SEXT4(OP
[i
]));
308 sprintf (p
, "%s%d", comma
, SEXT3(OP
[i
]));
314 sprintf (p
, "%s@r%d", comma
, OP
[i
]);
320 sprintf (p
, "%s@(%d,r%d)", comma
, (int16
)OP
[i
], OP
[i
+1]);
326 sprintf (p
, "%s@r%d+", comma
, OP
[i
]);
332 sprintf (p
, "%s@r%d-", comma
, OP
[i
]);
338 sprintf (p
, "%s@-r%d", comma
, OP
[i
]);
346 sprintf (p
, "%sf0", comma
);
349 sprintf (p
, "%sf1", comma
);
352 sprintf (p
, "%sc", comma
);
360 if ((d10v_debug
& DEBUG_VALUES
) == 0)
364 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%s", buf
);
369 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%-*s", SIZE_OPERANDS
, buf
);
372 for (i
= 0; i
< 3; i
++)
378 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s", SIZE_VALUES
, "");
384 case OP_ACCUM_OUTPUT
:
386 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s", SIZE_VALUES
, "---");
394 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
395 (uint16
)State
.regs
[OP
[i
]]);
399 tmp
= (long)((((uint32
) State
.regs
[OP
[i
]]) << 16) | ((uint32
) State
.regs
[OP
[i
]+1]));
400 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.8lx", SIZE_VALUES
-10, "", tmp
);
405 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
406 (uint16
)State
.cregs
[OP
[i
]]);
410 case OP_ACCUM_REVERSE
:
411 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.2x%.8lx", SIZE_VALUES
-12, "",
412 ((int)(State
.a
[OP
[i
]] >> 32) & 0xff),
413 ((unsigned long)State
.a
[OP
[i
]]) & 0xffffffff);
417 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
422 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
423 (uint16
)SEXT4(OP
[i
]));
427 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
428 (uint16
)SEXT8(OP
[i
]));
432 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
433 (uint16
)SEXT3(OP
[i
]));
438 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sF0 = %d", SIZE_VALUES
-6, "",
442 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sF1 = %d", SIZE_VALUES
-6, "",
446 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sC = %d", SIZE_VALUES
-5, "",
452 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
454 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
455 (uint16
)State
.regs
[OP
[++i
]]);
459 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
460 (uint16
)State
.regs
[0]);
464 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
465 (uint16
)State
.regs
[1]);
469 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
470 (uint16
)State
.regs
[2]);
474 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
475 (uint16
)State
.regs
[0]);
476 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
477 (uint16
)State
.regs
[1]);
484 (*d10v_callback
->flush_stdout
) (d10v_callback
);
488 trace_output_func (result
)
489 enum op_types result
;
491 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
503 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
504 (uint16
)State
.regs
[OP
[0]],
505 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
510 tmp
= (long)((((uint32
) State
.regs
[OP
[0]]) << 16) | ((uint32
) State
.regs
[OP
[0]+1]));
511 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES
-10, "", tmp
,
512 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
517 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
518 (uint16
)State
.cregs
[OP
[0]],
519 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
523 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
524 (uint16
)State
.cregs
[OP
[1]],
525 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
529 case OP_ACCUM_OUTPUT
:
530 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES
-12, "",
531 ((int)(State
.a
[OP
[0]] >> 32) & 0xff),
532 ((unsigned long)State
.a
[OP
[0]]) & 0xffffffff,
533 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
536 case OP_ACCUM_REVERSE
:
537 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES
-12, "",
538 ((int)(State
.a
[OP
[1]] >> 32) & 0xff),
539 ((unsigned long)State
.a
[OP
[1]]) & 0xffffffff,
540 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
545 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES
, "",
546 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
550 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
551 (uint16
)State
.regs
[0],
552 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
556 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-10, "",
557 (uint16
)State
.regs
[0], (uint16
)State
.regs
[1],
558 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
563 (*d10v_callback
->flush_stdout
) (d10v_callback
);
567 #define trace_input(NAME, IN1, IN2, IN3)
568 #define trace_output(RESULT)
575 trace_input ("abs", OP_REG
, OP_VOID
, OP_VOID
);
577 if ((int16
)(State
.regs
[OP
[0]]) < 0)
579 State
.regs
[OP
[0]] = -(int16
)(State
.regs
[OP
[0]]);
584 trace_output (OP_REG
);
593 trace_input ("abs", OP_ACCUM
, OP_VOID
, OP_VOID
);
595 State
.a
[OP
[0]] = SEXT40(State
.a
[OP
[0]]);
597 if (State
.a
[OP
[0]] < 0 )
599 tmp
= -State
.a
[OP
[0]];
603 State
.a
[OP
[0]] = MAX32
;
604 else if (tmp
< MIN32
)
605 State
.a
[OP
[0]] = MIN32
;
607 State
.a
[OP
[0]] = tmp
& MASK40
;
610 State
.a
[OP
[0]] = tmp
& MASK40
;
615 trace_output (OP_ACCUM
);
622 uint16 tmp
= State
.regs
[OP
[0]];
623 trace_input ("add", OP_REG
, OP_REG
, OP_VOID
);
624 State
.regs
[OP
[0]] += State
.regs
[OP
[1]];
625 if ( tmp
> State
.regs
[OP
[0]])
629 trace_output (OP_REG
);
637 tmp
= SEXT40(State
.a
[OP
[0]]) + (SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1]);
639 trace_input ("add", OP_ACCUM
, OP_REG
, OP_VOID
);
643 State
.a
[OP
[0]] = MAX32
;
644 else if ( tmp
< MIN32
)
645 State
.a
[OP
[0]] = MIN32
;
647 State
.a
[OP
[0]] = tmp
& MASK40
;
650 State
.a
[OP
[0]] = tmp
& MASK40
;
651 trace_output (OP_ACCUM
);
659 tmp
= SEXT40(State
.a
[OP
[0]]) + SEXT40(State
.a
[OP
[1]]);
661 trace_input ("add", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
665 State
.a
[OP
[0]] = MAX32
;
666 else if ( tmp
< MIN32
)
667 State
.a
[OP
[0]] = MIN32
;
669 State
.a
[OP
[0]] = tmp
& MASK40
;
672 State
.a
[OP
[0]] = tmp
& MASK40
;
673 trace_output (OP_ACCUM
);
681 uint32 a
= (State
.regs
[OP
[0]]) << 16 | State
.regs
[OP
[0]+1];
682 uint32 b
= (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
684 trace_input ("add2w", OP_DREG
, OP_DREG
, OP_VOID
);
687 State
.regs
[OP
[0]] = tmp
>> 16;
688 State
.regs
[OP
[0]+1] = tmp
& 0xFFFF;
689 trace_output (OP_DREG
);
696 uint16 tmp
= State
.regs
[OP
[1]];
697 State
.regs
[OP
[0]] = tmp
+ OP
[2];
699 trace_input ("add3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
700 State
.C
= (State
.regs
[OP
[0]] < tmp
);
701 trace_output (OP_REG
);
709 tmp
= SEXT40(State
.a
[OP
[2]]) + SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
711 trace_input ("addac3", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
712 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
713 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
714 trace_output (OP_DREG
);
722 tmp
= SEXT40(State
.a
[OP
[1]]) + SEXT40(State
.a
[OP
[2]]);
724 trace_input ("addac3", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
725 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
726 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
727 trace_output (OP_DREG
);
737 trace_input ("addac3s", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
738 tmp
= SEXT40(State
.a
[OP
[2]]) + SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
741 State
.regs
[OP
[0]] = 0x7fff;
742 State
.regs
[OP
[0]+1] = 0xffff;
745 else if (tmp
< MIN32
)
747 State
.regs
[OP
[0]] = 0x8000;
748 State
.regs
[OP
[0]+1] = 0;
753 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
754 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
757 trace_output (OP_DREG
);
767 trace_input ("addac3s", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
768 tmp
= SEXT40(State
.a
[OP
[1]]) + SEXT40(State
.a
[OP
[2]]);
771 State
.regs
[OP
[0]] = 0x7fff;
772 State
.regs
[OP
[0]+1] = 0xffff;
775 else if (tmp
< MIN32
)
777 State
.regs
[OP
[0]] = 0x8000;
778 State
.regs
[OP
[0]+1] = 0;
783 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
784 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
787 trace_output (OP_DREG
);
794 uint tmp
= State
.regs
[OP
[0]];
798 trace_input ("addi", OP_REG
, OP_CONSTANT16
, OP_VOID
);
799 State
.regs
[OP
[0]] += OP
[1];
800 State
.C
= (State
.regs
[OP
[0]] < tmp
);
801 trace_output (OP_REG
);
808 trace_input ("and", OP_REG
, OP_REG
, OP_VOID
);
809 State
.regs
[OP
[0]] &= State
.regs
[OP
[1]];
810 trace_output (OP_REG
);
817 trace_input ("and3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
818 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] & OP
[2];
819 trace_output (OP_REG
);
826 trace_input ("bclri", OP_REG
, OP_CONSTANT16
, OP_VOID
);
827 State
.regs
[OP
[0]] &= ~(0x8000 >> OP
[1]);
828 trace_output (OP_REG
);
835 trace_input ("bl.s", OP_CONSTANT8
, OP_R0
, OP_R1
);
836 State
.regs
[13] = PC
+1;
837 JMP( PC
+ SEXT8 (OP
[0]));
838 trace_output (OP_VOID
);
845 trace_input ("bl.l", OP_CONSTANT16
, OP_R0
, OP_R1
);
846 State
.regs
[13] = PC
+1;
848 trace_output (OP_VOID
);
855 trace_input ("bnoti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
856 State
.regs
[OP
[0]] ^= 0x8000 >> OP
[1];
857 trace_output (OP_REG
);
864 trace_input ("bra.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
865 JMP (PC
+ SEXT8 (OP
[0]));
866 trace_output (OP_VOID
);
873 trace_input ("bra.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
875 trace_output (OP_VOID
);
882 trace_input ("brf0f.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
884 JMP (PC
+ SEXT8 (OP
[0]));
885 trace_output (OP_FLAG
);
892 trace_input ("brf0f.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
895 trace_output (OP_FLAG
);
902 trace_input ("brf0t.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
904 JMP (PC
+ SEXT8 (OP
[0]));
905 trace_output (OP_FLAG
);
912 trace_input ("brf0t.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
915 trace_output (OP_FLAG
);
922 trace_input ("bseti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
923 State
.regs
[OP
[0]] |= 0x8000 >> OP
[1];
924 trace_output (OP_REG
);
931 trace_input ("btsti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
933 State
.F0
= (State
.regs
[OP
[0]] & (0x8000 >> OP
[1])) ? 1 : 0;
934 trace_output (OP_FLAG
);
941 trace_input ("clrac", OP_ACCUM_OUTPUT
, OP_VOID
, OP_VOID
);
943 trace_output (OP_ACCUM
);
950 trace_input ("cmp", OP_REG
, OP_REG
, OP_VOID
);
952 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)(State
.regs
[OP
[1]])) ? 1 : 0;
953 trace_output (OP_FLAG
);
960 trace_input ("cmp", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
962 State
.F0
= (SEXT40(State
.a
[OP
[0]]) < SEXT40(State
.a
[OP
[1]])) ? 1 : 0;
963 trace_output (OP_FLAG
);
970 trace_input ("cmpeq", OP_REG
, OP_REG
, OP_VOID
);
972 State
.F0
= (State
.regs
[OP
[0]] == State
.regs
[OP
[1]]) ? 1 : 0;
973 trace_output (OP_FLAG
);
980 trace_input ("cmpeq", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
982 State
.F0
= ((State
.a
[OP
[0]] & MASK40
) == (State
.a
[OP
[1]] & MASK40
)) ? 1 : 0;
983 trace_output (OP_FLAG
);
990 trace_input ("cmpeqi.s", OP_REG
, OP_CONSTANT4
, OP_VOID
);
992 State
.F0
= (State
.regs
[OP
[0]] == (reg_t
)SEXT4(OP
[1])) ? 1 : 0;
993 trace_output (OP_FLAG
);
1000 trace_input ("cmpeqi.l", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1001 State
.F1
= State
.F0
;
1002 State
.F0
= (State
.regs
[OP
[0]] == (reg_t
)OP
[1]) ? 1 : 0;
1003 trace_output (OP_FLAG
);
1010 trace_input ("cmpi.s", OP_REG
, OP_CONSTANT4
, OP_VOID
);
1011 State
.F1
= State
.F0
;
1012 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)SEXT4(OP
[1])) ? 1 : 0;
1013 trace_output (OP_FLAG
);
1020 trace_input ("cmpi.l", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1021 State
.F1
= State
.F0
;
1022 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)(OP
[1])) ? 1 : 0;
1023 trace_output (OP_FLAG
);
1030 trace_input ("cmpu", OP_REG
, OP_REG
, OP_VOID
);
1031 State
.F1
= State
.F0
;
1032 State
.F0
= (State
.regs
[OP
[0]] < State
.regs
[OP
[1]]) ? 1 : 0;
1033 trace_output (OP_FLAG
);
1040 trace_input ("cmpui", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1041 State
.F1
= State
.F0
;
1042 State
.F0
= (State
.regs
[OP
[0]] < (reg_t
)OP
[1]) ? 1 : 0;
1043 trace_output (OP_FLAG
);
1052 trace_input ("cpfg", OP_FLAG_OUTPUT
, OP_FLAG
, OP_VOID
);
1060 else if (OP
[1] == 1)
1066 trace_output (OP_FLAG
);
1073 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
1074 State
.exception
= SIGTRAP
;
1081 uint16 foo
, tmp
, tmpf
;
1083 trace_input ("divs", OP_DREG
, OP_REG
, OP_VOID
);
1084 foo
= (State
.regs
[OP
[0]] << 1) | (State
.regs
[OP
[0]+1] >> 15);
1085 tmp
= (int16
)foo
- (int16
)(State
.regs
[OP
[1]]);
1086 tmpf
= (foo
>= State
.regs
[OP
[1]]) ? 1 : 0;
1087 State
.regs
[OP
[0]] = (tmpf
== 1) ? tmp
: foo
;
1088 State
.regs
[OP
[0]+1] = (State
.regs
[OP
[0]+1] << 1) | tmpf
;
1089 trace_output (OP_DREG
);
1096 trace_input ("exef0f", OP_VOID
, OP_VOID
, OP_VOID
);
1097 State
.exe
= (State
.F0
== 0);
1098 trace_output (OP_FLAG
);
1105 trace_input ("exef0t", OP_VOID
, OP_VOID
, OP_VOID
);
1106 State
.exe
= (State
.F0
!= 0);
1107 trace_output (OP_FLAG
);
1114 trace_input ("exef1f", OP_VOID
, OP_VOID
, OP_VOID
);
1115 State
.exe
= (State
.F1
== 0);
1116 trace_output (OP_FLAG
);
1123 trace_input ("exef1t", OP_VOID
, OP_VOID
, OP_VOID
);
1124 State
.exe
= (State
.F1
!= 0);
1125 trace_output (OP_FLAG
);
1132 trace_input ("exefaf", OP_VOID
, OP_VOID
, OP_VOID
);
1133 State
.exe
= (State
.F0
== 0) & (State
.F1
== 0);
1134 trace_output (OP_FLAG
);
1141 trace_input ("exefat", OP_VOID
, OP_VOID
, OP_VOID
);
1142 State
.exe
= (State
.F0
== 0) & (State
.F1
!= 0);
1143 trace_output (OP_FLAG
);
1150 trace_input ("exetaf", OP_VOID
, OP_VOID
, OP_VOID
);
1151 State
.exe
= (State
.F0
!= 0) & (State
.F1
== 0);
1152 trace_output (OP_FLAG
);
1159 trace_input ("exetat", OP_VOID
, OP_VOID
, OP_VOID
);
1160 State
.exe
= (State
.F0
!= 0) & (State
.F1
!= 0);
1161 trace_output (OP_FLAG
);
1171 trace_input ("exp", OP_REG_OUTPUT
, OP_DREG
, OP_VOID
);
1172 if (((int16
)State
.regs
[OP
[1]]) >= 0)
1173 tmp
= (State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1];
1175 tmp
= ~((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
1182 State
.regs
[OP
[0]] = i
-1;
1183 trace_output (OP_REG
);
1188 State
.regs
[OP
[0]] = 16;
1189 trace_output (OP_REG
);
1199 trace_input ("exp", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1200 tmp
= SEXT40(State
.a
[OP
[1]]);
1202 tmp
= ~tmp
& MASK40
;
1204 foo
= 0x4000000000LL
;
1209 State
.regs
[OP
[0]] = i
-9;
1210 trace_output (OP_REG
);
1215 State
.regs
[OP
[0]] = 16;
1216 trace_output (OP_REG
);
1223 trace_input ("jl", OP_REG
, OP_R0
, OP_R1
);
1224 State
.regs
[13] = PC
+1;
1225 JMP (State
.regs
[OP
[0]]);
1226 trace_output (OP_VOID
);
1233 trace_input ("jmp", OP_REG
,
1234 (OP
[0] == 13) ? OP_R0
: OP_VOID
,
1235 (OP
[0] == 13) ? OP_R1
: OP_VOID
);
1237 JMP (State
.regs
[OP
[0]]);
1238 trace_output (OP_VOID
);
1245 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1246 State
.regs
[OP
[0]] = RW (OP
[1] + State
.regs
[OP
[2]]);
1247 trace_output (OP_REG
);
1254 trace_input ("ld", OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1255 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1256 INC_ADDR(State
.regs
[OP
[1]],-2);
1257 trace_output (OP_REG
);
1264 trace_input ("ld", OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1265 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1266 INC_ADDR(State
.regs
[OP
[1]],2);
1267 trace_output (OP_REG
);
1274 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1275 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1276 trace_output (OP_REG
);
1283 uint16 addr
= State
.regs
[OP
[2]];
1284 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1285 State
.regs
[OP
[0]] = RW (OP
[1] + addr
);
1286 State
.regs
[OP
[0]+1] = RW (OP
[1] + addr
+ 2);
1287 trace_output (OP_DREG
);
1294 uint16 addr
= State
.regs
[OP
[1]];
1295 trace_input ("ld2w", OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1296 State
.regs
[OP
[0]] = RW (addr
);
1297 State
.regs
[OP
[0]+1] = RW (addr
+2);
1298 INC_ADDR(State
.regs
[OP
[1]],-4);
1299 trace_output (OP_DREG
);
1306 uint16 addr
= State
.regs
[OP
[1]];
1307 trace_input ("ld2w", OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1308 State
.regs
[OP
[0]] = RW (addr
);
1309 State
.regs
[OP
[0]+1] = RW (addr
+2);
1310 INC_ADDR(State
.regs
[OP
[1]],4);
1311 trace_output (OP_DREG
);
1318 uint16 addr
= State
.regs
[OP
[1]];
1319 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1320 State
.regs
[OP
[0]] = RW (addr
);
1321 State
.regs
[OP
[0]+1] = RW (addr
+2);
1322 trace_output (OP_DREG
);
1329 trace_input ("ldb", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1330 State
.regs
[OP
[0]] = SEXT8 (RB (OP
[1] + State
.regs
[OP
[2]]));
1331 trace_output (OP_REG
);
1338 trace_input ("ldb", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1339 State
.regs
[OP
[0]] = SEXT8 (RB (State
.regs
[OP
[1]]));
1340 trace_output (OP_REG
);
1347 trace_input ("ldi.s", OP_REG_OUTPUT
, OP_CONSTANT4
, OP_VOID
);
1348 State
.regs
[OP
[0]] = SEXT4(OP
[1]);
1349 trace_output (OP_REG
);
1356 trace_input ("ldi.l", OP_REG_OUTPUT
, OP_CONSTANT16
, OP_VOID
);
1357 State
.regs
[OP
[0]] = OP
[1];
1358 trace_output (OP_REG
);
1365 trace_input ("ldub", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1366 State
.regs
[OP
[0]] = RB (OP
[1] + State
.regs
[OP
[2]]);
1367 trace_output (OP_REG
);
1374 trace_input ("ldub", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1375 State
.regs
[OP
[0]] = RB (State
.regs
[OP
[1]]);
1376 trace_output (OP_REG
);
1385 trace_input ("mac", OP_ACCUM
, OP_REG
, OP_REG
);
1386 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1389 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1391 if (State
.ST
&& tmp
> MAX32
)
1394 tmp
+= SEXT40(State
.a
[OP
[0]]);
1398 State
.a
[OP
[0]] = MAX32
;
1399 else if (tmp
< MIN32
)
1400 State
.a
[OP
[0]] = MIN32
;
1402 State
.a
[OP
[0]] = tmp
& MASK40
;
1405 State
.a
[OP
[0]] = tmp
& MASK40
;
1406 trace_output (OP_ACCUM
);
1415 trace_input ("macsu", OP_ACCUM
, OP_REG
, OP_REG
);
1416 tmp
= SEXT40 ((int16
)State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1418 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1420 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) + tmp
) & MASK40
;
1421 trace_output (OP_ACCUM
);
1432 trace_input ("macu", OP_ACCUM
, OP_REG
, OP_REG
);
1433 src1
= (uint16
) State
.regs
[OP
[1]];
1434 src2
= (uint16
) State
.regs
[OP
[2]];
1438 State
.a
[OP
[0]] = (State
.a
[OP
[0]] + tmp
) & MASK40
;
1439 trace_output (OP_ACCUM
);
1446 trace_input ("max", OP_REG
, OP_REG
, OP_VOID
);
1447 State
.F1
= State
.F0
;
1448 if ((int16
)State
.regs
[OP
[1]] > (int16
)State
.regs
[OP
[0]])
1450 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1455 trace_output (OP_REG
);
1464 trace_input ("max", OP_ACCUM
, OP_DREG
, OP_VOID
);
1465 State
.F1
= State
.F0
;
1466 tmp
= SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
1467 if (tmp
> SEXT40(State
.a
[OP
[0]]))
1469 State
.a
[OP
[0]] = tmp
& MASK40
;
1474 trace_output (OP_ACCUM
);
1481 trace_input ("max", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1482 State
.F1
= State
.F0
;
1483 if (SEXT40(State
.a
[OP
[1]]) > SEXT40(State
.a
[OP
[0]]))
1485 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1490 trace_output (OP_ACCUM
);
1498 trace_input ("min", OP_REG
, OP_REG
, OP_VOID
);
1499 State
.F1
= State
.F0
;
1500 if ((int16
)State
.regs
[OP
[1]] < (int16
)State
.regs
[OP
[0]])
1502 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1507 trace_output (OP_REG
);
1516 trace_input ("min", OP_ACCUM
, OP_DREG
, OP_VOID
);
1517 State
.F1
= State
.F0
;
1518 tmp
= SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
1519 if (tmp
< SEXT40(State
.a
[OP
[0]]))
1521 State
.a
[OP
[0]] = tmp
& MASK40
;
1526 trace_output (OP_ACCUM
);
1533 trace_input ("min", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1534 State
.F1
= State
.F0
;
1535 if (SEXT40(State
.a
[OP
[1]]) < SEXT40(State
.a
[OP
[0]]))
1537 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1542 trace_output (OP_ACCUM
);
1551 trace_input ("msb", OP_ACCUM
, OP_REG
, OP_REG
);
1552 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1555 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1557 if (State
.ST
&& tmp
> MAX32
)
1560 tmp
= SEXT40(State
.a
[OP
[0]]) - tmp
;
1564 State
.a
[OP
[0]] = MAX32
;
1565 else if (tmp
< MIN32
)
1566 State
.a
[OP
[0]] = MIN32
;
1568 State
.a
[OP
[0]] = tmp
& MASK40
;
1571 State
.a
[OP
[0]] = tmp
& MASK40
;
1572 trace_output (OP_ACCUM
);
1581 trace_input ("msbsu", OP_ACCUM
, OP_REG
, OP_REG
);
1582 tmp
= SEXT40 ((int16
)State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1584 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1586 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) - tmp
) & MASK40
;
1587 trace_output (OP_ACCUM
);
1598 trace_input ("msbu", OP_ACCUM
, OP_REG
, OP_REG
);
1599 src1
= (uint16
) State
.regs
[OP
[1]];
1600 src2
= (uint16
) State
.regs
[OP
[2]];
1605 State
.a
[OP
[0]] = (State
.a
[OP
[0]] - tmp
) & MASK40
;
1606 trace_output (OP_ACCUM
);
1613 trace_input ("mul", OP_REG
, OP_REG
, OP_VOID
);
1614 State
.regs
[OP
[0]] *= State
.regs
[OP
[1]];
1615 trace_output (OP_REG
);
1624 trace_input ("mulx", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1625 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1628 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1630 if (State
.ST
&& tmp
> MAX32
)
1631 State
.a
[OP
[0]] = MAX32
;
1633 State
.a
[OP
[0]] = tmp
& MASK40
;
1634 trace_output (OP_ACCUM
);
1643 trace_input ("mulxsu", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1644 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * State
.regs
[OP
[2]]);
1649 State
.a
[OP
[0]] = tmp
& MASK40
;
1650 trace_output (OP_ACCUM
);
1661 trace_input ("mulxu", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1662 src1
= (uint16
) State
.regs
[OP
[1]];
1663 src2
= (uint16
) State
.regs
[OP
[2]];
1668 State
.a
[OP
[0]] = tmp
& MASK40
;
1669 trace_output (OP_ACCUM
);
1676 trace_input ("mv", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1677 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1678 trace_output (OP_REG
);
1685 trace_input ("mv2w", OP_DREG_OUTPUT
, OP_DREG
, OP_VOID
);
1686 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1687 State
.regs
[OP
[0]+1] = State
.regs
[OP
[1]+1];
1688 trace_output (OP_DREG
);
1695 trace_input ("mv2wfac", OP_DREG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1696 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 16) & 0xffff;
1697 State
.regs
[OP
[0]+1] = State
.a
[OP
[1]] & 0xffff;
1698 trace_output (OP_DREG
);
1705 trace_input ("mv2wtac", OP_DREG
, OP_ACCUM_OUTPUT
, OP_VOID
);
1706 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]]) << 16 | State
.regs
[OP
[0]+1]) & MASK40
;
1707 trace_output (OP_ACCUM_REVERSE
);
1714 trace_input ("mvac", OP_ACCUM_OUTPUT
, OP_ACCUM
, OP_VOID
);
1715 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1716 trace_output (OP_ACCUM
);
1723 trace_input ("mvb", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1724 State
.regs
[OP
[0]] = SEXT8 (State
.regs
[OP
[1]] & 0xff);
1725 trace_output (OP_REG
);
1732 trace_input ("mf0f", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1734 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1735 trace_output (OP_REG
);
1742 trace_input ("mf0t", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1744 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1745 trace_output (OP_REG
);
1752 trace_input ("mvfacg", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1753 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 32) & 0xff;
1754 trace_output (OP_ACCUM
);
1761 trace_input ("mvfachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1762 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 16) & 0xffff;
1763 trace_output (OP_REG
);
1770 trace_input ("mvfaclo", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1771 State
.regs
[OP
[0]] = State
.a
[OP
[1]] & 0xffff;
1772 trace_output (OP_REG
);
1779 trace_input ("mvfc", OP_REG_OUTPUT
, OP_CR
, OP_VOID
);
1780 State
.regs
[OP
[0]] = move_from_cr (OP
[1]);
1781 trace_output (OP_REG
);
1788 trace_input ("mvtacg", OP_REG
, OP_ACCUM
, OP_VOID
);
1789 State
.a
[OP
[1]] &= MASK32
;
1790 State
.a
[OP
[1]] |= (int64
)(State
.regs
[OP
[0]] & 0xff) << 32;
1791 trace_output (OP_ACCUM_REVERSE
);
1800 trace_input ("mvtachi", OP_REG
, OP_ACCUM
, OP_VOID
);
1801 tmp
= State
.a
[OP
[1]] & 0xffff;
1802 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]]) << 16 | tmp
) & MASK40
;
1803 trace_output (OP_ACCUM_REVERSE
);
1810 trace_input ("mvtaclo", OP_REG
, OP_ACCUM
, OP_VOID
);
1811 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]])) & MASK40
;
1812 trace_output (OP_ACCUM_REVERSE
);
1819 trace_input ("mvtc", OP_REG
, OP_CR_OUTPUT
, OP_VOID
);
1820 move_to_cr (OP
[1], State
.regs
[OP
[0]]);
1821 trace_output (OP_CR_REVERSE
);
1828 trace_input ("mvub", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1829 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] & 0xff;
1830 trace_output (OP_REG
);
1837 trace_input ("neg", OP_REG
, OP_VOID
, OP_VOID
);
1838 State
.regs
[OP
[0]] = 0 - State
.regs
[OP
[0]];
1839 trace_output (OP_REG
);
1848 trace_input ("neg", OP_ACCUM
, OP_VOID
, OP_VOID
);
1849 tmp
= -SEXT40(State
.a
[OP
[0]]);
1853 State
.a
[OP
[0]] = MAX32
;
1854 else if (tmp
< MIN32
)
1855 State
.a
[OP
[0]] = MIN32
;
1857 State
.a
[OP
[0]] = tmp
& MASK40
;
1860 State
.a
[OP
[0]] = tmp
& MASK40
;
1861 trace_output (OP_ACCUM
);
1869 trace_input ("nop", OP_VOID
, OP_VOID
, OP_VOID
);
1871 ins_type_counters
[ (int)State
.ins_type
]--; /* don't count nops as normal instructions */
1872 switch (State
.ins_type
)
1875 ins_type_counters
[ (int)INS_UNKNOWN
]++;
1878 case INS_LEFT_PARALLEL
:
1879 /* Don't count a parallel op that includes a NOP as a true parallel op */
1880 ins_type_counters
[ (int)INS_RIGHT_PARALLEL
]--;
1881 ins_type_counters
[ (int)INS_RIGHT
]++;
1882 ins_type_counters
[ (int)INS_LEFT_NOPS
]++;
1886 case INS_LEFT_COND_EXE
:
1887 ins_type_counters
[ (int)INS_LEFT_NOPS
]++;
1890 case INS_RIGHT_PARALLEL
:
1891 /* Don't count a parallel op that includes a NOP as a true parallel op */
1892 ins_type_counters
[ (int)INS_LEFT_PARALLEL
]--;
1893 ins_type_counters
[ (int)INS_LEFT
]++;
1894 ins_type_counters
[ (int)INS_RIGHT_NOPS
]++;
1898 case INS_RIGHT_COND_EXE
:
1899 ins_type_counters
[ (int)INS_RIGHT_NOPS
]++;
1903 trace_output (OP_VOID
);
1910 trace_input ("not", OP_REG
, OP_VOID
, OP_VOID
);
1911 State
.regs
[OP
[0]] = ~(State
.regs
[OP
[0]]);
1912 trace_output (OP_REG
);
1919 trace_input ("or", OP_REG
, OP_REG
, OP_VOID
);
1920 State
.regs
[OP
[0]] |= State
.regs
[OP
[1]];
1921 trace_output (OP_REG
);
1928 trace_input ("or3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
1929 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] | OP
[2];
1930 trace_output (OP_REG
);
1938 int shift
= SEXT3 (OP
[2]);
1940 trace_input ("rac", OP_DREG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
1943 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1944 "ERROR at PC 0x%x: instruction only valid for A0\n",
1946 State
.exception
= SIGILL
;
1949 State
.F1
= State
.F0
;
1950 tmp
= SEXT56 ((State
.a
[0] << 16) | (State
.a
[1] & 0xffff));
1956 tmp
>>= 16; /* look at bits 0:43 */
1957 if (tmp
> SEXT44 (SIGNED64 (0x0007fffffff)))
1959 State
.regs
[OP
[0]] = 0x7fff;
1960 State
.regs
[OP
[0]+1] = 0xffff;
1963 else if (tmp
< SEXT44 (SIGNED64 (0xfff80000000)))
1965 State
.regs
[OP
[0]] = 0x8000;
1966 State
.regs
[OP
[0]+1] = 0;
1971 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
1972 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
1975 trace_output (OP_DREG
);
1983 int shift
= SEXT3 (OP
[2]);
1985 trace_input ("rachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
1986 State
.F1
= State
.F0
;
1988 tmp
= SEXT40 (State
.a
[OP
[1]]) << shift
;
1990 tmp
= SEXT40 (State
.a
[OP
[1]]) >> -shift
;
1993 if (tmp
> SEXT44 (SIGNED64 (0x0007fffffff)))
1995 State
.regs
[OP
[0]] = 0x7fff;
1998 else if (tmp
< SEXT44 (SIGNED64 (0xfff80000000)))
2000 State
.regs
[OP
[0]] = 0x8000;
2005 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2008 trace_output (OP_REG
);
2015 trace_input ("rep", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2018 RPT_C
= State
.regs
[OP
[0]];
2022 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: rep with count=0 is illegal.\n");
2023 State
.exception
= SIGILL
;
2027 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: rep must include at least 4 instructions.\n");
2028 State
.exception
= SIGILL
;
2030 trace_output (OP_VOID
);
2037 trace_input ("repi", OP_CONSTANT16
, OP_CONSTANT16
, OP_VOID
);
2044 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: repi with count=0 is illegal.\n");
2045 State
.exception
= SIGILL
;
2049 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: repi must include at least 4 instructions.\n");
2050 State
.exception
= SIGILL
;
2052 trace_output (OP_VOID
);
2059 d10v_callback
->printf_filtered(d10v_callback
, "ERROR: rtd - NOT IMPLEMENTED\n");
2060 State
.exception
= SIGILL
;
2067 trace_input ("rte", OP_VOID
, OP_VOID
, OP_VOID
);
2068 move_to_cr (PSW_CR
, BPSW
);
2070 trace_output (OP_VOID
);
2079 trace_input ("sadd", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
2080 tmp
= SEXT40(State
.a
[OP
[0]]) + (SEXT40(State
.a
[OP
[1]]) >> 16);
2084 State
.a
[OP
[0]] = MAX32
;
2085 else if (tmp
< MIN32
)
2086 State
.a
[OP
[0]] = MIN32
;
2088 State
.a
[OP
[0]] = tmp
& MASK40
;
2091 State
.a
[OP
[0]] = tmp
& MASK40
;
2092 trace_output (OP_ACCUM
);
2099 trace_input ("setf0f", OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
2100 State
.regs
[OP
[0]] = (State
.F0
== 0) ? 1 : 0;
2101 trace_output (OP_REG
);
2108 trace_input ("setf0t", OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
2109 State
.regs
[OP
[0]] = (State
.F0
== 1) ? 1 : 0;
2110 trace_output (OP_REG
);
2117 trace_input ("sleep", OP_VOID
, OP_VOID
, OP_VOID
);
2119 trace_output (OP_VOID
);
2126 trace_input ("sll", OP_REG
, OP_REG
, OP_VOID
);
2127 State
.regs
[OP
[0]] <<= (State
.regs
[OP
[1]] & 0xf);
2128 trace_output (OP_REG
);
2136 trace_input ("sll", OP_ACCUM
, OP_REG
, OP_VOID
);
2137 if ((State
.regs
[OP
[1]] & 31) <= 16)
2138 tmp
= SEXT40 (State
.a
[OP
[0]]) << (State
.regs
[OP
[1]] & 31);
2141 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", State
.regs
[OP
[1]] & 31);
2142 State
.exception
= SIGILL
;
2149 State
.a
[OP
[0]] = MAX32
;
2150 else if (tmp
< 0xffffff80000000LL
)
2151 State
.a
[OP
[0]] = MIN32
;
2153 State
.a
[OP
[0]] = tmp
& MASK40
;
2156 State
.a
[OP
[0]] = tmp
& MASK40
;
2157 trace_output (OP_ACCUM
);
2164 trace_input ("slli", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2165 State
.regs
[OP
[0]] <<= OP
[1];
2166 trace_output (OP_REG
);
2178 trace_input ("slli", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2179 tmp
= SEXT40(State
.a
[OP
[0]]) << OP
[1];
2184 State
.a
[OP
[0]] = MAX32
;
2185 else if (tmp
< 0xffffff80000000LL
)
2186 State
.a
[OP
[0]] = MIN32
;
2188 State
.a
[OP
[0]] = tmp
& MASK40
;
2191 State
.a
[OP
[0]] = tmp
& MASK40
;
2192 trace_output (OP_ACCUM
);
2199 trace_input ("slx", OP_REG
, OP_FLAG
, OP_VOID
);
2200 State
.regs
[OP
[0]] = (State
.regs
[OP
[0]] << 1) | State
.F0
;
2201 trace_output (OP_REG
);
2208 trace_input ("sra", OP_REG
, OP_REG
, OP_VOID
);
2209 State
.regs
[OP
[0]] = ((int16
)(State
.regs
[OP
[0]])) >> (State
.regs
[OP
[1]] & 0xf);
2210 trace_output (OP_REG
);
2217 trace_input ("sra", OP_ACCUM
, OP_REG
, OP_VOID
);
2218 if ((State
.regs
[OP
[1]] & 31) <= 16)
2219 State
.a
[OP
[0]] = (SEXT40(State
.a
[OP
[0]]) >> (State
.regs
[OP
[1]] & 31)) & MASK40
;
2222 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", State
.regs
[OP
[1]] & 31);
2223 State
.exception
= SIGILL
;
2227 trace_output (OP_ACCUM
);
2234 trace_input ("srai", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2235 State
.regs
[OP
[0]] = ((int16
)(State
.regs
[OP
[0]])) >> OP
[1];
2236 trace_output (OP_REG
);
2246 trace_input ("srai", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2247 State
.a
[OP
[0]] = (SEXT40(State
.a
[OP
[0]]) >> OP
[1]) & MASK40
;
2248 trace_output (OP_ACCUM
);
2255 trace_input ("srl", OP_REG
, OP_REG
, OP_VOID
);
2256 State
.regs
[OP
[0]] >>= (State
.regs
[OP
[1]] & 0xf);
2257 trace_output (OP_REG
);
2264 trace_input ("srl", OP_ACCUM
, OP_REG
, OP_VOID
);
2265 if ((State
.regs
[OP
[1]] & 31) <= 16)
2266 State
.a
[OP
[0]] = (uint64
)((State
.a
[OP
[0]] & MASK40
) >> (State
.regs
[OP
[1]] & 31));
2269 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", State
.regs
[OP
[1]] & 31);
2270 State
.exception
= SIGILL
;
2274 trace_output (OP_ACCUM
);
2281 trace_input ("srli", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2282 State
.regs
[OP
[0]] >>= OP
[1];
2283 trace_output (OP_REG
);
2293 trace_input ("srli", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2294 State
.a
[OP
[0]] = (uint64
)(State
.a
[OP
[0]] & MASK40
) >> OP
[1];
2295 trace_output (OP_ACCUM
);
2304 trace_input ("srx", OP_REG
, OP_FLAG
, OP_VOID
);
2305 tmp
= State
.F0
<< 15;
2306 State
.regs
[OP
[0]] = (State
.regs
[OP
[0]] >> 1) | tmp
;
2307 trace_output (OP_REG
);
2314 trace_input ("st", OP_REG
, OP_MEMREF2
, OP_VOID
);
2315 SW (OP
[1] + State
.regs
[OP
[2]], State
.regs
[OP
[0]]);
2316 trace_output (OP_VOID
);
2323 trace_input ("st", OP_REG
, OP_MEMREF
, OP_VOID
);
2324 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2325 trace_output (OP_VOID
);
2332 trace_input ("st", OP_REG
, OP_PREDEC
, OP_VOID
);
2335 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2336 State
.exception
= SIGILL
;
2339 State
.regs
[OP
[1]] -= 2;
2340 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2341 trace_output (OP_VOID
);
2348 trace_input ("st", OP_REG
, OP_POSTINC
, OP_VOID
);
2349 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2350 INC_ADDR (State
.regs
[OP
[1]],2);
2351 trace_output (OP_VOID
);
2358 trace_input ("st", OP_REG
, OP_POSTDEC
, OP_VOID
);
2361 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot post-decrement register r15 (SP).\n");
2362 State
.exception
= SIGILL
;
2365 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2366 INC_ADDR (State
.regs
[OP
[1]],-2);
2367 trace_output (OP_VOID
);
2374 trace_input ("st2w", OP_DREG
, OP_MEMREF2
, OP_VOID
);
2375 SW (State
.regs
[OP
[2]]+OP
[1], State
.regs
[OP
[0]]);
2376 SW (State
.regs
[OP
[2]]+OP
[1]+2, State
.regs
[OP
[0]+1]);
2377 trace_output (OP_VOID
);
2384 trace_input ("st2w", OP_DREG
, OP_MEMREF
, OP_VOID
);
2385 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2386 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2387 trace_output (OP_VOID
);
2394 trace_input ("st2w", OP_DREG
, OP_PREDEC
, OP_VOID
);
2397 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2398 State
.exception
= SIGILL
;
2401 State
.regs
[OP
[1]] -= 4;
2402 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2403 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2404 trace_output (OP_VOID
);
2411 trace_input ("st2w", OP_DREG
, OP_POSTINC
, OP_VOID
);
2412 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2413 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2414 INC_ADDR (State
.regs
[OP
[1]],4);
2415 trace_output (OP_VOID
);
2422 trace_input ("st2w", OP_DREG
, OP_POSTDEC
, OP_VOID
);
2425 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot post-decrement register r15 (SP).\n");
2426 State
.exception
= SIGILL
;
2429 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2430 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2431 INC_ADDR (State
.regs
[OP
[1]],-4);
2432 trace_output (OP_VOID
);
2439 trace_input ("stb", OP_REG
, OP_MEMREF2
, OP_VOID
);
2440 SB (State
.regs
[OP
[2]]+OP
[1], State
.regs
[OP
[0]]);
2441 trace_output (OP_VOID
);
2448 trace_input ("stb", OP_REG
, OP_MEMREF
, OP_VOID
);
2449 SB (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2450 trace_output (OP_VOID
);
2457 trace_input ("stop", OP_VOID
, OP_VOID
, OP_VOID
);
2458 State
.exception
= SIG_D10V_STOP
;
2459 trace_output (OP_VOID
);
2468 trace_input ("sub", OP_REG
, OP_REG
, OP_VOID
);
2469 /* see ../common/sim-alu.h for a more extensive discussion on how to
2470 compute the carry/overflow bits. */
2471 tmp
= State
.regs
[OP
[0]] - State
.regs
[OP
[1]];
2472 State
.C
= ((uint16
) State
.regs
[OP
[0]] >= (uint16
) State
.regs
[OP
[1]]);
2473 State
.regs
[OP
[0]] = tmp
;
2474 trace_output (OP_REG
);
2483 trace_input ("sub", OP_ACCUM
, OP_DREG
, OP_VOID
);
2484 tmp
= SEXT40(State
.a
[OP
[0]]) - (SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1]);
2488 State
.a
[OP
[0]] = MAX32
;
2489 else if ( tmp
< MIN32
)
2490 State
.a
[OP
[0]] = MIN32
;
2492 State
.a
[OP
[0]] = tmp
& MASK40
;
2495 State
.a
[OP
[0]] = tmp
& MASK40
;
2497 trace_output (OP_ACCUM
);
2507 trace_input ("sub", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
2508 tmp
= SEXT40(State
.a
[OP
[0]]) - SEXT40(State
.a
[OP
[1]]);
2512 State
.a
[OP
[0]] = MAX32
;
2513 else if ( tmp
< MIN32
)
2514 State
.a
[OP
[0]] = MIN32
;
2516 State
.a
[OP
[0]] = tmp
& MASK40
;
2519 State
.a
[OP
[0]] = tmp
& MASK40
;
2521 trace_output (OP_ACCUM
);
2530 trace_input ("sub2w", OP_DREG
, OP_DREG
, OP_VOID
);
2531 a
= (uint32
)((State
.regs
[OP
[0]] << 16) | State
.regs
[OP
[0]+1]);
2532 b
= (uint32
)((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
2533 /* see ../common/sim-alu.h for a more extensive discussion on how to
2534 compute the carry/overflow bits */
2537 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2538 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2539 trace_output (OP_DREG
);
2548 trace_input ("subac3", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
2549 tmp
= SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]) - SEXT40 (State
.a
[OP
[2]]);
2550 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2551 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2552 trace_output (OP_DREG
);
2561 trace_input ("subac3", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
2562 tmp
= SEXT40(State
.a
[OP
[1]]) - SEXT40(State
.a
[OP
[2]]);
2563 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2564 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2565 trace_output (OP_DREG
);
2574 trace_input ("subac3s", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
2575 State
.F1
= State
.F0
;
2576 tmp
= SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]) - SEXT40(State
.a
[OP
[2]]);
2579 State
.regs
[OP
[0]] = 0x7fff;
2580 State
.regs
[OP
[0]+1] = 0xffff;
2583 else if (tmp
< MIN32
)
2585 State
.regs
[OP
[0]] = 0x8000;
2586 State
.regs
[OP
[0]+1] = 0;
2591 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2592 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2595 trace_output (OP_DREG
);
2604 trace_input ("subac3s", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
2605 State
.F1
= State
.F0
;
2606 tmp
= SEXT40(State
.a
[OP
[1]]) - SEXT40(State
.a
[OP
[2]]);
2609 State
.regs
[OP
[0]] = 0x7fff;
2610 State
.regs
[OP
[0]+1] = 0xffff;
2613 else if (tmp
< MIN32
)
2615 State
.regs
[OP
[0]] = 0x8000;
2616 State
.regs
[OP
[0]+1] = 0;
2621 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2622 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2625 trace_output (OP_DREG
);
2636 trace_input ("subi", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2637 /* see ../common/sim-alu.h for a more extensive discussion on how to
2638 compute the carry/overflow bits. */
2639 /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
2640 tmp
= ((unsigned)(unsigned16
) State
.regs
[OP
[0]]
2641 + (unsigned)(unsigned16
) ( - OP
[1]));
2642 State
.C
= (tmp
>= (1 << 16));
2643 State
.regs
[OP
[0]] = tmp
;
2644 trace_output (OP_REG
);
2651 trace_input ("trap", OP_CONSTANT4
, OP_VOID
, OP_VOID
);
2652 trace_output (OP_VOID
);
2657 #if (DEBUG & DEBUG_TRAP) == 0
2659 uint16 vec
= OP
[0] + TRAP_VECTOR_START
;
2661 move_to_cr (BPSW_CR
, PSW
);
2662 move_to_cr (PSW_CR
, PSW
& PSW_SM_BIT
);
2666 #else /* if debugging use trap to print registers */
2669 static int first_time
= 1;
2674 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Trap # PC ");
2675 for (i
= 0; i
< 16; i
++)
2676 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %sr%d", (i
> 9) ? "" : " ", i
);
2677 (*d10v_callback
->printf_filtered
) (d10v_callback
, " a0 a1 f0 f1 c\n");
2680 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Trap %2d 0x%.4x:", (int)OP
[0], (int)PC
);
2682 for (i
= 0; i
< 16; i
++)
2683 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %.4x", (int) State
.regs
[i
]);
2685 for (i
= 0; i
< 2; i
++)
2686 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %.2x%.8lx",
2687 ((int)(State
.a
[i
] >> 32) & 0xff),
2688 ((unsigned long)State
.a
[i
]) & 0xffffffff);
2690 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %d %d %d\n",
2691 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
2692 (*d10v_callback
->flush_stdout
) (d10v_callback
);
2696 case 15: /* new system call trap */
2697 /* Trap 15 is used for simulating low-level I/O */
2701 /* Registers passed to trap 0 */
2703 #define FUNC State.regs[4] /* function number */
2704 #define PARM1 State.regs[0] /* optional parm 1 */
2705 #define PARM2 State.regs[1] /* optional parm 2 */
2706 #define PARM3 State.regs[2] /* optional parm 3 */
2707 #define PARM4 State.regs[3] /* optional parm 3 */
2709 /* Registers set by trap 0 */
2711 #define RETVAL State.regs[0] /* return value */
2712 #define RETVAL_HIGH State.regs[0] /* return value */
2713 #define RETVAL_LOW State.regs[1] /* return value */
2714 #define RETERR State.regs[4] /* return error code */
2716 /* Turn a pointer in a register into a pointer into real memory. */
2718 #define MEMPTR(x) ((char *)(dmem_addr(x)))
2722 #if !defined(__GO32__) && !defined(_WIN32)
2725 trace_input ("<fork>", OP_VOID
, OP_VOID
, OP_VOID
);
2726 trace_output (OP_R0
);
2730 trace_input ("<getpid>", OP_VOID
, OP_VOID
, OP_VOID
);
2732 trace_output (OP_R0
);
2736 trace_input ("<kill>", OP_REG
, OP_REG
, OP_VOID
);
2737 if (PARM1
== getpid ())
2739 trace_output (OP_VOID
);
2740 State
.exception
= PARM2
;
2748 case 1: os_sig
= SIGHUP
; break;
2751 case 2: os_sig
= SIGINT
; break;
2754 case 3: os_sig
= SIGQUIT
; break;
2757 case 4: os_sig
= SIGILL
; break;
2760 case 5: os_sig
= SIGTRAP
; break;
2763 case 6: os_sig
= SIGABRT
; break;
2764 #elif defined(SIGIOT)
2765 case 6: os_sig
= SIGIOT
; break;
2768 case 7: os_sig
= SIGEMT
; break;
2771 case 8: os_sig
= SIGFPE
; break;
2774 case 9: os_sig
= SIGKILL
; break;
2777 case 10: os_sig
= SIGBUS
; break;
2780 case 11: os_sig
= SIGSEGV
; break;
2783 case 12: os_sig
= SIGSYS
; break;
2786 case 13: os_sig
= SIGPIPE
; break;
2789 case 14: os_sig
= SIGALRM
; break;
2792 case 15: os_sig
= SIGTERM
; break;
2795 case 16: os_sig
= SIGURG
; break;
2798 case 17: os_sig
= SIGSTOP
; break;
2801 case 18: os_sig
= SIGTSTP
; break;
2804 case 19: os_sig
= SIGCONT
; break;
2807 case 20: os_sig
= SIGCHLD
; break;
2808 #elif defined(SIGCLD)
2809 case 20: os_sig
= SIGCLD
; break;
2812 case 21: os_sig
= SIGTTIN
; break;
2815 case 22: os_sig
= SIGTTOU
; break;
2818 case 23: os_sig
= SIGIO
; break;
2819 #elif defined (SIGPOLL)
2820 case 23: os_sig
= SIGPOLL
; break;
2823 case 24: os_sig
= SIGXCPU
; break;
2826 case 25: os_sig
= SIGXFSZ
; break;
2829 case 26: os_sig
= SIGVTALRM
; break;
2832 case 27: os_sig
= SIGPROF
; break;
2835 case 28: os_sig
= SIGWINCH
; break;
2838 case 29: os_sig
= SIGLOST
; break;
2841 case 30: os_sig
= SIGUSR1
; break;
2844 case 31: os_sig
= SIGUSR2
; break;
2850 trace_output (OP_VOID
);
2851 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Unknown signal %d\n", PARM2
);
2852 (*d10v_callback
->flush_stdout
) (d10v_callback
);
2853 State
.exception
= SIGILL
;
2857 RETVAL
= kill (PARM1
, PARM2
);
2858 trace_output (OP_R0
);
2864 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
),
2865 (char **)MEMPTR (PARM3
));
2866 trace_input ("<execve>", OP_R0
, OP_R1
, OP_R2
);
2867 trace_output (OP_R0
);
2872 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
), NULL
);
2873 trace_input ("<execv>", OP_R0
, OP_R1
, OP_VOID
);
2874 trace_output (OP_R0
);
2884 RETVAL
= pipe (host_fd
);
2885 SW (buf
, host_fd
[0]);
2886 buf
+= sizeof(uint16
);
2887 SW (buf
, host_fd
[1]);
2888 trace_input ("<pipe>", OP_R0
, OP_VOID
, OP_VOID
);
2889 trace_output (OP_R0
);
2898 RETVAL
= wait (&status
);
2901 trace_input ("<wait>", OP_R0
, OP_VOID
, OP_VOID
);
2902 trace_output (OP_R0
);
2908 trace_input ("<getpid>", OP_VOID
, OP_VOID
, OP_VOID
);
2910 trace_output (OP_R0
);
2914 trace_input ("<kill>", OP_REG
, OP_REG
, OP_VOID
);
2915 trace_output (OP_VOID
);
2916 State
.exception
= PARM2
;
2921 RETVAL
= d10v_callback
->read (d10v_callback
, PARM1
, MEMPTR (PARM2
),
2923 trace_input ("<read>", OP_R0
, OP_R1
, OP_R2
);
2924 trace_output (OP_R0
);
2929 RETVAL
= (int)d10v_callback
->write_stdout (d10v_callback
,
2930 MEMPTR (PARM2
), PARM3
);
2932 RETVAL
= (int)d10v_callback
->write (d10v_callback
, PARM1
,
2933 MEMPTR (PARM2
), PARM3
);
2934 trace_input ("<write>", OP_R0
, OP_R1
, OP_R2
);
2935 trace_output (OP_R0
);
2940 unsigned long ret
= d10v_callback
->lseek (d10v_callback
, PARM1
,
2941 (((unsigned long)PARM2
) << 16) || (unsigned long)PARM3
,
2943 RETVAL_HIGH
= ret
>> 16;
2944 RETVAL_LOW
= ret
& 0xffff;
2946 trace_input ("<lseek>", OP_R0
, OP_R1
, OP_R2
);
2947 trace_output (OP_R0R1
);
2951 RETVAL
= d10v_callback
->close (d10v_callback
, PARM1
);
2952 trace_input ("<close>", OP_R0
, OP_VOID
, OP_VOID
);
2953 trace_output (OP_R0
);
2957 RETVAL
= d10v_callback
->open (d10v_callback
, MEMPTR (PARM1
), PARM2
);
2958 trace_input ("<open>", OP_R0
, OP_R1
, OP_R2
);
2959 trace_output (OP_R0
);
2960 trace_input ("<open>", OP_R0
, OP_R1
, OP_R2
);
2961 trace_output (OP_R0
);
2965 State
.exception
= SIG_D10V_EXIT
;
2966 trace_input ("<exit>", OP_R0
, OP_VOID
, OP_VOID
);
2967 trace_output (OP_VOID
);
2971 /* stat system call */
2973 struct stat host_stat
;
2976 RETVAL
= stat (MEMPTR (PARM1
), &host_stat
);
2980 /* The hard-coded offsets and sizes were determined by using
2981 * the D10V compiler on a test program that used struct stat.
2983 SW (buf
, host_stat
.st_dev
);
2984 SW (buf
+2, host_stat
.st_ino
);
2985 SW (buf
+4, host_stat
.st_mode
);
2986 SW (buf
+6, host_stat
.st_nlink
);
2987 SW (buf
+8, host_stat
.st_uid
);
2988 SW (buf
+10, host_stat
.st_gid
);
2989 SW (buf
+12, host_stat
.st_rdev
);
2990 SLW (buf
+16, host_stat
.st_size
);
2991 SLW (buf
+20, host_stat
.st_atime
);
2992 SLW (buf
+28, host_stat
.st_mtime
);
2993 SLW (buf
+36, host_stat
.st_ctime
);
2995 trace_input ("<stat>", OP_R0
, OP_R1
, OP_VOID
);
2996 trace_output (OP_R0
);
3000 RETVAL
= chown (MEMPTR (PARM1
), PARM2
, PARM3
);
3001 trace_input ("<chown>", OP_R0
, OP_R1
, OP_R2
);
3002 trace_output (OP_R0
);
3006 RETVAL
= chmod (MEMPTR (PARM1
), PARM2
);
3007 trace_input ("<chmod>", OP_R0
, OP_R1
, OP_R2
);
3008 trace_output (OP_R0
);
3013 /* Cast the second argument to void *, to avoid type mismatch
3014 if a prototype is present. */
3015 RETVAL
= utime (MEMPTR (PARM1
), (void *) MEMPTR (PARM2
));
3016 trace_input ("<utime>", OP_R0
, OP_R1
, OP_R2
);
3017 trace_output (OP_R0
);
3024 unsigned long ret
= time (PARM1
? MEMPTR (PARM1
) : NULL
);
3025 RETVAL_HIGH
= ret
>> 16;
3026 RETVAL_LOW
= ret
& 0xffff;
3028 trace_input ("<time>", OP_R0
, OP_R1
, OP_R2
);
3029 trace_output (OP_R0R1
);
3034 d10v_callback
->error (d10v_callback
, "Unknown syscall %d", FUNC
);
3036 RETERR
= (RETVAL
== (uint16
) -1) ? d10v_callback
->get_errno(d10v_callback
) : 0;
3046 trace_input ("tst0i", OP_REG
, OP_CONSTANT16
, OP_VOID
);
3047 State
.F1
= State
.F0
;
3048 State
.F0
= (State
.regs
[OP
[0]] & OP
[1]) ? 1 : 0;
3049 trace_output (OP_FLAG
);
3056 trace_input ("tst1i", OP_REG
, OP_CONSTANT16
, OP_VOID
);
3057 State
.F1
= State
.F0
;
3058 State
.F0
= (~(State
.regs
[OP
[0]]) & OP
[1]) ? 1 : 0;
3059 trace_output (OP_FLAG
);
3066 trace_input ("wait", OP_VOID
, OP_VOID
, OP_VOID
);
3068 trace_output (OP_VOID
);
3075 trace_input ("xor", OP_REG
, OP_REG
, OP_VOID
);
3076 State
.regs
[OP
[0]] ^= State
.regs
[OP
[1]];
3077 trace_output (OP_REG
);
3084 trace_input ("xor3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
3085 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] ^ OP
[2];
3086 trace_output (OP_REG
);
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