2 // Mitsubishi Electric Corp. D30V Simulator.
3 // Copyright (C) 1997, Free Software Foundation, Inc.
4 // Contributed by Cygnus Solutions Inc.
6 // This file is part of GDB, the GNU debugger.
8 // This program is free software; you can redistribute it and/or modify
9 // it under the terms of the GNU General Public License as published by
10 // the Free Software Foundation; either version 2 of the License, or
11 // (at your option) any later version.
13 // This program is distributed in the hope that it will be useful,
14 // but WITHOUT ANY WARRANTY; without even the implied warranty of
15 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 // GNU General Public License for more details.
18 // You should have received a copy of the GNU General Public License
19 // along with this program; if not, write to the Free Software
20 // Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 define( _BRA, `1.*,CCC,000')
25 define( _LOGIC, `1.*,CCC,001')
26 define( _IMEM, `1.*,CCC,010')
27 define( _IALU1, `1.*,CCC,100')
28 define(_IALU2, `1.*,CCC,101')
32 define(_IMM6, `6.IMM_6S')
33 define(_IMM12, `12.IMM_12S')
34 define(_IMM18, `18.IMM_18S')
35 define(_IMM32, `6.IMM_6L,*,000,8.IMM_8L,00,18.IMM_18L')
39 // The following is called when ever an illegal instruction is
42 sim_io_eprintf (sd, "illegal instruction at 0x%lx\n", (long) cia);
43 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
45 // The following is called when ever an instruction in the wrong
46 // slot is encountered.
47 ::internal::wrong_slot
48 sim_io_eprintf (sd, "wrong slot at 0x%lx\n", (long) cia);
49 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
53 // Something illegal that can be used to contact the simulator emul
55 define(_EMUL, `1.*,CCC,111')
57 void::function::do_emul:int imm
58 /* temp hack - later replace with real interface */
60 param1 = 2, param2, param3, param4
65 sim_engine_abort (SD, CPU, cia, "UNIX call emulation unsupported");
69 /* Trap 1 - prints a string */
71 address_word str = GPR[param1];
74 chr = MEM (unsigned, str, 1);
75 if (chr == '\0') break;
76 sim_io_write_stdout (sd, &chr, sizeof chr);
82 /* Trap 3 - writes a character */
84 char chr = GPR[param1];
85 sim_io_write_stdout (sd, &chr, sizeof chr);
89 /* Trap 4 exits with status in [param1] */
91 sim_engine_halt (SD, CPU, NULL, cia, sim_exited, GPR[param1]);
95 /* Trap 5 breakpoints. If the breakpoint system knows about this, it
96 won't return. Otherwise, we fall through to treat this as an
97 unknown instruction. */
99 sim_handle_breakpoint (SD, CPU, cia);
100 /* Fall through to default case.*/
103 sim_engine_abort (SD, CPU, cia, "Unknown monitor call %d", imm);
106 _EMUL,00000,00,6.*,6.*,IMM_6S:EMUL:short,emul:iu,mu:EMUL
109 _BRA,00000,00,6.**,6.**,_IMM32:BRA:long:iu,mu:EMUL long
115 _IALU1,01000,00,6.RA,6.RB,6.**:IALU1:short:iu,mu:ABS
117 WRITE32_QUEUE (Ra, abs(Rb));
123 void::function::do_add:unsigned32 *ra, unsigned32 rb, unsigned32 imm
128 _IALU1,00000,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:ADD
129 "add r<RA>, r<RB>, r<RC>"
130 do_add (_SD, Ra, Rb, Rc);
131 _IALU1,00000,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:ADD imm
132 "add r<RA>, r<RB>, <imm>"
133 do_add (_SD, Ra, Rb, imm);
134 _IALU1,00000,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:ADD imm long
135 "add r<RA>, r<RB>, <imm>"
136 do_add (_SD, Ra, Rb, imm);
142 void::function::do_add2h:signed32 *ra, signed32 rb, signed32 imm
143 unsigned16 ah2 = VH2_4(rb) + VH2_4(imm);
144 unsigned16 al2 = VL2_4(rb) + VL2_4(imm);
145 WRITE32_QUEUE (ra, (ah2 << 16) | al2);
147 _IALU1,00001,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:ADD2H
148 "add2h r<RA>, r<RB>, r<RC>"
149 do_add2h (_SD, Ra, Rb, Rc);
150 _IALU1,00001,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:ADD2H imm
151 "add2h r<RA>, r<RB>, <imm>"
152 do_add2h (_SD, Ra, Rb, immHL);
153 _IALU1,00001,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:ADD2H imm long
154 "add2h r<RA>, r<RB>, <imm>"
155 do_add2h (_SD, Ra, Rb, imm);
161 void::function::do_addc:unsigned32 *ra, unsigned32 rb, unsigned32 imm
163 ALU_ADDC_C(imm, ALU_CARRY);
166 _IALU1,00100,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:ADDC
167 "addc r<RA>, r<RB>, r<RC>"
168 do_addc (_SD, Ra, Rb, Rc);
169 _IALU1,00100,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:ADDC imm
170 "addc r<RA>, r<RB>, <imm>"
171 do_addc (_SD, Ra, Rb, imm);
172 _IALU1,00100,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:ADDC imm long
173 "addc r<RA>, r<RB>, <imm>"
174 do_addc (_SD, Ra, Rb, imm);
180 void::function::do_addh_ppp:int ppp, unsigned32 *ra, unsigned32 rb, unsigned32 src
184 ALU16_BEGIN(VL2_4(rb));
185 ALU16_ADDC(VL2_4(src));
191 ALU16_BEGIN(VL2_4(rb));
192 ALU16_ADDC(VH2_4(src));
198 ALU16_BEGIN(VH2_4(rb));
199 ALU16_ADDC(VL2_4(src));
205 ALU16_BEGIN(VH2_4(rb));
206 ALU16_ADDC(VH2_4(src));
212 ALU16_BEGIN(VL2_4(rb));
213 ALU16_ADDC(VL2_4(src));
219 ALU16_BEGIN(VL2_4(rb));
220 ALU16_ADDC(VH2_4(src));
226 ALU16_BEGIN(VH2_4(rb));
227 ALU16_ADDC(VL2_4(src));
233 ALU16_BEGIN(VH2_4(rb));
234 ALU16_ADDC(VH2_4(src));
239 sim_engine_abort (SD, CPU, cia, "do_addh_ppp - internal error - bad switch");
244 case 0x0: return "lll";
245 case 0x1: return "llh";
246 case 0x2: return "lhl";
247 case 0x3: return "lhh";
248 case 0x4: return "hll";
249 case 0x5: return "hlh";
250 case 0x6: return "hhl";
251 case 0x7: return "hhh";
255 _IALU1,10,ppp,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:ADDHppp
256 "addh%s<ppp> r<RA>, r<RB>, r<RC>"
257 do_addh_ppp(_SD, ppp, Ra, Rb, Rc);
258 _IALU1,10,ppp,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:ADDHppp imm
259 "addh%s<ppp> r<RA>, r<RB>, <imm>"
260 do_addh_ppp(_SD, ppp, Ra, Rb, immHL);
261 _IALU1,10,ppp,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:ADDHppp imm long
262 "addh%s<ppp> r<RA>, r<RB>, <imm>"
263 do_addh_ppp(_SD, ppp, Ra, Rb, imm);
269 void::function::do_adds:unsigned32 *ra, unsigned32 rb, unsigned32 imm
271 ALU_ADDC(EXTRACTED32(imm, 0, 0));
274 _IALU1,00110,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:ADDS
275 "adds r<RA>, r<RB>, r<RC>"
276 do_adds (_SD, Ra, Rb, Rc);
277 _IALU1,00110,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:ADDS imm
278 "adds r<RA>, r<RB>, <imm>"
279 do_adds (_SD, Ra, Rb, imm);
280 _IALU1,00110,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:ADDS imm long
281 "adds r<RA>, r<RB>, <imm>"
282 do_adds (_SD, Ra, Rb, imm);
288 void::function::do_adds2h:unsigned32 *ra, unsigned32 rb, unsigned32 immHL
289 unsigned16 high = VH2_4(rb) + EXTRACTED32(immHL, 0, 0);
290 unsigned16 low = VL2_4(rb) + EXTRACTED32(immHL, 16, 16);
291 WRITE32_QUEUE (ra, (high << 16) | low);
293 _IALU1,00111,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:ADDS2H
294 "adds2h r<RA>, r<RB>, r<RC>"
295 do_adds2h (_SD, Ra, Rb, Rc);
296 _IALU1,00111,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:ADDS2H imm
297 "adds2h r<RA>, r<RB>, <imm>"
298 do_adds2h (_SD, Ra, Rb, immHL);
299 _IALU1,00111,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:ADDS2H imm long
300 "adds2h r<RA>, r<RB>, <imm>"
301 do_adds2h (_SD, Ra, Rb, imm);
307 _LOGIC,11000,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:AND
308 "and r<RA>, r<RB>, r<RC>"
309 WRITE32_QUEUE (Ra, Rb & Rc);
310 _LOGIC,11000,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:AND imm
311 "and r<RA>, r<RB>, <imm>"
312 WRITE32_QUEUE (Ra, Rb & imm);
313 _LOGIC,11000,10,6.RA,6.RB,_IMM32:LOGIC:long:iu,mu:AND imm long
314 "and r<RA>, r<RB>, <imm>"
315 WRITE32_QUEUE (Ra, Rb & imm);
320 _LOGIC,01000,00,***,3.FA,***,3.FB,***,3.FC:LOGIC:short:iu,mu:Logical AND Flags
321 "andfg f<FA>, f<FB>, f<FC>"
322 PSW_FLAG_SET_QUEUE(FA, PSW_FLAG_VAL(FB) & PSW_FLAG_VAL(FC));
323 _LOGIC,01000,10,***,3.FA,***,3.FB,_IMM6:LOGIC:short:iu,mu:Logical AND Flags imm
324 "andfg f<FA>, f<FB>, <imm_6>"
325 PSW_FLAG_SET_QUEUE(FA, PSW_FLAG_VAL(FB) & (imm_6 & 1));
331 void::function::do_avg:unsigned32 *ra, unsigned32 rb, unsigned32 imm
332 WRITE32_QUEUE (ra, ((signed64)(signed32)rb + (signed64)(signed32)imm + 1) >> 1);
334 _IALU1,01010,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:AVG
335 "avg r<RA>, r<RB>, r<RC>"
336 do_avg (_SD, Ra, Rb, Rc);
337 _IALU1,01010,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:AVG imm
338 "avg r<RA>, r<RB>, <imm>"
339 do_avg (_SD, Ra, Rb, imm);
340 _IALU1,01010,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:AVG imm long
341 "avg r<RA>, r<RB>, <imm>"
342 do_avg (_SD, Ra, Rb, imm);
348 void::function::do_avg2h:unsigned32 *ra, unsigned32 rb, unsigned32 imm
349 unsigned16 high = ((signed32)(signed16)VH2_4(rb) + (signed32)(signed16)VH2_4(imm) + 1) >> 1;
350 unsigned16 low = ((signed32)(signed16)VL2_4(rb) + (signed32)(signed16)VL2_4(imm) + 1) >> 1;
351 WRITE32_QUEUE (ra, (high << 16) | low);
353 _IALU1,01011,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:AVG2H
354 "avg2h r<RA>, r<RB>, r<RC>"
355 do_avg2h (_SD, Ra, Rb, Rc);
356 _IALU1,01011,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:AVG2H imm
357 "avg2h r<RA>, r<RB>, <imm>"
358 do_avg2h (_SD, Ra, Rb, immHL);
359 _IALU1,01011,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:AVG2H imm long
360 "avg2h r<RA>, r<RB>, <imm>"
361 do_avg2h (_SD, Ra, Rb, imm);
367 _LOGIC,00011,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:BCLR
368 "bclr r<RA>, r<RB>, r<RC>"
369 WRITE32_QUEUE(Ra, Rb & ~BIT32((Rc) % 32));
370 _LOGIC,00011,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:BCLR imm
371 "bclr r<RA>, r<RB>, <imm>"
372 WRITE32_QUEUE(Ra, Rb & ~BIT32((imm) % 32));
378 _LOGIC,00001,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:BNOT
379 "bnot r<RA>, r<RB>, r<RC>"
380 WRITE32_QUEUE (Ra, Rb ^ BIT32((Rc) % 32));
381 _LOGIC,00001,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:BNOT imm
382 "bnot r<RA>, r<RB>, <imm>"
383 WRITE32_QUEUE (Ra, Rb ^ BIT32((imm) % 32));
389 _BRA,00000,00,6.**,6.**,6.RC:BRA:short:mu:BRA
392 _BRA,00000,10,_IMM18:BRA:short:mu:BRA imm
395 _BRA,00000,10,6.**,6.**,_IMM32:BRA:long:mu:BRA imm long
403 _BRA,00100,01,6.RA,6.**,6.RC:BRA:short:mu:BRATNZ
407 _BRA,00100,11,6.RA,_IMM12:BRA:short:mu:BRATNZ imm
411 _BRA,00100,11,6.RA,6.**,_IMM32:BRA:long:mu:BRATNZ imm long
420 _BRA,00100,00,6.RA,6.**,6.RC:BRA:short:mu:BRATZR
424 _BRA,00100,10,6.RA,_IMM12:BRA:short:mu:BRATZR imm
428 _BRA,00100,10,6.RA,6.**,_IMM32:BRA:long:mu:BRATZR imm long
437 _LOGIC,00010,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:BSET
438 "bset r<RA>, r<RB>, r<RC>"
439 WRITE32_QUEUE (Ra, Rb | BIT32((Rc) % 32));
440 _LOGIC,00010,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:BSET imm
441 "bset r<RA>, r<RB>, <imm>"
442 WRITE32_QUEUE (Ra, Rb | BIT32((imm) % 32));
448 _BRA,00010,00,6.**,6.**,6.RC:BRA:short:mu:BSR
450 if (cia == RPT_E && PSW_VAL (PSW_RP))
451 WRITE32_QUEUE (&GPR[62], RPT_S);
453 WRITE32_QUEUE (&GPR[62], cia + 8);
456 TRACE_ACTION |= TRACE_ACTION_CALL;
457 _BRA,00010,10,_IMM18:BRA:short:mu:BSR imm
459 if (cia == RPT_E && PSW_VAL (PSW_RP))
460 WRITE32_QUEUE (&GPR[62], RPT_S);
462 WRITE32_QUEUE (&GPR[62], cia + 8);
465 TRACE_ACTION |= TRACE_ACTION_CALL;
466 _BRA,00010,10,6.**,6.**,_IMM32:BRA:long:mu:BSR imm long
468 if (cia == RPT_E && PSW_VAL (PSW_RP))
469 WRITE32_QUEUE (&GPR[62], RPT_S);
471 WRITE32_QUEUE (&GPR[62], cia + 8);
474 TRACE_ACTION |= TRACE_ACTION_CALL;
479 _BRA,00110,01,6.RA,6.**,6.RC:BRA:short:mu:BSRTNZ
482 if (cia == RPT_E && PSW_VAL (PSW_RP))
483 WRITE32_QUEUE (&GPR[62], RPT_S);
485 WRITE32_QUEUE (&GPR[62], cia + 8);
488 TRACE_ACTION |= TRACE_ACTION_CALL;
491 _BRA,00110,11,6.RA,_IMM12:BRA:short:mu:BSRTNZ imm
494 if (cia == RPT_E && PSW_VAL (PSW_RP))
495 WRITE32_QUEUE (&GPR[62], RPT_S);
497 WRITE32_QUEUE (&GPR[62], cia + 8);
500 TRACE_ACTION |= TRACE_ACTION_CALL;
503 _BRA,00110,11,6.RA,6.**,_IMM32:BRA:long:mu:BSRTNZ imm long
506 if (cia == RPT_E && PSW_VAL (PSW_RP))
507 WRITE32_QUEUE (&GPR[62], RPT_S);
509 WRITE32_QUEUE (&GPR[62], cia + 8);
512 TRACE_ACTION |= TRACE_ACTION_CALL;
518 _BRA,00110,00,6.RA,6.**,6.RC:BRA:short:mu:BSRTZR
521 if (cia == RPT_E && PSW_VAL (PSW_RP))
522 WRITE32_QUEUE (&GPR[62], RPT_S);
524 WRITE32_QUEUE (&GPR[62], cia + 8);
527 TRACE_ACTION |= TRACE_ACTION_CALL;
530 _BRA,00110,10,6.RA,_IMM12:BRA:short:mu:BSRTZR imm
533 if (cia == RPT_E && PSW_VAL (PSW_RP))
534 WRITE32_QUEUE (&GPR[62], RPT_S);
536 WRITE32_QUEUE (&GPR[62], cia + 8);
539 TRACE_ACTION |= TRACE_ACTION_CALL;
542 _BRA,00110,10,6.RA,6.**,_IMM32:BRA:long:mu:BSRTZR imm long
545 if (cia == RPT_E && PSW_VAL (PSW_RP))
546 WRITE32_QUEUE (&GPR[62], RPT_S);
548 WRITE32_QUEUE (&GPR[62], cia + 8);
551 TRACE_ACTION |= TRACE_ACTION_CALL;
557 _LOGIC,00000,00,***,3.FA,6.RB,6.RC:LOGIC:short:iu,mu:BTST
558 "btst f<FA>, r<RB>, r<RC>"
560 PSW_FLAG_SET_QUEUE(FA, MASKED32(Rb, bit, bit));
561 _LOGIC,00000,10,***,3.FA,6.RB,_IMM6:LOGIC:short:iu,mu:BTST imm
562 "btst f<FA>, r<RB>, <imm>"
564 PSW_FLAG_SET_QUEUE(FA, MASKED32(Rb, bit, bit));
570 void::function::do_cmp_cc:int cc, int fa, signed32 rb, signed32 rc
592 value = ((rb >= 0) && (rc >= 0));
595 value = ((rb < 0) && (rc < 0));
598 sim_engine_abort (SD, CPU, cia, "do_cmp_cc - internal error - bad switch (%d)", cc);
600 PSW_FLAG_SET_QUEUE(fa, value);
616 _LOGIC,01100,00,ccc,3.FA,6.RB,6.RC:LOGIC:short:iu,mu:CMPcc
617 "cmp%s<ccc> f<FA>, r<RB>, r<RC>"
618 do_cmp_cc(_SD, ccc, FA, Rb, Rc);
619 _LOGIC,01100,10,ccc,3.FA,6.RB,_IMM6:LOGIC:short:iu,mu:CMPcc imm
620 "cmp%s<ccc> f<FA>, r<RB>, <imm>"
621 do_cmp_cc(_SD, ccc, FA, Rb, imm);
622 _LOGIC,01100,10,ccc,3.FA,6.RB,_IMM32:LOGIC:long:iu,mu:CMPcc imm long
623 "cmp%s<ccc> f<FA>, r<RB>, <imm>"
624 do_cmp_cc(_SD, ccc, FA, Rb, imm);
630 void::function::do_cmpu_cc:int cc, int fa, unsigned32 rb, unsigned32 rc
646 sim_engine_abort (SD, CPU, cia, "do_cmpu_cc - internal error - bad switch (%d)", cc);
648 PSW_FLAG_SET_QUEUE(fa, value);
650 _LOGIC,01101,00,ccc,3.FA,6.RB,6.RC:LOGIC:short:iu,mu:CMPUcc
651 "cmpu%s<ccc> f<FA>, r<RB>, r<RC>"
652 do_cmpu_cc(_SD, ccc, FA, Rb, Rc);
653 _LOGIC,01101,10,ccc,3.FA,6.RB,_IMM6:LOGIC:short:iu,mu:CMPUcc imm
654 "cmpu%s<ccc> f<FA>, r<RB>, <imm>"
655 do_cmpu_cc(_SD, ccc, FA, Rb, imm_6u);
656 _LOGIC,01101,10,ccc,3.FA,6.RB,_IMM32:LOGIC:long:iu,mu:CMPUcc imm long
657 "cmpu%s<ccc> f<FA>, r<RB>, <imm>"
658 do_cmpu_cc(_SD, ccc, FA, Rb, imm);
664 void::function::do_dbra:address_word pcdisp, unsigned32 ra
665 PSW_SET_QUEUE (PSW_RP, 1);
666 WRITE32_QUEUE (&RPT_C, 1);
667 WRITE32_QUEUE (&RPT_S, cia + pcdisp);
668 WRITE32_QUEUE (&RPT_E, cia + (ra & ~0x7));
670 _BRA,10000,00,6.RA,6.**,6.RC:BRA:short:mu:DBRA
672 do_dbra(_SD, pcdisp, val_Ra);
673 _BRA,10000,10,6.RA,_IMM12:BRA:short:mu:DBRA imm
674 "dbra r<RA>, <pcdisp>"
675 do_dbra(_SD, pcdisp, val_Ra);
676 _BRA,10000,10,6.RA,6.**,_IMM32:BRA:long:mu:DBRA imm long
677 "dbra r<RA>, <pcdisp>"
678 do_dbra(_SD, pcdisp, val_Ra);
684 void::function::do_dbrai:address_word pcdisp, unsigned32 imm
685 PSW_SET_QUEUE (PSW_RP, 1);
686 WRITE32_QUEUE (&RPT_C, 1);
687 WRITE32_QUEUE (&RPT_S, cia + pcdisp);
688 WRITE32_QUEUE (&RPT_E, cia + (imm << 3));
690 _BRA,10100,00,6.IMM_6,6.**,6.RC:BRA:short:mu:DBRAI
691 "dbrai <IMM_6>, r<RC>"
692 do_dbrai(_SD, pcdisp, IMM_6);
693 _BRA,10100,10,6.IMM_6,_IMM12:BRA:short:mu:DBRAI imm
694 "dbrai <IMM_6>, <pcdisp>"
695 do_dbrai(_SD, pcdisp, IMM_6);
696 _BRA,10100,10,6.IMM_6,6.**,_IMM32:BRA:long:mu:DBRAI imm long
697 "dbrai <IMM_6>, <pcdisp>"
698 do_dbrai(_SD, pcdisp, IMM_6);
704 void::function::do_dbsr:address_word pcdisp, unsigned32 ra
705 PSW_SET_QUEUE (PSW_RP, 1);
706 WRITE32_QUEUE (&RPT_C, 1);
707 WRITE32_QUEUE (&RPT_S, cia + pcdisp);
708 WRITE32_QUEUE (&RPT_E, cia + ra);
709 WRITE32_QUEUE (&GPR[62], cia + ra + 8);
711 _BRA,10010,00,6.RA,6.**,6.RC:BRA:short:mu:DBSR
713 do_dbsr(_SD, pcdisp, val_Ra);
714 _BRA,10010,10,6.RA,_IMM12:BRA:short:mu:DBSR imm
715 "dbsr r<RA>, <pcdisp>"
716 do_dbsr(_SD, pcdisp, val_Ra);
717 _BRA,10010,10,6.RA,6.**,_IMM32:BRA:long:mu:DBSR imm long
718 "dbsr r<RA>, <pcdisp>"
719 do_dbsr(_SD, pcdisp, val_Ra);
725 void::function::do_dbsri:address_word pcdisp, unsigned32 imm
726 PSW_SET_QUEUE (PSW_RP, 1);
727 WRITE32_QUEUE (&RPT_C, 1);
728 WRITE32_QUEUE (&RPT_S, cia + pcdisp);
729 WRITE32_QUEUE (&RPT_E, cia + (imm << 3));
730 WRITE32_QUEUE (&GPR[62], cia + (imm << 3) + 8);
732 _BRA,10110,00,6.IMM_6,6.**,6.RC:BRA:short:mu:DBSRI
733 "dbsri <IMM_6>, r<RC>"
734 do_dbsri(_SD, pcdisp, IMM_6);
735 _BRA,10110,10,6.IMM_6,_IMM12:BRA:short:mu:DBSRI imm
736 "dbsri <IMM_6>, <pcdisp>"
737 do_dbsri(_SD, pcdisp, IMM_6);
738 _BRA,10110,10,6.IMM_6,6.**,_IMM32:BRA:long:mu:DBSRI imm long
739 "dbsri <IMM_6>, <pcdisp>"
740 do_dbsri(_SD, pcdisp, IMM_6);
747 _BRA,01011,00,6.**,6.**,6.**:BRA:short:mu:DBT
749 if (cia == RPT_E && PSW_VAL (PSW_RP))
751 WRITE32_QUEUE (&DPC, RPT_S);
756 WRITE32_QUEUE (&DPC, cia + 8);
758 nia = 0xfffff120; /* debug_trap_address */
762 void::function::do_djmp:address_word pcdisp, unsigned32 ra
763 PSW_SET_QUEUE (PSW_RP, 1);
764 WRITE32_QUEUE (&RPT_C, 1);
765 WRITE32_QUEUE (&RPT_S, pcdisp);
766 WRITE32_QUEUE (&RPT_E, cia + (ra & ~0x7));
768 _BRA,10001,00,6.RA,6.**,6.RC:BRA:short:mu:DJMP
770 do_djmp(_SD, pcdisp, val_Ra);
771 _BRA,10001,10,6.RA,_IMM12:BRA:short:mu:DJMP imm
772 "djmp r<RA>, <pcdisp>"
773 do_djmp(_SD, pcdisp, val_Ra);
774 _BRA,10001,10,6.RA,6.**,_IMM32:BRA:long:mu:DJMP imm long
775 "djmp r<RA>, <pcdisp>"
776 do_djmp(_SD, pcdisp, val_Ra);
782 void::function::do_djmpi:address_word pcdisp, unsigned32 imm
783 PSW_SET_QUEUE (PSW_RP, 1);
784 WRITE32_QUEUE (&RPT_C, 1);
785 WRITE32_QUEUE (&RPT_S, pcdisp);
786 WRITE32_QUEUE (&RPT_E, cia + (imm << 3));
788 _BRA,10101,00,6.IMM_6,6.**,6.RC:BRA:short:mu:DJMPI
789 "djmpi <IMM_6>, r<RC>"
790 do_djmpi(_SD, pcdisp, IMM_6);
791 _BRA,10101,10,6.IMM_6,_IMM12:BRA:short:mu:DJMPI imm
792 "djmpi <IMM_6>, <pcdisp>"
793 do_djmpi(_SD, pcdisp, IMM_6);
794 _BRA,10101,10,6.IMM_6,6.**,_IMM32:BRA:long:mu:DJMPI imm long
795 "djmpi <IMM_6>, <pcdisp>"
796 do_djmpi(_SD, pcdisp, IMM_6);
802 void::function::do_djsr:address_word pcdisp, unsigned32 ra
803 PSW_SET_QUEUE (PSW_RP, 1);
804 WRITE32_QUEUE (&RPT_C, 1);
805 WRITE32_QUEUE (&RPT_S, pcdisp);
806 WRITE32_QUEUE (&RPT_E, cia + (ra & ~0x7));
807 WRITE32_QUEUE (&GPR[62], cia + (ra & ~0x7) + 8);
809 _BRA,10011,00,6.RA,6.**,6.RC:BRA:short:mu:DJSR
811 do_djsr(_SD, pcdisp, val_Ra);
812 _BRA,10011,10,6.RA,_IMM12:BRA:short:mu:DJSR imm
813 "djsr r<RA>, <pcdisp>"
814 do_djsr(_SD, pcdisp, val_Ra);
815 _BRA,10011,10,6.RA,6.**,_IMM32:BRA:long:mu:DJSR imm long
816 "djsr r<RA>, <pcdisp>"
817 do_djsr(_SD, pcdisp, val_Ra);
823 void::function::do_djsri:address_word pcdisp, unsigned32 imm
824 PSW_SET_QUEUE (PSW_RP, 1);
825 WRITE32_QUEUE (&RPT_C, 1);
826 WRITE32_QUEUE (&RPT_S, pcdisp);
827 WRITE32_QUEUE (&RPT_E, cia + (imm << 3));
828 WRITE32_QUEUE (&GPR[62], cia + (imm << 3) + 8);
830 _BRA,10111,00,6.IMM_6,6.**,6.RC:BRA:short:mu:DJSRI
831 "djsri <IMM_6>, r<RC>"
832 do_djsri(_SD, pcdisp, IMM_6);
833 _BRA,10111,10,6.IMM_6,_IMM12:BRA:short:mu:DJSRI imm
834 "djsri <IMM_6>, <pcdisp>"
835 do_djsri(_SD, pcdisp, IMM_6);
836 _BRA,10111,10,6.IMM_6,6.**,_IMM32:BRA:long:mu:DJSRI imm long
837 "djsri <IMM_6>, <pcdisp>"
838 do_djsri(_SD, pcdisp, IMM_6);
844 _BRA,00001,00,6.**,6.**,6.RC:BRA:short:mu:JMP
847 if (RC == 62 && TRACE_CALL_P)
848 TRACE_ACTION |= TRACE_ACTION_RETURN;
849 _BRA,00001,10,_IMM18:BRA:short:mu:JMP imm
852 _BRA,00001,10,6.**,6.**,_IMM32:BRA:long:mu:JMP imm long
860 _BRA,00101,01,6.RA,6.**,6.RC:BRA:short:mu:JMPTNZ
864 _BRA,00101,11,6.RA,_IMM12:BRA:short:mu:JMPTNZ imm
868 _BRA,00101,11,6.RA,6.**,_IMM32:BRA:long:mu:JMPTNZ imm long
877 _BRA,00101,00,6.RA,6.**,6.RC:BRA:short:mu:JMPTZR
881 _BRA,00101,10,6.RA,_IMM12:BRA:short:mu:JMPTZR imm
885 _BRA,00101,10,6.RA,6.**,_IMM32:BRA:long:mu:JMPTZR imm long
894 void::function::do_join_pp:int pp, unsigned32 *ra, unsigned32 rb, unsigned32 src
897 WRITE32_QUEUE (ra, ((unsigned32)VL2_4(rb) << 16) | VL2_4(src));
900 WRITE32_QUEUE (ra, ((unsigned32)VL2_4(rb) << 16) | VH2_4(src));
903 WRITE32_QUEUE (ra, ((unsigned32)VH2_4(rb) << 16) | VL2_4(src));
906 WRITE32_QUEUE (ra, ((unsigned32)VH2_4(rb) << 16) | VH2_4(src));
913 case 0x0: return "ll";
914 case 0x1: return "lh";
915 case 0x2: return "hl";
916 case 0x3: return "hh";
920 _IALU1,011,pp,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:JOINpp
921 "join%s<pp> r<RA>, r<RB>, r<RC>"
922 do_join_pp(_SD, pp, Ra, Rb, Rc);
923 _IALU1,011,pp,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:JOINpp imm
924 "join%s<pp> r<RA>, r<RB>, <imm>"
925 do_join_pp(_SD, pp, Ra, Rb, immHL);
926 _IALU1,011,pp,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:JOINpp imm long
927 "join%s<pp> r<RA>, r<RB>, <imm>"
928 do_join_pp(_SD, pp, Ra, Rb, immHL);
934 _BRA,00011,00,6.**,6.**,6.RC:BRA:short:mu:JSR
936 if (cia == RPT_E && PSW_VAL (PSW_RP))
937 WRITE32_QUEUE (&GPR[62], RPT_S);
939 WRITE32_QUEUE (&GPR[62], cia + 8);
941 TRACE_ACTION |= TRACE_ACTION_CALL;
943 _BRA,00011,10,_IMM18:BRA:short:mu:JSR imm
945 if (cia == RPT_E && PSW_VAL (PSW_RP))
946 WRITE32_QUEUE (&GPR[62], RPT_S);
948 WRITE32_QUEUE (&GPR[62], cia + 8);
950 TRACE_ACTION |= TRACE_ACTION_CALL;
952 _BRA,00011,10,6.**,6.**,_IMM32:BRA:long:mu:JSR imm long
954 if (cia == RPT_E && PSW_VAL (PSW_RP))
955 WRITE32_QUEUE (&GPR[62], RPT_S);
957 WRITE32_QUEUE (&GPR[62], cia + 8);
959 TRACE_ACTION |= TRACE_ACTION_CALL;
965 _BRA,00111,01,6.RA,6.**,6.RC:BRA:short:mu:JSRTNZ
968 if (cia == RPT_E && PSW_VAL (PSW_RP))
969 WRITE32_QUEUE (&GPR[62], RPT_S);
971 WRITE32_QUEUE (&GPR[62], cia + 8);
974 TRACE_ACTION |= TRACE_ACTION_CALL;
976 _BRA,00111,11,6.RA,_IMM12:BRA:short:mu:JSRTNZ imm
979 if (cia == RPT_E && PSW_VAL (PSW_RP))
980 WRITE32_QUEUE (&GPR[62], RPT_S);
982 WRITE32_QUEUE (&GPR[62], cia + 8);
985 TRACE_ACTION |= TRACE_ACTION_CALL;
987 _BRA,00111,11,6.RA,6.**,_IMM32:BRA:long:mu:JSRTNZ imm long
990 if (cia == RPT_E && PSW_VAL (PSW_RP))
991 WRITE32_QUEUE (&GPR[62], RPT_S);
993 WRITE32_QUEUE (&GPR[62], cia + 8);
996 TRACE_ACTION |= TRACE_ACTION_CALL;
1003 _BRA,00111,00,6.RA,6.**,6.RC:BRA:short:mu:JSRTZR
1006 if (cia == RPT_E && PSW_VAL (PSW_RP))
1007 WRITE32_QUEUE (&GPR[62], RPT_S);
1009 WRITE32_QUEUE (&GPR[62], cia + 8);
1012 TRACE_ACTION |= TRACE_ACTION_CALL;
1014 _BRA,00111,10,6.RA,_IMM12:BRA:short:mu:JSRTZR imm
1017 if (cia == RPT_E && PSW_VAL (PSW_RP))
1018 WRITE32_QUEUE (&GPR[62], RPT_S);
1020 WRITE32_QUEUE (&GPR[62], cia + 8);
1023 TRACE_ACTION |= TRACE_ACTION_CALL;
1025 _BRA,00111,10,6.RA,6.**,_IMM32:BRA:long:mu:JSRTZR imm long
1028 if (cia == RPT_E && PSW_VAL (PSW_RP))
1029 WRITE32_QUEUE (&GPR[62], RPT_S);
1031 WRITE32_QUEUE (&GPR[62], cia + 8);
1034 TRACE_ACTION |= TRACE_ACTION_CALL;
1041 void::function::do_incr:int x, unsigned32 *rb, int delta
1044 next_rb = *rb + delta;
1046 next_rb = *rb - delta;
1048 next_rb = *rb; /* value not used */
1049 /* HW erratum: check value after incrementing */
1050 if (next_rb == MOD_E
1051 && (x == 1 || x == 3)
1052 && (PSW_VAL(PSW_MD))) {
1053 WRITE32_QUEUE (rb, MOD_S);
1055 else if (x == 1 || x == 3)
1056 WRITE32_QUEUE (rb, next_rb);
1060 int::function::make_even_reg:int reg, const char *name
1062 sim_engine_abort (SD, CPU, cia,
1063 "0x%lx:%s odd register (r%d) used in multi-word load/mulx2h",
1064 (long) cia, name, reg);
1067 void::function::do_ld2h:int ra, unsigned32 rb, unsigned32 src
1069 ra = make_even_reg(_SD, ra, "LD2H");
1070 mem = MEM(signed, rb + src, 4);
1073 WRITE32_QUEUE (&GPR[ra + 0], SEXT32(EXTRACTED32(mem, 0, 15), 16));
1074 WRITE32_QUEUE (&GPR[ra + 1], SEXT32(EXTRACTED32(mem, 16, 31), 16));
1083 default: return "?";
1086 _IMEM,00011,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LD2H
1087 "ld2h r<RA>, @(r<RB>, <SRC_6>)":XX == 0
1088 "ld2h r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
1089 do_ld2h(_SD, RA, Rb, src);
1090 do_incr(_SD, XX, &GPR[RB], 4);
1091 _IMEM,00011,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LD2H long
1092 "ld2h r<RA>, @(r<RB>, <imm>)"
1093 do_ld2h(_SD, RA, Rb, imm);
1099 void::function::do_ld2w:int ra, unsigned32 rb, unsigned32 src
1101 ra = make_even_reg(_SD, ra, "LD2W");
1102 mem = MEM(unsigned, rb + src, 8);
1105 WRITE32_QUEUE (&GPR[ra + 0], EXTRACTED64 (mem, 0, 31));
1106 WRITE32_QUEUE (&GPR[ra + 1], EXTRACTED64 (mem, 32, 63));
1109 _IMEM,00110,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:L2W
1110 "ld2w r<RA>, @(r<RB>, <SRC_6>)":XX == 0
1111 "ld2w r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
1112 do_ld2w(_SD, RA, Rb, src);
1113 do_incr(_SD, XX, &GPR[RB], 8);
1114 _IMEM,00110,10,6.RA,6.RB,_IMM32:IMEM:long:mu:L2W long
1115 "ld2w r<RA>, @(r<RB>, <imm>)"
1116 do_ld2w(_SD, RA, Rb, imm);
1122 void::function::do_ld4bh:unsigned32 ra, unsigned32 rb, unsigned32 src
1123 unsigned16 l1, l2, h1, h2;
1125 ra = make_even_reg(_SD, ra, "LD4BH");
1126 mem = MEM(unsigned, rb + src, 4);
1127 h1 = SEXT16(EXTRACTED32(mem, 0, 7), 8);
1128 l1 = SEXT16(EXTRACTED32(mem, 8, 15), 8);
1129 h2 = SEXT16(EXTRACTED32(mem, 16, 23), 8);
1130 l2 = SEXT16(EXTRACTED32(mem, 24, 31), 8);
1133 WRITE32_QUEUE (&GPR[ra + 0], (h1 << 16) | l1);
1134 WRITE32_QUEUE (&GPR[ra + 1], (h2 << 16) | l2);
1137 _IMEM,00101,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LD4BH
1138 "ld4bh r<RA>, @(r<RB>, <SRC_6>)":XX == 0
1139 "ld4bh r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
1140 do_ld4bh(_SD, RA, Rb, src);
1141 do_incr(_SD, XX, &GPR[RB], 4);
1142 _IMEM,00101,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LD4BH long
1143 "ld4bh r<RA>, @(r<RB>, <imm>)"
1144 do_ld4bh(_SD, RA, Rb, imm);
1150 void::function::do_ld4bhu:unsigned32 ra, unsigned32 rb, unsigned32 src
1151 unsigned16 l1, l2, h1, h2;
1153 ra = make_even_reg(_SD, ra, "LD4BH");
1154 mem = MEM(signed, rb + src, 4);
1155 h1 = EXTRACTED32(mem, 0, 7);
1156 l1 = EXTRACTED32(mem, 8, 15);
1157 h2 = EXTRACTED32(mem, 16, 23);
1158 l2 = EXTRACTED32(mem, 24, 31);
1161 WRITE32_QUEUE (&GPR[ra + 0], (h1 << 16) | l1);
1162 WRITE32_QUEUE (&GPR[ra + 1], (h2 << 16) | l2);
1165 _IMEM,01101,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LD4BHU
1166 "ld4hbu r<RA>, @(r<RB>, <SRC_6>)":XX == 0
1167 "ld4hbu r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
1168 do_ld4bhu(_SD, RA, Rb, src);
1169 do_incr(_SD, XX, &GPR[RB], 4);
1170 _IMEM,01101,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LD4BHU long
1171 "ld4hbu r<RA>, @(r<RB>, <imm>)"
1172 do_ld4bhu(_SD, RA, Rb, imm);
1178 void::function::do_ldb:unsigned32 *ra, unsigned32 rb, unsigned32 src
1179 WRITE32_QUEUE (ra, MEM(signed, rb + src, 1));
1181 _IMEM,00000,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LDB
1182 "ldb r<RA>, @(r<RB>, <SRC_6>)":XX == 0
1183 "ldb r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
1184 do_ldb(_SD, Ra, Rb, src);
1185 do_incr(_SD, XX, &GPR[RB], 1);
1186 _IMEM,00000,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LDB long
1187 "ldb r<RA>, @(r<RB>, <imm>)"
1188 do_ldb(_SD, Ra, Rb, imm);
1194 void::function::do_ldbu:unsigned32 *ra, unsigned32 rb, unsigned32 src
1195 WRITE32_QUEUE (ra, MEM(unsigned, rb + src, 1));
1197 _IMEM,01001,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LDBU
1198 "ldbu r<RA>, @(r<RB>, <SRC_6>)":XX == 0
1199 "ldbu r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
1200 do_ldbu(_SD, Ra, Rb, src);
1201 do_incr(_SD, XX, &GPR[RB], 1);
1202 _IMEM,01001,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LDBU long
1203 "ldbu r<RA>, @(r<RB>, <imm>)"
1204 do_ldbu(_SD, Ra, Rb, imm);
1210 void::function::do_ldh:unsigned32 *ra, unsigned32 rb, unsigned32 src
1211 WRITE32_QUEUE (ra, MEM(signed, rb + src, 2));
1213 _IMEM,00010,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LDH
1214 "ldh r<RA>, @(r<RB>, <SRC_6>)":XX == 0
1215 "ldh r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
1216 do_ldh(_SD, Ra, Rb, src);
1217 do_incr(_SD, XX, &GPR[RB], 2);
1218 _IMEM,00010,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LDH long
1219 "ldh r<RA>, @(r<RB>, <imm>)"
1220 do_ldh(_SD, Ra, Rb, imm);
1226 void::function::do_ldhh:unsigned32 *ra, unsigned32 rb, unsigned32 src
1227 WRITE32_QUEUE (ra, MEM(signed, rb + src, 2) << 16);
1229 _IMEM,00001,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LDHH
1230 "ldhh r<RA>, @(r<RB>, <SRC_6>)":XX == 0
1231 "ldhh r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
1232 do_ldhh(_SD, Ra, Rb, src);
1233 do_incr(_SD, XX, &GPR[RB], 2);
1234 _IMEM,00001,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LDHH long
1235 "ldhh r<RA>, @(r<RB>, <imm>)"
1236 do_ldhh(_SD, Ra, Rb, imm);
1242 void::function::do_ldhu:unsigned32 *ra, unsigned32 rb, unsigned32 src
1243 WRITE32_QUEUE (ra, MEM(unsigned, rb + src, 2));
1245 _IMEM,01010,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LDHU
1246 "ldhu r<RA>, @(r<RB>, <SRC_6>)":XX == 0
1247 "ldhu r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
1248 do_ldhu(_SD, Ra, Rb, src);
1249 do_incr(_SD, XX, &GPR[RB], 2);
1250 _IMEM,01010,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LDHU long
1251 "ldhu r<RA>, @(r<RB>, <imm>)"
1252 do_ldhu(_SD, Ra, Rb, imm);
1258 void::function::do_ldw:unsigned32 *ra, unsigned32 rb, unsigned32 src
1259 WRITE32_QUEUE (ra, MEM(signed, rb + src, 4));
1261 _IMEM,00100,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LDW
1262 "ldw r<RA>, @(r<RB>, <SRC_6>)":XX == 0
1263 "ldw r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
1264 do_ldw(_SD, Ra, Rb, src);
1265 do_incr(_SD, XX, &GPR[RB], 4);
1266 _IMEM,00100,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LDW long
1267 "ldw r<RA>, @(r<RB>, <imm>)"
1268 do_ldw(_SD, Ra, Rb, imm);
1274 void::function::do_mac:unsigned64 *aa, unsigned32 *ra, signed32 rb, signed32 src
1275 unsigned64 accum = *aa;
1276 accum += (signed64) (rb) * (signed64) (src);
1277 WRITE64_QUEUE (aa, accum);
1278 WRITE32_QUEUE (ra, EXTRACTED64(accum, 32, 63));
1280 _IALU2,10100,0,1.AA,6.RA,6.RB,6.RC:IALU2:short:iu:MACa
1281 "mac<AA> r<RA>, r<RB>, r<RC>"
1282 do_mac(_SD, Aa, Ra, Rb, Rc);
1283 _IALU2,10100,1,1.AA,6.RA,6.RB,_IMM6:IALU2:short:iu:MACa imm
1284 "mac<AA> r<RA>, r<RB>, <imm>"
1285 do_mac(_SD, Aa, Ra, Rb, imm);
1291 void::function::do_macs:unsigned64 *aa, unsigned32 *ra, signed32 rb, signed32 src
1292 unsigned64 accum = *aa;
1293 accum += ((signed64) (rb) * (signed64) (src)) << 1;
1294 WRITE64_QUEUE (aa, accum);
1295 WRITE32_QUEUE (ra, EXTRACTED64(accum, 0, 31));
1297 _IALU2,10101,0,1.AA,6.RA,6.RB,6.RC:IALU2:short:iu:MACSa
1298 "macs<AA> r<RA>, r<RB>, r<RC>"
1299 do_macs(_SD, Aa, Ra, Rb, Rc);
1300 _IALU2,10101,1,1.AA,6.RA,6.RB,_IMM6:IALU2:short:iu:MACSa imm
1301 "macs<AA> r<RA>, r<RB>, <imm>"
1302 do_macs(_SD, Aa, Ra, Rb, imm);
1308 _IMEM,00111,11,6.**,6.RB,_IMM6:IMEM:short:mu:MODDEC
1309 "moddec r<RB>, <imm>"
1310 do_incr(_SD, 3/*0b11*/, &GPR[RB], imm_5);
1311 _IMEM,00111,01,6.**,6.RB,_IMM6:IMEM:short:mu:MODINC
1312 "modinc r<RB>, <imm>"
1313 do_incr(_SD, 1/*0b01*/, &GPR[RB], imm_5);
1319 void::function::do_msub:unsigned64 *aa, unsigned32 *ra, signed32 rb, signed32 src
1320 unsigned64 accum = *aa;
1321 accum -= (signed64) (rb) * (signed64) (src);
1322 WRITE64_QUEUE (aa, accum);
1323 WRITE32_QUEUE (ra, EXTRACTED64(accum, 32, 63));
1325 _IALU2,10110,0,1.AA,6.RA,6.RB,6.RC:IALU2:short:iu:MSUBa
1326 "msub<AA> r<RA>, r<RB>, r<RC>"
1327 do_msub(_SD, Aa, Ra, Rb, Rc);
1328 _IALU2,10110,1,1.AA,6.RA,6.RB,_IMM6:IALU2:short:iu:MSUBa imm
1329 "msub<AA> r<RA>, r<RB>, <imm>"
1330 do_msub(_SD, Aa, Ra, Rb, imm);
1336 void::function::do_msubs:unsigned64 *aa, unsigned32 *ra, signed32 rb, signed32 src
1337 unsigned64 accum = *aa;
1338 accum -= ((signed64) (rb) * (signed64) (src)) << 1;
1339 WRITE64_QUEUE (aa, accum);
1340 WRITE32_QUEUE (ra, EXTRACTED64(accum, 0, 31));
1342 _IALU2,10111,0,1.AA,6.RA,6.RB,6.RC:IALU2:short:iu:MSUBSa
1343 "msubs<AA> r<RA>, r<RB>, r<RC>"
1344 do_msubs(_SD, Aa, Ra, Rb, Rc);
1345 _IALU2,10111,1,1.AA,6.RA,6.RB,_IMM6:IALU2:short:iu:MSUBSa imm
1346 "msubs<AA> r<RA>, r<RB>, <imm>"
1347 do_msubs(_SD, Aa, Ra, Rb, imm);
1353 void::function::do_mul:unsigned32 *ra, unsigned32 rb, unsigned32 src
1354 WRITE32_QUEUE (ra, rb * src);
1356 _IALU2,10000,00,6.RA,6.RB,6.RC:IALU2:short:iu:MUL
1357 "mul r<RA>, r<RB>, r<RC>"
1358 do_mul(_SD, Ra, Rb, Rc);
1359 _IALU2,10000,10,6.RA,6.RB,_IMM6:IALU2:short:iu:MUL imm
1360 "mul r<RA>, r<RB>, <imm>"
1361 do_mul(_SD, Ra, Rb, imm);
1367 void::function::do_mul2h:unsigned32 *ra, unsigned32 rb, unsigned32 src
1368 unsigned16 high = VH2_4(rb) * VH2_4(src);
1369 unsigned16 low = VL2_4(rb) * VL2_4(src);
1370 WRITE32_QUEUE (ra, (high << 16) | low);
1372 _IALU2,00000,00,6.RA,6.RB,6.RC:IALU2:short:iu:MUL2H
1373 "mul2h r<RA>, r<RB>, r<RC>"
1374 do_mul2h(_SD, Ra, Rb, Rc);
1375 _IALU2,00000,10,6.RA,6.RB,_IMM6:IALU2:short:iu:MUL2H imm
1376 "mul2h r<RA>, r<RB>, <imm>"
1377 do_mul2h(_SD, Ra, Rb, immHL);
1383 void::function::do_mulx:unsigned64 *aa, signed32 rb, signed32 src
1384 WRITE64_QUEUE (aa, (signed64) (rb) * (signed64) (src));
1386 _IALU2,11000,00,5.*,1.AA,6.RB,6.RC:IALU2:short:iu:MULX
1387 "mulx a<AA>, r<RB>, r<RC>"
1388 do_mulx(_SD, Aa, Rb, Rc);
1389 _IALU2,11000,10,5.*,1.AA,6.RB,_IMM6:IALU2:short:iu:MULX imm
1390 "mulx a<AA>, r<RB>, <imm>"
1391 do_mulx(_SD, Aa, Rb, imm);
1396 void::function::do_mulx2h:int ra, signed32 rb, signed32 src, int high
1397 signed32 result = rb * src;
1400 ra = make_even_reg(_SD, ra, "MULX2H");
1402 WRITE32_QUEUE (&GPR[ra+1], result);
1406 WRITE32_QUEUE (&GPR[ra+0], result);
1409 _IALU2,00001,00,6.RA,6.RB,6.RC:IALU2:short:iu:MULX2H
1410 "mul2h r<RA>, r<RB>, r<RC>"
1411 do_mulx2h(_SD, RA, RbH, RcH, 1);
1412 do_mulx2h(_SD, RA, RbL, RcL, 0);
1413 _IALU2,00001,10,6.RA,6.RB,_IMM6:IALU2:short:iu:MULX2H imm
1414 "mul2h r<RA>, r<RB>, <imm>"
1415 do_mulx2h(_SD, RA, RbH, imm, 1);
1416 do_mulx2h(_SD, RA, RbL, imm, 0);
1420 void::function::do_mulhx:int pp, unsigned32 *ra, unsigned32 rb, unsigned32 src
1424 value = SEXT32(VL2_4(rb), 16) * SEXT32(VL2_4(src), 16);
1427 value = SEXT32(VL2_4(rb), 16) * SEXT32(VH2_4(src), 16);
1430 value = SEXT32(VH2_4(rb), 16) * SEXT32(VL2_4(src), 16);
1433 value = SEXT32(VH2_4(rb), 16) * SEXT32(VH2_4(src), 16);
1436 sim_engine_abort (SD, CPU, cia, "do_mulhx - internal error - bad switch");
1438 WRITE32_QUEUE (ra, value);
1440 _IALU2,001,pp,00,6.RA,6.RB,6.RC:IALU2:short:iu:MULHXpp
1441 "mulhx%s<pp> r<RA>, r<RB>, r<RC>"
1442 do_mulhx(_SD, pp, Ra, Rb, Rc);
1443 _IALU2,001,pp,10,6.RA,6.RB,_IMM6:IALU2:short:iu:MULHXpp imm
1444 "mulhx%s<pp> r<RA>, r<RB>, <imm>"
1445 do_mulhx(_SD, pp, Ra, Rb, immHL);
1451 void::function::do_mulxs:unsigned64 *aa, signed32 rb, signed32 src
1452 WRITE64_QUEUE (aa, ((signed64) (rb) * (signed64) (src)) << 1);
1454 _IALU2,11001,00,5.*,1.AA,6.RB,6.RC:IALU2:short:iu:MULXS
1455 "mulxs a<AA>, r<RB>, r<RC>"
1456 do_mulxs(_SD, Aa, Rb, Rc);
1457 _IALU2,11001,10,5.*,1.AA,6.RB,_IMM6:IALU2:short:iu:MULXS imm
1458 "mulxs a<AA>, r<RB>, <imm>"
1459 do_mulxs(_SD, Aa, Rb, imm);
1465 void::function::do_mvfacc:unsigned32 *ra, unsigned64 ab, unsigned32 src
1466 while (src > 63) src -= 64;
1467 WRITE32_QUEUE (ra, ((signed64)ab) >> src);
1469 _IALU2,11111,00,6.RA,5.*,1.AB,6.RC:IALU2:short:iu:MVFACC
1470 "mvfacc r<RA>, a<AB>, r<RC>"
1471 do_mvfacc(_SD, Ra, *Ab, Rc);
1472 _IALU2,11111,10,6.RA,5.*,1.AB,_IMM6:IALU2:short:iu:MVFACC imm
1473 "mvfacc r<RA>, a<AB>, <imm>"
1474 do_mvfacc(_SD, Ra, *Ab, imm_6u);
1480 _BRA,11110,00,6.RA,6.CR,6.ID:BRA:short:mu:MVFSYS
1481 "mvfsys r<RA>, cr<CR>"
1484 if (CR >= NR_CONTROL_REGISTERS)
1485 sim_engine_abort (SD, CPU, cia, "FIXME - illegal CR");
1487 WRITE32_QUEUE (Ra, (CPU)->regs.control[CR]);
1490 WRITE32_QUEUE (Ra, PSWL);
1493 WRITE32_QUEUE (Ra, EXTRACTED32(PSWH, 16, 31));
1496 WRITE32_QUEUE (Ra, PSW_FLAG_VAL(CR));
1499 sim_engine_abort (SD, CPU, cia, "FIXME - illegal ID");
1506 _IALU2,01111,00,5.*,1.AA,6.RB,6.RC:IALU2:short:iu:MVTACC
1507 "mvtacc a<AA>, r<RB>, r<RC>"
1508 WRITE64_QUEUE (Aa, INSERTED64(RbU, 0, 31) | (RcU));
1514 _BRA,01110,00,6.CR,6.RB,6.ID:BRA:short:mu:MVTSYS
1515 "mvtsys cr<CR>, r<RB>"
1517 case 0: /* control register */
1518 if (CR >= NR_CONTROL_REGISTERS)
1519 sim_engine_abort (SD, CPU, cia, "FIXME - illegal CR");
1522 unsigned32 value = Rb;
1523 CPU->mvtsys_left_p = 1;
1524 if (CR == processor_status_word_cr)
1526 unsigned32 ds = PSW & BIT32 (PSW_DS); /* preserve ds */
1527 value = ds | (value & PSW_VALID);
1529 else if (CR == backup_processor_status_word_cr
1530 || CR == debug_backup_processor_status_word_cr)
1531 value &= DPSW_VALID;
1532 else if (CR == eit_vector_base_cr)
1534 WRITE32_QUEUE (&(CPU)->regs.control[CR], value);
1538 WRITE32_QUEUE_MASK (&PSW, EXTRACTED32(Rb, 16, 31),
1539 PSW_VALID & 0x0000ffff);
1543 unsigned32 ds = PSW & BIT32 (PSW_DS); /* preserve ds */
1544 WRITE32_QUEUE_MASK (&PSW, (EXTRACTED32(Rb, 16, 31) << 16) | ds,
1545 (PSW_VALID | ds) & 0xffff0000);
1549 PSW_FLAG_SET_QUEUE(CR, Rb & 1);
1552 sim_engine_abort (SD, CPU, cia, "FIXME - illegal ID");
1559 _BRA,01111,00,6.**,6.**,6.**:BRA:short:iu,mu:NOP
1566 _LOGIC,11001,00,6.RA,6.RB,6.*:LOGIC:short:iu,mu:NOT
1568 WRITE32_QUEUE (Ra, ~Rb);
1574 _LOGIC,01001,00,***,3.FA,***,3.FB,***,3.FC:LOGIC:short:iu,mu:NOTFG
1575 "notfg f<FA>, f<FB>"
1576 PSW_FLAG_SET_QUEUE(FA, !PSW_FLAG_VAL(FB));
1581 _LOGIC,11010,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:OR
1582 "or r<RA>, r<RB>, r<RC>"
1583 WRITE32_QUEUE (Ra, Rb | Rc);
1584 _LOGIC,11010,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:OR imm
1585 "or r<RA>, r<RB>, <imm>"
1586 WRITE32_QUEUE (Ra, Rb | imm);
1587 _LOGIC,11010,10,6.RA,6.RB,_IMM32:LOGIC:long:iu,mu:OR imm long
1588 "or r<RA>, r<RB>, <imm>"
1589 WRITE32_QUEUE (Ra, Rb | imm);
1595 _LOGIC,01010,00,***,3.FA,***,3.FB,***,3.FC:LOGIC:short:iu,mu:ORFG
1596 "orfg f<FA>, f<FB>, f<FC>"
1597 PSW_FLAG_SET_QUEUE(FA, PSW_FLAG_VAL(FB) | PSW_FLAG_VAL(FC));
1598 _LOGIC,01010,10,***,3.FA,***,3.FB,_IMM6:LOGIC:short:iu,mu:ORFG imm
1599 "orfg f<FA>, f<FB>, <imm>"
1600 PSW_FLAG_SET_QUEUE(FA, PSW_FLAG_VAL(FB) | (imm_6 & 1));
1606 _BRA,01000,00,6.**,6.**,6.**:BRA:short:mu:REIT
1608 WRITE32_QUEUE (&PSW, bPSW);
1616 void::function::do_repeat:unsigned32 count, address_word pcaddr
1617 address_word rpt_s = cia + 8;
1618 address_word rpt_e = cia + pcaddr;
1621 sim_engine_abort (SD, CPU, cia, "REPEAT with ra=0 and REPEATI with imm = 0 is forbidden.");
1623 PSW_SET_QUEUE (PSW_RP, 1);
1624 if (rpt_e < rpt_s + 0x10)
1625 sim_io_eprintf (sd, "warning: 0x%lx: REPEAT or REPEATI loop is too small\n", (long) cia);
1626 WRITE32_QUEUE (&RPT_C, count - 1);
1627 WRITE32_QUEUE (&RPT_S, rpt_s);
1628 WRITE32_QUEUE (&RPT_E, rpt_e);
1630 _BRA,11000,00,6.RA,6.**,6.RC:BRA:short:mu:REPEAT
1631 "repeat r<RA>, r<RC>"
1632 do_repeat(_SD, val_Ra, pcaddr);
1633 _BRA,11000,10,6.RA,_IMM12:BRA:short:mu:REPEAT imm
1634 "repeat r<RA>, <pcaddr>"
1635 do_repeat(_SD, val_Ra, pcaddr);
1636 _BRA,11000,10,6.RA,6.**,_IMM32:BRA:long:mu:REPEAT imm long
1637 "repeat r<RA>, <pcaddr>"
1638 do_repeat(_SD, val_Ra, pcaddr);
1645 _BRA,11010,00,6.IMM_6,6.**,6.RC:BRA:short:mu:REPEATI
1646 "repeati <IMM_6>, r<RC>"
1647 do_repeat(_SD, IMM_6, pcaddr);
1648 _BRA,11010,10,6.IMM_6,_IMM12:BRA:short:mu:REPEATI imm
1649 "repeati <IMM_6>, <pcaddr>"
1650 do_repeat(_SD, IMM_6, pcaddr);
1651 _BRA,11010,10,6.IMM_6,6.**,_IMM32:BRA:long:mu:REPEATI imm long
1652 "repeati <IMM_6>, <pcaddr>"
1653 do_repeat(_SD, IMM_6, pcaddr);
1660 _BRA,01010,00,6.*,6.*,6.*:BRA:short:mu:RTD
1662 WRITE32_QUEUE (&PSW, DPSW);
1670 _LOGIC,10100,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:ROT
1671 "rot r<RA>, r<RB>, r<RC>"
1672 WRITE32_QUEUE (Ra, ROT32(Rb, Rc & 0x1f));
1673 _LOGIC,10100,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:ROT imm
1674 "rot r<RA>, r<RB>, <imm>"
1675 WRITE32_QUEUE (Ra, ROT32(Rb, imm & 0x1f));
1682 void::function::do_rot2h:unsigned32 *ra, unsigned32 rb, signed32 src
1683 unsigned16 high = ROTR16(VH2_4(rb), VH2_4(src) & 0xf);
1684 unsigned16 low = ROTR16(VL2_4(rb), VL2_4(src) & 0xf);
1685 WRITE32_QUEUE (ra, (high << 16) | low);
1687 _LOGIC,10101,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:ROT2H
1688 "rot2h r<RA>, r<RB>, r<RC>"
1689 do_rot2h(_SD, Ra, Rb, Rc);
1690 _LOGIC,10101,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:ROT2H imm
1691 "rot2h r<RA>, r<RB>, <imm>"
1692 do_rot2h(_SD, Ra, Rb, immHL);
1699 void::function::do_sat:signed32 *ra, signed32 rb, signed32 src
1700 int bits = LSMASKED32(src, 4, 0); /* 5 */
1701 signed32 sat = LSMASK32(bits, 0) >> 2;
1702 signed32 nsat = ~sat;
1705 sim_io_eprintf (sd, "warning: 0x%lx:SAT bit overflow\n", (long) cia);
1710 else if (rb <= nsat)
1714 WRITE32_QUEUE (ra, value);
1716 _IALU2,01000,00,6.RA,6.RB,6.RC:IALU2:short:iu:SAT
1717 "sat r<RA>, r<RB>, r<RC>"
1718 do_sat(_SD, Ra, Rb, Rc);
1719 _IALU2,01000,10,6.RA,6.RB,_IMM6:IALU2:short:iu:SAT imm
1720 "sat r<RA>, r<RB>, <imm>"
1721 do_sat(_SD, Ra, Rb, imm_5);
1728 void::function::do_sath:signed32 *ra, signed32 rb, signed32 src, int high, int updates_f4
1729 int bits = LSMASKED32(src, 4, 0); /* 5 */
1730 signed32 sat = LSMASK32(bits, 0) >> 2;
1731 signed32 nsat = ~sat;
1734 sim_io_eprintf (sd, "warning: 0x%lx:SAT bit overflow\n", (long) cia);
1739 else if (rb <= nsat)
1744 WRITE32_QUEUE_MASK (ra, value << 16, 0xffff0000);
1746 WRITE32_QUEUE_MASK (ra, value, 0x0000ffff);
1749 /* if MU instruction was a MVTSYS (lkr), unqueue register writes now */
1750 if(STATE_CPU (sd, 0)->mvtsys_left_p)
1751 unqueue_writes (sd, STATE_CPU (sd, 0), cia);
1752 PSW_FLAG_SET_QUEUE(PSW_S_FLAG, PSW_FLAG_VAL(PSW_S_FLAG) ^ (value & 1));
1755 _IALU2,01001,00,6.RA,6.RB,6.RC:IALU2:short:iu:SAT2H
1756 "sat2h r<RA>, r<RB>, r<RC>"
1757 do_sath(_SD, Ra, RbH, RcH, 1, 0);
1758 do_sath(_SD, Ra, RbL, RcL, 0, 0);
1759 _IALU2,01001,10,6.RA,6.RB,_IMM6:IALU2:short:iu:SAT2H imm
1760 "sat2h r<RA>, r<RB>, <imm>"
1761 do_sath(_SD, Ra, RbH, imm_5, 1, 0);
1762 do_sath(_SD, Ra, RbL, imm_5, 0, 0);
1774 default: return "?";
1777 _IALU2,1110,p,00,6.RA,6.RB,6.RC:IALU2:short:iu:SATHP
1778 "sath%s<p> r<RA>, r<RB>, r<RC>"
1779 do_sath(_SD, Ra, Rb, Rc, p, 1);
1780 _IALU2,1110,p,10,6.RA,6.RB,_IMM6:IALU2:short:iu:SATHP imm
1781 "sath%s<p> r<RA>, r<RB>, <imm>"
1782 do_sath(_SD, Ra, Rb, imm_5, p, 1);
1788 void::function::do_satz:signed32 *ra, signed32 rb, signed32 src
1790 WRITE32_QUEUE (ra, 0);
1792 do_sat (_SD, ra, rb, src);
1794 _IALU2,01010,00,6.RA,6.RB,6.RC:IALU2:short:iu:SATZ
1795 "satz r<RA>, r<RB>, r<RC>"
1796 do_satz(_SD, Ra, Rb, Rc);
1797 _IALU2,01010,10,6.RA,6.RB,_IMM6:IALU2:short:iu:SATZ imm
1798 "satz r<RA>, r<RB>, <imm>"
1799 do_satz(_SD, Ra, Rb, imm_5);
1806 void::function::do_satzh:signed32 *ra, signed16 rb, signed32 src, int high
1807 int bits = LSMASKED32(src, 3, 0); /*4*/
1808 signed16 sat = LSMASK16(bits, 0) >> 2;
1812 sim_io_eprintf (sd, "warning: 0x%lx:SATZ2H bit overflow\n", (long) cia);
1813 if (bits == 0 && rb > sat)
1822 WRITE32_QUEUE_MASK (ra, value << 16, 0xffff0000);
1824 WRITE32_QUEUE_MASK (ra, value, 0x0000ffff);
1827 _IALU2,01011,00,6.RA,6.RB,6.RC:IALU2:short:iu:SATZ2H
1828 "satz2h r<RA>, r<RB>, r<RC>"
1829 do_satzh(_SD, Ra, RbH, RcH, 1);
1830 do_satzh(_SD, Ra, RbL, RcL, 0);
1831 _IALU2,01011,10,6.RA,6.RB,_IMM6:IALU2:short:iu:SATZ2H imm
1832 "satz2h r<RA>, r<RB>, <imm>"
1833 do_satzh(_SD, Ra, RbH, imm, 1);
1834 do_satzh(_SD, Ra, RbL, imm, 0);
1841 void::function::do_sra:unsigned32 *ra, unsigned32 rb, signed32 src
1843 while (src > 31) src -= 32;
1844 while (src < -32) src += 32;
1846 value = (signed32)rb >> src;
1847 else if (src == -32)
1851 WRITE32_QUEUE (ra, value);
1853 _LOGIC,10000,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRA
1854 "sra r<RA>, r<RB>, r<RC>"
1855 do_sra(_SD, Ra, Rb, Rc);
1856 _LOGIC,10000,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRA imm
1857 "sra r<RA>, r<RB>, <imm>"
1858 do_sra(_SD, Ra, Rb, imm);
1865 void::function::do_srah:unsigned32 *ra, unsigned32 rb, int src, int high
1867 while (src > 31) src -= 32;
1868 while (src < -32) src += 32;
1870 value = (signed32)rb >> src;
1871 else if (src == -32)
1876 WRITE32_QUEUE_MASK (ra, value << 16, 0xffff0000);
1878 WRITE32_QUEUE_MASK (ra, value, 0x0000ffff);
1880 _LOGIC,0010,p,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRAHP
1881 "srah%s<p> r<RA>, r<RB>, r<RC>"
1882 do_srah(_SD, Ra, Rb, Rc, p);
1883 _LOGIC,0010,p,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRAHP imm
1884 "srah%s<p> r<RA>, r<RB>, <imm>"
1885 do_srah(_SD, Ra, Rb, imm, p);
1892 _LOGIC,10001,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRA2H
1893 "sra2h r<RA>, r<RB>, r<RC>"
1894 signed32 srcH = RcH;
1895 signed32 srcL = RcL;
1896 while (srcH > 15) srcH -= 16;
1897 while (srcH < -16) srcH += 16;
1898 while (srcL > 15) srcL -= 16;
1899 while (srcL < -16) srcL += 16;
1900 do_srah(_SD, Ra, RbH, srcH, 1);
1901 do_srah(_SD, Ra, RbL, srcL, 0);
1902 _LOGIC,10001,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRA2H imm
1903 "sra2h r<RA>, r<RB>, <imm>"
1905 while (src > 15) src -= 16;
1906 while (src < -16) src += 16;
1907 do_srah(_SD, Ra, RbH, src, 1);
1908 do_srah(_SD, Ra, RbL, src, 0);
1915 void::function::do_src:unsigned32 *ra, unsigned32 rb, int src
1919 while (src > 31) src -= 32;
1920 while (src < -32) src += 32;
1923 operand = (INSERTED64(rb, 0, 31) | INSERTED64(*ra, 32, 63));
1924 shifted = operand >> src;
1925 value = EXTRACTED64(shifted, 32, 63);
1929 operand = (INSERTED64(*ra, 0, 31) | INSERTED64(rb, 32, 63));
1930 shifted = operand << -src;
1931 value = EXTRACTED64(shifted, 0, 31);
1933 WRITE32_QUEUE (ra, value);
1935 _LOGIC,10110,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRC
1936 "src r<RA>, r<RB>, r<RC>"
1937 do_src(_SD, Ra, Rb, Rc);
1938 _LOGIC,10110,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRC imm
1939 "src r<RA>, r<RB>, <imm>"
1940 do_src(_SD, Ra, Rb, imm);
1947 void::function::do_srl:unsigned32 *ra, unsigned32 rb, int src
1949 while (src > 31) src -= 32;
1950 while (src < -32) src += 32;
1952 value = (unsigned32)rb >> src;
1953 else if (src == -32)
1956 value = (unsigned32)rb << -src;
1957 WRITE32_QUEUE (ra, value);
1959 _LOGIC,10010,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRL
1960 "srl r<RA>, r<RB>, r<RC>"
1961 do_srl(_SD, Ra, Rb, Rc);
1962 _LOGIC,10010,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRL imm
1963 "srl r<RA>, r<RB>, <imm>"
1964 do_srl(_SD, Ra, Rb, imm);
1971 void::function::do_srlh:unsigned32 *ra, unsigned32 rb, int src, int high
1973 while (src > 31) src -= 32;
1974 while (src < -32) src += 32;
1977 else if (src == -32)
1982 WRITE32_QUEUE_MASK (ra, value << 16, 0xffff0000);
1984 WRITE32_QUEUE_MASK (ra, value, 0x0000ffff);
1986 _LOGIC,0011,p,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRLHP
1987 "srlh%s<p> r<RA>, r<RB>, r<RC>"
1988 do_srlh(_SD, Ra, Rb, Rc, p);
1989 _LOGIC,0011,p,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRLHP imm
1990 "srlh%s<p> r<RA>, r<RB>, <imm>"
1991 do_srlh(_SD, Ra, Rb, imm, p);
1996 _LOGIC,10011,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRL2H
1997 "srl2h r<RA>, r<RB>, r<RC>"
1998 signed32 srcH = RcH;
1999 signed32 srcL = RcL;
2000 while (srcH > 15) srcH -= 16;
2001 while (srcH < -16) srcH += 16;
2002 while (srcL > 15) srcL -= 16;
2003 while (srcL < -16) srcL += 16;
2004 do_srlh(_SD, Ra, RbHU, srcH, 1);
2005 do_srlh(_SD, Ra, RbLU, srcL, 0);
2006 _LOGIC,10011,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRL2H imm
2007 "srl2h r<RA>, r<RB>, <imm>"
2009 while (src > 15) src -= 16;
2010 while (src < -16) src += 16;
2011 do_srlh(_SD, Ra, RbHU, src, 1);
2012 do_srlh(_SD, Ra, RbLU, src, 0);
2019 void::function::get_even_reg:int *reg, unsigned32 *r0, const char *name
2021 sim_engine_abort (SD, CPU, cia,
2022 "0x%lx:%s odd register (r%d) used in multi-word store",
2023 (long) cia, name, *reg);
2029 void::function::do_st2h:int ra, unsigned32 rb, unsigned32 src
2032 get_even_reg(_SD, &ra, &val_ra, "ST2H");
2033 mem = INSERTED32(val_ra, 0, 15) |
2034 INSERTED32(GPR[ra + 1], 16, 31);
2035 STORE(rb + src, 4, mem);
2037 _IMEM,10011,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:ST2H
2038 "st2h r<RA>, @(r<RB>, <SRC_6>)":XX == 0
2039 "st2h r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
2040 do_st2h(_SD, RA, Rb, src);
2041 do_incr(_SD, XX, &GPR[RB], 4);
2042 _IMEM,10011,10,6.RA,6.RB,_IMM32:IMEM:long:mu:ST2H long
2043 "st2h r<RA>, @(r<RB>, <imm>)"
2044 do_st2h(_SD, RA, Rb, imm);
2050 void::function::do_st2w:int ra, unsigned32 rb, unsigned32 src
2053 get_even_reg(_SD, &ra, &val_ra, "ST2W");
2054 mem = INSERTED64(val_ra, 0, 31) | INSERTED64(GPR[ra + 1], 32, 63);
2055 STORE(rb + src, 8, mem);
2057 _IMEM,10110,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:ST2W
2058 "st2w r<RA>, @(r<RB>, <SRC_6>)":XX == 0
2059 "st2w r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
2060 do_st2w(_SD, RA, Rb, src);
2061 do_incr(_SD, XX, &GPR[RB], 8);
2062 _IMEM,10110,10,6.RA,6.RB,_IMM32:IMEM:long:mu:ST2W long
2063 "st2w r<RA>, @(r<RB>, <imm>)"
2064 do_st2w(_SD, RA, Rb, imm);
2070 void::function::do_st4hb:int ra, unsigned32 rb, unsigned32 src
2073 get_even_reg(_SD, &ra, &val_ra, "ST4HB");
2074 mem = INSERTED32(EXTRACTED32(val_ra, 8, 15), 0, 7) |
2075 INSERTED32(EXTRACTED32(val_ra, 24, 31), 8, 15) |
2076 INSERTED32(EXTRACTED32(GPR[ra + 1], 8, 15), 16, 23) |
2077 INSERTED32(EXTRACTED32(GPR[ra + 1], 24, 31), 24, 31);
2078 STORE(rb + src, 4, mem);
2080 _IMEM,10101,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:ST4HB
2081 "st4hb r<RA>, @(r<RB>, <SRC_6>)":XX == 0
2082 "st4hb r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
2083 do_st4hb(_SD, RA, Rb, src);
2084 do_incr(_SD, XX, &GPR[RB], 4);
2085 _IMEM,10101,10,6.RA,6.RB,_IMM32:IMEM:long:mu:ST4HB long
2086 "st4hb r<RA>, @(r<RB>, <imm>)"
2087 do_st4hb(_SD, RA, Rb, imm);
2093 void::function::do_stb:unsigned32 ra, unsigned32 rb, unsigned32 src
2094 STORE(rb + src, 1, EXTRACTED32(ra, 24, 31));
2096 _IMEM,10000,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:STB
2097 "stb r<RA>, @(r<RB>, <SRC_6>)":XX == 0
2098 "stb r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
2099 do_stb(_SD, val_Ra, Rb, src);
2100 do_incr(_SD, XX, &GPR[RB], 1);
2101 _IMEM,10000,10,6.RA,6.RB,_IMM32:IMEM:long:mu:STB long
2102 "stb r<RA>, @(r<RB>, <imm>)"
2103 do_stb(_SD, val_Ra, Rb, imm);
2109 void::function::do_sth:unsigned32 ra, unsigned32 rb, unsigned32 src
2110 STORE(rb + src, 2, EXTRACTED32(ra, 16, 31));
2112 _IMEM,10010,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:STH
2113 "sth r<RA>, @(r<RB>, <SRC_6>)":XX == 0
2114 "sth r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
2115 do_sth(_SD, val_Ra, Rb, src);
2116 do_incr(_SD, XX, &GPR[RB], 2);
2117 _IMEM,10010,10,6.RA,6.RB,_IMM32:IMEM:long:mu:STH long
2118 "sth r<RA>, @(r<RB>, <imm>)"
2119 do_sth(_SD, val_Ra, Rb, imm);
2125 void::function::do_sthh:unsigned32 ra, unsigned32 rb, unsigned32 src
2126 STORE(rb + src, 2, EXTRACTED32(ra, 0, 15));
2128 _IMEM,10001,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:STHH
2129 "sthh r<RA>, @(r<RB>, <SRC_6>)":XX == 0
2130 "sthh r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
2131 do_sthh(_SD, val_Ra, Rb, src);
2132 do_incr(_SD, XX, &GPR[RB], 2);
2133 _IMEM,10001,10,6.RA,6.RB,_IMM32:IMEM:long:mu:STHH long
2134 "sthh r<RA>, @(r<RB>, <imm>)"
2135 do_sthh(_SD, val_Ra, Rb, imm);
2141 void::function::do_stw:unsigned32 ra, unsigned32 rb, unsigned32 src
2142 STORE(rb + src, 4, ra);
2144 _IMEM,10100,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:STW
2145 "stw r<RA>, @(r<RB>, <SRC_6>)":XX == 0
2146 "stw r<RA>, @(r<RB>%s<XX>, r<SRC_6>)"
2147 do_stw(_SD, val_Ra, Rb, src);
2148 do_incr(_SD, XX, &GPR[RB], 4);
2149 _IMEM,10100,10,6.RA,6.RB,_IMM32:IMEM:long:mu:STW long
2150 "stw r<RA>, @(r<RB>, <imm>)"
2151 do_stw(_SD, val_Ra, Rb, imm);
2157 void::function::do_sub:unsigned32 *ra, unsigned32 rb, unsigned32 imm
2162 _IALU1,00010,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:SUB
2163 "sub r<RA>, r<RB>, r<RC>"
2164 do_sub (_SD, Ra, Rb, Rc);
2165 _IALU1,00010,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:SUB imm
2166 "sub r<RA>, r<RB>, <imm>"
2167 do_sub (_SD, Ra, Rb, imm);
2168 _IALU1,00010,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:SUB imm long
2169 "sub r<RA>, r<RB>, <imm>"
2170 do_sub (_SD, Ra, Rb, imm);
2176 void::function::do_sub2h:unsigned32 *ra, unsigned32 rb, unsigned32 imm
2177 unsigned16 high = VH2_4(rb) - VH2_4(imm);
2178 unsigned16 low = VL2_4(rb) - VL2_4(imm);
2179 WRITE32_QUEUE (ra, (high << 16) | low);
2181 _IALU1,00011,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:SUB2H
2182 "sub2h r<RA>, r<RB>, r<RC>"
2183 do_sub2h (_SD, Ra, Rb, Rc);
2184 _IALU1,00011,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:SUB2H imm
2185 "sub2h r<RA>, r<RB>, <imm>"
2186 do_sub2h (_SD, Ra, Rb, immHL);
2187 _IALU1,00011,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:SUB2H imm long
2188 "sub2h r<RA>, r<RB>, <imm>"
2189 do_sub2h (_SD, Ra, Rb, imm);
2195 void::function::do_subb:unsigned32 *ra, unsigned32 rb, unsigned32 imm
2197 ALU_SUBB_B(imm, ALU_CARRY);
2200 _IALU1,00101,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:SUBB
2201 "subb r<RA>, r<RB>, r<RC>"
2202 do_subb (_SD, Ra, Rb, Rc);
2203 _IALU1,00101,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:SUBB imm
2204 "subb r<RA>, r<RB>, <imm>"
2205 do_subb (_SD, Ra, Rb, imm);
2206 _IALU1,00101,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:SUBB imm long
2207 "subb r<RA>, r<RB>, <imm>"
2208 do_subb (_SD, Ra, Rb, imm);
2214 void::function::do_subh_ppp:int ppp, unsigned32 *ra, unsigned32 rb, unsigned32 src
2218 ALU16_BEGIN(VL2_4(rb));
2219 ALU16_SUBB(VL2_4(src));
2225 ALU16_BEGIN(VL2_4(rb));
2226 ALU16_SUBB(VH2_4(src));
2232 ALU16_BEGIN(VH2_4(rb));
2233 ALU16_SUBB(VL2_4(src));
2239 ALU16_BEGIN(VH2_4(rb));
2240 ALU16_SUBB(VH2_4(src));
2246 ALU16_BEGIN(VL2_4(rb));
2247 ALU16_SUBB(VL2_4(src));
2253 ALU16_BEGIN(VL2_4(rb));
2254 ALU16_SUBB(VH2_4(src));
2260 ALU16_BEGIN(VH2_4(rb));
2261 ALU16_SUBB(VL2_4(src));
2267 ALU16_BEGIN(VH2_4(rb));
2268 ALU16_SUBB(VH2_4(src));
2273 sim_engine_abort (SD, CPU, cia, "do_subh_ppp - internal error - bad switch");
2276 _IALU1,11,ppp,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:SUBHppp
2277 "subh%s<ppp> r<RA>, r<RB>, r<RC>"
2278 do_subh_ppp(_SD, ppp, Ra, Rb, Rc);
2279 _IALU1,11,ppp,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:SUBHppp imm
2280 "subh%s<ppp> r<RA>, r<RB>, <imm>"
2281 do_subh_ppp(_SD, ppp, Ra, Rb, immHL);
2282 _IALU1,11,ppp,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:SUBHppp imm long
2283 "subh%s<ppp> r<RA>, r<RB>, <imm>"
2284 do_subh_ppp(_SD, ppp, Ra, Rb, imm);
2290 address_word::function::do_trap:address_word trap_vector, address_word nia
2291 /* Steal trap 31 for doing system calls */
2292 /* System calls are defined in libgloss/d30v/syscall.h. */
2293 if (trap_vector == EIT_VB + 0x20 + (31 << 3))
2295 enum { PARM1 = 2, PARM2, PARM3, PARM4, FUNC };
2296 if (GPR[FUNC] == 1) /* exit */
2298 sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, cia, sim_exited,
2300 return -1; /* dummy */
2306 CB_SYSCALL_INIT (&syscall);
2307 syscall.arg1 = GPR[PARM1];
2308 syscall.arg2 = GPR[PARM2];
2309 syscall.arg3 = GPR[PARM3];
2310 syscall.arg4 = GPR[PARM4];
2311 syscall.func = GPR[FUNC];
2312 syscall.p1 = (PTR) SD;
2313 syscall.read_mem = d30v_read_mem;
2314 syscall.write_mem = d30v_write_mem;
2316 WRITE32_QUEUE (&GPR[PARM1],
2317 ((cb_syscall (STATE_CALLBACK (SD), &syscall)
2320 : -syscall.errcode));
2324 else if (TRACE_TRAP_P)
2327 sim_io_eprintf (sd, "\nTrap %ld:\n", (long) ((trap_vector - (EIT_VB + 0x20)) >> 3));
2328 for (reg = 0; reg < NR_GENERAL_PURPOSE_REGISTERS; reg += 8)
2330 sim_io_eprintf (sd, "r%.2d - r%.2d: ", reg, reg+7);
2331 for (i = 0; i < 8; i++)
2332 sim_io_eprintf (sd, " 0x%.8lx", (long) GPR[reg+i]);
2333 sim_io_eprintf (sd, "\n");
2336 for (reg = 0; reg < 16; reg += 8)
2338 sim_io_eprintf (sd, "cr%.2d - cr%.2d:", reg, reg+7);
2339 for (i = 0; i < 8; i++)
2340 sim_io_eprintf (sd, " 0x%.8lx", (long) CREG[reg+i]);
2341 sim_io_eprintf (sd, "\n");
2344 sim_io_eprintf (sd, "a0 - a1: ");
2345 for (reg = 0; reg < NR_ACCUMULATORS; reg++)
2346 sim_io_eprintf (sd, " 0x%.8lx 0x%.8lx",
2347 (long)EXTRACTED64(ACC[reg], 0, 31),
2348 (long)EXTRACTED64(ACC[reg], 32, 63));
2349 sim_io_eprintf (sd, "\n");
2351 sim_io_eprintf (sd, "f0 - f7: ");
2352 sim_io_eprintf (sd, " (f0) %d", (int) PSW_VAL(PSW_F0));
2353 sim_io_eprintf (sd, " (f1) %d", (int) PSW_VAL(PSW_F1));
2354 sim_io_eprintf (sd, " (f2) %d", (int) PSW_VAL(PSW_F2));
2355 sim_io_eprintf (sd, " (f3) %d", (int) PSW_VAL(PSW_F3));
2356 sim_io_eprintf (sd, " (s) %d", (int) PSW_VAL(PSW_S));
2357 sim_io_eprintf (sd, " (v) %d", (int) PSW_VAL(PSW_V));
2358 sim_io_eprintf (sd, " (va) %d", (int) PSW_VAL(PSW_VA));
2359 sim_io_eprintf (sd, " (c) %d\n", (int) PSW_VAL(PSW_C));
2361 sim_io_eprintf (sd, "pswh: ");
2362 sim_io_eprintf (sd, " (sm) %d", (int) PSW_VAL(PSW_SM));
2363 sim_io_eprintf (sd, " (ea) %d", (int) PSW_VAL(PSW_EA));
2364 sim_io_eprintf (sd, " (ie) %d", (int) PSW_VAL(PSW_IE));
2365 sim_io_eprintf (sd, " (rp) %d", (int) PSW_VAL(PSW_RP));
2366 sim_io_eprintf (sd, " (md) %d", (int) PSW_VAL(PSW_MD));
2368 if (PSW_VAL(PSW_DB))
2369 sim_io_eprintf (sd, " (db) %d", (int) PSW_VAL(PSW_DB));
2371 if (PSW_VAL(PSW_DS))
2372 sim_io_eprintf (sd, " (ds) %d", (int) PSW_VAL(PSW_DS));
2374 sim_io_eprintf (sd, "\n");
2379 if(PSW_VAL(PSW_RP) && RPT_E == cia)
2381 WRITE32_QUEUE (&bPC, RPT_S);
2383 PSW_SET (PSW_RP, 0);
2386 WRITE32_QUEUE (&bPC, cia + 8);
2391 _BRA,01001,00,6.**,6.**,6.RC:BRA:short:mu:TRAP
2393 nia = do_trap (_SD, EIT_VB + 0x20 + MASKED32(Rc, 24, 28), nia);
2394 _BRA,01001,10,6.**,6.**,_IMM6:BRA:short:mu:TRAP imm
2396 nia = do_trap (_SD, EIT_VB + 0x20 + (imm_5 << 3), nia);
2402 _LOGIC,11011,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:XOR
2403 "xor r<RA>, r<RB>, r<RC>"
2404 WRITE32_QUEUE (Ra, Rb ^ Rc);
2405 _LOGIC,11011,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:XOR imm
2406 "xor r<RA>, r<RB>, <imm>"
2407 WRITE32_QUEUE (Ra, Rb ^ imm);
2408 _LOGIC,11011,10,6.RA,6.RB,_IMM32:LOGIC:long:iu,mu:XOR imm long
2409 "xor r<RA>, r<RB>, <imm>"
2410 WRITE32_QUEUE (Ra, Rb ^ imm);
2416 _LOGIC,01011,00,***,3.FA,***,3.FB,***,3.FC:LOGIC:short:iu,mu:XORFG
2417 "xorfg f<FA>, f<FB>, f<FC>"
2418 PSW_FLAG_SET_QUEUE(FA, PSW_FLAG_VAL(FB) ^ PSW_FLAG_VAL(FC));
2419 _LOGIC,01011,10,***,3.FA,***,3.FB,_IMM6:LOGIC:short:iu,mu:XORFG imm
2420 "xorfg f<FA>, f<FB>, <imm_6>"
2421 PSW_FLAG_SET_QUEUE(FA, PSW_FLAG_VAL(FB) ^ (imm_6 & 1));