sim/erc32/ChangeLog

   1 version 2.1 26-02-96
   2 --------------------
   3
   4 * Fixed bug in "go" command.
   5
   6 version 2.0 05-02-96
   7 --------------------
   8
   9 * Fixed bug in interrupt force register (erc32.c).
  10
  11 * Change file load function to use bfd_openr.
  12
  13 * SIS should now be endian independent.
  14
  15 version 1.8 24-11-95
  16 --------------------
  17
  18 * Fixed FPU timing - some sequences of FPU instructions did not calculate
  19   the resource dependencies right.
  20
  21 * Corrected STDFQ when qne = 0 (again!). The ftt is set to sequence_error
  22   but no FPU trap is generated.
  23
  24 version 1.7.1 31-10-95
  25 --------------------
  26
  27 * Corrected STDFQ when qne = 0. Now, a trap is immidiately generated but
  28   the FPU stays in execute mode.
  29
  30 * Corrected JMPL and RETT timing (these instructions takes two cycles).
  31
  32
  33 version 1.7 25-10-95
  34 --------------------
  35
  36 * Interrupt during annuled instruction corrupted return address - fixed.
  37
  38
  39 version 1.6.2 25-10-95
  40 --------------------
  41
  42 * Added -DFAST_UART to Makefile
  43
  44
  45 version 1.6.1 24-10-95
  46 --------------------
  47
  48 * Fixed bug in STDFQ which caused bus error
  49
  50
  51 version 1.6 02-10-95
  52 --------------------
  53
  54 * Modified srt0.s to include code that initiates registers in IU and FPU
  55   and initializes the data segment. The simulator 'load' command does not
  56   longer initialize the data segment!
  57
  58 * Corrected MEC timer operation; scalers now divide the frequency by
  59   (scaler_value + 1).
  60
  61 * MEC breakpoints are not checked during store operation
  62
  63
  64 version 1.5 14-09-95
  65 --------------------
  66
  67 * Fixed some bugs in the cycle counting for IU & FPU instructions.
  68
  69 * Fixed bug that allowed an annuled instruction to cause memory exception.
  70
  71 * The *ws parameter in mem.c should now contain the number of waitstates
  72   required by the memory access (was total number of cycles).
  73
  74 * The supplied srt0.s now clears the BSS (thanks Joel).
  75
  76 version 1.4 22-08-95
  77 --------------------
  78
  79 * Added a '-g' switch to enable/disable the GNU readline(), which cause
  80 some problems on solaris 2.x machines.
  81
  82 * Enabled MEC watchpoint and breakpoint function to mem.c. Performance
  83 may suffer a bit ...
  84
  85 NOTE: The UARTs are now connected to /dev/ttypc and /dev/ttypd.
  86
  87 version 1.3 26-07-95
  88 --------------------
  89
  90 * Fixed bug in mulscc instruction (how could that ever have worked?)
  91
  92 * Fixed bug in UART B (flushed characters on UART A), thanks Paul.
  93
  94 version 1.2 13-07-95
  95 --------------------
  96
  97 * Fixed bug in interrupt handling (wrong interrupt selected when more that
  98 one interrupt pending)
  99
 100 * Fixed updating of condition codes during logical instructions (carry and
 101 overflow were not reset)
 102
 103 * Fixed bug in WRTBR (tt field was wrongly over-written)
 104
 105 version 1.1 07-07-95
 106 --------------------
 107
 108 * Fixed several bugs in the interrupt handler and callback routines.
 109 (reported by Paul Warren, Alsys)