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sim/erc32: Perform pseudo-init if binary linked to non-zero address.
[deliverable/binutils-gdb.git] / sim / erc32 / erc32.c
1 /*
2 * This file is part of SIS.
3 *
4 * SIS, SPARC instruction simulator V2.5 Copyright (C) 1995 Jiri Gaisler,
5 * European Space Agency
6 *
7 * This program is free software; you can redistribute it and/or modify it under
8 * the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 3 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, see <http://www.gnu.org/licenses/>.
19 *
20 */
21
22 /* The control space devices */
23
24 #include "config.h"
25 #include <sys/types.h>
26 #include <stdio.h>
27 #include <string.h>
28 #include <termios.h>
29 #include <sys/fcntl.h>
30 #include <sys/file.h>
31 #include <unistd.h>
32 #include "sis.h"
33 #include "end.h"
34 #include "sim-config.h"
35
36 extern int ctrl_c;
37 extern int32 sis_verbose;
38 extern int32 sparclite, sparclite_board;
39 extern int rom8,wrp,uben;
40 extern char uart_dev1[], uart_dev2[];
41
42 int dumbio = 0; /* normal, smart, terminal oriented IO by default */
43
44 /* MEC registers */
45 #define MEC_START 0x01f80000
46 #define MEC_END 0x01f80100
47
48 /* Memory exception waitstates */
49 #define MEM_EX_WS 1
50
51 /* ERC32 always adds one waitstate during RAM std */
52 #define STD_WS 1
53
54 #ifdef ERRINJ
55 extern int errmec;
56 #endif
57
58 /* The target's byte order is big-endian by default until we load a
59 little-endian program. */
60
61 int current_target_byte_order = BIG_ENDIAN;
62
63 #define MEC_WS 0 /* Waitstates per MEC access (0 ws) */
64 #define MOK 0
65
66 /* MEC register addresses */
67
68 #define MEC_MCR 0x000
69 #define MEC_SFR 0x004
70 #define MEC_PWDR 0x008
71 #define MEC_MEMCFG 0x010
72 #define MEC_IOCR 0x014
73 #define MEC_WCR 0x018
74
75 #define MEC_MAR0 0x020
76 #define MEC_MAR1 0x024
77
78 #define MEC_SSA1 0x020
79 #define MEC_SEA1 0x024
80 #define MEC_SSA2 0x028
81 #define MEC_SEA2 0x02C
82 #define MEC_ISR 0x044
83 #define MEC_IPR 0x048
84 #define MEC_IMR 0x04C
85 #define MEC_ICR 0x050
86 #define MEC_IFR 0x054
87 #define MEC_WDOG 0x060
88 #define MEC_TRAPD 0x064
89 #define MEC_RTC_COUNTER 0x080
90 #define MEC_RTC_RELOAD 0x080
91 #define MEC_RTC_SCALER 0x084
92 #define MEC_GPT_COUNTER 0x088
93 #define MEC_GPT_RELOAD 0x088
94 #define MEC_GPT_SCALER 0x08C
95 #define MEC_TIMER_CTRL 0x098
96 #define MEC_SFSR 0x0A0
97 #define MEC_FFAR 0x0A4
98 #define MEC_ERSR 0x0B0
99 #define MEC_DBG 0x0C0
100 #define MEC_TCR 0x0D0
101
102 #define MEC_BRK 0x0C4
103 #define MEC_WPR 0x0C8
104
105 #define MEC_UARTA 0x0E0
106 #define MEC_UARTB 0x0E4
107 #define MEC_UART_CTRL 0x0E8
108 #define SIM_LOAD 0x0F0
109
110 /* Memory exception causes */
111 #define PROT_EXC 0x3
112 #define UIMP_ACC 0x4
113 #define MEC_ACC 0x6
114 #define WATCH_EXC 0xa
115 #define BREAK_EXC 0xb
116
117 /* Size of UART buffers (bytes) */
118 #define UARTBUF 1024
119
120 /* Number of simulator ticks between flushing the UARTS. */
121 /* For good performance, keep above 1000 */
122 #define UART_FLUSH_TIME 3000
123
124 /* MEC timer control register bits */
125 #define TCR_GACR 1
126 #define TCR_GACL 2
127 #define TCR_GASE 4
128 #define TCR_GASL 8
129 #define TCR_TCRCR 0x100
130 #define TCR_TCRCL 0x200
131 #define TCR_TCRSE 0x400
132 #define TCR_TCRSL 0x800
133
134 /* New uart defines */
135 #define UART_TX_TIME 1000
136 #define UART_RX_TIME 1000
137 #define UARTA_DR 0x1
138 #define UARTA_SRE 0x2
139 #define UARTA_HRE 0x4
140 #define UARTA_OR 0x40
141 #define UARTA_CLR 0x80
142 #define UARTB_DR 0x10000
143 #define UARTB_SRE 0x20000
144 #define UARTB_HRE 0x40000
145 #define UARTB_OR 0x400000
146 #define UARTB_CLR 0x800000
147
148 #define UART_DR 0x100
149 #define UART_TSE 0x200
150 #define UART_THE 0x400
151
152 /* MEC registers */
153
154 static char fname[256];
155 static int32 find = 0;
156 static uint32 mec_ssa[2]; /* Write protection start address */
157 static uint32 mec_sea[2]; /* Write protection end address */
158 static uint32 mec_wpr[2]; /* Write protection control fields */
159 static uint32 mec_sfsr;
160 static uint32 mec_ffar;
161 static uint32 mec_ipr;
162 static uint32 mec_imr;
163 static uint32 mec_isr;
164 static uint32 mec_icr;
165 static uint32 mec_ifr;
166 static uint32 mec_mcr; /* MEC control register */
167 static uint32 mec_memcfg; /* Memory control register */
168 static uint32 mec_wcr; /* MEC waitstate register */
169 static uint32 mec_iocr; /* MEC IO control register */
170 static uint32 posted_irq;
171 static uint32 mec_ersr; /* MEC error and status register */
172 static uint32 mec_tcr; /* MEC test comtrol register */
173
174 static uint32 rtc_counter;
175 static uint32 rtc_reload;
176 static uint32 rtc_scaler;
177 static uint32 rtc_scaler_start;
178 static uint32 rtc_enabled;
179 static uint32 rtc_cr;
180 static uint32 rtc_se;
181
182 static uint32 gpt_counter;
183 static uint32 gpt_reload;
184 static uint32 gpt_scaler;
185 static uint32 gpt_scaler_start;
186 static uint32 gpt_enabled;
187 static uint32 gpt_cr;
188 static uint32 gpt_se;
189
190 static uint32 wdog_scaler;
191 static uint32 wdog_counter;
192 static uint32 wdog_rst_delay;
193 static uint32 wdog_rston;
194
195 enum wdog_type {
196 init, disabled, enabled, stopped
197 };
198
199 static enum wdog_type wdog_status;
200
201
202 /* ROM size 1024 Kbyte */
203 #define ROM_SZ 0x100000
204 #define ROM_MASK 0x0fffff
205
206 /* RAM size 4 Mbyte */
207 #define RAM_START 0x02000000
208 #define RAM_END 0x02400000
209 #define RAM_MASK 0x003fffff
210
211 /* SPARClite boards all seem to have RAM at the same place. */
212 #define RAM_START_SLITE 0x40000000
213 #define RAM_END_SLITE 0x40400000
214 #define RAM_MASK_SLITE 0x003fffff
215
216 /* Memory support variables */
217
218 static uint32 mem_ramr_ws; /* RAM read waitstates */
219 static uint32 mem_ramw_ws; /* RAM write waitstates */
220 static uint32 mem_romr_ws; /* ROM read waitstates */
221 static uint32 mem_romw_ws; /* ROM write waitstates */
222 static uint32 mem_ramstart; /* RAM start */
223 static uint32 mem_ramend; /* RAM end */
224 static uint32 mem_rammask; /* RAM address mask */
225 static uint32 mem_ramsz; /* RAM size */
226 static uint32 mem_romsz; /* ROM size */
227 static uint32 mem_accprot; /* RAM write protection enabled */
228 static uint32 mem_blockprot; /* RAM block write protection enabled */
229
230 static unsigned char romb[ROM_SZ];
231 static unsigned char ramb[RAM_END - RAM_START];
232
233
234 /* UART support variables */
235
236 static int32 fd1, fd2; /* file descriptor for input file */
237 static int32 Ucontrol; /* UART status register */
238 static unsigned char aq[UARTBUF], bq[UARTBUF];
239 static int32 anum, aind = 0;
240 static int32 bnum, bind = 0;
241 static char wbufa[UARTBUF], wbufb[UARTBUF];
242 static unsigned wnuma;
243 static unsigned wnumb;
244 static FILE *f1in, *f1out, *f2in, *f2out;
245 static struct termios ioc1, ioc2, iocold1, iocold2;
246 static int f1open = 0, f2open = 0;
247
248 static char uarta_sreg, uarta_hreg, uartb_sreg, uartb_hreg;
249 static uint32 uart_stat_reg;
250 static uint32 uarta_data, uartb_data;
251
252 #ifdef ERA
253 int era = 0;
254 int erareg;
255 #endif
256
257 /* Forward declarations */
258
259 static void decode_ersr (void);
260 #ifdef ERRINJ
261 static void iucomperr (void);
262 #endif
263 static void mecparerror (void);
264 static void decode_memcfg (void);
265 static void decode_wcr (void);
266 static void decode_mcr (void);
267 static void close_port (void);
268 static void mec_reset (void);
269 static void mec_intack (int32 level);
270 static void chk_irq (void);
271 static void mec_irq (int32 level);
272 static void set_sfsr (uint32 fault, uint32 addr,
273 uint32 asi, uint32 read);
274 static int32 mec_read (uint32 addr, uint32 asi, uint32 *data);
275 static int mec_write (uint32 addr, uint32 data);
276 static void port_init (void);
277 static uint32 read_uart (uint32 addr);
278 static void write_uart (uint32 addr, uint32 data);
279 static void flush_uart (void);
280 static void uarta_tx (void);
281 static void uartb_tx (void);
282 static void uart_rx (caddr_t arg);
283 static void uart_intr (caddr_t arg);
284 static void uart_irq_start (void);
285 static void wdog_intr (caddr_t arg);
286 static void wdog_start (void);
287 static void rtc_intr (caddr_t arg);
288 static void rtc_start (void);
289 static uint32 rtc_counter_read (void);
290 static void rtc_scaler_set (uint32 val);
291 static void rtc_reload_set (uint32 val);
292 static void gpt_intr (caddr_t arg);
293 static void gpt_start (void);
294 static uint32 gpt_counter_read (void);
295 static void gpt_scaler_set (uint32 val);
296 static void gpt_reload_set (uint32 val);
297 static void timer_ctrl (uint32 val);
298 static unsigned char *
299 get_mem_ptr (uint32 addr, uint32 size);
300
301 static void fetch_bytes (int asi, unsigned char *mem,
302 uint32 *data, int sz);
303
304 static void store_bytes (unsigned char *mem, uint32 *data, int sz);
305
306 extern int ext_irl;
307
308
309 /* One-time init */
310
311 void
312 init_sim()
313 {
314 port_init();
315 }
316
317 /* Power-on reset init */
318
319 void
320 reset()
321 {
322 mec_reset();
323 uart_irq_start();
324 wdog_start();
325 }
326
327 static void
328 decode_ersr()
329 {
330 if (mec_ersr & 0x01) {
331 if (!(mec_mcr & 0x20)) {
332 if (mec_mcr & 0x40) {
333 sys_reset();
334 mec_ersr = 0x8000;
335 if (sis_verbose)
336 printf("Error manager reset - IU in error mode\n");
337 } else {
338 sys_halt();
339 mec_ersr |= 0x2000;
340 if (sis_verbose)
341 printf("Error manager halt - IU in error mode\n");
342 }
343 } else
344 mec_irq(1);
345 }
346 if (mec_ersr & 0x04) {
347 if (!(mec_mcr & 0x200)) {
348 if (mec_mcr & 0x400) {
349 sys_reset();
350 mec_ersr = 0x8000;
351 if (sis_verbose)
352 printf("Error manager reset - IU comparison error\n");
353 } else {
354 sys_halt();
355 mec_ersr |= 0x2000;
356 if (sis_verbose)
357 printf("Error manager halt - IU comparison error\n");
358 }
359 } else
360 mec_irq(1);
361 }
362 if (mec_ersr & 0x20) {
363 if (!(mec_mcr & 0x2000)) {
364 if (mec_mcr & 0x4000) {
365 sys_reset();
366 mec_ersr = 0x8000;
367 if (sis_verbose)
368 printf("Error manager reset - MEC hardware error\n");
369 } else {
370 sys_halt();
371 mec_ersr |= 0x2000;
372 if (sis_verbose)
373 printf("Error manager halt - MEC hardware error\n");
374 }
375 } else
376 mec_irq(1);
377 }
378 }
379
380 #ifdef ERRINJ
381 static void
382 iucomperr()
383 {
384 mec_ersr |= 0x04;
385 decode_ersr();
386 }
387 #endif
388
389 static void
390 mecparerror()
391 {
392 mec_ersr |= 0x20;
393 decode_ersr();
394 }
395
396
397 /* IU error mode manager */
398
399 void
400 error_mode(pc)
401 uint32 pc;
402 {
403
404 mec_ersr |= 0x1;
405 decode_ersr();
406 }
407
408
409 /* Check memory settings */
410
411 static void
412 decode_memcfg()
413 {
414 if (rom8) mec_memcfg &= ~0x20000;
415 else mec_memcfg |= 0x20000;
416
417 mem_ramsz = (256 * 1024) << ((mec_memcfg >> 10) & 7);
418 mem_romsz = (128 * 1024) << ((mec_memcfg >> 18) & 7);
419
420 if (sparclite_board) {
421 mem_ramstart = RAM_START_SLITE;
422 mem_ramend = RAM_END_SLITE;
423 mem_rammask = RAM_MASK_SLITE;
424 }
425 else {
426 mem_ramstart = RAM_START;
427 mem_ramend = RAM_END;
428 mem_rammask = RAM_MASK;
429 }
430 if (sis_verbose)
431 printf("RAM start: 0x%x, RAM size: %d K, ROM size: %d K\n",
432 mem_ramstart, mem_ramsz >> 10, mem_romsz >> 10);
433 }
434
435 static void
436 decode_wcr()
437 {
438 mem_ramr_ws = mec_wcr & 3;
439 mem_ramw_ws = (mec_wcr >> 2) & 3;
440 mem_romr_ws = (mec_wcr >> 4) & 0x0f;
441 if (rom8) {
442 if (mem_romr_ws > 0 ) mem_romr_ws--;
443 mem_romr_ws = 5 + (4*mem_romr_ws);
444 }
445 mem_romw_ws = (mec_wcr >> 8) & 0x0f;
446 if (sis_verbose)
447 printf("Waitstates = RAM read: %d, RAM write: %d, ROM read: %d, ROM write: %d\n",
448 mem_ramr_ws, mem_ramw_ws, mem_romr_ws, mem_romw_ws);
449 }
450
451 static void
452 decode_mcr()
453 {
454 mem_accprot = (mec_wpr[0] | mec_wpr[1]);
455 mem_blockprot = (mec_mcr >> 3) & 1;
456 if (sis_verbose && mem_accprot)
457 printf("Memory block write protection enabled\n");
458 if (mec_mcr & 0x08000) {
459 mec_ersr |= 0x20;
460 decode_ersr();
461 }
462 if (sis_verbose && (mec_mcr & 2))
463 printf("Software reset enabled\n");
464 if (sis_verbose && (mec_mcr & 1))
465 printf("Power-down mode enabled\n");
466 }
467
468 /* Flush ports when simulator stops */
469
470 void
471 sim_halt()
472 {
473 #ifdef FAST_UART
474 flush_uart();
475 #endif
476 }
477
478 int
479 sim_stop(SIM_DESC sd)
480 {
481 ctrl_c = 1;
482 return 1;
483 }
484
485 static void
486 close_port()
487 {
488 if (f1open && f1in != stdin)
489 fclose(f1in);
490 if (f2open && f2in != stdin)
491 fclose(f2in);
492 }
493
494 void
495 exit_sim()
496 {
497 close_port();
498 }
499
500 static void
501 mec_reset()
502 {
503 int i;
504
505 find = 0;
506 for (i = 0; i < 2; i++)
507 mec_ssa[i] = mec_sea[i] = mec_wpr[i] = 0;
508 mec_mcr = 0x01350014;
509 mec_iocr = 0;
510 mec_sfsr = 0x078;
511 mec_ffar = 0;
512 mec_ipr = 0;
513 mec_imr = 0x7ffe;
514 mec_isr = 0;
515 mec_icr = 0;
516 mec_ifr = 0;
517 mec_memcfg = 0x10000;
518 mec_wcr = -1;
519 mec_ersr = 0; /* MEC error and status register */
520 mec_tcr = 0; /* MEC test comtrol register */
521
522 decode_memcfg();
523 decode_wcr();
524 decode_mcr();
525
526 posted_irq = 0;
527 wnuma = wnumb = 0;
528 anum = aind = bnum = bind = 0;
529
530 uart_stat_reg = UARTA_SRE | UARTA_HRE | UARTB_SRE | UARTB_HRE;
531 uarta_data = uartb_data = UART_THE | UART_TSE;
532
533 rtc_counter = 0xffffffff;
534 rtc_reload = 0xffffffff;
535 rtc_scaler = 0xff;
536 rtc_enabled = 0;
537 rtc_cr = 0;
538 rtc_se = 0;
539
540 gpt_counter = 0xffffffff;
541 gpt_reload = 0xffffffff;
542 gpt_scaler = 0xffff;
543 gpt_enabled = 0;
544 gpt_cr = 0;
545 gpt_se = 0;
546
547 wdog_scaler = 255;
548 wdog_rst_delay = 255;
549 wdog_counter = 0xffff;
550 wdog_rston = 0;
551 wdog_status = init;
552
553 #ifdef ERA
554 erareg = 0;
555 #endif
556
557 }
558
559
560
561 static void
562 mec_intack(level)
563 int32 level;
564 {
565 int irq_test;
566
567 if (sis_verbose)
568 printf("interrupt %d acknowledged\n", level);
569 irq_test = mec_tcr & 0x80000;
570 if ((irq_test) && (mec_ifr & (1 << level)))
571 mec_ifr &= ~(1 << level);
572 else
573 mec_ipr &= ~(1 << level);
574 chk_irq();
575 }
576
577 static void
578 chk_irq()
579 {
580 int32 i;
581 uint32 itmp;
582 int old_irl;
583
584 old_irl = ext_irl;
585 if (mec_tcr & 0x80000) itmp = mec_ifr;
586 else itmp = 0;
587 itmp = ((mec_ipr | itmp) & ~mec_imr) & 0x0fffe;
588 ext_irl = 0;
589 if (itmp != 0) {
590 for (i = 15; i > 0; i--) {
591 if (((itmp >> i) & 1) != 0) {
592 if ((sis_verbose) && (i > old_irl))
593 printf("IU irl: %d\n", i);
594 ext_irl = i;
595 set_int(i, mec_intack, i);
596 break;
597 }
598 }
599 }
600 }
601
602 static void
603 mec_irq(level)
604 int32 level;
605 {
606 mec_ipr |= (1 << level);
607 chk_irq();
608 }
609
610 static void
611 set_sfsr(fault, addr, asi, read)
612 uint32 fault;
613 uint32 addr;
614 uint32 asi;
615 uint32 read;
616 {
617 if ((asi == 0xa) || (asi == 0xb)) {
618 mec_ffar = addr;
619 mec_sfsr = (fault << 3) | (!read << 15);
620 mec_sfsr |= ((mec_sfsr & 1) ^ 1) | (mec_sfsr & 1);
621 switch (asi) {
622 case 0xa:
623 mec_sfsr |= 0x0004;
624 break;
625 case 0xb:
626 mec_sfsr |= 0x1004;
627 break;
628 }
629 }
630 }
631
632 static int32
633 mec_read(addr, asi, data)
634 uint32 addr;
635 uint32 asi;
636 uint32 *data;
637 {
638
639 switch (addr & 0x0ff) {
640
641 case MEC_MCR: /* 0x00 */
642 *data = mec_mcr;
643 break;
644
645 case MEC_MEMCFG: /* 0x10 */
646 *data = mec_memcfg;
647 break;
648
649 case MEC_IOCR:
650 *data = mec_iocr; /* 0x14 */
651 break;
652
653 case MEC_SSA1: /* 0x20 */
654 *data = mec_ssa[0] | (mec_wpr[0] << 23);
655 break;
656 case MEC_SEA1: /* 0x24 */
657 *data = mec_sea[0];
658 break;
659 case MEC_SSA2: /* 0x28 */
660 *data = mec_ssa[1] | (mec_wpr[1] << 23);
661 break;
662 case MEC_SEA2: /* 0x2c */
663 *data = mec_sea[1];
664 break;
665
666 case MEC_ISR: /* 0x44 */
667 *data = mec_isr;
668 break;
669
670 case MEC_IPR: /* 0x48 */
671 *data = mec_ipr;
672 break;
673
674 case MEC_IMR: /* 0x4c */
675 *data = mec_imr;
676 break;
677
678 case MEC_IFR: /* 0x54 */
679 *data = mec_ifr;
680 break;
681
682 case MEC_RTC_COUNTER: /* 0x80 */
683 *data = rtc_counter_read();
684 break;
685 case MEC_RTC_SCALER: /* 0x84 */
686 if (rtc_enabled)
687 *data = rtc_scaler - (now() - rtc_scaler_start);
688 else
689 *data = rtc_scaler;
690 break;
691
692 case MEC_GPT_COUNTER: /* 0x88 */
693 *data = gpt_counter_read();
694 break;
695
696 case MEC_GPT_SCALER: /* 0x8c */
697 if (rtc_enabled)
698 *data = gpt_scaler - (now() - gpt_scaler_start);
699 else
700 *data = gpt_scaler;
701 break;
702
703
704 case MEC_SFSR: /* 0xA0 */
705 *data = mec_sfsr;
706 break;
707
708 case MEC_FFAR: /* 0xA4 */
709 *data = mec_ffar;
710 break;
711
712 case SIM_LOAD:
713 fname[find] = 0;
714 if (find == 0)
715 strcpy(fname, "simload");
716 find = bfd_load(fname);
717 if (find == -1)
718 *data = 0;
719 else
720 *data = 1;
721 find = 0;
722 break;
723
724 case MEC_ERSR: /* 0xB0 */
725 *data = mec_ersr;
726 break;
727
728 case MEC_TCR: /* 0xD0 */
729 *data = mec_tcr;
730 break;
731
732 case MEC_UARTA: /* 0xE0 */
733 case MEC_UARTB: /* 0xE4 */
734 if (asi != 0xb) {
735 set_sfsr(MEC_ACC, addr, asi, 1);
736 return (1);
737 }
738 *data = read_uart(addr);
739 break;
740
741 case MEC_UART_CTRL: /* 0xE8 */
742
743 *data = read_uart(addr);
744 break;
745
746 case 0xF4: /* simulator RAM size in bytes */
747 *data = 4096*1024;
748 break;
749
750 case 0xF8: /* simulator ROM size in bytes */
751 *data = 1024*1024;
752 break;
753
754 default:
755 set_sfsr(MEC_ACC, addr, asi, 1);
756 return (1);
757 break;
758 }
759 return (MOK);
760 }
761
762 static int
763 mec_write(addr, data)
764 uint32 addr;
765 uint32 data;
766 {
767 if (sis_verbose > 1)
768 printf("MEC write a: %08x, d: %08x\n",addr,data);
769 switch (addr & 0x0ff) {
770
771 case MEC_MCR:
772 mec_mcr = data;
773 decode_mcr();
774 if (mec_mcr & 0x08000) mecparerror();
775 break;
776
777 case MEC_SFR:
778 if (mec_mcr & 0x2) {
779 sys_reset();
780 mec_ersr = 0x4000;
781 if (sis_verbose)
782 printf(" Software reset issued\n");
783 }
784 break;
785
786 case MEC_IOCR:
787 mec_iocr = data;
788 if (mec_iocr & 0xC0C0C0C0) mecparerror();
789 break;
790
791 case MEC_SSA1: /* 0x20 */
792 if (data & 0xFE000000) mecparerror();
793 mec_ssa[0] = data & 0x7fffff;
794 mec_wpr[0] = (data >> 23) & 0x03;
795 mem_accprot = mec_wpr[0] || mec_wpr[1];
796 if (sis_verbose && mec_wpr[0])
797 printf("Segment 1 memory protection enabled (0x02%06x - 0x02%06x)\n",
798 mec_ssa[0] << 2, mec_sea[0] << 2);
799 break;
800 case MEC_SEA1: /* 0x24 */
801 if (data & 0xFF800000) mecparerror();
802 mec_sea[0] = data & 0x7fffff;
803 break;
804 case MEC_SSA2: /* 0x28 */
805 if (data & 0xFE000000) mecparerror();
806 mec_ssa[1] = data & 0x7fffff;
807 mec_wpr[1] = (data >> 23) & 0x03;
808 mem_accprot = mec_wpr[0] || mec_wpr[1];
809 if (sis_verbose && mec_wpr[1])
810 printf("Segment 2 memory protection enabled (0x02%06x - 0x02%06x)\n",
811 mec_ssa[1] << 2, mec_sea[1] << 2);
812 break;
813 case MEC_SEA2: /* 0x2c */
814 if (data & 0xFF800000) mecparerror();
815 mec_sea[1] = data & 0x7fffff;
816 break;
817
818 case MEC_UARTA:
819 case MEC_UARTB:
820 if (data & 0xFFFFFF00) mecparerror();
821 case MEC_UART_CTRL:
822 if (data & 0xFF00FF00) mecparerror();
823 write_uart(addr, data);
824 break;
825
826 case MEC_GPT_RELOAD:
827 gpt_reload_set(data);
828 break;
829
830 case MEC_GPT_SCALER:
831 if (data & 0xFFFF0000) mecparerror();
832 gpt_scaler_set(data);
833 break;
834
835 case MEC_TIMER_CTRL:
836 if (data & 0xFFFFF0F0) mecparerror();
837 timer_ctrl(data);
838 break;
839
840 case MEC_RTC_RELOAD:
841 rtc_reload_set(data);
842 break;
843
844 case MEC_RTC_SCALER:
845 if (data & 0xFFFFFF00) mecparerror();
846 rtc_scaler_set(data);
847 break;
848
849 case MEC_SFSR: /* 0xA0 */
850 if (data & 0xFFFF0880) mecparerror();
851 mec_sfsr = 0x78;
852 break;
853
854 case MEC_ISR:
855 if (data & 0xFFFFE000) mecparerror();
856 mec_isr = data;
857 break;
858
859 case MEC_IMR: /* 0x4c */
860
861 if (data & 0xFFFF8001) mecparerror();
862 mec_imr = data & 0x7ffe;
863 chk_irq();
864 break;
865
866 case MEC_ICR: /* 0x50 */
867
868 if (data & 0xFFFF0001) mecparerror();
869 mec_ipr &= ~data & 0x0fffe;
870 chk_irq();
871 break;
872
873 case MEC_IFR: /* 0x54 */
874
875 if (mec_tcr & 0x080000) {
876 if (data & 0xFFFF0001) mecparerror();
877 mec_ifr = data & 0xfffe;
878 chk_irq();
879 }
880 break;
881 case SIM_LOAD:
882 fname[find++] = (char) data;
883 break;
884
885
886 case MEC_MEMCFG: /* 0x10 */
887 if (data & 0xC0E08000) mecparerror();
888 mec_memcfg = data;
889 decode_memcfg();
890 if (mec_memcfg & 0xc0e08000)
891 mecparerror();
892 break;
893
894 case MEC_WCR: /* 0x18 */
895 mec_wcr = data;
896 decode_wcr();
897 break;
898
899 case MEC_ERSR: /* 0xB0 */
900 if (mec_tcr & 0x100000)
901 if (data & 0xFFFFEFC0) mecparerror();
902 mec_ersr = data & 0x103f;
903 break;
904
905 case MEC_TCR: /* 0xD0 */
906 if (data & 0xFFE1FFC0) mecparerror();
907 mec_tcr = data & 0x1e003f;
908 break;
909
910 case MEC_WDOG: /* 0x60 */
911 wdog_scaler = (data >> 16) & 0x0ff;
912 wdog_counter = data & 0x0ffff;
913 wdog_rst_delay = data >> 24;
914 wdog_rston = 0;
915 if (wdog_status == stopped)
916 wdog_start();
917 wdog_status = enabled;
918 break;
919
920 case MEC_TRAPD: /* 0x64 */
921 if (wdog_status == init) {
922 wdog_status = disabled;
923 if (sis_verbose)
924 printf("Watchdog disabled\n");
925 }
926 break;
927
928 case MEC_PWDR:
929 if (mec_mcr & 1)
930 wait_for_irq();
931 break;
932
933 default:
934 set_sfsr(MEC_ACC, addr, 0xb, 0);
935 return (1);
936 break;
937 }
938 return (MOK);
939 }
940
941
942 /* MEC UARTS */
943
944 static int ifd1 = -1, ifd2 = -1, ofd1 = -1, ofd2 = -1;
945
946 void
947 init_stdio()
948 {
949 if (dumbio)
950 return; /* do nothing */
951 if (!ifd1)
952 tcsetattr(0, TCSANOW, &ioc1);
953 if (!ifd2)
954 tcsetattr(0, TCSANOW, &ioc2);
955 }
956
957 void
958 restore_stdio()
959 {
960 if (dumbio)
961 return; /* do nothing */
962 if (!ifd1)
963 tcsetattr(0, TCSANOW, &iocold1);
964 if (!ifd2)
965 tcsetattr(0, TCSANOW, &iocold2);
966 }
967
968 #define DO_STDIO_READ( _fd_, _buf_, _len_ ) \
969 ( dumbio \
970 ? (0) /* no bytes read, no delay */ \
971 : read( _fd_, _buf_, _len_ ) )
972
973
974 static void
975 port_init()
976 {
977
978 if (uben) {
979 f2in = stdin;
980 f1in = NULL;
981 f2out = stdout;
982 f1out = NULL;
983 } else {
984 f1in = stdin;
985 f2in = NULL;
986 f1out = stdout;
987 f2out = NULL;
988 }
989 if (uart_dev1[0] != 0)
990 if ((fd1 = open(uart_dev1, O_RDWR | O_NONBLOCK)) < 0) {
991 printf("Warning, couldn't open output device %s\n", uart_dev1);
992 } else {
993 if (sis_verbose)
994 printf("serial port A on %s\n", uart_dev1);
995 f1in = f1out = fdopen(fd1, "r+");
996 setbuf(f1out, NULL);
997 f1open = 1;
998 }
999 if (f1in) ifd1 = fileno(f1in);
1000 if (ifd1 == 0) {
1001 if (sis_verbose)
1002 printf("serial port A on stdin/stdout\n");
1003 if (!dumbio) {
1004 tcgetattr(ifd1, &ioc1);
1005 iocold1 = ioc1;
1006 ioc1.c_lflag &= ~(ICANON | ECHO);
1007 ioc1.c_cc[VMIN] = 0;
1008 ioc1.c_cc[VTIME] = 0;
1009 }
1010 f1open = 1;
1011 }
1012
1013 if (f1out) {
1014 ofd1 = fileno(f1out);
1015 if (!dumbio && ofd1 == 1) setbuf(f1out, NULL);
1016 }
1017
1018 if (uart_dev2[0] != 0)
1019 if ((fd2 = open(uart_dev2, O_RDWR | O_NONBLOCK)) < 0) {
1020 printf("Warning, couldn't open output device %s\n", uart_dev2);
1021 } else {
1022 if (sis_verbose)
1023 printf("serial port B on %s\n", uart_dev2);
1024 f2in = f2out = fdopen(fd2, "r+");
1025 setbuf(f2out, NULL);
1026 f2open = 1;
1027 }
1028 if (f2in) ifd2 = fileno(f2in);
1029 if (ifd2 == 0) {
1030 if (sis_verbose)
1031 printf("serial port B on stdin/stdout\n");
1032 if (!dumbio) {
1033 tcgetattr(ifd2, &ioc2);
1034 iocold2 = ioc2;
1035 ioc2.c_lflag &= ~(ICANON | ECHO);
1036 ioc2.c_cc[VMIN] = 0;
1037 ioc2.c_cc[VTIME] = 0;
1038 }
1039 f2open = 1;
1040 }
1041
1042 if (f2out) {
1043 ofd2 = fileno(f2out);
1044 if (!dumbio && ofd2 == 1) setbuf(f2out, NULL);
1045 }
1046
1047 wnuma = wnumb = 0;
1048
1049 }
1050
1051 static uint32
1052 read_uart(addr)
1053 uint32 addr;
1054 {
1055
1056 unsigned tmp;
1057
1058 tmp = 0;
1059 switch (addr & 0xff) {
1060
1061 case 0xE0: /* UART 1 */
1062 #ifndef _WIN32
1063 #ifdef FAST_UART
1064
1065 if (aind < anum) {
1066 if ((aind + 1) < anum)
1067 mec_irq(4);
1068 return (0x700 | (uint32) aq[aind++]);
1069 } else {
1070 if (f1open) {
1071 anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
1072 }
1073 if (anum > 0) {
1074 aind = 0;
1075 if ((aind + 1) < anum)
1076 mec_irq(4);
1077 return (0x700 | (uint32) aq[aind++]);
1078 } else {
1079 return (0x600 | (uint32) aq[aind]);
1080 }
1081
1082 }
1083 #else
1084 tmp = uarta_data;
1085 uarta_data &= ~UART_DR;
1086 uart_stat_reg &= ~UARTA_DR;
1087 return tmp;
1088 #endif
1089 #else
1090 return(0);
1091 #endif
1092 break;
1093
1094 case 0xE4: /* UART 2 */
1095 #ifndef _WIN32
1096 #ifdef FAST_UART
1097 if (bind < bnum) {
1098 if ((bind + 1) < bnum)
1099 mec_irq(5);
1100 return (0x700 | (uint32) bq[bind++]);
1101 } else {
1102 if (f2open) {
1103 bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
1104 }
1105 if (bnum > 0) {
1106 bind = 0;
1107 if ((bind + 1) < bnum)
1108 mec_irq(5);
1109 return (0x700 | (uint32) bq[bind++]);
1110 } else {
1111 return (0x600 | (uint32) bq[bind]);
1112 }
1113
1114 }
1115 #else
1116 tmp = uartb_data;
1117 uartb_data &= ~UART_DR;
1118 uart_stat_reg &= ~UARTB_DR;
1119 return tmp;
1120 #endif
1121 #else
1122 return(0);
1123 #endif
1124 break;
1125
1126 case 0xE8: /* UART status register */
1127 #ifndef _WIN32
1128 #ifdef FAST_UART
1129
1130 Ucontrol = 0;
1131 if (aind < anum) {
1132 Ucontrol |= 0x00000001;
1133 } else {
1134 if (f1open) {
1135 anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
1136 }
1137 if (anum > 0) {
1138 Ucontrol |= 0x00000001;
1139 aind = 0;
1140 mec_irq(4);
1141 }
1142 }
1143 if (bind < bnum) {
1144 Ucontrol |= 0x00010000;
1145 } else {
1146 if (f2open) {
1147 bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
1148 }
1149 if (bnum > 0) {
1150 Ucontrol |= 0x00010000;
1151 bind = 0;
1152 mec_irq(5);
1153 }
1154 }
1155
1156 Ucontrol |= 0x00060006;
1157 return (Ucontrol);
1158 #else
1159 return (uart_stat_reg);
1160 #endif
1161 #else
1162 return(0x00060006);
1163 #endif
1164 break;
1165 default:
1166 if (sis_verbose)
1167 printf("Read from unimplemented MEC register (%x)\n", addr);
1168
1169 }
1170 return (0);
1171 }
1172
1173 static void
1174 write_uart(addr, data)
1175 uint32 addr;
1176 uint32 data;
1177 {
1178 unsigned char c;
1179
1180 c = (unsigned char) data;
1181 switch (addr & 0xff) {
1182
1183 case 0xE0: /* UART A */
1184 #ifdef FAST_UART
1185 if (f1open) {
1186 if (wnuma < UARTBUF)
1187 wbufa[wnuma++] = c;
1188 else {
1189 while (wnuma)
1190 wnuma -= fwrite(wbufa, 1, wnuma, f1out);
1191 wbufa[wnuma++] = c;
1192 }
1193 }
1194 mec_irq(4);
1195 #else
1196 if (uart_stat_reg & UARTA_SRE) {
1197 uarta_sreg = c;
1198 uart_stat_reg &= ~UARTA_SRE;
1199 event(uarta_tx, 0, UART_TX_TIME);
1200 } else {
1201 uarta_hreg = c;
1202 uart_stat_reg &= ~UARTA_HRE;
1203 }
1204 #endif
1205 break;
1206
1207 case 0xE4: /* UART B */
1208 #ifdef FAST_UART
1209 if (f2open) {
1210 if (wnumb < UARTBUF)
1211 wbufb[wnumb++] = c;
1212 else {
1213 while (wnumb)
1214 wnumb -= fwrite(wbufb, 1, wnumb, f2out);
1215 wbufb[wnumb++] = c;
1216 }
1217 }
1218 mec_irq(5);
1219 #else
1220 if (uart_stat_reg & UARTB_SRE) {
1221 uartb_sreg = c;
1222 uart_stat_reg &= ~UARTB_SRE;
1223 event(uartb_tx, 0, UART_TX_TIME);
1224 } else {
1225 uartb_hreg = c;
1226 uart_stat_reg &= ~UARTB_HRE;
1227 }
1228 #endif
1229 break;
1230 case 0xE8: /* UART status register */
1231 #ifndef FAST_UART
1232 if (data & UARTA_CLR) {
1233 uart_stat_reg &= 0xFFFF0000;
1234 uart_stat_reg |= UARTA_SRE | UARTA_HRE;
1235 }
1236 if (data & UARTB_CLR) {
1237 uart_stat_reg &= 0x0000FFFF;
1238 uart_stat_reg |= UARTB_SRE | UARTB_HRE;
1239 }
1240 #endif
1241 break;
1242 default:
1243 if (sis_verbose)
1244 printf("Write to unimplemented MEC register (%x)\n", addr);
1245
1246 }
1247 }
1248
1249 static void
1250 flush_uart()
1251 {
1252 while (wnuma && f1open)
1253 wnuma -= fwrite(wbufa, 1, wnuma, f1out);
1254 while (wnumb && f2open)
1255 wnumb -= fwrite(wbufb, 1, wnumb, f2out);
1256 }
1257
1258
1259
1260 static void
1261 uarta_tx()
1262 {
1263
1264 while (f1open && fwrite(&uarta_sreg, 1, 1, f1out) != 1);
1265 if (uart_stat_reg & UARTA_HRE) {
1266 uart_stat_reg |= UARTA_SRE;
1267 } else {
1268 uarta_sreg = uarta_hreg;
1269 uart_stat_reg |= UARTA_HRE;
1270 event(uarta_tx, 0, UART_TX_TIME);
1271 }
1272 mec_irq(4);
1273 }
1274
1275 static void
1276 uartb_tx()
1277 {
1278 while (f2open && fwrite(&uartb_sreg, 1, 1, f2out) != 1);
1279 if (uart_stat_reg & UARTB_HRE) {
1280 uart_stat_reg |= UARTB_SRE;
1281 } else {
1282 uartb_sreg = uartb_hreg;
1283 uart_stat_reg |= UARTB_HRE;
1284 event(uartb_tx, 0, UART_TX_TIME);
1285 }
1286 mec_irq(5);
1287 }
1288
1289 static void
1290 uart_rx(arg)
1291 caddr_t arg;
1292 {
1293 int32 rsize;
1294 char rxd;
1295
1296
1297 rsize = 0;
1298 if (f1open)
1299 rsize = DO_STDIO_READ(ifd1, &rxd, 1);
1300 if (rsize > 0) {
1301 uarta_data = UART_DR | rxd;
1302 if (uart_stat_reg & UARTA_HRE)
1303 uarta_data |= UART_THE;
1304 if (uart_stat_reg & UARTA_SRE)
1305 uarta_data |= UART_TSE;
1306 if (uart_stat_reg & UARTA_DR) {
1307 uart_stat_reg |= UARTA_OR;
1308 mec_irq(7); /* UART error interrupt */
1309 }
1310 uart_stat_reg |= UARTA_DR;
1311 mec_irq(4);
1312 }
1313 rsize = 0;
1314 if (f2open)
1315 rsize = DO_STDIO_READ(ifd2, &rxd, 1);
1316 if (rsize) {
1317 uartb_data = UART_DR | rxd;
1318 if (uart_stat_reg & UARTB_HRE)
1319 uartb_data |= UART_THE;
1320 if (uart_stat_reg & UARTB_SRE)
1321 uartb_data |= UART_TSE;
1322 if (uart_stat_reg & UARTB_DR) {
1323 uart_stat_reg |= UARTB_OR;
1324 mec_irq(7); /* UART error interrupt */
1325 }
1326 uart_stat_reg |= UARTB_DR;
1327 mec_irq(5);
1328 }
1329 event(uart_rx, 0, UART_RX_TIME);
1330 }
1331
1332 static void
1333 uart_intr(arg)
1334 caddr_t arg;
1335 {
1336 read_uart(0xE8); /* Check for UART interrupts every 1000 clk */
1337 flush_uart(); /* Flush UART ports */
1338 event(uart_intr, 0, UART_FLUSH_TIME);
1339 }
1340
1341
1342 static void
1343 uart_irq_start()
1344 {
1345 #ifdef FAST_UART
1346 event(uart_intr, 0, UART_FLUSH_TIME);
1347 #else
1348 #ifndef _WIN32
1349 event(uart_rx, 0, UART_RX_TIME);
1350 #endif
1351 #endif
1352 }
1353
1354 /* Watch-dog */
1355
1356 static void
1357 wdog_intr(arg)
1358 caddr_t arg;
1359 {
1360 if (wdog_status == disabled) {
1361 wdog_status = stopped;
1362 } else {
1363
1364 if (wdog_counter) {
1365 wdog_counter--;
1366 event(wdog_intr, 0, wdog_scaler + 1);
1367 } else {
1368 if (wdog_rston) {
1369 printf("Watchdog reset!\n");
1370 sys_reset();
1371 mec_ersr = 0xC000;
1372 } else {
1373 mec_irq(15);
1374 wdog_rston = 1;
1375 wdog_counter = wdog_rst_delay;
1376 event(wdog_intr, 0, wdog_scaler + 1);
1377 }
1378 }
1379 }
1380 }
1381
1382 static void
1383 wdog_start()
1384 {
1385 event(wdog_intr, 0, wdog_scaler + 1);
1386 if (sis_verbose)
1387 printf("Watchdog started, scaler = %d, counter = %d\n",
1388 wdog_scaler, wdog_counter);
1389 }
1390
1391
1392 /* MEC timers */
1393
1394
1395 static void
1396 rtc_intr(arg)
1397 caddr_t arg;
1398 {
1399 if (rtc_counter == 0) {
1400
1401 mec_irq(13);
1402 if (rtc_cr)
1403 rtc_counter = rtc_reload;
1404 else
1405 rtc_se = 0;
1406 } else
1407 rtc_counter -= 1;
1408 if (rtc_se) {
1409 event(rtc_intr, 0, rtc_scaler + 1);
1410 rtc_scaler_start = now();
1411 rtc_enabled = 1;
1412 } else {
1413 if (sis_verbose)
1414 printf("RTC stopped\n\r");
1415 rtc_enabled = 0;
1416 }
1417 }
1418
1419 static void
1420 rtc_start()
1421 {
1422 if (sis_verbose)
1423 printf("RTC started (period %d)\n\r", rtc_scaler + 1);
1424 event(rtc_intr, 0, rtc_scaler + 1);
1425 rtc_scaler_start = now();
1426 rtc_enabled = 1;
1427 }
1428
1429 static uint32
1430 rtc_counter_read()
1431 {
1432 return (rtc_counter);
1433 }
1434
1435 static void
1436 rtc_scaler_set(val)
1437 uint32 val;
1438 {
1439 rtc_scaler = val & 0x0ff; /* eight-bit scaler only */
1440 }
1441
1442 static void
1443 rtc_reload_set(val)
1444 uint32 val;
1445 {
1446 rtc_reload = val;
1447 }
1448
1449 static void
1450 gpt_intr(arg)
1451 caddr_t arg;
1452 {
1453 if (gpt_counter == 0) {
1454 mec_irq(12);
1455 if (gpt_cr)
1456 gpt_counter = gpt_reload;
1457 else
1458 gpt_se = 0;
1459 } else
1460 gpt_counter -= 1;
1461 if (gpt_se) {
1462 event(gpt_intr, 0, gpt_scaler + 1);
1463 gpt_scaler_start = now();
1464 gpt_enabled = 1;
1465 } else {
1466 if (sis_verbose)
1467 printf("GPT stopped\n\r");
1468 gpt_enabled = 0;
1469 }
1470 }
1471
1472 static void
1473 gpt_start()
1474 {
1475 if (sis_verbose)
1476 printf("GPT started (period %d)\n\r", gpt_scaler + 1);
1477 event(gpt_intr, 0, gpt_scaler + 1);
1478 gpt_scaler_start = now();
1479 gpt_enabled = 1;
1480 }
1481
1482 static uint32
1483 gpt_counter_read()
1484 {
1485 return (gpt_counter);
1486 }
1487
1488 static void
1489 gpt_scaler_set(val)
1490 uint32 val;
1491 {
1492 gpt_scaler = val & 0x0ffff; /* 16-bit scaler */
1493 }
1494
1495 static void
1496 gpt_reload_set(val)
1497 uint32 val;
1498 {
1499 gpt_reload = val;
1500 }
1501
1502 static void
1503 timer_ctrl(val)
1504 uint32 val;
1505 {
1506
1507 rtc_cr = ((val & TCR_TCRCR) != 0);
1508 if (val & TCR_TCRCL) {
1509 rtc_counter = rtc_reload;
1510 }
1511 if (val & TCR_TCRSL) {
1512 }
1513 rtc_se = ((val & TCR_TCRSE) != 0);
1514 if (rtc_se && (rtc_enabled == 0))
1515 rtc_start();
1516
1517 gpt_cr = (val & TCR_GACR);
1518 if (val & TCR_GACL) {
1519 gpt_counter = gpt_reload;
1520 }
1521 if (val & TCR_GACL) {
1522 }
1523 gpt_se = (val & TCR_GASE) >> 2;
1524 if (gpt_se && (gpt_enabled == 0))
1525 gpt_start();
1526 }
1527
1528
1529 /* Retrieve data from target memory. MEM points to location from which
1530 to read the data; DATA points to words where retrieved data will be
1531 stored in host byte order. SZ contains log(2) of the number of bytes
1532 to retrieve, and can be 0 (1 byte), 1 (one half-word), 2 (one word),
1533 or 3 (two words). */
1534
1535 static void
1536 fetch_bytes (asi, mem, data, sz)
1537 int asi;
1538 unsigned char *mem;
1539 uint32 *data;
1540 int sz;
1541 {
1542 if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN
1543 || asi == 8 || asi == 9) {
1544 switch (sz) {
1545 case 3:
1546 data[1] = (((uint32) mem[7]) & 0xff) |
1547 ((((uint32) mem[6]) & 0xff) << 8) |
1548 ((((uint32) mem[5]) & 0xff) << 16) |
1549 ((((uint32) mem[4]) & 0xff) << 24);
1550 /* Fall through to 2 */
1551 case 2:
1552 data[0] = (((uint32) mem[3]) & 0xff) |
1553 ((((uint32) mem[2]) & 0xff) << 8) |
1554 ((((uint32) mem[1]) & 0xff) << 16) |
1555 ((((uint32) mem[0]) & 0xff) << 24);
1556 break;
1557 case 1:
1558 data[0] = (((uint32) mem[1]) & 0xff) |
1559 ((((uint32) mem[0]) & 0xff) << 8);
1560 break;
1561 case 0:
1562 data[0] = mem[0] & 0xff;
1563 break;
1564
1565 }
1566 } else {
1567 switch (sz) {
1568 case 3:
1569 data[1] = ((((uint32) mem[7]) & 0xff) << 24) |
1570 ((((uint32) mem[6]) & 0xff) << 16) |
1571 ((((uint32) mem[5]) & 0xff) << 8) |
1572 (((uint32) mem[4]) & 0xff);
1573 /* Fall through to 4 */
1574 case 2:
1575 data[0] = ((((uint32) mem[3]) & 0xff) << 24) |
1576 ((((uint32) mem[2]) & 0xff) << 16) |
1577 ((((uint32) mem[1]) & 0xff) << 8) |
1578 (((uint32) mem[0]) & 0xff);
1579 break;
1580 case 1:
1581 data[0] = ((((uint32) mem[1]) & 0xff) << 8) |
1582 (((uint32) mem[0]) & 0xff);
1583 break;
1584 case 0:
1585 data[0] = mem[0] & 0xff;
1586 break;
1587 }
1588 }
1589 }
1590
1591
1592 /* Store data in target byte order. MEM points to location to store data;
1593 DATA points to words in host byte order to be stored. SZ contains log(2)
1594 of the number of bytes to retrieve, and can be 0 (1 byte), 1 (one half-word),
1595 2 (one word), or 3 (two words). */
1596
1597 static void
1598 store_bytes (mem, data, sz)
1599 unsigned char *mem;
1600 uint32 *data;
1601 int sz;
1602 {
1603 if (CURRENT_TARGET_BYTE_ORDER == LITTLE_ENDIAN) {
1604 switch (sz) {
1605 case 3:
1606 mem[7] = (data[1] >> 24) & 0xff;
1607 mem[6] = (data[1] >> 16) & 0xff;
1608 mem[5] = (data[1] >> 8) & 0xff;
1609 mem[4] = data[1] & 0xff;
1610 /* Fall through to 2 */
1611 case 2:
1612 mem[3] = (data[0] >> 24) & 0xff;
1613 mem[2] = (data[0] >> 16) & 0xff;
1614 /* Fall through to 1 */
1615 case 1:
1616 mem[1] = (data[0] >> 8) & 0xff;
1617 /* Fall through to 0 */
1618 case 0:
1619 mem[0] = data[0] & 0xff;
1620 break;
1621 }
1622 } else {
1623 switch (sz) {
1624 case 3:
1625 mem[7] = data[1] & 0xff;
1626 mem[6] = (data[1] >> 8) & 0xff;
1627 mem[5] = (data[1] >> 16) & 0xff;
1628 mem[4] = (data[1] >> 24) & 0xff;
1629 /* Fall through to 2 */
1630 case 2:
1631 mem[3] = data[0] & 0xff;
1632 mem[2] = (data[0] >> 8) & 0xff;
1633 mem[1] = (data[0] >> 16) & 0xff;
1634 mem[0] = (data[0] >> 24) & 0xff;
1635 break;
1636 case 1:
1637 mem[1] = data[0] & 0xff;
1638 mem[0] = (data[0] >> 8) & 0xff;
1639 break;
1640 case 0:
1641 mem[0] = data[0] & 0xff;
1642 break;
1643
1644 }
1645 }
1646 }
1647
1648
1649 /* Memory emulation */
1650
1651 int
1652 memory_read(asi, addr, data, sz, ws)
1653 int32 asi;
1654 uint32 addr;
1655 uint32 *data;
1656 int32 sz;
1657 int32 *ws;
1658 {
1659 int32 mexc;
1660
1661 #ifdef ERRINJ
1662 if (errmec) {
1663 if (sis_verbose)
1664 printf("Inserted MEC error %d\n",errmec);
1665 set_sfsr(errmec, addr, asi, 1);
1666 if (errmec == 5) mecparerror();
1667 if (errmec == 6) iucomperr();
1668 errmec = 0;
1669 return(1);
1670 }
1671 #endif
1672
1673 if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
1674 fetch_bytes (asi, &ramb[addr & mem_rammask], data, sz);
1675 *ws = mem_ramr_ws;
1676 return (0);
1677 } else if ((addr >= MEC_START) && (addr < MEC_END)) {
1678 mexc = mec_read(addr, asi, data);
1679 if (mexc) {
1680 set_sfsr(MEC_ACC, addr, asi, 1);
1681 *ws = MEM_EX_WS;
1682 } else {
1683 *ws = 0;
1684 }
1685 return (mexc);
1686
1687 #ifdef ERA
1688
1689 } else if (era) {
1690 if ((addr < 0x100000) ||
1691 ((addr>= 0x80000000) && (addr < 0x80100000))) {
1692 fetch_bytes (asi, &romb[addr & ROM_MASK], data, sz);
1693 *ws = 4;
1694 return (0);
1695 } else if ((addr >= 0x10000000) &&
1696 (addr < (0x10000000 + (512 << (mec_iocr & 0x0f)))) &&
1697 (mec_iocr & 0x10)) {
1698 *data = erareg;
1699 return (0);
1700 }
1701
1702 } else if (addr < mem_romsz) {
1703 fetch_bytes (asi, &romb[addr], data, sz);
1704 *ws = mem_romr_ws;
1705 return (0);
1706
1707 #else
1708 } else if (addr < mem_romsz) {
1709 fetch_bytes (asi, &romb[addr], data, sz);
1710 *ws = mem_romr_ws;
1711 return (0);
1712 #endif
1713
1714 }
1715
1716 printf("Memory exception at %x (illegal address)\n", addr);
1717 set_sfsr(UIMP_ACC, addr, asi, 1);
1718 *ws = MEM_EX_WS;
1719 return (1);
1720 }
1721
1722 int
1723 memory_write(asi, addr, data, sz, ws)
1724 int32 asi;
1725 uint32 addr;
1726 uint32 *data;
1727 int32 sz;
1728 int32 *ws;
1729 {
1730 uint32 byte_addr;
1731 uint32 byte_mask;
1732 uint32 waddr;
1733 uint32 *ram;
1734 int32 mexc;
1735 int i;
1736 int wphit[2];
1737
1738 #ifdef ERRINJ
1739 if (errmec) {
1740 if (sis_verbose)
1741 printf("Inserted MEC error %d\n",errmec);
1742 set_sfsr(errmec, addr, asi, 0);
1743 if (errmec == 5) mecparerror();
1744 if (errmec == 6) iucomperr();
1745 errmec = 0;
1746 return(1);
1747 }
1748 #endif
1749
1750 if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
1751 if (mem_accprot) {
1752
1753 waddr = (addr & 0x7fffff) >> 2;
1754 for (i = 0; i < 2; i++)
1755 wphit[i] =
1756 (((asi == 0xa) && (mec_wpr[i] & 1)) ||
1757 ((asi == 0xb) && (mec_wpr[i] & 2))) &&
1758 ((waddr >= mec_ssa[i]) && ((waddr | (sz == 3)) < mec_sea[i]));
1759
1760 if (((mem_blockprot) && (wphit[0] || wphit[1])) ||
1761 ((!mem_blockprot) &&
1762 !((mec_wpr[0] && wphit[0]) || (mec_wpr[1] && wphit[1]))
1763 )) {
1764 if (sis_verbose)
1765 printf("Memory access protection error at 0x%08x\n", addr);
1766 set_sfsr(PROT_EXC, addr, asi, 0);
1767 *ws = MEM_EX_WS;
1768 return (1);
1769 }
1770 }
1771
1772 store_bytes (&ramb[addr & mem_rammask], data, sz);
1773
1774 switch (sz) {
1775 case 0:
1776 case 1:
1777 *ws = mem_ramw_ws + 3;
1778 break;
1779 case 2:
1780 *ws = mem_ramw_ws;
1781 break;
1782 case 3:
1783 *ws = 2 * mem_ramw_ws + STD_WS;
1784 break;
1785 }
1786 return (0);
1787 } else if ((addr >= MEC_START) && (addr < MEC_END)) {
1788 if ((sz != 2) || (asi != 0xb)) {
1789 set_sfsr(MEC_ACC, addr, asi, 0);
1790 *ws = MEM_EX_WS;
1791 return (1);
1792 }
1793 mexc = mec_write(addr, *data);
1794 if (mexc) {
1795 set_sfsr(MEC_ACC, addr, asi, 0);
1796 *ws = MEM_EX_WS;
1797 } else {
1798 *ws = 0;
1799 }
1800 return (mexc);
1801
1802 #ifdef ERA
1803
1804 } else if (era) {
1805 if ((erareg & 2) &&
1806 ((addr < 0x100000) || ((addr >= 0x80000000) && (addr < 0x80100000)))) {
1807 addr &= ROM_MASK;
1808 *ws = sz == 3 ? 8 : 4;
1809 store_bytes (&romb[addr], data, sz);
1810 return (0);
1811 } else if ((addr >= 0x10000000) &&
1812 (addr < (0x10000000 + (512 << (mec_iocr & 0x0f)))) &&
1813 (mec_iocr & 0x10)) {
1814 erareg = *data & 0x0e;
1815 return (0);
1816 }
1817
1818 } else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) &&
1819 (((mec_memcfg & 0x20000) && (sz > 1)) ||
1820 (!(mec_memcfg & 0x20000) && (sz == 0)))) {
1821
1822 *ws = mem_romw_ws + 1;
1823 if (sz == 3)
1824 *ws += mem_romw_ws + STD_WS;
1825 store_bytes (&romb[addr], data, sz);
1826 return (0);
1827
1828 #else
1829 } else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) &&
1830 (((mec_memcfg & 0x20000) && (sz > 1)) ||
1831 (!(mec_memcfg & 0x20000) && (sz == 0)))) {
1832
1833 *ws = mem_romw_ws + 1;
1834 if (sz == 3)
1835 *ws += mem_romw_ws + STD_WS;
1836 store_bytes (&romb[addr], data, sz);
1837 return (0);
1838
1839 #endif
1840
1841 }
1842
1843 *ws = MEM_EX_WS;
1844 set_sfsr(UIMP_ACC, addr, asi, 0);
1845 return (1);
1846 }
1847
1848 static unsigned char *
1849 get_mem_ptr(addr, size)
1850 uint32 addr;
1851 uint32 size;
1852 {
1853 if ((addr + size) < ROM_SZ) {
1854 return (&romb[addr]);
1855 } else if ((addr >= mem_ramstart) && ((addr + size) < mem_ramend)) {
1856 return (&ramb[addr & mem_rammask]);
1857 }
1858
1859 #ifdef ERA
1860 else if ((era) && ((addr <0x100000) ||
1861 ((addr >= (unsigned) 0x80000000) && ((addr + size) < (unsigned) 0x80100000)))) {
1862 return (&romb[addr & ROM_MASK]);
1863 }
1864 #endif
1865
1866 return ((char *) -1);
1867 }
1868
1869 int
1870 sis_memory_write(addr, data, length)
1871 uint32 addr;
1872 const unsigned char *data;
1873 uint32 length;
1874 {
1875 char *mem;
1876
1877 if ((mem = get_mem_ptr(addr, length)) == ((char *) -1))
1878 return (0);
1879
1880 memcpy(mem, data, length);
1881 return (length);
1882 }
1883
1884 int
1885 sis_memory_read(addr, data, length)
1886 uint32 addr;
1887 char *data;
1888 uint32 length;
1889 {
1890 char *mem;
1891
1892 if ((mem = get_mem_ptr(addr, length)) == ((char *) -1))
1893 return (0);
1894
1895 memcpy(data, mem, length);
1896 return (length);
1897 }
1898
1899 extern struct pstate sregs;
1900
1901 void
1902 boot_init (void)
1903 {
1904 mec_write(MEC_WCR, 0); /* zero waitstates */
1905 mec_write(MEC_TRAPD, 0); /* turn off watch-dog */
1906 mec_write(MEC_RTC_SCALER, sregs.freq - 1); /* generate 1 MHz RTC tick */
1907 mec_write(MEC_MEMCFG, (3 << 18) | (4 << 10)); /* 1 MB ROM, 4 MB RAM */
1908 sregs.wim = 2;
1909 sregs.psr = 0x110010e0;
1910 sregs.r[30] = RAM_END;
1911 sregs.r[14] = sregs.r[30] - 96 * 4;
1912 mec_mcr |= 1; /* power-down enabled */
1913 }
GDB Binutils - Deliverables
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