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* end.c: Include config.h before system header files.
[deliverable/binutils-gdb.git] / sim / erc32 / erc32.c
1 /*
2 * This file is part of SIS.
3 *
4 * SIS, SPARC instruction simulator V2.5 Copyright (C) 1995 Jiri Gaisler,
5 * European Space Agency
6 *
7 * This program is free software; you can redistribute it and/or modify it under
8 * the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 675
19 * Mass Ave, Cambridge, MA 02139, USA.
20 *
21 */
22
23 /* The control space devices */
24
25 #include "config.h"
26 #include <sys/types.h>
27 #include <stdio.h>
28 #include <string.h>
29 #include <termios.h>
30 #include <sys/fcntl.h>
31 #include <sys/file.h>
32 #include <unistd.h>
33 #include "sis.h"
34 #include "end.h"
35 #include "sim-config.h"
36
37 extern int ctrl_c;
38 extern int32 sis_verbose;
39 extern int32 sparclite, sparclite_board;
40 extern int rom8,wrp,uben;
41 extern char uart_dev1[], uart_dev2[];
42
43 int dumbio = 0; /* normal, smart, terminal oriented IO by default */
44
45 /* MEC registers */
46 #define MEC_START 0x01f80000
47 #define MEC_END 0x01f80100
48
49 /* Memory exception waitstates */
50 #define MEM_EX_WS 1
51
52 /* ERC32 always adds one waitstate during RAM std */
53 #define STD_WS 1
54
55 #ifdef ERRINJ
56 extern int errmec;
57 #endif
58
59 /* The target's byte order is big-endian by default until we load a
60 little-endian program. */
61
62 int current_target_byte_order = BIG_ENDIAN;
63
64 #define MEC_WS 0 /* Waitstates per MEC access (0 ws) */
65 #define MOK 0
66
67 /* MEC register addresses */
68
69 #define MEC_MCR 0x000
70 #define MEC_SFR 0x004
71 #define MEC_PWDR 0x008
72 #define MEC_MEMCFG 0x010
73 #define MEC_IOCR 0x014
74 #define MEC_WCR 0x018
75
76 #define MEC_MAR0 0x020
77 #define MEC_MAR1 0x024
78
79 #define MEC_SSA1 0x020
80 #define MEC_SEA1 0x024
81 #define MEC_SSA2 0x028
82 #define MEC_SEA2 0x02C
83 #define MEC_ISR 0x044
84 #define MEC_IPR 0x048
85 #define MEC_IMR 0x04C
86 #define MEC_ICR 0x050
87 #define MEC_IFR 0x054
88 #define MEC_WDOG 0x060
89 #define MEC_TRAPD 0x064
90 #define MEC_RTC_COUNTER 0x080
91 #define MEC_RTC_RELOAD 0x080
92 #define MEC_RTC_SCALER 0x084
93 #define MEC_GPT_COUNTER 0x088
94 #define MEC_GPT_RELOAD 0x088
95 #define MEC_GPT_SCALER 0x08C
96 #define MEC_TIMER_CTRL 0x098
97 #define MEC_SFSR 0x0A0
98 #define MEC_FFAR 0x0A4
99 #define MEC_ERSR 0x0B0
100 #define MEC_DBG 0x0C0
101 #define MEC_TCR 0x0D0
102
103 #define MEC_BRK 0x0C4
104 #define MEC_WPR 0x0C8
105
106 #define MEC_UARTA 0x0E0
107 #define MEC_UARTB 0x0E4
108 #define MEC_UART_CTRL 0x0E8
109 #define SIM_LOAD 0x0F0
110
111 /* Memory exception causes */
112 #define PROT_EXC 0x3
113 #define UIMP_ACC 0x4
114 #define MEC_ACC 0x6
115 #define WATCH_EXC 0xa
116 #define BREAK_EXC 0xb
117
118 /* Size of UART buffers (bytes) */
119 #define UARTBUF 1024
120
121 /* Number of simulator ticks between flushing the UARTS. */
122 /* For good performance, keep above 1000 */
123 #define UART_FLUSH_TIME 3000
124
125 /* MEC timer control register bits */
126 #define TCR_GACR 1
127 #define TCR_GACL 2
128 #define TCR_GASE 4
129 #define TCR_GASL 8
130 #define TCR_TCRCR 0x100
131 #define TCR_TCRCL 0x200
132 #define TCR_TCRSE 0x400
133 #define TCR_TCRSL 0x800
134
135 /* New uart defines */
136 #define UART_TX_TIME 1000
137 #define UART_RX_TIME 1000
138 #define UARTA_DR 0x1
139 #define UARTA_SRE 0x2
140 #define UARTA_HRE 0x4
141 #define UARTA_OR 0x40
142 #define UARTA_CLR 0x80
143 #define UARTB_DR 0x10000
144 #define UARTB_SRE 0x20000
145 #define UARTB_HRE 0x40000
146 #define UARTB_OR 0x400000
147 #define UARTB_CLR 0x800000
148
149 #define UART_DR 0x100
150 #define UART_TSE 0x200
151 #define UART_THE 0x400
152
153 /* MEC registers */
154
155 static char fname[256];
156 static int32 find = 0;
157 static uint32 mec_ssa[2]; /* Write protection start address */
158 static uint32 mec_sea[2]; /* Write protection end address */
159 static uint32 mec_wpr[2]; /* Write protection control fields */
160 static uint32 mec_sfsr;
161 static uint32 mec_ffar;
162 static uint32 mec_ipr;
163 static uint32 mec_imr;
164 static uint32 mec_isr;
165 static uint32 mec_icr;
166 static uint32 mec_ifr;
167 static uint32 mec_mcr; /* MEC control register */
168 static uint32 mec_memcfg; /* Memory control register */
169 static uint32 mec_wcr; /* MEC waitstate register */
170 static uint32 mec_iocr; /* MEC IO control register */
171 static uint32 posted_irq;
172 static uint32 mec_ersr; /* MEC error and status register */
173 static uint32 mec_tcr; /* MEC test comtrol register */
174
175 static uint32 rtc_counter;
176 static uint32 rtc_reload;
177 static uint32 rtc_scaler;
178 static uint32 rtc_scaler_start;
179 static uint32 rtc_enabled;
180 static uint32 rtc_cr;
181 static uint32 rtc_se;
182
183 static uint32 gpt_counter;
184 static uint32 gpt_reload;
185 static uint32 gpt_scaler;
186 static uint32 gpt_scaler_start;
187 static uint32 gpt_enabled;
188 static uint32 gpt_cr;
189 static uint32 gpt_se;
190
191 static uint32 wdog_scaler;
192 static uint32 wdog_counter;
193 static uint32 wdog_rst_delay;
194 static uint32 wdog_rston;
195
196 enum wdog_type {
197 init, disabled, enabled, stopped
198 };
199
200 static enum wdog_type wdog_status;
201
202
203 /* ROM size 1024 Kbyte */
204 #define ROM_SZ 0x100000
205 #define ROM_MASK 0x0fffff
206
207 /* RAM size 4 Mbyte */
208 #define RAM_START 0x02000000
209 #define RAM_END 0x02400000
210 #define RAM_MASK 0x003fffff
211
212 /* SPARClite boards all seem to have RAM at the same place. */
213 #define RAM_START_SLITE 0x40000000
214 #define RAM_END_SLITE 0x40400000
215 #define RAM_MASK_SLITE 0x003fffff
216
217 /* Memory support variables */
218
219 static uint32 mem_ramr_ws; /* RAM read waitstates */
220 static uint32 mem_ramw_ws; /* RAM write waitstates */
221 static uint32 mem_romr_ws; /* ROM read waitstates */
222 static uint32 mem_romw_ws; /* ROM write waitstates */
223 static uint32 mem_ramstart; /* RAM start */
224 static uint32 mem_ramend; /* RAM end */
225 static uint32 mem_rammask; /* RAM address mask */
226 static uint32 mem_ramsz; /* RAM size */
227 static uint32 mem_romsz; /* ROM size */
228 static uint32 mem_accprot; /* RAM write protection enabled */
229 static uint32 mem_blockprot; /* RAM block write protection enabled */
230
231 static unsigned char romb[ROM_SZ];
232 static unsigned char ramb[RAM_END - RAM_START];
233
234
235 /* UART support variables */
236
237 static int32 fd1, fd2; /* file descriptor for input file */
238 static int32 Ucontrol; /* UART status register */
239 static unsigned char aq[UARTBUF], bq[UARTBUF];
240 static int32 anum, aind = 0;
241 static int32 bnum, bind = 0;
242 static char wbufa[UARTBUF], wbufb[UARTBUF];
243 static unsigned wnuma;
244 static unsigned wnumb;
245 static FILE *f1in, *f1out, *f2in, *f2out;
246 static struct termios ioc1, ioc2, iocold1, iocold2;
247 static int f1open = 0, f2open = 0;
248
249 static char uarta_sreg, uarta_hreg, uartb_sreg, uartb_hreg;
250 static uint32 uart_stat_reg;
251 static uint32 uarta_data, uartb_data;
252
253 #ifdef ERA
254 int era = 0;
255 int erareg;
256 #endif
257
258 /* Forward declarations */
259
260 static void decode_ersr PARAMS ((void));
261 #ifdef ERRINJ
262 static void iucomperr PARAMS ((void));
263 #endif
264 static void mecparerror PARAMS ((void));
265 static void decode_memcfg PARAMS ((void));
266 static void decode_wcr PARAMS ((void));
267 static void decode_mcr PARAMS ((void));
268 static void close_port PARAMS ((void));
269 static void mec_reset PARAMS ((void));
270 static void mec_intack PARAMS ((int32 level));
271 static void chk_irq PARAMS ((void));
272 static void mec_irq PARAMS ((int32 level));
273 static void set_sfsr PARAMS ((uint32 fault, uint32 addr,
274 uint32 asi, uint32 read));
275 static int32 mec_read PARAMS ((uint32 addr, uint32 asi, uint32 *data));
276 static int mec_write PARAMS ((uint32 addr, uint32 data));
277 static void port_init PARAMS ((void));
278 static uint32 read_uart PARAMS ((uint32 addr));
279 static void write_uart PARAMS ((uint32 addr, uint32 data));
280 static void flush_uart PARAMS ((void));
281 static void uarta_tx PARAMS ((void));
282 static void uartb_tx PARAMS ((void));
283 static void uart_rx PARAMS ((caddr_t arg));
284 static void uart_intr PARAMS ((caddr_t arg));
285 static void uart_irq_start PARAMS ((void));
286 static void wdog_intr PARAMS ((caddr_t arg));
287 static void wdog_start PARAMS ((void));
288 static void rtc_intr PARAMS ((caddr_t arg));
289 static void rtc_start PARAMS ((void));
290 static uint32 rtc_counter_read PARAMS ((void));
291 static void rtc_scaler_set PARAMS ((uint32 val));
292 static void rtc_reload_set PARAMS ((uint32 val));
293 static void gpt_intr PARAMS ((caddr_t arg));
294 static void gpt_start PARAMS ((void));
295 static uint32 gpt_counter_read PARAMS ((void));
296 static void gpt_scaler_set PARAMS ((uint32 val));
297 static void gpt_reload_set PARAMS ((uint32 val));
298 static void timer_ctrl PARAMS ((uint32 val));
299 static unsigned char *
300 get_mem_ptr PARAMS ((uint32 addr, uint32 size));
301
302 static void fetch_bytes PARAMS ((int asi, unsigned char *mem,
303 uint32 *data, int sz));
304
305 static void store_bytes PARAMS ((unsigned char *mem, uint32 *data, int sz));
306
307 extern int ext_irl;
308
309
310 /* One-time init */
311
312 void
313 init_sim()
314 {
315 port_init();
316 }
317
318 /* Power-on reset init */
319
320 void
321 reset()
322 {
323 mec_reset();
324 uart_irq_start();
325 wdog_start();
326 }
327
328 static void
329 decode_ersr()
330 {
331 if (mec_ersr & 0x01) {
332 if (!(mec_mcr & 0x20)) {
333 if (mec_mcr & 0x40) {
334 sys_reset();
335 mec_ersr = 0x8000;
336 if (sis_verbose)
337 printf("Error manager reset - IU in error mode\n");
338 } else {
339 sys_halt();
340 mec_ersr |= 0x2000;
341 if (sis_verbose)
342 printf("Error manager halt - IU in error mode\n");
343 }
344 } else
345 mec_irq(1);
346 }
347 if (mec_ersr & 0x04) {
348 if (!(mec_mcr & 0x200)) {
349 if (mec_mcr & 0x400) {
350 sys_reset();
351 mec_ersr = 0x8000;
352 if (sis_verbose)
353 printf("Error manager reset - IU comparison error\n");
354 } else {
355 sys_halt();
356 mec_ersr |= 0x2000;
357 if (sis_verbose)
358 printf("Error manager halt - IU comparison error\n");
359 }
360 } else
361 mec_irq(1);
362 }
363 if (mec_ersr & 0x20) {
364 if (!(mec_mcr & 0x2000)) {
365 if (mec_mcr & 0x4000) {
366 sys_reset();
367 mec_ersr = 0x8000;
368 if (sis_verbose)
369 printf("Error manager reset - MEC hardware error\n");
370 } else {
371 sys_halt();
372 mec_ersr |= 0x2000;
373 if (sis_verbose)
374 printf("Error manager halt - MEC hardware error\n");
375 }
376 } else
377 mec_irq(1);
378 }
379 }
380
381 #ifdef ERRINJ
382 static void
383 iucomperr()
384 {
385 mec_ersr |= 0x04;
386 decode_ersr();
387 }
388 #endif
389
390 static void
391 mecparerror()
392 {
393 mec_ersr |= 0x20;
394 decode_ersr();
395 }
396
397
398 /* IU error mode manager */
399
400 void
401 error_mode(pc)
402 uint32 pc;
403 {
404
405 mec_ersr |= 0x1;
406 decode_ersr();
407 }
408
409
410 /* Check memory settings */
411
412 static void
413 decode_memcfg()
414 {
415 if (rom8) mec_memcfg &= ~0x20000;
416 else mec_memcfg |= 0x20000;
417
418 mem_ramsz = (256 * 1024) << ((mec_memcfg >> 10) & 7);
419 mem_romsz = (128 * 1024) << ((mec_memcfg >> 18) & 7);
420
421 if (sparclite_board) {
422 mem_ramstart = RAM_START_SLITE;
423 mem_ramend = RAM_END_SLITE;
424 mem_rammask = RAM_MASK_SLITE;
425 }
426 else {
427 mem_ramstart = RAM_START;
428 mem_ramend = RAM_END;
429 mem_rammask = RAM_MASK;
430 }
431 if (sis_verbose)
432 printf("RAM start: 0x%x, RAM size: %d K, ROM size: %d K\n",
433 mem_ramstart, mem_ramsz >> 10, mem_romsz >> 10);
434 }
435
436 static void
437 decode_wcr()
438 {
439 mem_ramr_ws = mec_wcr & 3;
440 mem_ramw_ws = (mec_wcr >> 2) & 3;
441 mem_romr_ws = (mec_wcr >> 4) & 0x0f;
442 if (rom8) {
443 if (mem_romr_ws > 0 ) mem_romr_ws--;
444 mem_romr_ws = 5 + (4*mem_romr_ws);
445 }
446 mem_romw_ws = (mec_wcr >> 8) & 0x0f;
447 if (sis_verbose)
448 printf("Waitstates = RAM read: %d, RAM write: %d, ROM read: %d, ROM write: %d\n",
449 mem_ramr_ws, mem_ramw_ws, mem_romr_ws, mem_romw_ws);
450 }
451
452 static void
453 decode_mcr()
454 {
455 mem_accprot = (mec_wpr[0] | mec_wpr[1]);
456 mem_blockprot = (mec_mcr >> 3) & 1;
457 if (sis_verbose && mem_accprot)
458 printf("Memory block write protection enabled\n");
459 if (mec_mcr & 0x08000) {
460 mec_ersr |= 0x20;
461 decode_ersr();
462 }
463 if (sis_verbose && (mec_mcr & 2))
464 printf("Software reset enabled\n");
465 if (sis_verbose && (mec_mcr & 1))
466 printf("Power-down mode enabled\n");
467 }
468
469 /* Flush ports when simulator stops */
470
471 void
472 sim_halt()
473 {
474 #ifdef FAST_UART
475 flush_uart();
476 #endif
477 }
478
479 int
480 sim_stop(SIM_DESC sd)
481 {
482 ctrl_c = 1;
483 return 1;
484 }
485
486 static void
487 close_port()
488 {
489 if (f1open && f1in != stdin)
490 fclose(f1in);
491 if (f2open && f2in != stdin)
492 fclose(f2in);
493 }
494
495 void
496 exit_sim()
497 {
498 close_port();
499 }
500
501 static void
502 mec_reset()
503 {
504 int i;
505
506 find = 0;
507 for (i = 0; i < 2; i++)
508 mec_ssa[i] = mec_sea[i] = mec_wpr[i] = 0;
509 mec_mcr = 0x01350014;
510 mec_iocr = 0;
511 mec_sfsr = 0x078;
512 mec_ffar = 0;
513 mec_ipr = 0;
514 mec_imr = 0x7ffe;
515 mec_isr = 0;
516 mec_icr = 0;
517 mec_ifr = 0;
518 mec_memcfg = 0x10000;
519 mec_wcr = -1;
520 mec_ersr = 0; /* MEC error and status register */
521 mec_tcr = 0; /* MEC test comtrol register */
522
523 decode_memcfg();
524 decode_wcr();
525 decode_mcr();
526
527 posted_irq = 0;
528 wnuma = wnumb = 0;
529 anum = aind = bnum = bind = 0;
530
531 uart_stat_reg = UARTA_SRE | UARTA_HRE | UARTB_SRE | UARTB_HRE;
532 uarta_data = uartb_data = UART_THE | UART_TSE;
533
534 rtc_counter = 0xffffffff;
535 rtc_reload = 0xffffffff;
536 rtc_scaler = 0xff;
537 rtc_enabled = 0;
538 rtc_cr = 0;
539 rtc_se = 0;
540
541 gpt_counter = 0xffffffff;
542 gpt_reload = 0xffffffff;
543 gpt_scaler = 0xffff;
544 gpt_enabled = 0;
545 gpt_cr = 0;
546 gpt_se = 0;
547
548 wdog_scaler = 255;
549 wdog_rst_delay = 255;
550 wdog_counter = 0xffff;
551 wdog_rston = 0;
552 wdog_status = init;
553
554 #ifdef ERA
555 erareg = 0;
556 #endif
557
558 }
559
560
561
562 static void
563 mec_intack(level)
564 int32 level;
565 {
566 int irq_test;
567
568 if (sis_verbose)
569 printf("interrupt %d acknowledged\n", level);
570 irq_test = mec_tcr & 0x80000;
571 if ((irq_test) && (mec_ifr & (1 << level)))
572 mec_ifr &= ~(1 << level);
573 else
574 mec_ipr &= ~(1 << level);
575 chk_irq();
576 }
577
578 static void
579 chk_irq()
580 {
581 int32 i;
582 uint32 itmp;
583 int old_irl;
584
585 old_irl = ext_irl;
586 if (mec_tcr & 0x80000) itmp = mec_ifr;
587 else itmp = 0;
588 itmp = ((mec_ipr | itmp) & ~mec_imr) & 0x0fffe;
589 ext_irl = 0;
590 if (itmp != 0) {
591 for (i = 15; i > 0; i--) {
592 if (((itmp >> i) & 1) != 0) {
593 if ((sis_verbose) && (i > old_irl))
594 printf("IU irl: %d\n", i);
595 ext_irl = i;
596 set_int(i, mec_intack, i);
597 break;
598 }
599 }
600 }
601 }
602
603 static void
604 mec_irq(level)
605 int32 level;
606 {
607 mec_ipr |= (1 << level);
608 chk_irq();
609 }
610
611 static void
612 set_sfsr(fault, addr, asi, read)
613 uint32 fault;
614 uint32 addr;
615 uint32 asi;
616 uint32 read;
617 {
618 if ((asi == 0xa) || (asi == 0xb)) {
619 mec_ffar = addr;
620 mec_sfsr = (fault << 3) | (!read << 15);
621 mec_sfsr |= ((mec_sfsr & 1) ^ 1) | (mec_sfsr & 1);
622 switch (asi) {
623 case 0xa:
624 mec_sfsr |= 0x0004;
625 break;
626 case 0xb:
627 mec_sfsr |= 0x1004;
628 break;
629 }
630 }
631 }
632
633 static int32
634 mec_read(addr, asi, data)
635 uint32 addr;
636 uint32 asi;
637 uint32 *data;
638 {
639
640 switch (addr & 0x0ff) {
641
642 case MEC_MCR: /* 0x00 */
643 *data = mec_mcr;
644 break;
645
646 case MEC_MEMCFG: /* 0x10 */
647 *data = mec_memcfg;
648 break;
649
650 case MEC_IOCR:
651 *data = mec_iocr; /* 0x14 */
652 break;
653
654 case MEC_SSA1: /* 0x20 */
655 *data = mec_ssa[0] | (mec_wpr[0] << 23);
656 break;
657 case MEC_SEA1: /* 0x24 */
658 *data = mec_sea[0];
659 break;
660 case MEC_SSA2: /* 0x28 */
661 *data = mec_ssa[1] | (mec_wpr[1] << 23);
662 break;
663 case MEC_SEA2: /* 0x2c */
664 *data = mec_sea[1];
665 break;
666
667 case MEC_ISR: /* 0x44 */
668 *data = mec_isr;
669 break;
670
671 case MEC_IPR: /* 0x48 */
672 *data = mec_ipr;
673 break;
674
675 case MEC_IMR: /* 0x4c */
676 *data = mec_imr;
677 break;
678
679 case MEC_IFR: /* 0x54 */
680 *data = mec_ifr;
681 break;
682
683 case MEC_RTC_COUNTER: /* 0x80 */
684 *data = rtc_counter_read();
685 break;
686 case MEC_RTC_SCALER: /* 0x84 */
687 if (rtc_enabled)
688 *data = rtc_scaler - (now() - rtc_scaler_start);
689 else
690 *data = rtc_scaler;
691 break;
692
693 case MEC_GPT_COUNTER: /* 0x88 */
694 *data = gpt_counter_read();
695 break;
696
697 case MEC_GPT_SCALER: /* 0x8c */
698 if (rtc_enabled)
699 *data = gpt_scaler - (now() - gpt_scaler_start);
700 else
701 *data = gpt_scaler;
702 break;
703
704
705 case MEC_SFSR: /* 0xA0 */
706 *data = mec_sfsr;
707 break;
708
709 case MEC_FFAR: /* 0xA4 */
710 *data = mec_ffar;
711 break;
712
713 case SIM_LOAD:
714 fname[find] = 0;
715 if (find == 0)
716 strcpy(fname, "simload");
717 find = bfd_load(fname);
718 if (find == -1)
719 *data = 0;
720 else
721 *data = 1;
722 find = 0;
723 break;
724
725 case MEC_ERSR: /* 0xB0 */
726 *data = mec_ersr;
727 break;
728
729 case MEC_TCR: /* 0xD0 */
730 *data = mec_tcr;
731 break;
732
733 case MEC_UARTA: /* 0xE0 */
734 case MEC_UARTB: /* 0xE4 */
735 if (asi != 0xb) {
736 set_sfsr(MEC_ACC, addr, asi, 1);
737 return (1);
738 }
739 *data = read_uart(addr);
740 break;
741
742 case MEC_UART_CTRL: /* 0xE8 */
743
744 *data = read_uart(addr);
745 break;
746
747 default:
748 set_sfsr(MEC_ACC, addr, asi, 1);
749 return (1);
750 break;
751 }
752 return (MOK);
753 }
754
755 static int
756 mec_write(addr, data)
757 uint32 addr;
758 uint32 data;
759 {
760 if (sis_verbose > 1)
761 printf("MEC write a: %08x, d: %08x\n",addr,data);
762 switch (addr & 0x0ff) {
763
764 case MEC_MCR:
765 mec_mcr = data;
766 decode_mcr();
767 if (mec_mcr & 0x08000) mecparerror();
768 break;
769
770 case MEC_SFR:
771 if (mec_mcr & 0x2) {
772 sys_reset();
773 mec_ersr = 0x4000;
774 if (sis_verbose)
775 printf(" Software reset issued\n");
776 }
777 break;
778
779 case MEC_IOCR:
780 mec_iocr = data;
781 if (mec_iocr & 0xC0C0C0C0) mecparerror();
782 break;
783
784 case MEC_SSA1: /* 0x20 */
785 if (data & 0xFE000000) mecparerror();
786 mec_ssa[0] = data & 0x7fffff;
787 mec_wpr[0] = (data >> 23) & 0x03;
788 mem_accprot = mec_wpr[0] || mec_wpr[1];
789 if (sis_verbose && mec_wpr[0])
790 printf("Segment 1 memory protection enabled (0x02%06x - 0x02%06x)\n",
791 mec_ssa[0] << 2, mec_sea[0] << 2);
792 break;
793 case MEC_SEA1: /* 0x24 */
794 if (data & 0xFF800000) mecparerror();
795 mec_sea[0] = data & 0x7fffff;
796 break;
797 case MEC_SSA2: /* 0x28 */
798 if (data & 0xFE000000) mecparerror();
799 mec_ssa[1] = data & 0x7fffff;
800 mec_wpr[1] = (data >> 23) & 0x03;
801 mem_accprot = mec_wpr[0] || mec_wpr[1];
802 if (sis_verbose && mec_wpr[1])
803 printf("Segment 2 memory protection enabled (0x02%06x - 0x02%06x)\n",
804 mec_ssa[1] << 2, mec_sea[1] << 2);
805 break;
806 case MEC_SEA2: /* 0x2c */
807 if (data & 0xFF800000) mecparerror();
808 mec_sea[1] = data & 0x7fffff;
809 break;
810
811 case MEC_UARTA:
812 case MEC_UARTB:
813 if (data & 0xFFFFFF00) mecparerror();
814 case MEC_UART_CTRL:
815 if (data & 0xFF00FF00) mecparerror();
816 write_uart(addr, data);
817 break;
818
819 case MEC_GPT_RELOAD:
820 gpt_reload_set(data);
821 break;
822
823 case MEC_GPT_SCALER:
824 if (data & 0xFFFF0000) mecparerror();
825 gpt_scaler_set(data);
826 break;
827
828 case MEC_TIMER_CTRL:
829 if (data & 0xFFFFF0F0) mecparerror();
830 timer_ctrl(data);
831 break;
832
833 case MEC_RTC_RELOAD:
834 rtc_reload_set(data);
835 break;
836
837 case MEC_RTC_SCALER:
838 if (data & 0xFFFFFF00) mecparerror();
839 rtc_scaler_set(data);
840 break;
841
842 case MEC_SFSR: /* 0xA0 */
843 if (data & 0xFFFF0880) mecparerror();
844 mec_sfsr = 0x78;
845 break;
846
847 case MEC_ISR:
848 if (data & 0xFFFFE000) mecparerror();
849 mec_isr = data;
850 break;
851
852 case MEC_IMR: /* 0x4c */
853
854 if (data & 0xFFFF8001) mecparerror();
855 mec_imr = data & 0x7ffe;
856 chk_irq();
857 break;
858
859 case MEC_ICR: /* 0x50 */
860
861 if (data & 0xFFFF0001) mecparerror();
862 mec_ipr &= ~data & 0x0fffe;
863 chk_irq();
864 break;
865
866 case MEC_IFR: /* 0x54 */
867
868 if (mec_tcr & 0x080000) {
869 if (data & 0xFFFF0001) mecparerror();
870 mec_ifr = data & 0xfffe;
871 chk_irq();
872 }
873 break;
874 case SIM_LOAD:
875 fname[find++] = (char) data;
876 break;
877
878
879 case MEC_MEMCFG: /* 0x10 */
880 if (data & 0xC0E08000) mecparerror();
881 mec_memcfg = data;
882 decode_memcfg();
883 if (mec_memcfg & 0xc0e08000)
884 mecparerror();
885 break;
886
887 case MEC_WCR: /* 0x18 */
888 mec_wcr = data;
889 decode_wcr();
890 break;
891
892 case MEC_ERSR: /* 0xB0 */
893 if (mec_tcr & 0x100000)
894 if (data & 0xFFFFEFC0) mecparerror();
895 mec_ersr = data & 0x103f;
896 break;
897
898 case MEC_TCR: /* 0xD0 */
899 if (data & 0xFFE1FFC0) mecparerror();
900 mec_tcr = data & 0x1e003f;
901 break;
902
903 case MEC_WDOG: /* 0x60 */
904 wdog_scaler = (data >> 16) & 0x0ff;
905 wdog_counter = data & 0x0ffff;
906 wdog_rst_delay = data >> 24;
907 wdog_rston = 0;
908 if (wdog_status == stopped)
909 wdog_start();
910 wdog_status = enabled;
911 break;
912
913 case MEC_TRAPD: /* 0x64 */
914 if (wdog_status == init) {
915 wdog_status = disabled;
916 if (sis_verbose)
917 printf("Watchdog disabled\n");
918 }
919 break;
920
921 case MEC_PWDR:
922 if (mec_mcr & 1)
923 wait_for_irq();
924 break;
925
926 default:
927 set_sfsr(MEC_ACC, addr, 0xb, 0);
928 return (1);
929 break;
930 }
931 return (MOK);
932 }
933
934
935 /* MEC UARTS */
936
937 static int ifd1 = -1, ifd2 = -1, ofd1 = -1, ofd2 = -1;
938
939 void
940 init_stdio()
941 {
942 if (dumbio)
943 return; /* do nothing */
944 if (!ifd1)
945 tcsetattr(0, TCSANOW, &ioc1);
946 if (!ifd2)
947 tcsetattr(0, TCSANOW, &ioc2);
948 }
949
950 void
951 restore_stdio()
952 {
953 if (dumbio)
954 return; /* do nothing */
955 if (!ifd1)
956 tcsetattr(0, TCSANOW, &iocold1);
957 if (!ifd2)
958 tcsetattr(0, TCSANOW, &iocold2);
959 }
960
961 #define DO_STDIO_READ( _fd_, _buf_, _len_ ) \
962 ( dumbio \
963 ? (0) /* no bytes read, no delay */ \
964 : read( _fd_, _buf_, _len_ ) )
965
966
967 static void
968 port_init()
969 {
970
971 if (uben) {
972 f2in = stdin;
973 f1in = NULL;
974 f2out = stdout;
975 f1out = NULL;
976 } else {
977 f1in = stdin;
978 f2in = NULL;
979 f1out = stdout;
980 f2out = NULL;
981 }
982 if (uart_dev1[0] != 0)
983 if ((fd1 = open(uart_dev1, O_RDWR | O_NONBLOCK)) < 0) {
984 printf("Warning, couldn't open output device %s\n", uart_dev1);
985 } else {
986 if (sis_verbose)
987 printf("serial port A on %s\n", uart_dev1);
988 f1in = f1out = fdopen(fd1, "r+");
989 setbuf(f1out, NULL);
990 f1open = 1;
991 }
992 if (f1in) ifd1 = fileno(f1in);
993 if (ifd1 == 0) {
994 if (sis_verbose)
995 printf("serial port A on stdin/stdout\n");
996 if (!dumbio) {
997 tcgetattr(ifd1, &ioc1);
998 iocold1 = ioc1;
999 ioc1.c_lflag &= ~(ICANON | ECHO);
1000 ioc1.c_cc[VMIN] = 0;
1001 ioc1.c_cc[VTIME] = 0;
1002 }
1003 f1open = 1;
1004 }
1005
1006 if (f1out) {
1007 ofd1 = fileno(f1out);
1008 if (!dumbio && ofd1 == 1) setbuf(f1out, NULL);
1009 }
1010
1011 if (uart_dev2[0] != 0)
1012 if ((fd2 = open(uart_dev2, O_RDWR | O_NONBLOCK)) < 0) {
1013 printf("Warning, couldn't open output device %s\n", uart_dev2);
1014 } else {
1015 if (sis_verbose)
1016 printf("serial port B on %s\n", uart_dev2);
1017 f2in = f2out = fdopen(fd2, "r+");
1018 setbuf(f2out, NULL);
1019 f2open = 1;
1020 }
1021 if (f2in) ifd2 = fileno(f2in);
1022 if (ifd2 == 0) {
1023 if (sis_verbose)
1024 printf("serial port B on stdin/stdout\n");
1025 if (!dumbio) {
1026 tcgetattr(ifd2, &ioc2);
1027 iocold2 = ioc2;
1028 ioc2.c_lflag &= ~(ICANON | ECHO);
1029 ioc2.c_cc[VMIN] = 0;
1030 ioc2.c_cc[VTIME] = 0;
1031 }
1032 f2open = 1;
1033 }
1034
1035 if (f2out) {
1036 ofd2 = fileno(f2out);
1037 if (!dumbio && ofd2 == 1) setbuf(f2out, NULL);
1038 }
1039
1040 wnuma = wnumb = 0;
1041
1042 }
1043
1044 static uint32
1045 read_uart(addr)
1046 uint32 addr;
1047 {
1048
1049 unsigned tmp;
1050
1051 tmp = 0;
1052 switch (addr & 0xff) {
1053
1054 case 0xE0: /* UART 1 */
1055 #ifndef _WIN32
1056 #ifdef FAST_UART
1057
1058 if (aind < anum) {
1059 if ((aind + 1) < anum)
1060 mec_irq(4);
1061 return (0x700 | (uint32) aq[aind++]);
1062 } else {
1063 if (f1open) {
1064 anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
1065 }
1066 if (anum > 0) {
1067 aind = 0;
1068 if ((aind + 1) < anum)
1069 mec_irq(4);
1070 return (0x700 | (uint32) aq[aind++]);
1071 } else {
1072 return (0x600 | (uint32) aq[aind]);
1073 }
1074
1075 }
1076 #else
1077 tmp = uarta_data;
1078 uarta_data &= ~UART_DR;
1079 uart_stat_reg &= ~UARTA_DR;
1080 return tmp;
1081 #endif
1082 #else
1083 return(0);
1084 #endif
1085 break;
1086
1087 case 0xE4: /* UART 2 */
1088 #ifndef _WIN32
1089 #ifdef FAST_UART
1090 if (bind < bnum) {
1091 if ((bind + 1) < bnum)
1092 mec_irq(5);
1093 return (0x700 | (uint32) bq[bind++]);
1094 } else {
1095 if (f2open) {
1096 bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
1097 }
1098 if (bnum > 0) {
1099 bind = 0;
1100 if ((bind + 1) < bnum)
1101 mec_irq(5);
1102 return (0x700 | (uint32) bq[bind++]);
1103 } else {
1104 return (0x600 | (uint32) bq[bind]);
1105 }
1106
1107 }
1108 #else
1109 tmp = uartb_data;
1110 uartb_data &= ~UART_DR;
1111 uart_stat_reg &= ~UARTB_DR;
1112 return tmp;
1113 #endif
1114 #else
1115 return(0);
1116 #endif
1117 break;
1118
1119 case 0xE8: /* UART status register */
1120 #ifndef _WIN32
1121 #ifdef FAST_UART
1122
1123 Ucontrol = 0;
1124 if (aind < anum) {
1125 Ucontrol |= 0x00000001;
1126 } else {
1127 if (f1open) {
1128 anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
1129 }
1130 if (anum > 0) {
1131 Ucontrol |= 0x00000001;
1132 aind = 0;
1133 mec_irq(4);
1134 }
1135 }
1136 if (bind < bnum) {
1137 Ucontrol |= 0x00010000;
1138 } else {
1139 if (f2open) {
1140 bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
1141 }
1142 if (bnum > 0) {
1143 Ucontrol |= 0x00010000;
1144 bind = 0;
1145 mec_irq(5);
1146 }
1147 }
1148
1149 Ucontrol |= 0x00060006;
1150 return (Ucontrol);
1151 #else
1152 return (uart_stat_reg);
1153 #endif
1154 #else
1155 return(0x00060006);
1156 #endif
1157 break;
1158 default:
1159 if (sis_verbose)
1160 printf("Read from unimplemented MEC register (%x)\n", addr);
1161
1162 }
1163 return (0);
1164 }
1165
1166 static void
1167 write_uart(addr, data)
1168 uint32 addr;
1169 uint32 data;
1170 {
1171 unsigned char c;
1172
1173 c = (unsigned char) data;
1174 switch (addr & 0xff) {
1175
1176 case 0xE0: /* UART A */
1177 #ifdef FAST_UART
1178 if (f1open) {
1179 if (wnuma < UARTBUF)
1180 wbufa[wnuma++] = c;
1181 else {
1182 while (wnuma)
1183 wnuma -= fwrite(wbufa, 1, wnuma, f1out);
1184 wbufa[wnuma++] = c;
1185 }
1186 }
1187 mec_irq(4);
1188 #else
1189 if (uart_stat_reg & UARTA_SRE) {
1190 uarta_sreg = c;
1191 uart_stat_reg &= ~UARTA_SRE;
1192 event(uarta_tx, 0, UART_TX_TIME);
1193 } else {
1194 uarta_hreg = c;
1195 uart_stat_reg &= ~UARTA_HRE;
1196 }
1197 #endif
1198 break;
1199
1200 case 0xE4: /* UART B */
1201 #ifdef FAST_UART
1202 if (f2open) {
1203 if (wnumb < UARTBUF)
1204 wbufb[wnumb++] = c;
1205 else {
1206 while (wnumb)
1207 wnumb -= fwrite(wbufb, 1, wnumb, f2out);
1208 wbufb[wnumb++] = c;
1209 }
1210 }
1211 mec_irq(5);
1212 #else
1213 if (uart_stat_reg & UARTB_SRE) {
1214 uartb_sreg = c;
1215 uart_stat_reg &= ~UARTB_SRE;
1216 event(uartb_tx, 0, UART_TX_TIME);
1217 } else {
1218 uartb_hreg = c;
1219 uart_stat_reg &= ~UARTB_HRE;
1220 }
1221 #endif
1222 break;
1223 case 0xE8: /* UART status register */
1224 #ifndef FAST_UART
1225 if (data & UARTA_CLR) {
1226 uart_stat_reg &= 0xFFFF0000;
1227 uart_stat_reg |= UARTA_SRE | UARTA_HRE;
1228 }
1229 if (data & UARTB_CLR) {
1230 uart_stat_reg &= 0x0000FFFF;
1231 uart_stat_reg |= UARTB_SRE | UARTB_HRE;
1232 }
1233 #endif
1234 break;
1235 default:
1236 if (sis_verbose)
1237 printf("Write to unimplemented MEC register (%x)\n", addr);
1238
1239 }
1240 }
1241
1242 static void
1243 flush_uart()
1244 {
1245 while (wnuma && f1open)
1246 wnuma -= fwrite(wbufa, 1, wnuma, f1out);
1247 while (wnumb && f2open)
1248 wnumb -= fwrite(wbufb, 1, wnumb, f2out);
1249 }
1250
1251
1252
1253 static void
1254 uarta_tx()
1255 {
1256
1257 while (f1open && fwrite(&uarta_sreg, 1, 1, f1out) != 1);
1258 if (uart_stat_reg & UARTA_HRE) {
1259 uart_stat_reg |= UARTA_SRE;
1260 } else {
1261 uarta_sreg = uarta_hreg;
1262 uart_stat_reg |= UARTA_HRE;
1263 event(uarta_tx, 0, UART_TX_TIME);
1264 }
1265 mec_irq(4);
1266 }
1267
1268 static void
1269 uartb_tx()
1270 {
1271 while (f2open && fwrite(&uartb_sreg, 1, 1, f2out) != 1);
1272 if (uart_stat_reg & UARTB_HRE) {
1273 uart_stat_reg |= UARTB_SRE;
1274 } else {
1275 uartb_sreg = uartb_hreg;
1276 uart_stat_reg |= UARTB_HRE;
1277 event(uartb_tx, 0, UART_TX_TIME);
1278 }
1279 mec_irq(5);
1280 }
1281
1282 static void
1283 uart_rx(arg)
1284 caddr_t arg;
1285 {
1286 int32 rsize;
1287 char rxd;
1288
1289
1290 rsize = 0;
1291 if (f1open)
1292 rsize = DO_STDIO_READ(ifd1, &rxd, 1);
1293 if (rsize > 0) {
1294 uarta_data = UART_DR | rxd;
1295 if (uart_stat_reg & UARTA_HRE)
1296 uarta_data |= UART_THE;
1297 if (uart_stat_reg & UARTA_SRE)
1298 uarta_data |= UART_TSE;
1299 if (uart_stat_reg & UARTA_DR) {
1300 uart_stat_reg |= UARTA_OR;
1301 mec_irq(7); /* UART error interrupt */
1302 }
1303 uart_stat_reg |= UARTA_DR;
1304 mec_irq(4);
1305 }
1306 rsize = 0;
1307 if (f2open)
1308 rsize = DO_STDIO_READ(ifd2, &rxd, 1);
1309 if (rsize) {
1310 uartb_data = UART_DR | rxd;
1311 if (uart_stat_reg & UARTB_HRE)
1312 uartb_data |= UART_THE;
1313 if (uart_stat_reg & UARTB_SRE)
1314 uartb_data |= UART_TSE;
1315 if (uart_stat_reg & UARTB_DR) {
1316 uart_stat_reg |= UARTB_OR;
1317 mec_irq(7); /* UART error interrupt */
1318 }
1319 uart_stat_reg |= UARTB_DR;
1320 mec_irq(5);
1321 }
1322 event(uart_rx, 0, UART_RX_TIME);
1323 }
1324
1325 static void
1326 uart_intr(arg)
1327 caddr_t arg;
1328 {
1329 read_uart(0xE8); /* Check for UART interrupts every 1000 clk */
1330 flush_uart(); /* Flush UART ports */
1331 event(uart_intr, 0, UART_FLUSH_TIME);
1332 }
1333
1334
1335 static void
1336 uart_irq_start()
1337 {
1338 #ifdef FAST_UART
1339 event(uart_intr, 0, UART_FLUSH_TIME);
1340 #else
1341 #ifndef _WIN32
1342 event(uart_rx, 0, UART_RX_TIME);
1343 #endif
1344 #endif
1345 }
1346
1347 /* Watch-dog */
1348
1349 static void
1350 wdog_intr(arg)
1351 caddr_t arg;
1352 {
1353 if (wdog_status == disabled) {
1354 wdog_status = stopped;
1355 } else {
1356
1357 if (wdog_counter) {
1358 wdog_counter--;
1359 event(wdog_intr, 0, wdog_scaler + 1);
1360 } else {
1361 if (wdog_rston) {
1362 printf("Watchdog reset!\n");
1363 sys_reset();
1364 mec_ersr = 0xC000;
1365 } else {
1366 mec_irq(15);
1367 wdog_rston = 1;
1368 wdog_counter = wdog_rst_delay;
1369 event(wdog_intr, 0, wdog_scaler + 1);
1370 }
1371 }
1372 }
1373 }
1374
1375 static void
1376 wdog_start()
1377 {
1378 event(wdog_intr, 0, wdog_scaler + 1);
1379 if (sis_verbose)
1380 printf("Watchdog started, scaler = %d, counter = %d\n",
1381 wdog_scaler, wdog_counter);
1382 }
1383
1384
1385 /* MEC timers */
1386
1387
1388 static void
1389 rtc_intr(arg)
1390 caddr_t arg;
1391 {
1392 if (rtc_counter == 0) {
1393
1394 mec_irq(13);
1395 if (rtc_cr)
1396 rtc_counter = rtc_reload;
1397 else
1398 rtc_se = 0;
1399 } else
1400 rtc_counter -= 1;
1401 if (rtc_se) {
1402 event(rtc_intr, 0, rtc_scaler + 1);
1403 rtc_scaler_start = now();
1404 rtc_enabled = 1;
1405 } else {
1406 if (sis_verbose)
1407 printf("RTC stopped\n\r");
1408 rtc_enabled = 0;
1409 }
1410 }
1411
1412 static void
1413 rtc_start()
1414 {
1415 if (sis_verbose)
1416 printf("RTC started (period %d)\n\r", rtc_scaler + 1);
1417 event(rtc_intr, 0, rtc_scaler + 1);
1418 rtc_scaler_start = now();
1419 rtc_enabled = 1;
1420 }
1421
1422 static uint32
1423 rtc_counter_read()
1424 {
1425 return (rtc_counter);
1426 }
1427
1428 static void
1429 rtc_scaler_set(val)
1430 uint32 val;
1431 {
1432 rtc_scaler = val & 0x0ff; /* eight-bit scaler only */
1433 }
1434
1435 static void
1436 rtc_reload_set(val)
1437 uint32 val;
1438 {
1439 rtc_reload = val;
1440 }
1441
1442 static void
1443 gpt_intr(arg)
1444 caddr_t arg;
1445 {
1446 if (gpt_counter == 0) {
1447 mec_irq(12);
1448 if (gpt_cr)
1449 gpt_counter = gpt_reload;
1450 else
1451 gpt_se = 0;
1452 } else
1453 gpt_counter -= 1;
1454 if (gpt_se) {
1455 event(gpt_intr, 0, gpt_scaler + 1);
1456 gpt_scaler_start = now();
1457 gpt_enabled = 1;
1458 } else {
1459 if (sis_verbose)
1460 printf("GPT stopped\n\r");
1461 gpt_enabled = 0;
1462 }
1463 }
1464
1465 static void
1466 gpt_start()
1467 {
1468 if (sis_verbose)
1469 printf("GPT started (period %d)\n\r", gpt_scaler + 1);
1470 event(gpt_intr, 0, gpt_scaler + 1);
1471 gpt_scaler_start = now();
1472 gpt_enabled = 1;
1473 }
1474
1475 static uint32
1476 gpt_counter_read()
1477 {
1478 return (gpt_counter);
1479 }
1480
1481 static void
1482 gpt_scaler_set(val)
1483 uint32 val;
1484 {
1485 gpt_scaler = val & 0x0ffff; /* 16-bit scaler */
1486 }
1487
1488 static void
1489 gpt_reload_set(val)
1490 uint32 val;
1491 {
1492 gpt_reload = val;
1493 }
1494
1495 static void
1496 timer_ctrl(val)
1497 uint32 val;
1498 {
1499
1500 rtc_cr = ((val & TCR_TCRCR) != 0);
1501 if (val & TCR_TCRCL) {
1502 rtc_counter = rtc_reload;
1503 }
1504 if (val & TCR_TCRSL) {
1505 }
1506 rtc_se = ((val & TCR_TCRSE) != 0);
1507 if (rtc_se && (rtc_enabled == 0))
1508 rtc_start();
1509
1510 gpt_cr = (val & TCR_GACR);
1511 if (val & TCR_GACL) {
1512 gpt_counter = gpt_reload;
1513 }
1514 if (val & TCR_GACL) {
1515 }
1516 gpt_se = (val & TCR_GASE) >> 2;
1517 if (gpt_se && (gpt_enabled == 0))
1518 gpt_start();
1519 }
1520
1521
1522 /* Retrieve data from target memory. MEM points to location from which
1523 to read the data; DATA points to words where retrieved data will be
1524 stored in host byte order. SZ contains log(2) of the number of bytes
1525 to retrieve, and can be 0 (1 byte), 1 (one half-word), 2 (one word),
1526 or 3 (two words). */
1527
1528 static void
1529 fetch_bytes (asi, mem, data, sz)
1530 int asi;
1531 unsigned char *mem;
1532 uint32 *data;
1533 int sz;
1534 {
1535 if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN
1536 || asi == 8 || asi == 9) {
1537 switch (sz) {
1538 case 3:
1539 data[1] = (((uint32) mem[7]) & 0xff) |
1540 ((((uint32) mem[6]) & 0xff) << 8) |
1541 ((((uint32) mem[5]) & 0xff) << 16) |
1542 ((((uint32) mem[4]) & 0xff) << 24);
1543 /* Fall through to 2 */
1544 case 2:
1545 data[0] = (((uint32) mem[3]) & 0xff) |
1546 ((((uint32) mem[2]) & 0xff) << 8) |
1547 ((((uint32) mem[1]) & 0xff) << 16) |
1548 ((((uint32) mem[0]) & 0xff) << 24);
1549 break;
1550 case 1:
1551 data[0] = (((uint32) mem[1]) & 0xff) |
1552 ((((uint32) mem[0]) & 0xff) << 8);
1553 break;
1554 case 0:
1555 data[0] = mem[0] & 0xff;
1556 break;
1557
1558 }
1559 } else {
1560 switch (sz) {
1561 case 3:
1562 data[1] = ((((uint32) mem[7]) & 0xff) << 24) |
1563 ((((uint32) mem[6]) & 0xff) << 16) |
1564 ((((uint32) mem[5]) & 0xff) << 8) |
1565 (((uint32) mem[4]) & 0xff);
1566 /* Fall through to 4 */
1567 case 2:
1568 data[0] = ((((uint32) mem[3]) & 0xff) << 24) |
1569 ((((uint32) mem[2]) & 0xff) << 16) |
1570 ((((uint32) mem[1]) & 0xff) << 8) |
1571 (((uint32) mem[0]) & 0xff);
1572 break;
1573 case 1:
1574 data[0] = ((((uint32) mem[1]) & 0xff) << 8) |
1575 (((uint32) mem[0]) & 0xff);
1576 break;
1577 case 0:
1578 data[0] = mem[0] & 0xff;
1579 break;
1580 }
1581 }
1582 }
1583
1584
1585 /* Store data in target byte order. MEM points to location to store data;
1586 DATA points to words in host byte order to be stored. SZ contains log(2)
1587 of the number of bytes to retrieve, and can be 0 (1 byte), 1 (one half-word),
1588 2 (one word), or 3 (two words). */
1589
1590 static void
1591 store_bytes (mem, data, sz)
1592 unsigned char *mem;
1593 uint32 *data;
1594 int sz;
1595 {
1596 if (CURRENT_TARGET_BYTE_ORDER == LITTLE_ENDIAN) {
1597 switch (sz) {
1598 case 3:
1599 mem[7] = (data[1] >> 24) & 0xff;
1600 mem[6] = (data[1] >> 16) & 0xff;
1601 mem[5] = (data[1] >> 8) & 0xff;
1602 mem[4] = data[1] & 0xff;
1603 /* Fall through to 2 */
1604 case 2:
1605 mem[3] = (data[0] >> 24) & 0xff;
1606 mem[2] = (data[0] >> 16) & 0xff;
1607 /* Fall through to 1 */
1608 case 1:
1609 mem[1] = (data[0] >> 8) & 0xff;
1610 /* Fall through to 0 */
1611 case 0:
1612 mem[0] = data[0] & 0xff;
1613 break;
1614 }
1615 } else {
1616 switch (sz) {
1617 case 3:
1618 mem[7] = data[1] & 0xff;
1619 mem[6] = (data[1] >> 8) & 0xff;
1620 mem[5] = (data[1] >> 16) & 0xff;
1621 mem[4] = (data[1] >> 24) & 0xff;
1622 /* Fall through to 2 */
1623 case 2:
1624 mem[3] = data[0] & 0xff;
1625 mem[2] = (data[0] >> 8) & 0xff;
1626 mem[1] = (data[0] >> 16) & 0xff;
1627 mem[0] = (data[0] >> 24) & 0xff;
1628 break;
1629 case 1:
1630 mem[1] = data[0] & 0xff;
1631 mem[0] = (data[0] >> 8) & 0xff;
1632 break;
1633 case 0:
1634 mem[0] = data[0] & 0xff;
1635 break;
1636
1637 }
1638 }
1639 }
1640
1641
1642 /* Memory emulation */
1643
1644 int
1645 memory_read(asi, addr, data, sz, ws)
1646 int32 asi;
1647 uint32 addr;
1648 uint32 *data;
1649 int32 sz;
1650 int32 *ws;
1651 {
1652 int32 mexc;
1653
1654 #ifdef ERRINJ
1655 if (errmec) {
1656 if (sis_verbose)
1657 printf("Inserted MEC error %d\n",errmec);
1658 set_sfsr(errmec, addr, asi, 1);
1659 if (errmec == 5) mecparerror();
1660 if (errmec == 6) iucomperr();
1661 errmec = 0;
1662 return(1);
1663 }
1664 #endif
1665
1666 if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
1667 fetch_bytes (asi, &ramb[addr & mem_rammask], data, sz);
1668 *ws = mem_ramr_ws;
1669 return (0);
1670 } else if ((addr >= MEC_START) && (addr < MEC_END)) {
1671 mexc = mec_read(addr, asi, data);
1672 if (mexc) {
1673 set_sfsr(MEC_ACC, addr, asi, 1);
1674 *ws = MEM_EX_WS;
1675 } else {
1676 *ws = 0;
1677 }
1678 return (mexc);
1679
1680 #ifdef ERA
1681
1682 } else if (era) {
1683 if ((addr < 0x100000) ||
1684 ((addr>= 0x80000000) && (addr < 0x80100000))) {
1685 fetch_bytes (asi, &romb[addr & ROM_MASK], data, sz);
1686 *ws = 4;
1687 return (0);
1688 } else if ((addr >= 0x10000000) &&
1689 (addr < (0x10000000 + (512 << (mec_iocr & 0x0f)))) &&
1690 (mec_iocr & 0x10)) {
1691 *data = erareg;
1692 return (0);
1693 }
1694
1695 } else if (addr < mem_romsz) {
1696 fetch_bytes (asi, &romb[addr], data, sz);
1697 *ws = mem_romr_ws;
1698 return (0);
1699
1700 #else
1701 } else if (addr < mem_romsz) {
1702 fetch_bytes (asi, &romb[addr], data, sz);
1703 *ws = mem_romr_ws;
1704 return (0);
1705 #endif
1706
1707 }
1708
1709 printf("Memory exception at %x (illegal address)\n", addr);
1710 set_sfsr(UIMP_ACC, addr, asi, 1);
1711 *ws = MEM_EX_WS;
1712 return (1);
1713 }
1714
1715 int
1716 memory_write(asi, addr, data, sz, ws)
1717 int32 asi;
1718 uint32 addr;
1719 uint32 *data;
1720 int32 sz;
1721 int32 *ws;
1722 {
1723 uint32 byte_addr;
1724 uint32 byte_mask;
1725 uint32 waddr;
1726 uint32 *ram;
1727 int32 mexc;
1728 int i;
1729 int wphit[2];
1730
1731 #ifdef ERRINJ
1732 if (errmec) {
1733 if (sis_verbose)
1734 printf("Inserted MEC error %d\n",errmec);
1735 set_sfsr(errmec, addr, asi, 0);
1736 if (errmec == 5) mecparerror();
1737 if (errmec == 6) iucomperr();
1738 errmec = 0;
1739 return(1);
1740 }
1741 #endif
1742
1743 if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
1744 if (mem_accprot) {
1745
1746 waddr = (addr & 0x7fffff) >> 2;
1747 for (i = 0; i < 2; i++)
1748 wphit[i] =
1749 (((asi == 0xa) && (mec_wpr[i] & 1)) ||
1750 ((asi == 0xb) && (mec_wpr[i] & 2))) &&
1751 ((waddr >= mec_ssa[i]) && ((waddr | (sz == 3)) < mec_sea[i]));
1752
1753 if (((mem_blockprot) && (wphit[0] || wphit[1])) ||
1754 ((!mem_blockprot) &&
1755 !((mec_wpr[0] && wphit[0]) || (mec_wpr[1] && wphit[1]))
1756 )) {
1757 if (sis_verbose)
1758 printf("Memory access protection error at 0x%08x\n", addr);
1759 set_sfsr(PROT_EXC, addr, asi, 0);
1760 *ws = MEM_EX_WS;
1761 return (1);
1762 }
1763 }
1764
1765 store_bytes (&ramb[addr & mem_rammask], data, sz);
1766
1767 switch (sz) {
1768 case 0:
1769 case 1:
1770 *ws = mem_ramw_ws + 3;
1771 break;
1772 case 2:
1773 *ws = mem_ramw_ws;
1774 break;
1775 case 3:
1776 *ws = 2 * mem_ramw_ws + STD_WS;
1777 break;
1778 }
1779 return (0);
1780 } else if ((addr >= MEC_START) && (addr < MEC_END)) {
1781 if ((sz != 2) || (asi != 0xb)) {
1782 set_sfsr(MEC_ACC, addr, asi, 0);
1783 *ws = MEM_EX_WS;
1784 return (1);
1785 }
1786 mexc = mec_write(addr, *data);
1787 if (mexc) {
1788 set_sfsr(MEC_ACC, addr, asi, 0);
1789 *ws = MEM_EX_WS;
1790 } else {
1791 *ws = 0;
1792 }
1793 return (mexc);
1794
1795 #ifdef ERA
1796
1797 } else if (era) {
1798 if ((erareg & 2) &&
1799 ((addr < 0x100000) || ((addr >= 0x80000000) && (addr < 0x80100000)))) {
1800 addr &= ROM_MASK;
1801 *ws = sz == 3 ? 8 : 4;
1802 store_bytes (&romb[addr], data, sz);
1803 return (0);
1804 } else if ((addr >= 0x10000000) &&
1805 (addr < (0x10000000 + (512 << (mec_iocr & 0x0f)))) &&
1806 (mec_iocr & 0x10)) {
1807 erareg = *data & 0x0e;
1808 return (0);
1809 }
1810
1811 } else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) &&
1812 (((mec_memcfg & 0x20000) && (sz > 1)) ||
1813 (!(mec_memcfg & 0x20000) && (sz == 0)))) {
1814
1815 *ws = mem_romw_ws + 1;
1816 if (sz == 3)
1817 *ws += mem_romw_ws + STD_WS;
1818 store_bytes (&romb[addr], data, sz);
1819 return (0);
1820
1821 #else
1822 } else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) &&
1823 (((mec_memcfg & 0x20000) && (sz > 1)) ||
1824 (!(mec_memcfg & 0x20000) && (sz == 0)))) {
1825
1826 *ws = mem_romw_ws + 1;
1827 if (sz == 3)
1828 *ws += mem_romw_ws + STD_WS;
1829 store_bytes (&romb[addr], data, sz);
1830 return (0);
1831
1832 #endif
1833
1834 }
1835
1836 *ws = MEM_EX_WS;
1837 set_sfsr(UIMP_ACC, addr, asi, 0);
1838 return (1);
1839 }
1840
1841 static unsigned char *
1842 get_mem_ptr(addr, size)
1843 uint32 addr;
1844 uint32 size;
1845 {
1846 if ((addr + size) < ROM_SZ) {
1847 return (&romb[addr]);
1848 } else if ((addr >= mem_ramstart) && ((addr + size) < mem_ramend)) {
1849 return (&ramb[addr & mem_rammask]);
1850 }
1851
1852 #ifdef ERA
1853 else if ((era) && ((addr <0x100000) ||
1854 ((addr >= (unsigned) 0x80000000) && ((addr + size) < (unsigned) 0x80100000)))) {
1855 return (&romb[addr & ROM_MASK]);
1856 }
1857 #endif
1858
1859 return ((char *) -1);
1860 }
1861
1862 int
1863 sis_memory_write(addr, data, length)
1864 uint32 addr;
1865 const unsigned char *data;
1866 uint32 length;
1867 {
1868 char *mem;
1869
1870 if ((mem = get_mem_ptr(addr, length)) == ((char *) -1))
1871 return (0);
1872
1873 memcpy(mem, data, length);
1874 return (length);
1875 }
1876
1877 int
1878 sis_memory_read(addr, data, length)
1879 uint32 addr;
1880 char *data;
1881 uint32 length;
1882 {
1883 char *mem;
1884
1885 if ((mem = get_mem_ptr(addr, length)) == ((char *) -1))
1886 return (0);
1887
1888 memcpy(data, mem, length);
1889 return (length);
1890 }
GDB Binutils - Deliverables
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