2 * This file is part of SIS.
4 * SIS, SPARC instruction simulator V2.5 Copyright (C) 1995 Jiri Gaisler,
5 * European Space Agency
7 * This program is free software; you can redistribute it and/or modify it under
8 * the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 3 of the License, or (at your option)
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, see <http://www.gnu.org/licenses/>.
22 /* The control space devices */
25 #include <sys/types.h>
29 #include <sys/fcntl.h>
33 #include "sim-config.h"
36 extern int32 sis_verbose
;
37 extern int32 sparclite
, sparclite_board
;
38 extern int rom8
,wrp
,uben
;
39 extern char uart_dev1
[], uart_dev2
[];
41 int dumbio
= 0; /* normal, smart, terminal oriented IO by default */
44 #define MEC_START 0x01f80000
45 #define MEC_END 0x01f80100
47 /* Memory exception waitstates */
50 /* ERC32 always adds one waitstate during RAM std */
57 #define MEC_WS 0 /* Waitstates per MEC access (0 ws) */
60 /* MEC register addresses */
64 #define MEC_PWDR 0x008
65 #define MEC_MEMCFG 0x010
66 #define MEC_IOCR 0x014
69 #define MEC_MAR0 0x020
70 #define MEC_MAR1 0x024
72 #define MEC_SSA1 0x020
73 #define MEC_SEA1 0x024
74 #define MEC_SSA2 0x028
75 #define MEC_SEA2 0x02C
81 #define MEC_WDOG 0x060
82 #define MEC_TRAPD 0x064
83 #define MEC_RTC_COUNTER 0x080
84 #define MEC_RTC_RELOAD 0x080
85 #define MEC_RTC_SCALER 0x084
86 #define MEC_GPT_COUNTER 0x088
87 #define MEC_GPT_RELOAD 0x088
88 #define MEC_GPT_SCALER 0x08C
89 #define MEC_TIMER_CTRL 0x098
90 #define MEC_SFSR 0x0A0
91 #define MEC_FFAR 0x0A4
92 #define MEC_ERSR 0x0B0
99 #define MEC_UARTA 0x0E0
100 #define MEC_UARTB 0x0E4
101 #define MEC_UART_CTRL 0x0E8
102 #define SIM_LOAD 0x0F0
104 /* Memory exception causes */
108 #define WATCH_EXC 0xa
109 #define BREAK_EXC 0xb
111 /* Size of UART buffers (bytes) */
114 /* Number of simulator ticks between flushing the UARTS. */
115 /* For good performance, keep above 1000 */
116 #define UART_FLUSH_TIME 3000
118 /* MEC timer control register bits */
123 #define TCR_TCRCR 0x100
124 #define TCR_TCRCL 0x200
125 #define TCR_TCRSE 0x400
126 #define TCR_TCRSL 0x800
128 /* New uart defines */
129 #define UART_TX_TIME 1000
130 #define UART_RX_TIME 1000
132 #define UARTA_SRE 0x2
133 #define UARTA_HRE 0x4
134 #define UARTA_OR 0x40
135 #define UARTA_CLR 0x80
136 #define UARTB_DR 0x10000
137 #define UARTB_SRE 0x20000
138 #define UARTB_HRE 0x40000
139 #define UARTB_OR 0x400000
140 #define UARTB_CLR 0x800000
142 #define UART_DR 0x100
143 #define UART_TSE 0x200
144 #define UART_THE 0x400
148 static char fname
[256];
149 static int32 find
= 0;
150 static uint32 mec_ssa
[2]; /* Write protection start address */
151 static uint32 mec_sea
[2]; /* Write protection end address */
152 static uint32 mec_wpr
[2]; /* Write protection control fields */
153 static uint32 mec_sfsr
;
154 static uint32 mec_ffar
;
155 static uint32 mec_ipr
;
156 static uint32 mec_imr
;
157 static uint32 mec_isr
;
158 static uint32 mec_icr
;
159 static uint32 mec_ifr
;
160 static uint32 mec_mcr
; /* MEC control register */
161 static uint32 mec_memcfg
; /* Memory control register */
162 static uint32 mec_wcr
; /* MEC waitstate register */
163 static uint32 mec_iocr
; /* MEC IO control register */
164 static uint32 posted_irq
;
165 static uint32 mec_ersr
; /* MEC error and status register */
166 static uint32 mec_tcr
; /* MEC test comtrol register */
168 static uint32 rtc_counter
;
169 static uint32 rtc_reload
;
170 static uint32 rtc_scaler
;
171 static uint32 rtc_scaler_start
;
172 static uint32 rtc_enabled
;
173 static uint32 rtc_cr
;
174 static uint32 rtc_se
;
176 static uint32 gpt_counter
;
177 static uint32 gpt_reload
;
178 static uint32 gpt_scaler
;
179 static uint32 gpt_scaler_start
;
180 static uint32 gpt_enabled
;
181 static uint32 gpt_cr
;
182 static uint32 gpt_se
;
184 static uint32 wdog_scaler
;
185 static uint32 wdog_counter
;
186 static uint32 wdog_rst_delay
;
187 static uint32 wdog_rston
;
190 init
, disabled
, enabled
, stopped
193 static enum wdog_type wdog_status
;
196 /* ROM size 1024 Kbyte */
197 #define ROM_SZ 0x100000
198 #define ROM_MASK 0x0fffff
200 /* RAM size 4 Mbyte */
201 #define RAM_START 0x02000000
202 #define RAM_END 0x02400000
203 #define RAM_MASK 0x003fffff
205 /* SPARClite boards all seem to have RAM at the same place. */
206 #define RAM_START_SLITE 0x40000000
207 #define RAM_END_SLITE 0x40400000
208 #define RAM_MASK_SLITE 0x003fffff
210 /* Memory support variables */
212 static uint32 mem_ramr_ws
; /* RAM read waitstates */
213 static uint32 mem_ramw_ws
; /* RAM write waitstates */
214 static uint32 mem_romr_ws
; /* ROM read waitstates */
215 static uint32 mem_romw_ws
; /* ROM write waitstates */
216 static uint32 mem_ramstart
; /* RAM start */
217 static uint32 mem_ramend
; /* RAM end */
218 static uint32 mem_rammask
; /* RAM address mask */
219 static uint32 mem_ramsz
; /* RAM size */
220 static uint32 mem_romsz
; /* ROM size */
221 static uint32 mem_accprot
; /* RAM write protection enabled */
222 static uint32 mem_blockprot
; /* RAM block write protection enabled */
224 static unsigned char romb
[ROM_SZ
];
225 static unsigned char ramb
[RAM_END
- RAM_START
];
228 /* UART support variables */
230 static int32 fd1
, fd2
; /* file descriptor for input file */
231 static int32 Ucontrol
; /* UART status register */
232 static unsigned char aq
[UARTBUF
], bq
[UARTBUF
];
233 static int32 anum
, aind
= 0;
234 static int32 bnum
, bind
= 0;
235 static char wbufa
[UARTBUF
], wbufb
[UARTBUF
];
236 static unsigned wnuma
;
237 static unsigned wnumb
;
238 static FILE *f1in
, *f1out
, *f2in
, *f2out
;
239 static struct termios ioc1
, ioc2
, iocold1
, iocold2
;
240 static int f1open
= 0, f2open
= 0;
242 static char uarta_sreg
, uarta_hreg
, uartb_sreg
, uartb_hreg
;
243 static uint32 uart_stat_reg
;
244 static uint32 uarta_data
, uartb_data
;
251 /* Forward declarations */
253 static void decode_ersr (void);
255 static void iucomperr (void);
257 static void mecparerror (void);
258 static void decode_memcfg (void);
259 static void decode_wcr (void);
260 static void decode_mcr (void);
261 static void close_port (void);
262 static void mec_reset (void);
263 static void mec_intack (int32 level
);
264 static void chk_irq (void);
265 static void mec_irq (int32 level
);
266 static void set_sfsr (uint32 fault
, uint32 addr
,
267 uint32 asi
, uint32 read
);
268 static int32
mec_read (uint32 addr
, uint32 asi
, uint32
*data
);
269 static int mec_write (uint32 addr
, uint32 data
);
270 static void port_init (void);
271 static uint32
read_uart (uint32 addr
);
272 static void write_uart (uint32 addr
, uint32 data
);
273 static void flush_uart (void);
274 static void uarta_tx (void);
275 static void uartb_tx (void);
276 static void uart_rx (caddr_t arg
);
277 static void uart_intr (caddr_t arg
);
278 static void uart_irq_start (void);
279 static void wdog_intr (caddr_t arg
);
280 static void wdog_start (void);
281 static void rtc_intr (caddr_t arg
);
282 static void rtc_start (void);
283 static uint32
rtc_counter_read (void);
284 static void rtc_scaler_set (uint32 val
);
285 static void rtc_reload_set (uint32 val
);
286 static void gpt_intr (caddr_t arg
);
287 static void gpt_start (void);
288 static uint32
gpt_counter_read (void);
289 static void gpt_scaler_set (uint32 val
);
290 static void gpt_reload_set (uint32 val
);
291 static void timer_ctrl (uint32 val
);
292 static unsigned char *
293 get_mem_ptr (uint32 addr
, uint32 size
);
294 static void store_bytes (unsigned char *mem
, uint32 waddr
,
295 uint32
*data
, int sz
, int32
*ws
);
308 /* Power-on reset init */
321 if (mec_ersr
& 0x01) {
322 if (!(mec_mcr
& 0x20)) {
323 if (mec_mcr
& 0x40) {
327 printf("Error manager reset - IU in error mode\n");
332 printf("Error manager halt - IU in error mode\n");
337 if (mec_ersr
& 0x04) {
338 if (!(mec_mcr
& 0x200)) {
339 if (mec_mcr
& 0x400) {
343 printf("Error manager reset - IU comparison error\n");
348 printf("Error manager halt - IU comparison error\n");
353 if (mec_ersr
& 0x20) {
354 if (!(mec_mcr
& 0x2000)) {
355 if (mec_mcr
& 0x4000) {
359 printf("Error manager reset - MEC hardware error\n");
364 printf("Error manager halt - MEC hardware error\n");
388 /* IU error mode manager */
400 /* Check memory settings */
405 if (rom8
) mec_memcfg
&= ~0x20000;
406 else mec_memcfg
|= 0x20000;
408 mem_ramsz
= (256 * 1024) << ((mec_memcfg
>> 10) & 7);
409 mem_romsz
= (128 * 1024) << ((mec_memcfg
>> 18) & 7);
411 if (sparclite_board
) {
412 mem_ramstart
= RAM_START_SLITE
;
413 mem_ramend
= RAM_END_SLITE
;
414 mem_rammask
= RAM_MASK_SLITE
;
417 mem_ramstart
= RAM_START
;
418 mem_ramend
= RAM_END
;
419 mem_rammask
= RAM_MASK
;
422 printf("RAM start: 0x%x, RAM size: %d K, ROM size: %d K\n",
423 mem_ramstart
, mem_ramsz
>> 10, mem_romsz
>> 10);
429 mem_ramr_ws
= mec_wcr
& 3;
430 mem_ramw_ws
= (mec_wcr
>> 2) & 3;
431 mem_romr_ws
= (mec_wcr
>> 4) & 0x0f;
433 if (mem_romr_ws
> 0 ) mem_romr_ws
--;
434 mem_romr_ws
= 5 + (4*mem_romr_ws
);
436 mem_romw_ws
= (mec_wcr
>> 8) & 0x0f;
438 printf("Waitstates = RAM read: %d, RAM write: %d, ROM read: %d, ROM write: %d\n",
439 mem_ramr_ws
, mem_ramw_ws
, mem_romr_ws
, mem_romw_ws
);
445 mem_accprot
= (mec_wpr
[0] | mec_wpr
[1]);
446 mem_blockprot
= (mec_mcr
>> 3) & 1;
447 if (sis_verbose
&& mem_accprot
)
448 printf("Memory block write protection enabled\n");
449 if (mec_mcr
& 0x08000) {
453 if (sis_verbose
&& (mec_mcr
& 2))
454 printf("Software reset enabled\n");
455 if (sis_verbose
&& (mec_mcr
& 1))
456 printf("Power-down mode enabled\n");
459 /* Flush ports when simulator stops */
470 sim_stop(SIM_DESC sd
)
479 if (f1open
&& f1in
!= stdin
)
481 if (f2open
&& f2in
!= stdin
)
497 for (i
= 0; i
< 2; i
++)
498 mec_ssa
[i
] = mec_sea
[i
] = mec_wpr
[i
] = 0;
499 mec_mcr
= 0x01350014;
508 mec_memcfg
= 0x10000;
510 mec_ersr
= 0; /* MEC error and status register */
511 mec_tcr
= 0; /* MEC test comtrol register */
519 anum
= aind
= bnum
= bind
= 0;
521 uart_stat_reg
= UARTA_SRE
| UARTA_HRE
| UARTB_SRE
| UARTB_HRE
;
522 uarta_data
= uartb_data
= UART_THE
| UART_TSE
;
524 rtc_counter
= 0xffffffff;
525 rtc_reload
= 0xffffffff;
531 gpt_counter
= 0xffffffff;
532 gpt_reload
= 0xffffffff;
539 wdog_rst_delay
= 255;
540 wdog_counter
= 0xffff;
559 printf("interrupt %d acknowledged\n", level
);
560 irq_test
= mec_tcr
& 0x80000;
561 if ((irq_test
) && (mec_ifr
& (1 << level
)))
562 mec_ifr
&= ~(1 << level
);
564 mec_ipr
&= ~(1 << level
);
576 if (mec_tcr
& 0x80000) itmp
= mec_ifr
;
578 itmp
= ((mec_ipr
| itmp
) & ~mec_imr
) & 0x0fffe;
581 for (i
= 15; i
> 0; i
--) {
582 if (((itmp
>> i
) & 1) != 0) {
583 if ((sis_verbose
) && (i
> old_irl
))
584 printf("IU irl: %d\n", i
);
586 set_int(i
, mec_intack
, i
);
597 mec_ipr
|= (1 << level
);
602 set_sfsr(fault
, addr
, asi
, read
)
608 if ((asi
== 0xa) || (asi
== 0xb)) {
610 mec_sfsr
= (fault
<< 3) | (!read
<< 15);
611 mec_sfsr
|= ((mec_sfsr
& 1) ^ 1) | (mec_sfsr
& 1);
624 mec_read(addr
, asi
, data
)
630 switch (addr
& 0x0ff) {
632 case MEC_MCR
: /* 0x00 */
636 case MEC_MEMCFG
: /* 0x10 */
641 *data
= mec_iocr
; /* 0x14 */
644 case MEC_SSA1
: /* 0x20 */
645 *data
= mec_ssa
[0] | (mec_wpr
[0] << 23);
647 case MEC_SEA1
: /* 0x24 */
650 case MEC_SSA2
: /* 0x28 */
651 *data
= mec_ssa
[1] | (mec_wpr
[1] << 23);
653 case MEC_SEA2
: /* 0x2c */
657 case MEC_ISR
: /* 0x44 */
661 case MEC_IPR
: /* 0x48 */
665 case MEC_IMR
: /* 0x4c */
669 case MEC_IFR
: /* 0x54 */
673 case MEC_RTC_COUNTER
: /* 0x80 */
674 *data
= rtc_counter_read();
676 case MEC_RTC_SCALER
: /* 0x84 */
678 *data
= rtc_scaler
- (now() - rtc_scaler_start
);
683 case MEC_GPT_COUNTER
: /* 0x88 */
684 *data
= gpt_counter_read();
687 case MEC_GPT_SCALER
: /* 0x8c */
689 *data
= gpt_scaler
- (now() - gpt_scaler_start
);
695 case MEC_SFSR
: /* 0xA0 */
699 case MEC_FFAR
: /* 0xA4 */
706 strcpy(fname
, "simload");
707 find
= bfd_load(fname
);
715 case MEC_ERSR
: /* 0xB0 */
719 case MEC_TCR
: /* 0xD0 */
723 case MEC_UARTA
: /* 0xE0 */
724 case MEC_UARTB
: /* 0xE4 */
726 set_sfsr(MEC_ACC
, addr
, asi
, 1);
729 *data
= read_uart(addr
);
732 case MEC_UART_CTRL
: /* 0xE8 */
734 *data
= read_uart(addr
);
737 case 0xF4: /* simulator RAM size in bytes */
741 case 0xF8: /* simulator ROM size in bytes */
746 set_sfsr(MEC_ACC
, addr
, asi
, 1);
754 mec_write(addr
, data
)
759 printf("MEC write a: %08x, d: %08x\n",addr
,data
);
760 switch (addr
& 0x0ff) {
765 if (mec_mcr
& 0x08000) mecparerror();
773 printf(" Software reset issued\n");
779 if (mec_iocr
& 0xC0C0C0C0) mecparerror();
782 case MEC_SSA1
: /* 0x20 */
783 if (data
& 0xFE000000) mecparerror();
784 mec_ssa
[0] = data
& 0x7fffff;
785 mec_wpr
[0] = (data
>> 23) & 0x03;
786 mem_accprot
= mec_wpr
[0] || mec_wpr
[1];
787 if (sis_verbose
&& mec_wpr
[0])
788 printf("Segment 1 memory protection enabled (0x02%06x - 0x02%06x)\n",
789 mec_ssa
[0] << 2, mec_sea
[0] << 2);
791 case MEC_SEA1
: /* 0x24 */
792 if (data
& 0xFF800000) mecparerror();
793 mec_sea
[0] = data
& 0x7fffff;
795 case MEC_SSA2
: /* 0x28 */
796 if (data
& 0xFE000000) mecparerror();
797 mec_ssa
[1] = data
& 0x7fffff;
798 mec_wpr
[1] = (data
>> 23) & 0x03;
799 mem_accprot
= mec_wpr
[0] || mec_wpr
[1];
800 if (sis_verbose
&& mec_wpr
[1])
801 printf("Segment 2 memory protection enabled (0x02%06x - 0x02%06x)\n",
802 mec_ssa
[1] << 2, mec_sea
[1] << 2);
804 case MEC_SEA2
: /* 0x2c */
805 if (data
& 0xFF800000) mecparerror();
806 mec_sea
[1] = data
& 0x7fffff;
811 if (data
& 0xFFFFFF00) mecparerror();
813 if (data
& 0xFF00FF00) mecparerror();
814 write_uart(addr
, data
);
818 gpt_reload_set(data
);
822 if (data
& 0xFFFF0000) mecparerror();
823 gpt_scaler_set(data
);
827 if (data
& 0xFFFFF0F0) mecparerror();
832 rtc_reload_set(data
);
836 if (data
& 0xFFFFFF00) mecparerror();
837 rtc_scaler_set(data
);
840 case MEC_SFSR
: /* 0xA0 */
841 if (data
& 0xFFFF0880) mecparerror();
846 if (data
& 0xFFFFE000) mecparerror();
850 case MEC_IMR
: /* 0x4c */
852 if (data
& 0xFFFF8001) mecparerror();
853 mec_imr
= data
& 0x7ffe;
857 case MEC_ICR
: /* 0x50 */
859 if (data
& 0xFFFF0001) mecparerror();
860 mec_ipr
&= ~data
& 0x0fffe;
864 case MEC_IFR
: /* 0x54 */
866 if (mec_tcr
& 0x080000) {
867 if (data
& 0xFFFF0001) mecparerror();
868 mec_ifr
= data
& 0xfffe;
873 fname
[find
++] = (char) data
;
877 case MEC_MEMCFG
: /* 0x10 */
878 if (data
& 0xC0E08000) mecparerror();
881 if (mec_memcfg
& 0xc0e08000)
885 case MEC_WCR
: /* 0x18 */
890 case MEC_ERSR
: /* 0xB0 */
891 if (mec_tcr
& 0x100000)
892 if (data
& 0xFFFFEFC0) mecparerror();
893 mec_ersr
= data
& 0x103f;
896 case MEC_TCR
: /* 0xD0 */
897 if (data
& 0xFFE1FFC0) mecparerror();
898 mec_tcr
= data
& 0x1e003f;
901 case MEC_WDOG
: /* 0x60 */
902 wdog_scaler
= (data
>> 16) & 0x0ff;
903 wdog_counter
= data
& 0x0ffff;
904 wdog_rst_delay
= data
>> 24;
906 if (wdog_status
== stopped
)
908 wdog_status
= enabled
;
911 case MEC_TRAPD
: /* 0x64 */
912 if (wdog_status
== init
) {
913 wdog_status
= disabled
;
915 printf("Watchdog disabled\n");
925 set_sfsr(MEC_ACC
, addr
, 0xb, 0);
935 static int ifd1
= -1, ifd2
= -1, ofd1
= -1, ofd2
= -1;
941 return; /* do nothing */
943 tcsetattr(0, TCSANOW
, &ioc1
);
945 tcsetattr(0, TCSANOW
, &ioc2
);
952 return; /* do nothing */
954 tcsetattr(0, TCSANOW
, &iocold1
);
956 tcsetattr(0, TCSANOW
, &iocold2
);
959 #define DO_STDIO_READ( _fd_, _buf_, _len_ ) \
961 ? (0) /* no bytes read, no delay */ \
962 : read( _fd_, _buf_, _len_ ) )
980 if (uart_dev1
[0] != 0)
981 if ((fd1
= open(uart_dev1
, O_RDWR
| O_NONBLOCK
)) < 0) {
982 printf("Warning, couldn't open output device %s\n", uart_dev1
);
985 printf("serial port A on %s\n", uart_dev1
);
986 f1in
= f1out
= fdopen(fd1
, "r+");
990 if (f1in
) ifd1
= fileno(f1in
);
993 printf("serial port A on stdin/stdout\n");
995 tcgetattr(ifd1
, &ioc1
);
997 ioc1
.c_lflag
&= ~(ICANON
| ECHO
);
999 ioc1
.c_cc
[VTIME
] = 0;
1005 ofd1
= fileno(f1out
);
1006 if (!dumbio
&& ofd1
== 1) setbuf(f1out
, NULL
);
1009 if (uart_dev2
[0] != 0)
1010 if ((fd2
= open(uart_dev2
, O_RDWR
| O_NONBLOCK
)) < 0) {
1011 printf("Warning, couldn't open output device %s\n", uart_dev2
);
1014 printf("serial port B on %s\n", uart_dev2
);
1015 f2in
= f2out
= fdopen(fd2
, "r+");
1016 setbuf(f2out
, NULL
);
1019 if (f2in
) ifd2
= fileno(f2in
);
1022 printf("serial port B on stdin/stdout\n");
1024 tcgetattr(ifd2
, &ioc2
);
1026 ioc2
.c_lflag
&= ~(ICANON
| ECHO
);
1027 ioc2
.c_cc
[VMIN
] = 0;
1028 ioc2
.c_cc
[VTIME
] = 0;
1034 ofd2
= fileno(f2out
);
1035 if (!dumbio
&& ofd2
== 1) setbuf(f2out
, NULL
);
1050 switch (addr
& 0xff) {
1052 case 0xE0: /* UART 1 */
1057 if ((aind
+ 1) < anum
)
1059 return (0x700 | (uint32
) aq
[aind
++]);
1062 anum
= DO_STDIO_READ(ifd1
, aq
, UARTBUF
);
1066 if ((aind
+ 1) < anum
)
1068 return (0x700 | (uint32
) aq
[aind
++]);
1070 return (0x600 | (uint32
) aq
[aind
]);
1076 uarta_data
&= ~UART_DR
;
1077 uart_stat_reg
&= ~UARTA_DR
;
1085 case 0xE4: /* UART 2 */
1089 if ((bind
+ 1) < bnum
)
1091 return (0x700 | (uint32
) bq
[bind
++]);
1094 bnum
= DO_STDIO_READ(ifd2
, bq
, UARTBUF
);
1098 if ((bind
+ 1) < bnum
)
1100 return (0x700 | (uint32
) bq
[bind
++]);
1102 return (0x600 | (uint32
) bq
[bind
]);
1108 uartb_data
&= ~UART_DR
;
1109 uart_stat_reg
&= ~UARTB_DR
;
1117 case 0xE8: /* UART status register */
1123 Ucontrol
|= 0x00000001;
1126 anum
= DO_STDIO_READ(ifd1
, aq
, UARTBUF
);
1129 Ucontrol
|= 0x00000001;
1135 Ucontrol
|= 0x00010000;
1138 bnum
= DO_STDIO_READ(ifd2
, bq
, UARTBUF
);
1141 Ucontrol
|= 0x00010000;
1147 Ucontrol
|= 0x00060006;
1150 return uart_stat_reg
;
1158 printf("Read from unimplemented MEC register (%x)\n", addr
);
1165 write_uart(addr
, data
)
1171 c
= (unsigned char) data
;
1172 switch (addr
& 0xff) {
1174 case 0xE0: /* UART A */
1177 if (wnuma
< UARTBUF
)
1181 wnuma
-= fwrite(wbufa
, 1, wnuma
, f1out
);
1187 if (uart_stat_reg
& UARTA_SRE
) {
1189 uart_stat_reg
&= ~UARTA_SRE
;
1190 event(uarta_tx
, 0, UART_TX_TIME
);
1193 uart_stat_reg
&= ~UARTA_HRE
;
1198 case 0xE4: /* UART B */
1201 if (wnumb
< UARTBUF
)
1205 wnumb
-= fwrite(wbufb
, 1, wnumb
, f2out
);
1211 if (uart_stat_reg
& UARTB_SRE
) {
1213 uart_stat_reg
&= ~UARTB_SRE
;
1214 event(uartb_tx
, 0, UART_TX_TIME
);
1217 uart_stat_reg
&= ~UARTB_HRE
;
1221 case 0xE8: /* UART status register */
1223 if (data
& UARTA_CLR
) {
1224 uart_stat_reg
&= 0xFFFF0000;
1225 uart_stat_reg
|= UARTA_SRE
| UARTA_HRE
;
1227 if (data
& UARTB_CLR
) {
1228 uart_stat_reg
&= 0x0000FFFF;
1229 uart_stat_reg
|= UARTB_SRE
| UARTB_HRE
;
1235 printf("Write to unimplemented MEC register (%x)\n", addr
);
1243 while (wnuma
&& f1open
)
1244 wnuma
-= fwrite(wbufa
, 1, wnuma
, f1out
);
1245 while (wnumb
&& f2open
)
1246 wnumb
-= fwrite(wbufb
, 1, wnumb
, f2out
);
1255 while (f1open
&& fwrite(&uarta_sreg
, 1, 1, f1out
) != 1);
1256 if (uart_stat_reg
& UARTA_HRE
) {
1257 uart_stat_reg
|= UARTA_SRE
;
1259 uarta_sreg
= uarta_hreg
;
1260 uart_stat_reg
|= UARTA_HRE
;
1261 event(uarta_tx
, 0, UART_TX_TIME
);
1269 while (f2open
&& fwrite(&uartb_sreg
, 1, 1, f2out
) != 1);
1270 if (uart_stat_reg
& UARTB_HRE
) {
1271 uart_stat_reg
|= UARTB_SRE
;
1273 uartb_sreg
= uartb_hreg
;
1274 uart_stat_reg
|= UARTB_HRE
;
1275 event(uartb_tx
, 0, UART_TX_TIME
);
1290 rsize
= DO_STDIO_READ(ifd1
, &rxd
, 1);
1292 uarta_data
= UART_DR
| rxd
;
1293 if (uart_stat_reg
& UARTA_HRE
)
1294 uarta_data
|= UART_THE
;
1295 if (uart_stat_reg
& UARTA_SRE
)
1296 uarta_data
|= UART_TSE
;
1297 if (uart_stat_reg
& UARTA_DR
) {
1298 uart_stat_reg
|= UARTA_OR
;
1299 mec_irq(7); /* UART error interrupt */
1301 uart_stat_reg
|= UARTA_DR
;
1306 rsize
= DO_STDIO_READ(ifd2
, &rxd
, 1);
1308 uartb_data
= UART_DR
| rxd
;
1309 if (uart_stat_reg
& UARTB_HRE
)
1310 uartb_data
|= UART_THE
;
1311 if (uart_stat_reg
& UARTB_SRE
)
1312 uartb_data
|= UART_TSE
;
1313 if (uart_stat_reg
& UARTB_DR
) {
1314 uart_stat_reg
|= UARTB_OR
;
1315 mec_irq(7); /* UART error interrupt */
1317 uart_stat_reg
|= UARTB_DR
;
1320 event(uart_rx
, 0, UART_RX_TIME
);
1327 read_uart(0xE8); /* Check for UART interrupts every 1000 clk */
1328 flush_uart(); /* Flush UART ports */
1329 event(uart_intr
, 0, UART_FLUSH_TIME
);
1337 event(uart_intr
, 0, UART_FLUSH_TIME
);
1340 event(uart_rx
, 0, UART_RX_TIME
);
1351 if (wdog_status
== disabled
) {
1352 wdog_status
= stopped
;
1357 event(wdog_intr
, 0, wdog_scaler
+ 1);
1360 printf("Watchdog reset!\n");
1366 wdog_counter
= wdog_rst_delay
;
1367 event(wdog_intr
, 0, wdog_scaler
+ 1);
1376 event(wdog_intr
, 0, wdog_scaler
+ 1);
1378 printf("Watchdog started, scaler = %d, counter = %d\n",
1379 wdog_scaler
, wdog_counter
);
1390 if (rtc_counter
== 0) {
1394 rtc_counter
= rtc_reload
;
1400 event(rtc_intr
, 0, rtc_scaler
+ 1);
1401 rtc_scaler_start
= now();
1405 printf("RTC stopped\n\r");
1414 printf("RTC started (period %d)\n\r", rtc_scaler
+ 1);
1415 event(rtc_intr
, 0, rtc_scaler
+ 1);
1416 rtc_scaler_start
= now();
1430 rtc_scaler
= val
& 0x0ff; /* eight-bit scaler only */
1444 if (gpt_counter
== 0) {
1447 gpt_counter
= gpt_reload
;
1453 event(gpt_intr
, 0, gpt_scaler
+ 1);
1454 gpt_scaler_start
= now();
1458 printf("GPT stopped\n\r");
1467 printf("GPT started (period %d)\n\r", gpt_scaler
+ 1);
1468 event(gpt_intr
, 0, gpt_scaler
+ 1);
1469 gpt_scaler_start
= now();
1483 gpt_scaler
= val
& 0x0ffff; /* 16-bit scaler */
1498 rtc_cr
= ((val
& TCR_TCRCR
) != 0);
1499 if (val
& TCR_TCRCL
) {
1500 rtc_counter
= rtc_reload
;
1502 if (val
& TCR_TCRSL
) {
1504 rtc_se
= ((val
& TCR_TCRSE
) != 0);
1505 if (rtc_se
&& (rtc_enabled
== 0))
1508 gpt_cr
= (val
& TCR_GACR
);
1509 if (val
& TCR_GACL
) {
1510 gpt_counter
= gpt_reload
;
1512 if (val
& TCR_GACL
) {
1514 gpt_se
= (val
& TCR_GASE
) >> 2;
1515 if (gpt_se
&& (gpt_enabled
== 0))
1519 /* Store data in host byte order. MEM points to the beginning of the
1520 emulated memory; WADDR contains the index the emulated memory,
1521 DATA points to words in host byte order to be stored. SZ contains log(2)
1522 of the number of bytes to retrieve, and can be 0 (1 byte), 1 (one half-word),
1523 2 (one word), or 3 (two words); WS should return the number of
1527 store_bytes (unsigned char *mem
, uint32 waddr
, uint32
*data
, int32 sz
,
1533 mem
[waddr
] = *data
& 0x0ff;
1534 *ws
= mem_ramw_ws
+ 3;
1537 #ifdef HOST_LITTLE_ENDIAN
1540 memcpy (&mem
[waddr
], data
, 2);
1541 *ws
= mem_ramw_ws
+ 3;
1544 memcpy (&mem
[waddr
], data
, 4);
1548 memcpy (&mem
[waddr
], data
, 8);
1549 *ws
= 2 * mem_ramw_ws
+ STD_WS
;
1555 /* Memory emulation */
1558 memory_iread (uint32 addr
, uint32
*data
, int32
*ws
)
1561 if ((addr
>= mem_ramstart
) && (addr
< (mem_ramstart
+ mem_ramsz
))) {
1562 memcpy (data
, &ramb
[addr
& mem_rammask
& ~3], 4);
1565 } else if (addr
< mem_romsz
) {
1566 memcpy (data
, &romb
[addr
& ~3], 4);
1572 printf ("Memory exception at %x (illegal address)\n", addr
);
1573 if (sregs
.psr
& 0x080)
1577 set_sfsr (UIMP_ACC
, addr
, asi
, 1);
1583 memory_read(asi
, addr
, data
, sz
, ws
)
1595 printf("Inserted MEC error %d\n",errmec
);
1596 set_sfsr(errmec
, addr
, asi
, 1);
1597 if (errmec
== 5) mecparerror();
1598 if (errmec
== 6) iucomperr();
1604 if ((addr
>= mem_ramstart
) && (addr
< (mem_ramstart
+ mem_ramsz
))) {
1605 memcpy (data
, &ramb
[addr
& mem_rammask
& ~3], 4);
1608 } else if ((addr
>= MEC_START
) && (addr
< MEC_END
)) {
1609 mexc
= mec_read(addr
, asi
, data
);
1611 set_sfsr(MEC_ACC
, addr
, asi
, 1);
1621 if ((addr
< 0x100000) ||
1622 ((addr
>= 0x80000000) && (addr
< 0x80100000))) {
1623 memcpy (data
, &romb
[addr
& ROM_MASK
& ~3], 4);
1626 } else if ((addr
>= 0x10000000) &&
1627 (addr
< (0x10000000 + (512 << (mec_iocr
& 0x0f)))) &&
1628 (mec_iocr
& 0x10)) {
1633 } else if (addr
< mem_romsz
) {
1634 memcpy (data
, &romb
[addr
& ~3], 4);
1638 } else if (addr
< mem_romsz
) {
1639 memcpy (data
, &romb
[addr
& ~3], 4);
1647 printf ("Memory exception at %x (illegal address)\n", addr
);
1648 set_sfsr(UIMP_ACC
, addr
, asi
, 1);
1654 memory_write(asi
, addr
, data
, sz
, ws
)
1672 printf("Inserted MEC error %d\n",errmec
);
1673 set_sfsr(errmec
, addr
, asi
, 0);
1674 if (errmec
== 5) mecparerror();
1675 if (errmec
== 6) iucomperr();
1681 if ((addr
>= mem_ramstart
) && (addr
< (mem_ramstart
+ mem_ramsz
))) {
1684 waddr
= (addr
& 0x7fffff) >> 2;
1685 for (i
= 0; i
< 2; i
++)
1687 (((asi
== 0xa) && (mec_wpr
[i
] & 1)) ||
1688 ((asi
== 0xb) && (mec_wpr
[i
] & 2))) &&
1689 ((waddr
>= mec_ssa
[i
]) && ((waddr
| (sz
== 3)) < mec_sea
[i
]));
1691 if (((mem_blockprot
) && (wphit
[0] || wphit
[1])) ||
1692 ((!mem_blockprot
) &&
1693 !((mec_wpr
[0] && wphit
[0]) || (mec_wpr
[1] && wphit
[1]))
1696 printf("Memory access protection error at 0x%08x\n", addr
);
1697 set_sfsr(PROT_EXC
, addr
, asi
, 0);
1702 waddr
= addr
& mem_rammask
;
1703 store_bytes (ramb
, waddr
, data
, sz
, ws
);
1705 } else if ((addr
>= MEC_START
) && (addr
< MEC_END
)) {
1706 if ((sz
!= 2) || (asi
!= 0xb)) {
1707 set_sfsr(MEC_ACC
, addr
, asi
, 0);
1711 mexc
= mec_write(addr
, *data
);
1713 set_sfsr(MEC_ACC
, addr
, asi
, 0);
1724 ((addr
< 0x100000) || ((addr
>= 0x80000000) && (addr
< 0x80100000)))) {
1726 *ws
= sz
== 3 ? 8 : 4;
1727 store_bytes (romb
, addr
, data
, sz
, ws
);
1729 } else if ((addr
>= 0x10000000) &&
1730 (addr
< (0x10000000 + (512 << (mec_iocr
& 0x0f)))) &&
1731 (mec_iocr
& 0x10)) {
1732 erareg
= *data
& 0x0e;
1736 } else if ((addr
< mem_romsz
) && (mec_memcfg
& 0x10000) && (wrp
) &&
1737 (((mec_memcfg
& 0x20000) && (sz
> 1)) ||
1738 (!(mec_memcfg
& 0x20000) && (sz
== 0)))) {
1740 *ws
= mem_romw_ws
+ 1;
1742 *ws
+= mem_romw_ws
+ STD_WS
;
1743 store_bytes (romb
, addr
, data
, sz
, ws
);
1747 } else if ((addr
< mem_romsz
) && (mec_memcfg
& 0x10000) && (wrp
) &&
1748 (((mec_memcfg
& 0x20000) && (sz
> 1)) ||
1749 (!(mec_memcfg
& 0x20000) && (sz
== 0)))) {
1751 *ws
= mem_romw_ws
+ 1;
1753 *ws
+= mem_romw_ws
+ STD_WS
;
1754 store_bytes (romb
, addr
, data
, sz
, ws
);
1762 set_sfsr(UIMP_ACC
, addr
, asi
, 0);
1766 static unsigned char *
1767 get_mem_ptr(addr
, size
)
1771 if ((addr
+ size
) < ROM_SZ
) {
1773 } else if ((addr
>= mem_ramstart
) && ((addr
+ size
) < mem_ramend
)) {
1774 return &ramb
[addr
& mem_rammask
];
1778 else if ((era
) && ((addr
<0x100000) ||
1779 ((addr
>= (unsigned) 0x80000000) && ((addr
+ size
) < (unsigned) 0x80100000)))) {
1780 return &romb
[addr
& ROM_MASK
];
1788 sis_memory_write(addr
, data
, length
)
1790 const unsigned char *data
;
1795 if ((mem
= get_mem_ptr(addr
, length
)) == ((char *) -1))
1798 memcpy(mem
, data
, length
);
1803 sis_memory_read(addr
, data
, length
)
1810 if ((mem
= get_mem_ptr(addr
, length
)) == ((char *) -1))
1813 memcpy(data
, mem
, length
);
1817 extern struct pstate sregs
;
1822 mec_write(MEC_WCR
, 0); /* zero waitstates */
1823 mec_write(MEC_TRAPD
, 0); /* turn off watch-dog */
1824 mec_write(MEC_RTC_SCALER
, sregs
.freq
- 1); /* generate 1 MHz RTC tick */
1825 mec_write(MEC_MEMCFG
, (3 << 18) | (4 << 10)); /* 1 MB ROM, 4 MB RAM */
1827 sregs
.psr
= 0x110010e0;
1828 sregs
.r
[30] = RAM_END
;
1829 sregs
.r
[14] = sregs
.r
[30] - 96 * 4;
1830 mec_mcr
|= 1; /* power-down enabled */
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