sim/frv/pipeline.c

   1 /* frv vliw model.
   2    Copyright (C) 1999-2001, 2003, 2007-2012 Free Software Foundation,
   3    Inc.
   4    Contributed by Red Hat.
   5
   6 This file is part of the GNU simulators.
   7
   8 This program is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 3 of the License, or
  11 (at your option) any later version.
  12
  13 This program is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #define WANT_CPU frvbf
  22 #define WANT_CPU_FRVBF
  23
  24 #include "sim-main.h"
  25
  26 /* Simulator specific vliw related functions.  Additional vliw related
  27    code used by both the simulator and the assembler is in frv.opc.  */
  28
  29 int insns_in_slot[UNIT_NUM_UNITS] = {0};
  30
  31 void
  32 frv_vliw_setup_insn (SIM_CPU *current_cpu, const CGEN_INSN *insn)
  33 {
  34   FRV_VLIW *vliw;
  35   int index;
  36
  37   /* Always clear the NE index which indicates the target register
  38      of a non excepting insn. This will be reset by the insn if
  39      necessary.  */
  40   frv_interrupt_state.ne_index = NE_NOFLAG;
  41
  42   vliw = CPU_VLIW (current_cpu);
  43   index = vliw->next_slot - 1;
  44   if (frv_is_float_insn (insn))
  45     {
  46       /* If the insn is to be added and is a floating point insn and
  47          it is the first floating point insn in the vliw, then clear
  48          FSR0.FTT.  */
  49       int i;
  50       for (i = 0; i < index; ++i)
  51         if (frv_is_float_major (vliw->major[i], vliw->mach))
  52           break; /* found float insn.  */
  53       if (i >= index)
  54         {
  55           SI fsr0 = GET_FSR (0);
  56           SET_FSR_FTT (fsr0, FTT_NONE);
  57           SET_FSR (0, fsr0);
  58         }
  59     }
  60   else if (frv_is_media_insn (insn))
  61     {
  62       /* Clear the appropriate MSR fields depending on which slot
  63          this insn is in.  */
  64       CGEN_ATTR_VALUE_ENUM_TYPE preserve_ovf;
  65       SI msr0 = GET_MSR (0);
  66
  67       preserve_ovf = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_PRESERVE_OVF);
  68       if ((*vliw->current_vliw)[index] == UNIT_FM0)
  69         {
  70           if (! preserve_ovf)
  71             {
  72               /* Clear MSR0.OVF and MSR0.SIE.  */
  73               CLEAR_MSR_SIE (msr0);
  74               CLEAR_MSR_OVF (msr0);
  75             }
  76         }
  77       else
  78         {
  79           if (! preserve_ovf)
  80             {
  81               /* Clear MSR1.OVF and MSR1.SIE.  */
  82               SI msr1 = GET_MSR (1);
  83               CLEAR_MSR_SIE (msr1);
  84               CLEAR_MSR_OVF (msr1);
  85               SET_MSR (1, msr1);
  86             }
  87         }
  88       SET_MSR (0, msr0);
  89     } /* Insn is a media insns.  */
  90   COUNT_INSNS_IN_SLOT ((*vliw->current_vliw)[index]);
  91 }
  92