sim/h8300/compile.c

   1 /*
   2  * Simulator for the Hitachi H8/300 architecture.
   3  *
   4  * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
   5  *
   6  * This file is part of H8/300 sim
   7  *
   8  *
   9  * THIS SOFTWARE IS NOT COPYRIGHTED
  10  *
  11  * Cygnus offers the following for use in the public domain.  Cygnus makes no
  12  * warranty with regard to the software or its performance and the user
  13  * accepts the software "AS IS" with all faults.
  14  *
  15  * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
  16  * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
  17  * AND FITNESS FOR A PARTICULAR PURPOSE.
  18  */
  19
  20 #include "config.h"
  21
  22 #include <signal.h>
  23 #ifdef HAVE_TIME_H
  24 #include <time.h>
  25 #endif
  26 #ifdef HAVE_STDLIB_H
  27 #include <stdlib.h>
  28 #endif
  29 #include <sys/param.h>
  30 #include "wait.h"
  31 #include "ansidecl.h"
  32 #include "callback.h"
  33 #include "remote-sim.h"
  34 #include "bfd.h"
  35
  36 int debug;
  37
  38
  39 #define X(op, size)  op*4+size
  40
  41 #define SP (h8300hmode ? SL:SW)
  42 #define SB 0
  43 #define SW 1
  44 #define SL 2
  45 #define OP_REG 1
  46 #define OP_DEC 2
  47 #define OP_DISP 3
  48 #define OP_INC 4
  49 #define OP_PCREL 5
  50 #define OP_MEM 6
  51 #define OP_CCR 7
  52 #define OP_IMM 8
  53 #define OP_ABS 10
  54 #define h8_opcodes ops
  55 #define DEFINE_TABLE
  56 #include "opcode/h8300.h"
  57
  58 #include "inst.h"
  59
  60 #define LOW_BYTE(x) ((x) & 0xff)
  61 #define HIGH_BYTE(x) (((x)>>8) & 0xff)
  62 #define P(X,Y) ((X<<8) | Y)
  63
  64 #define BUILDSR()   cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C;
  65
  66 #define GETSR()             \
  67   c = (cpu.ccr >> 0) & 1;\
  68   v = (cpu.ccr >> 1) & 1;\
  69   nz = !((cpu.ccr >> 2) & 1);\
  70   n = (cpu.ccr >> 3) & 1;
  71
  72 #ifdef __CHAR_IS_SIGNED__
  73 #define SEXTCHAR(x) ((char)(x))
  74 #endif
  75
  76 #ifndef SEXTCHAR
  77 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff): x & 0xff)
  78 #endif
  79
  80 #define UEXTCHAR(x) ((x) & 0xff)
  81 #define UEXTSHORT(x) ((x) & 0xffff)
  82 #define SEXTSHORT(x) ((short)(x))
  83
  84 static cpu_state_type cpu;
  85
  86 int h8300hmode = 0;
  87 /* start-sanitize-h8s */
  88 int h8300smode = 0;
  89 /* end-sanitize-h8s */
  90
  91 static int memory_size;
  92
  93
  94 static int
  95 get_now ()
  96 {
  97 #ifndef WIN32
  98   return time (0);
  99 #endif
 100   return 0;
 101 }
 102
 103 static int
 104 now_persec ()
 105 {
 106   return 1;
 107 }
 108
 109
 110 static int
 111 bitfrom (x)
 112 {
 113   switch (x & SIZE)
 114     {
 115     case L_8:
 116       return SB;
 117     case L_16:
 118       return SW;
 119     case L_32:
 120       return SL;
 121     case L_P:
 122       return h8300hmode ? SL : SW;
 123     }
 124 }
 125
 126 static
 127 unsigned int
 128 lvalue (x, rn)
 129 {
 130   switch (x / 4)
 131     {
 132     case OP_DISP:
 133       if (rn == 8)
 134         {
 135           return X (OP_IMM, SP);
 136         }
 137       return X (OP_REG, SP);
 138
 139     case OP_MEM:
 140
 141       return X (OP_MEM, SP);
 142     default:
 143       abort ();
 144     }
 145 }
 146
 147 static unsigned int
 148 decode (addr, data, dst)
 149      int addr;
 150      unsigned char *data;
 151      decoded_inst *dst;
 152
 153 {
 154   int rs = 0;
 155   int rd = 0;
 156   int rdisp = 0;
 157   int abs = 0;
 158   int plen = 0;
 159   int bit = 0;
 160
 161   struct h8_opcode *q = h8_opcodes;
 162   int size = 0;
 163   dst->dst.type = -1;
 164   dst->src.type = -1;
 165   /* Find the exact opcode/arg combo */
 166   while (q->name)
 167     {
 168       op_type *nib;
 169       unsigned int len = 0;
 170
 171       nib = q->data.nib;
 172
 173       while (1)
 174         {
 175           op_type looking_for = *nib;
 176           int thisnib = data[len >> 1];
 177
 178           thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf);
 179
 180           if (looking_for < 16 && looking_for >= 0)
 181             {
 182               if (looking_for != thisnib)
 183                 goto fail;
 184             }
 185           else
 186             {
 187               if ((int) looking_for & (int) B31)
 188                 {
 189                   if (!(((int) thisnib & 0x8) != 0))
 190                     goto fail;
 191                   looking_for = (op_type) ((int) looking_for & ~(int)
 192                                            B31);
 193                   thisnib &= 0x7;
 194                 }
 195               if ((int) looking_for & (int) B30)
 196                 {
 197                   if (!(((int) thisnib & 0x8) == 0))
 198                     goto fail;
 199                   looking_for = (op_type) ((int) looking_for & ~(int) B30);
 200                 }
 201               if (looking_for & DBIT)
 202                 {
 203                   if ((looking_for & 5) != (thisnib & 5))
 204                     goto fail;
 205                   abs = (thisnib & 0x8) ? 2 : 1;
 206                 }
 207               else if (looking_for & (REG | IND | INC | DEC))
 208                 {
 209                   if (looking_for & REG)
 210                     {
 211                       /*
 212                        * Can work out size from the
 213                        * register
 214                        */
 215                       size = bitfrom (looking_for);
 216                     }
 217                   if (looking_for & SRC)
 218                     {
 219                       rs = thisnib;
 220                     }
 221                   else
 222                     {
 223                       rd = thisnib;
 224                     }
 225                 }
 226               else if (looking_for & L_16)
 227                 {
 228                   abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1];
 229                   plen = 16;
 230                   if (looking_for & (PCREL | DISP))
 231                     {
 232                       abs = (short) (abs);
 233                     }
 234                 }
 235               else if (looking_for & ABSJMP)
 236                 {
 237                   abs =
 238                     (data[1] << 16)
 239                     | (data[2] << 8)
 240                     | (data[3]);
 241                 }
 242               else if (looking_for & MEMIND)
 243                 {
 244                   abs = data[1];
 245                 }
 246               else if (looking_for & L_32)
 247                 {
 248                   int i = len >> 1;
 249                   abs = (data[i] << 24)
 250                     | (data[i + 1] << 16)
 251                     | (data[i + 2] << 8)
 252                     | (data[i + 3]);
 253
 254                   plen = 32;
 255                 }
 256               else if (looking_for & L_24)
 257                 {
 258                   int i = len >> 1;
 259                   abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]);
 260                   plen = 24;
 261                 }
 262               else if (looking_for & IGNORE)
 263                 {
 264                   /* nothing to do */
 265                 }
 266               else if (looking_for & DISPREG)
 267                 {
 268                   rdisp = thisnib & 0x7;
 269                 }
 270               else if (looking_for & KBIT)
 271                 {
 272                   switch (thisnib)
 273                     {
 274                     case 9:
 275                       abs = 4;
 276                       break;
 277                     case 8:
 278                       abs = 2;
 279                       break;
 280                     case 0:
 281                       abs = 1;
 282                       break;
 283                     }
 284                 }
 285               else if (looking_for & L_8)
 286                 {
 287                   plen = 8;
 288
 289                   if (looking_for & PCREL)
 290                     {
 291                       abs = SEXTCHAR (data[len >> 1]);
 292                     }
 293                   else if (looking_for & ABS8MEM)
 294                     {
 295                       plen = 8;
 296                       abs = h8300hmode ? ~0xff0000ff : ~0xffff00ff;
 297                       abs |= data[len >> 1] & 0xff ;
 298                     }
 299                    else
 300                     {
 301                       abs = data[len >> 1] & 0xff;
 302                     }
 303                 }
 304               else if (looking_for & L_3)
 305                 {
 306                   plen = 3;
 307
 308                   bit = thisnib;
 309                 }
 310               else if (looking_for == E)
 311                 {
 312                   dst->op = q;
 313
 314                   /* Fill in the args */
 315                   {
 316                     op_type *args = q->args.nib;
 317                     int hadone = 0;
 318
 319                     while (*args != E)
 320                       {
 321                         int x = *args;
 322                         int rn = (x & DST) ? rd : rs;
 323                         ea_type *p;
 324
 325                         if (x & DST)
 326                           {
 327                             p = &(dst->dst);
 328                           }
 329                         else
 330                           {
 331                             p = &(dst->src);
 332                           }
 333
 334                         if (x & (L_3))
 335                           {
 336                             p->type = X (OP_IMM, size);
 337                             p->literal = bit;
 338                           }
 339                         else if (x & (IMM | KBIT | DBIT))
 340                           {
 341                             p->type = X (OP_IMM, size);
 342                             p->literal = abs;
 343                           }
 344                         else if (x & REG)
 345                           {
 346                             /* Reset the size, some
 347                                ops (like mul) have two sizes */
 348
 349                             size = bitfrom (x);
 350                             p->type = X (OP_REG, size);
 351                             p->reg = rn;
 352                           }
 353                         else if (x & INC)
 354                           {
 355                             p->type = X (OP_INC, size);
 356                             p->reg = rn & 0x7;
 357                           }
 358                         else if (x & DEC)
 359                           {
 360                             p->type = X (OP_DEC, size);
 361                             p->reg = rn & 0x7;
 362                           }
 363                         else if (x & IND)
 364                           {
 365                             p->type = X (OP_DISP, size);
 366                             p->reg = rn & 0x7;
 367                             p->literal = 0;
 368                           }
 369                         else if (x & (ABS | ABSJMP | ABS8MEM))
 370                           {
 371                             p->type = X (OP_DISP, size);
 372                             p->literal = abs;
 373                             p->reg = 8;
 374                           }
 375                         else if (x & MEMIND)
 376                           {
 377                             p->type = X (OP_MEM, size);
 378                             p->literal = abs;
 379                           }
 380                         else if (x & PCREL)
 381                           {
 382                             p->type = X (OP_PCREL, size);
 383                             p->literal = abs + addr + 2;
 384                             if (x & L_16)
 385                               p->literal += 2;
 386                           }
 387                         else if (x & ABSJMP)
 388                           {
 389                             p->type = X (OP_IMM, SP);
 390                             p->literal = abs;
 391                           }
 392                         else if (x & DISP)
 393                           {
 394                             p->type = X (OP_DISP, size);
 395                             p->literal = abs;
 396                             p->reg = rdisp & 0x7;
 397                           }
 398                         else if (x & CCR)
 399                           {
 400                             p->type = OP_CCR;
 401                           }
 402                         else
 403                           printf ("Hmmmm %x", x);
 404
 405                         args++;
 406                       }
 407                   }
 408
 409                   /*
 410                      * But a jmp or a jsr gets
 411                      * automagically lvalued, since we
 412                      * branch to their address not their
 413                      * contents
 414                    */
 415                   if (q->how == O (O_JSR, SB)
 416                       || q->how == O (O_JMP, SB))
 417                     {
 418                       dst->src.type = lvalue (dst->src.type, dst->src.reg);
 419                     }
 420
 421                   if (dst->dst.type == -1)
 422                     dst->dst = dst->src;
 423
 424                   dst->opcode = q->how;
 425                   dst->cycles = q->time;
 426
 427                   /* And a jsr to 0xc4 is turned into a magic trap */
 428
 429                   if (dst->opcode == O (O_JSR, SB))
 430                     {
 431                       if (dst->src.literal == 0xc4)
 432                         {
 433                           dst->opcode = O (O_SYSCALL, SB);
 434                         }
 435                     }
 436
 437                   dst->next_pc = addr + len / 2;
 438                   return;
 439                 }
 440               else
 441                 {
 442                   printf ("Dont understand %x \n", looking_for);
 443                 }
 444             }
 445
 446           len++;
 447           nib++;
 448         }
 449
 450     fail:
 451       q++;
 452     }
 453
 454   dst->opcode = O (O_ILL, SB);
 455 }
 456
 457
 458 static void
 459 compile (pc)
 460 {
 461   int idx;
 462
 463   /* find the next cache entry to use */
 464
 465   idx = cpu.cache_top + 1;
 466   cpu.compiles++;
 467   if (idx >= cpu.csize)
 468     {
 469       idx = 1;
 470     }
 471   cpu.cache_top = idx;
 472
 473   /* Throw away its old meaning */
 474   cpu.cache_idx[cpu.cache[idx].oldpc] = 0;
 475
 476   /* set to new address */
 477   cpu.cache[idx].oldpc = pc;
 478
 479   /* fill in instruction info */
 480   decode (pc, cpu.memory + pc, cpu.cache + idx);
 481
 482   /* point to new cache entry */
 483   cpu.cache_idx[pc] = idx;
 484 }
 485
 486
 487 static unsigned char *breg[18];
 488 static unsigned short *wreg[18];
 489 static unsigned int *lreg[18];
 490
 491 #define GET_B_REG(x) *(breg[x])
 492 #define SET_B_REG(x,y) (*(breg[x])) = (y)
 493 #define GET_W_REG(x) *(wreg[x])
 494 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
 495
 496 #define GET_L_REG(x) *(lreg[x])
 497 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
 498
 499 #define GET_MEMORY_L(x) \
 500   (x < memory_size \
 501    ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \
 502       | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \
 503    : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \
 504       | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff]))
 505
 506 #define GET_MEMORY_W(x) \
 507   (x < memory_size \
 508    ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \
 509    : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0)))
 510
 511
 512 #define GET_MEMORY_B(x) \
 513   (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff]))
 514
 515 #define SET_MEMORY_L(x,y)  \
 516 {  register unsigned char *_p; register int __y = y; \
 517    _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
 518    _p[0] = (__y)>>24; _p[1] = (__y)>>16; \
 519    _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
 520
 521 #define SET_MEMORY_W(x,y) \
 522 {  register unsigned char *_p; register int __y = y; \
 523    _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
 524    _p[0] = (__y)>>8; _p[1] =(__y);}
 525
 526 #define SET_MEMORY_B(x,y) \
 527   (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y))
 528
 529 int
 530 fetch (arg, n)
 531      ea_type *arg;
 532 {
 533   int rn = arg->reg;
 534   int abs = arg->literal;
 535   int r;
 536   int t;
 537
 538   switch (arg->type)
 539     {
 540     case X (OP_REG, SB):
 541       return GET_B_REG (rn);
 542     case X (OP_REG, SW):
 543       return GET_W_REG (rn);
 544     case X (OP_REG, SL):
 545       return GET_L_REG (rn);
 546     case X (OP_IMM, SB):
 547     case X (OP_IMM, SW):
 548     case X (OP_IMM, SL):
 549       return abs;
 550     case X (OP_DEC, SB):
 551       abort ();
 552
 553     case X (OP_INC, SB):
 554       t = GET_L_REG (rn);
 555       t &= cpu.mask;
 556       r = GET_MEMORY_B (t);
 557       t++;
 558       t = t & cpu.mask;
 559       SET_L_REG (rn, t);
 560       return r;
 561       break;
 562     case X (OP_INC, SW):
 563       t = GET_L_REG (rn);
 564       t &= cpu.mask;
 565       r = GET_MEMORY_W (t);
 566       t += 2;
 567       t = t & cpu.mask;
 568       SET_L_REG (rn, t);
 569       return r;
 570     case X (OP_INC, SL):
 571       t = GET_L_REG (rn);
 572       t &= cpu.mask;
 573       r = GET_MEMORY_L (t);
 574
 575       t += 4;
 576       t = t & cpu.mask;
 577       SET_L_REG (rn, t);
 578       return r;
 579
 580     case X (OP_DISP, SB):
 581       t = GET_L_REG (rn) + abs;
 582       t &= cpu.mask;
 583       return GET_MEMORY_B (t);
 584
 585     case X (OP_DISP, SW):
 586       t = GET_L_REG (rn) + abs;
 587       t &= cpu.mask;
 588       return GET_MEMORY_W (t);
 589
 590     case X (OP_DISP, SL):
 591       t = GET_L_REG (rn) + abs;
 592       t &= cpu.mask;
 593       return GET_MEMORY_L (t);
 594
 595     case X (OP_MEM, SL):
 596       t = GET_MEMORY_L (abs);
 597       t &= cpu.mask;
 598       return t;
 599
 600     case X (OP_MEM, SW):
 601       t = GET_MEMORY_W (abs);
 602       t &= cpu.mask;
 603       return t;
 604
 605     default:
 606       abort ();
 607
 608     }
 609 }
 610
 611
 612 static
 613 void
 614 store (arg, n)
 615      ea_type *arg;
 616      int n;
 617 {
 618   int rn = arg->reg;
 619   int abs = arg->literal;
 620   int t;
 621
 622   switch (arg->type)
 623     {
 624     case X (OP_REG, SB):
 625       SET_B_REG (rn, n);
 626       break;
 627     case X (OP_REG, SW):
 628       SET_W_REG (rn, n);
 629       break;
 630     case X (OP_REG, SL):
 631       SET_L_REG (rn, n);
 632       break;
 633
 634     case X (OP_DEC, SB):
 635       t = GET_L_REG (rn) - 1;
 636       t &= cpu.mask;
 637       SET_L_REG (rn, t);
 638       SET_MEMORY_B (t, n);
 639
 640       break;
 641     case X (OP_DEC, SW):
 642       t = (GET_L_REG (rn) - 2) & cpu.mask;
 643       SET_L_REG (rn, t);
 644       SET_MEMORY_W (t, n);
 645       break;
 646
 647     case X (OP_DEC, SL):
 648       t = (GET_L_REG (rn) - 4) & cpu.mask;
 649       SET_L_REG (rn, t);
 650       SET_MEMORY_L (t, n);
 651       break;
 652
 653     case X (OP_DISP, SB):
 654       t = GET_L_REG (rn) + abs;
 655       t &= cpu.mask;
 656       SET_MEMORY_B (t, n);
 657       break;
 658
 659     case X (OP_DISP, SW):
 660       t = GET_L_REG (rn) + abs;
 661       t &= cpu.mask;
 662       SET_MEMORY_W (t, n);
 663       break;
 664
 665     case X (OP_DISP, SL):
 666       t = GET_L_REG (rn) + abs;
 667       t &= cpu.mask;
 668       SET_MEMORY_L (t, n);
 669       break;
 670     default:
 671       abort ();
 672     }
 673 }
 674
 675
 676 static union
 677 {
 678   short int i;
 679   struct
 680     {
 681       char low;
 682       char high;
 683     }
 684   u;
 685 }
 686
 687 littleendian;
 688
 689 static
 690 void
 691 init_pointers ()
 692 {
 693   static int init;
 694
 695   if (!init)
 696     {
 697       int i;
 698
 699       init = 1;
 700       littleendian.i = 1;
 701
 702       if (h8300hmode)
 703         memory_size = H8300H_MSIZE;
 704       else
 705         memory_size = H8300_MSIZE;
 706       cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
 707       cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
 708       cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
 709
 710       /* `msize' must be a power of two */
 711       if ((memory_size & (memory_size - 1)) != 0)
 712         abort ();
 713       cpu.mask = memory_size - 1;
 714
 715       for (i = 0; i < 9; i++)
 716         {
 717           cpu.regs[i] = 0;
 718         }
 719
 720       for (i = 0; i < 8; i++)
 721         {
 722           unsigned char *p = (unsigned char *) (cpu.regs + i);
 723           unsigned char *e = (unsigned char *) (cpu.regs + i + 1);
 724           unsigned short *q = (unsigned short *) (cpu.regs + i);
 725           unsigned short *u = (unsigned short *) (cpu.regs + i + 1);
 726           cpu.regs[i] = 0x00112233;
 727           while (p < e)
 728             {
 729               if (*p == 0x22)
 730                 {
 731                   breg[i] = p;
 732                 }
 733               if (*p == 0x33)
 734                 {
 735                   breg[i + 8] = p;
 736                 }
 737               p++;
 738             }
 739           while (q < u)
 740             {
 741               if (*q == 0x2233)
 742                 {
 743                   wreg[i] = q;
 744                 }
 745               if (*q == 0x0011)
 746                 {
 747                   wreg[i + 8] = q;
 748                 }
 749               q++;
 750             }
 751           cpu.regs[i] = 0;
 752           lreg[i] = &cpu.regs[i];
 753         }
 754
 755       lreg[8] = &cpu.regs[8];
 756
 757       /* initialize the seg registers */
 758       if (!cpu.cache)
 759         sim_csize (CSIZE);
 760     }
 761 }
 762
 763 static void
 764 control_c (sig, code, scp, addr)
 765      int sig;
 766      int code;
 767      char *scp;
 768      char *addr;
 769 {
 770   cpu.exception = SIGINT;
 771 }
 772
 773 #define C (c != 0)
 774 #define Z (nz == 0)
 775 #define V (v != 0)
 776 #define N (n != 0)
 777
 778 static int
 779 mop (code, bsize, sign)
 780      decoded_inst *code;
 781      int bsize;
 782      int sign;
 783 {
 784   int multiplier;
 785   int multiplicand;
 786   int result;
 787   int n, nz;
 788
 789   if (sign)
 790     {
 791       multiplicand =
 792         bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) :
 793         SEXTSHORT (GET_W_REG (code->dst.reg));
 794       multiplier =
 795         bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) :
 796         SEXTSHORT (GET_W_REG (code->src.reg));
 797     }
 798   else
 799     {
 800       multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) :
 801         UEXTSHORT (GET_W_REG (code->dst.reg));
 802       multiplier =
 803         bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) :
 804         UEXTSHORT (GET_W_REG (code->src.reg));
 805
 806     }
 807   result = multiplier * multiplicand;
 808
 809   if (sign)
 810     {
 811       n = result & (bsize ? 0x8000 : 0x80000000);
 812       nz = result & (bsize ? 0xffff : 0xffffffff);
 813     }
 814   if (bsize)
 815     {
 816       SET_W_REG (code->dst.reg, result);
 817     }
 818   else
 819     {
 820       SET_L_REG (code->dst.reg, result);
 821     }
 822 /*  return ((n==1) << 1) | (nz==1); */
 823
 824 }
 825
 826 #define OSHIFTS(name, how) \
 827 case O(name, SB):                               \
 828 {                                               \
 829   int t;                                        \
 830   int hm = 0x80;                                \
 831   rd = GET_B_REG (code->src.reg);               \
 832   how;                                          \
 833   goto shift8;                                  \
 834 }                                               \
 835 case O(name, SW):                               \
 836 {                                               \
 837   int t;                                        \
 838   int hm = 0x8000;                              \
 839   rd = GET_W_REG (code->src.reg);               \
 840   how;                                          \
 841   goto shift16;                                 \
 842 }                                               \
 843 case O(name, SL):                               \
 844 {                                               \
 845   int t;                                        \
 846   int hm = 0x80000000;                          \
 847   rd = GET_L_REG (code->src.reg);               \
 848   how;                                          \
 849   goto shift32;                                 \
 850 }
 851
 852 #define OBITOP(name,f, s, op)                   \
 853 case  O(name, SB):                              \
 854 {                                               \
 855   int m;                                        \
 856   int b;                                        \
 857   if (f) ea = fetch (&code->dst);               \
 858   m=1<< fetch(&code->src);                      \
 859   op;                                           \
 860   if(s) store (&code->dst,ea); goto next;       \
 861 }
 862
 863 void
 864 sim_resume (step, siggnal)
 865 {
 866   static int init1;
 867   int cycles = 0;
 868   int insts = 0;
 869   int tick_start = get_now ();
 870   void (*prev) ();
 871   int poll_count = 0;
 872   int res;
 873   int tmp;
 874   int rd;
 875   int ea;
 876   int bit;
 877   int pc;
 878   int c, nz, v, n;
 879   int oldmask;
 880   init_pointers ();
 881
 882   prev = signal (SIGINT, control_c);
 883
 884   if (step)
 885     {
 886       cpu.exception = SIGTRAP;
 887     }
 888   else
 889     {
 890       cpu.exception = 0;
 891     }
 892
 893   pc = cpu.pc;
 894
 895   /* The PC should never be odd.  */
 896   if (pc & 0x1)
 897     abort ();
 898
 899   GETSR ();
 900   oldmask = cpu.mask;
 901   if (!h8300hmode)
 902     cpu.mask = 0xffff;
 903   do
 904     {
 905       int cidx;
 906       decoded_inst *code;
 907
 908     top:
 909       cidx = cpu.cache_idx[pc];
 910       code = cpu.cache + cidx;
 911
 912
 913 #define ALUOP(STORE, NAME, HOW) \
 914     case O(NAME,SB):  HOW; if(STORE)goto alu8;else goto just_flags_alu8;  \
 915     case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \
 916     case O(NAME,SL):  HOW; if(STORE)goto alu32;else goto just_flags_alu32;
 917
 918
 919 #define LOGOP(NAME, HOW) \
 920     case O(NAME,SB): HOW; goto log8;\
 921     case O(NAME, SW): HOW; goto log16;\
 922     case O(NAME,SL): HOW; goto log32;
 923
 924
 925
 926 #if ADEBUG
 927       if (debug)
 928         {
 929           printf ("%x %d %s\n", pc, code->opcode,
 930                   code->op ? code->op->name : "**");
 931         }
 932       cpu.stats[code->opcode]++;
 933
 934 #endif
 935
 936       cycles += code->cycles;
 937       insts++;
 938       switch (code->opcode)
 939         {
 940         case 0:
 941           /*
 942            * This opcode is a fake for when we get to an
 943            * instruction which hasnt been compiled
 944            */
 945           compile (pc);
 946           goto top;
 947           break;
 948
 949
 950         case O (O_SUBX, SB):
 951           rd = fetch (&code->dst);
 952           ea = fetch (&code->src);
 953           ea = -(ea + C);
 954           res = rd + ea;
 955           goto alu8;
 956
 957         case O (O_ADDX, SB):
 958           rd = fetch (&code->dst);
 959           ea = fetch (&code->src);
 960           ea = C + ea;
 961           res = rd + ea;
 962           goto alu8;
 963
 964 #define EA    ea = fetch(&code->src);
 965 #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst);
 966
 967           ALUOP (1, O_SUB, RD_EA;
 968                  ea = -ea;
 969                  res = rd + ea);
 970           ALUOP (1, O_NEG, EA;
 971                  ea = -ea;
 972                  rd = 0;
 973                  res = rd + ea);
 974
 975         case O (O_ADD, SB):
 976           rd = GET_B_REG (code->dst.reg);
 977           ea = fetch (&code->src);
 978           res = rd + ea;
 979           goto alu8;
 980         case O (O_ADD, SW):
 981           rd = GET_W_REG (code->dst.reg);
 982           ea = fetch (&code->src);
 983           res = rd + ea;
 984           goto alu16;
 985         case O (O_ADD, SL):
 986           rd = GET_L_REG (code->dst.reg);
 987           ea = fetch (&code->src);
 988           res = rd + ea;
 989           goto alu32;
 990
 991
 992           LOGOP (O_AND, RD_EA;
 993                  res = rd & ea);
 994
 995           LOGOP (O_OR, RD_EA;
 996                  res = rd | ea);
 997
 998           LOGOP (O_XOR, RD_EA;
 999                  res = rd ^ ea);
1000
1001
1002         case O (O_MOV_TO_MEM, SB):
1003           res = GET_B_REG (code->src.reg);
1004           goto log8;
1005         case O (O_MOV_TO_MEM, SW):
1006           res = GET_W_REG (code->src.reg);
1007           goto log16;
1008         case O (O_MOV_TO_MEM, SL):
1009           res = GET_L_REG (code->src.reg);
1010           goto log32;
1011
1012
1013         case O (O_MOV_TO_REG, SB):
1014           res = fetch (&code->src);
1015           SET_B_REG (code->dst.reg, res);
1016           goto just_flags_log8;
1017         case O (O_MOV_TO_REG, SW):
1018           res = fetch (&code->src);
1019           SET_W_REG (code->dst.reg, res);
1020           goto just_flags_log16;
1021         case O (O_MOV_TO_REG, SL):
1022           res = fetch (&code->src);
1023           SET_L_REG (code->dst.reg, res);
1024           goto just_flags_log32;
1025
1026
1027         case O (O_ADDS, SL):
1028           SET_L_REG (code->dst.reg,
1029                      GET_L_REG (code->dst.reg)
1030                      + code->src.literal);
1031
1032           goto next;
1033
1034         case O (O_SUBS, SL):
1035           SET_L_REG (code->dst.reg,
1036                      GET_L_REG (code->dst.reg)
1037                      - code->src.literal);
1038           goto next;
1039
1040         case O (O_CMP, SB):
1041           rd = fetch (&code->dst);
1042           ea = fetch (&code->src);
1043           ea = -ea;
1044           res = rd + ea;
1045           goto just_flags_alu8;
1046
1047         case O (O_CMP, SW):
1048           rd = fetch (&code->dst);
1049           ea = fetch (&code->src);
1050           ea = -ea;
1051           res = rd + ea;
1052           goto just_flags_alu16;
1053
1054         case O (O_CMP, SL):
1055           rd = fetch (&code->dst);
1056           ea = fetch (&code->src);
1057           ea = -ea;
1058           res = rd + ea;
1059           goto just_flags_alu32;
1060
1061
1062         case O (O_DEC, SB):
1063           rd = GET_B_REG (code->src.reg);
1064           ea = -1;
1065           res = rd + ea;
1066           SET_B_REG (code->src.reg, res);
1067           goto just_flags_inc8;
1068
1069         case O (O_DEC, SW):
1070           rd = GET_W_REG (code->dst.reg);
1071           ea = -code->src.literal;
1072           res = rd + ea;
1073           SET_W_REG (code->dst.reg, res);
1074           goto just_flags_inc16;
1075
1076         case O (O_DEC, SL):
1077           rd = GET_L_REG (code->dst.reg);
1078           ea = -code->src.literal;
1079           res = rd + ea;
1080           SET_L_REG (code->dst.reg, res);
1081           goto just_flags_inc32;
1082
1083
1084         case O (O_INC, SB):
1085           rd = GET_B_REG (code->src.reg);
1086           ea = 1;
1087           res = rd + ea;
1088           SET_B_REG (code->src.reg, res);
1089           goto just_flags_inc8;
1090
1091         case O (O_INC, SW):
1092           rd = GET_W_REG (code->dst.reg);
1093           ea = code->src.literal;
1094           res = rd + ea;
1095           SET_W_REG (code->dst.reg, res);
1096           goto just_flags_inc16;
1097
1098         case O (O_INC, SL):
1099           rd = GET_L_REG (code->dst.reg);
1100           ea = code->src.literal;
1101           res = rd + ea;
1102           SET_L_REG (code->dst.reg, res);
1103           goto just_flags_inc32;
1104
1105
1106 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1107
1108         case O (O_ANDC, SB):
1109           GET_CCR (rd);
1110           ea = code->src.literal;
1111           res = rd & ea;
1112           goto setc;
1113
1114         case O (O_ORC, SB):
1115           GET_CCR (rd);
1116           ea = code->src.literal;
1117           res = rd | ea;
1118           goto setc;
1119
1120         case O (O_XORC, SB):
1121           GET_CCR (rd);
1122           ea = code->src.literal;
1123           res = rd ^ ea;
1124           goto setc;
1125
1126
1127         case O (O_BRA, SB):
1128           if (1)
1129             goto condtrue;
1130           goto next;
1131
1132         case O (O_BRN, SB):
1133           if (0)
1134             goto condtrue;
1135           goto next;
1136
1137         case O (O_BHI, SB):
1138           if ((C || Z) == 0)
1139             goto condtrue;
1140           goto next;
1141
1142
1143         case O (O_BLS, SB):
1144           if ((C || Z))
1145             goto condtrue;
1146           goto next;
1147
1148         case O (O_BCS, SB):
1149           if ((C == 1))
1150             goto condtrue;
1151           goto next;
1152
1153         case O (O_BCC, SB):
1154           if ((C == 0))
1155             goto condtrue;
1156           goto next;
1157
1158         case O (O_BEQ, SB):
1159           if (Z)
1160             goto condtrue;
1161           goto next;
1162         case O (O_BGT, SB):
1163           if (((Z || (N ^ V)) == 0))
1164             goto condtrue;
1165           goto next;
1166
1167
1168         case O (O_BLE, SB):
1169           if (((Z || (N ^ V)) == 1))
1170             goto condtrue;
1171           goto next;
1172
1173         case O (O_BGE, SB):
1174           if ((N ^ V) == 0)
1175             goto condtrue;
1176           goto next;
1177         case O (O_BLT, SB):
1178           if ((N ^ V))
1179             goto condtrue;
1180           goto next;
1181         case O (O_BMI, SB):
1182           if ((N))
1183             goto condtrue;
1184           goto next;
1185         case O (O_BNE, SB):
1186           if ((Z == 0))
1187             goto condtrue;
1188           goto next;
1189
1190         case O (O_BPL, SB):
1191           if (N == 0)
1192             goto condtrue;
1193           goto next;
1194         case O (O_BVC, SB):
1195           if ((V == 0))
1196             goto condtrue;
1197           goto next;
1198         case O (O_BVS, SB):
1199           if ((V == 1))
1200             goto condtrue;
1201           goto next;
1202
1203         case O (O_SYSCALL, SB):
1204           printf ("%c", cpu.regs[2]);
1205           goto next;
1206
1207           OSHIFTS (O_NOT, rd = ~rd; v = 0;);
1208           OSHIFTS (O_SHLL, c = rd & hm; v = 0;
1209                    rd <<= 1);
1210           OSHIFTS (O_SHLR, c = rd & 1; v = 0;
1211                    rd = (unsigned int) rd >> 1);
1212           OSHIFTS (O_SHAL, c = rd & hm;
1213                    v = (rd & hm) != ((rd & (hm >> 1)) << 1);
1214                    rd <<= 1);
1215           OSHIFTS (O_SHAR, t = rd & hm;
1216                    c = rd & 1;
1217                    v = 0;
1218                    rd >>= 1;
1219                    rd |= t;
1220                    );
1221           OSHIFTS (O_ROTL, c = rd & hm;
1222                    v = 0;
1223                    rd <<= 1;
1224                    rd |= C);
1225           OSHIFTS (O_ROTR, c = rd & 1;
1226                    v = 0;
1227                    rd = (unsigned int) rd >> 1;
1228                    if (c) rd |= hm;);
1229           OSHIFTS (O_ROTXL, t = rd & hm;
1230                    rd <<= 1;
1231                    rd |= C;
1232                    c = t;
1233                    v = 0;
1234                    );
1235           OSHIFTS (O_ROTXR, t = rd & 1;
1236                    rd = (unsigned int) rd >> 1;
1237                    if (C) rd |= hm; c = t;
1238                    v = 0;);
1239
1240         case O (O_JMP, SB):
1241           {
1242             pc = fetch (&code->src);
1243             goto end;
1244
1245           }
1246
1247         case O (O_JSR, SB):
1248           {
1249             int tmp;
1250             pc = fetch (&code->src);
1251           call:
1252             tmp = cpu.regs[7];
1253
1254             if (h8300hmode)
1255               {
1256                 tmp -= 4;
1257                 SET_MEMORY_L (tmp, code->next_pc);
1258               }
1259             else
1260               {
1261                 tmp -= 2;
1262                 SET_MEMORY_W (tmp, code->next_pc);
1263               }
1264             cpu.regs[7] = tmp;
1265
1266             goto end;
1267           }
1268         case O (O_BSR, SB):
1269           pc = code->src.literal;
1270           goto call;
1271
1272         case O (O_RTS, SB):
1273           {
1274             int tmp;
1275
1276             tmp = cpu.regs[7];
1277
1278             if (h8300hmode)
1279               {
1280                 pc = GET_MEMORY_L (tmp);
1281                 tmp += 4;
1282               }
1283             else
1284               {
1285                 pc = GET_MEMORY_W (tmp);
1286                 tmp += 2;
1287               }
1288
1289             cpu.regs[7] = tmp;
1290             goto end;
1291           }
1292
1293         case O (O_ILL, SB):
1294           cpu.exception = SIGILL;
1295           goto end;
1296         case O (O_SLEEP, SB):
1297           /* The format of r0 is defined by devo/include/wait.h.
1298              cpu.exception handling needs some cleanup: we need to make the
1299              the handling of normal exits vs signals, etc. more sensible.  */
1300           if (! WIFEXITED (cpu.regs[0]) && WIFSIGNALED (cpu.regs[0]))
1301             cpu.exception = SIGILL;
1302           else
1303             cpu.exception = SIGTRAP;
1304           goto end;
1305         case O (O_BPT, SB):
1306           cpu.exception = SIGTRAP;
1307           goto end;
1308
1309           OBITOP (O_BNOT, 1, 1, ea ^= m);
1310           OBITOP (O_BTST, 1, 0, nz = ea & m);
1311           OBITOP (O_BCLR, 1, 1, ea &= ~m);
1312           OBITOP (O_BSET, 1, 1, ea |= m);
1313           OBITOP (O_BLD, 1, 0, c = ea & m);
1314           OBITOP (O_BILD, 1, 0, c = !(ea & m));
1315           OBITOP (O_BST, 1, 1, ea &= ~m;
1316                   if (C) ea |= m);
1317           OBITOP (O_BIST, 1, 1, ea &= ~m;
1318                   if (!C) ea |= m);
1319           OBITOP (O_BAND, 1, 0, c = (ea & m) && C);
1320           OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C);
1321           OBITOP (O_BOR, 1, 0, c = (ea & m) || C);
1322           OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C);
1323           OBITOP (O_BXOR, 1, 0, c = (ea & m) != C);
1324           OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C);
1325
1326
1327 #define MOP(bsize, signed) mop(code, bsize,signed); goto next;
1328
1329         case O (O_MULS, SB):
1330           MOP (1, 1);
1331           break;
1332         case O (O_MULS, SW):
1333           MOP (0, 1);
1334           break;
1335         case O (O_MULU, SB):
1336           MOP (1, 0);
1337           break;
1338         case O (O_MULU, SW):
1339           MOP (0, 0);
1340           break;
1341
1342
1343         case O (O_DIVU, SB):
1344           {
1345             rd = GET_W_REG (code->dst.reg);
1346             ea = GET_B_REG (code->src.reg);
1347             if (ea)
1348               {
1349                 tmp = (unsigned)rd % ea;
1350                 rd = (unsigned)rd / ea;
1351               }
1352             SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1353             n = ea & 0x80;
1354             nz = ea & 0xff;
1355
1356             goto next;
1357           }
1358         case O (O_DIVU, SW):
1359           {
1360             rd = GET_L_REG (code->dst.reg);
1361             ea = GET_W_REG (code->src.reg);
1362             n = ea & 0x8000;
1363             nz = ea & 0xffff;
1364             if (ea)
1365               {
1366                 tmp = (unsigned)rd % ea;
1367                 rd = (unsigned)rd / ea;
1368               }
1369             SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1370             goto next;
1371           }
1372
1373         case O (O_DIVS, SB):
1374           {
1375
1376             rd = SEXTSHORT (GET_W_REG (code->dst.reg));
1377             ea = SEXTCHAR (GET_B_REG (code->src.reg));
1378             if (ea)
1379               {
1380                 tmp = (int) rd % (int) ea;
1381                 rd = (int) rd / (int) ea;
1382                 n = rd & 0x8000;
1383                 nz = 1;
1384               }
1385             else
1386               nz = 0;
1387             SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1388             goto next;
1389           }
1390         case O (O_DIVS, SW):
1391           {
1392             rd = GET_L_REG (code->dst.reg);
1393             ea = SEXTSHORT (GET_W_REG (code->src.reg));
1394             if (ea)
1395               {
1396                 tmp = (int) rd % (int) ea;
1397                 rd = (int) rd / (int) ea;
1398                 n = rd & 0x80000000;
1399                 nz = 1;
1400               }
1401             else
1402               nz = 0;
1403             SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1404             goto next;
1405           }
1406         case O (O_EXTS, SW):
1407           rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst.  */
1408           ea = rd & 0x80 ? -256 : 0;
1409           res = rd + ea;
1410           goto log16;
1411         case O (O_EXTS, SL):
1412           rd = GET_W_REG (code->src.reg) & 0xffff;
1413           ea = rd & 0x8000 ? -65536 : 0;
1414           res = rd + ea;
1415           goto log32;
1416         case O (O_EXTU, SW):
1417           rd = GET_B_REG (code->src.reg + 8) & 0xff;
1418           ea = 0;
1419           res = rd + ea;
1420           goto log16;
1421         case O (O_EXTU, SL):
1422           rd = GET_W_REG (code->src.reg) & 0xffff;
1423           ea = 0;
1424           res = rd + ea;
1425           goto log32;
1426
1427         case O (O_NOP, SB):
1428           goto next;
1429
1430 /* start-sanitize-h8s */
1431         case O (O_STM, SL):
1432           {
1433             int nregs, firstreg, i;
1434
1435             nregs = GET_MEMORY_B (pc + 1);
1436             nregs >>= 4;
1437             nregs &= 0xf;
1438             firstreg = GET_MEMORY_B (pc + 3);
1439             firstreg &= 0xf;
1440             for (i = firstreg; i <= firstreg + nregs; i++)
1441               {
1442                 cpu.regs[7] -= 4;
1443                 SET_MEMORY_L (cpu.regs[7], cpu.regs[i]);
1444               }
1445           }
1446           goto next;
1447
1448         case O (O_LDM, SL):
1449           {
1450             int nregs, firstreg, i;
1451
1452             nregs = GET_MEMORY_B (pc + 1);
1453             nregs >>= 4;
1454             nregs &= 0xf;
1455             firstreg = GET_MEMORY_B (pc + 3);
1456             firstreg &= 0xf;
1457             for (i = firstreg; i >= firstreg - nregs; i--)
1458               {
1459                 cpu.regs[i] = GET_MEMORY_L (cpu.regs[7]);
1460                 cpu.regs[7] += 4;
1461               }
1462           }
1463           goto next;
1464
1465 /* end-sanitize-h8s */
1466         default:
1467           cpu.exception = SIGILL;
1468           goto end;
1469
1470         }
1471       abort ();
1472
1473     setc:
1474       cpu.ccr = res;
1475       GETSR ();
1476       goto next;
1477
1478     condtrue:
1479       /* When a branch works */
1480       pc = code->src.literal;
1481       goto end;
1482
1483       /* Set the cond codes from res */
1484     bitop:
1485
1486       /* Set the flags after an 8 bit inc/dec operation */
1487     just_flags_inc8:
1488       n = res & 0x80;
1489       nz = res & 0xff;
1490       v = (rd & 0x7f) == 0x7f;
1491       goto next;
1492
1493
1494       /* Set the flags after an 16 bit inc/dec operation */
1495     just_flags_inc16:
1496       n = res & 0x8000;
1497       nz = res & 0xffff;
1498       v = (rd & 0x7fff) == 0x7fff;
1499       goto next;
1500
1501
1502       /* Set the flags after an 32 bit inc/dec operation */
1503     just_flags_inc32:
1504       n = res & 0x80000000;
1505       nz = res & 0xffffffff;
1506       v = (rd & 0x7fffffff) == 0x7fffffff;
1507       goto next;
1508
1509
1510     shift8:
1511       /* Set flags after an 8 bit shift op, carry,overflow set in insn */
1512       n = (rd & 0x80);
1513       nz = rd & 0xff;
1514       SET_B_REG (code->src.reg, rd);
1515       goto next;
1516
1517     shift16:
1518       /* Set flags after an 16 bit shift op, carry,overflow set in insn */
1519       n = (rd & 0x8000);
1520       nz = rd & 0xffff;
1521       SET_W_REG (code->src.reg, rd);
1522       goto next;
1523
1524     shift32:
1525       /* Set flags after an 32 bit shift op, carry,overflow set in insn */
1526       n = (rd & 0x80000000);
1527       nz = rd & 0xffffffff;
1528       SET_L_REG (code->src.reg, rd);
1529       goto next;
1530
1531     log32:
1532       store (&code->dst, res);
1533     just_flags_log32:
1534       /* flags after a 32bit logical operation */
1535       n = res & 0x80000000;
1536       nz = res & 0xffffffff;
1537       v = 0;
1538       goto next;
1539
1540     log16:
1541       store (&code->dst, res);
1542     just_flags_log16:
1543       /* flags after a 16bit logical operation */
1544       n = res & 0x8000;
1545       nz = res & 0xffff;
1546       v = 0;
1547       goto next;
1548
1549
1550     log8:
1551       store (&code->dst, res);
1552     just_flags_log8:
1553       n = res & 0x80;
1554       nz = res & 0xff;
1555       v = 0;
1556       goto next;
1557
1558     alu8:
1559       SET_B_REG (code->dst.reg, res);
1560     just_flags_alu8:
1561       n = res & 0x80;
1562       nz = res & 0xff;
1563       c = (res & 0x100);
1564       switch (code->opcode / 4)
1565         {
1566         case O_ADD:
1567           v = ((rd & 0x80) == (ea & 0x80)
1568                && (rd & 0x80) != (res & 0x80));
1569           break;
1570         case O_SUB:
1571         case O_CMP:
1572           v = ((rd & 0x80) != (-ea & 0x80)
1573                && (rd & 0x80) != (res & 0x80));
1574           break;
1575         case O_NEG:
1576           v = (rd == 0x80);
1577           break;
1578         }
1579       goto next;
1580
1581     alu16:
1582       SET_W_REG (code->dst.reg, res);
1583     just_flags_alu16:
1584       n = res & 0x8000;
1585       nz = res & 0xffff;
1586       c = (res & 0x10000);
1587       switch (code->opcode / 4)
1588         {
1589         case O_ADD:
1590           v = ((rd & 0x8000) == (ea & 0x8000)
1591                && (rd & 0x8000) != (res & 0x8000));
1592           break;
1593         case O_SUB:
1594         case O_CMP:
1595           v = ((rd & 0x8000) != (-ea & 0x8000)
1596                && (rd & 0x8000) != (res & 0x8000));
1597           break;
1598         case O_NEG:
1599           v = (rd == 0x8000);
1600           break;
1601         }
1602       goto next;
1603
1604     alu32:
1605       SET_L_REG (code->dst.reg, res);
1606     just_flags_alu32:
1607       n = res & 0x80000000;
1608       nz = res & 0xffffffff;
1609       switch (code->opcode / 4)
1610         {
1611         case O_ADD:
1612           v = ((rd & 0x80000000) == (ea & 0x80000000)
1613                && (rd & 0x80000000) != (res & 0x80000000));
1614           c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea);
1615           break;
1616         case O_SUB:
1617         case O_CMP:
1618           v = ((rd & 0x80000000) != (-ea & 0x80000000)
1619                && (rd & 0x80000000) != (res & 0x80000000));
1620           c = (unsigned) rd < (unsigned) -ea;
1621           break;
1622         case O_NEG:
1623           v = (rd == 0x80000000);
1624           c = res != 0;
1625           break;
1626         }
1627       goto next;
1628
1629     next:;
1630       pc = code->next_pc;
1631
1632     end:
1633       ;
1634       /*      if (cpu.regs[8] ) abort(); */
1635
1636 #if defined (WIN32)
1637       /* Poll after every 100th insn, */
1638       if (poll_count++ > 100)
1639         {
1640           poll_count = 0;
1641           if (win32pollquit())
1642             {
1643               control_c();
1644             }
1645         }
1646 #endif
1647 #if defined(__GO32__)
1648       /* Poll after every 100th insn, */
1649       if (poll_count++ > 100)
1650         {
1651           poll_count = 0;
1652           if (kbhit ())
1653             {
1654               int c = getkey ();
1655               control_c ();
1656             }
1657         }
1658 #endif
1659
1660     }
1661   while (!cpu.exception);
1662   cpu.ticks += get_now () - tick_start;
1663   cpu.cycles += cycles;
1664   cpu.insts += insts;
1665
1666   cpu.pc = pc;
1667   BUILDSR ();
1668   cpu.mask = oldmask;
1669   signal (SIGINT, prev);
1670 }
1671
1672
1673 int
1674 sim_write (addr, buffer, size)
1675      SIM_ADDR addr;
1676      unsigned char *buffer;
1677      int size;
1678 {
1679   int i;
1680
1681   init_pointers ();
1682   if (addr < 0)
1683     return 0;
1684   for (i = 0; i < size; i++)
1685     {
1686       if (addr < memory_size)
1687         {
1688           cpu.memory[addr + i] = buffer[i];
1689           cpu.cache_idx[addr + i] = 0;
1690         }
1691       else
1692         cpu.eightbit[(addr + i) & 0xff] = buffer[i];
1693     }
1694   return size;
1695 }
1696
1697 int
1698 sim_read (addr, buffer, size)
1699      SIM_ADDR addr;
1700      unsigned char *buffer;
1701      int size;
1702 {
1703   init_pointers ();
1704   if (addr < 0)
1705     return 0;
1706   if (addr < memory_size)
1707     memcpy (buffer, cpu.memory + addr, size);
1708   else
1709     memcpy (buffer, cpu.eightbit + (addr & 0xff), size);
1710   return size;
1711 }
1712
1713
1714 #define R0_REGNUM       0
1715 #define R1_REGNUM       1
1716 #define R2_REGNUM       2
1717 #define R3_REGNUM       3
1718 #define R4_REGNUM       4
1719 #define R5_REGNUM       5
1720 #define R6_REGNUM       6
1721 #define R7_REGNUM       7
1722
1723 #define SP_REGNUM       R7_REGNUM       /* Contains address of top of stack */
1724 #define FP_REGNUM       R6_REGNUM       /* Contains address of executing
1725                                            * stack frame */
1726
1727 #define CCR_REGNUM      8       /* Contains processor status */
1728 #define PC_REGNUM       9       /* Contains program counter */
1729
1730 #define CYCLE_REGNUM    10
1731 #define INST_REGNUM     11
1732 #define TICK_REGNUM     12
1733
1734
1735 void
1736 sim_store_register (rn, value)
1737      int rn;
1738      unsigned char *value;
1739 {
1740   int longval;
1741   int shortval;
1742   int intval;
1743   longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3];
1744   shortval = (value[0] << 8) | (value[1]);
1745   intval = h8300hmode ? longval : shortval;
1746
1747   init_pointers ();
1748   switch (rn)
1749     {
1750     case PC_REGNUM:
1751       cpu.pc = intval;
1752       break;
1753     default:
1754       abort ();
1755     case R0_REGNUM:
1756     case R1_REGNUM:
1757     case R2_REGNUM:
1758     case R3_REGNUM:
1759     case R4_REGNUM:
1760     case R5_REGNUM:
1761     case R6_REGNUM:
1762     case R7_REGNUM:
1763       cpu.regs[rn] = intval;
1764       break;
1765     case CCR_REGNUM:
1766       cpu.ccr = intval;
1767       break;
1768     case CYCLE_REGNUM:
1769       cpu.cycles = longval;
1770       break;
1771
1772     case INST_REGNUM:
1773       cpu.insts = longval;
1774       break;
1775
1776     case TICK_REGNUM:
1777       cpu.ticks = longval;
1778       break;
1779     }
1780 }
1781
1782 void
1783 sim_fetch_register (rn, buf)
1784      int rn;
1785      unsigned char *buf;
1786 {
1787   int v;
1788   int longreg = 0;
1789
1790   init_pointers ();
1791
1792   switch (rn)
1793     {
1794     default:
1795       abort ();
1796     case 8:
1797       v = cpu.ccr;
1798       break;
1799     case 9:
1800       v = cpu.pc;
1801       break;
1802     case R0_REGNUM:
1803     case R1_REGNUM:
1804     case R2_REGNUM:
1805     case R3_REGNUM:
1806     case R4_REGNUM:
1807     case R5_REGNUM:
1808     case R6_REGNUM:
1809     case R7_REGNUM:
1810       v = cpu.regs[rn];
1811       break;
1812     case 10:
1813       v = cpu.cycles;
1814       longreg = 1;
1815       break;
1816     case 11:
1817       v = cpu.ticks;
1818       longreg = 1;
1819       break;
1820     case 12:
1821       v = cpu.insts;
1822       longreg = 1;
1823       break;
1824     }
1825   if (h8300hmode || longreg)
1826     {
1827       buf[0] = v >> 24;
1828       buf[1] = v >> 16;
1829       buf[2] = v >> 8;
1830       buf[3] = v >> 0;
1831     }
1832   else
1833     {
1834       buf[0] = v >> 8;
1835       buf[1] = v;
1836     }
1837 }
1838
1839 void
1840 sim_stop_reason (reason, sigrc)
1841      enum sim_stop *reason;
1842      int *sigrc;
1843 {
1844   *reason = sim_stopped;
1845   *sigrc = cpu.exception;
1846 }
1847
1848 sim_csize (n)
1849 {
1850   if (cpu.cache)
1851     free (cpu.cache);
1852   if (n < 2)
1853     n = 2;
1854   cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n);
1855   memset (cpu.cache, 0, sizeof (decoded_inst) * n);
1856   cpu.csize = n;
1857 }
1858
1859
1860 void
1861 sim_info (verbose)
1862      int verbose;
1863 {
1864   double timetaken = (double) cpu.ticks / (double) now_persec ();
1865   double virttime = cpu.cycles / 10.0e6;
1866
1867   printf_filtered ("\n\n#instructions executed  %10d\n", cpu.insts);
1868   printf_filtered ("#cycles (v approximate) %10d\n", cpu.cycles);
1869   printf_filtered ("#real time taken        %10.4f\n", timetaken);
1870   printf_filtered ("#virtual time taked     %10.4f\n", virttime);
1871   if (timetaken != 0.0)
1872     printf_filtered ("#simulation ratio       %10.4f\n", virttime / timetaken);
1873   printf_filtered ("#compiles               %10d\n", cpu.compiles);
1874   printf_filtered ("#cache size             %10d\n", cpu.csize);
1875
1876 #ifdef ADEBUG
1877   if (verbose)
1878     {
1879       int i;
1880       for (i = 0; i < O_LAST; i++)
1881         {
1882           if (cpu.stats[i])
1883             printf_filtered ("%d: %d\n", i, cpu.stats[i]);
1884         }
1885     }
1886 #endif
1887 }
1888
1889 /* Indicate whether the cpu is an h8/300 or h8/300h.
1890    FLAG is non-zero for the h8/300h.  */
1891
1892 void
1893 set_h8300h (flag)
1894      int flag;
1895 {
1896   h8300hmode = flag;
1897 }
1898
1899 void
1900 sim_kill ()
1901 {
1902   /* nothing to do */
1903 }
1904
1905 void
1906 sim_open (args)
1907      char *args;
1908 {
1909   /* nothing to do */
1910 }
1911
1912 void
1913 sim_close (quitting)
1914      int quitting;
1915 {
1916   /* nothing to do */
1917 }
1918
1919 /* Called by gdb to load a program into memory.  */
1920
1921 int
1922 sim_load (prog, from_tty)
1923      char *prog;
1924      int from_tty;
1925 {
1926   bfd *abfd;
1927
1928   /* See if the file is for the h8/300 or h8/300h.  */
1929   /* ??? This may not be the most efficient way.  The z8k simulator
1930      does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO).  */
1931   if ((abfd = bfd_openr (prog, "coff-h8300")) != 0)
1932     {
1933       if (bfd_check_format (abfd, bfd_object))
1934         {
1935           set_h8300h (abfd->arch_info->mach == bfd_mach_h8300h
1936 /* start-sanitize-h8s */
1937                       || abfd->arch_info->mach == bfd_mach_h8300s
1938 /* end-sanitize-h8s */
1939                       );
1940         }
1941       bfd_close (abfd);
1942     }
1943
1944   /* If we're using gdb attached to the simulator, then we have to
1945      reallocate memory for the simulator.
1946
1947      When gdb first starts, it calls fetch_registers (among other
1948      functions), which in turn calls init_pointers, which allocates
1949      simulator memory.
1950
1951      The problem is when we do that, we don't know whether we're
1952      debugging an h8/300 or h8/300h program.
1953
1954      This is the first point at which we can make that determination,
1955      so we just reallocate memory now; this will also allow us to handle
1956      switching between h8/300 and h8/300h programs without exiting
1957      gdb.  */
1958   if (h8300hmode)
1959     memory_size = H8300H_MSIZE;
1960   else
1961     memory_size = H8300_MSIZE;
1962
1963   if (cpu.memory)
1964     free (cpu.memory);
1965   if (cpu.cache_idx)
1966     free (cpu.cache_idx);
1967   if (cpu.eightbit)
1968     free (cpu.eightbit);
1969
1970   cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
1971   cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
1972   cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
1973
1974   /* `msize' must be a power of two */
1975   if ((memory_size & (memory_size - 1)) != 0)
1976     abort ();
1977   cpu.mask = memory_size - 1;
1978
1979   /* Return non-zero so gdb will handle it.  */
1980   return 1;
1981 }
1982
1983 void
1984 sim_create_inferior (start_address, argv, env)
1985      SIM_ADDR start_address;
1986      char **argv;
1987      char **env;
1988 {
1989   cpu.pc = start_address;
1990 }
1991
1992 void
1993 sim_do_command (cmd)
1994      char *cmd;
1995 {
1996   printf_filtered ("This simulator does not accept any commands.\n");
1997 }
1998
1999
2000
2001 void
2002 sim_set_callbacks (ptr)
2003 struct host_callback_struct *ptr;
2004 {
2005
2006 }
2007