2 * Simulator for the Renesas (formerly Hitachi) H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
24 #ifdef HAVE_SYS_PARAM_H
25 #include <sys/param.h>
30 #include "gdb/sim-h8300.h"
32 #include "sys/types.h"
33 #include "sim-options.h"
41 #define X(op, size) (op * 4 + size)
43 #define SP (h8300hmode && !h8300_normal_mode ? SL : SW)
45 #define h8_opcodes ops
47 #include "opcode/h8300.h"
49 /* CPU data object: */
52 h8_get_pc (SIM_DESC sd
)
54 return (STATE_CPU (sd
, 0)) -> pc
;
58 h8_set_pc (SIM_DESC sd
, unsigned int val
)
60 (STATE_CPU (sd
, 0)) -> pc
= val
;
64 h8_get_ccr (SIM_DESC sd
)
66 return (STATE_CPU (sd
, 0)) -> regs
[CCR_REGNUM
];
70 h8_set_ccr (SIM_DESC sd
, unsigned int val
)
72 (STATE_CPU (sd
, 0)) -> regs
[CCR_REGNUM
] = val
;
76 h8_get_exr (SIM_DESC sd
)
78 return (STATE_CPU (sd
, 0)) -> regs
[EXR_REGNUM
];
82 h8_set_exr (SIM_DESC sd
, unsigned int val
)
84 (STATE_CPU (sd
, 0)) -> regs
[EXR_REGNUM
] = val
;
88 h8_get_sbr (SIM_DESC sd
)
90 return (STATE_CPU (sd
, 0)) -> regs
[SBR_REGNUM
];
94 h8_set_sbr (SIM_DESC sd
, int val
)
96 (STATE_CPU (sd
, 0)) -> regs
[SBR_REGNUM
] = val
;
100 h8_get_vbr (SIM_DESC sd
)
102 return (STATE_CPU (sd
, 0)) -> regs
[VBR_REGNUM
];
106 h8_set_vbr (SIM_DESC sd
, int val
)
108 (STATE_CPU (sd
, 0)) -> regs
[VBR_REGNUM
] = val
;
112 h8_get_mask (SIM_DESC sd
)
114 return (STATE_CPU (sd
, 0)) -> mask
;
118 h8_set_mask (SIM_DESC sd
, int val
)
120 (STATE_CPU (sd
, 0)) -> mask
= val
;
124 h8_get_exception (SIM_DESC sd
)
126 return (STATE_CPU (sd
, 0)) -> exception
;
130 h8_set_exception (SIM_DESC sd
, int val
)
132 (STATE_CPU (sd
, 0)) -> exception
= val
;
135 static enum h8300_sim_state
136 h8_get_state (SIM_DESC sd
)
142 h8_set_state (SIM_DESC sd
, enum h8300_sim_state val
)
148 h8_get_cycles (SIM_DESC sd
)
150 return (STATE_CPU (sd
, 0)) -> regs
[CYCLE_REGNUM
];
154 h8_set_cycles (SIM_DESC sd
, unsigned int val
)
156 (STATE_CPU (sd
, 0)) -> regs
[CYCLE_REGNUM
] = val
;
160 h8_get_insts (SIM_DESC sd
)
162 return (STATE_CPU (sd
, 0)) -> regs
[INST_REGNUM
];
166 h8_set_insts (SIM_DESC sd
, unsigned int val
)
168 (STATE_CPU (sd
, 0)) -> regs
[INST_REGNUM
] = val
;
172 h8_get_ticks (SIM_DESC sd
)
174 return (STATE_CPU (sd
, 0)) -> regs
[TICK_REGNUM
];
178 h8_set_ticks (SIM_DESC sd
, unsigned int val
)
180 (STATE_CPU (sd
, 0)) -> regs
[TICK_REGNUM
] = val
;
184 h8_get_mach (SIM_DESC sd
)
186 return (STATE_CPU (sd
, 0)) -> regs
[MACH_REGNUM
];
190 h8_set_mach (SIM_DESC sd
, unsigned int val
)
192 (STATE_CPU (sd
, 0)) -> regs
[MACH_REGNUM
] = val
;
196 h8_get_macl (SIM_DESC sd
)
198 return (STATE_CPU (sd
, 0)) -> regs
[MACL_REGNUM
];
202 h8_set_macl (SIM_DESC sd
, unsigned int val
)
204 (STATE_CPU (sd
, 0)) -> regs
[MACL_REGNUM
] = val
;
207 static unsigned int *
208 h8_get_reg_buf (SIM_DESC sd
)
210 return &(((STATE_CPU (sd
, 0)) -> regs
)[0]);
214 h8_get_reg (SIM_DESC sd
, int regnum
)
216 return (STATE_CPU (sd
, 0)) -> regs
[regnum
];
220 h8_set_reg (SIM_DESC sd
, int regnum
, int val
)
222 (STATE_CPU (sd
, 0)) -> regs
[regnum
] = val
;
227 h8_get_stats (SIM_DESC sd
, int idx
)
229 return sd
-> stats
[idx
];
233 h8_increment_stats (SIM_DESC sd
, int idx
)
239 static unsigned char *
240 h8_get_memory_buf (SIM_DESC sd
)
242 return (STATE_CPU (sd
, 0)) -> memory
;
246 h8_set_memory_buf (SIM_DESC sd
, unsigned char *ptr
)
248 (STATE_CPU (sd
, 0)) -> memory
= ptr
;
252 h8_get_memory (SIM_DESC sd
, int idx
)
254 return (STATE_CPU (sd
, 0)) -> memory
[idx
];
258 h8_set_memory (SIM_DESC sd
, int idx
, unsigned int val
)
260 (STATE_CPU (sd
, 0)) -> memory
[idx
] = (unsigned char) val
;
263 static unsigned char *
264 h8_get_eightbit_buf (SIM_DESC sd
)
266 return (STATE_CPU (sd
, 0)) -> eightbit
;
270 h8_set_eightbit_buf (SIM_DESC sd
, unsigned char *ptr
)
272 (STATE_CPU (sd
, 0)) -> eightbit
= ptr
;
276 h8_get_eightbit (SIM_DESC sd
, int idx
)
278 return (STATE_CPU (sd
, 0)) -> eightbit
[idx
];
282 h8_set_eightbit (SIM_DESC sd
, int idx
, unsigned int val
)
284 (STATE_CPU (sd
, 0)) -> eightbit
[idx
] = (unsigned char) val
;
288 h8_get_delayed_branch (SIM_DESC sd
)
290 return (STATE_CPU (sd
, 0)) -> delayed_branch
;
294 h8_set_delayed_branch (SIM_DESC sd
, unsigned int dest
)
296 (STATE_CPU (sd
, 0)) -> delayed_branch
= dest
;
300 h8_get_command_line (SIM_DESC sd
)
302 return (STATE_CPU (sd
, 0)) -> command_line
;
306 h8_set_command_line (SIM_DESC sd
, char ** val
)
308 (STATE_CPU (sd
, 0)) -> command_line
= val
;
312 h8_get_cmdline_arg (SIM_DESC sd
, int index
)
314 return (STATE_CPU (sd
, 0)) -> command_line
[index
];
318 h8_set_cmdline_arg (SIM_DESC sd
, int index
, char * val
)
320 (STATE_CPU (sd
, 0)) -> command_line
[index
] = val
;
323 /* MAC Saturation Mode */
325 h8_get_macS (SIM_DESC sd
)
327 return (STATE_CPU (sd
, 0)) -> macS
;
331 h8_set_macS (SIM_DESC sd
, int val
)
333 (STATE_CPU (sd
, 0)) -> macS
= (val
!= 0);
338 h8_get_macZ (SIM_DESC sd
)
340 return (STATE_CPU (sd
, 0)) -> macZ
;
344 h8_set_macZ (SIM_DESC sd
, int val
)
346 (STATE_CPU (sd
, 0)) -> macZ
= (val
!= 0);
349 /* MAC Negative Flag */
351 h8_get_macN (SIM_DESC sd
)
353 return (STATE_CPU (sd
, 0)) -> macN
;
357 h8_set_macN (SIM_DESC sd
, int val
)
359 (STATE_CPU (sd
, 0)) -> macN
= (val
!= 0);
362 /* MAC Overflow Flag */
364 h8_get_macV (SIM_DESC sd
)
366 return (STATE_CPU (sd
, 0)) -> macV
;
370 h8_set_macV (SIM_DESC sd
, int val
)
372 (STATE_CPU (sd
, 0)) -> macV
= (val
!= 0);
375 /* End CPU data object. */
377 /* The rate at which to call the host's poll_quit callback. */
379 enum { POLL_QUIT_INTERVAL
= 0x80000 };
381 #define LOW_BYTE(x) ((x) & 0xff)
382 #define HIGH_BYTE(x) (((x) >> 8) & 0xff)
383 #define P(X, Y) ((X << 8) | Y)
392 #define I (intMaskBit != 0)
394 #define BUILDSR(SD) \
395 h8_set_ccr (SD, (I << 7) | (UI << 6) | (H << 5) | (U << 4) \
396 | (N << 3) | (Z << 2) | (V << 1) | C)
399 /* Get Status Register (flags). */ \
400 c = (h8_get_ccr (sd) >> 0) & 1; \
401 v = (h8_get_ccr (sd) >> 1) & 1; \
402 nz = !((h8_get_ccr (sd) >> 2) & 1); \
403 n = (h8_get_ccr (sd) >> 3) & 1; \
404 u = (h8_get_ccr (sd) >> 4) & 1; \
405 h = (h8_get_ccr (sd) >> 5) & 1; \
406 ui = ((h8_get_ccr (sd) >> 6) & 1); \
407 intMaskBit = (h8_get_ccr (sd) >> 7) & 1
410 #ifdef __CHAR_IS_SIGNED__
411 #define SEXTCHAR(x) ((char) (x))
415 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff) : x & 0xff)
418 #define UEXTCHAR(x) ((x) & 0xff)
419 #define UEXTSHORT(x) ((x) & 0xffff)
420 #define SEXTSHORT(x) ((short) (x))
424 int h8300_normal_mode
= 0;
427 static int memory_size
;
432 return time (0); /* WinXX HAS UNIX like 'time', so why not use it? */
454 return (h8300hmode
&& !h8300_normal_mode
)? SL
: SW
;
459 /* Simulate an indirection / dereference.
460 return 0 for success, -1 for failure.
464 lvalue (SIM_DESC sd
, int x
, int rn
, unsigned int *val
)
466 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
468 if (val
== NULL
) /* Paranoia. */
474 if (rn
== ZERO_REGNUM
)
475 *val
= X (OP_IMM
, SP
);
477 *val
= X (OP_REG
, SP
);
480 *val
= X (OP_MEM
, SP
);
483 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGSEGV
);
492 if (h8300smode
&& !h8300_normal_mode
)
494 else if (h8300hmode
&& !h8300_normal_mode
)
501 decode (SIM_DESC sd
, int addr
, unsigned char *data
, decoded_inst
*dst
)
503 int cst
[3] = {0, 0, 0};
504 int reg
[3] = {0, 0, 0};
505 int rdisp
[3] = {0, 0, 0};
507 const struct h8_opcode
*q
;
512 /* Find the exact opcode/arg combo. */
513 for (q
= h8_opcodes
; q
->name
; q
++)
515 const op_type
*nib
= q
->data
.nib
;
516 unsigned int len
= 0;
518 if ((q
->available
== AV_H8SX
&& !h8300sxmode
) ||
519 (q
->available
== AV_H8S
&& !h8300smode
) ||
520 (q
->available
== AV_H8H
&& !h8300hmode
))
523 cst
[0] = cst
[1] = cst
[2] = 0;
524 reg
[0] = reg
[1] = reg
[2] = 0;
525 rdisp
[0] = rdisp
[1] = rdisp
[2] = 0;
529 op_type looking_for
= *nib
;
530 int thisnib
= data
[len
/ 2];
532 thisnib
= (len
& 1) ? (thisnib
& 0xf) : ((thisnib
>> 4) & 0xf);
533 opnum
= ((looking_for
& OP3
) ? 2 :
534 (looking_for
& DST
) ? 1 : 0);
536 if (looking_for
< 16 && looking_for
>= 0)
538 if (looking_for
!= thisnib
)
543 if (looking_for
& B31
)
545 if (!((thisnib
& 0x8) != 0))
548 looking_for
= (op_type
) (looking_for
& ~B31
);
551 else if (looking_for
& B30
)
553 if (!((thisnib
& 0x8) == 0))
556 looking_for
= (op_type
) (looking_for
& ~B30
);
559 if (looking_for
& B21
)
561 if (!((thisnib
& 0x4) != 0))
564 looking_for
= (op_type
) (looking_for
& ~B21
);
567 else if (looking_for
& B20
)
569 if (!((thisnib
& 0x4) == 0))
572 looking_for
= (op_type
) (looking_for
& ~B20
);
575 if (looking_for
& B11
)
577 if (!((thisnib
& 0x2) != 0))
580 looking_for
= (op_type
) (looking_for
& ~B11
);
583 else if (looking_for
& B10
)
585 if (!((thisnib
& 0x2) == 0))
588 looking_for
= (op_type
) (looking_for
& ~B10
);
591 if (looking_for
& B01
)
593 if (!((thisnib
& 0x1) != 0))
596 looking_for
= (op_type
) (looking_for
& ~B01
);
599 else if (looking_for
& B00
)
601 if (!((thisnib
& 0x1) == 0))
604 looking_for
= (op_type
) (looking_for
& ~B00
);
607 if (looking_for
& IGNORE
)
609 /* Hitachi has declared that IGNORE must be zero. */
613 else if ((looking_for
& MODE
) == DATA
)
615 ; /* Skip embedded data. */
617 else if ((looking_for
& MODE
) == DBIT
)
619 /* Exclude adds/subs by looking at bit 0 and 2, and
620 make sure the operand size, either w or l,
621 matches by looking at bit 1. */
622 if ((looking_for
& 7) != (thisnib
& 7))
625 cst
[opnum
] = (thisnib
& 0x8) ? 2 : 1;
627 else if ((looking_for
& MODE
) == REG
||
628 (looking_for
& MODE
) == LOWREG
||
629 (looking_for
& MODE
) == IND
||
630 (looking_for
& MODE
) == PREINC
||
631 (looking_for
& MODE
) == POSTINC
||
632 (looking_for
& MODE
) == PREDEC
||
633 (looking_for
& MODE
) == POSTDEC
)
635 reg
[opnum
] = thisnib
;
637 else if (looking_for
& CTRL
)
640 if (((looking_for
& MODE
) == CCR
&& (thisnib
!= C_CCR
)) ||
641 ((looking_for
& MODE
) == EXR
&& (thisnib
!= C_EXR
)) ||
642 ((looking_for
& MODE
) == MACH
&& (thisnib
!= C_MACH
)) ||
643 ((looking_for
& MODE
) == MACL
&& (thisnib
!= C_MACL
)) ||
644 ((looking_for
& MODE
) == VBR
&& (thisnib
!= C_VBR
)) ||
645 ((looking_for
& MODE
) == SBR
&& (thisnib
!= C_SBR
)))
647 if (((looking_for
& MODE
) == CCR_EXR
&&
648 (thisnib
!= C_CCR
&& thisnib
!= C_EXR
)) ||
649 ((looking_for
& MODE
) == VBR_SBR
&&
650 (thisnib
!= C_VBR
&& thisnib
!= C_SBR
)) ||
651 ((looking_for
& MODE
) == MACREG
&&
652 (thisnib
!= C_MACH
&& thisnib
!= C_MACL
)))
654 if (((looking_for
& MODE
) == CC_EX_VB_SB
&&
655 (thisnib
!= C_CCR
&& thisnib
!= C_EXR
&&
656 thisnib
!= C_VBR
&& thisnib
!= C_SBR
)))
659 reg
[opnum
] = thisnib
;
661 else if ((looking_for
& MODE
) == ABS
)
663 /* Absolute addresses are unsigned. */
664 switch (looking_for
& SIZE
)
667 cst
[opnum
] = UEXTCHAR (data
[len
/ 2]);
671 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
675 (data
[len
/ 2 + 0] << 24) +
676 (data
[len
/ 2 + 1] << 16) +
677 (data
[len
/ 2 + 2] << 8) +
681 printf ("decode: bad size ABS: %d\n",
682 (looking_for
& SIZE
));
686 else if ((looking_for
& MODE
) == DISP
||
687 (looking_for
& MODE
) == PCREL
||
688 (looking_for
& MODE
) == INDEXB
||
689 (looking_for
& MODE
) == INDEXW
||
690 (looking_for
& MODE
) == INDEXL
)
692 switch (looking_for
& SIZE
)
695 cst
[opnum
] = thisnib
& 3;
698 cst
[opnum
] = SEXTCHAR (data
[len
/ 2]);
701 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
702 cst
[opnum
] = (short) cst
[opnum
]; /* Sign extend. */
705 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
709 (data
[len
/ 2 + 0] << 24) +
710 (data
[len
/ 2 + 1] << 16) +
711 (data
[len
/ 2 + 2] << 8) +
715 printf ("decode: bad size DISP/PCREL/INDEX: %d\n",
716 (looking_for
& SIZE
));
720 else if ((looking_for
& SIZE
) == L_16
||
721 (looking_for
& SIZE
) == L_16U
)
723 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
724 /* Immediates are always unsigned. */
725 if ((looking_for
& SIZE
) != L_16U
&&
726 (looking_for
& MODE
) != IMM
)
727 cst
[opnum
] = (short) cst
[opnum
]; /* Sign extend. */
729 else if (looking_for
& ABSJMP
)
731 switch (looking_for
& SIZE
) {
733 cst
[opnum
] = (data
[1] << 16) | (data
[2] << 8) | (data
[3]);
737 (data
[len
/ 2 + 0] << 24) +
738 (data
[len
/ 2 + 1] << 16) +
739 (data
[len
/ 2 + 2] << 8) +
743 printf ("decode: bad size ABSJMP: %d\n",
744 (looking_for
& SIZE
));
748 else if ((looking_for
& MODE
) == MEMIND
)
750 cst
[opnum
] = data
[1];
752 else if ((looking_for
& MODE
) == VECIND
)
754 if(h8300_normal_mode
)
755 cst
[opnum
] = ((data
[1] & 0x7f) + 0x80) * 2;
757 cst
[opnum
] = ((data
[1] & 0x7f) + 0x80) * 4;
758 cst
[opnum
] += h8_get_vbr (sd
); /* Add vector base reg. */
760 else if ((looking_for
& SIZE
) == L_32
)
765 (data
[i
+ 0] << 24) |
766 (data
[i
+ 1] << 16) |
770 else if ((looking_for
& SIZE
) == L_24
)
775 (data
[i
+ 0] << 16) |
779 else if (looking_for
& DISPREG
)
781 rdisp
[opnum
] = thisnib
& 0x7;
783 else if ((looking_for
& MODE
) == KBIT
)
800 else if ((looking_for
& SIZE
) == L_8
)
802 if ((looking_for
& MODE
) == ABS
)
804 /* Will be combined with contents of SBR_REGNUM
805 by fetch (). For all modes except h8sx, this
806 will always contain the value 0xFFFFFF00. */
807 cst
[opnum
] = data
[len
/ 2] & 0xff;
811 cst
[opnum
] = data
[len
/ 2] & 0xff;
814 else if ((looking_for
& SIZE
) == L_2
)
816 cst
[opnum
] = thisnib
& 3;
818 else if ((looking_for
& SIZE
) == L_3
||
819 (looking_for
& SIZE
) == L_3NZ
)
821 cst
[opnum
] = thisnib
& 7;
822 if (cst
[opnum
] == 0 && (looking_for
& SIZE
) == L_3NZ
)
825 else if ((looking_for
& SIZE
) == L_4
)
827 cst
[opnum
] = thisnib
& 15;
829 else if ((looking_for
& SIZE
) == L_5
)
831 cst
[opnum
] = data
[len
/ 2] & 0x1f;
833 else if (looking_for
== E
)
838 /* Fill in the args. */
840 const op_type
*args
= q
->args
.nib
;
845 nargs
< 3 && *args
!= E
;
851 opnum
= ((x
& OP3
) ? 2 :
860 if ((x
& MODE
) == IMM
||
861 (x
& MODE
) == KBIT
||
864 /* Use the instruction to determine
866 p
->type
= X (OP_IMM
, OP_SIZE (q
->how
));
867 p
->literal
= cst
[opnum
];
869 else if ((x
& MODE
) == CONST_2
||
870 (x
& MODE
) == CONST_4
||
871 (x
& MODE
) == CONST_8
||
872 (x
& MODE
) == CONST_16
)
874 /* Use the instruction to determine
876 p
->type
= X (OP_IMM
, OP_SIZE (q
->how
));
878 case CONST_2
: p
->literal
= 2; break;
879 case CONST_4
: p
->literal
= 4; break;
880 case CONST_8
: p
->literal
= 8; break;
881 case CONST_16
: p
->literal
= 16; break;
884 else if ((x
& MODE
) == REG
)
886 p
->type
= X (OP_REG
, bitfrom (x
));
889 else if ((x
& MODE
) == LOWREG
)
891 p
->type
= X (OP_LOWREG
, bitfrom (x
));
894 else if ((x
& MODE
) == PREINC
)
896 /* Use the instruction to determine
898 p
->type
= X (OP_PREINC
, OP_SIZE (q
->how
));
899 p
->reg
= reg
[opnum
] & 0x7;
901 else if ((x
& MODE
) == POSTINC
)
903 /* Use the instruction to determine
905 p
->type
= X (OP_POSTINC
, OP_SIZE (q
->how
));
906 p
->reg
= reg
[opnum
] & 0x7;
908 else if ((x
& MODE
) == PREDEC
)
910 /* Use the instruction to determine
912 p
->type
= X (OP_PREDEC
, OP_SIZE (q
->how
));
913 p
->reg
= reg
[opnum
] & 0x7;
915 else if ((x
& MODE
) == POSTDEC
)
917 /* Use the instruction to determine
919 p
->type
= X (OP_POSTDEC
, OP_SIZE (q
->how
));
920 p
->reg
= reg
[opnum
] & 0x7;
922 else if ((x
& MODE
) == IND
)
924 /* Note: an indirect is transformed into
925 a displacement of zero.
927 /* Use the instruction to determine
929 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
930 p
->reg
= reg
[opnum
] & 0x7;
932 if (OP_KIND (q
->how
) == O_JSR
||
933 OP_KIND (q
->how
) == O_JMP
)
934 if (lvalue (sd
, p
->type
, p
->reg
, (unsigned int *)&p
->type
))
937 else if ((x
& MODE
) == ABS
)
939 /* Note: a 16 or 32 bit ABS is transformed into a
940 displacement from pseudo-register ZERO_REGNUM,
941 which is always zero. An 8 bit ABS becomes
942 a displacement from SBR_REGNUM.
944 /* Use the instruction to determine
946 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
947 p
->literal
= cst
[opnum
];
949 /* 8-bit ABS is displacement from SBR.
950 16 and 32-bit ABS are displacement from ZERO.
951 (SBR will always be zero except for h8/sx)
953 if ((x
& SIZE
) == L_8
)
956 p
->reg
= ZERO_REGNUM
;;
958 else if ((x
& MODE
) == MEMIND
||
959 (x
& MODE
) == VECIND
)
961 /* Size doesn't matter. */
962 p
->type
= X (OP_MEM
, SB
);
963 p
->literal
= cst
[opnum
];
964 if (OP_KIND (q
->how
) == O_JSR
||
965 OP_KIND (q
->how
) == O_JMP
)
966 if (lvalue (sd
, p
->type
, p
->reg
, (unsigned int *)&p
->type
))
969 else if ((x
& MODE
) == PCREL
)
971 /* Size doesn't matter. */
972 p
->type
= X (OP_PCREL
, SB
);
973 p
->literal
= cst
[opnum
];
977 p
->type
= X (OP_IMM
, SP
);
978 p
->literal
= cst
[opnum
];
980 else if ((x
& MODE
) == INDEXB
)
982 p
->type
= X (OP_INDEXB
, OP_SIZE (q
->how
));
983 p
->literal
= cst
[opnum
];
984 p
->reg
= rdisp
[opnum
];
986 else if ((x
& MODE
) == INDEXW
)
988 p
->type
= X (OP_INDEXW
, OP_SIZE (q
->how
));
989 p
->literal
= cst
[opnum
];
990 p
->reg
= rdisp
[opnum
];
992 else if ((x
& MODE
) == INDEXL
)
994 p
->type
= X (OP_INDEXL
, OP_SIZE (q
->how
));
995 p
->literal
= cst
[opnum
];
996 p
->reg
= rdisp
[opnum
];
998 else if ((x
& MODE
) == DISP
)
1000 /* Yuck -- special for mova args. */
1001 if (strncmp (q
->name
, "mova", 4) == 0 &&
1004 /* Mova can have a DISP2 dest, with an
1005 INDEXB or INDEXW src. The multiplier
1006 for the displacement value is determined
1007 by the src operand, not by the insn. */
1009 switch (OP_KIND (dst
->src
.type
))
1012 p
->type
= X (OP_DISP
, SB
);
1013 p
->literal
= cst
[opnum
];
1016 p
->type
= X (OP_DISP
, SW
);
1017 p
->literal
= cst
[opnum
] * 2;
1025 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
1026 p
->literal
= cst
[opnum
];
1027 /* DISP2 is special. */
1028 if ((x
& SIZE
) == L_2
)
1029 switch (OP_SIZE (q
->how
))
1032 case SW
: p
->literal
*= 2; break;
1033 case SL
: p
->literal
*= 4; break;
1036 p
->reg
= rdisp
[opnum
];
1043 p
->type
= X (OP_CCR
, SB
);
1046 p
->type
= X (OP_EXR
, SB
);
1049 p
->type
= X (OP_MACH
, SL
);
1052 p
->type
= X (OP_MACL
, SL
);
1055 p
->type
= X (OP_VBR
, SL
);
1058 p
->type
= X (OP_SBR
, SL
);
1062 else if ((x
& MODE
) == CCR
)
1066 else if ((x
& MODE
) == EXR
)
1071 printf ("Hmmmm 0x%x...\n", x
);
1077 /* Unary operators: treat src and dst as equivalent. */
1078 if (dst
->dst
.type
== -1)
1079 dst
->dst
= dst
->src
;
1080 if (dst
->src
.type
== -1)
1081 dst
->src
= dst
->dst
;
1083 dst
->opcode
= q
->how
;
1084 dst
->cycles
= q
->time
;
1086 /* And jsr's to these locations are turned into
1089 if (OP_KIND (dst
->opcode
) == O_JSR
)
1091 switch (dst
->src
.literal
)
1094 dst
->opcode
= O (O_SYS_OPEN
, SB
);
1097 dst
->opcode
= O (O_SYS_READ
, SB
);
1100 dst
->opcode
= O (O_SYS_WRITE
, SB
);
1103 dst
->opcode
= O (O_SYS_LSEEK
, SB
);
1106 dst
->opcode
= O (O_SYS_CLOSE
, SB
);
1109 dst
->opcode
= O (O_SYS_STAT
, SB
);
1112 dst
->opcode
= O (O_SYS_FSTAT
, SB
);
1115 dst
->opcode
= O (O_SYS_CMDLINE
, SB
);
1118 /* End of Processing for system calls. */
1121 dst
->next_pc
= addr
+ len
/ 2;
1125 printf ("Don't understand 0x%x \n", looking_for
);
1136 /* Fell off the end. */
1137 dst
->opcode
= O (O_ILL
, SB
);
1140 static unsigned char *breg
[32];
1141 static unsigned short *wreg
[16];
1143 #define GET_B_REG(X) *(breg[X])
1144 #define SET_B_REG(X, Y) (*(breg[X])) = (Y)
1145 #define GET_W_REG(X) *(wreg[X])
1146 #define SET_W_REG(X, Y) (*(wreg[X])) = (Y)
1147 #define GET_L_REG(X) h8_get_reg (sd, X)
1148 #define SET_L_REG(X, Y) h8_set_reg (sd, X, Y)
1150 #define GET_MEMORY_L(X) \
1151 ((X) < memory_size \
1152 ? ((h8_get_memory (sd, (X)+0) << 24) | (h8_get_memory (sd, (X)+1) << 16) \
1153 | (h8_get_memory (sd, (X)+2) << 8) | (h8_get_memory (sd, (X)+3) << 0)) \
1154 : ((h8_get_eightbit (sd, ((X)+0) & 0xff) << 24) \
1155 | (h8_get_eightbit (sd, ((X)+1) & 0xff) << 16) \
1156 | (h8_get_eightbit (sd, ((X)+2) & 0xff) << 8) \
1157 | (h8_get_eightbit (sd, ((X)+3) & 0xff) << 0)))
1159 #define GET_MEMORY_W(X) \
1160 ((X) < memory_size \
1161 ? ((h8_get_memory (sd, (X)+0) << 8) \
1162 | (h8_get_memory (sd, (X)+1) << 0)) \
1163 : ((h8_get_eightbit (sd, ((X)+0) & 0xff) << 8) \
1164 | (h8_get_eightbit (sd, ((X)+1) & 0xff) << 0)))
1167 #define GET_MEMORY_B(X) \
1168 ((X) < memory_size ? (h8_get_memory (sd, (X))) \
1169 : (h8_get_eightbit (sd, (X) & 0xff)))
1171 #define SET_MEMORY_L(X, Y) \
1172 { register unsigned char *_p; register int __y = (Y); \
1173 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : \
1174 h8_get_eightbit_buf (sd) + ((X) & 0xff)); \
1175 _p[0] = __y >> 24; _p[1] = __y >> 16; \
1176 _p[2] = __y >> 8; _p[3] = __y >> 0; \
1179 #define SET_MEMORY_W(X, Y) \
1180 { register unsigned char *_p; register int __y = (Y); \
1181 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : \
1182 h8_get_eightbit_buf (sd) + ((X) & 0xff)); \
1183 _p[0] = __y >> 8; _p[1] = __y; \
1186 #define SET_MEMORY_B(X, Y) \
1187 ((X) < memory_size ? (h8_set_memory (sd, (X), (Y))) \
1188 : (h8_set_eightbit (sd, (X) & 0xff, (Y))))
1190 /* Simulate a memory fetch.
1191 Return 0 for success, -1 for failure.
1195 fetch_1 (SIM_DESC sd
, ea_type
*arg
, int *val
, int twice
)
1197 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1199 int abs
= arg
->literal
;
1204 return -1; /* Paranoia. */
1208 /* Indexed register plus displacement mode:
1210 This new family of addressing modes are similar to OP_DISP
1211 (register plus displacement), with two differences:
1212 1) INDEXB uses only the least significant byte of the register,
1213 INDEXW uses only the least significant word, and
1214 INDEXL uses the entire register (just like OP_DISP).
1216 2) The displacement value in abs is multiplied by two
1217 for SW-sized operations, and by four for SL-size.
1219 This gives nine possible variations.
1222 case X (OP_INDEXB
, SB
):
1223 case X (OP_INDEXB
, SW
):
1224 case X (OP_INDEXB
, SL
):
1225 case X (OP_INDEXW
, SB
):
1226 case X (OP_INDEXW
, SW
):
1227 case X (OP_INDEXW
, SL
):
1228 case X (OP_INDEXL
, SB
):
1229 case X (OP_INDEXL
, SW
):
1230 case X (OP_INDEXL
, SL
):
1232 switch (OP_KIND (arg
->type
)) {
1233 case OP_INDEXB
: t
&= 0xff; break;
1234 case OP_INDEXW
: t
&= 0xffff; break;
1238 switch (OP_SIZE (arg
->type
)) {
1240 *val
= GET_MEMORY_B ((t
* 1 + abs
) & h8_get_mask (sd
));
1243 *val
= GET_MEMORY_W ((t
* 2 + abs
) & h8_get_mask (sd
));
1246 *val
= GET_MEMORY_L ((t
* 4 + abs
) & h8_get_mask (sd
));
1251 case X (OP_LOWREG
, SB
):
1252 *val
= GET_L_REG (rn
) & 0xff;
1254 case X (OP_LOWREG
, SW
):
1255 *val
= GET_L_REG (rn
) & 0xffff;
1258 case X (OP_REG
, SB
): /* Register direct, byte. */
1259 *val
= GET_B_REG (rn
);
1261 case X (OP_REG
, SW
): /* Register direct, word. */
1262 *val
= GET_W_REG (rn
);
1264 case X (OP_REG
, SL
): /* Register direct, long. */
1265 *val
= GET_L_REG (rn
);
1267 case X (OP_IMM
, SB
): /* Immediate, byte. */
1268 case X (OP_IMM
, SW
): /* Immediate, word. */
1269 case X (OP_IMM
, SL
): /* Immediate, long. */
1272 case X (OP_POSTINC
, SB
): /* Register indirect w/post-incr: byte. */
1274 r
= GET_MEMORY_B (t
& h8_get_mask (sd
));
1280 case X (OP_POSTINC
, SW
): /* Register indirect w/post-incr: word. */
1282 r
= GET_MEMORY_W (t
& h8_get_mask (sd
));
1288 case X (OP_POSTINC
, SL
): /* Register indirect w/post-incr: long. */
1290 r
= GET_MEMORY_L (t
& h8_get_mask (sd
));
1297 case X (OP_POSTDEC
, SB
): /* Register indirect w/post-decr: byte. */
1299 r
= GET_MEMORY_B (t
& h8_get_mask (sd
));
1305 case X (OP_POSTDEC
, SW
): /* Register indirect w/post-decr: word. */
1307 r
= GET_MEMORY_W (t
& h8_get_mask (sd
));
1313 case X (OP_POSTDEC
, SL
): /* Register indirect w/post-decr: long. */
1315 r
= GET_MEMORY_L (t
& h8_get_mask (sd
));
1322 case X (OP_PREDEC
, SB
): /* Register indirect w/pre-decr: byte. */
1323 t
= GET_L_REG (rn
) - 1;
1325 t
&= h8_get_mask (sd
);
1326 *val
= GET_MEMORY_B (t
);
1329 case X (OP_PREDEC
, SW
): /* Register indirect w/pre-decr: word. */
1330 t
= GET_L_REG (rn
) - 2;
1332 t
&= h8_get_mask (sd
);
1333 *val
= GET_MEMORY_W (t
);
1336 case X (OP_PREDEC
, SL
): /* Register indirect w/pre-decr: long. */
1337 t
= GET_L_REG (rn
) - 4;
1339 t
&= h8_get_mask (sd
);
1340 *val
= GET_MEMORY_L (t
);
1343 case X (OP_PREINC
, SB
): /* Register indirect w/pre-incr: byte. */
1344 t
= GET_L_REG (rn
) + 1;
1346 t
&= h8_get_mask (sd
);
1347 *val
= GET_MEMORY_B (t
);
1350 case X (OP_PREINC
, SW
): /* Register indirect w/pre-incr: long. */
1351 t
= GET_L_REG (rn
) + 2;
1353 t
&= h8_get_mask (sd
);
1354 *val
= GET_MEMORY_W (t
);
1357 case X (OP_PREINC
, SL
): /* Register indirect w/pre-incr: long. */
1358 t
= GET_L_REG (rn
) + 4;
1360 t
&= h8_get_mask (sd
);
1361 *val
= GET_MEMORY_L (t
);
1364 case X (OP_DISP
, SB
): /* Register indirect w/displacement: byte. */
1365 t
= GET_L_REG (rn
) + abs
;
1366 t
&= h8_get_mask (sd
);
1367 *val
= GET_MEMORY_B (t
);
1370 case X (OP_DISP
, SW
): /* Register indirect w/displacement: word. */
1371 t
= GET_L_REG (rn
) + abs
;
1372 t
&= h8_get_mask (sd
);
1373 *val
= GET_MEMORY_W (t
);
1376 case X (OP_DISP
, SL
): /* Register indirect w/displacement: long. */
1377 t
= GET_L_REG (rn
) + abs
;
1378 t
&= h8_get_mask (sd
);
1379 *val
=GET_MEMORY_L (t
);
1382 case X (OP_MEM
, SL
): /* Absolute memory address, long. */
1383 t
= GET_MEMORY_L (abs
);
1384 t
&= h8_get_mask (sd
);
1388 case X (OP_MEM
, SW
): /* Absolute memory address, word. */
1389 t
= GET_MEMORY_W (abs
);
1390 t
&= h8_get_mask (sd
);
1394 case X (OP_PCREL
, SB
): /* PC relative (for jump, branch etc). */
1395 case X (OP_PCREL
, SW
):
1396 case X (OP_PCREL
, SL
):
1397 case X (OP_PCREL
, SN
):
1401 case X (OP_MEM
, SB
): /* Why isn't this implemented? */
1403 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGSEGV
);
1406 return 0; /* Success. */
1412 fetch (SIM_DESC sd
, ea_type
*arg
, int *val
)
1414 return fetch_1 (sd
, arg
, val
, 0);
1417 /* Fetch which will be followed by a store to the same location.
1418 The difference being that we don't want to do a post-increment
1419 or post-decrement at this time: we'll do it when we store. */
1422 fetch2 (SIM_DESC sd
, ea_type
*arg
, int *val
)
1424 return fetch_1 (sd
, arg
, val
, 1);
1427 /* Simulate a memory store.
1428 Return 0 for success, -1 for failure.
1432 store_1 (SIM_DESC sd
, ea_type
*arg
, int n
, int twice
)
1434 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1436 int abs
= arg
->literal
;
1441 /* Indexed register plus displacement mode:
1443 This new family of addressing modes are similar to OP_DISP
1444 (register plus displacement), with two differences:
1445 1) INDEXB uses only the least significant byte of the register,
1446 INDEXW uses only the least significant word, and
1447 INDEXL uses the entire register (just like OP_DISP).
1449 2) The displacement value in abs is multiplied by two
1450 for SW-sized operations, and by four for SL-size.
1452 This gives nine possible variations.
1455 case X (OP_INDEXB
, SB
):
1456 case X (OP_INDEXB
, SW
):
1457 case X (OP_INDEXB
, SL
):
1458 case X (OP_INDEXW
, SB
):
1459 case X (OP_INDEXW
, SW
):
1460 case X (OP_INDEXW
, SL
):
1461 case X (OP_INDEXL
, SB
):
1462 case X (OP_INDEXL
, SW
):
1463 case X (OP_INDEXL
, SL
):
1465 switch (OP_KIND (arg
->type
)) {
1466 case OP_INDEXB
: t
&= 0xff; break;
1467 case OP_INDEXW
: t
&= 0xffff; break;
1471 switch (OP_SIZE (arg
->type
)) {
1473 SET_MEMORY_B ((t
* 1 + abs
) & h8_get_mask (sd
), n
);
1476 SET_MEMORY_W ((t
* 2 + abs
) & h8_get_mask (sd
), n
);
1479 SET_MEMORY_L ((t
* 4 + abs
) & h8_get_mask (sd
), n
);
1484 case X (OP_REG
, SB
): /* Register direct, byte. */
1487 case X (OP_REG
, SW
): /* Register direct, word. */
1490 case X (OP_REG
, SL
): /* Register direct, long. */
1494 case X (OP_PREDEC
, SB
): /* Register indirect w/pre-decr, byte. */
1499 t
&= h8_get_mask (sd
);
1500 SET_MEMORY_B (t
, n
);
1503 case X (OP_PREDEC
, SW
): /* Register indirect w/pre-decr, word. */
1508 t
&= h8_get_mask (sd
);
1509 SET_MEMORY_W (t
, n
);
1512 case X (OP_PREDEC
, SL
): /* Register indirect w/pre-decr, long. */
1517 t
&= h8_get_mask (sd
);
1518 SET_MEMORY_L (t
, n
);
1521 case X (OP_PREINC
, SB
): /* Register indirect w/pre-incr, byte. */
1526 t
&= h8_get_mask (sd
);
1527 SET_MEMORY_B (t
, n
);
1530 case X (OP_PREINC
, SW
): /* Register indirect w/pre-incr, word. */
1535 t
&= h8_get_mask (sd
);
1536 SET_MEMORY_W (t
, n
);
1539 case X (OP_PREINC
, SL
): /* Register indirect w/pre-incr, long. */
1544 t
&= h8_get_mask (sd
);
1545 SET_MEMORY_L (t
, n
);
1548 case X (OP_POSTDEC
, SB
): /* Register indirect w/post-decr, byte. */
1550 SET_L_REG (rn
, t
- 1);
1551 t
&= h8_get_mask (sd
);
1552 SET_MEMORY_B (t
, n
);
1555 case X (OP_POSTDEC
, SW
): /* Register indirect w/post-decr, word. */
1557 SET_L_REG (rn
, t
- 2);
1558 t
&= h8_get_mask (sd
);
1559 SET_MEMORY_W (t
, n
);
1562 case X (OP_POSTDEC
, SL
): /* Register indirect w/post-decr, long. */
1564 SET_L_REG (rn
, t
- 4);
1565 t
&= h8_get_mask (sd
);
1566 SET_MEMORY_L (t
, n
);
1569 case X (OP_POSTINC
, SB
): /* Register indirect w/post-incr, byte. */
1571 SET_L_REG (rn
, t
+ 1);
1572 t
&= h8_get_mask (sd
);
1573 SET_MEMORY_B (t
, n
);
1576 case X (OP_POSTINC
, SW
): /* Register indirect w/post-incr, word. */
1578 SET_L_REG (rn
, t
+ 2);
1579 t
&= h8_get_mask (sd
);
1580 SET_MEMORY_W (t
, n
);
1583 case X (OP_POSTINC
, SL
): /* Register indirect w/post-incr, long. */
1585 SET_L_REG (rn
, t
+ 4);
1586 t
&= h8_get_mask (sd
);
1587 SET_MEMORY_L (t
, n
);
1590 case X (OP_DISP
, SB
): /* Register indirect w/displacement, byte. */
1591 t
= GET_L_REG (rn
) + abs
;
1592 t
&= h8_get_mask (sd
);
1593 SET_MEMORY_B (t
, n
);
1596 case X (OP_DISP
, SW
): /* Register indirect w/displacement, word. */
1597 t
= GET_L_REG (rn
) + abs
;
1598 t
&= h8_get_mask (sd
);
1599 SET_MEMORY_W (t
, n
);
1602 case X (OP_DISP
, SL
): /* Register indirect w/displacement, long. */
1603 t
= GET_L_REG (rn
) + abs
;
1604 t
&= h8_get_mask (sd
);
1605 SET_MEMORY_L (t
, n
);
1609 case X (OP_MEM
, SB
): /* Why isn't this implemented? */
1610 case X (OP_MEM
, SW
): /* Why isn't this implemented? */
1611 case X (OP_MEM
, SL
): /* Why isn't this implemented? */
1613 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGSEGV
);
1622 store (SIM_DESC sd
, ea_type
*arg
, int n
)
1624 return store_1 (sd
, arg
, n
, 0);
1627 /* Store which follows a fetch from the same location.
1628 The difference being that we don't want to do a pre-increment
1629 or pre-decrement at this time: it was already done when we fetched. */
1632 store2 (SIM_DESC sd
, ea_type
*arg
, int n
)
1634 return store_1 (sd
, arg
, n
, 1);
1637 /* Flag to be set whenever a new SIM_DESC object is created. */
1638 static int init_pointers_needed
= 1;
1641 init_pointers (SIM_DESC sd
)
1643 if (init_pointers_needed
)
1647 if (h8300smode
&& !h8300_normal_mode
)
1648 memory_size
= H8300S_MSIZE
;
1649 else if (h8300hmode
&& !h8300_normal_mode
)
1650 memory_size
= H8300H_MSIZE
;
1652 memory_size
= H8300_MSIZE
;
1653 /* `msize' must be a power of two. */
1654 if ((memory_size
& (memory_size
- 1)) != 0)
1658 "init_pointers: bad memory size %d, defaulting to %d.\n",
1659 memory_size
, memory_size
= H8300S_MSIZE
);
1662 if (h8_get_memory_buf (sd
))
1663 free (h8_get_memory_buf (sd
));
1664 if (h8_get_eightbit_buf (sd
))
1665 free (h8_get_eightbit_buf (sd
));
1667 h8_set_memory_buf (sd
, (unsigned char *)
1668 calloc (sizeof (char), memory_size
));
1669 sd
->memory_size
= memory_size
;
1670 h8_set_eightbit_buf (sd
, (unsigned char *) calloc (sizeof (char), 256));
1672 h8_set_mask (sd
, memory_size
- 1);
1674 memset (h8_get_reg_buf (sd
), 0, sizeof (((STATE_CPU (sd
, 0))->regs
)));
1676 for (i
= 0; i
< 8; i
++)
1678 /* FIXME: rewrite using local buffer. */
1679 unsigned char *p
= (unsigned char *) (h8_get_reg_buf (sd
) + i
);
1680 unsigned char *e
= (unsigned char *) (h8_get_reg_buf (sd
) + i
+ 1);
1681 unsigned short *q
= (unsigned short *) (h8_get_reg_buf (sd
) + i
);
1682 unsigned short *u
= (unsigned short *) (h8_get_reg_buf (sd
) + i
+ 1);
1683 h8_set_reg (sd
, i
, 0x00112233);
1698 wreg
[i
] = wreg
[i
+ 8] = 0;
1712 if (wreg
[i
] == 0 || wreg
[i
+ 8] == 0)
1713 sim_io_printf (sd
, "init_pointers: internal error.\n");
1715 h8_set_reg (sd
, i
, 0);
1718 init_pointers_needed
= 0;
1722 #define OBITOP(name, f, s, op) \
1723 case O (name, SB): \
1728 if (fetch (sd, &code->dst, &ea)) \
1730 if (fetch (sd, &code->src, &tmp)) \
1732 m = 1 << (tmp & 7); \
1735 if (store (sd, &code->dst,ea)) \
1741 step_once (SIM_DESC sd
, SIM_CPU
*cpu
)
1745 int tick_start
= get_now ();
1752 int c
, nz
, v
, n
, u
, h
, ui
, intMaskBit
;
1755 host_callback
*sim_callback
= STATE_CALLBACK (sd
);
1759 pc
= h8_get_pc (sd
);
1761 /* The PC should never be odd. */
1764 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGBUS
);
1768 /* Get Status Register (flags). */
1771 if (h8300smode
) /* Get exr. */
1773 trace
= (h8_get_exr (sd
) >> 7) & 1;
1774 intMask
= h8_get_exr (sd
) & 7;
1777 oldmask
= h8_get_mask (sd
);
1778 if (!h8300hmode
|| h8300_normal_mode
)
1779 h8_set_mask (sd
, 0xffff);
1782 decoded_inst _code
, *code
= &_code
;
1783 memset (code
, 0, sizeof (*code
));
1784 decode (sd
, pc
, h8_get_memory_buf (sd
) + pc
, code
);
1790 printf ("%x %d %s\n", pc
, code
->opcode
,
1791 code
->op
? code
->op
->name
: "**");
1793 h8_increment_stats (sd
, code
->opcode
);
1798 cycles
+= code
->cycles
;
1802 switch (code
->opcode
)
1804 case O (O_MOVAB
, SL
):
1805 case O (O_MOVAW
, SL
):
1806 case O (O_MOVAL
, SL
):
1807 /* 1) Evaluate 2nd argument (dst).
1808 2) Mask / zero extend according to whether 1st argument (src)
1809 is INDEXB, INDEXW, or INDEXL.
1810 3) Left-shift the result by 0, 1 or 2, according to size of mova
1811 (mova/b, mova/w, mova/l).
1812 4) Add literal value of 1st argument (src).
1813 5) Store result in 3rd argument (op3).
1816 /* Alas, since this is the only instruction with 3 arguments,
1817 decode doesn't handle them very well. Some fix-up is required.
1819 a) The size of dst is determined by whether src is
1820 INDEXB or INDEXW. */
1822 if (OP_KIND (code
->src
.type
) == OP_INDEXB
)
1823 code
->dst
.type
= X (OP_KIND (code
->dst
.type
), SB
);
1824 else if (OP_KIND (code
->src
.type
) == OP_INDEXW
)
1825 code
->dst
.type
= X (OP_KIND (code
->dst
.type
), SW
);
1827 /* b) If op3 == null, then this is the short form of the insn.
1828 Dst is the dispreg of src, and op3 is the 32-bit form
1829 of the same register.
1832 if (code
->op3
.type
== 0)
1834 /* Short form: src == INDEXB/INDEXW, dst == op3 == 0.
1835 We get to compose dst and op3 as follows:
1837 op3 is a 32-bit register, ID == src.reg.
1838 dst is the same register, but 8 or 16 bits
1839 depending on whether src is INDEXB or INDEXW.
1842 code
->op3
.type
= X (OP_REG
, SL
);
1843 code
->op3
.reg
= code
->src
.reg
;
1844 code
->op3
.literal
= 0;
1846 if (OP_KIND (code
->src
.type
) == OP_INDEXB
)
1848 code
->dst
.type
= X (OP_REG
, SB
);
1849 code
->dst
.reg
= code
->op3
.reg
+ 8;
1852 code
->dst
.type
= X (OP_REG
, SW
);
1855 if (fetch (sd
, &code
->dst
, &ea
))
1858 switch (OP_KIND (code
->src
.type
)) {
1859 case OP_INDEXB
: ea
= ea
& 0xff; break;
1860 case OP_INDEXW
: ea
= ea
& 0xffff; break;
1861 case OP_INDEXL
: break;
1862 default: goto illegal
;
1865 switch (code
->opcode
) {
1866 case O (O_MOVAB
, SL
): break;
1867 case O (O_MOVAW
, SL
): ea
= ea
<< 1; break;
1868 case O (O_MOVAL
, SL
): ea
= ea
<< 2; break;
1869 default: goto illegal
;
1872 ea
= ea
+ code
->src
.literal
;
1874 if (store (sd
, &code
->op3
, ea
))
1879 case O (O_SUBX
, SB
): /* subx, extended sub */
1880 if (fetch2 (sd
, &code
->dst
, &rd
))
1882 if (fetch (sd
, &code
->src
, &ea
))
1888 case O (O_SUBX
, SW
): /* subx, extended sub */
1889 if (fetch2 (sd
, &code
->dst
, &rd
))
1891 if (fetch (sd
, &code
->src
, &ea
))
1897 case O (O_SUBX
, SL
): /* subx, extended sub */
1898 if (fetch2 (sd
, &code
->dst
, &rd
))
1900 if (fetch (sd
, &code
->src
, &ea
))
1906 case O (O_ADDX
, SB
): /* addx, extended add */
1907 if (fetch2 (sd
, &code
->dst
, &rd
))
1909 if (fetch (sd
, &code
->src
, &ea
))
1915 case O (O_ADDX
, SW
): /* addx, extended add */
1916 if (fetch2 (sd
, &code
->dst
, &rd
))
1918 if (fetch (sd
, &code
->src
, &ea
))
1924 case O (O_ADDX
, SL
): /* addx, extended add */
1925 if (fetch2 (sd
, &code
->dst
, &rd
))
1927 if (fetch (sd
, &code
->src
, &ea
))
1933 case O (O_SUB
, SB
): /* sub.b */
1934 /* Fetch rd and ea. */
1935 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1941 case O (O_SUB
, SW
): /* sub.w */
1942 /* Fetch rd and ea. */
1943 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1949 case O (O_SUB
, SL
): /* sub.l */
1950 /* Fetch rd and ea. */
1951 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1957 case O (O_NEG
, SB
): /* neg.b */
1959 if (fetch2 (sd
, &code
->src
, &ea
))
1966 case O (O_NEG
, SW
): /* neg.w */
1968 if (fetch2 (sd
, &code
->src
, &ea
))
1975 case O (O_NEG
, SL
): /* neg.l */
1977 if (fetch2 (sd
, &code
->src
, &ea
))
1984 case O (O_ADD
, SB
): /* add.b */
1985 if (fetch2 (sd
, &code
->dst
, &rd
))
1987 if (fetch (sd
, &code
->src
, &ea
))
1992 case O (O_ADD
, SW
): /* add.w */
1993 if (fetch2 (sd
, &code
->dst
, &rd
))
1995 if (fetch (sd
, &code
->src
, &ea
))
2000 case O (O_ADD
, SL
): /* add.l */
2001 if (fetch2 (sd
, &code
->dst
, &rd
))
2003 if (fetch (sd
, &code
->src
, &ea
))
2008 case O (O_AND
, SB
): /* and.b */
2009 /* Fetch rd and ea. */
2010 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2015 case O (O_AND
, SW
): /* and.w */
2016 /* Fetch rd and ea. */
2017 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2022 case O (O_AND
, SL
): /* and.l */
2023 /* Fetch rd and ea. */
2024 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2029 case O (O_OR
, SB
): /* or.b */
2030 /* Fetch rd and ea. */
2031 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2036 case O (O_OR
, SW
): /* or.w */
2037 /* Fetch rd and ea. */
2038 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2043 case O (O_OR
, SL
): /* or.l */
2044 /* Fetch rd and ea. */
2045 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2050 case O (O_XOR
, SB
): /* xor.b */
2051 /* Fetch rd and ea. */
2052 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2057 case O (O_XOR
, SW
): /* xor.w */
2058 /* Fetch rd and ea. */
2059 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2064 case O (O_XOR
, SL
): /* xor.l */
2065 /* Fetch rd and ea. */
2066 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2072 if (fetch (sd
, &code
->src
, &res
))
2074 if (store (sd
, &code
->dst
, res
))
2076 goto just_flags_log8
;
2078 if (fetch (sd
, &code
->src
, &res
))
2080 if (store (sd
, &code
->dst
, res
))
2082 goto just_flags_log16
;
2084 if (fetch (sd
, &code
->src
, &res
))
2086 if (store (sd
, &code
->dst
, res
))
2088 goto just_flags_log32
;
2090 case O (O_MOVMD
, SB
): /* movmd.b */
2097 rd
= GET_MEMORY_B (GET_L_REG (5));
2098 SET_MEMORY_B (GET_L_REG (6), rd
);
2099 SET_L_REG (5, GET_L_REG (5) + 1);
2100 SET_L_REG (6, GET_L_REG (6) + 1);
2105 case O (O_MOVMD
, SW
): /* movmd.w */
2112 rd
= GET_MEMORY_W (GET_L_REG (5));
2113 SET_MEMORY_W (GET_L_REG (6), rd
);
2114 SET_L_REG (5, GET_L_REG (5) + 2);
2115 SET_L_REG (6, GET_L_REG (6) + 2);
2120 case O (O_MOVMD
, SL
): /* movmd.l */
2127 rd
= GET_MEMORY_L (GET_L_REG (5));
2128 SET_MEMORY_L (GET_L_REG (6), rd
);
2129 SET_L_REG (5, GET_L_REG (5) + 4);
2130 SET_L_REG (6, GET_L_REG (6) + 4);
2135 case O (O_MOVSD
, SB
): /* movsd.b */
2136 /* This instruction implements strncpy, with a conditional branch.
2137 r4 contains n, r5 contains src, and r6 contains dst.
2138 The 16-bit displacement operand is added to the pc
2139 if and only if the end of string is reached before
2140 n bytes are transferred. */
2142 ea
= GET_L_REG (4) & 0xffff;
2148 rd
= GET_MEMORY_B (GET_L_REG (5));
2149 SET_MEMORY_B (GET_L_REG (6), rd
);
2150 SET_L_REG (5, GET_L_REG (5) + 1);
2151 SET_L_REG (6, GET_L_REG (6) + 1);
2158 case O (O_EEPMOV
, SB
): /* eepmov.b */
2159 case O (O_EEPMOV
, SW
): /* eepmov.w */
2160 if (h8300hmode
|| h8300smode
)
2162 register unsigned char *_src
, *_dst
;
2163 unsigned int count
= ((code
->opcode
== O (O_EEPMOV
, SW
))
2164 ? h8_get_reg (sd
, R4_REGNUM
) & 0xffff
2165 : h8_get_reg (sd
, R4_REGNUM
) & 0xff);
2167 _src
= (h8_get_reg (sd
, R5_REGNUM
) < memory_size
2168 ? h8_get_memory_buf (sd
) + h8_get_reg (sd
, R5_REGNUM
)
2169 : h8_get_eightbit_buf (sd
) +
2170 (h8_get_reg (sd
, R5_REGNUM
) & 0xff));
2171 if ((_src
+ count
) >= (h8_get_memory_buf (sd
) + memory_size
))
2173 if ((_src
+ count
) >= (h8_get_eightbit_buf (sd
) + 0x100))
2176 _dst
= (h8_get_reg (sd
, R6_REGNUM
) < memory_size
2177 ? h8_get_memory_buf (sd
) + h8_get_reg (sd
, R6_REGNUM
)
2178 : h8_get_eightbit_buf (sd
) +
2179 (h8_get_reg (sd
, R6_REGNUM
) & 0xff));
2181 if ((_dst
+ count
) >= (h8_get_memory_buf (sd
) + memory_size
))
2183 if ((_dst
+ count
) >= (h8_get_eightbit_buf (sd
) + 0x100))
2186 memcpy (_dst
, _src
, count
);
2188 h8_set_reg (sd
, R5_REGNUM
, h8_get_reg (sd
, R5_REGNUM
) + count
);
2189 h8_set_reg (sd
, R6_REGNUM
, h8_get_reg (sd
, R6_REGNUM
) + count
);
2190 h8_set_reg (sd
, R4_REGNUM
, h8_get_reg (sd
, R4_REGNUM
) &
2191 ((code
->opcode
== O (O_EEPMOV
, SW
))
2192 ? (~0xffff) : (~0xff)));
2193 cycles
+= 2 * count
;
2198 case O (O_ADDS
, SL
): /* adds (.l) */
2200 * This insn only uses register operands, but still
2201 * it would be cleaner to use fetch and store... */
2202 SET_L_REG (code
->dst
.reg
,
2203 GET_L_REG (code
->dst
.reg
)
2204 + code
->src
.literal
);
2208 case O (O_SUBS
, SL
): /* subs (.l) */
2210 * This insn only uses register operands, but still
2211 * it would be cleaner to use fetch and store... */
2212 SET_L_REG (code
->dst
.reg
,
2213 GET_L_REG (code
->dst
.reg
)
2214 - code
->src
.literal
);
2217 case O (O_CMP
, SB
): /* cmp.b */
2218 if (fetch (sd
, &code
->dst
, &rd
))
2220 if (fetch (sd
, &code
->src
, &ea
))
2224 goto just_flags_alu8
;
2226 case O (O_CMP
, SW
): /* cmp.w */
2227 if (fetch (sd
, &code
->dst
, &rd
))
2229 if (fetch (sd
, &code
->src
, &ea
))
2233 goto just_flags_alu16
;
2235 case O (O_CMP
, SL
): /* cmp.l */
2236 if (fetch (sd
, &code
->dst
, &rd
))
2238 if (fetch (sd
, &code
->src
, &ea
))
2242 goto just_flags_alu32
;
2244 case O (O_DEC
, SB
): /* dec.b */
2246 * This insn only uses register operands, but still
2247 * it would be cleaner to use fetch and store... */
2248 rd
= GET_B_REG (code
->src
.reg
);
2251 SET_B_REG (code
->src
.reg
, res
);
2252 goto just_flags_inc8
;
2254 case O (O_DEC
, SW
): /* dec.w */
2256 * This insn only uses register operands, but still
2257 * it would be cleaner to use fetch and store... */
2258 rd
= GET_W_REG (code
->dst
.reg
);
2259 ea
= -code
->src
.literal
;
2261 SET_W_REG (code
->dst
.reg
, res
);
2262 goto just_flags_inc16
;
2264 case O (O_DEC
, SL
): /* dec.l */
2266 * This insn only uses register operands, but still
2267 * it would be cleaner to use fetch and store... */
2268 rd
= GET_L_REG (code
->dst
.reg
);
2269 ea
= -code
->src
.literal
;
2271 SET_L_REG (code
->dst
.reg
, res
);
2272 goto just_flags_inc32
;
2274 case O (O_INC
, SB
): /* inc.b */
2276 * This insn only uses register operands, but still
2277 * it would be cleaner to use fetch and store... */
2278 rd
= GET_B_REG (code
->src
.reg
);
2281 SET_B_REG (code
->src
.reg
, res
);
2282 goto just_flags_inc8
;
2284 case O (O_INC
, SW
): /* inc.w */
2286 * This insn only uses register operands, but still
2287 * it would be cleaner to use fetch and store... */
2288 rd
= GET_W_REG (code
->dst
.reg
);
2289 ea
= code
->src
.literal
;
2291 SET_W_REG (code
->dst
.reg
, res
);
2292 goto just_flags_inc16
;
2294 case O (O_INC
, SL
): /* inc.l */
2296 * This insn only uses register operands, but still
2297 * it would be cleaner to use fetch and store... */
2298 rd
= GET_L_REG (code
->dst
.reg
);
2299 ea
= code
->src
.literal
;
2301 SET_L_REG (code
->dst
.reg
, res
);
2302 goto just_flags_inc32
;
2304 case O (O_LDC
, SB
): /* ldc.b */
2305 if (fetch (sd
, &code
->src
, &res
))
2309 case O (O_LDC
, SW
): /* ldc.w */
2310 if (fetch (sd
, &code
->src
, &res
))
2313 /* Word operand, value from MSB, must be shifted. */
2317 case O (O_LDC
, SL
): /* ldc.l */
2318 if (fetch (sd
, &code
->src
, &res
))
2320 switch (code
->dst
.type
) {
2321 case X (OP_SBR
, SL
):
2322 h8_set_sbr (sd
, res
);
2324 case X (OP_VBR
, SL
):
2325 h8_set_vbr (sd
, res
);
2332 case O (O_STC
, SW
): /* stc.w */
2333 case O (O_STC
, SB
): /* stc.b */
2334 if (code
->src
.type
== X (OP_CCR
, SB
))
2337 res
= h8_get_ccr (sd
);
2339 else if (code
->src
.type
== X (OP_EXR
, SB
) && h8300smode
)
2342 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2343 res
= h8_get_exr (sd
);
2348 /* Word operand, value to MSB, must be shifted. */
2349 if (code
->opcode
== X (O_STC
, SW
))
2351 if (store (sd
, &code
->dst
, res
))
2354 case O (O_STC
, SL
): /* stc.l */
2355 switch (code
->src
.type
) {
2356 case X (OP_SBR
, SL
):
2357 res
= h8_get_sbr (sd
);
2359 case X (OP_VBR
, SL
):
2360 res
= h8_get_vbr (sd
);
2365 if (store (sd
, &code
->dst
, res
))
2369 case O (O_ANDC
, SB
): /* andc.b */
2370 if (code
->dst
.type
== X (OP_CCR
, SB
))
2373 rd
= h8_get_ccr (sd
);
2375 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2378 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2379 rd
= h8_get_exr (sd
);
2383 ea
= code
->src
.literal
;
2387 case O (O_ORC
, SB
): /* orc.b */
2388 if (code
->dst
.type
== X (OP_CCR
, SB
))
2391 rd
= h8_get_ccr (sd
);
2393 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2396 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2397 rd
= h8_get_exr (sd
);
2401 ea
= code
->src
.literal
;
2405 case O (O_XORC
, SB
): /* xorc.b */
2406 if (code
->dst
.type
== X (OP_CCR
, SB
))
2409 rd
= h8_get_ccr (sd
);
2411 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2414 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2415 rd
= h8_get_exr (sd
);
2419 ea
= code
->src
.literal
;
2423 case O (O_BRAS
, SB
): /* bra/s */
2424 /* This is basically an ordinary branch, with a delay slot. */
2425 if (fetch (sd
, &code
->src
, &res
))
2433 /* Execution continues at next instruction, but
2434 delayed_branch is set up for next cycle. */
2435 h8_set_delayed_branch (sd
, code
->next_pc
+ res
);
2439 case O (O_BRAB
, SB
): /* bra rd.b */
2440 case O (O_BRAW
, SW
): /* bra rd.w */
2441 case O (O_BRAL
, SL
): /* bra erd.l */
2442 if (fetch (sd
, &code
->src
, &rd
))
2444 switch (OP_SIZE (code
->opcode
)) {
2445 case SB
: rd
&= 0xff; break;
2446 case SW
: rd
&= 0xffff; break;
2447 case SL
: rd
&= 0xffffffff; break;
2449 pc
= code
->next_pc
+ rd
;
2452 case O (O_BRABC
, SB
): /* bra/bc, branch if bit clear */
2453 case O (O_BRABS
, SB
): /* bra/bs, branch if bit set */
2454 case O (O_BSRBC
, SB
): /* bsr/bc, call if bit clear */
2455 case O (O_BSRBS
, SB
): /* bsr/bs, call if bit set */
2456 if (fetch (sd
, &code
->dst
, &rd
) ||
2457 fetch (sd
, &code
->src
, &bit
))
2460 if (code
->opcode
== O (O_BRABC
, SB
) || /* branch if clear */
2461 code
->opcode
== O (O_BSRBC
, SB
)) /* call if clear */
2463 if ((rd
& (1 << bit
))) /* no branch */
2466 else /* branch/call if set */
2468 if (!(rd
& (1 << bit
))) /* no branch */
2472 if (fetch (sd
, &code
->op3
, &res
)) /* branch */
2474 pc
= code
->next_pc
+ res
;
2476 if (code
->opcode
== O (O_BRABC
, SB
) ||
2477 code
->opcode
== O (O_BRABS
, SB
)) /* branch */
2485 case O (O_BRA
, SB
): /* bra, branch always */
2490 case O (O_BRN
, SB
): /* brn, ;-/ branch never? */
2495 case O (O_BHI
, SB
): /* bhi */
2501 case O (O_BLS
, SB
): /* bls */
2506 case O (O_BCS
, SB
): /* bcs, branch if carry set */
2511 case O (O_BCC
, SB
): /* bcc, branch if carry clear */
2516 case O (O_BEQ
, SB
): /* beq, branch if zero set */
2520 case O (O_BGT
, SB
): /* bgt */
2521 if (((Z
|| (N
^ V
)) == 0))
2525 case O (O_BLE
, SB
): /* ble */
2526 if (((Z
|| (N
^ V
)) == 1))
2530 case O (O_BGE
, SB
): /* bge */
2534 case O (O_BLT
, SB
): /* blt */
2538 case O (O_BMI
, SB
): /* bmi */
2542 case O (O_BNE
, SB
): /* bne, branch if zero clear */
2547 case O (O_BPL
, SB
): /* bpl */
2551 case O (O_BVC
, SB
): /* bvc */
2555 case O (O_BVS
, SB
): /* bvs */
2560 /* Trap for Command Line setup. */
2561 case O (O_SYS_CMDLINE
, SB
):
2563 int i
= 0; /* Loop counter. */
2564 int j
= 0; /* Loop counter. */
2565 int ind_arg_len
= 0; /* Length of each argument. */
2566 int no_of_args
= 0; /* The no. or cmdline args. */
2567 int current_location
= 0; /* Location of string. */
2568 int old_sp
= 0; /* The Initial Stack Pointer. */
2569 int no_of_slots
= 0; /* No. of slots required on the stack
2570 for storing cmdline args. */
2571 int sp_move
= 0; /* No. of locations by which the stack needs
2573 int new_sp
= 0; /* The final stack pointer location passed
2575 int *argv_ptrs
; /* Pointers of argv strings to be stored. */
2576 int argv_ptrs_location
= 0; /* Location of pointers to cmdline
2577 args on the stack. */
2578 int char_ptr_size
= 0; /* Size of a character pointer on
2580 int addr_cmdline
= 0; /* Memory location where cmdline has
2582 int size_cmdline
= 0; /* Size of cmdline. */
2584 /* Set the address of 256 free locations where command line is
2586 addr_cmdline
= cmdline_location();
2587 h8_set_reg (sd
, 0, addr_cmdline
);
2589 /* Counting the no. of commandline arguments. */
2590 for (i
= 0; h8_get_cmdline_arg (sd
, i
) != NULL
; i
++)
2593 /* No. of arguments in the command line. */
2596 /* Current location is just a temporary variable,which we are
2597 setting to the point to the start of our commandline string. */
2598 current_location
= addr_cmdline
;
2600 /* Allocating space for storing pointers of the command line
2602 argv_ptrs
= (int *) malloc (sizeof (int) * no_of_args
);
2604 /* Setting char_ptr_size to the sizeof (char *) on the different
2606 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2615 for (i
= 0; i
< no_of_args
; i
++)
2619 /* The size of the commandline argument. */
2620 ind_arg_len
= strlen (h8_get_cmdline_arg (sd
, i
)) + 1;
2622 /* The total size of the command line string. */
2623 size_cmdline
+= ind_arg_len
;
2625 /* As we have only 256 bytes, we need to provide a graceful
2626 exit. Anyways, a program using command line arguments
2627 where we cannot store all the command line arguments
2628 given may behave unpredictably. */
2629 if (size_cmdline
>= 256)
2631 h8_set_reg (sd
, 0, 0);
2636 /* current_location points to the memory where the next
2637 commandline argument is stored. */
2638 argv_ptrs
[i
] = current_location
;
2639 for (j
= 0; j
< ind_arg_len
; j
++)
2641 SET_MEMORY_B ((current_location
+
2642 (sizeof (char) * j
)),
2643 *(h8_get_cmdline_arg (sd
, i
) +
2644 sizeof (char) * j
));
2647 /* Setting current_location to the starting of next
2649 current_location
+= ind_arg_len
;
2653 /* This is the original position of the stack pointer. */
2654 old_sp
= h8_get_reg (sd
, SP_REGNUM
);
2656 /* We need space from the stack to store the pointers to argvs. */
2657 /* As we will infringe on the stack, we need to shift the stack
2658 pointer so that the data is not overwritten. We calculate how
2659 much space is required. */
2660 sp_move
= (no_of_args
) * (char_ptr_size
);
2662 /* The final position of stack pointer, we have thus taken some
2663 space from the stack. */
2664 new_sp
= old_sp
- sp_move
;
2666 /* Temporary variable holding value where the argv pointers need
2668 argv_ptrs_location
= new_sp
;
2670 /* The argv pointers are stored at sequential locations. As per
2672 for (i
= 0; i
< no_of_args
; i
++)
2674 /* Saving the argv pointer. */
2675 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2677 SET_MEMORY_L (argv_ptrs_location
, argv_ptrs
[i
]);
2681 SET_MEMORY_W (argv_ptrs_location
, argv_ptrs
[i
]);
2684 /* The next location where the pointer to the next argv
2685 string has to be stored. */
2686 argv_ptrs_location
+= char_ptr_size
;
2689 /* Required by POSIX, Setting 0x0 at the end of the list of argv
2691 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2693 SET_MEMORY_L (old_sp
, 0x0);
2697 SET_MEMORY_W (old_sp
, 0x0);
2700 /* Freeing allocated memory. */
2702 for (i
= 0; i
<= no_of_args
; i
++)
2704 free (h8_get_cmdline_arg (sd
, i
));
2706 free (h8_get_command_line (sd
));
2708 /* The no. of argv arguments are returned in Reg 0. */
2709 h8_set_reg (sd
, 0, no_of_args
);
2710 /* The Pointer to argv in Register 1. */
2711 h8_set_reg (sd
, 1, new_sp
);
2712 /* Setting the stack pointer to the new value. */
2713 h8_set_reg (sd
, SP_REGNUM
, new_sp
);
2717 /* System call processing starts. */
2718 case O (O_SYS_OPEN
, SB
):
2720 int len
= 0; /* Length of filename. */
2721 char *filename
; /* Filename would go here. */
2722 char temp_char
; /* Temporary character */
2723 int mode
= 0; /* Mode bits for the file. */
2724 int open_return
; /* Return value of open, file descriptor. */
2725 int i
; /* Loop counter */
2726 int filename_ptr
; /* Pointer to filename in cpu memory. */
2728 /* Setting filename_ptr to first argument of open, */
2729 /* and trying to get mode. */
2730 if ((h8300sxmode
|| h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2732 filename_ptr
= GET_L_REG (0);
2733 mode
= GET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
) + 4);
2737 filename_ptr
= GET_W_REG (0);
2738 mode
= GET_MEMORY_W (h8_get_reg (sd
, SP_REGNUM
) + 2);
2741 /* Trying to find the length of the filename. */
2742 temp_char
= GET_MEMORY_B (h8_get_reg (sd
, 0));
2745 while (temp_char
!= '\0')
2747 temp_char
= GET_MEMORY_B (filename_ptr
+ len
);
2751 /* Allocating space for the filename. */
2752 filename
= (char *) malloc (sizeof (char) * len
);
2754 /* String copying the filename from memory. */
2755 for (i
= 0; i
< len
; i
++)
2757 temp_char
= GET_MEMORY_B (filename_ptr
+ i
);
2758 filename
[i
] = temp_char
;
2761 /* Callback to open and return the file descriptor. */
2762 open_return
= sim_callback
->open (sim_callback
, filename
, mode
);
2764 /* Return value in register 0. */
2765 h8_set_reg (sd
, 0, open_return
);
2767 /* Freeing memory used for filename. */
2772 case O (O_SYS_READ
, SB
):
2774 char *char_ptr
; /* Where characters read would be stored. */
2775 int fd
; /* File descriptor */
2776 int buf_size
; /* BUF_SIZE parameter in read. */
2777 int i
= 0; /* Temporary Loop counter */
2778 int read_return
= 0; /* Return value from callback to
2781 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2782 buf_size
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2784 char_ptr
= (char *) malloc (sizeof (char) * buf_size
);
2786 /* Callback to read and return the no. of characters read. */
2788 sim_callback
->read (sim_callback
, fd
, char_ptr
, buf_size
);
2790 /* The characters read are stored in cpu memory. */
2791 for (i
= 0; i
< buf_size
; i
++)
2793 SET_MEMORY_B ((h8_get_reg (sd
, 1) + (sizeof (char) * i
)),
2794 *(char_ptr
+ (sizeof (char) * i
)));
2797 /* Return value in Register 0. */
2798 h8_set_reg (sd
, 0, read_return
);
2800 /* Freeing memory used as buffer. */
2805 case O (O_SYS_WRITE
, SB
):
2807 int fd
; /* File descriptor */
2808 char temp_char
; /* Temporary character */
2809 int len
; /* Length of write, Parameter II to write. */
2810 int char_ptr
; /* Character Pointer, Parameter I of write. */
2811 char *ptr
; /* Where characters to be written are stored.
2813 int write_return
; /* Return value from callback to write. */
2814 int i
= 0; /* Loop counter */
2816 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2817 char_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2818 len
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2820 /* Allocating space for the characters to be written. */
2821 ptr
= (char *) malloc (sizeof (char) * len
);
2823 /* Fetching the characters from cpu memory. */
2824 for (i
= 0; i
< len
; i
++)
2826 temp_char
= GET_MEMORY_B (char_ptr
+ i
);
2830 /* Callback write and return the no. of characters written. */
2831 write_return
= sim_callback
->write (sim_callback
, fd
, ptr
, len
);
2833 /* Return value in Register 0. */
2834 h8_set_reg (sd
, 0, write_return
);
2836 /* Freeing memory used as buffer. */
2841 case O (O_SYS_LSEEK
, SB
):
2843 int fd
; /* File descriptor */
2844 int offset
; /* Offset */
2845 int origin
; /* Origin */
2846 int lseek_return
; /* Return value from callback to lseek. */
2848 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2849 offset
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2850 origin
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2852 /* Callback lseek and return offset. */
2854 sim_callback
->lseek (sim_callback
, fd
, offset
, origin
);
2856 /* Return value in register 0. */
2857 h8_set_reg (sd
, 0, lseek_return
);
2861 case O (O_SYS_CLOSE
, SB
):
2863 int fd
; /* File descriptor */
2864 int close_return
; /* Return value from callback to close. */
2866 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2868 /* Callback close and return. */
2869 close_return
= sim_callback
->close (sim_callback
, fd
);
2871 /* Return value in register 0. */
2872 h8_set_reg (sd
, 0, close_return
);
2876 case O (O_SYS_FSTAT
, SB
):
2878 int fd
; /* File descriptor */
2879 struct stat stat_rec
; /* Stat record */
2880 int fstat_return
; /* Return value from callback to stat. */
2881 int stat_ptr
; /* Pointer to stat record. */
2882 char *temp_stat_ptr
; /* Temporary stat_rec pointer. */
2884 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2886 /* Setting stat_ptr to second argument of stat. */
2887 stat_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2889 /* Callback stat and return. */
2890 fstat_return
= sim_callback
->to_fstat (sim_callback
, fd
,
2893 /* Have stat_ptr point to starting of stat_rec. */
2894 temp_stat_ptr
= (char *) (&stat_rec
);
2896 /* Setting up the stat structure returned. */
2897 SET_MEMORY_W (stat_ptr
, stat_rec
.st_dev
);
2899 SET_MEMORY_W (stat_ptr
, stat_rec
.st_ino
);
2901 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mode
);
2903 SET_MEMORY_W (stat_ptr
, stat_rec
.st_nlink
);
2905 SET_MEMORY_W (stat_ptr
, stat_rec
.st_uid
);
2907 SET_MEMORY_W (stat_ptr
, stat_rec
.st_gid
);
2909 SET_MEMORY_W (stat_ptr
, stat_rec
.st_rdev
);
2911 SET_MEMORY_L (stat_ptr
, stat_rec
.st_size
);
2913 SET_MEMORY_L (stat_ptr
, stat_rec
.st_atime
);
2915 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mtime
);
2917 SET_MEMORY_L (stat_ptr
, stat_rec
.st_ctime
);
2919 /* Return value in register 0. */
2920 h8_set_reg (sd
, 0, fstat_return
);
2924 case O (O_SYS_STAT
, SB
):
2926 int len
= 0; /* Length of filename. */
2927 char *filename
; /* Filename would go here. */
2928 char temp_char
; /* Temporary character */
2929 int filename_ptr
; /* Pointer to filename in cpu memory. */
2930 struct stat stat_rec
; /* Stat record */
2931 int stat_return
; /* Return value from callback to stat */
2932 int stat_ptr
; /* Pointer to stat record. */
2933 char *temp_stat_ptr
; /* Temporary stat_rec pointer. */
2934 int i
= 0; /* Loop Counter */
2936 /* Setting filename_ptr to first argument of open. */
2937 filename_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2939 /* Trying to find the length of the filename. */
2940 temp_char
= GET_MEMORY_B (h8_get_reg (sd
, 0));
2943 while (temp_char
!= '\0')
2945 temp_char
= GET_MEMORY_B (filename_ptr
+ len
);
2949 /* Allocating space for the filename. */
2950 filename
= (char *) malloc (sizeof (char) * len
);
2952 /* String copying the filename from memory. */
2953 for (i
= 0; i
< len
; i
++)
2955 temp_char
= GET_MEMORY_B (filename_ptr
+ i
);
2956 filename
[i
] = temp_char
;
2959 /* Setting stat_ptr to second argument of stat. */
2960 /* stat_ptr = h8_get_reg (sd, 1); */
2961 stat_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2963 /* Callback stat and return. */
2965 sim_callback
->to_stat (sim_callback
, filename
, &stat_rec
);
2967 /* Have stat_ptr point to starting of stat_rec. */
2968 temp_stat_ptr
= (char *) (&stat_rec
);
2970 /* Freeing memory used for filename. */
2973 /* Setting up the stat structure returned. */
2974 SET_MEMORY_W (stat_ptr
, stat_rec
.st_dev
);
2976 SET_MEMORY_W (stat_ptr
, stat_rec
.st_ino
);
2978 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mode
);
2980 SET_MEMORY_W (stat_ptr
, stat_rec
.st_nlink
);
2982 SET_MEMORY_W (stat_ptr
, stat_rec
.st_uid
);
2984 SET_MEMORY_W (stat_ptr
, stat_rec
.st_gid
);
2986 SET_MEMORY_W (stat_ptr
, stat_rec
.st_rdev
);
2988 SET_MEMORY_L (stat_ptr
, stat_rec
.st_size
);
2990 SET_MEMORY_L (stat_ptr
, stat_rec
.st_atime
);
2992 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mtime
);
2994 SET_MEMORY_L (stat_ptr
, stat_rec
.st_ctime
);
2996 /* Return value in register 0. */
2997 h8_set_reg (sd
, 0, stat_return
);
3000 /* End of system call processing. */
3002 case O (O_NOT
, SB
): /* not.b */
3003 if (fetch2 (sd
, &code
->src
, &rd
))
3009 case O (O_NOT
, SW
): /* not.w */
3010 if (fetch2 (sd
, &code
->src
, &rd
))
3016 case O (O_NOT
, SL
): /* not.l */
3017 if (fetch2 (sd
, &code
->src
, &rd
))
3023 case O (O_SHLL
, SB
): /* shll.b */
3024 case O (O_SHLR
, SB
): /* shlr.b */
3025 if (fetch2 (sd
, &code
->dst
, &rd
))
3028 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3029 ea
= 1; /* unary op */
3030 else /* binary op */
3031 fetch (sd
, &code
->src
, &ea
);
3033 if (code
->opcode
== O (O_SHLL
, SB
))
3036 c
= rd
& (0x80 >> (ea
- 1));
3042 c
= rd
& (1 << (ea
- 1));
3043 rd
= (unsigned char) rd
>> ea
;
3047 case O (O_SHLL
, SW
): /* shll.w */
3048 case O (O_SHLR
, SW
): /* shlr.w */
3049 if (fetch2 (sd
, &code
->dst
, &rd
))
3052 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3053 ea
= 1; /* unary op */
3055 fetch (sd
, &code
->src
, &ea
);
3057 if (code
->opcode
== O (O_SHLL
, SW
))
3060 c
= rd
& (0x8000 >> (ea
- 1));
3066 c
= rd
& (1 << (ea
- 1));
3067 rd
= (unsigned short) rd
>> ea
;
3071 case O (O_SHLL
, SL
): /* shll.l */
3072 case O (O_SHLR
, SL
): /* shlr.l */
3073 if (fetch2 (sd
, &code
->dst
, &rd
))
3076 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3077 ea
= 1; /* unary op */
3079 fetch (sd
, &code
->src
, &ea
);
3081 if (code
->opcode
== O (O_SHLL
, SL
))
3084 c
= rd
& (0x80000000 >> (ea
- 1));
3090 c
= rd
& (1 << (ea
- 1));
3091 rd
= (unsigned int) rd
>> ea
;
3095 case O (O_SHAL
, SB
):
3096 case O (O_SHAR
, SB
):
3097 if (fetch2 (sd
, &code
->dst
, &rd
))
3100 if (code
->src
.type
== X (OP_IMM
, SB
))
3101 fetch (sd
, &code
->src
, &ea
);
3105 if (code
->opcode
== O (O_SHAL
, SB
))
3107 c
= rd
& (0x80 >> (ea
- 1));
3108 res
= rd
>> (7 - ea
);
3109 v
= ((res
& 1) && !(res
& 2))
3110 || (!(res
& 1) && (res
& 2));
3115 c
= rd
& (1 << (ea
- 1));
3117 rd
= ((signed char) rd
) >> ea
;
3121 case O (O_SHAL
, SW
):
3122 case O (O_SHAR
, SW
):
3123 if (fetch2 (sd
, &code
->dst
, &rd
))
3126 if (code
->src
.type
== X (OP_IMM
, SW
))
3127 fetch (sd
, &code
->src
, &ea
);
3131 if (code
->opcode
== O (O_SHAL
, SW
))
3133 c
= rd
& (0x8000 >> (ea
- 1));
3134 res
= rd
>> (15 - ea
);
3135 v
= ((res
& 1) && !(res
& 2))
3136 || (!(res
& 1) && (res
& 2));
3141 c
= rd
& (1 << (ea
- 1));
3143 rd
= ((signed short) rd
) >> ea
;
3147 case O (O_SHAL
, SL
):
3148 case O (O_SHAR
, SL
):
3149 if (fetch2 (sd
, &code
->dst
, &rd
))
3152 if (code
->src
.type
== X (OP_IMM
, SL
))
3153 fetch (sd
, &code
->src
, &ea
);
3157 if (code
->opcode
== O (O_SHAL
, SL
))
3159 c
= rd
& (0x80000000 >> (ea
- 1));
3160 res
= rd
>> (31 - ea
);
3161 v
= ((res
& 1) && !(res
& 2))
3162 || (!(res
& 1) && (res
& 2));
3167 c
= rd
& (1 << (ea
- 1));
3169 rd
= ((signed int) rd
) >> ea
;
3173 case O (O_ROTL
, SB
):
3174 case O (O_ROTR
, SB
):
3175 if (fetch2 (sd
, &code
->dst
, &rd
))
3178 if (code
->src
.type
== X (OP_IMM
, SB
))
3179 fetch (sd
, &code
->src
, &ea
);
3184 if (code
->opcode
== O (O_ROTL
, SB
))
3194 rd
= ((unsigned char) rd
) >> 1;
3202 case O (O_ROTL
, SW
):
3203 case O (O_ROTR
, SW
):
3204 if (fetch2 (sd
, &code
->dst
, &rd
))
3207 if (code
->src
.type
== X (OP_IMM
, SW
))
3208 fetch (sd
, &code
->src
, &ea
);
3213 if (code
->opcode
== O (O_ROTL
, SW
))
3223 rd
= ((unsigned short) rd
) >> 1;
3231 case O (O_ROTL
, SL
):
3232 case O (O_ROTR
, SL
):
3233 if (fetch2 (sd
, &code
->dst
, &rd
))
3236 if (code
->src
.type
== X (OP_IMM
, SL
))
3237 fetch (sd
, &code
->src
, &ea
);
3242 if (code
->opcode
== O (O_ROTL
, SL
))
3244 c
= rd
& 0x80000000;
3252 rd
= ((unsigned int) rd
) >> 1;
3260 case O (O_ROTXL
, SB
):
3261 case O (O_ROTXR
, SB
):
3262 if (fetch2 (sd
, &code
->dst
, &rd
))
3265 if (code
->src
.type
== X (OP_IMM
, SB
))
3266 fetch (sd
, &code
->src
, &ea
);
3271 if (code
->opcode
== O (O_ROTXL
, SB
))
3282 rd
= ((unsigned char) rd
) >> 1;
3291 case O (O_ROTXL
, SW
):
3292 case O (O_ROTXR
, SW
):
3293 if (fetch2 (sd
, &code
->dst
, &rd
))
3296 if (code
->src
.type
== X (OP_IMM
, SW
))
3297 fetch (sd
, &code
->src
, &ea
);
3302 if (code
->opcode
== O (O_ROTXL
, SW
))
3313 rd
= ((unsigned short) rd
) >> 1;
3322 case O (O_ROTXL
, SL
):
3323 case O (O_ROTXR
, SL
):
3324 if (fetch2 (sd
, &code
->dst
, &rd
))
3327 if (code
->src
.type
== X (OP_IMM
, SL
))
3328 fetch (sd
, &code
->src
, &ea
);
3333 if (code
->opcode
== O (O_ROTXL
, SL
))
3335 res
= rd
& 0x80000000;
3344 rd
= ((unsigned int) rd
) >> 1;
3355 case O (O_JMP
, SB
): /* jmp */
3357 fetch (sd
, &code
->src
, &pc
);
3362 case O (O_JSR
, SB
): /* jsr, jump to subroutine */
3364 if (fetch (sd
, &code
->src
, &pc
))
3367 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3369 if (h8300hmode
&& !h8300_normal_mode
)
3372 SET_MEMORY_L (tmp
, code
->next_pc
);
3377 SET_MEMORY_W (tmp
, code
->next_pc
);
3379 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3385 case O (O_BSR
, SB
): /* bsr, branch to subroutine */
3386 if (fetch (sd
, &code
->src
, &res
))
3388 pc
= code
->next_pc
+ res
;
3391 case O (O_RTE
, SN
): /* rte, return from exception */
3393 /* Pops exr and ccr before pc -- otherwise identical to rts. */
3394 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3396 if (h8300smode
) /* pop exr */
3398 h8_set_exr (sd
, GET_MEMORY_L (tmp
));
3401 if (h8300hmode
&& !h8300_normal_mode
)
3403 h8_set_ccr (sd
, GET_MEMORY_L (tmp
));
3405 pc
= GET_MEMORY_L (tmp
);
3410 h8_set_ccr (sd
, GET_MEMORY_W (tmp
));
3412 pc
= GET_MEMORY_W (tmp
);
3417 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3420 case O (O_RTS
, SN
): /* rts, return from subroutine */
3422 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3424 if (h8300hmode
&& !h8300_normal_mode
)
3426 pc
= GET_MEMORY_L (tmp
);
3431 pc
= GET_MEMORY_W (tmp
);
3435 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3438 case O (O_ILL
, SB
): /* illegal */
3439 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGILL
);
3442 case O (O_SLEEP
, SN
): /* sleep */
3443 /* Check for magic numbers in r1 and r2. */
3444 if ((h8_get_reg (sd
, R1_REGNUM
) & 0xffff) == LIBC_EXIT_MAGIC1
&&
3445 (h8_get_reg (sd
, R2_REGNUM
) & 0xffff) == LIBC_EXIT_MAGIC2
&&
3446 SIM_WIFEXITED (h8_get_reg (sd
, 0)))
3448 /* This trap comes from _exit, not from gdb. */
3449 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_exited
,
3450 SIM_WEXITSTATUS (h8_get_reg (sd
, 0)));
3453 /* Unfortunately this won't really work, because
3454 when we take a breakpoint trap, R0 has a "random",
3455 user-defined value. Don't see any immediate solution. */
3456 else if (SIM_WIFSTOPPED (h8_get_reg (sd
, 0)))
3458 /* Pass the stop signal up to gdb. */
3459 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
,
3460 SIM_WSTOPSIG (h8_get_reg (sd
, 0)));
3465 /* Treat it as a sigtrap. */
3466 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
3470 case O (O_TRAPA
, SB
): /* trapa */
3471 if (fetch (sd
, &code
->src
, &res
))
3472 goto end
; /* res is vector number. */
3474 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3475 if(h8300_normal_mode
)
3478 SET_MEMORY_W (tmp
, code
->next_pc
);
3480 SET_MEMORY_W (tmp
, h8_get_ccr (sd
));
3485 SET_MEMORY_L (tmp
, code
->next_pc
);
3487 SET_MEMORY_L (tmp
, h8_get_ccr (sd
));
3495 SET_MEMORY_L (tmp
, h8_get_exr (sd
));
3498 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3500 if(h8300_normal_mode
)
3501 pc
= GET_MEMORY_L (0x10 + res
* 2); /* Vector addresses are 0x10,0x12,0x14 and 0x16 */
3503 pc
= GET_MEMORY_L (0x20 + res
* 4);
3507 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
3510 case O (O_BSETEQ
, SB
):
3515 case O (O_BSETNE
, SB
):
3520 case O (O_BCLREQ
, SB
):
3525 case O (O_BCLRNE
, SB
):
3530 OBITOP (O_BNOT
, 1, 1, ea
^= m
); /* bnot */
3531 OBITOP (O_BTST
, 1, 0, nz
= ea
& m
); /* btst */
3533 OBITOP (O_BSET
, 1, 1, ea
|= m
); /* bset */
3535 OBITOP (O_BCLR
, 1, 1, ea
&= ~m
); /* bclr */
3536 OBITOP (O_BLD
, 1, 0, c
= ea
& m
); /* bld */
3537 OBITOP (O_BILD
, 1, 0, c
= !(ea
& m
)); /* bild */
3538 OBITOP (O_BST
, 1, 1, ea
&= ~m
;
3539 if (C
) ea
|= m
); /* bst */
3540 OBITOP (O_BIST
, 1, 1, ea
&= ~m
;
3541 if (!C
) ea
|= m
); /* bist */
3542 OBITOP (O_BSTZ
, 1, 1, ea
&= ~m
;
3543 if (Z
) ea
|= m
); /* bstz */
3544 OBITOP (O_BISTZ
, 1, 1, ea
&= ~m
;
3545 if (!Z
) ea
|= m
); /* bistz */
3546 OBITOP (O_BAND
, 1, 0, c
= (ea
& m
) && C
); /* band */
3547 OBITOP (O_BIAND
, 1, 0, c
= !(ea
& m
) && C
); /* biand */
3548 OBITOP (O_BOR
, 1, 0, c
= (ea
& m
) || C
); /* bor */
3549 OBITOP (O_BIOR
, 1, 0, c
= !(ea
& m
) || C
); /* bior */
3550 OBITOP (O_BXOR
, 1, 0, c
= ((ea
& m
) != 0)!= C
); /* bxor */
3551 OBITOP (O_BIXOR
, 1, 0, c
= !(ea
& m
) != C
); /* bixor */
3553 case O (O_BFLD
, SB
): /* bfld */
3556 if (fetch (sd
, &code
->src
, &bit
))
3561 if (fetch (sd
, &code
->dst
, &ea
))
3571 if (store (sd
, &code
->op3
, ea
))
3576 case O(O_BFST
, SB
): /* bfst */
3577 /* bitfield store */
3578 /* NOTE: the imm8 value is in dst, and the ea value
3579 (which is actually the destination) is in op3.
3580 It has to be that way, to avoid breaking the assembler. */
3582 if (fetch (sd
, &code
->dst
, &bit
)) /* imm8 */
3584 if (bit
== 0) /* noop -- nothing to do. */
3587 if (fetch (sd
, &code
->src
, &rd
)) /* reg8 src */
3590 if (fetch2 (sd
, &code
->op3
, &ea
)) /* ea dst */
3593 /* Left-shift the register data into position. */
3594 for (tmp
= bit
; !(tmp
& 1); tmp
>>= 1)
3597 /* Combine it with the neighboring bits. */
3598 ea
= (ea
& ~bit
) | (rd
& bit
);
3601 if (store2 (sd
, &code
->op3
, ea
))
3605 case O (O_CLRMAC
, SN
): /* clrmac */
3606 h8_set_mach (sd
, 0);
3607 h8_set_macl (sd
, 0);
3608 h8_set_macZ (sd
, 1);
3609 h8_set_macV (sd
, 0);
3610 h8_set_macN (sd
, 0);
3613 case O (O_STMAC
, SL
): /* stmac, 260 */
3614 switch (code
->src
.type
) {
3615 case X (OP_MACH
, SL
):
3616 res
= h8_get_mach (sd
);
3617 if (res
& 0x200) /* sign extend */
3620 case X (OP_MACL
, SL
):
3621 res
= h8_get_macl (sd
);
3623 default: goto illegal
;
3625 nz
= !h8_get_macZ (sd
);
3626 n
= h8_get_macN (sd
);
3627 v
= h8_get_macV (sd
);
3629 if (store (sd
, &code
->dst
, res
))
3634 case O (O_LDMAC
, SL
): /* ldmac, 179 */
3635 if (fetch (sd
, &code
->src
, &rd
))
3638 switch (code
->dst
.type
) {
3639 case X (OP_MACH
, SL
):
3640 rd
&= 0x3ff; /* Truncate to 10 bits */
3641 h8_set_mach (sd
, rd
);
3643 case X (OP_MACL
, SL
):
3644 h8_set_macl (sd
, rd
);
3646 default: goto illegal
;
3648 h8_set_macV (sd
, 0);
3652 if (fetch (sd
, &code
->src
, &rd
) ||
3653 fetch (sd
, &code
->dst
, &res
))
3656 /* Ye gods, this is non-portable!
3657 However, the existing mul/div code is similar. */
3658 res
= SEXTSHORT (res
) * SEXTSHORT (rd
);
3660 if (h8_get_macS (sd
)) /* Saturating mode */
3662 long long mac
= h8_get_macl (sd
);
3664 if (mac
& 0x80000000) /* sign extend */
3665 mac
|= 0xffffffff00000000LL
;
3668 if (mac
> 0x7fffffff || mac
< 0xffffffff80000000LL
)
3669 h8_set_macV (sd
, 1);
3670 h8_set_macZ (sd
, (mac
== 0));
3671 h8_set_macN (sd
, (mac
< 0));
3672 h8_set_macl (sd
, (int) mac
);
3674 else /* "Less Saturating" mode */
3676 long long mac
= h8_get_mach (sd
);
3678 mac
+= h8_get_macl (sd
);
3680 if (mac
& 0x20000000000LL
) /* sign extend */
3681 mac
|= 0xfffffc0000000000LL
;
3684 if (mac
> 0x1ffffffffffLL
||
3685 mac
< (long long) 0xfffffe0000000000LL
)
3686 h8_set_macV (sd
, 1);
3687 h8_set_macZ (sd
, (mac
== 0));
3688 h8_set_macN (sd
, (mac
< 0));
3689 h8_set_macl (sd
, (int) mac
);
3691 h8_set_mach (sd
, (int) (mac
& 0x3ff));
3695 case O (O_MULS
, SW
): /* muls.w */
3696 if (fetch (sd
, &code
->src
, &ea
) ||
3697 fetch (sd
, &code
->dst
, &rd
))
3700 ea
= SEXTSHORT (ea
);
3701 res
= SEXTSHORT (ea
* SEXTSHORT (rd
));
3705 if (store (sd
, &code
->dst
, res
))
3710 case O (O_MULS
, SL
): /* muls.l */
3711 if (fetch (sd
, &code
->src
, &ea
) ||
3712 fetch (sd
, &code
->dst
, &rd
))
3717 n
= res
& 0x80000000;
3718 nz
= res
& 0xffffffff;
3719 if (store (sd
, &code
->dst
, res
))
3723 case O (O_MULSU
, SL
): /* muls/u.l */
3724 if (fetch (sd
, &code
->src
, &ea
) ||
3725 fetch (sd
, &code
->dst
, &rd
))
3728 /* Compute upper 32 bits of the 64-bit result. */
3729 res
= (((long long) ea
) * ((long long) rd
)) >> 32;
3731 n
= res
& 0x80000000;
3732 nz
= res
& 0xffffffff;
3733 if (store (sd
, &code
->dst
, res
))
3737 case O (O_MULU
, SW
): /* mulu.w */
3738 if (fetch (sd
, &code
->src
, &ea
) ||
3739 fetch (sd
, &code
->dst
, &rd
))
3742 res
= UEXTSHORT ((UEXTSHORT (ea
) * UEXTSHORT (rd
)));
3744 /* Don't set Z or N. */
3745 if (store (sd
, &code
->dst
, res
))
3750 case O (O_MULU
, SL
): /* mulu.l */
3751 if (fetch (sd
, &code
->src
, &ea
) ||
3752 fetch (sd
, &code
->dst
, &rd
))
3757 /* Don't set Z or N. */
3758 if (store (sd
, &code
->dst
, res
))
3763 case O (O_MULUU
, SL
): /* mulu/u.l */
3764 if (fetch (sd
, &code
->src
, &ea
) ||
3765 fetch (sd
, &code
->dst
, &rd
))
3768 /* Compute upper 32 bits of the 64-bit result. */
3769 res
= (((unsigned long long) (unsigned) ea
) *
3770 ((unsigned long long) (unsigned) rd
)) >> 32;
3772 /* Don't set Z or N. */
3773 if (store (sd
, &code
->dst
, res
))
3778 case O (O_MULXS
, SB
): /* mulxs.b */
3779 if (fetch (sd
, &code
->src
, &ea
) ||
3780 fetch (sd
, &code
->dst
, &rd
))
3784 res
= ea
* SEXTCHAR (rd
);
3788 if (store (sd
, &code
->dst
, res
))
3793 case O (O_MULXS
, SW
): /* mulxs.w */
3794 if (fetch (sd
, &code
->src
, &ea
) ||
3795 fetch (sd
, &code
->dst
, &rd
))
3798 ea
= SEXTSHORT (ea
);
3799 res
= ea
* SEXTSHORT (rd
& 0xffff);
3801 n
= res
& 0x80000000;
3802 nz
= res
& 0xffffffff;
3803 if (store (sd
, &code
->dst
, res
))
3808 case O (O_MULXU
, SB
): /* mulxu.b */
3809 if (fetch (sd
, &code
->src
, &ea
) ||
3810 fetch (sd
, &code
->dst
, &rd
))
3813 res
= UEXTCHAR (ea
) * UEXTCHAR (rd
);
3815 if (store (sd
, &code
->dst
, res
))
3820 case O (O_MULXU
, SW
): /* mulxu.w */
3821 if (fetch (sd
, &code
->src
, &ea
) ||
3822 fetch (sd
, &code
->dst
, &rd
))
3825 res
= UEXTSHORT (ea
) * UEXTSHORT (rd
);
3827 if (store (sd
, &code
->dst
, res
))
3832 case O (O_TAS
, SB
): /* tas (test and set) */
3833 if (!h8300sxmode
) /* h8sx can use any register. */
3834 switch (code
->src
.reg
)
3845 if (fetch (sd
, &code
->src
, &res
))
3847 if (store (sd
, &code
->src
, res
| 0x80))
3850 goto just_flags_log8
;
3852 case O (O_DIVU
, SW
): /* divu.w */
3853 if (fetch (sd
, &code
->src
, &ea
) ||
3854 fetch (sd
, &code
->dst
, &rd
))
3860 res
= (unsigned) (UEXTSHORT (rd
) / UEXTSHORT (ea
));
3864 if (store (sd
, &code
->dst
, res
))
3868 case O (O_DIVU
, SL
): /* divu.l */
3869 if (fetch (sd
, &code
->src
, &ea
) ||
3870 fetch (sd
, &code
->dst
, &rd
))
3873 n
= ea
& 0x80000000;
3874 nz
= ea
& 0xffffffff;
3876 res
= (unsigned) rd
/ ea
;
3880 if (store (sd
, &code
->dst
, res
))
3884 case O (O_DIVS
, SW
): /* divs.w */
3885 if (fetch (sd
, &code
->src
, &ea
) ||
3886 fetch (sd
, &code
->dst
, &rd
))
3891 res
= SEXTSHORT (rd
) / SEXTSHORT (ea
);
3901 if (store (sd
, &code
->dst
, res
))
3905 case O (O_DIVS
, SL
): /* divs.l */
3906 if (fetch (sd
, &code
->src
, &ea
) ||
3907 fetch (sd
, &code
->dst
, &rd
))
3921 n
= res
& 0x80000000;
3922 if (store (sd
, &code
->dst
, res
))
3926 case O (O_DIVXU
, SB
): /* divxu.b */
3927 if (fetch (sd
, &code
->src
, &ea
) ||
3928 fetch (sd
, &code
->dst
, &rd
))
3931 rd
= UEXTSHORT (rd
);
3938 tmp
= (unsigned) rd
% ea
;
3939 res
= (unsigned) rd
/ ea
;
3947 if (store (sd
, &code
->dst
, (res
& 0xff) | (tmp
<< 8)))
3951 case O (O_DIVXU
, SW
): /* divxu.w */
3952 if (fetch (sd
, &code
->src
, &ea
) ||
3953 fetch (sd
, &code
->dst
, &rd
))
3956 ea
= UEXTSHORT (ea
);
3962 tmp
= (unsigned) rd
% ea
;
3963 res
= (unsigned) rd
/ ea
;
3971 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 16)))
3975 case O (O_DIVXS
, SB
): /* divxs.b */
3976 if (fetch (sd
, &code
->src
, &ea
) ||
3977 fetch (sd
, &code
->dst
, &rd
))
3980 rd
= SEXTSHORT (rd
);
3985 tmp
= (int) rd
% (int) ea
;
3986 res
= (int) rd
/ (int) ea
;
3997 if (store (sd
, &code
->dst
, (res
& 0xff) | (tmp
<< 8)))
4001 case O (O_DIVXS
, SW
): /* divxs.w */
4002 if (fetch (sd
, &code
->src
, &ea
) ||
4003 fetch (sd
, &code
->dst
, &rd
))
4006 ea
= SEXTSHORT (ea
);
4010 tmp
= (int) rd
% (int) ea
;
4011 res
= (int) rd
/ (int) ea
;
4021 n
= res
& 0x80000000;
4022 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 16)))
4026 case O (O_EXTS
, SW
): /* exts.w, signed extend */
4027 if (fetch2 (sd
, &code
->dst
, &rd
))
4029 ea
= rd
& 0x80 ? -256 : 0;
4030 res
= (rd
& 0xff) + ea
;
4033 case O (O_EXTS
, SL
): /* exts.l, signed extend */
4034 if (fetch2 (sd
, &code
->dst
, &rd
))
4036 if (code
->src
.type
== X (OP_IMM
, SL
))
4038 if (fetch (sd
, &code
->src
, &ea
))
4041 if (ea
== 2) /* exts.l #2, nn */
4043 /* Sign-extend from 8-bit to 32-bit. */
4044 ea
= rd
& 0x80 ? -256 : 0;
4045 res
= (rd
& 0xff) + ea
;
4049 /* Sign-extend from 16-bit to 32-bit. */
4050 ea
= rd
& 0x8000 ? -65536 : 0;
4051 res
= (rd
& 0xffff) + ea
;
4054 case O (O_EXTU
, SW
): /* extu.w, unsigned extend */
4055 if (fetch2 (sd
, &code
->dst
, &rd
))
4058 res
= (rd
& 0xff) + ea
;
4061 case O (O_EXTU
, SL
): /* extu.l, unsigned extend */
4062 if (fetch2 (sd
, &code
->dst
, &rd
))
4064 if (code
->src
.type
== X (OP_IMM
, SL
))
4066 if (fetch (sd
, &code
->src
, &ea
))
4069 if (ea
== 2) /* extu.l #2, nn */
4071 /* Zero-extend from 8-bit to 32-bit. */
4073 res
= (rd
& 0xff) + ea
;
4077 /* Zero-extend from 16-bit to 32-bit. */
4079 res
= (rd
& 0xffff) + ea
;
4082 case O (O_NOP
, SN
): /* nop */
4085 case O (O_STM
, SL
): /* stm, store to memory */
4087 int nregs
, firstreg
, i
;
4089 nregs
= GET_MEMORY_B (pc
+ 1);
4092 firstreg
= code
->src
.reg
;
4094 for (i
= firstreg
; i
<= firstreg
+ nregs
; i
++)
4096 h8_set_reg (sd
, SP_REGNUM
, h8_get_reg (sd
, SP_REGNUM
) - 4);
4097 SET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
), h8_get_reg (sd
, i
));
4102 case O (O_LDM
, SL
): /* ldm, load from memory */
4103 case O (O_RTEL
, SN
): /* rte/l, ldm plus rte */
4104 case O (O_RTSL
, SN
): /* rts/l, ldm plus rts */
4106 int nregs
, firstreg
, i
;
4108 nregs
= ((GET_MEMORY_B (pc
+ 1) >> 4) & 0xf);
4109 firstreg
= code
->dst
.reg
& 0xf;
4110 for (i
= firstreg
; i
>= firstreg
- nregs
; i
--)
4112 h8_set_reg (sd
, i
, GET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
)));
4113 h8_set_reg (sd
, SP_REGNUM
, h8_get_reg (sd
, SP_REGNUM
) + 4);
4116 switch (code
->opcode
) {
4117 case O (O_RTEL
, SN
):
4119 case O (O_RTSL
, SN
):
4128 /* Decimal Adjust Addition. This is for BCD arithmetic. */
4129 res
= GET_B_REG (code
->src
.reg
); /* FIXME fetch? */
4130 if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4131 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4132 res
= res
; /* Value added == 0. */
4133 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 8) &&
4134 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4135 res
= res
+ 0x6; /* Value added == 6. */
4136 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4137 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4138 res
= res
+ 0x6; /* Value added == 6. */
4139 else if (!c
&& (10 <= (res
>> 4) && (res
>> 4) <= 15) &&
4140 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4141 res
= res
+ 0x60; /* Value added == 60. */
4142 else if (!c
&& (9 <= (res
>> 4) && (res
>> 4) <= 15) &&
4143 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4144 res
= res
+ 0x66; /* Value added == 66. */
4145 else if (!c
&& (10 <= (res
>> 4) && (res
>> 4) <= 15) &&
4146 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4147 res
= res
+ 0x66; /* Value added == 66. */
4148 else if ( c
&& (1 <= (res
>> 4) && (res
>> 4) <= 2) &&
4149 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4150 res
= res
+ 0x60; /* Value added == 60. */
4151 else if ( c
&& (1 <= (res
>> 4) && (res
>> 4) <= 2) &&
4152 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4153 res
= res
+ 0x66; /* Value added == 66. */
4154 else if (c
&& (1 <= (res
>> 4) && (res
>> 4) <= 3) &&
4155 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4156 res
= res
+ 0x66; /* Value added == 66. */
4161 /* Decimal Adjust Subtraction. This is for BCD arithmetic. */
4162 res
= GET_B_REG (code
->src
.reg
); /* FIXME fetch, fetch2... */
4163 if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4164 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4165 res
= res
; /* Value added == 0. */
4166 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 8) &&
4167 h
&& (6 <= (res
& 0xf) && (res
& 0xf) <= 15))
4168 res
= res
+ 0xfa; /* Value added == 0xfa. */
4169 else if ( c
&& (7 <= (res
>> 4) && (res
>> 4) <= 15) &&
4170 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4171 res
= res
+ 0xa0; /* Value added == 0xa0. */
4172 else if (c
&& (6 <= (res
>> 4) && (res
>> 4) <= 15) &&
4173 h
&& (6 <= (res
& 0xf) && (res
& 0xf) <= 15))
4174 res
= res
+ 0x9a; /* Value added == 0x9a. */
4180 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGILL
);
4185 sim_io_printf (sd
, "sim_resume: internal error.\n");
4186 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGILL
);
4190 if (code
->dst
.type
== X (OP_CCR
, SB
) ||
4191 code
->dst
.type
== X (OP_CCR
, SW
))
4193 h8_set_ccr (sd
, res
);
4196 else if (h8300smode
&&
4197 (code
->dst
.type
== X (OP_EXR
, SB
) ||
4198 code
->dst
.type
== X (OP_EXR
, SW
)))
4200 h8_set_exr (sd
, res
);
4201 if (h8300smode
) /* Get exr. */
4203 trace
= (h8_get_exr (sd
) >> 7) & 1;
4204 intMask
= h8_get_exr (sd
) & 7;
4213 /* When a branch works */
4214 if (fetch (sd
, &code
->src
, &res
))
4216 if (res
& 1) /* bad address */
4218 pc
= code
->next_pc
+ res
;
4221 /* Set the cond codes from res */
4224 /* Set the flags after an 8 bit inc/dec operation */
4228 v
= (rd
& 0x7f) == 0x7f;
4231 /* Set the flags after an 16 bit inc/dec operation */
4235 v
= (rd
& 0x7fff) == 0x7fff;
4238 /* Set the flags after an 32 bit inc/dec operation */
4240 n
= res
& 0x80000000;
4241 nz
= res
& 0xffffffff;
4242 v
= (rd
& 0x7fffffff) == 0x7fffffff;
4246 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
4249 if (store2 (sd
, &code
->dst
, rd
))
4254 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
4257 if (store2 (sd
, &code
->dst
, rd
))
4262 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
4263 n
= (rd
& 0x80000000);
4264 nz
= rd
& 0xffffffff;
4265 if (store2 (sd
, &code
->dst
, rd
))
4270 if (store2 (sd
, &code
->dst
, res
))
4274 /* flags after a 32bit logical operation */
4275 n
= res
& 0x80000000;
4276 nz
= res
& 0xffffffff;
4281 if (store2 (sd
, &code
->dst
, res
))
4285 /* flags after a 16bit logical operation */
4292 if (store2 (sd
, &code
->dst
, res
))
4302 if (store2 (sd
, &code
->dst
, res
))
4309 switch (code
->opcode
/ 4)
4313 v
= ((rd
& 0x80) == (ea
& 0x80)
4314 && (rd
& 0x80) != (res
& 0x80));
4319 v
= ((rd
& 0x80) != (-ea
& 0x80)
4320 && (rd
& 0x80) != (res
& 0x80));
4327 break; /* No effect on v flag. */
4332 if (store2 (sd
, &code
->dst
, res
))
4338 c
= (res
& 0x10000);
4339 switch (code
->opcode
/ 4)
4343 v
= ((rd
& 0x8000) == (ea
& 0x8000)
4344 && (rd
& 0x8000) != (res
& 0x8000));
4349 v
= ((rd
& 0x8000) != (-ea
& 0x8000)
4350 && (rd
& 0x8000) != (res
& 0x8000));
4359 if (store2 (sd
, &code
->dst
, res
))
4363 n
= res
& 0x80000000;
4364 nz
= res
& 0xffffffff;
4365 switch (code
->opcode
/ 4)
4369 v
= ((rd
& 0x80000000) == (ea
& 0x80000000)
4370 && (rd
& 0x80000000) != (res
& 0x80000000));
4371 c
= ((unsigned) res
< (unsigned) rd
) ||
4372 ((unsigned) res
< (unsigned) ea
);
4377 v
= ((rd
& 0x80000000) != (-ea
& 0x80000000)
4378 && (rd
& 0x80000000) != (res
& 0x80000000));
4379 c
= (unsigned) rd
< (unsigned) -ea
;
4382 v
= (rd
== 0x80000000);
4389 if ((res
= h8_get_delayed_branch (sd
)) != 0)
4392 h8_set_delayed_branch (sd
, 0);
4400 h8_set_ticks (sd
, h8_get_ticks (sd
) + get_now () - tick_start
);
4401 h8_set_cycles (sd
, h8_get_cycles (sd
) + cycles
);
4402 h8_set_insts (sd
, h8_get_insts (sd
) + insts
);
4407 h8_set_exr (sd
, (trace
<<7) | intMask
);
4409 h8_set_mask (sd
, oldmask
);
4413 sim_engine_run (SIM_DESC sd
,
4414 int next_cpu_nr
, /* ignore */
4415 int nr_cpus
, /* ignore */
4420 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
4422 cpu
= STATE_CPU (sd
, 0);
4426 step_once (sd
, cpu
);
4427 if (sim_events_tick (sd
))
4428 sim_events_process (sd
);
4433 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
)
4440 for (i
= 0; i
< size
; i
++)
4442 if (addr
< memory_size
)
4444 h8_set_memory (sd
, addr
+ i
, buffer
[i
]);
4448 h8_set_eightbit (sd
, (addr
+ i
) & 0xff, buffer
[i
]);
4455 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
4460 if (addr
< memory_size
)
4461 memcpy (buffer
, h8_get_memory_buf (sd
) + addr
, size
);
4463 memcpy (buffer
, h8_get_eightbit_buf (sd
) + (addr
& 0xff), size
);
4468 h8300_reg_store (SIM_CPU
*cpu
, int rn
, unsigned char *value
, int length
)
4473 longval
= (value
[0] << 24) | (value
[1] << 16) | (value
[2] << 8) | value
[3];
4474 shortval
= (value
[0] << 8) | (value
[1]);
4475 intval
= h8300hmode
? longval
: shortval
;
4477 init_pointers (CPU_STATE (cpu
));
4481 if(h8300_normal_mode
)
4482 cpu
->pc
= shortval
; /* PC for Normal mode is 2 bytes */
4502 cpu
->regs
[rn
] = intval
;
4507 cpu
->regs
[rn
] = longval
;
4514 h8300_reg_fetch (SIM_CPU
*cpu
, int rn
, unsigned char *buf
, int length
)
4519 init_pointers (CPU_STATE (cpu
));
4521 if (!h8300smode
&& rn
>= EXR_REGNUM
)
4556 /* In Normal mode PC is 2 byte, but other registers are 4 byte */
4557 if ((h8300hmode
|| longreg
) && !(rn
== PC_REGNUM
&& h8300_normal_mode
))
4574 sim_info (SIM_DESC sd
, int verbose
)
4576 double timetaken
= (double) h8_get_ticks (sd
) / (double) now_persec ();
4577 double virttime
= h8_get_cycles (sd
) / 10.0e6
;
4579 sim_io_printf (sd
, "\n\n#instructions executed %10d\n", h8_get_insts (sd
));
4580 sim_io_printf (sd
, "#cycles (v approximate) %10d\n", h8_get_cycles (sd
));
4581 sim_io_printf (sd
, "#real time taken %10.4f\n", timetaken
);
4582 sim_io_printf (sd
, "#virtual time taken %10.4f\n", virttime
);
4583 if (timetaken
!= 0.0)
4584 sim_io_printf (sd
, "#simulation ratio %10.4f\n", virttime
/ timetaken
);
4587 /* This to be conditional on `what' (aka `verbose'),
4588 however it was never passed as non-zero. */
4592 for (i
= 0; i
< O_LAST
; i
++)
4594 if (h8_get_stats (sd
, i
))
4595 sim_io_printf (sd
, "%d: %d\n", i
, h8_get_stats (sd
, i
));
4601 /* Indicate whether the cpu is an H8/300 or H8/300H.
4602 FLAG is non-zero for the H8/300H. */
4605 set_h8300h (unsigned long machine
)
4607 /* FIXME: Much of the code in sim_load can be moved to sim_open.
4608 This function being replaced by a sim_open:ARGV configuration
4611 h8300hmode
= h8300smode
= h8300sxmode
= h8300_normal_mode
= 0;
4613 if (machine
== bfd_mach_h8300sx
|| machine
== bfd_mach_h8300sxn
)
4616 if (machine
== bfd_mach_h8300s
|| machine
== bfd_mach_h8300sn
|| h8300sxmode
)
4619 if (machine
== bfd_mach_h8300h
|| machine
== bfd_mach_h8300hn
|| h8300smode
)
4622 if(machine
== bfd_mach_h8300hn
|| machine
== bfd_mach_h8300sn
|| machine
== bfd_mach_h8300sxn
)
4623 h8300_normal_mode
= 1;
4626 /* H8300-specific options.
4627 TODO: These really should be merged into the common model modules. */
4635 h8300_option_handler (SIM_DESC sd
, sim_cpu
*cpu ATTRIBUTE_UNUSED
, int opt
,
4636 char *arg
, int is_command ATTRIBUTE_UNUSED
)
4638 switch ((H8300_OPTIONS
) opt
)
4641 set_h8300h (bfd_mach_h8300h
);
4644 set_h8300h (bfd_mach_h8300s
);
4646 case OPTION_H8300SX
:
4647 set_h8300h (bfd_mach_h8300sx
);
4651 /* We'll actually never get here; the caller handles the error
4653 sim_io_eprintf (sd
, "Unknown option `%s'\n", arg
);
4660 static const OPTION h8300_options
[] =
4662 { {"h8300h", no_argument
, NULL
, OPTION_H8300H
},
4663 'h', NULL
, "Indicate the CPU is H8/300H",
4664 h8300_option_handler
},
4665 { {"h8300s", no_argument
, NULL
, OPTION_H8300S
},
4666 'S', NULL
, "Indicate the CPU is H8S",
4667 h8300_option_handler
},
4668 { {"h8300sx", no_argument
, NULL
, OPTION_H8300SX
},
4669 'x', NULL
, "Indicate the CPU is H8SX",
4670 h8300_option_handler
},
4671 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
, NULL
}
4675 h8300_pc_get (sim_cpu
*cpu
)
4681 h8300_pc_set (sim_cpu
*cpu
, sim_cia pc
)
4686 /* Cover function of sim_state_free to free the cpu buffers as well. */
4689 free_state (SIM_DESC sd
)
4691 if (STATE_MODULES (sd
) != NULL
)
4692 sim_module_uninstall (sd
);
4694 /* Fixme: free buffers in _sim_cpu. */
4695 sim_state_free (sd
);
4699 sim_open (SIM_OPEN_KIND kind
,
4700 struct host_callback_struct
*callback
,
4708 sd
= sim_state_alloc (kind
, callback
);
4710 /* The cpu data is kept in a separately allocated chunk of memory. */
4711 if (sim_cpu_alloc_all (sd
, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK
)
4717 cpu
= STATE_CPU (sd
, 0);
4718 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
4719 cpu
->regs
[SBR_REGNUM
] = 0xFFFFFF00;
4720 /* sim_cpu object is new, so some initialization is needed. */
4721 init_pointers_needed
= 1;
4723 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
4729 if (sim_add_option_table (sd
, NULL
, h8300_options
) != SIM_RC_OK
)
4735 /* The parser will print an error message for us, so we silently return. */
4736 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
4738 /* Uninstall the modules to avoid memory leaks,
4739 file descriptor leaks, etc. */
4744 /* Check for/establish the a reference program image. */
4745 if (sim_analyze_program (sd
,
4746 (STATE_PROG_ARGV (sd
) != NULL
4747 ? *STATE_PROG_ARGV (sd
)
4748 : NULL
), abfd
) != SIM_RC_OK
)
4754 /* Establish any remaining configuration options. */
4755 if (sim_config (sd
) != SIM_RC_OK
)
4761 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
4763 /* Uninstall the modules to avoid memory leaks,
4764 file descriptor leaks, etc. */
4769 /* CPU specific initialization. */
4770 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
4772 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
4774 CPU_REG_FETCH (cpu
) = h8300_reg_fetch
;
4775 CPU_REG_STORE (cpu
) = h8300_reg_store
;
4776 CPU_PC_FETCH (cpu
) = h8300_pc_get
;
4777 CPU_PC_STORE (cpu
) = h8300_pc_set
;
4780 /* sim_hw_configure (sd); */
4782 /* FIXME: Much of the code in sim_load can be moved here. */
4787 /* Called by gdb to load a program into memory. */
4790 sim_load (SIM_DESC sd
, const char *prog
, bfd
*abfd
, int from_tty
)
4794 /* FIXME: The code below that sets a specific variant of the H8/300
4795 being simulated should be moved to sim_open(). */
4797 /* See if the file is for the H8/300 or H8/300H. */
4798 /* ??? This may not be the most efficient way. The z8k simulator
4799 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
4803 prog_bfd
= bfd_openr (prog
, NULL
);
4804 if (prog_bfd
!= NULL
)
4806 /* Set the cpu type. We ignore failure from bfd_check_format
4807 and bfd_openr as sim_load_file checks too. */
4808 if (bfd_check_format (prog_bfd
, bfd_object
))
4810 set_h8300h (bfd_get_mach (prog_bfd
));
4814 /* If we're using gdb attached to the simulator, then we have to
4815 reallocate memory for the simulator.
4817 When gdb first starts, it calls fetch_registers (among other
4818 functions), which in turn calls init_pointers, which allocates
4821 The problem is when we do that, we don't know whether we're
4822 debugging an H8/300 or H8/300H program.
4824 This is the first point at which we can make that determination,
4825 so we just reallocate memory now; this will also allow us to handle
4826 switching between H8/300 and H8/300H programs without exiting
4829 if (h8300smode
&& !h8300_normal_mode
)
4830 memory_size
= H8300S_MSIZE
;
4831 else if (h8300hmode
&& !h8300_normal_mode
)
4832 memory_size
= H8300H_MSIZE
;
4834 memory_size
= H8300_MSIZE
;
4836 if (h8_get_memory_buf (sd
))
4837 free (h8_get_memory_buf (sd
));
4838 if (h8_get_eightbit_buf (sd
))
4839 free (h8_get_eightbit_buf (sd
));
4841 h8_set_memory_buf (sd
, (unsigned char *)
4842 calloc (sizeof (char), memory_size
));
4843 sd
->memory_size
= memory_size
;
4844 h8_set_eightbit_buf (sd
, (unsigned char *) calloc (sizeof (char), 256));
4846 /* `msize' must be a power of two. */
4847 if ((memory_size
& (memory_size
- 1)) != 0)
4849 sim_io_printf (sd
, "sim_load: bad memory size.\n");
4852 h8_set_mask (sd
, memory_size
- 1);
4854 if (sim_load_file (sd
, STATE_MY_NAME (sd
), STATE_CALLBACK (sd
), prog
,
4855 prog_bfd
, STATE_OPEN_KIND (sd
) == SIM_OPEN_DEBUG
,
4859 /* Close the bfd if we opened it. */
4860 if (abfd
== NULL
&& prog_bfd
!= NULL
)
4861 bfd_close (prog_bfd
);
4865 /* Close the bfd if we opened it. */
4866 if (abfd
== NULL
&& prog_bfd
!= NULL
)
4867 bfd_close (prog_bfd
);
4872 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
,
4873 char * const *argv
, char * const *env
)
4880 h8_set_pc (sd
, bfd_get_start_address (abfd
));
4884 /* Command Line support. */
4887 /* Counting the no. of commandline arguments. */
4888 for (no_of_args
= 0; argv
[no_of_args
] != NULL
; no_of_args
++)
4891 /* Allocating memory for the argv pointers. */
4892 h8_set_command_line (sd
, (char **) malloc ((sizeof (char *))
4893 * (no_of_args
+ 1)));
4895 for (i
= 0; i
< no_of_args
; i
++)
4897 /* Copying the argument string. */
4898 h8_set_cmdline_arg (sd
, i
, (char *) strdup (argv
[i
]));
4900 h8_set_cmdline_arg (sd
, i
, NULL
);