2 * Simulator for the Hitachi H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
30 #ifdef HAVE_SYS_PARAM_H
31 #include <sys/param.h>
36 #include "remote-sim.h"
44 host_callback
*sim_callback
;
46 static SIM_OPEN_KIND sim_kind
;
49 /* FIXME: Needs to live in header file.
50 This header should also include the things in remote-sim.h.
51 One could move this to remote-sim.h but this function isn't needed
53 void sim_set_simcache_size
PARAMS ((int));
55 #define X(op, size) op * 4 + size
57 #define SP (h8300hmode ? SL : SW)
70 #define h8_opcodes ops
72 #include "opcode/h8300.h"
76 /* The rate at which to call the host's poll_quit callback. */
78 #define POLL_QUIT_INTERVAL 0x80000
80 #define LOW_BYTE(x) ((x) & 0xff)
81 #define HIGH_BYTE(x) (((x) >> 8) & 0xff)
82 #define P(X,Y) ((X << 8) | Y)
84 #define BUILDSR() cpu.ccr = (I << 7) | (UI << 6)| (H<<5) | (U<<4) | \
85 (N << 3) | (Z << 2) | (V<<1) | C;
88 c = (cpu.ccr >> 0) & 1;\
89 v = (cpu.ccr >> 1) & 1;\
90 nz = !((cpu.ccr >> 2) & 1);\
91 n = (cpu.ccr >> 3) & 1;\
92 u = (cpu.ccr >> 4) & 1;\
93 h = (cpu.ccr >> 5) & 1;\
94 ui = ((cpu.ccr >> 6) & 1);\
95 intMaskBit = (cpu.ccr >> 7) & 1;
97 #ifdef __CHAR_IS_SIGNED__
98 #define SEXTCHAR(x) ((char) (x))
102 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff): x & 0xff)
105 #define UEXTCHAR(x) ((x) & 0xff)
106 #define UEXTSHORT(x) ((x) & 0xffff)
107 #define SEXTSHORT(x) ((short) (x))
109 static cpu_state_type cpu
;
114 static int memory_size
;
119 return time (0); /* WinXX HAS UNIX like 'time', so why not using it? */
140 return h8300hmode
? SL
: SW
;
152 return X (OP_IMM
, SP
);
154 return X (OP_REG
, SP
);
157 return X (OP_MEM
, SP
);
160 abort (); /* ?? May be something more usefull? */
165 decode (addr
, data
, dst
)
183 /* Find the exact opcode/arg combo. */
184 for (q
= h8_opcodes
; q
->name
; q
++)
186 op_type
*nib
= q
->data
.nib
;
187 unsigned int len
= 0;
191 op_type looking_for
= *nib
;
192 int thisnib
= data
[len
>> 1];
194 thisnib
= (len
& 1) ? (thisnib
& 0xf) : ((thisnib
>> 4) & 0xf);
196 if (looking_for
< 16 && looking_for
>= 0)
198 if (looking_for
!= thisnib
)
203 if ((int) looking_for
& (int) B31
)
205 if (!(((int) thisnib
& 0x8) != 0))
208 looking_for
= (op_type
) ((int) looking_for
& ~(int) B31
);
212 if ((int) looking_for
& (int) B30
)
214 if (!(((int) thisnib
& 0x8) == 0))
217 looking_for
= (op_type
) ((int) looking_for
& ~(int) B30
);
220 if (looking_for
& DBIT
)
222 /* Exclude adds/subs by looking at bit 0 and 2, and
223 make sure the operand size, either w or l,
224 matches by looking at bit 1. */
225 if ((looking_for
& 7) != (thisnib
& 7))
228 abs
= (thisnib
& 0x8) ? 2 : 1;
230 else if (looking_for
& (REG
| IND
| INC
| DEC
))
232 if (looking_for
& REG
)
234 /* Can work out size from the register. */
235 size
= bitfrom (looking_for
);
237 if (looking_for
& SRC
)
242 else if (looking_for
& L_16
)
244 abs
= (data
[len
>> 1]) * 256 + data
[(len
+ 2) >> 1];
246 if (looking_for
& (PCREL
| DISP
))
251 else if (looking_for
& ABSJMP
)
253 abs
= (data
[1] << 16) | (data
[2] << 8) | (data
[3]);
255 else if (looking_for
& MEMIND
)
259 else if (looking_for
& L_32
)
263 abs
= (data
[i
] << 24)
264 | (data
[i
+ 1] << 16)
270 else if (looking_for
& L_24
)
274 abs
= (data
[i
] << 16) | (data
[i
+ 1] << 8) | (data
[i
+ 2]);
277 else if (looking_for
& IGNORE
)
281 else if (looking_for
& DISPREG
)
283 rdisp
= thisnib
& 0x7;
285 else if (looking_for
& KBIT
)
302 else if (looking_for
& L_8
)
306 if (looking_for
& PCREL
)
308 abs
= SEXTCHAR (data
[len
>> 1]);
310 else if (looking_for
& ABS8MEM
)
313 abs
= h8300hmode
? ~0xff0000ff : ~0xffff00ff;
314 abs
|= data
[len
>> 1] & 0xff;
318 abs
= data
[len
>> 1] & 0xff;
321 else if (looking_for
& L_3
)
327 else if (looking_for
== E
)
331 /* Fill in the args. */
333 op_type
*args
= q
->args
.nib
;
339 int rn
= (x
& DST
) ? rd
: rs
;
349 p
->type
= X (OP_IMM
, size
);
352 else if (x
& (IMM
| KBIT
| DBIT
))
354 p
->type
= X (OP_IMM
, size
);
360 Some ops (like mul) have two sizes. */
363 p
->type
= X (OP_REG
, size
);
368 p
->type
= X (OP_INC
, size
);
373 p
->type
= X (OP_DEC
, size
);
378 p
->type
= X (OP_DISP
, size
);
382 else if (x
& (ABS
| ABSJMP
| ABS8MEM
))
384 p
->type
= X (OP_DISP
, size
);
390 p
->type
= X (OP_MEM
, size
);
395 p
->type
= X (OP_PCREL
, size
);
396 p
->literal
= abs
+ addr
+ 2;
402 p
->type
= X (OP_IMM
, SP
);
407 p
->type
= X (OP_DISP
, size
);
409 p
->reg
= rdisp
& 0x7;
416 printf ("Hmmmm %x", x
);
422 /* But a jmp or a jsr gets automagically lvalued,
423 since we branch to their address not their
425 if (q
->how
== O (O_JSR
, SB
)
426 || q
->how
== O (O_JMP
, SB
))
428 dst
->src
.type
= lvalue (dst
->src
.type
, dst
->src
.reg
);
431 if (dst
->dst
.type
== -1)
434 dst
->opcode
= q
->how
;
435 dst
->cycles
= q
->time
;
437 /* And a jsr to 0xc4 is turned into a magic trap. */
439 if (dst
->opcode
== O (O_JSR
, SB
))
441 if (dst
->src
.literal
== 0xc4)
443 dst
->opcode
= O (O_SYSCALL
, SB
);
447 dst
->next_pc
= addr
+ len
/ 2;
451 printf ("Don't understand %x \n", looking_for
);
462 /* Fell off the end. */
463 dst
->opcode
= O (O_ILL
, SB
);
471 /* Find the next cache entry to use. */
472 idx
= cpu
.cache_top
+ 1;
474 if (idx
>= cpu
.csize
)
480 /* Throw away its old meaning. */
481 cpu
.cache_idx
[cpu
.cache
[idx
].oldpc
] = 0;
483 /* Set to new address. */
484 cpu
.cache
[idx
].oldpc
= pc
;
486 /* Fill in instruction info. */
487 decode (pc
, cpu
.memory
+ pc
, cpu
.cache
+ idx
);
489 /* Point to new cache entry. */
490 cpu
.cache_idx
[pc
] = idx
;
494 static unsigned char *breg
[18];
495 static unsigned short *wreg
[18];
496 static unsigned int *lreg
[18];
498 #define GET_B_REG(x) *(breg[x])
499 #define SET_B_REG(x,y) (*(breg[x])) = (y)
500 #define GET_W_REG(x) *(wreg[x])
501 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
503 #define GET_L_REG(x) *(lreg[x])
504 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
506 #define GET_MEMORY_L(x) \
508 ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \
509 | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \
510 : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \
511 | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff]))
513 #define GET_MEMORY_W(x) \
515 ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \
516 : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0)))
519 #define GET_MEMORY_B(x) \
520 (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff]))
522 #define SET_MEMORY_L(x,y) \
523 { register unsigned char *_p; register int __y = y; \
524 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
525 _p[0] = (__y)>>24; _p[1] = (__y)>>16; \
526 _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
528 #define SET_MEMORY_W(x,y) \
529 { register unsigned char *_p; register int __y = y; \
530 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
531 _p[0] = (__y)>>8; _p[1] =(__y);}
533 #define SET_MEMORY_B(x,y) \
534 (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y))
541 int abs
= arg
->literal
;
548 return GET_B_REG (rn
);
550 return GET_W_REG (rn
);
552 return GET_L_REG (rn
);
563 r
= GET_MEMORY_B (t
);
572 r
= GET_MEMORY_W (t
);
580 r
= GET_MEMORY_L (t
);
587 case X (OP_DISP
, SB
):
588 t
= GET_L_REG (rn
) + abs
;
590 return GET_MEMORY_B (t
);
592 case X (OP_DISP
, SW
):
593 t
= GET_L_REG (rn
) + abs
;
595 return GET_MEMORY_W (t
);
597 case X (OP_DISP
, SL
):
598 t
= GET_L_REG (rn
) + abs
;
600 return GET_MEMORY_L (t
);
603 t
= GET_MEMORY_L (abs
);
608 t
= GET_MEMORY_W (abs
);
613 abort (); /* ?? May be something more usefull? */
625 int abs
= arg
->literal
;
641 t
= GET_L_REG (rn
) - 1;
648 t
= (GET_L_REG (rn
) - 2) & cpu
.mask
;
654 t
= (GET_L_REG (rn
) - 4) & cpu
.mask
;
659 case X (OP_DISP
, SB
):
660 t
= GET_L_REG (rn
) + abs
;
665 case X (OP_DISP
, SW
):
666 t
= GET_L_REG (rn
) + abs
;
671 case X (OP_DISP
, SL
):
672 t
= GET_L_REG (rn
) + abs
;
708 memory_size
= H8300S_MSIZE
;
710 memory_size
= H8300H_MSIZE
;
712 memory_size
= H8300_MSIZE
;
713 cpu
.memory
= (unsigned char *) calloc (sizeof (char), memory_size
);
714 cpu
.cache_idx
= (unsigned short *) calloc (sizeof (short), memory_size
);
715 cpu
.eightbit
= (unsigned char *) calloc (sizeof (char), 256);
717 /* `msize' must be a power of two. */
718 if ((memory_size
& (memory_size
- 1)) != 0)
720 cpu
.mask
= memory_size
- 1;
722 for (i
= 0; i
< 9; i
++)
727 for (i
= 0; i
< 8; i
++)
729 unsigned char *p
= (unsigned char *) (cpu
.regs
+ i
);
730 unsigned char *e
= (unsigned char *) (cpu
.regs
+ i
+ 1);
731 unsigned short *q
= (unsigned short *) (cpu
.regs
+ i
);
732 unsigned short *u
= (unsigned short *) (cpu
.regs
+ i
+ 1);
733 cpu
.regs
[i
] = 0x00112233;
759 lreg
[i
] = &cpu
.regs
[i
];
762 lreg
[8] = &cpu
.regs
[8];
764 /* Initialize the seg registers. */
766 sim_set_simcache_size (CSIZE
);
771 control_c (sig
, code
, scp
, addr
)
777 cpu
.state
= SIM_STATE_STOPPED
;
778 cpu
.exception
= SIGINT
;
788 #define I (intMaskBit != 0)
791 mop (code
, bsize
, sign
)
804 bsize
? SEXTCHAR (GET_W_REG (code
->dst
.reg
)) :
805 SEXTSHORT (GET_W_REG (code
->dst
.reg
));
807 bsize
? SEXTCHAR (GET_B_REG (code
->src
.reg
)) :
808 SEXTSHORT (GET_W_REG (code
->src
.reg
));
812 multiplicand
= bsize
? UEXTCHAR (GET_W_REG (code
->dst
.reg
)) :
813 UEXTSHORT (GET_W_REG (code
->dst
.reg
));
815 bsize
? UEXTCHAR (GET_B_REG (code
->src
.reg
)) :
816 UEXTSHORT (GET_W_REG (code
->src
.reg
));
819 result
= multiplier
* multiplicand
;
823 n
= result
& (bsize
? 0x8000 : 0x80000000);
824 nz
= result
& (bsize
? 0xffff : 0xffffffff);
828 SET_W_REG (code
->dst
.reg
, result
);
832 SET_L_REG (code
->dst
.reg
, result
);
835 return ((n
== 1) << 1) | (nz
== 1);
839 #define ONOT(name, how) \
844 rd = GET_B_REG (code->src.reg); \
852 rd = GET_W_REG (code->src.reg); \
859 int hm = 0x80000000; \
860 rd = GET_L_REG (code->src.reg); \
865 #define OSHIFTS(name, how1, how2) \
870 rd = GET_B_REG (code->src.reg); \
871 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
885 rd = GET_W_REG (code->src.reg); \
886 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
899 int hm = 0x80000000; \
900 rd = GET_L_REG (code->src.reg); \
901 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
912 #define OBITOP(name,f, s, op) \
917 if (f) ea = fetch (&code->dst); \
918 m=1<< fetch(&code->src); \
920 if(s) store (&code->dst,ea); goto next; \
927 cpu
.state
= SIM_STATE_STOPPED
;
928 cpu
.exception
= SIGINT
;
933 sim_resume (sd
, step
, siggnal
)
939 int tick_start
= get_now ();
948 int c
, nz
, v
, n
, u
, h
, ui
, intMaskBit
;
952 prev
= signal (SIGINT
, control_c
);
956 cpu
.state
= SIM_STATE_STOPPED
;
957 cpu
.exception
= SIGTRAP
;
961 cpu
.state
= SIM_STATE_RUNNING
;
967 /* The PC should never be odd. */
981 cidx
= cpu
.cache_idx
[pc
];
982 code
= cpu
.cache
+ cidx
;
985 #define ALUOP(STORE, NAME, HOW) \
986 case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \
987 case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \
988 case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32;
991 #define LOGOP(NAME, HOW) \
992 case O(NAME,SB): HOW; goto log8;\
993 case O(NAME, SW): HOW; goto log16;\
994 case O(NAME,SL): HOW; goto log32;
1001 printf ("%x %d %s\n", pc
, code
->opcode
,
1002 code
->op
? code
->op
->name
: "**");
1004 cpu
.stats
[code
->opcode
]++;
1010 cycles
+= code
->cycles
;
1014 switch (code
->opcode
)
1018 * This opcode is a fake for when we get to an
1019 * instruction which hasnt been compiled
1026 case O (O_SUBX
, SB
):
1027 rd
= fetch (&code
->dst
);
1028 ea
= fetch (&code
->src
);
1033 case O (O_ADDX
, SB
):
1034 rd
= fetch (&code
->dst
);
1035 ea
= fetch (&code
->src
);
1040 #define EA ea = fetch(&code->src);
1041 #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst);
1043 ALUOP (1, O_SUB
, RD_EA
;
1046 ALUOP (1, O_NEG
, EA
;
1052 rd
= GET_B_REG (code
->dst
.reg
);
1053 ea
= fetch (&code
->src
);
1057 rd
= GET_W_REG (code
->dst
.reg
);
1058 ea
= fetch (&code
->src
);
1062 rd
= GET_L_REG (code
->dst
.reg
);
1063 ea
= fetch (&code
->src
);
1068 LOGOP (O_AND
, RD_EA
;
1074 LOGOP (O_XOR
, RD_EA
;
1078 case O (O_MOV_TO_MEM
, SB
):
1079 res
= GET_B_REG (code
->src
.reg
);
1081 case O (O_MOV_TO_MEM
, SW
):
1082 res
= GET_W_REG (code
->src
.reg
);
1084 case O (O_MOV_TO_MEM
, SL
):
1085 res
= GET_L_REG (code
->src
.reg
);
1089 case O (O_MOV_TO_REG
, SB
):
1090 res
= fetch (&code
->src
);
1091 SET_B_REG (code
->dst
.reg
, res
);
1092 goto just_flags_log8
;
1093 case O (O_MOV_TO_REG
, SW
):
1094 res
= fetch (&code
->src
);
1095 SET_W_REG (code
->dst
.reg
, res
);
1096 goto just_flags_log16
;
1097 case O (O_MOV_TO_REG
, SL
):
1098 res
= fetch (&code
->src
);
1099 SET_L_REG (code
->dst
.reg
, res
);
1100 goto just_flags_log32
;
1103 case O (O_ADDS
, SL
):
1104 SET_L_REG (code
->dst
.reg
,
1105 GET_L_REG (code
->dst
.reg
)
1106 + code
->src
.literal
);
1110 case O (O_SUBS
, SL
):
1111 SET_L_REG (code
->dst
.reg
,
1112 GET_L_REG (code
->dst
.reg
)
1113 - code
->src
.literal
);
1117 rd
= fetch (&code
->dst
);
1118 ea
= fetch (&code
->src
);
1121 goto just_flags_alu8
;
1124 rd
= fetch (&code
->dst
);
1125 ea
= fetch (&code
->src
);
1128 goto just_flags_alu16
;
1131 rd
= fetch (&code
->dst
);
1132 ea
= fetch (&code
->src
);
1135 goto just_flags_alu32
;
1139 rd
= GET_B_REG (code
->src
.reg
);
1142 SET_B_REG (code
->src
.reg
, res
);
1143 goto just_flags_inc8
;
1146 rd
= GET_W_REG (code
->dst
.reg
);
1147 ea
= -code
->src
.literal
;
1149 SET_W_REG (code
->dst
.reg
, res
);
1150 goto just_flags_inc16
;
1153 rd
= GET_L_REG (code
->dst
.reg
);
1154 ea
= -code
->src
.literal
;
1156 SET_L_REG (code
->dst
.reg
, res
);
1157 goto just_flags_inc32
;
1161 rd
= GET_B_REG (code
->src
.reg
);
1164 SET_B_REG (code
->src
.reg
, res
);
1165 goto just_flags_inc8
;
1168 rd
= GET_W_REG (code
->dst
.reg
);
1169 ea
= code
->src
.literal
;
1171 SET_W_REG (code
->dst
.reg
, res
);
1172 goto just_flags_inc16
;
1175 rd
= GET_L_REG (code
->dst
.reg
);
1176 ea
= code
->src
.literal
;
1178 SET_L_REG (code
->dst
.reg
, res
);
1179 goto just_flags_inc32
;
1182 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1184 case O (O_ANDC
, SB
):
1186 ea
= code
->src
.literal
;
1192 ea
= code
->src
.literal
;
1196 case O (O_XORC
, SB
):
1198 ea
= code
->src
.literal
;
1239 if (((Z
|| (N
^ V
)) == 0))
1245 if (((Z
|| (N
^ V
)) == 1))
1279 case O (O_SYSCALL
, SB
):
1281 char c
= cpu
.regs
[2];
1282 sim_callback
->write_stdout (sim_callback
, &c
, 1);
1286 ONOT (O_NOT
, rd
= ~rd
; v
= 0;);
1288 c
= rd
& hm
; v
= 0; rd
<<= 1,
1289 c
= rd
& (hm
>> 1); v
= 0; rd
<<= 2);
1291 c
= rd
& 1; v
= 0; rd
= (unsigned int) rd
>> 1,
1292 c
= rd
& 2; v
= 0; rd
= (unsigned int) rd
>> 2);
1294 c
= rd
& hm
; v
= (rd
& hm
) != ((rd
& (hm
>> 1)) << 1); rd
<<= 1,
1295 c
= rd
& (hm
>> 1); v
= (rd
& (hm
>> 1)) != ((rd
& (hm
>> 2)) << 2); rd
<<= 2);
1297 t
= rd
& hm
; c
= rd
& 1; v
= 0; rd
>>= 1; rd
|= t
,
1298 t
= rd
& hm
; c
= rd
& 2; v
= 0; rd
>>= 2; rd
|= t
| t
>> 1 );
1300 c
= rd
& hm
; v
= 0; rd
<<= 1; rd
|= C
,
1301 c
= rd
& hm
; v
= 0; rd
<<= 1; rd
|= C
; c
= rd
& hm
; rd
<<= 1; rd
|= C
);
1303 c
= rd
& 1; v
= 0; rd
= (unsigned int) rd
>> 1; if (c
) rd
|= hm
,
1304 c
= rd
& 1; v
= 0; rd
= (unsigned int) rd
>> 1; if (c
) rd
|= hm
; c
= rd
& 1; rd
= (unsigned int) rd
>> 1; if (c
) rd
|= hm
);
1306 t
= rd
& hm
; rd
<<= 1; rd
|= C
; c
= t
; v
= 0,
1307 t
= rd
& hm
; rd
<<= 1; rd
|= C
; c
= t
; v
= 0; t
= rd
& hm
; rd
<<= 1; rd
|= C
; c
= t
);
1309 t
= rd
& 1; rd
= (unsigned int) rd
>> 1; if (C
) rd
|= hm
; c
= t
; v
= 0,
1310 t
= rd
& 1; rd
= (unsigned int) rd
>> 1; if (C
) rd
|= hm
; c
= t
; v
= 0; t
= rd
& 1; rd
= (unsigned int) rd
>> 1; if (C
) rd
|= hm
; c
= t
);
1314 pc
= fetch (&code
->src
);
1322 pc
= fetch (&code
->src
);
1329 SET_MEMORY_L (tmp
, code
->next_pc
);
1334 SET_MEMORY_W (tmp
, code
->next_pc
);
1341 pc
= code
->src
.literal
;
1352 pc
= GET_MEMORY_L (tmp
);
1357 pc
= GET_MEMORY_W (tmp
);
1366 cpu
.state
= SIM_STATE_STOPPED
;
1367 cpu
.exception
= SIGILL
;
1369 case O (O_SLEEP
, SN
):
1370 /* FIXME: Doesn't this break for breakpoints when r0
1371 contains just the right (er, wrong) value? */
1372 cpu
.state
= SIM_STATE_STOPPED
;
1373 /* The format of r0 is defined by target newlib. Expand
1374 the macros here instead of looking for .../sys/wait.h. */
1375 #define SIM_WIFEXITED(v) (((v) & 0xff) == 0)
1376 #define SIM_WIFSIGNALED(v) (((v) & 0x7f) > 0 && (((v) & 0x7f) < 0x7f))
1377 if (! SIM_WIFEXITED (cpu
.regs
[0]) && SIM_WIFSIGNALED (cpu
.regs
[0]))
1378 cpu
.exception
= SIGILL
;
1380 cpu
.exception
= SIGTRAP
;
1383 cpu
.state
= SIM_STATE_STOPPED
;
1384 cpu
.exception
= SIGTRAP
;
1387 OBITOP (O_BNOT
, 1, 1, ea
^= m
);
1388 OBITOP (O_BTST
, 1, 0, nz
= ea
& m
);
1389 OBITOP (O_BCLR
, 1, 1, ea
&= ~m
);
1390 OBITOP (O_BSET
, 1, 1, ea
|= m
);
1391 OBITOP (O_BLD
, 1, 0, c
= ea
& m
);
1392 OBITOP (O_BILD
, 1, 0, c
= !(ea
& m
));
1393 OBITOP (O_BST
, 1, 1, ea
&= ~m
;
1395 OBITOP (O_BIST
, 1, 1, ea
&= ~m
;
1397 OBITOP (O_BAND
, 1, 0, c
= (ea
& m
) && C
);
1398 OBITOP (O_BIAND
, 1, 0, c
= !(ea
& m
) && C
);
1399 OBITOP (O_BOR
, 1, 0, c
= (ea
& m
) || C
);
1400 OBITOP (O_BIOR
, 1, 0, c
= !(ea
& m
) || C
);
1401 OBITOP (O_BXOR
, 1, 0, c
= (ea
& m
) != C
);
1402 OBITOP (O_BIXOR
, 1, 0, c
= !(ea
& m
) != C
);
1404 #define MOP(bsize, signed) \
1405 mop (code, bsize, signed); \
1408 case O (O_MULS
, SB
):
1411 case O (O_MULS
, SW
):
1414 case O (O_MULU
, SB
):
1417 case O (O_MULU
, SW
):
1422 case O (O_DIVU
, SB
):
1424 rd
= GET_W_REG (code
->dst
.reg
);
1425 ea
= GET_B_REG (code
->src
.reg
);
1428 tmp
= (unsigned) rd
% ea
;
1429 rd
= (unsigned) rd
/ ea
;
1431 SET_W_REG (code
->dst
.reg
, (rd
& 0xff) | (tmp
<< 8));
1437 case O (O_DIVU
, SW
):
1439 rd
= GET_L_REG (code
->dst
.reg
);
1440 ea
= GET_W_REG (code
->src
.reg
);
1445 tmp
= (unsigned) rd
% ea
;
1446 rd
= (unsigned) rd
/ ea
;
1448 SET_L_REG (code
->dst
.reg
, (rd
& 0xffff) | (tmp
<< 16));
1452 case O (O_DIVS
, SB
):
1455 rd
= SEXTSHORT (GET_W_REG (code
->dst
.reg
));
1456 ea
= SEXTCHAR (GET_B_REG (code
->src
.reg
));
1459 tmp
= (int) rd
% (int) ea
;
1460 rd
= (int) rd
/ (int) ea
;
1466 SET_W_REG (code
->dst
.reg
, (rd
& 0xff) | (tmp
<< 8));
1469 case O (O_DIVS
, SW
):
1471 rd
= GET_L_REG (code
->dst
.reg
);
1472 ea
= SEXTSHORT (GET_W_REG (code
->src
.reg
));
1475 tmp
= (int) rd
% (int) ea
;
1476 rd
= (int) rd
/ (int) ea
;
1477 n
= rd
& 0x80000000;
1482 SET_L_REG (code
->dst
.reg
, (rd
& 0xffff) | (tmp
<< 16));
1485 case O (O_EXTS
, SW
):
1486 rd
= GET_B_REG (code
->src
.reg
+ 8) & 0xff; /* Yes, src, not dst. */
1487 ea
= rd
& 0x80 ? -256 : 0;
1490 case O (O_EXTS
, SL
):
1491 rd
= GET_W_REG (code
->src
.reg
) & 0xffff;
1492 ea
= rd
& 0x8000 ? -65536 : 0;
1495 case O (O_EXTU
, SW
):
1496 rd
= GET_B_REG (code
->src
.reg
+ 8) & 0xff;
1500 case O (O_EXTU
, SL
):
1501 rd
= GET_W_REG (code
->src
.reg
) & 0xffff;
1511 int nregs
, firstreg
, i
;
1513 nregs
= GET_MEMORY_B (pc
+ 1);
1516 firstreg
= GET_MEMORY_B (pc
+ 3);
1518 for (i
= firstreg
; i
<= firstreg
+ nregs
; i
++)
1521 SET_MEMORY_L (cpu
.regs
[7], cpu
.regs
[i
]);
1528 int nregs
, firstreg
, i
;
1530 nregs
= GET_MEMORY_B (pc
+ 1);
1533 firstreg
= GET_MEMORY_B (pc
+ 3);
1535 for (i
= firstreg
; i
>= firstreg
- nregs
; i
--)
1537 cpu
.regs
[i
] = GET_MEMORY_L (cpu
.regs
[7]);
1544 cpu
.state
= SIM_STATE_STOPPED
;
1545 cpu
.exception
= SIGILL
;
1557 /* When a branch works */
1558 pc
= code
->src
.literal
;
1561 /* Set the cond codes from res */
1564 /* Set the flags after an 8 bit inc/dec operation */
1568 v
= (rd
& 0x7f) == 0x7f;
1572 /* Set the flags after an 16 bit inc/dec operation */
1576 v
= (rd
& 0x7fff) == 0x7fff;
1580 /* Set the flags after an 32 bit inc/dec operation */
1582 n
= res
& 0x80000000;
1583 nz
= res
& 0xffffffff;
1584 v
= (rd
& 0x7fffffff) == 0x7fffffff;
1589 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
1592 SET_B_REG (code
->src
.reg
, rd
);
1596 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
1599 SET_W_REG (code
->src
.reg
, rd
);
1603 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
1604 n
= (rd
& 0x80000000);
1605 nz
= rd
& 0xffffffff;
1606 SET_L_REG (code
->src
.reg
, rd
);
1610 store (&code
->dst
, res
);
1612 /* flags after a 32bit logical operation */
1613 n
= res
& 0x80000000;
1614 nz
= res
& 0xffffffff;
1619 store (&code
->dst
, res
);
1621 /* flags after a 16bit logical operation */
1629 store (&code
->dst
, res
);
1637 SET_B_REG (code
->dst
.reg
, res
);
1642 switch (code
->opcode
/ 4)
1645 v
= ((rd
& 0x80) == (ea
& 0x80)
1646 && (rd
& 0x80) != (res
& 0x80));
1650 v
= ((rd
& 0x80) != (-ea
& 0x80)
1651 && (rd
& 0x80) != (res
& 0x80));
1660 SET_W_REG (code
->dst
.reg
, res
);
1664 c
= (res
& 0x10000);
1665 switch (code
->opcode
/ 4)
1668 v
= ((rd
& 0x8000) == (ea
& 0x8000)
1669 && (rd
& 0x8000) != (res
& 0x8000));
1673 v
= ((rd
& 0x8000) != (-ea
& 0x8000)
1674 && (rd
& 0x8000) != (res
& 0x8000));
1683 SET_L_REG (code
->dst
.reg
, res
);
1685 n
= res
& 0x80000000;
1686 nz
= res
& 0xffffffff;
1687 switch (code
->opcode
/ 4)
1690 v
= ((rd
& 0x80000000) == (ea
& 0x80000000)
1691 && (rd
& 0x80000000) != (res
& 0x80000000));
1692 c
= ((unsigned) res
< (unsigned) rd
) || ((unsigned) res
< (unsigned) ea
);
1696 v
= ((rd
& 0x80000000) != (-ea
& 0x80000000)
1697 && (rd
& 0x80000000) != (res
& 0x80000000));
1698 c
= (unsigned) rd
< (unsigned) -ea
;
1701 v
= (rd
== 0x80000000);
1717 if (--poll_count
< 0)
1719 poll_count
= POLL_QUIT_INTERVAL
;
1720 if ((*sim_callback
->poll_quit
) != NULL
1721 && (*sim_callback
->poll_quit
) (sim_callback
))
1726 while (cpu
.state
== SIM_STATE_RUNNING
);
1727 cpu
.ticks
+= get_now () - tick_start
;
1728 cpu
.cycles
+= cycles
;
1734 signal (SIGINT
, prev
);
1741 /* FIXME: Unfinished. */
1746 sim_write (sd
, addr
, buffer
, size
)
1749 unsigned char *buffer
;
1757 for (i
= 0; i
< size
; i
++)
1759 if (addr
< memory_size
)
1761 cpu
.memory
[addr
+ i
] = buffer
[i
];
1762 cpu
.cache_idx
[addr
+ i
] = 0;
1765 cpu
.eightbit
[(addr
+ i
) & 0xff] = buffer
[i
];
1771 sim_read (sd
, addr
, buffer
, size
)
1774 unsigned char *buffer
;
1780 if (addr
< memory_size
)
1781 memcpy (buffer
, cpu
.memory
+ addr
, size
);
1783 memcpy (buffer
, cpu
.eightbit
+ (addr
& 0xff), size
);
1797 #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */
1798 #define FP_REGNUM R6_REGNUM /* Contains address of executing
1801 #define CCR_REGNUM 8 /* Contains processor status */
1802 #define PC_REGNUM 9 /* Contains program counter */
1804 #define CYCLE_REGNUM 10
1805 #define INST_REGNUM 11
1806 #define TICK_REGNUM 12
1810 sim_store_register (sd
, rn
, value
, length
)
1813 unsigned char *value
;
1819 longval
= (value
[0] << 24) | (value
[1] << 16) | (value
[2] << 8) | value
[3];
1820 shortval
= (value
[0] << 8) | (value
[1]);
1821 intval
= h8300hmode
? longval
: shortval
;
1839 cpu
.regs
[rn
] = intval
;
1845 cpu
.cycles
= longval
;
1849 cpu
.insts
= longval
;
1853 cpu
.ticks
= longval
;
1860 sim_fetch_register (sd
, rn
, buf
, length
)
1904 if (h8300hmode
|| longreg
)
1920 sim_stop_reason (sd
, reason
, sigrc
)
1922 enum sim_stop
*reason
;
1925 #if 0 /* FIXME: This should work but we can't use it.
1926 grep for SLEEP above. */
1929 case SIM_STATE_EXITED
: *reason
= sim_exited
; break;
1930 case SIM_STATE_SIGNALLED
: *reason
= sim_signalled
; break;
1931 case SIM_STATE_STOPPED
: *reason
= sim_stopped
; break;
1935 *reason
= sim_stopped
;
1937 *sigrc
= cpu
.exception
;
1940 /* FIXME: Rename to sim_set_mem_size. */
1946 /* Memory size is fixed. */
1950 sim_set_simcache_size (n
)
1956 cpu
.cache
= (decoded_inst
*) malloc (sizeof (decoded_inst
) * n
);
1957 memset (cpu
.cache
, 0, sizeof (decoded_inst
) * n
);
1963 sim_info (sd
, verbose
)
1967 double timetaken
= (double) cpu
.ticks
/ (double) now_persec ();
1968 double virttime
= cpu
.cycles
/ 10.0e6
;
1970 (*sim_callback
->printf_filtered
) (sim_callback
,
1971 "\n\n#instructions executed %10d\n",
1973 (*sim_callback
->printf_filtered
) (sim_callback
,
1974 "#cycles (v approximate) %10d\n",
1976 (*sim_callback
->printf_filtered
) (sim_callback
,
1977 "#real time taken %10.4f\n",
1979 (*sim_callback
->printf_filtered
) (sim_callback
,
1980 "#virtual time taked %10.4f\n",
1982 if (timetaken
!= 0.0)
1983 (*sim_callback
->printf_filtered
) (sim_callback
,
1984 "#simulation ratio %10.4f\n",
1985 virttime
/ timetaken
);
1986 (*sim_callback
->printf_filtered
) (sim_callback
,
1989 (*sim_callback
->printf_filtered
) (sim_callback
,
1990 "#cache size %10d\n",
1994 /* This to be conditional on `what' (aka `verbose'),
1995 however it was never passed as non-zero. */
1999 for (i
= 0; i
< O_LAST
; i
++)
2002 (*sim_callback
->printf_filtered
) (sim_callback
,
2003 "%d: %d\n", i
, cpu
.stats
[i
]);
2009 /* Indicate whether the cpu is an H8/300 or H8/300H.
2010 FLAG is non-zero for the H8/300H. */
2013 set_h8300h (h_flag
, s_flag
)
2016 /* FIXME: Much of the code in sim_load can be moved to sim_open.
2017 This function being replaced by a sim_open:ARGV configuration
2019 h8300hmode
= h_flag
;
2020 h8300smode
= s_flag
;
2024 sim_open (kind
, ptr
, abfd
, argv
)
2026 struct host_callback_struct
*ptr
;
2030 /* FIXME: Much of the code in sim_load can be moved here. */
2035 /* Fudge our descriptor. */
2036 return (SIM_DESC
) 1;
2040 sim_close (sd
, quitting
)
2044 /* Nothing to do. */
2047 /* Called by gdb to load a program into memory. */
2050 sim_load (sd
, prog
, abfd
, from_tty
)
2058 /* FIXME: The code below that sets a specific variant of the H8/300
2059 being simulated should be moved to sim_open(). */
2061 /* See if the file is for the H8/300 or H8/300H. */
2062 /* ??? This may not be the most efficient way. The z8k simulator
2063 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
2067 prog_bfd
= bfd_openr (prog
, "coff-h8300");
2068 if (prog_bfd
!= NULL
)
2070 /* Set the cpu type. We ignore failure from bfd_check_format
2071 and bfd_openr as sim_load_file checks too. */
2072 if (bfd_check_format (prog_bfd
, bfd_object
))
2074 unsigned long mach
= bfd_get_mach (prog_bfd
);
2075 set_h8300h (mach
== bfd_mach_h8300h
|| mach
== bfd_mach_h8300s
,
2076 mach
== bfd_mach_h8300s
);
2080 /* If we're using gdb attached to the simulator, then we have to
2081 reallocate memory for the simulator.
2083 When gdb first starts, it calls fetch_registers (among other
2084 functions), which in turn calls init_pointers, which allocates
2087 The problem is when we do that, we don't know whether we're
2088 debugging an H8/300 or H8/300H program.
2090 This is the first point at which we can make that determination,
2091 so we just reallocate memory now; this will also allow us to handle
2092 switching between H8/300 and H8/300H programs without exiting
2096 memory_size
= H8300S_MSIZE
;
2097 else if (h8300hmode
)
2098 memory_size
= H8300H_MSIZE
;
2100 memory_size
= H8300_MSIZE
;
2105 free (cpu
.cache_idx
);
2107 free (cpu
.eightbit
);
2109 cpu
.memory
= (unsigned char *) calloc (sizeof (char), memory_size
);
2110 cpu
.cache_idx
= (unsigned short *) calloc (sizeof (short), memory_size
);
2111 cpu
.eightbit
= (unsigned char *) calloc (sizeof (char), 256);
2113 /* `msize' must be a power of two. */
2114 if ((memory_size
& (memory_size
- 1)) != 0)
2116 cpu
.mask
= memory_size
- 1;
2118 if (sim_load_file (sd
, myname
, sim_callback
, prog
, prog_bfd
,
2119 sim_kind
== SIM_OPEN_DEBUG
,
2123 /* Close the bfd if we opened it. */
2124 if (abfd
== NULL
&& prog_bfd
!= NULL
)
2125 bfd_close (prog_bfd
);
2129 /* Close the bfd if we opened it. */
2130 if (abfd
== NULL
&& prog_bfd
!= NULL
)
2131 bfd_close (prog_bfd
);
2136 sim_create_inferior (sd
, abfd
, argv
, env
)
2143 cpu
.pc
= bfd_get_start_address (abfd
);
2150 sim_do_command (sd
, cmd
)
2154 (*sim_callback
->printf_filtered
) (sim_callback
,
2155 "This simulator does not accept any commands.\n");
2159 sim_set_callbacks (ptr
)
2160 struct host_callback_struct
*ptr
;
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