1 /* Decode header for i960base.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
7 This file is part of the GNU Simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25 #ifndef I960BASE_DECODE_H
26 #define I960BASE_DECODE_H
28 extern const IDESC
*i960base_decode (SIM_CPU
*, IADDR
,
31 extern void i960base_init_idesc_table (SIM_CPU
*);
33 /* Enum declaration for instructions in cpu family i960base. */
34 typedef enum i960base_insn_type
{
35 I960BASE_INSN_X_INVALID
, I960BASE_INSN_X_AFTER
, I960BASE_INSN_X_BEFORE
, I960BASE_INSN_X_CTI_CHAIN
36 , I960BASE_INSN_X_CHAIN
, I960BASE_INSN_X_BEGIN
, I960BASE_INSN_MULO
, I960BASE_INSN_MULO1
37 , I960BASE_INSN_MULO2
, I960BASE_INSN_MULO3
, I960BASE_INSN_REMO
, I960BASE_INSN_REMO1
38 , I960BASE_INSN_REMO2
, I960BASE_INSN_REMO3
, I960BASE_INSN_DIVO
, I960BASE_INSN_DIVO1
39 , I960BASE_INSN_DIVO2
, I960BASE_INSN_DIVO3
, I960BASE_INSN_REMI
, I960BASE_INSN_REMI1
40 , I960BASE_INSN_REMI2
, I960BASE_INSN_REMI3
, I960BASE_INSN_DIVI
, I960BASE_INSN_DIVI1
41 , I960BASE_INSN_DIVI2
, I960BASE_INSN_DIVI3
, I960BASE_INSN_ADDO
, I960BASE_INSN_ADDO1
42 , I960BASE_INSN_ADDO2
, I960BASE_INSN_ADDO3
, I960BASE_INSN_SUBO
, I960BASE_INSN_SUBO1
43 , I960BASE_INSN_SUBO2
, I960BASE_INSN_SUBO3
, I960BASE_INSN_NOTBIT
, I960BASE_INSN_NOTBIT1
44 , I960BASE_INSN_NOTBIT2
, I960BASE_INSN_NOTBIT3
, I960BASE_INSN_AND
, I960BASE_INSN_AND1
45 , I960BASE_INSN_AND2
, I960BASE_INSN_AND3
, I960BASE_INSN_ANDNOT
, I960BASE_INSN_ANDNOT1
46 , I960BASE_INSN_ANDNOT2
, I960BASE_INSN_ANDNOT3
, I960BASE_INSN_SETBIT
, I960BASE_INSN_SETBIT1
47 , I960BASE_INSN_SETBIT2
, I960BASE_INSN_SETBIT3
, I960BASE_INSN_NOTAND
, I960BASE_INSN_NOTAND1
48 , I960BASE_INSN_NOTAND2
, I960BASE_INSN_NOTAND3
, I960BASE_INSN_XOR
, I960BASE_INSN_XOR1
49 , I960BASE_INSN_XOR2
, I960BASE_INSN_XOR3
, I960BASE_INSN_OR
, I960BASE_INSN_OR1
50 , I960BASE_INSN_OR2
, I960BASE_INSN_OR3
, I960BASE_INSN_NOR
, I960BASE_INSN_NOR1
51 , I960BASE_INSN_NOR2
, I960BASE_INSN_NOR3
, I960BASE_INSN_NOT
, I960BASE_INSN_NOT1
52 , I960BASE_INSN_NOT2
, I960BASE_INSN_NOT3
, I960BASE_INSN_CLRBIT
, I960BASE_INSN_CLRBIT1
53 , I960BASE_INSN_CLRBIT2
, I960BASE_INSN_CLRBIT3
, I960BASE_INSN_SHLO
, I960BASE_INSN_SHLO1
54 , I960BASE_INSN_SHLO2
, I960BASE_INSN_SHLO3
, I960BASE_INSN_SHRO
, I960BASE_INSN_SHRO1
55 , I960BASE_INSN_SHRO2
, I960BASE_INSN_SHRO3
, I960BASE_INSN_SHLI
, I960BASE_INSN_SHLI1
56 , I960BASE_INSN_SHLI2
, I960BASE_INSN_SHLI3
, I960BASE_INSN_SHRI
, I960BASE_INSN_SHRI1
57 , I960BASE_INSN_SHRI2
, I960BASE_INSN_SHRI3
, I960BASE_INSN_EMUL
, I960BASE_INSN_EMUL1
58 , I960BASE_INSN_EMUL2
, I960BASE_INSN_EMUL3
, I960BASE_INSN_MOV
, I960BASE_INSN_MOV1
59 , I960BASE_INSN_MOVL
, I960BASE_INSN_MOVL1
, I960BASE_INSN_MOVT
, I960BASE_INSN_MOVT1
60 , I960BASE_INSN_MOVQ
, I960BASE_INSN_MOVQ1
, I960BASE_INSN_MODPC
, I960BASE_INSN_MODAC
61 , I960BASE_INSN_LDA_OFFSET
, I960BASE_INSN_LDA_INDIRECT_OFFSET
, I960BASE_INSN_LDA_INDIRECT
, I960BASE_INSN_LDA_INDIRECT_INDEX
62 , I960BASE_INSN_LDA_DISP
, I960BASE_INSN_LDA_INDIRECT_DISP
, I960BASE_INSN_LDA_INDEX_DISP
, I960BASE_INSN_LDA_INDIRECT_INDEX_DISP
63 , I960BASE_INSN_LD_OFFSET
, I960BASE_INSN_LD_INDIRECT_OFFSET
, I960BASE_INSN_LD_INDIRECT
, I960BASE_INSN_LD_INDIRECT_INDEX
64 , I960BASE_INSN_LD_DISP
, I960BASE_INSN_LD_INDIRECT_DISP
, I960BASE_INSN_LD_INDEX_DISP
, I960BASE_INSN_LD_INDIRECT_INDEX_DISP
65 , I960BASE_INSN_LDOB_OFFSET
, I960BASE_INSN_LDOB_INDIRECT_OFFSET
, I960BASE_INSN_LDOB_INDIRECT
, I960BASE_INSN_LDOB_INDIRECT_INDEX
66 , I960BASE_INSN_LDOB_DISP
, I960BASE_INSN_LDOB_INDIRECT_DISP
, I960BASE_INSN_LDOB_INDEX_DISP
, I960BASE_INSN_LDOB_INDIRECT_INDEX_DISP
67 , I960BASE_INSN_LDOS_OFFSET
, I960BASE_INSN_LDOS_INDIRECT_OFFSET
, I960BASE_INSN_LDOS_INDIRECT
, I960BASE_INSN_LDOS_INDIRECT_INDEX
68 , I960BASE_INSN_LDOS_DISP
, I960BASE_INSN_LDOS_INDIRECT_DISP
, I960BASE_INSN_LDOS_INDEX_DISP
, I960BASE_INSN_LDOS_INDIRECT_INDEX_DISP
69 , I960BASE_INSN_LDIB_OFFSET
, I960BASE_INSN_LDIB_INDIRECT_OFFSET
, I960BASE_INSN_LDIB_INDIRECT
, I960BASE_INSN_LDIB_INDIRECT_INDEX
70 , I960BASE_INSN_LDIB_DISP
, I960BASE_INSN_LDIB_INDIRECT_DISP
, I960BASE_INSN_LDIB_INDEX_DISP
, I960BASE_INSN_LDIB_INDIRECT_INDEX_DISP
71 , I960BASE_INSN_LDIS_OFFSET
, I960BASE_INSN_LDIS_INDIRECT_OFFSET
, I960BASE_INSN_LDIS_INDIRECT
, I960BASE_INSN_LDIS_INDIRECT_INDEX
72 , I960BASE_INSN_LDIS_DISP
, I960BASE_INSN_LDIS_INDIRECT_DISP
, I960BASE_INSN_LDIS_INDEX_DISP
, I960BASE_INSN_LDIS_INDIRECT_INDEX_DISP
73 , I960BASE_INSN_LDL_OFFSET
, I960BASE_INSN_LDL_INDIRECT_OFFSET
, I960BASE_INSN_LDL_INDIRECT
, I960BASE_INSN_LDL_INDIRECT_INDEX
74 , I960BASE_INSN_LDL_DISP
, I960BASE_INSN_LDL_INDIRECT_DISP
, I960BASE_INSN_LDL_INDEX_DISP
, I960BASE_INSN_LDL_INDIRECT_INDEX_DISP
75 , I960BASE_INSN_LDT_OFFSET
, I960BASE_INSN_LDT_INDIRECT_OFFSET
, I960BASE_INSN_LDT_INDIRECT
, I960BASE_INSN_LDT_INDIRECT_INDEX
76 , I960BASE_INSN_LDT_DISP
, I960BASE_INSN_LDT_INDIRECT_DISP
, I960BASE_INSN_LDT_INDEX_DISP
, I960BASE_INSN_LDT_INDIRECT_INDEX_DISP
77 , I960BASE_INSN_LDQ_OFFSET
, I960BASE_INSN_LDQ_INDIRECT_OFFSET
, I960BASE_INSN_LDQ_INDIRECT
, I960BASE_INSN_LDQ_INDIRECT_INDEX
78 , I960BASE_INSN_LDQ_DISP
, I960BASE_INSN_LDQ_INDIRECT_DISP
, I960BASE_INSN_LDQ_INDEX_DISP
, I960BASE_INSN_LDQ_INDIRECT_INDEX_DISP
79 , I960BASE_INSN_ST_OFFSET
, I960BASE_INSN_ST_INDIRECT_OFFSET
, I960BASE_INSN_ST_INDIRECT
, I960BASE_INSN_ST_INDIRECT_INDEX
80 , I960BASE_INSN_ST_DISP
, I960BASE_INSN_ST_INDIRECT_DISP
, I960BASE_INSN_ST_INDEX_DISP
, I960BASE_INSN_ST_INDIRECT_INDEX_DISP
81 , I960BASE_INSN_STOB_OFFSET
, I960BASE_INSN_STOB_INDIRECT_OFFSET
, I960BASE_INSN_STOB_INDIRECT
, I960BASE_INSN_STOB_INDIRECT_INDEX
82 , I960BASE_INSN_STOB_DISP
, I960BASE_INSN_STOB_INDIRECT_DISP
, I960BASE_INSN_STOB_INDEX_DISP
, I960BASE_INSN_STOB_INDIRECT_INDEX_DISP
83 , I960BASE_INSN_STOS_OFFSET
, I960BASE_INSN_STOS_INDIRECT_OFFSET
, I960BASE_INSN_STOS_INDIRECT
, I960BASE_INSN_STOS_INDIRECT_INDEX
84 , I960BASE_INSN_STOS_DISP
, I960BASE_INSN_STOS_INDIRECT_DISP
, I960BASE_INSN_STOS_INDEX_DISP
, I960BASE_INSN_STOS_INDIRECT_INDEX_DISP
85 , I960BASE_INSN_STL_OFFSET
, I960BASE_INSN_STL_INDIRECT_OFFSET
, I960BASE_INSN_STL_INDIRECT
, I960BASE_INSN_STL_INDIRECT_INDEX
86 , I960BASE_INSN_STL_DISP
, I960BASE_INSN_STL_INDIRECT_DISP
, I960BASE_INSN_STL_INDEX_DISP
, I960BASE_INSN_STL_INDIRECT_INDEX_DISP
87 , I960BASE_INSN_STT_OFFSET
, I960BASE_INSN_STT_INDIRECT_OFFSET
, I960BASE_INSN_STT_INDIRECT
, I960BASE_INSN_STT_INDIRECT_INDEX
88 , I960BASE_INSN_STT_DISP
, I960BASE_INSN_STT_INDIRECT_DISP
, I960BASE_INSN_STT_INDEX_DISP
, I960BASE_INSN_STT_INDIRECT_INDEX_DISP
89 , I960BASE_INSN_STQ_OFFSET
, I960BASE_INSN_STQ_INDIRECT_OFFSET
, I960BASE_INSN_STQ_INDIRECT
, I960BASE_INSN_STQ_INDIRECT_INDEX
90 , I960BASE_INSN_STQ_DISP
, I960BASE_INSN_STQ_INDIRECT_DISP
, I960BASE_INSN_STQ_INDEX_DISP
, I960BASE_INSN_STQ_INDIRECT_INDEX_DISP
91 , I960BASE_INSN_CMPOBE_REG
, I960BASE_INSN_CMPOBE_LIT
, I960BASE_INSN_CMPOBNE_REG
, I960BASE_INSN_CMPOBNE_LIT
92 , I960BASE_INSN_CMPOBL_REG
, I960BASE_INSN_CMPOBL_LIT
, I960BASE_INSN_CMPOBLE_REG
, I960BASE_INSN_CMPOBLE_LIT
93 , I960BASE_INSN_CMPOBG_REG
, I960BASE_INSN_CMPOBG_LIT
, I960BASE_INSN_CMPOBGE_REG
, I960BASE_INSN_CMPOBGE_LIT
94 , I960BASE_INSN_CMPIBE_REG
, I960BASE_INSN_CMPIBE_LIT
, I960BASE_INSN_CMPIBNE_REG
, I960BASE_INSN_CMPIBNE_LIT
95 , I960BASE_INSN_CMPIBL_REG
, I960BASE_INSN_CMPIBL_LIT
, I960BASE_INSN_CMPIBLE_REG
, I960BASE_INSN_CMPIBLE_LIT
96 , I960BASE_INSN_CMPIBG_REG
, I960BASE_INSN_CMPIBG_LIT
, I960BASE_INSN_CMPIBGE_REG
, I960BASE_INSN_CMPIBGE_LIT
97 , I960BASE_INSN_BBC_REG
, I960BASE_INSN_BBC_LIT
, I960BASE_INSN_BBS_REG
, I960BASE_INSN_BBS_LIT
98 , I960BASE_INSN_CMPI
, I960BASE_INSN_CMPI1
, I960BASE_INSN_CMPI2
, I960BASE_INSN_CMPI3
99 , I960BASE_INSN_CMPO
, I960BASE_INSN_CMPO1
, I960BASE_INSN_CMPO2
, I960BASE_INSN_CMPO3
100 , I960BASE_INSN_TESTNO_REG
, I960BASE_INSN_TESTG_REG
, I960BASE_INSN_TESTE_REG
, I960BASE_INSN_TESTGE_REG
101 , I960BASE_INSN_TESTL_REG
, I960BASE_INSN_TESTNE_REG
, I960BASE_INSN_TESTLE_REG
, I960BASE_INSN_TESTO_REG
102 , I960BASE_INSN_BNO
, I960BASE_INSN_BG
, I960BASE_INSN_BE
, I960BASE_INSN_BGE
103 , I960BASE_INSN_BL
, I960BASE_INSN_BNE
, I960BASE_INSN_BLE
, I960BASE_INSN_BO
104 , I960BASE_INSN_B
, I960BASE_INSN_BX_INDIRECT_OFFSET
, I960BASE_INSN_BX_INDIRECT
, I960BASE_INSN_BX_INDIRECT_INDEX
105 , I960BASE_INSN_BX_DISP
, I960BASE_INSN_BX_INDIRECT_DISP
, I960BASE_INSN_CALLX_DISP
, I960BASE_INSN_CALLX_INDIRECT
106 , I960BASE_INSN_CALLX_INDIRECT_OFFSET
, I960BASE_INSN_RET
, I960BASE_INSN_CALLS
, I960BASE_INSN_FMARK
107 , I960BASE_INSN_FLUSHREG
, I960BASE_INSN_MAX
108 } I960BASE_INSN_TYPE
;
110 #if ! WITH_SEM_SWITCH_FULL
111 #define SEMFULL(fn) extern SEMANTIC_FN CONCAT3 (i960base,_sem_,fn);
116 #if ! WITH_SEM_SWITCH_FAST
117 #define SEMFAST(fn) extern SEMANTIC_FN CONCAT3 (i960base,_semf_,fn);
122 #define SEM(fn) SEMFULL (fn) SEMFAST (fn)
124 /* The function version of the before/after handlers is always needed,
125 so we always want the SEMFULL declaration of them. */
126 extern SEMANTIC_FN
CONCAT3 (i960base
,_sem_
,x_before
);
127 extern SEMANTIC_FN
CONCAT3 (i960base
,_sem_
,x_after
);
234 SEM (lda_indirect_offset
)
236 SEM (lda_indirect_index
)
238 SEM (lda_indirect_disp
)
240 SEM (lda_indirect_index_disp
)
242 SEM (ld_indirect_offset
)
244 SEM (ld_indirect_index
)
246 SEM (ld_indirect_disp
)
248 SEM (ld_indirect_index_disp
)
250 SEM (ldob_indirect_offset
)
252 SEM (ldob_indirect_index
)
254 SEM (ldob_indirect_disp
)
255 SEM (ldob_index_disp
)
256 SEM (ldob_indirect_index_disp
)
258 SEM (ldos_indirect_offset
)
260 SEM (ldos_indirect_index
)
262 SEM (ldos_indirect_disp
)
263 SEM (ldos_index_disp
)
264 SEM (ldos_indirect_index_disp
)
266 SEM (ldib_indirect_offset
)
268 SEM (ldib_indirect_index
)
270 SEM (ldib_indirect_disp
)
271 SEM (ldib_index_disp
)
272 SEM (ldib_indirect_index_disp
)
274 SEM (ldis_indirect_offset
)
276 SEM (ldis_indirect_index
)
278 SEM (ldis_indirect_disp
)
279 SEM (ldis_index_disp
)
280 SEM (ldis_indirect_index_disp
)
282 SEM (ldl_indirect_offset
)
284 SEM (ldl_indirect_index
)
286 SEM (ldl_indirect_disp
)
288 SEM (ldl_indirect_index_disp
)
290 SEM (ldt_indirect_offset
)
292 SEM (ldt_indirect_index
)
294 SEM (ldt_indirect_disp
)
296 SEM (ldt_indirect_index_disp
)
298 SEM (ldq_indirect_offset
)
300 SEM (ldq_indirect_index
)
302 SEM (ldq_indirect_disp
)
304 SEM (ldq_indirect_index_disp
)
306 SEM (st_indirect_offset
)
308 SEM (st_indirect_index
)
310 SEM (st_indirect_disp
)
312 SEM (st_indirect_index_disp
)
314 SEM (stob_indirect_offset
)
316 SEM (stob_indirect_index
)
318 SEM (stob_indirect_disp
)
319 SEM (stob_index_disp
)
320 SEM (stob_indirect_index_disp
)
322 SEM (stos_indirect_offset
)
324 SEM (stos_indirect_index
)
326 SEM (stos_indirect_disp
)
327 SEM (stos_index_disp
)
328 SEM (stos_indirect_index_disp
)
330 SEM (stl_indirect_offset
)
332 SEM (stl_indirect_index
)
334 SEM (stl_indirect_disp
)
336 SEM (stl_indirect_index_disp
)
338 SEM (stt_indirect_offset
)
340 SEM (stt_indirect_index
)
342 SEM (stt_indirect_disp
)
344 SEM (stt_indirect_index_disp
)
346 SEM (stq_indirect_offset
)
348 SEM (stq_indirect_index
)
350 SEM (stq_indirect_disp
)
352 SEM (stq_indirect_index_disp
)
406 SEM (bx_indirect_offset
)
408 SEM (bx_indirect_index
)
410 SEM (bx_indirect_disp
)
413 SEM (callx_indirect_offset
)
423 /* Function unit handlers (user written). */
425 extern int i960base_model_i960KA_u_exec (SIM_CPU
*, const IDESC
*, int /*unit_num*/, int /*referenced*/);
426 extern int i960base_model_i960CA_u_exec (SIM_CPU
*, const IDESC
*, int /*unit_num*/, int /*referenced*/);
428 /* Profiling before/after handlers (user written) */
430 extern void i960base_model_insn_before (SIM_CPU
*, int /*first_p*/);
431 extern void i960base_model_insn_after (SIM_CPU
*, int /*last_p*/, int /*cycles*/);
433 #endif /* I960BASE_DECODE_H */