sim/i960/i960-desc.h

   1 /* CPU data header for i960.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef I960_CPU_H
  26 #define I960_CPU_H
  27
  28 #define CGEN_ARCH i960
  29
  30 /* Given symbol S, return i960_cgen_<S>.  */
  31 #define CGEN_SYM(s) CONCAT3 (i960,_cgen_,s)
  32
  33 /* Selected cpu families.  */
  34 #define HAVE_CPU_I960BASE
  35
  36 #define CGEN_INSN_LSB0_P 0
  37
  38 /* Maximum size of any insn (in bytes).  */
  39 #define CGEN_MAX_INSN_SIZE 8
  40
  41 #define CGEN_INT_INSN_P 0
  42
  43 /* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES.  */
  44
  45 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
  46    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
  47    we can't hash on everything up to the space.  */
  48 #define CGEN_MNEMONIC_OPERANDS
  49 /* Maximum number of operands any insn or macro-insn has.  */
  50 #define CGEN_MAX_INSN_OPERANDS 16
  51
  52 /* Maximum number of fields in an instruction.  */
  53 #define CGEN_MAX_IFMT_OPERANDS 9
  54
  55 /* Enums.  */
  56
  57 /* Enum declaration for insn opcode enums.  */
  58 typedef enum insn_opcode {
  59   OPCODE_00, OPCODE_01, OPCODE_02, OPCODE_03
  60  , OPCODE_04, OPCODE_05, OPCODE_06, OPCODE_07
  61  , OPCODE_08, OPCODE_09, OPCODE_0A, OPCODE_0B
  62  , OPCODE_0C, OPCODE_0D, OPCODE_0E, OPCODE_0F
  63  , OPCODE_10, OPCODE_11, OPCODE_12, OPCODE_13
  64  , OPCODE_14, OPCODE_15, OPCODE_16, OPCODE_17
  65  , OPCODE_18, OPCODE_19, OPCODE_1A, OPCODE_1B
  66  , OPCODE_1C, OPCODE_1D, OPCODE_1E, OPCODE_1F
  67  , OPCODE_20, OPCODE_21, OPCODE_22, OPCODE_23
  68  , OPCODE_24, OPCODE_25, OPCODE_26, OPCODE_27
  69  , OPCODE_28, OPCODE_29, OPCODE_2A, OPCODE_2B
  70  , OPCODE_2C, OPCODE_2D, OPCODE_2E, OPCODE_2F
  71  , OPCODE_30, OPCODE_31, OPCODE_32, OPCODE_33
  72  , OPCODE_34, OPCODE_35, OPCODE_36, OPCODE_37
  73  , OPCODE_38, OPCODE_39, OPCODE_3A, OPCODE_3B
  74  , OPCODE_3C, OPCODE_3D, OPCODE_3E, OPCODE_3F
  75  , OPCODE_40, OPCODE_41, OPCODE_42, OPCODE_43
  76  , OPCODE_44, OPCODE_45, OPCODE_46, OPCODE_47
  77  , OPCODE_48, OPCODE_49, OPCODE_4A, OPCODE_4B
  78  , OPCODE_4C, OPCODE_4D, OPCODE_4E, OPCODE_4F
  79  , OPCODE_50, OPCODE_51, OPCODE_52, OPCODE_53
  80  , OPCODE_54, OPCODE_55, OPCODE_56, OPCODE_57
  81  , OPCODE_58, OPCODE_59, OPCODE_5A, OPCODE_5B
  82  , OPCODE_5C, OPCODE_5D, OPCODE_5E, OPCODE_5F
  83  , OPCODE_60, OPCODE_61, OPCODE_62, OPCODE_63
  84  , OPCODE_64, OPCODE_65, OPCODE_66, OPCODE_67
  85  , OPCODE_68, OPCODE_69, OPCODE_6A, OPCODE_6B
  86  , OPCODE_6C, OPCODE_6D, OPCODE_6E, OPCODE_6F
  87  , OPCODE_70, OPCODE_71, OPCODE_72, OPCODE_73
  88  , OPCODE_74, OPCODE_75, OPCODE_76, OPCODE_77
  89  , OPCODE_78, OPCODE_79, OPCODE_7A, OPCODE_7B
  90  , OPCODE_7C, OPCODE_7D, OPCODE_7E, OPCODE_7F
  91  , OPCODE_80, OPCODE_81, OPCODE_82, OPCODE_83
  92  , OPCODE_84, OPCODE_85, OPCODE_86, OPCODE_87
  93  , OPCODE_88, OPCODE_89, OPCODE_8A, OPCODE_8B
  94  , OPCODE_8C, OPCODE_8D, OPCODE_8E, OPCODE_8F
  95  , OPCODE_90, OPCODE_91, OPCODE_92, OPCODE_93
  96  , OPCODE_94, OPCODE_95, OPCODE_96, OPCODE_97
  97  , OPCODE_98, OPCODE_99, OPCODE_9A, OPCODE_9B
  98  , OPCODE_9C, OPCODE_9D, OPCODE_9E, OPCODE_9F
  99  , OPCODE_A0, OPCODE_A1, OPCODE_A2, OPCODE_A3
 100  , OPCODE_A4, OPCODE_A5, OPCODE_A6, OPCODE_A7
 101  , OPCODE_A8, OPCODE_A9, OPCODE_AA, OPCODE_AB
 102  , OPCODE_AC, OPCODE_AD, OPCODE_AE, OPCODE_AF
 103  , OPCODE_B0, OPCODE_B1, OPCODE_B2, OPCODE_B3
 104  , OPCODE_B4, OPCODE_B5, OPCODE_B6, OPCODE_B7
 105  , OPCODE_B8, OPCODE_B9, OPCODE_BA, OPCODE_BB
 106  , OPCODE_BC, OPCODE_BD, OPCODE_BE, OPCODE_BF
 107  , OPCODE_C0, OPCODE_C1, OPCODE_C2, OPCODE_C3
 108  , OPCODE_C4, OPCODE_C5, OPCODE_C6, OPCODE_C7
 109  , OPCODE_C8, OPCODE_C9, OPCODE_CA, OPCODE_CB
 110  , OPCODE_CC, OPCODE_CD, OPCODE_CE, OPCODE_CF
 111  , OPCODE_D0, OPCODE_D1, OPCODE_D2, OPCODE_D3
 112  , OPCODE_D4, OPCODE_D5, OPCODE_D6, OPCODE_D7
 113  , OPCODE_D8, OPCODE_D9, OPCODE_DA, OPCODE_DB
 114  , OPCODE_DC, OPCODE_DD, OPCODE_DE, OPCODE_DF
 115  , OPCODE_E0, OPCODE_E1, OPCODE_E2, OPCODE_E3
 116  , OPCODE_E4, OPCODE_E5, OPCODE_E6, OPCODE_E7
 117  , OPCODE_E8, OPCODE_E9, OPCODE_EA, OPCODE_EB
 118  , OPCODE_EC, OPCODE_ED, OPCODE_EE, OPCODE_EF
 119  , OPCODE_F0, OPCODE_F1, OPCODE_F2, OPCODE_F3
 120  , OPCODE_F4, OPCODE_F5, OPCODE_F6, OPCODE_F7
 121  , OPCODE_F8, OPCODE_F9, OPCODE_FA, OPCODE_FB
 122  , OPCODE_FC, OPCODE_FD, OPCODE_FE, OPCODE_FF
 123 } INSN_OPCODE;
 124
 125 /* Enum declaration for insn opcode2 enums.  */
 126 typedef enum insn_opcode2 {
 127   OPCODE2_0, OPCODE2_1, OPCODE2_2, OPCODE2_3
 128  , OPCODE2_4, OPCODE2_5, OPCODE2_6, OPCODE2_7
 129  , OPCODE2_8, OPCODE2_9, OPCODE2_A, OPCODE2_B
 130  , OPCODE2_C, OPCODE2_D, OPCODE2_E, OPCODE2_F
 131 } INSN_OPCODE2;
 132
 133 /* Enum declaration for insn m3 enums.  */
 134 typedef enum insn_m3 {
 135   M3_0, M3_1
 136 } INSN_M3;
 137
 138 /* Enum declaration for insn m3 enums.  */
 139 typedef enum insn_m2 {
 140   M2_0, M2_1
 141 } INSN_M2;
 142
 143 /* Enum declaration for insn m1 enums.  */
 144 typedef enum insn_m1 {
 145   M1_0, M1_1
 146 } INSN_M1;
 147
 148 /* Enum declaration for insn zero enums.  */
 149 typedef enum insn_zero {
 150   ZERO_0
 151 } INSN_ZERO;
 152
 153 /* Enum declaration for insn mode a enums.  */
 154 typedef enum insn_modea {
 155   MODEA_OFFSET, MODEA_INDIRECT_OFFSET
 156 } INSN_MODEA;
 157
 158 /* Enum declaration for insn zero a enums.  */
 159 typedef enum insn_zeroa {
 160   ZEROA_0
 161 } INSN_ZEROA;
 162
 163 /* Enum declaration for insn mode b enums.  */
 164 typedef enum insn_modeb {
 165   MODEB_ILL0, MODEB_ILL1, MODEB_ILL2, MODEB_ILL3
 166  , MODEB_INDIRECT, MODEB_IP_DISP, MODEB_RES6, MODEB_INDIRECT_INDEX
 167  , MODEB_ILL8, MODEB_ILL9, MODEB_ILL10, MODEB_ILL11
 168  , MODEB_DISP, MODEB_INDIRECT_DISP, MODEB_INDEX_DISP, MODEB_INDIRECT_INDEX_DISP
 169 } INSN_MODEB;
 170
 171 /* Enum declaration for insn zero b enums.  */
 172 typedef enum insn_zerob {
 173   ZEROB_0
 174 } INSN_ZEROB;
 175
 176 /* Enum declaration for insn branch m1 enums.  */
 177 typedef enum insn_br_m1 {
 178   BR_M1_0, BR_M1_1
 179 } INSN_BR_M1;
 180
 181 /* Enum declaration for insn branch zero enums.  */
 182 typedef enum insn_br_zero {
 183   BR_ZERO_0
 184 } INSN_BR_ZERO;
 185
 186 /* Enum declaration for insn ctrl zero enums.  */
 187 typedef enum insn_ctrl_zero {
 188   CTRL_ZERO_0
 189 } INSN_CTRL_ZERO;
 190
 191 /* Attributes.  */
 192
 193 /* Enum declaration for machine type selection.  */
 194 typedef enum mach_attr {
 195   MACH_BASE, MACH_I960_KA_SA, MACH_I960_CA, MACH_MAX
 196 } MACH_ATTR;
 197
 198 /* Enum declaration for instruction set selection.  */
 199 typedef enum isa_attr {
 200   ISA_I960, ISA_MAX
 201 } ISA_ATTR;
 202
 203 /* Number of architecture variants.  */
 204 #define MAX_ISAS  1
 205 #define MAX_MACHS ((int) MACH_MAX)
 206
 207 /* Ifield support.  */
 208
 209 extern const struct cgen_ifld i960_cgen_ifld_table[];
 210
 211 /* Ifield attribute indices.  */
 212
 213 /* Enum declaration for cgen_ifld attrs.  */
 214 typedef enum cgen_ifld_attr {
 215   CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
 216  , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
 217  , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
 218 } CGEN_IFLD_ATTR;
 219
 220 /* Number of non-boolean elements in cgen_ifld_attr.  */
 221 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
 222
 223 /* Enum declaration for i960 ifield types.  */
 224 typedef enum ifield_type {
 225   I960_F_NIL, I960_F_OPCODE, I960_F_SRCDST, I960_F_SRC2
 226  , I960_F_M3, I960_F_M2, I960_F_M1, I960_F_OPCODE2
 227  , I960_F_ZERO, I960_F_SRC1, I960_F_ABASE, I960_F_MODEA
 228  , I960_F_ZEROA, I960_F_OFFSET, I960_F_MODEB, I960_F_SCALE
 229  , I960_F_ZEROB, I960_F_INDEX, I960_F_OPTDISP, I960_F_BR_SRC1
 230  , I960_F_BR_SRC2, I960_F_BR_M1, I960_F_BR_DISP, I960_F_BR_ZERO
 231  , I960_F_CTRL_DISP, I960_F_CTRL_ZERO, I960_F_MAX
 232 } IFIELD_TYPE;
 233
 234 #define MAX_IFLD ((int) I960_F_MAX)
 235
 236 /* Hardware attribute indices.  */
 237
 238 /* Enum declaration for cgen_hw attrs.  */
 239 typedef enum cgen_hw_attr {
 240   CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
 241  , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
 242 } CGEN_HW_ATTR;
 243
 244 /* Number of non-boolean elements in cgen_hw_attr.  */
 245 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
 246
 247 /* Enum declaration for i960 hardware types.  */
 248 typedef enum cgen_hw_type {
 249   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
 250  , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_CC
 251  , HW_MAX
 252 } CGEN_HW_TYPE;
 253
 254 #define MAX_HW ((int) HW_MAX)
 255
 256 /* Operand attribute indices.  */
 257
 258 /* Enum declaration for cgen_operand attrs.  */
 259 typedef enum cgen_operand_attr {
 260   CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
 261  , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
 262  , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
 263 } CGEN_OPERAND_ATTR;
 264
 265 /* Number of non-boolean elements in cgen_operand_attr.  */
 266 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
 267
 268 /* Enum declaration for i960 operand types.  */
 269 typedef enum cgen_operand_type {
 270   I960_OPERAND_PC, I960_OPERAND_SRC1, I960_OPERAND_SRC2, I960_OPERAND_DST
 271  , I960_OPERAND_LIT1, I960_OPERAND_LIT2, I960_OPERAND_ST_SRC, I960_OPERAND_ABASE
 272  , I960_OPERAND_OFFSET, I960_OPERAND_SCALE, I960_OPERAND_INDEX, I960_OPERAND_OPTDISP
 273  , I960_OPERAND_BR_SRC1, I960_OPERAND_BR_SRC2, I960_OPERAND_BR_DISP, I960_OPERAND_BR_LIT1
 274  , I960_OPERAND_CTRL_DISP, I960_OPERAND_MAX
 275 } CGEN_OPERAND_TYPE;
 276
 277 /* Number of operands types.  */
 278 #define MAX_OPERANDS ((int) I960_OPERAND_MAX)
 279
 280 /* Maximum number of operands referenced by any insn.  */
 281 #define MAX_OPERAND_INSTANCES 8
 282
 283 /* Insn attribute indices.  */
 284
 285 /* Enum declaration for cgen_insn attrs.  */
 286 typedef enum cgen_insn_attr {
 287   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
 288  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
 289  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
 290  , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
 291 } CGEN_INSN_ATTR;
 292
 293 /* Number of non-boolean elements in cgen_insn_attr.  */
 294 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
 295
 296 /* cgen.h uses things we just defined.  */
 297 #include "opcode/cgen.h"
 298
 299 /* Attributes.  */
 300 extern const CGEN_ATTR_TABLE i960_cgen_hardware_attr_table[];
 301 extern const CGEN_ATTR_TABLE i960_cgen_ifield_attr_table[];
 302 extern const CGEN_ATTR_TABLE i960_cgen_operand_attr_table[];
 303 extern const CGEN_ATTR_TABLE i960_cgen_insn_attr_table[];
 304
 305 /* Hardware decls.  */
 306
 307 extern CGEN_KEYWORD i960_cgen_opval_h_gr;
 308 extern CGEN_KEYWORD i960_cgen_opval_h_cc;
 309
 310
 311
 312
 313 #endif /* I960_CPU_H */