sim/i960/i960-sim.h

   1 #ifndef I960_SIM_H
   2 #define I960_SIM_H
   3
   4 /* gdb register numbers */
   5 /* Copied from gdb/config/i960/tc-i960.h.  */
   6 #define PCW_REGNUM 32   /* process control word */
   7 #define ACW_REGNUM 33   /* arithmetic control word */
   8 #define TCW_REGNUM 34   /* trace control word */
   9 #define IP_REGNUM  35   /* instruction pointer */
  10 #define FP0_REGNUM 36   /* First floating point register */
  11 /* Some registers have more than one name */
  12 #define PC_REGNUM  IP_REGNUM    /* GDB refers to ip as the Program Counter */
  13
  14 SI a_i960_h_gr_get (SIM_CPU *, UINT);
  15 void a_i960_h_gr_set (SIM_CPU *, UINT, SI);
  16 IADDR a_i960_h_pc_get (SIM_CPU *);
  17 void a_i960_h_pc_set (SIM_CPU *, IADDR);
  18 \f
  19 #define GETTWI GETTSI
  20 #define SETTWI SETTSI
  21 \f
  22 /* Exception, Interrupt, and Trap addresses */
  23 /* ??? Hack for traps.c.  */
  24 #define EIT_TRAP_BASE_ADDR      0x40
  25
  26 /* Special purpose traps.  */
  27 /* ??? Hack for traps.c.  */
  28 #define TRAP_SYSCALL    0
  29 #define TRAP_BREAKPOINT 1
  30
  31 /* Cache Purge Control (only exists on early versions of chips) */
  32 /* ??? Hack for devices.c.  */
  33 #define MSPR_ADDR 0xfffffff7
  34 #define MSPR_PURGE 1
  35
  36 /* Cache Control Register */
  37 /* ??? Hack for devices.c.  */
  38 #define MCCR_ADDR 0xffffffff
  39 #define MCCR_CP 0x80
  40
  41 /* Start address and length of all device support.  */
  42 /* ??? Hack for sim-if.c.  */
  43 #define I960_DEVICE_ADDR        0xff000000
  44 #define I960_DEVICE_LEN         0x00ffffff
  45
  46 /* sim_core_attach device argument.  */
  47 /* ??? Hack for sim-if.c.  */
  48 extern device i960_devices;
  49
  50 /* FIXME: Temporary, until device support ready.  */
  51 /* ??? Hack for devices.c.  */
  52 struct _device { int foo; };
  53
  54 #endif I960_SIM_H