1 /* Lattice Mico32 exception and system call support.
2 Contributed by Jon Beniston <jon@beniston.com>
4 Copyright (C) 2009-2015 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #define WANT_CPU lm32bf
22 #define WANT_CPU_LM32BF
25 #include "sim-syscall.h"
27 #include "targ-vals.h"
29 /* Handle invalid instructions. */
32 sim_engine_invalid_insn (SIM_CPU
* current_cpu
, IADDR cia
, SEM_PC pc
)
34 SIM_DESC sd
= CPU_STATE (current_cpu
);
36 sim_engine_halt (sd
, current_cpu
, NULL
, cia
, sim_stopped
, SIM_SIGILL
);
41 /* Handle divide instructions. */
44 lm32bf_divu_insn (SIM_CPU
* current_cpu
, IADDR pc
, USI r0
, USI r1
, USI r2
)
46 SIM_DESC sd
= CPU_STATE (current_cpu
);
47 host_callback
*cb
= STATE_CALLBACK (sd
);
49 /* Check for divide by zero */
50 if (GET_H_GR (r1
) == 0)
52 if (STATE_ENVIRONMENT (sd
) != OPERATING_ENVIRONMENT
)
53 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGFPE
);
56 /* Save PC in exception address register. */
58 /* Save and clear interrupt enable. */
59 SET_H_CSR (LM32_CSR_IE
, (GET_H_CSR (LM32_CSR_IE
) & 1) << 1);
60 /* Branch to divide by zero exception handler. */
61 return GET_H_CSR (LM32_CSR_EBA
) + LM32_EID_DIVIDE_BY_ZERO
* 32;
66 SET_H_GR (r2
, (USI
) GET_H_GR (r0
) / (USI
) GET_H_GR (r1
));
72 lm32bf_modu_insn (SIM_CPU
* current_cpu
, IADDR pc
, USI r0
, USI r1
, USI r2
)
74 SIM_DESC sd
= CPU_STATE (current_cpu
);
75 host_callback
*cb
= STATE_CALLBACK (sd
);
77 /* Check for divide by zero. */
78 if (GET_H_GR (r1
) == 0)
80 if (STATE_ENVIRONMENT (sd
) != OPERATING_ENVIRONMENT
)
81 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGFPE
);
84 /* Save PC in exception address register. */
86 /* Save and clear interrupt enable. */
87 SET_H_CSR (LM32_CSR_IE
, (GET_H_CSR (LM32_CSR_IE
) & 1) << 1);
88 /* Branch to divide by zero exception handler. */
89 return GET_H_CSR (LM32_CSR_EBA
) + LM32_EID_DIVIDE_BY_ZERO
* 32;
94 SET_H_GR (r2
, (USI
) GET_H_GR (r0
) % (USI
) GET_H_GR (r1
));
99 /* Handle break instructions. */
102 lm32bf_break_insn (SIM_CPU
* current_cpu
, IADDR pc
)
104 SIM_DESC sd
= CPU_STATE (current_cpu
);
105 host_callback
*cb
= STATE_CALLBACK (sd
);
107 if (STATE_ENVIRONMENT (sd
) != OPERATING_ENVIRONMENT
)
109 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
114 /* Save PC in breakpoint address register. */
116 /* Save and clear interrupt enable. */
117 SET_H_CSR (LM32_CSR_IE
, (GET_H_CSR (LM32_CSR_IE
) & 1) << 2);
118 /* Branch to breakpoint exception handler. */
119 return GET_H_CSR (LM32_CSR_DEBA
) + LM32_EID_BREAKPOINT
* 32;
123 /* Handle scall instructions. */
126 lm32bf_scall_insn (SIM_CPU
* current_cpu
, IADDR pc
)
128 SIM_DESC sd
= CPU_STATE (current_cpu
);
129 host_callback
*cb
= STATE_CALLBACK (sd
);
131 if ((STATE_ENVIRONMENT (sd
) != OPERATING_ENVIRONMENT
)
132 || (GET_H_GR (8) == TARGET_SYS_exit
))
134 /* Delegate system call to host O/S. */
136 CB_SYSCALL_INIT (&s
);
138 s
.p2
= (PTR
) current_cpu
;
139 s
.read_mem
= sim_syscall_read_mem
;
140 s
.write_mem
= sim_syscall_write_mem
;
141 /* Extract parameters. */
142 s
.func
= GET_H_GR (8);
143 s
.arg1
= GET_H_GR (1);
144 s
.arg2
= GET_H_GR (2);
145 s
.arg3
= GET_H_GR (3);
146 /* Halt the simulator if the requested system call is _exit. */
147 if (s
.func
== TARGET_SYS_exit
)
148 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_exited
, s
.arg1
);
149 /* Perform the system call. */
151 /* Store the return value in the CPU's registers. */
152 SET_H_GR (1, s
.result
);
153 SET_H_GR (2, s
.result2
);
154 SET_H_GR (3, s
.errcode
);
155 /* Skip over scall instruction. */
160 /* Save PC in exception address register. */
162 /* Save and clear interrupt enable */
163 SET_H_CSR (LM32_CSR_IE
, (GET_H_CSR (LM32_CSR_IE
) & 1) << 1);
164 /* Branch to system call exception handler. */
165 return GET_H_CSR (LM32_CSR_EBA
) + LM32_EID_SYSTEM_CALL
* 32;
169 /* Handle b instructions. */
172 lm32bf_b_insn (SIM_CPU
* current_cpu
, USI r0
, USI f_r0
)
174 SIM_DESC sd
= CPU_STATE (current_cpu
);
175 host_callback
*cb
= STATE_CALLBACK (sd
);
177 /* Restore interrupt enable. */
179 SET_H_CSR (LM32_CSR_IE
, (GET_H_CSR (LM32_CSR_IE
) & 2) >> 1);
181 SET_H_CSR (LM32_CSR_IE
, (GET_H_CSR (LM32_CSR_IE
) & 4) >> 2);
185 /* Handle wcsr instructions. */
188 lm32bf_wcsr_insn (SIM_CPU
* current_cpu
, USI f_csr
, USI r1
)
190 SIM_DESC sd
= CPU_STATE (current_cpu
);
191 host_callback
*cb
= STATE_CALLBACK (sd
);
193 /* Writing a 1 to IP CSR clears a bit, writing 0 has no effect. */
194 if (f_csr
== LM32_CSR_IP
)
195 SET_H_CSR (f_csr
, GET_H_CSR (f_csr
) & ~r1
);
197 SET_H_CSR (f_csr
, r1
);
200 /* Handle signals. */
203 lm32_core_signal (SIM_DESC sd
,
209 transfer_type transfer
, sim_core_signals sig
)
211 const char *copy
= (transfer
== read_transfer
? "read" : "write");
212 address_word ip
= CIA_ADDR (cia
);
213 SIM_CPU
*current_cpu
= cpu
;
217 case sim_core_unmapped_signal
:
219 "core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
220 nr_bytes
, copy
, (unsigned long) addr
,
223 /* Save and clear interrupt enable. */
224 SET_H_CSR (LM32_CSR_IE
, (GET_H_CSR (LM32_CSR_IE
) & 1) << 1);
225 CPU_PC_SET (cpu
, GET_H_CSR (LM32_CSR_EBA
) + LM32_EID_DATA_BUS_ERROR
* 32);
226 sim_engine_halt (sd
, cpu
, NULL
, LM32_EID_DATA_BUS_ERROR
* 32,
227 sim_stopped
, SIM_SIGSEGV
);
229 case sim_core_unaligned_signal
:
231 "core: %d byte misaligned %s to address 0x%lx at 0x%lx\n",
232 nr_bytes
, copy
, (unsigned long) addr
,
235 /* Save and clear interrupt enable. */
236 SET_H_CSR (LM32_CSR_IE
, (GET_H_CSR (LM32_CSR_IE
) & 1) << 1);
237 CPU_PC_SET (cpu
, GET_H_CSR (LM32_CSR_EBA
) + LM32_EID_DATA_BUS_ERROR
* 32);
238 sim_engine_halt (sd
, cpu
, NULL
, LM32_EID_DATA_BUS_ERROR
* 32,
239 sim_stopped
, SIM_SIGBUS
);
242 sim_engine_abort (sd
, cpu
, cia
,
243 "sim_core_signal - internal error - bad switch");